2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
76 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
78 struct ath_atx_tid *tid;
79 tid = ATH_AN_2_TID(an, tidno);
81 if (tid->state & AGGR_ADDBA_COMPLETE ||
82 tid->state & AGGR_ADDBA_PROGRESS)
88 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
90 struct ath_atx_ac *ac = tid->ac;
99 list_add_tail(&tid->list, &ac->tid_q);
105 list_add_tail(&ac->list, &txq->axq_acq);
108 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
110 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
112 spin_lock_bh(&txq->axq_lock);
114 spin_unlock_bh(&txq->axq_lock);
117 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
119 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
121 ASSERT(tid->paused > 0);
122 spin_lock_bh(&txq->axq_lock);
129 if (list_empty(&tid->buf_q))
132 ath_tx_queue_tid(txq, tid);
133 ath_txq_schedule(sc, txq);
135 spin_unlock_bh(&txq->axq_lock);
138 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
140 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
142 struct list_head bf_head;
143 INIT_LIST_HEAD(&bf_head);
145 ASSERT(tid->paused > 0);
146 spin_lock_bh(&txq->axq_lock);
150 if (tid->paused > 0) {
151 spin_unlock_bh(&txq->axq_lock);
155 while (!list_empty(&tid->buf_q)) {
156 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
157 ASSERT(!bf_isretried(bf));
158 list_move_tail(&bf->list, &bf_head);
159 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
162 spin_unlock_bh(&txq->axq_lock);
165 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
170 index = ATH_BA_INDEX(tid->seq_start, seqno);
171 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
173 tid->tx_buf[cindex] = NULL;
175 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
176 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
177 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
181 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
186 if (bf_isretried(bf))
189 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
190 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
192 ASSERT(tid->tx_buf[cindex] == NULL);
193 tid->tx_buf[cindex] = bf;
195 if (index >= ((tid->baw_tail - tid->baw_head) &
196 (ATH_TID_MAX_BUFS - 1))) {
197 tid->baw_tail = cindex;
198 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
203 * TODO: For frame(s) that are in the retry state, we will reuse the
204 * sequence number(s) without setting the retry bit. The
205 * alternative is to give up on these and BAR the receiver's window
208 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
209 struct ath_atx_tid *tid)
213 struct list_head bf_head;
214 INIT_LIST_HEAD(&bf_head);
217 if (list_empty(&tid->buf_q))
220 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
221 list_move_tail(&bf->list, &bf_head);
223 if (bf_isretried(bf))
224 ath_tx_update_baw(sc, tid, bf->bf_seqno);
226 spin_unlock(&txq->axq_lock);
227 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
228 spin_lock(&txq->axq_lock);
231 tid->seq_next = tid->seq_start;
232 tid->baw_tail = tid->baw_head;
235 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
238 struct ieee80211_hdr *hdr;
240 bf->bf_state.bf_type |= BUF_RETRY;
244 hdr = (struct ieee80211_hdr *)skb->data;
245 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
248 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
252 spin_lock_bh(&sc->tx.txbuflock);
253 ASSERT(!list_empty((&sc->tx.txbuf)));
254 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
255 list_del(&tbf->list);
256 spin_unlock_bh(&sc->tx.txbuflock);
258 ATH_TXBUF_RESET(tbf);
260 tbf->bf_mpdu = bf->bf_mpdu;
261 tbf->bf_buf_addr = bf->bf_buf_addr;
262 *(tbf->bf_desc) = *(bf->bf_desc);
263 tbf->bf_state = bf->bf_state;
264 tbf->bf_dmacontext = bf->bf_dmacontext;
269 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
270 struct ath_buf *bf, struct list_head *bf_q,
273 struct ath_node *an = NULL;
275 struct ieee80211_sta *sta;
276 struct ieee80211_hdr *hdr;
277 struct ath_atx_tid *tid = NULL;
278 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
279 struct ath_desc *ds = bf_last->bf_desc;
280 struct list_head bf_head, bf_pending;
281 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
282 u32 ba[WME_BA_BMP_SIZE >> 5];
283 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
284 bool rc_update = true;
287 hdr = (struct ieee80211_hdr *)skb->data;
291 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
297 an = (struct ath_node *)sta->drv_priv;
298 tid = ATH_AN_2_TID(an, bf->bf_tidno);
300 isaggr = bf_isaggr(bf);
301 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
303 if (isaggr && txok) {
304 if (ATH_DS_TX_BA(ds)) {
305 seq_st = ATH_DS_BA_SEQ(ds);
306 memcpy(ba, ATH_DS_BA_BITMAP(ds),
307 WME_BA_BMP_SIZE >> 3);
310 * AR5416 can become deaf/mute when BA
311 * issue happens. Chip needs to be reset.
312 * But AP code may have sychronization issues
313 * when perform internal reset in this routine.
314 * Only enable reset in STA mode for now.
316 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
321 INIT_LIST_HEAD(&bf_pending);
322 INIT_LIST_HEAD(&bf_head);
324 nbad = ath_tx_num_badfrms(sc, bf, txok);
326 txfail = txpending = 0;
327 bf_next = bf->bf_next;
329 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
330 /* transmit completion, subframe is
331 * acked by block ack */
333 } else if (!isaggr && txok) {
334 /* transmit completion */
337 if (!(tid->state & AGGR_CLEANUP) &&
338 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
339 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
340 ath_tx_set_retry(sc, bf);
343 bf->bf_state.bf_type |= BUF_XRETRY;
350 * cleanup in progress, just fail
351 * the un-acked sub-frames
357 if (bf_next == NULL) {
358 INIT_LIST_HEAD(&bf_head);
360 ASSERT(!list_empty(bf_q));
361 list_move_tail(&bf->list, &bf_head);
366 * complete the acked-ones/xretried ones; update
369 spin_lock_bh(&txq->axq_lock);
370 ath_tx_update_baw(sc, tid, bf->bf_seqno);
371 spin_unlock_bh(&txq->axq_lock);
373 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
374 ath_tx_rc_status(bf, ds, nbad, txok, true);
377 ath_tx_rc_status(bf, ds, nbad, txok, false);
380 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
382 /* retry the un-acked ones */
383 if (bf->bf_next == NULL && bf_last->bf_stale) {
386 tbf = ath_clone_txbuf(sc, bf_last);
387 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
388 list_add_tail(&tbf->list, &bf_head);
391 * Clear descriptor status words for
394 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
398 * Put this buffer to the temporary pending
399 * queue to retain ordering
401 list_splice_tail_init(&bf_head, &bf_pending);
407 if (tid->state & AGGR_CLEANUP) {
408 if (tid->baw_head == tid->baw_tail) {
409 tid->state &= ~AGGR_ADDBA_COMPLETE;
410 tid->addba_exchangeattempts = 0;
411 tid->state &= ~AGGR_CLEANUP;
413 /* send buffered frames as singles */
414 ath_tx_flush_tid(sc, tid);
420 /* prepend un-acked frames to the beginning of the pending frame queue */
421 if (!list_empty(&bf_pending)) {
422 spin_lock_bh(&txq->axq_lock);
423 list_splice(&bf_pending, &tid->buf_q);
424 ath_tx_queue_tid(txq, tid);
425 spin_unlock_bh(&txq->axq_lock);
431 ath_reset(sc, false);
434 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
435 struct ath_atx_tid *tid)
437 const struct ath_rate_table *rate_table = sc->cur_rate_table;
439 struct ieee80211_tx_info *tx_info;
440 struct ieee80211_tx_rate *rates;
441 struct ath_tx_info_priv *tx_info_priv;
442 u32 max_4ms_framelen, frmlen;
443 u16 aggr_limit, legacy = 0, maxampdu;
447 tx_info = IEEE80211_SKB_CB(skb);
448 rates = tx_info->control.rates;
449 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
452 * Find the lowest frame length among the rate series that will have a
453 * 4ms transmit duration.
454 * TODO - TXOP limit needs to be considered.
456 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
458 for (i = 0; i < 4; i++) {
459 if (rates[i].count) {
460 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
465 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
466 max_4ms_framelen = min(max_4ms_framelen, frmlen);
471 * limit aggregate size by the minimum rate if rate selected is
472 * not a probe rate, if rate selected is a probe rate then
473 * avoid aggregation of this packet.
475 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
478 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
481 * h/w can accept aggregates upto 16 bit lengths (65535).
482 * The IE, however can hold upto 65536, which shows up here
483 * as zero. Ignore 65536 since we are constrained by hw.
485 maxampdu = tid->an->maxampdu;
487 aggr_limit = min(aggr_limit, maxampdu);
493 * Returns the number of delimiters to be added to
494 * meet the minimum required mpdudensity.
495 * caller should make sure that the rate is HT rate .
497 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
498 struct ath_buf *bf, u16 frmlen)
500 const struct ath_rate_table *rt = sc->cur_rate_table;
501 struct sk_buff *skb = bf->bf_mpdu;
502 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
503 u32 nsymbits, nsymbols, mpdudensity;
506 int width, half_gi, ndelim, mindelim;
508 /* Select standard number of delimiters based on frame length alone */
509 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
512 * If encryption enabled, hardware requires some more padding between
514 * TODO - this could be improved to be dependent on the rate.
515 * The hardware can keep up at lower rates, but not higher rates
517 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
518 ndelim += ATH_AGGR_ENCRYPTDELIM;
521 * Convert desired mpdu density from microeconds to bytes based
522 * on highest rate in rate series (i.e. first rate) to determine
523 * required minimum length for subframe. Take into account
524 * whether high rate is 20 or 40Mhz and half or full GI.
526 mpdudensity = tid->an->mpdudensity;
529 * If there is no mpdu density restriction, no further calculation
532 if (mpdudensity == 0)
535 rix = tx_info->control.rates[0].idx;
536 flags = tx_info->control.rates[0].flags;
537 rc = rt->info[rix].ratecode;
538 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
539 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
542 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
544 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
549 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
550 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
552 if (frmlen < minlen) {
553 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
554 ndelim = max(mindelim, ndelim);
560 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
561 struct ath_atx_tid *tid,
562 struct list_head *bf_q)
564 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
565 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
566 int rl = 0, nframes = 0, ndelim, prev_al = 0;
567 u16 aggr_limit = 0, al = 0, bpad = 0,
568 al_delta, h_baw = tid->baw_size / 2;
569 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
571 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
574 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
576 /* do not step over block-ack window */
577 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
578 status = ATH_AGGR_BAW_CLOSED;
583 aggr_limit = ath_lookup_rate(sc, bf, tid);
587 /* do not exceed aggregation limit */
588 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
591 (aggr_limit < (al + bpad + al_delta + prev_al))) {
592 status = ATH_AGGR_LIMITED;
596 /* do not exceed subframe limit */
597 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
598 status = ATH_AGGR_LIMITED;
603 /* add padding for previous frame to aggregation length */
604 al += bpad + al_delta;
607 * Get the delimiters needed to meet the MPDU
608 * density for this node.
610 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
611 bpad = PADBYTES(al_delta) + (ndelim << 2);
614 bf->bf_desc->ds_link = 0;
616 /* link buffers of this frame to the aggregate */
617 ath_tx_addto_baw(sc, tid, bf);
618 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
619 list_move_tail(&bf->list, bf_q);
621 bf_prev->bf_next = bf;
622 bf_prev->bf_desc->ds_link = bf->bf_daddr;
625 } while (!list_empty(&tid->buf_q));
627 bf_first->bf_al = al;
628 bf_first->bf_nframes = nframes;
634 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
635 struct ath_atx_tid *tid)
638 enum ATH_AGGR_STATUS status;
639 struct list_head bf_q;
642 if (list_empty(&tid->buf_q))
645 INIT_LIST_HEAD(&bf_q);
647 status = ath_tx_form_aggr(sc, tid, &bf_q);
650 * no frames picked up to be aggregated;
651 * block-ack window is not open.
653 if (list_empty(&bf_q))
656 bf = list_first_entry(&bf_q, struct ath_buf, list);
657 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
659 /* if only one frame, send as non-aggregate */
660 if (bf->bf_nframes == 1) {
661 bf->bf_state.bf_type &= ~BUF_AGGR;
662 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
663 ath_buf_set_rate(sc, bf);
664 ath_tx_txqaddbuf(sc, txq, &bf_q);
668 /* setup first desc of aggregate */
669 bf->bf_state.bf_type |= BUF_AGGR;
670 ath_buf_set_rate(sc, bf);
671 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
673 /* anchor last desc of aggregate */
674 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
676 txq->axq_aggr_depth++;
677 ath_tx_txqaddbuf(sc, txq, &bf_q);
679 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
680 status != ATH_AGGR_BAW_CLOSED);
683 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
686 struct ath_atx_tid *txtid;
689 an = (struct ath_node *)sta->drv_priv;
691 if (sc->sc_flags & SC_OP_TXAGGR) {
692 txtid = ATH_AN_2_TID(an, tid);
693 txtid->state |= AGGR_ADDBA_PROGRESS;
694 ath_tx_pause_tid(sc, txtid);
695 *ssn = txtid->seq_start;
701 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
703 struct ath_node *an = (struct ath_node *)sta->drv_priv;
704 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
705 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
707 struct list_head bf_head;
708 INIT_LIST_HEAD(&bf_head);
710 if (txtid->state & AGGR_CLEANUP)
713 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
714 txtid->addba_exchangeattempts = 0;
718 ath_tx_pause_tid(sc, txtid);
720 /* drop all software retried frames and mark this TID */
721 spin_lock_bh(&txq->axq_lock);
722 while (!list_empty(&txtid->buf_q)) {
723 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
724 if (!bf_isretried(bf)) {
726 * NB: it's based on the assumption that
727 * software retried frame will always stay
728 * at the head of software queue.
732 list_move_tail(&bf->list, &bf_head);
733 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
734 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
736 spin_unlock_bh(&txq->axq_lock);
738 if (txtid->baw_head != txtid->baw_tail) {
739 txtid->state |= AGGR_CLEANUP;
741 txtid->state &= ~AGGR_ADDBA_COMPLETE;
742 txtid->addba_exchangeattempts = 0;
743 ath_tx_flush_tid(sc, txtid);
749 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
751 struct ath_atx_tid *txtid;
754 an = (struct ath_node *)sta->drv_priv;
756 if (sc->sc_flags & SC_OP_TXAGGR) {
757 txtid = ATH_AN_2_TID(an, tid);
759 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
760 txtid->state |= AGGR_ADDBA_COMPLETE;
761 txtid->state &= ~AGGR_ADDBA_PROGRESS;
762 ath_tx_resume_tid(sc, txtid);
766 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
768 struct ath_atx_tid *txtid;
770 if (!(sc->sc_flags & SC_OP_TXAGGR))
773 txtid = ATH_AN_2_TID(an, tidno);
775 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
776 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
777 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
778 txtid->addba_exchangeattempts++;
786 /********************/
787 /* Queue Management */
788 /********************/
790 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
793 struct ath_atx_ac *ac, *ac_tmp;
794 struct ath_atx_tid *tid, *tid_tmp;
796 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
799 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
800 list_del(&tid->list);
802 ath_tid_drain(sc, txq, tid);
807 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
809 struct ath_hw *ah = sc->sc_ah;
810 struct ath9k_tx_queue_info qi;
813 memset(&qi, 0, sizeof(qi));
814 qi.tqi_subtype = subtype;
815 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
816 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
817 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
818 qi.tqi_physCompBuf = 0;
821 * Enable interrupts only for EOL and DESC conditions.
822 * We mark tx descriptors to receive a DESC interrupt
823 * when a tx queue gets deep; otherwise waiting for the
824 * EOL to reap descriptors. Note that this is done to
825 * reduce interrupt load and this only defers reaping
826 * descriptors, never transmitting frames. Aside from
827 * reducing interrupts this also permits more concurrency.
828 * The only potential downside is if the tx queue backs
829 * up in which case the top half of the kernel may backup
830 * due to a lack of tx descriptors.
832 * The UAPSD queue is an exception, since we take a desc-
833 * based intr on the EOSP frames.
835 if (qtype == ATH9K_TX_QUEUE_UAPSD)
836 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
838 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
839 TXQ_FLAG_TXDESCINT_ENABLE;
840 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
843 * NB: don't print a message, this happens
844 * normally on parts with too few tx queues
848 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
849 DPRINTF(sc, ATH_DBG_FATAL,
850 "qnum %u out of range, max %u!\n",
851 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
852 ath9k_hw_releasetxqueue(ah, qnum);
855 if (!ATH_TXQ_SETUP(sc, qnum)) {
856 struct ath_txq *txq = &sc->tx.txq[qnum];
858 txq->axq_qnum = qnum;
859 txq->axq_link = NULL;
860 INIT_LIST_HEAD(&txq->axq_q);
861 INIT_LIST_HEAD(&txq->axq_acq);
862 spin_lock_init(&txq->axq_lock);
864 txq->axq_aggr_depth = 0;
865 txq->axq_totalqueued = 0;
866 txq->axq_linkbuf = NULL;
867 sc->tx.txqsetup |= 1<<qnum;
869 return &sc->tx.txq[qnum];
872 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
877 case ATH9K_TX_QUEUE_DATA:
878 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
879 DPRINTF(sc, ATH_DBG_FATAL,
880 "HAL AC %u out of range, max %zu!\n",
881 haltype, ARRAY_SIZE(sc->tx.hwq_map));
884 qnum = sc->tx.hwq_map[haltype];
886 case ATH9K_TX_QUEUE_BEACON:
887 qnum = sc->beacon.beaconq;
889 case ATH9K_TX_QUEUE_CAB:
890 qnum = sc->beacon.cabq->axq_qnum;
898 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
900 struct ath_txq *txq = NULL;
903 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
904 txq = &sc->tx.txq[qnum];
906 spin_lock_bh(&txq->axq_lock);
908 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
909 DPRINTF(sc, ATH_DBG_XMIT,
910 "TX queue: %d is full, depth: %d\n",
911 qnum, txq->axq_depth);
912 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
914 spin_unlock_bh(&txq->axq_lock);
918 spin_unlock_bh(&txq->axq_lock);
923 int ath_txq_update(struct ath_softc *sc, int qnum,
924 struct ath9k_tx_queue_info *qinfo)
926 struct ath_hw *ah = sc->sc_ah;
928 struct ath9k_tx_queue_info qi;
930 if (qnum == sc->beacon.beaconq) {
932 * XXX: for beacon queue, we just save the parameter.
933 * It will be picked up by ath_beaconq_config when
936 sc->beacon.beacon_qi = *qinfo;
940 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
942 ath9k_hw_get_txq_props(ah, qnum, &qi);
943 qi.tqi_aifs = qinfo->tqi_aifs;
944 qi.tqi_cwmin = qinfo->tqi_cwmin;
945 qi.tqi_cwmax = qinfo->tqi_cwmax;
946 qi.tqi_burstTime = qinfo->tqi_burstTime;
947 qi.tqi_readyTime = qinfo->tqi_readyTime;
949 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
950 DPRINTF(sc, ATH_DBG_FATAL,
951 "Unable to update hardware queue %u!\n", qnum);
954 ath9k_hw_resettxqueue(ah, qnum);
960 int ath_cabq_update(struct ath_softc *sc)
962 struct ath9k_tx_queue_info qi;
963 int qnum = sc->beacon.cabq->axq_qnum;
965 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
967 * Ensure the readytime % is within the bounds.
969 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
970 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
971 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
972 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
974 qi.tqi_readyTime = (sc->beacon_interval *
975 sc->config.cabqReadytime) / 100;
976 ath_txq_update(sc, qnum, &qi);
982 * Drain a given TX queue (could be Beacon or Data)
984 * This assumes output has been stopped and
985 * we do not need to block ath_tx_tasklet.
987 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
989 struct ath_buf *bf, *lastbf;
990 struct list_head bf_head;
992 INIT_LIST_HEAD(&bf_head);
995 spin_lock_bh(&txq->axq_lock);
997 if (list_empty(&txq->axq_q)) {
998 txq->axq_link = NULL;
999 txq->axq_linkbuf = NULL;
1000 spin_unlock_bh(&txq->axq_lock);
1004 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1007 list_del(&bf->list);
1008 spin_unlock_bh(&txq->axq_lock);
1010 spin_lock_bh(&sc->tx.txbuflock);
1011 list_add_tail(&bf->list, &sc->tx.txbuf);
1012 spin_unlock_bh(&sc->tx.txbuflock);
1016 lastbf = bf->bf_lastbf;
1018 lastbf->bf_desc->ds_txstat.ts_flags =
1019 ATH9K_TX_SW_ABORTED;
1021 /* remove ath_buf's of the same mpdu from txq */
1022 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1025 spin_unlock_bh(&txq->axq_lock);
1028 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1030 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1033 /* flush any pending frames if aggregation is enabled */
1034 if (sc->sc_flags & SC_OP_TXAGGR) {
1036 spin_lock_bh(&txq->axq_lock);
1037 ath_txq_drain_pending_buffers(sc, txq);
1038 spin_unlock_bh(&txq->axq_lock);
1043 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1045 struct ath_hw *ah = sc->sc_ah;
1046 struct ath_txq *txq;
1049 if (sc->sc_flags & SC_OP_INVALID)
1052 /* Stop beacon queue */
1053 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1055 /* Stop data queues */
1056 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1057 if (ATH_TXQ_SETUP(sc, i)) {
1058 txq = &sc->tx.txq[i];
1059 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1060 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1067 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1069 spin_lock_bh(&sc->sc_resetlock);
1070 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1072 DPRINTF(sc, ATH_DBG_FATAL,
1073 "Unable to reset hardware; reset status %d\n",
1075 spin_unlock_bh(&sc->sc_resetlock);
1078 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1079 if (ATH_TXQ_SETUP(sc, i))
1080 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1084 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1086 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1087 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1090 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1092 struct ath_atx_ac *ac;
1093 struct ath_atx_tid *tid;
1095 if (list_empty(&txq->axq_acq))
1098 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1099 list_del(&ac->list);
1103 if (list_empty(&ac->tid_q))
1106 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1107 list_del(&tid->list);
1113 if ((txq->axq_depth % 2) == 0)
1114 ath_tx_sched_aggr(sc, txq, tid);
1117 * add tid to round-robin queue if more frames
1118 * are pending for the tid
1120 if (!list_empty(&tid->buf_q))
1121 ath_tx_queue_tid(txq, tid);
1124 } while (!list_empty(&ac->tid_q));
1126 if (!list_empty(&ac->tid_q)) {
1129 list_add_tail(&ac->list, &txq->axq_acq);
1134 int ath_tx_setup(struct ath_softc *sc, int haltype)
1136 struct ath_txq *txq;
1138 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1139 DPRINTF(sc, ATH_DBG_FATAL,
1140 "HAL AC %u out of range, max %zu!\n",
1141 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1144 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1146 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1157 * Insert a chain of ath_buf (descriptors) on a txq and
1158 * assume the descriptors are already chained together by caller.
1160 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1161 struct list_head *head)
1163 struct ath_hw *ah = sc->sc_ah;
1167 * Insert the frame on the outbound list and
1168 * pass it on to the hardware.
1171 if (list_empty(head))
1174 bf = list_first_entry(head, struct ath_buf, list);
1176 list_splice_tail_init(head, &txq->axq_q);
1178 txq->axq_totalqueued++;
1179 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1181 DPRINTF(sc, ATH_DBG_QUEUE,
1182 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1184 if (txq->axq_link == NULL) {
1185 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1186 DPRINTF(sc, ATH_DBG_XMIT,
1187 "TXDP[%u] = %llx (%p)\n",
1188 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1190 *txq->axq_link = bf->bf_daddr;
1191 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1192 txq->axq_qnum, txq->axq_link,
1193 ito64(bf->bf_daddr), bf->bf_desc);
1195 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1196 ath9k_hw_txstart(ah, txq->axq_qnum);
1199 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1201 struct ath_buf *bf = NULL;
1203 spin_lock_bh(&sc->tx.txbuflock);
1205 if (unlikely(list_empty(&sc->tx.txbuf))) {
1206 spin_unlock_bh(&sc->tx.txbuflock);
1210 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1211 list_del(&bf->list);
1213 spin_unlock_bh(&sc->tx.txbuflock);
1218 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1219 struct list_head *bf_head,
1220 struct ath_tx_control *txctl)
1224 bf = list_first_entry(bf_head, struct ath_buf, list);
1225 bf->bf_state.bf_type |= BUF_AMPDU;
1228 * Do not queue to h/w when any of the following conditions is true:
1229 * - there are pending frames in software queue
1230 * - the TID is currently paused for ADDBA/BAR request
1231 * - seqno is not within block-ack window
1232 * - h/w queue depth exceeds low water mark
1234 if (!list_empty(&tid->buf_q) || tid->paused ||
1235 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1236 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1238 * Add this frame to software queue for scheduling later
1241 list_move_tail(&bf->list, &tid->buf_q);
1242 ath_tx_queue_tid(txctl->txq, tid);
1246 /* Add sub-frame to BAW */
1247 ath_tx_addto_baw(sc, tid, bf);
1249 /* Queue to h/w without aggregation */
1252 ath_buf_set_rate(sc, bf);
1253 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1256 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1257 struct ath_atx_tid *tid,
1258 struct list_head *bf_head)
1262 bf = list_first_entry(bf_head, struct ath_buf, list);
1263 bf->bf_state.bf_type &= ~BUF_AMPDU;
1265 /* update starting sequence number for subsequent ADDBA request */
1266 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1270 ath_buf_set_rate(sc, bf);
1271 ath_tx_txqaddbuf(sc, txq, bf_head);
1274 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1275 struct list_head *bf_head)
1279 bf = list_first_entry(bf_head, struct ath_buf, list);
1283 ath_buf_set_rate(sc, bf);
1284 ath_tx_txqaddbuf(sc, txq, bf_head);
1287 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1289 struct ieee80211_hdr *hdr;
1290 enum ath9k_pkt_type htype;
1293 hdr = (struct ieee80211_hdr *)skb->data;
1294 fc = hdr->frame_control;
1296 if (ieee80211_is_beacon(fc))
1297 htype = ATH9K_PKT_TYPE_BEACON;
1298 else if (ieee80211_is_probe_resp(fc))
1299 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1300 else if (ieee80211_is_atim(fc))
1301 htype = ATH9K_PKT_TYPE_ATIM;
1302 else if (ieee80211_is_pspoll(fc))
1303 htype = ATH9K_PKT_TYPE_PSPOLL;
1305 htype = ATH9K_PKT_TYPE_NORMAL;
1310 static bool is_pae(struct sk_buff *skb)
1312 struct ieee80211_hdr *hdr;
1315 hdr = (struct ieee80211_hdr *)skb->data;
1316 fc = hdr->frame_control;
1318 if (ieee80211_is_data(fc)) {
1319 if (ieee80211_is_nullfunc(fc) ||
1320 /* Port Access Entity (IEEE 802.1X) */
1321 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1329 static int get_hw_crypto_keytype(struct sk_buff *skb)
1331 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1333 if (tx_info->control.hw_key) {
1334 if (tx_info->control.hw_key->alg == ALG_WEP)
1335 return ATH9K_KEY_TYPE_WEP;
1336 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1337 return ATH9K_KEY_TYPE_TKIP;
1338 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1339 return ATH9K_KEY_TYPE_AES;
1342 return ATH9K_KEY_TYPE_CLEAR;
1345 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1348 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1349 struct ieee80211_hdr *hdr;
1350 struct ath_node *an;
1351 struct ath_atx_tid *tid;
1355 if (!tx_info->control.sta)
1358 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1359 hdr = (struct ieee80211_hdr *)skb->data;
1360 fc = hdr->frame_control;
1362 if (ieee80211_is_data_qos(fc)) {
1363 qc = ieee80211_get_qos_ctl(hdr);
1364 bf->bf_tidno = qc[0] & 0xf;
1368 * For HT capable stations, we save tidno for later use.
1369 * We also override seqno set by upper layer with the one
1370 * in tx aggregation state.
1372 * If fragmentation is on, the sequence number is
1373 * not overridden, since it has been
1374 * incremented by the fragmentation routine.
1376 * FIXME: check if the fragmentation threshold exceeds
1379 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1380 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1381 IEEE80211_SEQ_SEQ_SHIFT);
1382 bf->bf_seqno = tid->seq_next;
1383 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1386 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1387 struct ath_txq *txq)
1389 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1392 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1393 flags |= ATH9K_TXDESC_INTREQ;
1395 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1396 flags |= ATH9K_TXDESC_NOACK;
1403 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1404 * width - 0 for 20 MHz, 1 for 40 MHz
1405 * half_gi - to use 4us v/s 3.6 us for symbol time
1407 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1408 int width, int half_gi, bool shortPreamble)
1410 const struct ath_rate_table *rate_table = sc->cur_rate_table;
1411 u32 nbits, nsymbits, duration, nsymbols;
1413 int streams, pktlen;
1415 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1416 rc = rate_table->info[rix].ratecode;
1418 /* for legacy rates, use old function to compute packet duration */
1419 if (!IS_HT_RATE(rc))
1420 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1421 rix, shortPreamble);
1423 /* find number of symbols: PLCP + data */
1424 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1425 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1426 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1429 duration = SYMBOL_TIME(nsymbols);
1431 duration = SYMBOL_TIME_HALFGI(nsymbols);
1433 /* addup duration for legacy/ht training and signal fields */
1434 streams = HT_RC_2_STREAMS(rc);
1435 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1440 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1442 const struct ath_rate_table *rt = sc->cur_rate_table;
1443 struct ath9k_11n_rate_series series[4];
1444 struct sk_buff *skb;
1445 struct ieee80211_tx_info *tx_info;
1446 struct ieee80211_tx_rate *rates;
1447 struct ieee80211_hdr *hdr;
1449 u8 rix = 0, ctsrate = 0;
1452 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1455 tx_info = IEEE80211_SKB_CB(skb);
1456 rates = tx_info->control.rates;
1457 hdr = (struct ieee80211_hdr *)skb->data;
1458 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1461 * We check if Short Preamble is needed for the CTS rate by
1462 * checking the BSS's global flag.
1463 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1465 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1466 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1467 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1469 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1472 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1473 * Check the first rate in the series to decide whether RTS/CTS
1474 * or CTS-to-self has to be used.
1476 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1477 flags = ATH9K_TXDESC_CTSENA;
1478 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1479 flags = ATH9K_TXDESC_RTSENA;
1481 /* FIXME: Handle aggregation protection */
1482 if (sc->config.ath_aggr_prot &&
1483 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1484 flags = ATH9K_TXDESC_RTSENA;
1487 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1488 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1489 flags &= ~(ATH9K_TXDESC_RTSENA);
1491 for (i = 0; i < 4; i++) {
1492 if (!rates[i].count || (rates[i].idx < 0))
1496 series[i].Tries = rates[i].count;
1497 series[i].ChSel = sc->tx_chainmask;
1499 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1500 series[i].Rate = rt->info[rix].ratecode |
1501 rt->info[rix].short_preamble;
1503 series[i].Rate = rt->info[rix].ratecode;
1505 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1506 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1507 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1508 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1509 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1510 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1512 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1513 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1514 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1515 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1518 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1519 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1520 bf->bf_lastbf->bf_desc,
1521 !is_pspoll, ctsrate,
1522 0, series, 4, flags);
1524 if (sc->config.ath_aggr_prot && flags)
1525 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1528 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1529 struct sk_buff *skb,
1530 struct ath_tx_control *txctl)
1532 struct ath_wiphy *aphy = hw->priv;
1533 struct ath_softc *sc = aphy->sc;
1534 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1535 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1536 struct ath_tx_info_priv *tx_info_priv;
1540 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1541 if (unlikely(!tx_info_priv))
1543 tx_info->rate_driver_data[0] = tx_info_priv;
1544 tx_info_priv->aphy = aphy;
1545 tx_info_priv->frame_type = txctl->frame_type;
1546 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1547 fc = hdr->frame_control;
1549 ATH_TXBUF_RESET(bf);
1551 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1553 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1554 bf->bf_state.bf_type |= BUF_HT;
1556 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1558 bf->bf_keytype = get_hw_crypto_keytype(skb);
1559 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1560 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1561 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1563 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1566 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1567 assign_aggr_tid_seqno(skb, bf);
1571 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1572 skb->len, DMA_TO_DEVICE);
1573 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1575 kfree(tx_info_priv);
1576 tx_info->rate_driver_data[0] = NULL;
1577 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n");
1581 bf->bf_buf_addr = bf->bf_dmacontext;
1585 /* FIXME: tx power */
1586 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1587 struct ath_tx_control *txctl)
1589 struct sk_buff *skb = bf->bf_mpdu;
1590 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1591 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1592 struct ath_node *an = NULL;
1593 struct list_head bf_head;
1594 struct ath_desc *ds;
1595 struct ath_atx_tid *tid;
1596 struct ath_hw *ah = sc->sc_ah;
1600 frm_type = get_hw_packet_type(skb);
1601 fc = hdr->frame_control;
1603 INIT_LIST_HEAD(&bf_head);
1604 list_add_tail(&bf->list, &bf_head);
1608 ds->ds_data = bf->bf_buf_addr;
1610 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1611 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1613 ath9k_hw_filltxdesc(ah, ds,
1614 skb->len, /* segment length */
1615 true, /* first segment */
1616 true, /* last segment */
1617 ds); /* first descriptor */
1619 spin_lock_bh(&txctl->txq->axq_lock);
1621 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1622 tx_info->control.sta) {
1623 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1624 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1626 if (!ieee80211_is_data_qos(fc)) {
1627 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1631 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1633 * Try aggregation if it's a unicast data frame
1634 * and the destination is HT capable.
1636 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1639 * Send this frame as regular when ADDBA
1640 * exchange is neither complete nor pending.
1642 ath_tx_send_ht_normal(sc, txctl->txq,
1646 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1650 spin_unlock_bh(&txctl->txq->axq_lock);
1653 /* Upon failure caller should free skb */
1654 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1655 struct ath_tx_control *txctl)
1657 struct ath_wiphy *aphy = hw->priv;
1658 struct ath_softc *sc = aphy->sc;
1662 bf = ath_tx_get_buffer(sc);
1664 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1668 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1670 struct ath_txq *txq = txctl->txq;
1672 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1674 /* upon ath_tx_processq() this TX queue will be resumed, we
1675 * guarantee this will happen by knowing beforehand that
1676 * we will at least have to run TX completionon one buffer
1678 spin_lock_bh(&txq->axq_lock);
1679 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1680 ieee80211_stop_queue(sc->hw,
1681 skb_get_queue_mapping(skb));
1684 spin_unlock_bh(&txq->axq_lock);
1686 spin_lock_bh(&sc->tx.txbuflock);
1687 list_add_tail(&bf->list, &sc->tx.txbuf);
1688 spin_unlock_bh(&sc->tx.txbuflock);
1693 ath_tx_start_dma(sc, bf, txctl);
1698 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1700 struct ath_wiphy *aphy = hw->priv;
1701 struct ath_softc *sc = aphy->sc;
1702 int hdrlen, padsize;
1703 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1704 struct ath_tx_control txctl;
1706 memset(&txctl, 0, sizeof(struct ath_tx_control));
1709 * As a temporary workaround, assign seq# here; this will likely need
1710 * to be cleaned up to work better with Beacon transmission and virtual
1713 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1714 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1715 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1716 sc->tx.seq_no += 0x10;
1717 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1718 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1721 /* Add the padding after the header if this is not already done */
1722 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1724 padsize = hdrlen % 4;
1725 if (skb_headroom(skb) < padsize) {
1726 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1727 dev_kfree_skb_any(skb);
1730 skb_push(skb, padsize);
1731 memmove(skb->data, skb->data + padsize, hdrlen);
1734 txctl.txq = sc->beacon.cabq;
1736 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1738 if (ath_tx_start(hw, skb, &txctl) != 0) {
1739 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1745 dev_kfree_skb_any(skb);
1752 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1755 struct ieee80211_hw *hw = sc->hw;
1756 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1757 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1758 int hdrlen, padsize;
1759 int frame_type = ATH9K_NOT_INTERNAL;
1761 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1764 hw = tx_info_priv->aphy->hw;
1765 frame_type = tx_info_priv->frame_type;
1768 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1769 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1770 kfree(tx_info_priv);
1771 tx_info->rate_driver_data[0] = NULL;
1774 if (tx_flags & ATH_TX_BAR)
1775 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1777 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1778 /* Frame was ACKed */
1779 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1782 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1783 padsize = hdrlen & 3;
1784 if (padsize && hdrlen >= 24) {
1786 * Remove MAC header padding before giving the frame back to
1789 memmove(skb->data + padsize, skb->data, hdrlen);
1790 skb_pull(skb, padsize);
1793 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1794 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1795 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having "
1796 "received TX status (0x%x)\n",
1797 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1798 SC_OP_WAIT_FOR_CAB |
1799 SC_OP_WAIT_FOR_PSPOLL_DATA |
1800 SC_OP_WAIT_FOR_TX_ACK));
1803 if (frame_type == ATH9K_NOT_INTERNAL)
1804 ieee80211_tx_status(hw, skb);
1806 ath9k_tx_status(hw, skb);
1809 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1810 struct list_head *bf_q,
1811 int txok, int sendbar)
1813 struct sk_buff *skb = bf->bf_mpdu;
1814 unsigned long flags;
1819 tx_flags = ATH_TX_BAR;
1822 tx_flags |= ATH_TX_ERROR;
1824 if (bf_isxretried(bf))
1825 tx_flags |= ATH_TX_XRETRY;
1828 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1829 ath_tx_complete(sc, skb, tx_flags);
1832 * Return the list of ath_buf of this mpdu to free queue
1834 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1835 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1836 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1839 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1842 struct ath_buf *bf_last = bf->bf_lastbf;
1843 struct ath_desc *ds = bf_last->bf_desc;
1845 u32 ba[WME_BA_BMP_SIZE >> 5];
1850 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1853 isaggr = bf_isaggr(bf);
1855 seq_st = ATH_DS_BA_SEQ(ds);
1856 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1860 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1861 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1870 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1871 int nbad, int txok, bool update_rc)
1873 struct sk_buff *skb = bf->bf_mpdu;
1874 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1875 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1876 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1877 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1881 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1883 tx_rateindex = ds->ds_txstat.ts_rateindex;
1884 WARN_ON(tx_rateindex >= hw->max_rates);
1886 tx_info_priv->update_rc = update_rc;
1887 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1888 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1890 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1891 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1892 if (ieee80211_is_data(hdr->frame_control)) {
1893 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1894 sizeof(tx_info_priv->tx));
1895 tx_info_priv->n_frames = bf->bf_nframes;
1896 tx_info_priv->n_bad_frames = nbad;
1900 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1901 tx_info->status.rates[i].count = 0;
1903 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1906 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1910 spin_lock_bh(&txq->axq_lock);
1912 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1913 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1915 ieee80211_wake_queue(sc->hw, qnum);
1919 spin_unlock_bh(&txq->axq_lock);
1922 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1924 struct ath_hw *ah = sc->sc_ah;
1925 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1926 struct list_head bf_head;
1927 struct ath_desc *ds;
1931 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1932 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1936 spin_lock_bh(&txq->axq_lock);
1937 if (list_empty(&txq->axq_q)) {
1938 txq->axq_link = NULL;
1939 txq->axq_linkbuf = NULL;
1940 spin_unlock_bh(&txq->axq_lock);
1943 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1946 * There is a race condition that a BH gets scheduled
1947 * after sw writes TxE and before hw re-load the last
1948 * descriptor to get the newly chained one.
1949 * Software must keep the last DONE descriptor as a
1950 * holding descriptor - software does so by marking
1951 * it with the STALE flag.
1956 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1957 txq->axq_link = NULL;
1958 txq->axq_linkbuf = NULL;
1959 spin_unlock_bh(&txq->axq_lock);
1962 * The holding descriptor is the last
1963 * descriptor in queue. It's safe to remove
1964 * the last holding descriptor in BH context.
1966 spin_lock_bh(&sc->tx.txbuflock);
1967 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1968 spin_unlock_bh(&sc->tx.txbuflock);
1972 bf = list_entry(bf_held->list.next,
1973 struct ath_buf, list);
1977 lastbf = bf->bf_lastbf;
1978 ds = lastbf->bf_desc;
1980 status = ath9k_hw_txprocdesc(ah, ds);
1981 if (status == -EINPROGRESS) {
1982 spin_unlock_bh(&txq->axq_lock);
1985 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1986 txq->axq_lastdsWithCTS = NULL;
1987 if (ds == txq->axq_gatingds)
1988 txq->axq_gatingds = NULL;
1991 * Remove ath_buf's of the same transmit unit from txq,
1992 * however leave the last descriptor back as the holding
1993 * descriptor for hw.
1995 lastbf->bf_stale = true;
1996 INIT_LIST_HEAD(&bf_head);
1997 if (!list_is_singular(&lastbf->list))
1998 list_cut_position(&bf_head,
1999 &txq->axq_q, lastbf->list.prev);
2003 txq->axq_aggr_depth--;
2005 txok = (ds->ds_txstat.ts_status == 0);
2006 spin_unlock_bh(&txq->axq_lock);
2009 spin_lock_bh(&sc->tx.txbuflock);
2010 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2011 spin_unlock_bh(&sc->tx.txbuflock);
2014 if (!bf_isampdu(bf)) {
2016 * This frame is sent out as a single frame.
2017 * Use hardware retry status for this frame.
2019 bf->bf_retries = ds->ds_txstat.ts_longretry;
2020 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2021 bf->bf_state.bf_type |= BUF_XRETRY;
2022 ath_tx_rc_status(bf, ds, 0, txok, true);
2026 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2028 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2030 ath_wake_mac80211_queue(sc, txq);
2032 spin_lock_bh(&txq->axq_lock);
2033 if (sc->sc_flags & SC_OP_TXAGGR)
2034 ath_txq_schedule(sc, txq);
2035 spin_unlock_bh(&txq->axq_lock);
2040 void ath_tx_tasklet(struct ath_softc *sc)
2043 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2045 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2047 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2048 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2049 ath_tx_processq(sc, &sc->tx.txq[i]);
2057 int ath_tx_init(struct ath_softc *sc, int nbufs)
2061 spin_lock_init(&sc->tx.txbuflock);
2063 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2066 DPRINTF(sc, ATH_DBG_FATAL,
2067 "Failed to allocate tx descriptors: %d\n", error);
2071 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2072 "beacon", ATH_BCBUF, 1);
2074 DPRINTF(sc, ATH_DBG_FATAL,
2075 "Failed to allocate beacon descriptors: %d\n", error);
2086 void ath_tx_cleanup(struct ath_softc *sc)
2088 if (sc->beacon.bdma.dd_desc_len != 0)
2089 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2091 if (sc->tx.txdma.dd_desc_len != 0)
2092 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2095 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2097 struct ath_atx_tid *tid;
2098 struct ath_atx_ac *ac;
2101 for (tidno = 0, tid = &an->tid[tidno];
2102 tidno < WME_NUM_TID;
2106 tid->seq_start = tid->seq_next = 0;
2107 tid->baw_size = WME_MAX_BA;
2108 tid->baw_head = tid->baw_tail = 0;
2110 tid->paused = false;
2111 tid->state &= ~AGGR_CLEANUP;
2112 INIT_LIST_HEAD(&tid->buf_q);
2113 acno = TID_TO_WME_AC(tidno);
2114 tid->ac = &an->ac[acno];
2115 tid->state &= ~AGGR_ADDBA_COMPLETE;
2116 tid->state &= ~AGGR_ADDBA_PROGRESS;
2117 tid->addba_exchangeattempts = 0;
2120 for (acno = 0, ac = &an->ac[acno];
2121 acno < WME_NUM_AC; acno++, ac++) {
2123 INIT_LIST_HEAD(&ac->tid_q);
2127 ac->qnum = ath_tx_get_qnum(sc,
2128 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2131 ac->qnum = ath_tx_get_qnum(sc,
2132 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2135 ac->qnum = ath_tx_get_qnum(sc,
2136 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2139 ac->qnum = ath_tx_get_qnum(sc,
2140 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2146 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2149 struct ath_atx_ac *ac, *ac_tmp;
2150 struct ath_atx_tid *tid, *tid_tmp;
2151 struct ath_txq *txq;
2153 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2154 if (ATH_TXQ_SETUP(sc, i)) {
2155 txq = &sc->tx.txq[i];
2157 spin_lock(&txq->axq_lock);
2159 list_for_each_entry_safe(ac,
2160 ac_tmp, &txq->axq_acq, list) {
2161 tid = list_first_entry(&ac->tid_q,
2162 struct ath_atx_tid, list);
2163 if (tid && tid->an != an)
2165 list_del(&ac->list);
2168 list_for_each_entry_safe(tid,
2169 tid_tmp, &ac->tid_q, list) {
2170 list_del(&tid->list);
2172 ath_tid_drain(sc, txq, tid);
2173 tid->state &= ~AGGR_ADDBA_COMPLETE;
2174 tid->addba_exchangeattempts = 0;
2175 tid->state &= ~AGGR_CLEANUP;
2179 spin_unlock(&txq->axq_lock);