drivers/net/wireless/ath/ath9k/recv.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18 #include "ar9003_mac.h"
  19
  20 #define SKB_CB_ATHBUF(__skb)    (*((struct ath_buf **)__skb->cb))
  21
  22 static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
  23                                                int mindelta, int main_rssi_avg,
  24                                                int alt_rssi_avg, int pkt_count)
  25 {
  26         return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  27                 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
  28                 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
  29 }
  30
  31 static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
  32 {
  33         return sc->ps_enabled &&
  34                (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
  35 }
  36
  37 static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc,
  38                                              struct ieee80211_hdr *hdr)
  39 {
  40         struct ieee80211_hw *hw = sc->pri_wiphy->hw;
  41         int i;
  42
  43         spin_lock_bh(&sc->wiphy_lock);
  44         for (i = 0; i < sc->num_sec_wiphy; i++) {
  45                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
  46                 if (aphy == NULL)
  47                         continue;
  48                 if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr)
  49                     == 0) {
  50                         hw = aphy->hw;
  51                         break;
  52                 }
  53         }
  54         spin_unlock_bh(&sc->wiphy_lock);
  55         return hw;
  56 }
  57
  58 /*
  59  * Setup and link descriptors.
  60  *
  61  * 11N: we can no longer afford to self link the last descriptor.
  62  * MAC acknowledges BA status as long as it copies frames to host
  63  * buffer (or rx fifo). This can incorrectly acknowledge packets
  64  * to a sender if last desc is self-linked.
  65  */
  66 static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  67 {
  68         struct ath_hw *ah = sc->sc_ah;
  69         struct ath_common *common = ath9k_hw_common(ah);
  70         struct ath_desc *ds;
  71         struct sk_buff *skb;
  72
  73         ATH_RXBUF_RESET(bf);
  74
  75         ds = bf->bf_desc;
  76         ds->ds_link = 0; /* link to null */
  77         ds->ds_data = bf->bf_buf_addr;
  78
  79         /* virtual addr of the beginning of the buffer. */
  80         skb = bf->bf_mpdu;
  81         BUG_ON(skb == NULL);
  82         ds->ds_vdata = skb->data;
  83
  84         /*
  85          * setup rx descriptors. The rx_bufsize here tells the hardware
  86          * how much data it can DMA to us and that we are prepared
  87          * to process
  88          */
  89         ath9k_hw_setuprxdesc(ah, ds,
  90                              common->rx_bufsize,
  91                              0);
  92
  93         if (sc->rx.rxlink == NULL)
  94                 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  95         else
  96                 *sc->rx.rxlink = bf->bf_daddr;
  97
  98         sc->rx.rxlink = &ds->ds_link;
  99         ath9k_hw_rxena(ah);
 100 }
 101
 102 static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
 103 {
 104         /* XXX block beacon interrupts */
 105         ath9k_hw_setantenna(sc->sc_ah, antenna);
 106         sc->rx.defant = antenna;
 107         sc->rx.rxotherant = 0;
 108 }
 109
 110 static void ath_opmode_init(struct ath_softc *sc)
 111 {
 112         struct ath_hw *ah = sc->sc_ah;
 113         struct ath_common *common = ath9k_hw_common(ah);
 114
 115         u32 rfilt, mfilt[2];
 116
 117         /* configure rx filter */
 118         rfilt = ath_calcrxfilter(sc);
 119         ath9k_hw_setrxfilter(ah, rfilt);
 120
 121         /* configure bssid mask */
 122         ath_hw_setbssidmask(common);
 123
 124         /* configure operational mode */
 125         ath9k_hw_setopmode(ah);
 126
 127         /* calculate and install multicast filter */
 128         mfilt[0] = mfilt[1] = ~0;
 129         ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
 130 }
 131
 132 static bool ath_rx_edma_buf_link(struct ath_softc *sc,
 133                                  enum ath9k_rx_qtype qtype)
 134 {
 135         struct ath_hw *ah = sc->sc_ah;
 136         struct ath_rx_edma *rx_edma;
 137         struct sk_buff *skb;
 138         struct ath_buf *bf;
 139
 140         rx_edma = &sc->rx.rx_edma[qtype];
 141         if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
 142                 return false;
 143
 144         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 145         list_del_init(&bf->list);
 146
 147         skb = bf->bf_mpdu;
 148
 149         ATH_RXBUF_RESET(bf);
 150         memset(skb->data, 0, ah->caps.rx_status_len);
 151         dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 152                                 ah->caps.rx_status_len, DMA_TO_DEVICE);
 153
 154         SKB_CB_ATHBUF(skb) = bf;
 155         ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
 156         skb_queue_tail(&rx_edma->rx_fifo, skb);
 157
 158         return true;
 159 }
 160
 161 static void ath_rx_addbuffer_edma(struct ath_softc *sc,
 162                                   enum ath9k_rx_qtype qtype, int size)
 163 {
 164         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 165         u32 nbuf = 0;
 166
 167         if (list_empty(&sc->rx.rxbuf)) {
 168                 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
 169                 return;
 170         }
 171
 172         while (!list_empty(&sc->rx.rxbuf)) {
 173                 nbuf++;
 174
 175                 if (!ath_rx_edma_buf_link(sc, qtype))
 176                         break;
 177
 178                 if (nbuf >= size)
 179                         break;
 180         }
 181 }
 182
 183 static void ath_rx_remove_buffer(struct ath_softc *sc,
 184                                  enum ath9k_rx_qtype qtype)
 185 {
 186         struct ath_buf *bf;
 187         struct ath_rx_edma *rx_edma;
 188         struct sk_buff *skb;
 189
 190         rx_edma = &sc->rx.rx_edma[qtype];
 191
 192         while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
 193                 bf = SKB_CB_ATHBUF(skb);
 194                 BUG_ON(!bf);
 195                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 196         }
 197 }
 198
 199 static void ath_rx_edma_cleanup(struct ath_softc *sc)
 200 {
 201         struct ath_buf *bf;
 202
 203         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
 204         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
 205
 206         list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 207                 if (bf->bf_mpdu)
 208                         dev_kfree_skb_any(bf->bf_mpdu);
 209         }
 210
 211         INIT_LIST_HEAD(&sc->rx.rxbuf);
 212
 213         kfree(sc->rx.rx_bufptr);
 214         sc->rx.rx_bufptr = NULL;
 215 }
 216
 217 static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
 218 {
 219         skb_queue_head_init(&rx_edma->rx_fifo);
 220         skb_queue_head_init(&rx_edma->rx_buffers);
 221         rx_edma->rx_fifo_hwsize = size;
 222 }
 223
 224 static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
 225 {
 226         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 227         struct ath_hw *ah = sc->sc_ah;
 228         struct sk_buff *skb;
 229         struct ath_buf *bf;
 230         int error = 0, i;
 231         u32 size;
 232
 233
 234         common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN +
 235                                      ah->caps.rx_status_len,
 236                                      min(common->cachelsz, (u16)64));
 237
 238         ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 239                                     ah->caps.rx_status_len);
 240
 241         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
 242                                ah->caps.rx_lp_qdepth);
 243         ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
 244                                ah->caps.rx_hp_qdepth);
 245
 246         size = sizeof(struct ath_buf) * nbufs;
 247         bf = kzalloc(size, GFP_KERNEL);
 248         if (!bf)
 249                 return -ENOMEM;
 250
 251         INIT_LIST_HEAD(&sc->rx.rxbuf);
 252         sc->rx.rx_bufptr = bf;
 253
 254         for (i = 0; i < nbufs; i++, bf++) {
 255                 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
 256                 if (!skb) {
 257                         error = -ENOMEM;
 258                         goto rx_init_fail;
 259                 }
 260
 261                 memset(skb->data, 0, common->rx_bufsize);
 262                 bf->bf_mpdu = skb;
 263
 264                 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 265                                                  common->rx_bufsize,
 266                                                  DMA_BIDIRECTIONAL);
 267                 if (unlikely(dma_mapping_error(sc->dev,
 268                                                 bf->bf_buf_addr))) {
 269                                 dev_kfree_skb_any(skb);
 270                                 bf->bf_mpdu = NULL;
 271                                 bf->bf_buf_addr = 0;
 272                                 ath_err(common,
 273                                         "dma_mapping_error() on RX init\n");
 274                                 error = -ENOMEM;
 275                                 goto rx_init_fail;
 276                 }
 277
 278                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 279         }
 280
 281         return 0;
 282
 283 rx_init_fail:
 284         ath_rx_edma_cleanup(sc);
 285         return error;
 286 }
 287
 288 static void ath_edma_start_recv(struct ath_softc *sc)
 289 {
 290         spin_lock_bh(&sc->rx.rxbuflock);
 291
 292         ath9k_hw_rxena(sc->sc_ah);
 293
 294         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
 295                               sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
 296
 297         ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
 298                               sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
 299
 300         ath_opmode_init(sc);
 301
 302         ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
 303
 304         spin_unlock_bh(&sc->rx.rxbuflock);
 305 }
 306
 307 static void ath_edma_stop_recv(struct ath_softc *sc)
 308 {
 309         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
 310         ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
 311 }
 312
 313 int ath_rx_init(struct ath_softc *sc, int nbufs)
 314 {
 315         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 316         struct sk_buff *skb;
 317         struct ath_buf *bf;
 318         int error = 0;
 319
 320         spin_lock_init(&sc->sc_pcu_lock);
 321         sc->sc_flags &= ~SC_OP_RXFLUSH;
 322         spin_lock_init(&sc->rx.rxbuflock);
 323
 324         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 325                 return ath_rx_edma_init(sc, nbufs);
 326         } else {
 327                 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
 328                                 min(common->cachelsz, (u16)64));
 329
 330                 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
 331                         common->cachelsz, common->rx_bufsize);
 332
 333                 /* Initialize rx descriptors */
 334
 335                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
 336                                 "rx", nbufs, 1, 0);
 337                 if (error != 0) {
 338                         ath_err(common,
 339                                 "failed to allocate rx descriptors: %d\n",
 340                                 error);
 341                         goto err;
 342                 }
 343
 344                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 345                         skb = ath_rxbuf_alloc(common, common->rx_bufsize,
 346                                               GFP_KERNEL);
 347                         if (skb == NULL) {
 348                                 error = -ENOMEM;
 349                                 goto err;
 350                         }
 351
 352                         bf->bf_mpdu = skb;
 353                         bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
 354                                         common->rx_bufsize,
 355                                         DMA_FROM_DEVICE);
 356                         if (unlikely(dma_mapping_error(sc->dev,
 357                                                         bf->bf_buf_addr))) {
 358                                 dev_kfree_skb_any(skb);
 359                                 bf->bf_mpdu = NULL;
 360                                 bf->bf_buf_addr = 0;
 361                                 ath_err(common,
 362                                         "dma_mapping_error() on RX init\n");
 363                                 error = -ENOMEM;
 364                                 goto err;
 365                         }
 366                 }
 367                 sc->rx.rxlink = NULL;
 368         }
 369
 370 err:
 371         if (error)
 372                 ath_rx_cleanup(sc);
 373
 374         return error;
 375 }
 376
 377 void ath_rx_cleanup(struct ath_softc *sc)
 378 {
 379         struct ath_hw *ah = sc->sc_ah;
 380         struct ath_common *common = ath9k_hw_common(ah);
 381         struct sk_buff *skb;
 382         struct ath_buf *bf;
 383
 384         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 385                 ath_rx_edma_cleanup(sc);
 386                 return;
 387         } else {
 388                 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
 389                         skb = bf->bf_mpdu;
 390                         if (skb) {
 391                                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
 392                                                 common->rx_bufsize,
 393                                                 DMA_FROM_DEVICE);
 394                                 dev_kfree_skb(skb);
 395                                 bf->bf_buf_addr = 0;
 396                                 bf->bf_mpdu = NULL;
 397                         }
 398                 }
 399
 400                 if (sc->rx.rxdma.dd_desc_len != 0)
 401                         ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
 402         }
 403 }
 404
 405 /*
 406  * Calculate the receive filter according to the
 407  * operating mode and state:
 408  *
 409  * o always accept unicast, broadcast, and multicast traffic
 410  * o maintain current state of phy error reception (the hal
 411  *   may enable phy error frames for noise immunity work)
 412  * o probe request frames are accepted only when operating in
 413  *   hostap, adhoc, or monitor modes
 414  * o enable promiscuous mode according to the interface state
 415  * o accept beacons:
 416  *   - when operating in adhoc mode so the 802.11 layer creates
 417  *     node table entries for peers,
 418  *   - when operating in station mode for collecting rssi data when
 419  *     the station is otherwise quiet, or
 420  *   - when operating as a repeater so we see repeater-sta beacons
 421  *   - when scanning
 422  */
 423
 424 u32 ath_calcrxfilter(struct ath_softc *sc)
 425 {
 426 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
 427
 428         u32 rfilt;
 429
 430         rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
 431                 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
 432                 | ATH9K_RX_FILTER_MCAST;
 433
 434         if (sc->rx.rxfilter & FIF_PROBE_REQ)
 435                 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
 436
 437         /*
 438          * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
 439          * mode interface or when in monitor mode. AP mode does not need this
 440          * since it receives all in-BSS frames anyway.
 441          */
 442         if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) &&
 443              (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) ||
 444             (sc->sc_ah->is_monitoring))
 445                 rfilt |= ATH9K_RX_FILTER_PROM;
 446
 447         if (sc->rx.rxfilter & FIF_CONTROL)
 448                 rfilt |= ATH9K_RX_FILTER_CONTROL;
 449
 450         if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
 451             (sc->nvifs <= 1) &&
 452             !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
 453                 rfilt |= ATH9K_RX_FILTER_MYBEACON;
 454         else
 455                 rfilt |= ATH9K_RX_FILTER_BEACON;
 456
 457         if ((AR_SREV_9280_20_OR_LATER(sc->sc_ah) ||
 458             AR_SREV_9285_12_OR_LATER(sc->sc_ah)) &&
 459             (sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
 460             (sc->rx.rxfilter & FIF_PSPOLL))
 461                 rfilt |= ATH9K_RX_FILTER_PSPOLL;
 462
 463         if (conf_is_ht(&sc->hw->conf))
 464                 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
 465
 466         if (sc->sec_wiphy || (sc->nvifs > 1) ||
 467             (sc->rx.rxfilter & FIF_OTHER_BSS)) {
 468                 /* The following may also be needed for other older chips */
 469                 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
 470                         rfilt |= ATH9K_RX_FILTER_PROM;
 471                 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
 472         }
 473
 474         return rfilt;
 475
 476 #undef RX_FILTER_PRESERVE
 477 }
 478
 479 int ath_startrecv(struct ath_softc *sc)
 480 {
 481         struct ath_hw *ah = sc->sc_ah;
 482         struct ath_buf *bf, *tbf;
 483
 484         if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
 485                 ath_edma_start_recv(sc);
 486                 return 0;
 487         }
 488
 489         spin_lock_bh(&sc->rx.rxbuflock);
 490         if (list_empty(&sc->rx.rxbuf))
 491                 goto start_recv;
 492
 493         sc->rx.rxlink = NULL;
 494         list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
 495                 ath_rx_buf_link(sc, bf);
 496         }
 497
 498         /* We could have deleted elements so the list may be empty now */
 499         if (list_empty(&sc->rx.rxbuf))
 500                 goto start_recv;
 501
 502         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 503         ath9k_hw_putrxbuf(ah, bf->bf_daddr);
 504         ath9k_hw_rxena(ah);
 505
 506 start_recv:
 507         ath_opmode_init(sc);
 508         ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
 509
 510         spin_unlock_bh(&sc->rx.rxbuflock);
 511
 512         return 0;
 513 }
 514
 515 bool ath_stoprecv(struct ath_softc *sc)
 516 {
 517         struct ath_hw *ah = sc->sc_ah;
 518         bool stopped;
 519
 520         spin_lock_bh(&sc->rx.rxbuflock);
 521         ath9k_hw_abortpcurecv(ah);
 522         ath9k_hw_setrxfilter(ah, 0);
 523         stopped = ath9k_hw_stopdmarecv(ah);
 524
 525         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 526                 ath_edma_stop_recv(sc);
 527         else
 528                 sc->rx.rxlink = NULL;
 529         spin_unlock_bh(&sc->rx.rxbuflock);
 530
 531         if (unlikely(!stopped)) {
 532                 ath_err(ath9k_hw_common(sc->sc_ah),
 533                         "Could not stop RX, we could be "
 534                         "confusing the DMA engine when we start RX up\n");
 535                 ATH_DBG_WARN_ON_ONCE(!stopped);
 536         }
 537         return stopped;
 538 }
 539
 540 void ath_flushrecv(struct ath_softc *sc)
 541 {
 542         sc->sc_flags |= SC_OP_RXFLUSH;
 543         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
 544                 ath_rx_tasklet(sc, 1, true);
 545         ath_rx_tasklet(sc, 1, false);
 546         sc->sc_flags &= ~SC_OP_RXFLUSH;
 547 }
 548
 549 static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
 550 {
 551         /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
 552         struct ieee80211_mgmt *mgmt;
 553         u8 *pos, *end, id, elen;
 554         struct ieee80211_tim_ie *tim;
 555
 556         mgmt = (struct ieee80211_mgmt *)skb->data;
 557         pos = mgmt->u.beacon.variable;
 558         end = skb->data + skb->len;
 559
 560         while (pos + 2 < end) {
 561                 id = *pos++;
 562                 elen = *pos++;
 563                 if (pos + elen > end)
 564                         break;
 565
 566                 if (id == WLAN_EID_TIM) {
 567                         if (elen < sizeof(*tim))
 568                                 break;
 569                         tim = (struct ieee80211_tim_ie *) pos;
 570                         if (tim->dtim_count != 0)
 571                                 break;
 572                         return tim->bitmap_ctrl & 0x01;
 573                 }
 574
 575                 pos += elen;
 576         }
 577
 578         return false;
 579 }
 580
 581 static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
 582 {
 583         struct ieee80211_mgmt *mgmt;
 584         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 585
 586         if (skb->len < 24 + 8 + 2 + 2)
 587                 return;
 588
 589         mgmt = (struct ieee80211_mgmt *)skb->data;
 590         if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0)
 591                 return; /* not from our current AP */
 592
 593         sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
 594
 595         if (sc->ps_flags & PS_BEACON_SYNC) {
 596                 sc->ps_flags &= ~PS_BEACON_SYNC;
 597                 ath_dbg(common, ATH_DBG_PS,
 598                         "Reconfigure Beacon timers based on timestamp from the AP\n");
 599                 ath_beacon_config(sc, NULL);
 600         }
 601
 602         if (ath_beacon_dtim_pending_cab(skb)) {
 603                 /*
 604                  * Remain awake waiting for buffered broadcast/multicast
 605                  * frames. If the last broadcast/multicast frame is not
 606                  * received properly, the next beacon frame will work as
 607                  * a backup trigger for returning into NETWORK SLEEP state,
 608                  * so we are waiting for it as well.
 609                  */
 610                 ath_dbg(common, ATH_DBG_PS,
 611                         "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
 612                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
 613                 return;
 614         }
 615
 616         if (sc->ps_flags & PS_WAIT_FOR_CAB) {
 617                 /*
 618                  * This can happen if a broadcast frame is dropped or the AP
 619                  * fails to send a frame indicating that all CAB frames have
 620                  * been delivered.
 621                  */
 622                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
 623                 ath_dbg(common, ATH_DBG_PS,
 624                         "PS wait for CAB frames timed out\n");
 625         }
 626 }
 627
 628 static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
 629 {
 630         struct ieee80211_hdr *hdr;
 631         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 632
 633         hdr = (struct ieee80211_hdr *)skb->data;
 634
 635         /* Process Beacon and CAB receive in PS state */
 636         if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
 637             && ieee80211_is_beacon(hdr->frame_control))
 638                 ath_rx_ps_beacon(sc, skb);
 639         else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
 640                  (ieee80211_is_data(hdr->frame_control) ||
 641                   ieee80211_is_action(hdr->frame_control)) &&
 642                  is_multicast_ether_addr(hdr->addr1) &&
 643                  !ieee80211_has_moredata(hdr->frame_control)) {
 644                 /*
 645                  * No more broadcast/multicast frames to be received at this
 646                  * point.
 647                  */
 648                 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
 649                 ath_dbg(common, ATH_DBG_PS,
 650                         "All PS CAB frames received, back to sleep\n");
 651         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
 652                    !is_multicast_ether_addr(hdr->addr1) &&
 653                    !ieee80211_has_morefrags(hdr->frame_control)) {
 654                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
 655                 ath_dbg(common, ATH_DBG_PS,
 656                         "Going back to sleep after having received PS-Poll data (0x%lx)\n",
 657                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
 658                                         PS_WAIT_FOR_CAB |
 659                                         PS_WAIT_FOR_PSPOLL_DATA |
 660                                         PS_WAIT_FOR_TX_ACK));
 661         }
 662 }
 663
 664 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
 665                                     struct ath_softc *sc, struct sk_buff *skb,
 666                                     struct ieee80211_rx_status *rxs)
 667 {
 668         struct ieee80211_hdr *hdr;
 669
 670         hdr = (struct ieee80211_hdr *)skb->data;
 671
 672         /* Send the frame to mac80211 */
 673         if (is_multicast_ether_addr(hdr->addr1)) {
 674                 int i;
 675                 /*
 676                  * Deliver broadcast/multicast frames to all suitable
 677                  * virtual wiphys.
 678                  */
 679                 /* TODO: filter based on channel configuration */
 680                 for (i = 0; i < sc->num_sec_wiphy; i++) {
 681                         struct ath_wiphy *aphy = sc->sec_wiphy[i];
 682                         struct sk_buff *nskb;
 683                         if (aphy == NULL)
 684                                 continue;
 685                         nskb = skb_copy(skb, GFP_ATOMIC);
 686                         if (!nskb)
 687                                 continue;
 688                         ieee80211_rx(aphy->hw, nskb);
 689                 }
 690                 ieee80211_rx(sc->hw, skb);
 691         } else
 692                 /* Deliver unicast frames based on receiver address */
 693                 ieee80211_rx(hw, skb);
 694 }
 695
 696 static bool ath_edma_get_buffers(struct ath_softc *sc,
 697                                  enum ath9k_rx_qtype qtype)
 698 {
 699         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
 700         struct ath_hw *ah = sc->sc_ah;
 701         struct ath_common *common = ath9k_hw_common(ah);
 702         struct sk_buff *skb;
 703         struct ath_buf *bf;
 704         int ret;
 705
 706         skb = skb_peek(&rx_edma->rx_fifo);
 707         if (!skb)
 708                 return false;
 709
 710         bf = SKB_CB_ATHBUF(skb);
 711         BUG_ON(!bf);
 712
 713         dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
 714                                 common->rx_bufsize, DMA_FROM_DEVICE);
 715
 716         ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
 717         if (ret == -EINPROGRESS) {
 718                 /*let device gain the buffer again*/
 719                 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 720                                 common->rx_bufsize, DMA_FROM_DEVICE);
 721                 return false;
 722         }
 723
 724         __skb_unlink(skb, &rx_edma->rx_fifo);
 725         if (ret == -EINVAL) {
 726                 /* corrupt descriptor, skip this one and the following one */
 727                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 728                 ath_rx_edma_buf_link(sc, qtype);
 729                 skb = skb_peek(&rx_edma->rx_fifo);
 730                 if (!skb)
 731                         return true;
 732
 733                 bf = SKB_CB_ATHBUF(skb);
 734                 BUG_ON(!bf);
 735
 736                 __skb_unlink(skb, &rx_edma->rx_fifo);
 737                 list_add_tail(&bf->list, &sc->rx.rxbuf);
 738                 ath_rx_edma_buf_link(sc, qtype);
 739                 return true;
 740         }
 741         skb_queue_tail(&rx_edma->rx_buffers, skb);
 742
 743         return true;
 744 }
 745
 746 static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
 747                                                 struct ath_rx_status *rs,
 748                                                 enum ath9k_rx_qtype qtype)
 749 {
 750         struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
 751         struct sk_buff *skb;
 752         struct ath_buf *bf;
 753
 754         while (ath_edma_get_buffers(sc, qtype));
 755         skb = __skb_dequeue(&rx_edma->rx_buffers);
 756         if (!skb)
 757                 return NULL;
 758
 759         bf = SKB_CB_ATHBUF(skb);
 760         ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
 761         return bf;
 762 }
 763
 764 static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
 765                                            struct ath_rx_status *rs)
 766 {
 767         struct ath_hw *ah = sc->sc_ah;
 768         struct ath_common *common = ath9k_hw_common(ah);
 769         struct ath_desc *ds;
 770         struct ath_buf *bf;
 771         int ret;
 772
 773         if (list_empty(&sc->rx.rxbuf)) {
 774                 sc->rx.rxlink = NULL;
 775                 return NULL;
 776         }
 777
 778         bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
 779         ds = bf->bf_desc;
 780
 781         /*
 782          * Must provide the virtual address of the current
 783          * descriptor, the physical address, and the virtual
 784          * address of the next descriptor in the h/w chain.
 785          * This allows the HAL to look ahead to see if the
 786          * hardware is done with a descriptor by checking the
 787          * done bit in the following descriptor and the address
 788          * of the current descriptor the DMA engine is working
 789          * on.  All this is necessary because of our use of
 790          * a self-linked list to avoid rx overruns.
 791          */
 792         ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
 793         if (ret == -EINPROGRESS) {
 794                 struct ath_rx_status trs;
 795                 struct ath_buf *tbf;
 796                 struct ath_desc *tds;
 797
 798                 memset(&trs, 0, sizeof(trs));
 799                 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
 800                         sc->rx.rxlink = NULL;
 801                         return NULL;
 802                 }
 803
 804                 tbf = list_entry(bf->list.next, struct ath_buf, list);
 805
 806                 /*
 807                  * On some hardware the descriptor status words could
 808                  * get corrupted, including the done bit. Because of
 809                  * this, check if the next descriptor's done bit is
 810                  * set or not.
 811                  *
 812                  * If the next descriptor's done bit is set, the current
 813                  * descriptor has been corrupted. Force s/w to discard
 814                  * this descriptor and continue...
 815                  */
 816
 817                 tds = tbf->bf_desc;
 818                 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
 819                 if (ret == -EINPROGRESS)
 820                         return NULL;
 821         }
 822
 823         if (!bf->bf_mpdu)
 824                 return bf;
 825
 826         /*
 827          * Synchronize the DMA transfer with CPU before
 828          * 1. accessing the frame
 829          * 2. requeueing the same buffer to h/w
 830          */
 831         dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
 832                         common->rx_bufsize,
 833                         DMA_FROM_DEVICE);
 834
 835         return bf;
 836 }
 837
 838 /* Assumes you've already done the endian to CPU conversion */
 839 static bool ath9k_rx_accept(struct ath_common *common,
 840                             struct ieee80211_hdr *hdr,
 841                             struct ieee80211_rx_status *rxs,
 842                             struct ath_rx_status *rx_stats,
 843                             bool *decrypt_error)
 844 {
 845         struct ath_hw *ah = common->ah;
 846         __le16 fc;
 847         u8 rx_status_len = ah->caps.rx_status_len;
 848
 849         fc = hdr->frame_control;
 850
 851         if (!rx_stats->rs_datalen)
 852                 return false;
 853         /*
 854          * rs_status follows rs_datalen so if rs_datalen is too large
 855          * we can take a hint that hardware corrupted it, so ignore
 856          * those frames.
 857          */
 858         if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
 859                 return false;
 860
 861         /*
 862          * rs_more indicates chained descriptors which can be used
 863          * to link buffers together for a sort of scatter-gather
 864          * operation.
 865          * reject the frame, we don't support scatter-gather yet and
 866          * the frame is probably corrupt anyway
 867          */
 868         if (rx_stats->rs_more)
 869                 return false;
 870
 871         /*
 872          * The rx_stats->rs_status will not be set until the end of the
 873          * chained descriptors so it can be ignored if rs_more is set. The
 874          * rs_more will be false at the last element of the chained
 875          * descriptors.
 876          */
 877         if (rx_stats->rs_status != 0) {
 878                 if (rx_stats->rs_status & ATH9K_RXERR_CRC)
 879                         rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
 880                 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
 881                         return false;
 882
 883                 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
 884                         *decrypt_error = true;
 885                 } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) {
 886                         /*
 887                          * The MIC error bit is only valid if the frame
 888                          * is not a control frame or fragment, and it was
 889                          * decrypted using a valid TKIP key.
 890                          */
 891                         if (!ieee80211_is_ctl(fc) &&
 892                             !ieee80211_has_morefrags(fc) &&
 893                             !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
 894                             test_bit(rx_stats->rs_keyix, common->tkip_keymap))
 895                                 rxs->flag |= RX_FLAG_MMIC_ERROR;
 896                         else
 897                                 rx_stats->rs_status &= ~ATH9K_RXERR_MIC;
 898                 }
 899                 /*
 900                  * Reject error frames with the exception of
 901                  * decryption and MIC failures. For monitor mode,
 902                  * we also ignore the CRC error.
 903                  */
 904                 if (ah->is_monitoring) {
 905                         if (rx_stats->rs_status &
 906                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
 907                               ATH9K_RXERR_CRC))
 908                                 return false;
 909                 } else {
 910                         if (rx_stats->rs_status &
 911                             ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
 912                                 return false;
 913                         }
 914                 }
 915         }
 916         return true;
 917 }
 918
 919 static int ath9k_process_rate(struct ath_common *common,
 920                               struct ieee80211_hw *hw,
 921                               struct ath_rx_status *rx_stats,
 922                               struct ieee80211_rx_status *rxs)
 923 {
 924         struct ieee80211_supported_band *sband;
 925         enum ieee80211_band band;
 926         unsigned int i = 0;
 927
 928         band = hw->conf.channel->band;
 929         sband = hw->wiphy->bands[band];
 930
 931         if (rx_stats->rs_rate & 0x80) {
 932                 /* HT rate */
 933                 rxs->flag |= RX_FLAG_HT;
 934                 if (rx_stats->rs_flags & ATH9K_RX_2040)
 935                         rxs->flag |= RX_FLAG_40MHZ;
 936                 if (rx_stats->rs_flags & ATH9K_RX_GI)
 937                         rxs->flag |= RX_FLAG_SHORT_GI;
 938                 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
 939                 return 0;
 940         }
 941
 942         for (i = 0; i < sband->n_bitrates; i++) {
 943                 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
 944                         rxs->rate_idx = i;
 945                         return 0;
 946                 }
 947                 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
 948                         rxs->flag |= RX_FLAG_SHORTPRE;
 949                         rxs->rate_idx = i;
 950                         return 0;
 951                 }
 952         }
 953
 954         /*
 955          * No valid hardware bitrate found -- we should not get here
 956          * because hardware has already validated this frame as OK.
 957          */
 958         ath_dbg(common, ATH_DBG_XMIT,
 959                 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
 960                 rx_stats->rs_rate);
 961
 962         return -EINVAL;
 963 }
 964
 965 static void ath9k_process_rssi(struct ath_common *common,
 966                                struct ieee80211_hw *hw,
 967                                struct ieee80211_hdr *hdr,
 968                                struct ath_rx_status *rx_stats)
 969 {
 970         struct ath_wiphy *aphy = hw->priv;
 971         struct ath_hw *ah = common->ah;
 972         int last_rssi;
 973         __le16 fc;
 974
 975         if (ah->opmode != NL80211_IFTYPE_STATION)
 976                 return;
 977
 978         fc = hdr->frame_control;
 979         if (!ieee80211_is_beacon(fc) ||
 980             compare_ether_addr(hdr->addr3, common->curbssid))
 981                 return;
 982
 983         if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
 984                 ATH_RSSI_LPF(aphy->last_rssi, rx_stats->rs_rssi);
 985
 986         last_rssi = aphy->last_rssi;
 987         if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
 988                 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
 989                                               ATH_RSSI_EP_MULTIPLIER);
 990         if (rx_stats->rs_rssi < 0)
 991                 rx_stats->rs_rssi = 0;
 992
 993         /* Update Beacon RSSI, this is used by ANI. */
 994         ah->stats.avgbrssi = rx_stats->rs_rssi;
 995 }
 996
 997 /*
 998  * For Decrypt or Demic errors, we only mark packet status here and always push
 999  * up the frame up to let mac80211 handle the actual error case, be it no
1000  * decryption key or real decryption error. This let us keep statistics there.
1001  */
1002 static int ath9k_rx_skb_preprocess(struct ath_common *common,
1003                                    struct ieee80211_hw *hw,
1004                                    struct ieee80211_hdr *hdr,
1005                                    struct ath_rx_status *rx_stats,
1006                                    struct ieee80211_rx_status *rx_status,
1007                                    bool *decrypt_error)
1008 {
1009         memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1010
1011         /*
1012          * everything but the rate is checked here, the rate check is done
1013          * separately to avoid doing two lookups for a rate for each frame.
1014          */
1015         if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1016                 return -EINVAL;
1017
1018         ath9k_process_rssi(common, hw, hdr, rx_stats);
1019
1020         if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1021                 return -EINVAL;
1022
1023         rx_status->band = hw->conf.channel->band;
1024         rx_status->freq = hw->conf.channel->center_freq;
1025         rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1026         rx_status->antenna = rx_stats->rs_antenna;
1027         rx_status->flag |= RX_FLAG_TSFT;
1028
1029         return 0;
1030 }
1031
1032 static void ath9k_rx_skb_postprocess(struct ath_common *common,
1033                                      struct sk_buff *skb,
1034                                      struct ath_rx_status *rx_stats,
1035                                      struct ieee80211_rx_status *rxs,
1036                                      bool decrypt_error)
1037 {
1038         struct ath_hw *ah = common->ah;
1039         struct ieee80211_hdr *hdr;
1040         int hdrlen, padpos, padsize;
1041         u8 keyix;
1042         __le16 fc;
1043
1044         /* see if any padding is done by the hw and remove it */
1045         hdr = (struct ieee80211_hdr *) skb->data;
1046         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1047         fc = hdr->frame_control;
1048         padpos = ath9k_cmn_padpos(hdr->frame_control);
1049
1050         /* The MAC header is padded to have 32-bit boundary if the
1051          * packet payload is non-zero. The general calculation for
1052          * padsize would take into account odd header lengths:
1053          * padsize = (4 - padpos % 4) % 4; However, since only
1054          * even-length headers are used, padding can only be 0 or 2
1055          * bytes and we can optimize this a bit. In addition, we must
1056          * not try to remove padding from short control frames that do
1057          * not have payload. */
1058         padsize = padpos & 3;
1059         if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1060                 memmove(skb->data + padsize, skb->data, padpos);
1061                 skb_pull(skb, padsize);
1062         }
1063
1064         keyix = rx_stats->rs_keyix;
1065
1066         if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1067             ieee80211_has_protected(fc)) {
1068                 rxs->flag |= RX_FLAG_DECRYPTED;
1069         } else if (ieee80211_has_protected(fc)
1070                    && !decrypt_error && skb->len >= hdrlen + 4) {
1071                 keyix = skb->data[hdrlen + 3] >> 6;
1072
1073                 if (test_bit(keyix, common->keymap))
1074                         rxs->flag |= RX_FLAG_DECRYPTED;
1075         }
1076         if (ah->sw_mgmt_crypto &&
1077             (rxs->flag & RX_FLAG_DECRYPTED) &&
1078             ieee80211_is_mgmt(fc))
1079                 /* Use software decrypt for management frames. */
1080                 rxs->flag &= ~RX_FLAG_DECRYPTED;
1081 }
1082
1083 static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1084                                       struct ath_hw_antcomb_conf ant_conf,
1085                                       int main_rssi_avg)
1086 {
1087         antcomb->quick_scan_cnt = 0;
1088
1089         if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1090                 antcomb->rssi_lna2 = main_rssi_avg;
1091         else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1092                 antcomb->rssi_lna1 = main_rssi_avg;
1093
1094         switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1095         case (0x10): /* LNA2 A-B */
1096                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1097                 antcomb->first_quick_scan_conf =
1098                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1099                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1100                 break;
1101         case (0x20): /* LNA1 A-B */
1102                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1103                 antcomb->first_quick_scan_conf =
1104                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1105                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1106                 break;
1107         case (0x21): /* LNA1 LNA2 */
1108                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1109                 antcomb->first_quick_scan_conf =
1110                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1111                 antcomb->second_quick_scan_conf =
1112                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1113                 break;
1114         case (0x12): /* LNA2 LNA1 */
1115                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1116                 antcomb->first_quick_scan_conf =
1117                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1118                 antcomb->second_quick_scan_conf =
1119                         ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1120                 break;
1121         case (0x13): /* LNA2 A+B */
1122                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1123                 antcomb->first_quick_scan_conf =
1124                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1125                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1126                 break;
1127         case (0x23): /* LNA1 A+B */
1128                 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1129                 antcomb->first_quick_scan_conf =
1130                         ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1131                 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1132                 break;
1133         default:
1134                 break;
1135         }
1136 }
1137
1138 static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1139                                 struct ath_hw_antcomb_conf *div_ant_conf,
1140                                 int main_rssi_avg, int alt_rssi_avg,
1141                                 int alt_ratio)
1142 {
1143         /* alt_good */
1144         switch (antcomb->quick_scan_cnt) {
1145         case 0:
1146                 /* set alt to main, and alt to first conf */
1147                 div_ant_conf->main_lna_conf = antcomb->main_conf;
1148                 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1149                 break;
1150         case 1:
1151                 /* set alt to main, and alt to first conf */
1152                 div_ant_conf->main_lna_conf = antcomb->main_conf;
1153                 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1154                 antcomb->rssi_first = main_rssi_avg;
1155                 antcomb->rssi_second = alt_rssi_avg;
1156
1157                 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1158                         /* main is LNA1 */
1159                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1160                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1161                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1162                                                 main_rssi_avg, alt_rssi_avg,
1163                                                 antcomb->total_pkt_count))
1164                                 antcomb->first_ratio = true;
1165                         else
1166                                 antcomb->first_ratio = false;
1167                 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1168                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1169                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1170                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1171                                                 main_rssi_avg, alt_rssi_avg,
1172                                                 antcomb->total_pkt_count))
1173                                 antcomb->first_ratio = true;
1174                         else
1175                                 antcomb->first_ratio = false;
1176                 } else {
1177                         if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1178                             (alt_rssi_avg > main_rssi_avg +
1179                             ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1180                             (alt_rssi_avg > main_rssi_avg)) &&
1181                             (antcomb->total_pkt_count > 50))
1182                                 antcomb->first_ratio = true;
1183                         else
1184                                 antcomb->first_ratio = false;
1185                 }
1186                 break;
1187         case 2:
1188                 antcomb->alt_good = false;
1189                 antcomb->scan_not_start = false;
1190                 antcomb->scan = false;
1191                 antcomb->rssi_first = main_rssi_avg;
1192                 antcomb->rssi_third = alt_rssi_avg;
1193
1194                 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1195                         antcomb->rssi_lna1 = alt_rssi_avg;
1196                 else if (antcomb->second_quick_scan_conf ==
1197                          ATH_ANT_DIV_COMB_LNA2)
1198                         antcomb->rssi_lna2 = alt_rssi_avg;
1199                 else if (antcomb->second_quick_scan_conf ==
1200                          ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1201                         if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1202                                 antcomb->rssi_lna2 = main_rssi_avg;
1203                         else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1204                                 antcomb->rssi_lna1 = main_rssi_avg;
1205                 }
1206
1207                 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1208                     ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1209                         div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1210                 else
1211                         div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1212
1213                 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1214                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1215                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1216                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1217                                                 main_rssi_avg, alt_rssi_avg,
1218                                                 antcomb->total_pkt_count))
1219                                 antcomb->second_ratio = true;
1220                         else
1221                                 antcomb->second_ratio = false;
1222                 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1223                         if (ath_is_alt_ant_ratio_better(alt_ratio,
1224                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1225                                                 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1226                                                 main_rssi_avg, alt_rssi_avg,
1227                                                 antcomb->total_pkt_count))
1228                                 antcomb->second_ratio = true;
1229                         else
1230                                 antcomb->second_ratio = false;
1231                 } else {
1232                         if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1233                             (alt_rssi_avg > main_rssi_avg +
1234                             ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1235                             (alt_rssi_avg > main_rssi_avg)) &&
1236                             (antcomb->total_pkt_count > 50))
1237                                 antcomb->second_ratio = true;
1238                         else
1239                                 antcomb->second_ratio = false;
1240                 }
1241
1242                 /* set alt to the conf with maximun ratio */
1243                 if (antcomb->first_ratio && antcomb->second_ratio) {
1244                         if (antcomb->rssi_second > antcomb->rssi_third) {
1245                                 /* first alt*/
1246                                 if ((antcomb->first_quick_scan_conf ==
1247                                     ATH_ANT_DIV_COMB_LNA1) ||
1248                                     (antcomb->first_quick_scan_conf ==
1249                                     ATH_ANT_DIV_COMB_LNA2))
1250                                         /* Set alt LNA1 or LNA2*/
1251                                         if (div_ant_conf->main_lna_conf ==
1252                                             ATH_ANT_DIV_COMB_LNA2)
1253                                                 div_ant_conf->alt_lna_conf =
1254                                                         ATH_ANT_DIV_COMB_LNA1;
1255                                         else
1256                                                 div_ant_conf->alt_lna_conf =
1257                                                         ATH_ANT_DIV_COMB_LNA2;
1258                                 else
1259                                         /* Set alt to A+B or A-B */
1260                                         div_ant_conf->alt_lna_conf =
1261                                                 antcomb->first_quick_scan_conf;
1262                         } else if ((antcomb->second_quick_scan_conf ==
1263                                    ATH_ANT_DIV_COMB_LNA1) ||
1264                                    (antcomb->second_quick_scan_conf ==
1265                                    ATH_ANT_DIV_COMB_LNA2)) {
1266                                 /* Set alt LNA1 or LNA2 */
1267                                 if (div_ant_conf->main_lna_conf ==
1268                                     ATH_ANT_DIV_COMB_LNA2)
1269                                         div_ant_conf->alt_lna_conf =
1270                                                 ATH_ANT_DIV_COMB_LNA1;
1271                                 else
1272                                         div_ant_conf->alt_lna_conf =
1273                                                 ATH_ANT_DIV_COMB_LNA2;
1274                         } else {
1275                                 /* Set alt to A+B or A-B */
1276                                 div_ant_conf->alt_lna_conf =
1277                                         antcomb->second_quick_scan_conf;
1278                         }
1279                 } else if (antcomb->first_ratio) {
1280                         /* first alt */
1281                         if ((antcomb->first_quick_scan_conf ==
1282                             ATH_ANT_DIV_COMB_LNA1) ||
1283                             (antcomb->first_quick_scan_conf ==
1284                             ATH_ANT_DIV_COMB_LNA2))
1285                                         /* Set alt LNA1 or LNA2 */
1286                                 if (div_ant_conf->main_lna_conf ==
1287                                     ATH_ANT_DIV_COMB_LNA2)
1288                                         div_ant_conf->alt_lna_conf =
1289                                                         ATH_ANT_DIV_COMB_LNA1;
1290                                 else
1291                                         div_ant_conf->alt_lna_conf =
1292                                                         ATH_ANT_DIV_COMB_LNA2;
1293                         else
1294                                 /* Set alt to A+B or A-B */
1295                                 div_ant_conf->alt_lna_conf =
1296                                                 antcomb->first_quick_scan_conf;
1297                 } else if (antcomb->second_ratio) {
1298                                 /* second alt */
1299                         if ((antcomb->second_quick_scan_conf ==
1300                             ATH_ANT_DIV_COMB_LNA1) ||
1301                             (antcomb->second_quick_scan_conf ==
1302                             ATH_ANT_DIV_COMB_LNA2))
1303                                 /* Set alt LNA1 or LNA2 */
1304                                 if (div_ant_conf->main_lna_conf ==
1305                                     ATH_ANT_DIV_COMB_LNA2)
1306                                         div_ant_conf->alt_lna_conf =
1307                                                 ATH_ANT_DIV_COMB_LNA1;
1308                                 else
1309                                         div_ant_conf->alt_lna_conf =
1310                                                 ATH_ANT_DIV_COMB_LNA2;
1311                         else
1312                                 /* Set alt to A+B or A-B */
1313                                 div_ant_conf->alt_lna_conf =
1314                                                 antcomb->second_quick_scan_conf;
1315                 } else {
1316                         /* main is largest */
1317                         if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1318                             (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1319                                 /* Set alt LNA1 or LNA2 */
1320                                 if (div_ant_conf->main_lna_conf ==
1321                                     ATH_ANT_DIV_COMB_LNA2)
1322                                         div_ant_conf->alt_lna_conf =
1323                                                         ATH_ANT_DIV_COMB_LNA1;
1324                                 else
1325                                         div_ant_conf->alt_lna_conf =
1326                                                         ATH_ANT_DIV_COMB_LNA2;
1327                         else
1328                                 /* Set alt to A+B or A-B */
1329                                 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1330                 }
1331                 break;
1332         default:
1333                 break;
1334         }
1335 }
1336
1337 static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf)
1338 {
1339         /* Adjust the fast_div_bias based on main and alt lna conf */
1340         switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) {
1341         case (0x01): /* A-B LNA2 */
1342                 ant_conf->fast_div_bias = 0x3b;
1343                 break;
1344         case (0x02): /* A-B LNA1 */
1345                 ant_conf->fast_div_bias = 0x3d;
1346                 break;
1347         case (0x03): /* A-B A+B */
1348                 ant_conf->fast_div_bias = 0x1;
1349                 break;
1350         case (0x10): /* LNA2 A-B */
1351                 ant_conf->fast_div_bias = 0x7;
1352                 break;
1353         case (0x12): /* LNA2 LNA1 */
1354                 ant_conf->fast_div_bias = 0x2;
1355                 break;
1356         case (0x13): /* LNA2 A+B */
1357                 ant_conf->fast_div_bias = 0x7;
1358                 break;
1359         case (0x20): /* LNA1 A-B */
1360                 ant_conf->fast_div_bias = 0x6;
1361                 break;
1362         case (0x21): /* LNA1 LNA2 */
1363                 ant_conf->fast_div_bias = 0x0;
1364                 break;
1365         case (0x23): /* LNA1 A+B */
1366                 ant_conf->fast_div_bias = 0x6;
1367                 break;
1368         case (0x30): /* A+B A-B */
1369                 ant_conf->fast_div_bias = 0x1;
1370                 break;
1371         case (0x31): /* A+B LNA2 */
1372                 ant_conf->fast_div_bias = 0x3b;
1373                 break;
1374         case (0x32): /* A+B LNA1 */
1375                 ant_conf->fast_div_bias = 0x3d;
1376                 break;
1377         default:
1378                 break;
1379         }
1380 }
1381
1382 /* Antenna diversity and combining */
1383 static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1384 {
1385         struct ath_hw_antcomb_conf div_ant_conf;
1386         struct ath_ant_comb *antcomb = &sc->ant_comb;
1387         int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1388         int curr_main_set, curr_bias;
1389         int main_rssi = rs->rs_rssi_ctl0;
1390         int alt_rssi = rs->rs_rssi_ctl1;
1391         int rx_ant_conf,  main_ant_conf;
1392         bool short_scan = false;
1393
1394         rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1395                        ATH_ANT_RX_MASK;
1396         main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1397                          ATH_ANT_RX_MASK;
1398
1399         /* Record packet only when alt_rssi is positive */
1400         if (alt_rssi > 0) {
1401                 antcomb->total_pkt_count++;
1402                 antcomb->main_total_rssi += main_rssi;
1403                 antcomb->alt_total_rssi  += alt_rssi;
1404                 if (main_ant_conf == rx_ant_conf)
1405                         antcomb->main_recv_cnt++;
1406                 else
1407                         antcomb->alt_recv_cnt++;
1408         }
1409
1410         /* Short scan check */
1411         if (antcomb->scan && antcomb->alt_good) {
1412                 if (time_after(jiffies, antcomb->scan_start_time +
1413                     msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1414                         short_scan = true;
1415                 else
1416                         if (antcomb->total_pkt_count ==
1417                             ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1418                                 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1419                                             antcomb->total_pkt_count);
1420                                 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1421                                         short_scan = true;
1422                         }
1423         }
1424
1425         if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1426             rs->rs_moreaggr) && !short_scan)
1427                 return;
1428
1429         if (antcomb->total_pkt_count) {
1430                 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1431                              antcomb->total_pkt_count);
1432                 main_rssi_avg = (antcomb->main_total_rssi /
1433                                  antcomb->total_pkt_count);
1434                 alt_rssi_avg = (antcomb->alt_total_rssi /
1435                                  antcomb->total_pkt_count);
1436         }
1437
1438
1439         ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1440         curr_alt_set = div_ant_conf.alt_lna_conf;
1441         curr_main_set = div_ant_conf.main_lna_conf;
1442         curr_bias = div_ant_conf.fast_div_bias;
1443
1444         antcomb->count++;
1445
1446         if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1447                 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1448                         ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1449                                                   main_rssi_avg);
1450                         antcomb->alt_good = true;
1451                 } else {
1452                         antcomb->alt_good = false;
1453                 }
1454
1455                 antcomb->count = 0;
1456                 antcomb->scan = true;
1457                 antcomb->scan_not_start = true;
1458         }
1459
1460         if (!antcomb->scan) {
1461                 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1462                         if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1463                                 /* Switch main and alt LNA */
1464                                 div_ant_conf.main_lna_conf =
1465                                                 ATH_ANT_DIV_COMB_LNA2;
1466                                 div_ant_conf.alt_lna_conf  =
1467                                                 ATH_ANT_DIV_COMB_LNA1;
1468                         } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1469                                 div_ant_conf.main_lna_conf =
1470                                                 ATH_ANT_DIV_COMB_LNA1;
1471                                 div_ant_conf.alt_lna_conf  =
1472                                                 ATH_ANT_DIV_COMB_LNA2;
1473                         }
1474
1475                         goto div_comb_done;
1476                 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1477                            (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1478                         /* Set alt to another LNA */
1479                         if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1480                                 div_ant_conf.alt_lna_conf =
1481                                                 ATH_ANT_DIV_COMB_LNA1;
1482                         else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1483                                 div_ant_conf.alt_lna_conf =
1484                                                 ATH_ANT_DIV_COMB_LNA2;
1485
1486                         goto div_comb_done;
1487                 }
1488
1489                 if ((alt_rssi_avg < (main_rssi_avg +
1490                     ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA)))
1491                         goto div_comb_done;
1492         }
1493
1494         if (!antcomb->scan_not_start) {
1495                 switch (curr_alt_set) {
1496                 case ATH_ANT_DIV_COMB_LNA2:
1497                         antcomb->rssi_lna2 = alt_rssi_avg;
1498                         antcomb->rssi_lna1 = main_rssi_avg;
1499                         antcomb->scan = true;
1500                         /* set to A+B */
1501                         div_ant_conf.main_lna_conf =
1502                                 ATH_ANT_DIV_COMB_LNA1;
1503                         div_ant_conf.alt_lna_conf  =
1504                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1505                         break;
1506                 case ATH_ANT_DIV_COMB_LNA1:
1507                         antcomb->rssi_lna1 = alt_rssi_avg;
1508                         antcomb->rssi_lna2 = main_rssi_avg;
1509                         antcomb->scan = true;
1510                         /* set to A+B */
1511                         div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1512                         div_ant_conf.alt_lna_conf  =
1513                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1514                         break;
1515                 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1516                         antcomb->rssi_add = alt_rssi_avg;
1517                         antcomb->scan = true;
1518                         /* set to A-B */
1519                         div_ant_conf.alt_lna_conf =
1520                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1521                         break;
1522                 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1523                         antcomb->rssi_sub = alt_rssi_avg;
1524                         antcomb->scan = false;
1525                         if (antcomb->rssi_lna2 >
1526                             (antcomb->rssi_lna1 +
1527                             ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1528                                 /* use LNA2 as main LNA */
1529                                 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1530                                     (antcomb->rssi_add > antcomb->rssi_sub)) {
1531                                         /* set to A+B */
1532                                         div_ant_conf.main_lna_conf =
1533                                                 ATH_ANT_DIV_COMB_LNA2;
1534                                         div_ant_conf.alt_lna_conf  =
1535                                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1536                                 } else if (antcomb->rssi_sub >
1537                                            antcomb->rssi_lna1) {
1538                                         /* set to A-B */
1539                                         div_ant_conf.main_lna_conf =
1540                                                 ATH_ANT_DIV_COMB_LNA2;
1541                                         div_ant_conf.alt_lna_conf =
1542                                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1543                                 } else {
1544                                         /* set to LNA1 */
1545                                         div_ant_conf.main_lna_conf =
1546                                                 ATH_ANT_DIV_COMB_LNA2;
1547                                         div_ant_conf.alt_lna_conf =
1548                                                 ATH_ANT_DIV_COMB_LNA1;
1549                                 }
1550                         } else {
1551                                 /* use LNA1 as main LNA */
1552                                 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1553                                     (antcomb->rssi_add > antcomb->rssi_sub)) {
1554                                         /* set to A+B */
1555                                         div_ant_conf.main_lna_conf =
1556                                                 ATH_ANT_DIV_COMB_LNA1;
1557                                         div_ant_conf.alt_lna_conf  =
1558                                                 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1559                                 } else if (antcomb->rssi_sub >
1560                                            antcomb->rssi_lna1) {
1561                                         /* set to A-B */
1562                                         div_ant_conf.main_lna_conf =
1563                                                 ATH_ANT_DIV_COMB_LNA1;
1564                                         div_ant_conf.alt_lna_conf =
1565                                                 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1566                                 } else {
1567                                         /* set to LNA2 */
1568                                         div_ant_conf.main_lna_conf =
1569                                                 ATH_ANT_DIV_COMB_LNA1;
1570                                         div_ant_conf.alt_lna_conf =
1571                                                 ATH_ANT_DIV_COMB_LNA2;
1572                                 }
1573                         }
1574                         break;
1575                 default:
1576                         break;
1577                 }
1578         } else {
1579                 if (!antcomb->alt_good) {
1580                         antcomb->scan_not_start = false;
1581                         /* Set alt to another LNA */
1582                         if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1583                                 div_ant_conf.main_lna_conf =
1584                                                 ATH_ANT_DIV_COMB_LNA2;
1585                                 div_ant_conf.alt_lna_conf =
1586                                                 ATH_ANT_DIV_COMB_LNA1;
1587                         } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1588                                 div_ant_conf.main_lna_conf =
1589                                                 ATH_ANT_DIV_COMB_LNA1;
1590                                 div_ant_conf.alt_lna_conf =
1591                                                 ATH_ANT_DIV_COMB_LNA2;
1592                         }
1593                         goto div_comb_done;
1594                 }
1595         }
1596
1597         ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1598                                            main_rssi_avg, alt_rssi_avg,
1599                                            alt_ratio);
1600
1601         antcomb->quick_scan_cnt++;
1602
1603 div_comb_done:
1604         ath_ant_div_conf_fast_divbias(&div_ant_conf);
1605
1606         ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1607
1608         antcomb->scan_start_time = jiffies;
1609         antcomb->total_pkt_count = 0;
1610         antcomb->main_total_rssi = 0;
1611         antcomb->alt_total_rssi = 0;
1612         antcomb->main_recv_cnt = 0;
1613         antcomb->alt_recv_cnt = 0;
1614 }
1615
1616 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1617 {
1618         struct ath_buf *bf;
1619         struct sk_buff *skb = NULL, *requeue_skb;
1620         struct ieee80211_rx_status *rxs;
1621         struct ath_hw *ah = sc->sc_ah;
1622         struct ath_common *common = ath9k_hw_common(ah);
1623         /*
1624          * The hw can techncically differ from common->hw when using ath9k
1625          * virtual wiphy so to account for that we iterate over the active
1626          * wiphys and find the appropriate wiphy and therefore hw.
1627          */
1628         struct ieee80211_hw *hw = NULL;
1629         struct ieee80211_hdr *hdr;
1630         int retval;
1631         bool decrypt_error = false;
1632         struct ath_rx_status rs;
1633         enum ath9k_rx_qtype qtype;
1634         bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1635         int dma_type;
1636         u8 rx_status_len = ah->caps.rx_status_len;
1637         u64 tsf = 0;
1638         u32 tsf_lower = 0;
1639         unsigned long flags;
1640
1641         if (edma)
1642                 dma_type = DMA_BIDIRECTIONAL;
1643         else
1644                 dma_type = DMA_FROM_DEVICE;
1645
1646         qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1647         spin_lock_bh(&sc->rx.rxbuflock);
1648
1649         tsf = ath9k_hw_gettsf64(ah);
1650         tsf_lower = tsf & 0xffffffff;
1651
1652         do {
1653                 /* If handling rx interrupt and flush is in progress => exit */
1654                 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1655                         break;
1656
1657                 memset(&rs, 0, sizeof(rs));
1658                 if (edma)
1659                         bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1660                 else
1661                         bf = ath_get_next_rx_buf(sc, &rs);
1662
1663                 if (!bf)
1664                         break;
1665
1666                 skb = bf->bf_mpdu;
1667                 if (!skb)
1668                         continue;
1669
1670                 hdr = (struct ieee80211_hdr *) (skb->data + rx_status_len);
1671                 rxs =  IEEE80211_SKB_RXCB(skb);
1672
1673                 hw = ath_get_virt_hw(sc, hdr);
1674
1675                 ath_debug_stat_rx(sc, &rs);
1676
1677                 /*
1678                  * If we're asked to flush receive queue, directly
1679                  * chain it back at the queue without processing it.
1680                  */
1681                 if (flush)
1682                         goto requeue;
1683
1684                 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1685                                                  rxs, &decrypt_error);
1686                 if (retval)
1687                         goto requeue;
1688
1689                 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1690                 if (rs.rs_tstamp > tsf_lower &&
1691                     unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1692                         rxs->mactime -= 0x100000000ULL;
1693
1694                 if (rs.rs_tstamp < tsf_lower &&
1695                     unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1696                         rxs->mactime += 0x100000000ULL;
1697
1698                 /* Ensure we always have an skb to requeue once we are done
1699                  * processing the current buffer's skb */
1700                 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1701
1702                 /* If there is no memory we ignore the current RX'd frame,
1703                  * tell hardware it can give us a new frame using the old
1704                  * skb and put it at the tail of the sc->rx.rxbuf list for
1705                  * processing. */
1706                 if (!requeue_skb)
1707                         goto requeue;
1708
1709                 /* Unmap the frame */
1710                 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1711                                  common->rx_bufsize,
1712                                  dma_type);
1713
1714                 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1715                 if (ah->caps.rx_status_len)
1716                         skb_pull(skb, ah->caps.rx_status_len);
1717
1718                 ath9k_rx_skb_postprocess(common, skb, &rs,
1719                                          rxs, decrypt_error);
1720
1721                 /* We will now give hardware our shiny new allocated skb */
1722                 bf->bf_mpdu = requeue_skb;
1723                 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1724                                                  common->rx_bufsize,
1725                                                  dma_type);
1726                 if (unlikely(dma_mapping_error(sc->dev,
1727                           bf->bf_buf_addr))) {
1728                         dev_kfree_skb_any(requeue_skb);
1729                         bf->bf_mpdu = NULL;
1730                         bf->bf_buf_addr = 0;
1731                         ath_err(common, "dma_mapping_error() on RX\n");
1732                         ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1733                         break;
1734                 }
1735
1736                 /*
1737                  * change the default rx antenna if rx diversity chooses the
1738                  * other antenna 3 times in a row.
1739                  */
1740                 if (sc->rx.defant != rs.rs_antenna) {
1741                         if (++sc->rx.rxotherant >= 3)
1742                                 ath_setdefantenna(sc, rs.rs_antenna);
1743                 } else {
1744                         sc->rx.rxotherant = 0;
1745                 }
1746
1747                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1748
1749                 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1750                                               PS_WAIT_FOR_CAB |
1751                                               PS_WAIT_FOR_PSPOLL_DATA)) ||
1752                                         unlikely(ath9k_check_auto_sleep(sc)))
1753                         ath_rx_ps(sc, skb);
1754                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1755
1756                 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1757                         ath_ant_comb_scan(sc, &rs);
1758
1759                 ath_rx_send_to_mac80211(hw, sc, skb, rxs);
1760
1761 requeue:
1762                 if (edma) {
1763                         list_add_tail(&bf->list, &sc->rx.rxbuf);
1764                         ath_rx_edma_buf_link(sc, qtype);
1765                 } else {
1766                         list_move_tail(&bf->list, &sc->rx.rxbuf);
1767                         ath_rx_buf_link(sc, bf);
1768                 }
1769         } while (1);
1770
1771         spin_unlock_bh(&sc->rx.rxbuflock);
1772
1773         return 0;
1774 }