drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         const struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %d\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_FULL_RESET;
 291
 292         if (ath_startrecv(sc) != 0) {
 293                 DPRINTF(sc, ATH_DBG_FATAL,
 294                         "Unable to restart recv logic\n");
 295                 return -EIO;
 296         }
 297
 298         ath_cache_conf_rate(sc, &hw->conf);
 299         ath_update_txpow(sc);
 300         ath9k_hw_set_interrupts(ah, sc->imask);
 301         ath9k_ps_restore(sc);
 302         return 0;
 303 }
 304
 305 /*
 306  *  This routine performs the periodic noise floor calibration function
 307  *  that is used to adjust and optimize the chip performance.  This
 308  *  takes environmental changes (location, temperature) into account.
 309  *  When the task is complete, it reschedules itself depending on the
 310  *  appropriate interval that was calculated.
 311  */
 312 static void ath_ani_calibrate(unsigned long data)
 313 {
 314         struct ath_softc *sc = (struct ath_softc *)data;
 315         struct ath_hw *ah = sc->sc_ah;
 316         bool longcal = false;
 317         bool shortcal = false;
 318         bool aniflag = false;
 319         unsigned int timestamp = jiffies_to_msecs(jiffies);
 320         u32 cal_interval, short_cal_interval;
 321
 322         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 323                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 324
 325         /*
 326         * don't calibrate when we're scanning.
 327         * we are most likely not on our home channel.
 328         */
 329         if (sc->sc_flags & SC_OP_SCANNING)
 330                 goto set_timer;
 331
 332         /* Only calibrate if awake */
 333         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 334                 goto set_timer;
 335
 336         ath9k_ps_wakeup(sc);
 337
 338         /* Long calibration runs independently of short calibration. */
 339         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 340                 longcal = true;
 341                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 342                 sc->ani.longcal_timer = timestamp;
 343         }
 344
 345         /* Short calibration applies only while caldone is false */
 346         if (!sc->ani.caldone) {
 347                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 348                         shortcal = true;
 349                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 350                         sc->ani.shortcal_timer = timestamp;
 351                         sc->ani.resetcal_timer = timestamp;
 352                 }
 353         } else {
 354                 if ((timestamp - sc->ani.resetcal_timer) >=
 355                     ATH_RESTART_CALINTERVAL) {
 356                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 357                         if (sc->ani.caldone)
 358                                 sc->ani.resetcal_timer = timestamp;
 359                 }
 360         }
 361
 362         /* Verify whether we must check ANI */
 363         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 364                 aniflag = true;
 365                 sc->ani.checkani_timer = timestamp;
 366         }
 367
 368         /* Skip all processing if there's nothing to do. */
 369         if (longcal || shortcal || aniflag) {
 370                 /* Call ANI routine if necessary */
 371                 if (aniflag)
 372                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 373
 374                 /* Perform calibration if necessary */
 375                 if (longcal || shortcal) {
 376                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 377                                                      sc->rx_chainmask, longcal);
 378
 379                         if (longcal)
 380                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 381                                                                      ah->curchan);
 382
 383                         DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
 384                                 ah->curchan->channel, ah->curchan->channelFlags,
 385                                 sc->ani.noise_floor);
 386                 }
 387         }
 388
 389         ath9k_ps_restore(sc);
 390
 391 set_timer:
 392         /*
 393         * Set timer interval based on previous results.
 394         * The interval must be the shortest necessary to satisfy ANI,
 395         * short calibration and long calibration.
 396         */
 397         cal_interval = ATH_LONG_CALINTERVAL;
 398         if (sc->sc_ah->config.enable_ani)
 399                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 400         if (!sc->ani.caldone)
 401                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 402
 403         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 404 }
 405
 406 static void ath_start_ani(struct ath_softc *sc)
 407 {
 408         unsigned long timestamp = jiffies_to_msecs(jiffies);
 409
 410         sc->ani.longcal_timer = timestamp;
 411         sc->ani.shortcal_timer = timestamp;
 412         sc->ani.checkani_timer = timestamp;
 413
 414         mod_timer(&sc->ani.timer,
 415                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 416 }
 417
 418 /*
 419  * Update tx/rx chainmask. For legacy association,
 420  * hard code chainmask to 1x1, for 11n association, use
 421  * the chainmask configuration, for bt coexistence, use
 422  * the chainmask configuration even in legacy mode.
 423  */
 424 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 425 {
 426         if (is_ht ||
 427             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 428                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 429                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 430         } else {
 431                 sc->tx_chainmask = 1;
 432                 sc->rx_chainmask = 1;
 433         }
 434
 435         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 436                 sc->tx_chainmask, sc->rx_chainmask);
 437 }
 438
 439 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 440 {
 441         struct ath_node *an;
 442
 443         an = (struct ath_node *)sta->drv_priv;
 444
 445         if (sc->sc_flags & SC_OP_TXAGGR) {
 446                 ath_tx_node_init(sc, an);
 447                 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 448                                      sta->ht_cap.ampdu_factor);
 449                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 450         }
 451 }
 452
 453 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 454 {
 455         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 456
 457         if (sc->sc_flags & SC_OP_TXAGGR)
 458                 ath_tx_node_cleanup(sc, an);
 459 }
 460
 461 static void ath9k_tasklet(unsigned long data)
 462 {
 463         struct ath_softc *sc = (struct ath_softc *)data;
 464         u32 status = sc->intrstatus;
 465
 466         ath9k_ps_wakeup(sc);
 467
 468         if (status & ATH9K_INT_FATAL) {
 469                 ath_reset(sc, false);
 470                 ath9k_ps_restore(sc);
 471                 return;
 472         }
 473
 474         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 475                 spin_lock_bh(&sc->rx.rxflushlock);
 476                 ath_rx_tasklet(sc, 0);
 477                 spin_unlock_bh(&sc->rx.rxflushlock);
 478         }
 479
 480         if (status & ATH9K_INT_TX)
 481                 ath_tx_tasklet(sc);
 482
 483         if ((status & ATH9K_INT_TSFOOR) &&
 484             (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
 485                 /*
 486                  * TSF sync does not look correct; remain awake to sync with
 487                  * the next Beacon.
 488                  */
 489                 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
 490                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 491         }
 492
 493         /* re-enable hardware interrupt */
 494         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 495         ath9k_ps_restore(sc);
 496 }
 497
 498 irqreturn_t ath_isr(int irq, void *dev)
 499 {
 500 #define SCHED_INTR (                            \
 501                 ATH9K_INT_FATAL |               \
 502                 ATH9K_INT_RXORN |               \
 503                 ATH9K_INT_RXEOL |               \
 504                 ATH9K_INT_RX |                  \
 505                 ATH9K_INT_TX |                  \
 506                 ATH9K_INT_BMISS |               \
 507                 ATH9K_INT_CST |                 \
 508                 ATH9K_INT_TSFOOR)
 509
 510         struct ath_softc *sc = dev;
 511         struct ath_hw *ah = sc->sc_ah;
 512         enum ath9k_int status;
 513         bool sched = false;
 514
 515         /*
 516          * The hardware is not ready/present, don't
 517          * touch anything. Note this can happen early
 518          * on if the IRQ is shared.
 519          */
 520         if (sc->sc_flags & SC_OP_INVALID)
 521                 return IRQ_NONE;
 522
 523
 524         /* shared irq, not for us */
 525
 526         if (!ath9k_hw_intrpend(ah))
 527                 return IRQ_NONE;
 528
 529         /*
 530          * Figure out the reason(s) for the interrupt.  Note
 531          * that the hal returns a pseudo-ISR that may include
 532          * bits we haven't explicitly enabled so we mask the
 533          * value to insure we only process bits we requested.
 534          */
 535         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 536         status &= sc->imask;    /* discard unasked-for bits */
 537
 538         /*
 539          * If there are no status bits set, then this interrupt was not
 540          * for me (should have been caught above).
 541          */
 542         if (!status)
 543                 return IRQ_NONE;
 544
 545         /* Cache the status */
 546         sc->intrstatus = status;
 547
 548         if (status & SCHED_INTR)
 549                 sched = true;
 550
 551         /*
 552          * If a FATAL or RXORN interrupt is received, we have to reset the
 553          * chip immediately.
 554          */
 555         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 556                 goto chip_reset;
 557
 558         if (status & ATH9K_INT_SWBA)
 559                 tasklet_schedule(&sc->bcon_tasklet);
 560
 561         if (status & ATH9K_INT_TXURN)
 562                 ath9k_hw_updatetxtriglevel(ah, true);
 563
 564         if (status & ATH9K_INT_MIB) {
 565                 /*
 566                  * Disable interrupts until we service the MIB
 567                  * interrupt; otherwise it will continue to
 568                  * fire.
 569                  */
 570                 ath9k_hw_set_interrupts(ah, 0);
 571                 /*
 572                  * Let the hal handle the event. We assume
 573                  * it will clear whatever condition caused
 574                  * the interrupt.
 575                  */
 576                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 577                 ath9k_hw_set_interrupts(ah, sc->imask);
 578         }
 579
 580         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 581                 if (status & ATH9K_INT_TIM_TIMER) {
 582                         /* Clear RxAbort bit so that we can
 583                          * receive frames */
 584                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 585                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 586                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 587                 }
 588
 589 chip_reset:
 590
 591         ath_debug_stat_interrupt(sc, status);
 592
 593         if (sched) {
 594                 /* turn off every interrupt except SWBA */
 595                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 596                 tasklet_schedule(&sc->intr_tq);
 597         }
 598
 599         return IRQ_HANDLED;
 600
 601 #undef SCHED_INTR
 602 }
 603
 604 static u32 ath_get_extchanmode(struct ath_softc *sc,
 605                                struct ieee80211_channel *chan,
 606                                enum nl80211_channel_type channel_type)
 607 {
 608         u32 chanmode = 0;
 609
 610         switch (chan->band) {
 611         case IEEE80211_BAND_2GHZ:
 612                 switch(channel_type) {
 613                 case NL80211_CHAN_NO_HT:
 614                 case NL80211_CHAN_HT20:
 615                         chanmode = CHANNEL_G_HT20;
 616                         break;
 617                 case NL80211_CHAN_HT40PLUS:
 618                         chanmode = CHANNEL_G_HT40PLUS;
 619                         break;
 620                 case NL80211_CHAN_HT40MINUS:
 621                         chanmode = CHANNEL_G_HT40MINUS;
 622                         break;
 623                 }
 624                 break;
 625         case IEEE80211_BAND_5GHZ:
 626                 switch(channel_type) {
 627                 case NL80211_CHAN_NO_HT:
 628                 case NL80211_CHAN_HT20:
 629                         chanmode = CHANNEL_A_HT20;
 630                         break;
 631                 case NL80211_CHAN_HT40PLUS:
 632                         chanmode = CHANNEL_A_HT40PLUS;
 633                         break;
 634                 case NL80211_CHAN_HT40MINUS:
 635                         chanmode = CHANNEL_A_HT40MINUS;
 636                         break;
 637                 }
 638                 break;
 639         default:
 640                 break;
 641         }
 642
 643         return chanmode;
 644 }
 645
 646 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 647                            struct ath9k_keyval *hk, const u8 *addr,
 648                            bool authenticator)
 649 {
 650         const u8 *key_rxmic;
 651         const u8 *key_txmic;
 652
 653         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 654         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 655
 656         if (addr == NULL) {
 657                 /*
 658                  * Group key installation - only two key cache entries are used
 659                  * regardless of splitmic capability since group key is only
 660                  * used either for TX or RX.
 661                  */
 662                 if (authenticator) {
 663                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 664                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 665                 } else {
 666                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 667                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 668                 }
 669                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 670         }
 671         if (!sc->splitmic) {
 672                 /* TX and RX keys share the same key cache entry. */
 673                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 674                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 675                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 676         }
 677
 678         /* Separate key cache entries for TX and RX */
 679
 680         /* TX key goes at first index, RX key at +32. */
 681         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 682         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 683                 /* TX MIC entry failed. No need to proceed further */
 684                 DPRINTF(sc, ATH_DBG_FATAL,
 685                         "Setting TX MIC Key Failed\n");
 686                 return 0;
 687         }
 688
 689         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 690         /* XXX delete tx key on failure? */
 691         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 692 }
 693
 694 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 695 {
 696         int i;
 697
 698         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 699                 if (test_bit(i, sc->keymap) ||
 700                     test_bit(i + 64, sc->keymap))
 701                         continue; /* At least one part of TKIP key allocated */
 702                 if (sc->splitmic &&
 703                     (test_bit(i + 32, sc->keymap) ||
 704                      test_bit(i + 64 + 32, sc->keymap)))
 705                         continue; /* At least one part of TKIP key allocated */
 706
 707                 /* Found a free slot for a TKIP key */
 708                 return i;
 709         }
 710         return -1;
 711 }
 712
 713 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 714 {
 715         int i;
 716
 717         /* First, try to find slots that would not be available for TKIP. */
 718         if (sc->splitmic) {
 719                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 720                         if (!test_bit(i, sc->keymap) &&
 721                             (test_bit(i + 32, sc->keymap) ||
 722                              test_bit(i + 64, sc->keymap) ||
 723                              test_bit(i + 64 + 32, sc->keymap)))
 724                                 return i;
 725                         if (!test_bit(i + 32, sc->keymap) &&
 726                             (test_bit(i, sc->keymap) ||
 727                              test_bit(i + 64, sc->keymap) ||
 728                              test_bit(i + 64 + 32, sc->keymap)))
 729                                 return i + 32;
 730                         if (!test_bit(i + 64, sc->keymap) &&
 731                             (test_bit(i , sc->keymap) ||
 732                              test_bit(i + 32, sc->keymap) ||
 733                              test_bit(i + 64 + 32, sc->keymap)))
 734                                 return i + 64;
 735                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 736                             (test_bit(i, sc->keymap) ||
 737                              test_bit(i + 32, sc->keymap) ||
 738                              test_bit(i + 64, sc->keymap)))
 739                                 return i + 64 + 32;
 740                 }
 741         } else {
 742                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 743                         if (!test_bit(i, sc->keymap) &&
 744                             test_bit(i + 64, sc->keymap))
 745                                 return i;
 746                         if (test_bit(i, sc->keymap) &&
 747                             !test_bit(i + 64, sc->keymap))
 748                                 return i + 64;
 749                 }
 750         }
 751
 752         /* No partially used TKIP slots, pick any available slot */
 753         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 754                 /* Do not allow slots that could be needed for TKIP group keys
 755                  * to be used. This limitation could be removed if we know that
 756                  * TKIP will not be used. */
 757                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 758                         continue;
 759                 if (sc->splitmic) {
 760                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 761                                 continue;
 762                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 763                                 continue;
 764                 }
 765
 766                 if (!test_bit(i, sc->keymap))
 767                         return i; /* Found a free slot for a key */
 768         }
 769
 770         /* No free slot found */
 771         return -1;
 772 }
 773
 774 static int ath_key_config(struct ath_softc *sc,
 775                           struct ieee80211_vif *vif,
 776                           struct ieee80211_sta *sta,
 777                           struct ieee80211_key_conf *key)
 778 {
 779         struct ath9k_keyval hk;
 780         const u8 *mac = NULL;
 781         int ret = 0;
 782         int idx;
 783
 784         memset(&hk, 0, sizeof(hk));
 785
 786         switch (key->alg) {
 787         case ALG_WEP:
 788                 hk.kv_type = ATH9K_CIPHER_WEP;
 789                 break;
 790         case ALG_TKIP:
 791                 hk.kv_type = ATH9K_CIPHER_TKIP;
 792                 break;
 793         case ALG_CCMP:
 794                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 795                 break;
 796         default:
 797                 return -EOPNOTSUPP;
 798         }
 799
 800         hk.kv_len = key->keylen;
 801         memcpy(hk.kv_val, key->key, key->keylen);
 802
 803         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 804                 /* For now, use the default keys for broadcast keys. This may
 805                  * need to change with virtual interfaces. */
 806                 idx = key->keyidx;
 807         } else if (key->keyidx) {
 808                 if (WARN_ON(!sta))
 809                         return -EOPNOTSUPP;
 810                 mac = sta->addr;
 811
 812                 if (vif->type != NL80211_IFTYPE_AP) {
 813                         /* Only keyidx 0 should be used with unicast key, but
 814                          * allow this for client mode for now. */
 815                         idx = key->keyidx;
 816                 } else
 817                         return -EIO;
 818         } else {
 819                 if (WARN_ON(!sta))
 820                         return -EOPNOTSUPP;
 821                 mac = sta->addr;
 822
 823                 if (key->alg == ALG_TKIP)
 824                         idx = ath_reserve_key_cache_slot_tkip(sc);
 825                 else
 826                         idx = ath_reserve_key_cache_slot(sc);
 827                 if (idx < 0)
 828                         return -ENOSPC; /* no free key cache entries */
 829         }
 830
 831         if (key->alg == ALG_TKIP)
 832                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 833                                       vif->type == NL80211_IFTYPE_AP);
 834         else
 835                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 836
 837         if (!ret)
 838                 return -EIO;
 839
 840         set_bit(idx, sc->keymap);
 841         if (key->alg == ALG_TKIP) {
 842                 set_bit(idx + 64, sc->keymap);
 843                 if (sc->splitmic) {
 844                         set_bit(idx + 32, sc->keymap);
 845                         set_bit(idx + 64 + 32, sc->keymap);
 846                 }
 847         }
 848
 849         return idx;
 850 }
 851
 852 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 853 {
 854         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 855         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 856                 return;
 857
 858         clear_bit(key->hw_key_idx, sc->keymap);
 859         if (key->alg != ALG_TKIP)
 860                 return;
 861
 862         clear_bit(key->hw_key_idx + 64, sc->keymap);
 863         if (sc->splitmic) {
 864                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 865                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 866         }
 867 }
 868
 869 static void setup_ht_cap(struct ath_softc *sc,
 870                          struct ieee80211_sta_ht_cap *ht_info)
 871 {
 872 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 873 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 874
 875         ht_info->ht_supported = true;
 876         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 877                        IEEE80211_HT_CAP_SM_PS |
 878                        IEEE80211_HT_CAP_SGI_40 |
 879                        IEEE80211_HT_CAP_DSSSCCK40;
 880
 881         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 882         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 883
 884         /* set up supported mcs set */
 885         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 886
 887         switch(sc->rx_chainmask) {
 888         case 1:
 889                 ht_info->mcs.rx_mask[0] = 0xff;
 890                 break;
 891         case 3:
 892         case 5:
 893         case 7:
 894         default:
 895                 ht_info->mcs.rx_mask[0] = 0xff;
 896                 ht_info->mcs.rx_mask[1] = 0xff;
 897                 break;
 898         }
 899
 900         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 901 }
 902
 903 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 904                                  struct ieee80211_vif *vif,
 905                                  struct ieee80211_bss_conf *bss_conf)
 906 {
 907         struct ath_vif *avp = (void *)vif->drv_priv;
 908
 909         if (bss_conf->assoc) {
 910                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 911                         bss_conf->aid, sc->curbssid);
 912
 913                 /* New association, store aid */
 914                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 915                         sc->curaid = bss_conf->aid;
 916                         ath9k_hw_write_associd(sc);
 917                 }
 918
 919                 /* Configure the beacon */
 920                 ath_beacon_config(sc, vif);
 921
 922                 /* Reset rssi stats */
 923                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 924                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 925                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 926                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 927
 928                 ath_start_ani(sc);
 929         } else {
 930                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 931                 sc->curaid = 0;
 932         }
 933 }
 934
 935 /********************************/
 936 /*       LED functions          */
 937 /********************************/
 938
 939 static void ath_led_blink_work(struct work_struct *work)
 940 {
 941         struct ath_softc *sc = container_of(work, struct ath_softc,
 942                                             ath_led_blink_work.work);
 943
 944         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 945                 return;
 946
 947         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 948             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 949                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 950         else
 951                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 952                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 953
 954         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 955                            (sc->sc_flags & SC_OP_LED_ON) ?
 956                            msecs_to_jiffies(sc->led_off_duration) :
 957                            msecs_to_jiffies(sc->led_on_duration));
 958
 959         sc->led_on_duration = sc->led_on_cnt ?
 960                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 961                         ATH_LED_ON_DURATION_IDLE;
 962         sc->led_off_duration = sc->led_off_cnt ?
 963                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 964                         ATH_LED_OFF_DURATION_IDLE;
 965         sc->led_on_cnt = sc->led_off_cnt = 0;
 966         if (sc->sc_flags & SC_OP_LED_ON)
 967                 sc->sc_flags &= ~SC_OP_LED_ON;
 968         else
 969                 sc->sc_flags |= SC_OP_LED_ON;
 970 }
 971
 972 static void ath_led_brightness(struct led_classdev *led_cdev,
 973                                enum led_brightness brightness)
 974 {
 975         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 976         struct ath_softc *sc = led->sc;
 977
 978         switch (brightness) {
 979         case LED_OFF:
 980                 if (led->led_type == ATH_LED_ASSOC ||
 981                     led->led_type == ATH_LED_RADIO) {
 982                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 983                                 (led->led_type == ATH_LED_RADIO));
 984                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 985                         if (led->led_type == ATH_LED_RADIO)
 986                                 sc->sc_flags &= ~SC_OP_LED_ON;
 987                 } else {
 988                         sc->led_off_cnt++;
 989                 }
 990                 break;
 991         case LED_FULL:
 992                 if (led->led_type == ATH_LED_ASSOC) {
 993                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 994                         queue_delayed_work(sc->hw->workqueue,
 995                                            &sc->ath_led_blink_work, 0);
 996                 } else if (led->led_type == ATH_LED_RADIO) {
 997                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 998                         sc->sc_flags |= SC_OP_LED_ON;
 999                 } else {
1000                         sc->led_on_cnt++;
1001                 }
1002                 break;
1003         default:
1004                 break;
1005         }
1006 }
1007
1008 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1009                             char *trigger)
1010 {
1011         int ret;
1012
1013         led->sc = sc;
1014         led->led_cdev.name = led->name;
1015         led->led_cdev.default_trigger = trigger;
1016         led->led_cdev.brightness_set = ath_led_brightness;
1017
1018         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1019         if (ret)
1020                 DPRINTF(sc, ATH_DBG_FATAL,
1021                         "Failed to register led:%s", led->name);
1022         else
1023                 led->registered = 1;
1024         return ret;
1025 }
1026
1027 static void ath_unregister_led(struct ath_led *led)
1028 {
1029         if (led->registered) {
1030                 led_classdev_unregister(&led->led_cdev);
1031                 led->registered = 0;
1032         }
1033 }
1034
1035 static void ath_deinit_leds(struct ath_softc *sc)
1036 {
1037         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1038         ath_unregister_led(&sc->assoc_led);
1039         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1040         ath_unregister_led(&sc->tx_led);
1041         ath_unregister_led(&sc->rx_led);
1042         ath_unregister_led(&sc->radio_led);
1043         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1044 }
1045
1046 static void ath_init_leds(struct ath_softc *sc)
1047 {
1048         char *trigger;
1049         int ret;
1050
1051         /* Configure gpio 1 for output */
1052         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1053                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1054         /* LED off, active low */
1055         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1056
1057         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1058
1059         trigger = ieee80211_get_radio_led_name(sc->hw);
1060         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1061                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1062         ret = ath_register_led(sc, &sc->radio_led, trigger);
1063         sc->radio_led.led_type = ATH_LED_RADIO;
1064         if (ret)
1065                 goto fail;
1066
1067         trigger = ieee80211_get_assoc_led_name(sc->hw);
1068         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1069                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1070         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1071         sc->assoc_led.led_type = ATH_LED_ASSOC;
1072         if (ret)
1073                 goto fail;
1074
1075         trigger = ieee80211_get_tx_led_name(sc->hw);
1076         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1077                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1078         ret = ath_register_led(sc, &sc->tx_led, trigger);
1079         sc->tx_led.led_type = ATH_LED_TX;
1080         if (ret)
1081                 goto fail;
1082
1083         trigger = ieee80211_get_rx_led_name(sc->hw);
1084         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1085                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1086         ret = ath_register_led(sc, &sc->rx_led, trigger);
1087         sc->rx_led.led_type = ATH_LED_RX;
1088         if (ret)
1089                 goto fail;
1090
1091         return;
1092
1093 fail:
1094         ath_deinit_leds(sc);
1095 }
1096
1097 void ath_radio_enable(struct ath_softc *sc)
1098 {
1099         struct ath_hw *ah = sc->sc_ah;
1100         struct ieee80211_channel *channel = sc->hw->conf.channel;
1101         int r;
1102
1103         ath9k_ps_wakeup(sc);
1104         ath9k_hw_configpcipowersave(ah, 0);
1105
1106         spin_lock_bh(&sc->sc_resetlock);
1107         r = ath9k_hw_reset(ah, ah->curchan, false);
1108         if (r) {
1109                 DPRINTF(sc, ATH_DBG_FATAL,
1110                         "Unable to reset channel %u (%uMhz) ",
1111                         "reset status %d\n",
1112                         channel->center_freq, r);
1113         }
1114         spin_unlock_bh(&sc->sc_resetlock);
1115
1116         ath_update_txpow(sc);
1117         if (ath_startrecv(sc) != 0) {
1118                 DPRINTF(sc, ATH_DBG_FATAL,
1119                         "Unable to restart recv logic\n");
1120                 return;
1121         }
1122
1123         if (sc->sc_flags & SC_OP_BEACONS)
1124                 ath_beacon_config(sc, NULL);    /* restart beacons */
1125
1126         /* Re-Enable  interrupts */
1127         ath9k_hw_set_interrupts(ah, sc->imask);
1128
1129         /* Enable LED */
1130         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1131                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1132         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1133
1134         ieee80211_wake_queues(sc->hw);
1135         ath9k_ps_restore(sc);
1136 }
1137
1138 void ath_radio_disable(struct ath_softc *sc)
1139 {
1140         struct ath_hw *ah = sc->sc_ah;
1141         struct ieee80211_channel *channel = sc->hw->conf.channel;
1142         int r;
1143
1144         ath9k_ps_wakeup(sc);
1145         ieee80211_stop_queues(sc->hw);
1146
1147         /* Disable LED */
1148         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1149         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1150
1151         /* Disable interrupts */
1152         ath9k_hw_set_interrupts(ah, 0);
1153
1154         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1155         ath_stoprecv(sc);               /* turn off frame recv */
1156         ath_flushrecv(sc);              /* flush recv queue */
1157
1158         spin_lock_bh(&sc->sc_resetlock);
1159         r = ath9k_hw_reset(ah, ah->curchan, false);
1160         if (r) {
1161                 DPRINTF(sc, ATH_DBG_FATAL,
1162                         "Unable to reset channel %u (%uMhz) "
1163                         "reset status %d\n",
1164                         channel->center_freq, r);
1165         }
1166         spin_unlock_bh(&sc->sc_resetlock);
1167
1168         ath9k_hw_phy_disable(ah);
1169         ath9k_hw_configpcipowersave(ah, 1);
1170         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1171         ath9k_ps_restore(sc);
1172 }
1173
1174 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1175
1176 /*******************/
1177 /*      Rfkill     */
1178 /*******************/
1179
1180 static bool ath_is_rfkill_set(struct ath_softc *sc)
1181 {
1182         struct ath_hw *ah = sc->sc_ah;
1183
1184         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1185                                   ah->rfkill_polarity;
1186 }
1187
1188 /* h/w rfkill poll function */
1189 static void ath_rfkill_poll(struct work_struct *work)
1190 {
1191         struct ath_softc *sc = container_of(work, struct ath_softc,
1192                                             rf_kill.rfkill_poll.work);
1193         bool radio_on;
1194
1195         if (sc->sc_flags & SC_OP_INVALID)
1196                 return;
1197
1198         radio_on = !ath_is_rfkill_set(sc);
1199
1200         /*
1201          * enable/disable radio only when there is a
1202          * state change in RF switch
1203          */
1204         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1205                 enum rfkill_state state;
1206
1207                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1208                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1209                                 : RFKILL_STATE_HARD_BLOCKED;
1210                 } else if (radio_on) {
1211                         ath_radio_enable(sc);
1212                         state = RFKILL_STATE_UNBLOCKED;
1213                 } else {
1214                         ath_radio_disable(sc);
1215                         state = RFKILL_STATE_HARD_BLOCKED;
1216                 }
1217
1218                 if (state == RFKILL_STATE_HARD_BLOCKED)
1219                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1220                 else
1221                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1222
1223                 rfkill_force_state(sc->rf_kill.rfkill, state);
1224         }
1225
1226         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1227                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1228 }
1229
1230 /* s/w rfkill handler */
1231 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1232 {
1233         struct ath_softc *sc = data;
1234
1235         switch (state) {
1236         case RFKILL_STATE_SOFT_BLOCKED:
1237                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1238                     SC_OP_RFKILL_SW_BLOCKED)))
1239                         ath_radio_disable(sc);
1240                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1241                 return 0;
1242         case RFKILL_STATE_UNBLOCKED:
1243                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1244                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1245                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1246                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1247                                         "radio as it is disabled by h/w\n");
1248                                 return -EPERM;
1249                         }
1250                         ath_radio_enable(sc);
1251                 }
1252                 return 0;
1253         default:
1254                 return -EINVAL;
1255         }
1256 }
1257
1258 /* Init s/w rfkill */
1259 static int ath_init_sw_rfkill(struct ath_softc *sc)
1260 {
1261         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1262                                              RFKILL_TYPE_WLAN);
1263         if (!sc->rf_kill.rfkill) {
1264                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1265                 return -ENOMEM;
1266         }
1267
1268         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1269                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1270         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1271         sc->rf_kill.rfkill->data = sc;
1272         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1273         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1274
1275         return 0;
1276 }
1277
1278 /* Deinitialize rfkill */
1279 static void ath_deinit_rfkill(struct ath_softc *sc)
1280 {
1281         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1282                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1283
1284         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1285                 rfkill_unregister(sc->rf_kill.rfkill);
1286                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1287                 sc->rf_kill.rfkill = NULL;
1288         }
1289 }
1290
1291 static int ath_start_rfkill_poll(struct ath_softc *sc)
1292 {
1293         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1294                 queue_delayed_work(sc->hw->workqueue,
1295                                    &sc->rf_kill.rfkill_poll, 0);
1296
1297         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1298                 if (rfkill_register(sc->rf_kill.rfkill)) {
1299                         DPRINTF(sc, ATH_DBG_FATAL,
1300                                 "Unable to register rfkill\n");
1301                         rfkill_free(sc->rf_kill.rfkill);
1302
1303                         /* Deinitialize the device */
1304                         ath_cleanup(sc);
1305                         return -EIO;
1306                 } else {
1307                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1308                 }
1309         }
1310
1311         return 0;
1312 }
1313 #endif /* CONFIG_RFKILL */
1314
1315 void ath_cleanup(struct ath_softc *sc)
1316 {
1317         ath_detach(sc);
1318         free_irq(sc->irq, sc);
1319         ath_bus_cleanup(sc);
1320         kfree(sc->sec_wiphy);
1321         ieee80211_free_hw(sc->hw);
1322 }
1323
1324 void ath_detach(struct ath_softc *sc)
1325 {
1326         struct ieee80211_hw *hw = sc->hw;
1327         int i = 0;
1328
1329         ath9k_ps_wakeup(sc);
1330
1331         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1332
1333 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1334         ath_deinit_rfkill(sc);
1335 #endif
1336         ath_deinit_leds(sc);
1337         cancel_work_sync(&sc->chan_work);
1338         cancel_delayed_work_sync(&sc->wiphy_work);
1339
1340         for (i = 0; i < sc->num_sec_wiphy; i++) {
1341                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1342                 if (aphy == NULL)
1343                         continue;
1344                 sc->sec_wiphy[i] = NULL;
1345                 ieee80211_unregister_hw(aphy->hw);
1346                 ieee80211_free_hw(aphy->hw);
1347         }
1348         ieee80211_unregister_hw(hw);
1349         ath_rx_cleanup(sc);
1350         ath_tx_cleanup(sc);
1351
1352         tasklet_kill(&sc->intr_tq);
1353         tasklet_kill(&sc->bcon_tasklet);
1354
1355         if (!(sc->sc_flags & SC_OP_INVALID))
1356                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1357
1358         /* cleanup tx queues */
1359         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1360                 if (ATH_TXQ_SETUP(sc, i))
1361                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1362
1363         ath9k_hw_detach(sc->sc_ah);
1364         ath9k_exit_debug(sc);
1365         ath9k_ps_restore(sc);
1366 }
1367
1368 static int ath9k_reg_notifier(struct wiphy *wiphy,
1369                               struct regulatory_request *request)
1370 {
1371         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1372         struct ath_wiphy *aphy = hw->priv;
1373         struct ath_softc *sc = aphy->sc;
1374         struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1375
1376         return ath_reg_notifier_apply(wiphy, request, reg);
1377 }
1378
1379 static int ath_init(u16 devid, struct ath_softc *sc)
1380 {
1381         struct ath_hw *ah = NULL;
1382         int status;
1383         int error = 0, i;
1384         int csz = 0;
1385
1386         /* XXX: hardware will not be ready until ath_open() being called */
1387         sc->sc_flags |= SC_OP_INVALID;
1388
1389         if (ath9k_init_debug(sc) < 0)
1390                 printk(KERN_ERR "Unable to create debugfs files\n");
1391
1392         spin_lock_init(&sc->wiphy_lock);
1393         spin_lock_init(&sc->sc_resetlock);
1394         spin_lock_init(&sc->sc_serial_rw);
1395         mutex_init(&sc->mutex);
1396         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1397         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1398                      (unsigned long)sc);
1399
1400         /*
1401          * Cache line size is used to size and align various
1402          * structures used to communicate with the hardware.
1403          */
1404         ath_read_cachesize(sc, &csz);
1405         /* XXX assert csz is non-zero */
1406         sc->cachelsz = csz << 2;        /* convert to bytes */
1407
1408         ah = ath9k_hw_attach(devid, sc, &status);
1409         if (ah == NULL) {
1410                 DPRINTF(sc, ATH_DBG_FATAL,
1411                         "Unable to attach hardware; HAL status %d\n", status);
1412                 error = -ENXIO;
1413                 goto bad;
1414         }
1415         sc->sc_ah = ah;
1416
1417         /* Get the hardware key cache size. */
1418         sc->keymax = ah->caps.keycache_size;
1419         if (sc->keymax > ATH_KEYMAX) {
1420                 DPRINTF(sc, ATH_DBG_ANY,
1421                         "Warning, using only %u entries in %u key cache\n",
1422                         ATH_KEYMAX, sc->keymax);
1423                 sc->keymax = ATH_KEYMAX;
1424         }
1425
1426         /*
1427          * Reset the key cache since some parts do not
1428          * reset the contents on initial power up.
1429          */
1430         for (i = 0; i < sc->keymax; i++)
1431                 ath9k_hw_keyreset(ah, (u16) i);
1432
1433         error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1434                               ath9k_reg_notifier);
1435         if (error)
1436                 goto bad;
1437
1438         /* default to MONITOR mode */
1439         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1440
1441         /* Setup rate tables */
1442
1443         ath_rate_attach(sc);
1444         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1445         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1446
1447         /*
1448          * Allocate hardware transmit queues: one queue for
1449          * beacon frames and one data queue for each QoS
1450          * priority.  Note that the hal handles reseting
1451          * these queues at the needed time.
1452          */
1453         sc->beacon.beaconq = ath_beaconq_setup(ah);
1454         if (sc->beacon.beaconq == -1) {
1455                 DPRINTF(sc, ATH_DBG_FATAL,
1456                         "Unable to setup a beacon xmit queue\n");
1457                 error = -EIO;
1458                 goto bad2;
1459         }
1460         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1461         if (sc->beacon.cabq == NULL) {
1462                 DPRINTF(sc, ATH_DBG_FATAL,
1463                         "Unable to setup CAB xmit queue\n");
1464                 error = -EIO;
1465                 goto bad2;
1466         }
1467
1468         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1469         ath_cabq_update(sc);
1470
1471         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1472                 sc->tx.hwq_map[i] = -1;
1473
1474         /* Setup data queues */
1475         /* NB: ensure BK queue is the lowest priority h/w queue */
1476         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1477                 DPRINTF(sc, ATH_DBG_FATAL,
1478                         "Unable to setup xmit queue for BK traffic\n");
1479                 error = -EIO;
1480                 goto bad2;
1481         }
1482
1483         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1484                 DPRINTF(sc, ATH_DBG_FATAL,
1485                         "Unable to setup xmit queue for BE traffic\n");
1486                 error = -EIO;
1487                 goto bad2;
1488         }
1489         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1490                 DPRINTF(sc, ATH_DBG_FATAL,
1491                         "Unable to setup xmit queue for VI traffic\n");
1492                 error = -EIO;
1493                 goto bad2;
1494         }
1495         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1496                 DPRINTF(sc, ATH_DBG_FATAL,
1497                         "Unable to setup xmit queue for VO traffic\n");
1498                 error = -EIO;
1499                 goto bad2;
1500         }
1501
1502         /* Initializes the noise floor to a reasonable default value.
1503          * Later on this will be updated during ANI processing. */
1504
1505         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1506         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1507
1508         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1509                                    ATH9K_CIPHER_TKIP, NULL)) {
1510                 /*
1511                  * Whether we should enable h/w TKIP MIC.
1512                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1513                  * report WMM capable, so it's always safe to turn on
1514                  * TKIP MIC in this case.
1515                  */
1516                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1517                                        0, 1, NULL);
1518         }
1519
1520         /*
1521          * Check whether the separate key cache entries
1522          * are required to handle both tx+rx MIC keys.
1523          * With split mic keys the number of stations is limited
1524          * to 27 otherwise 59.
1525          */
1526         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1527                                    ATH9K_CIPHER_TKIP, NULL)
1528             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1529                                       ATH9K_CIPHER_MIC, NULL)
1530             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1531                                       0, NULL))
1532                 sc->splitmic = 1;
1533
1534         /* turn on mcast key search if possible */
1535         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1536                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1537                                              1, NULL);
1538
1539         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1540
1541         /* 11n Capabilities */
1542         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1543                 sc->sc_flags |= SC_OP_TXAGGR;
1544                 sc->sc_flags |= SC_OP_RXAGGR;
1545         }
1546
1547         sc->tx_chainmask = ah->caps.tx_chainmask;
1548         sc->rx_chainmask = ah->caps.rx_chainmask;
1549
1550         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1551         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1552
1553         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1554                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1555
1556         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1557
1558         /* initialize beacon slots */
1559         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1560                 sc->beacon.bslot[i] = NULL;
1561                 sc->beacon.bslot_aphy[i] = NULL;
1562         }
1563
1564         /* setup channels and rates */
1565
1566         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1567         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1568                 sc->rates[IEEE80211_BAND_2GHZ];
1569         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1570         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1571                 ARRAY_SIZE(ath9k_2ghz_chantable);
1572
1573         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1574                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1575                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1576                         sc->rates[IEEE80211_BAND_5GHZ];
1577                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1578                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1579                         ARRAY_SIZE(ath9k_5ghz_chantable);
1580         }
1581
1582         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1583                 ath9k_hw_btcoex_enable(sc->sc_ah);
1584
1585         return 0;
1586 bad2:
1587         /* cleanup tx queues */
1588         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1589                 if (ATH_TXQ_SETUP(sc, i))
1590                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1591 bad:
1592         if (ah)
1593                 ath9k_hw_detach(ah);
1594         ath9k_exit_debug(sc);
1595
1596         return error;
1597 }
1598
1599 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1600 {
1601         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1602                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1603                 IEEE80211_HW_SIGNAL_DBM |
1604                 IEEE80211_HW_AMPDU_AGGREGATION |
1605                 IEEE80211_HW_SUPPORTS_PS |
1606                 IEEE80211_HW_PS_NULLFUNC_STACK |
1607                 IEEE80211_HW_SPECTRUM_MGMT;
1608
1609         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1610                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1611
1612         hw->wiphy->interface_modes =
1613                 BIT(NL80211_IFTYPE_AP) |
1614                 BIT(NL80211_IFTYPE_STATION) |
1615                 BIT(NL80211_IFTYPE_ADHOC) |
1616                 BIT(NL80211_IFTYPE_MESH_POINT);
1617
1618         hw->queues = 4;
1619         hw->max_rates = 4;
1620         hw->channel_change_time = 5000;
1621         hw->max_listen_interval = 10;
1622         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1623         hw->sta_data_size = sizeof(struct ath_node);
1624         hw->vif_data_size = sizeof(struct ath_vif);
1625
1626         hw->rate_control_algorithm = "ath9k_rate_control";
1627
1628         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1629                 &sc->sbands[IEEE80211_BAND_2GHZ];
1630         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1631                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1632                         &sc->sbands[IEEE80211_BAND_5GHZ];
1633 }
1634
1635 int ath_attach(u16 devid, struct ath_softc *sc)
1636 {
1637         struct ieee80211_hw *hw = sc->hw;
1638         int error = 0, i;
1639         struct ath_regulatory *reg;
1640
1641         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1642
1643         error = ath_init(devid, sc);
1644         if (error != 0)
1645                 return error;
1646
1647         reg = &sc->sc_ah->regulatory;
1648
1649         /* get mac address from hardware and set in mac80211 */
1650
1651         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1652
1653         ath_set_hw_capab(sc, hw);
1654
1655         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1656                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1657                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1658                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1659         }
1660
1661         /* initialize tx/rx engine */
1662         error = ath_tx_init(sc, ATH_TXBUF);
1663         if (error != 0)
1664                 goto error_attach;
1665
1666         error = ath_rx_init(sc, ATH_RXBUF);
1667         if (error != 0)
1668                 goto error_attach;
1669
1670 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1671         /* Initialze h/w Rfkill */
1672         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1673                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1674
1675         /* Initialize s/w rfkill */
1676         error = ath_init_sw_rfkill(sc);
1677         if (error)
1678                 goto error_attach;
1679 #endif
1680
1681         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1682         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1683         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1684
1685         error = ieee80211_register_hw(hw);
1686
1687         if (!ath_is_world_regd(reg)) {
1688                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1689                 if (error)
1690                         goto error_attach;
1691         }
1692
1693         /* Initialize LED control */
1694         ath_init_leds(sc);
1695
1696
1697         return 0;
1698
1699 error_attach:
1700         /* cleanup tx queues */
1701         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1702                 if (ATH_TXQ_SETUP(sc, i))
1703                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1704
1705         ath9k_hw_detach(sc->sc_ah);
1706         ath9k_exit_debug(sc);
1707
1708         return error;
1709 }
1710
1711 int ath_reset(struct ath_softc *sc, bool retry_tx)
1712 {
1713         struct ath_hw *ah = sc->sc_ah;
1714         struct ieee80211_hw *hw = sc->hw;
1715         int r;
1716
1717         ath9k_hw_set_interrupts(ah, 0);
1718         ath_drain_all_txq(sc, retry_tx);
1719         ath_stoprecv(sc);
1720         ath_flushrecv(sc);
1721
1722         spin_lock_bh(&sc->sc_resetlock);
1723         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1724         if (r)
1725                 DPRINTF(sc, ATH_DBG_FATAL,
1726                         "Unable to reset hardware; reset status %d\n", r);
1727         spin_unlock_bh(&sc->sc_resetlock);
1728
1729         if (ath_startrecv(sc) != 0)
1730                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1731
1732         /*
1733          * We may be doing a reset in response to a request
1734          * that changes the channel so update any state that
1735          * might change as a result.
1736          */
1737         ath_cache_conf_rate(sc, &hw->conf);
1738
1739         ath_update_txpow(sc);
1740
1741         if (sc->sc_flags & SC_OP_BEACONS)
1742                 ath_beacon_config(sc, NULL);    /* restart beacons */
1743
1744         ath9k_hw_set_interrupts(ah, sc->imask);
1745
1746         if (retry_tx) {
1747                 int i;
1748                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1749                         if (ATH_TXQ_SETUP(sc, i)) {
1750                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1751                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1752                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1753                         }
1754                 }
1755         }
1756
1757         return r;
1758 }
1759
1760 /*
1761  *  This function will allocate both the DMA descriptor structure, and the
1762  *  buffers it contains.  These are used to contain the descriptors used
1763  *  by the system.
1764 */
1765 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1766                       struct list_head *head, const char *name,
1767                       int nbuf, int ndesc)
1768 {
1769 #define DS2PHYS(_dd, _ds)                                               \
1770         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1771 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1772 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1773
1774         struct ath_desc *ds;
1775         struct ath_buf *bf;
1776         int i, bsize, error;
1777
1778         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1779                 name, nbuf, ndesc);
1780
1781         INIT_LIST_HEAD(head);
1782         /* ath_desc must be a multiple of DWORDs */
1783         if ((sizeof(struct ath_desc) % 4) != 0) {
1784                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1785                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1786                 error = -ENOMEM;
1787                 goto fail;
1788         }
1789
1790         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1791
1792         /*
1793          * Need additional DMA memory because we can't use
1794          * descriptors that cross the 4K page boundary. Assume
1795          * one skipped descriptor per 4K page.
1796          */
1797         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1798                 u32 ndesc_skipped =
1799                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1800                 u32 dma_len;
1801
1802                 while (ndesc_skipped) {
1803                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1804                         dd->dd_desc_len += dma_len;
1805
1806                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1807                 };
1808         }
1809
1810         /* allocate descriptors */
1811         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1812                                          &dd->dd_desc_paddr, GFP_KERNEL);
1813         if (dd->dd_desc == NULL) {
1814                 error = -ENOMEM;
1815                 goto fail;
1816         }
1817         ds = dd->dd_desc;
1818         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1819                 name, ds, (u32) dd->dd_desc_len,
1820                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1821
1822         /* allocate buffers */
1823         bsize = sizeof(struct ath_buf) * nbuf;
1824         bf = kzalloc(bsize, GFP_KERNEL);
1825         if (bf == NULL) {
1826                 error = -ENOMEM;
1827                 goto fail2;
1828         }
1829         dd->dd_bufptr = bf;
1830
1831         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1832                 bf->bf_desc = ds;
1833                 bf->bf_daddr = DS2PHYS(dd, ds);
1834
1835                 if (!(sc->sc_ah->caps.hw_caps &
1836                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1837                         /*
1838                          * Skip descriptor addresses which can cause 4KB
1839                          * boundary crossing (addr + length) with a 32 dword
1840                          * descriptor fetch.
1841                          */
1842                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1843                                 ASSERT((caddr_t) bf->bf_desc <
1844                                        ((caddr_t) dd->dd_desc +
1845                                         dd->dd_desc_len));
1846
1847                                 ds += ndesc;
1848                                 bf->bf_desc = ds;
1849                                 bf->bf_daddr = DS2PHYS(dd, ds);
1850                         }
1851                 }
1852                 list_add_tail(&bf->list, head);
1853         }
1854         return 0;
1855 fail2:
1856         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1857                           dd->dd_desc_paddr);
1858 fail:
1859         memset(dd, 0, sizeof(*dd));
1860         return error;
1861 #undef ATH_DESC_4KB_BOUND_CHECK
1862 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1863 #undef DS2PHYS
1864 }
1865
1866 void ath_descdma_cleanup(struct ath_softc *sc,
1867                          struct ath_descdma *dd,
1868                          struct list_head *head)
1869 {
1870         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1871                           dd->dd_desc_paddr);
1872
1873         INIT_LIST_HEAD(head);
1874         kfree(dd->dd_bufptr);
1875         memset(dd, 0, sizeof(*dd));
1876 }
1877
1878 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1879 {
1880         int qnum;
1881
1882         switch (queue) {
1883         case 0:
1884                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1885                 break;
1886         case 1:
1887                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1888                 break;
1889         case 2:
1890                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1891                 break;
1892         case 3:
1893                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1894                 break;
1895         default:
1896                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1897                 break;
1898         }
1899
1900         return qnum;
1901 }
1902
1903 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1904 {
1905         int qnum;
1906
1907         switch (queue) {
1908         case ATH9K_WME_AC_VO:
1909                 qnum = 0;
1910                 break;
1911         case ATH9K_WME_AC_VI:
1912                 qnum = 1;
1913                 break;
1914         case ATH9K_WME_AC_BE:
1915                 qnum = 2;
1916                 break;
1917         case ATH9K_WME_AC_BK:
1918                 qnum = 3;
1919                 break;
1920         default:
1921                 qnum = -1;
1922                 break;
1923         }
1924
1925         return qnum;
1926 }
1927
1928 /* XXX: Remove me once we don't depend on ath9k_channel for all
1929  * this redundant data */
1930 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1931                            struct ath9k_channel *ichan)
1932 {
1933         struct ieee80211_channel *chan = hw->conf.channel;
1934         struct ieee80211_conf *conf = &hw->conf;
1935
1936         ichan->channel = chan->center_freq;
1937         ichan->chan = chan;
1938
1939         if (chan->band == IEEE80211_BAND_2GHZ) {
1940                 ichan->chanmode = CHANNEL_G;
1941                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1942         } else {
1943                 ichan->chanmode = CHANNEL_A;
1944                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1945         }
1946
1947         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1948
1949         if (conf_is_ht(conf)) {
1950                 if (conf_is_ht40(conf))
1951                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1952
1953                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1954                                             conf->channel_type);
1955         }
1956 }
1957
1958 /**********************/
1959 /* mac80211 callbacks */
1960 /**********************/
1961
1962 static int ath9k_start(struct ieee80211_hw *hw)
1963 {
1964         struct ath_wiphy *aphy = hw->priv;
1965         struct ath_softc *sc = aphy->sc;
1966         struct ieee80211_channel *curchan = hw->conf.channel;
1967         struct ath9k_channel *init_channel;
1968         int r, pos;
1969
1970         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1971                 "initial channel: %d MHz\n", curchan->center_freq);
1972
1973         mutex_lock(&sc->mutex);
1974
1975         if (ath9k_wiphy_started(sc)) {
1976                 if (sc->chan_idx == curchan->hw_value) {
1977                         /*
1978                          * Already on the operational channel, the new wiphy
1979                          * can be marked active.
1980                          */
1981                         aphy->state = ATH_WIPHY_ACTIVE;
1982                         ieee80211_wake_queues(hw);
1983                 } else {
1984                         /*
1985                          * Another wiphy is on another channel, start the new
1986                          * wiphy in paused state.
1987                          */
1988                         aphy->state = ATH_WIPHY_PAUSED;
1989                         ieee80211_stop_queues(hw);
1990                 }
1991                 mutex_unlock(&sc->mutex);
1992                 return 0;
1993         }
1994         aphy->state = ATH_WIPHY_ACTIVE;
1995
1996         /* setup initial channel */
1997
1998         pos = curchan->hw_value;
1999
2000         sc->chan_idx = pos;
2001         init_channel = &sc->sc_ah->channels[pos];
2002         ath9k_update_ichannel(sc, hw, init_channel);
2003
2004         /* Reset SERDES registers */
2005         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2006
2007         /*
2008          * The basic interface to setting the hardware in a good
2009          * state is ``reset''.  On return the hardware is known to
2010          * be powered up and with interrupts disabled.  This must
2011          * be followed by initialization of the appropriate bits
2012          * and then setup of the interrupt mask.
2013          */
2014         spin_lock_bh(&sc->sc_resetlock);
2015         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2016         if (r) {
2017                 DPRINTF(sc, ATH_DBG_FATAL,
2018                         "Unable to reset hardware; reset status %d "
2019                         "(freq %u MHz)\n", r,
2020                         curchan->center_freq);
2021                 spin_unlock_bh(&sc->sc_resetlock);
2022                 goto mutex_unlock;
2023         }
2024         spin_unlock_bh(&sc->sc_resetlock);
2025
2026         /*
2027          * This is needed only to setup initial state
2028          * but it's best done after a reset.
2029          */
2030         ath_update_txpow(sc);
2031
2032         /*
2033          * Setup the hardware after reset:
2034          * The receive engine is set going.
2035          * Frame transmit is handled entirely
2036          * in the frame output path; there's nothing to do
2037          * here except setup the interrupt mask.
2038          */
2039         if (ath_startrecv(sc) != 0) {
2040                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
2041                 r = -EIO;
2042                 goto mutex_unlock;
2043         }
2044
2045         /* Setup our intr mask. */
2046         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2047                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2048                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2049
2050         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2051                 sc->imask |= ATH9K_INT_GTT;
2052
2053         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2054                 sc->imask |= ATH9K_INT_CST;
2055
2056         ath_cache_conf_rate(sc, &hw->conf);
2057
2058         sc->sc_flags &= ~SC_OP_INVALID;
2059
2060         /* Disable BMISS interrupt when we're not associated */
2061         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2062         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2063
2064         ieee80211_wake_queues(hw);
2065
2066 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2067         r = ath_start_rfkill_poll(sc);
2068 #endif
2069
2070 mutex_unlock:
2071         mutex_unlock(&sc->mutex);
2072
2073         return r;
2074 }
2075
2076 static int ath9k_tx(struct ieee80211_hw *hw,
2077                     struct sk_buff *skb)
2078 {
2079         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2080         struct ath_wiphy *aphy = hw->priv;
2081         struct ath_softc *sc = aphy->sc;
2082         struct ath_tx_control txctl;
2083         int hdrlen, padsize;
2084
2085         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2086                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2087                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2088                 goto exit;
2089         }
2090
2091         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2092                 /*
2093                  * We are using PS-Poll and mac80211 can request TX while in
2094                  * power save mode. Need to wake up hardware for the TX to be
2095                  * completed and if needed, also for RX of buffered frames.
2096                  */
2097                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2098                 ath9k_ps_wakeup(sc);
2099                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2100                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2101                         DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2102                                 "buffered frame\n");
2103                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2104                 } else {
2105                         DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2106                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2107                 }
2108                 /*
2109                  * The actual restore operation will happen only after
2110                  * the sc_flags bit is cleared. We are just dropping
2111                  * the ps_usecount here.
2112                  */
2113                 ath9k_ps_restore(sc);
2114         }
2115
2116         memset(&txctl, 0, sizeof(struct ath_tx_control));
2117
2118         /*
2119          * As a temporary workaround, assign seq# here; this will likely need
2120          * to be cleaned up to work better with Beacon transmission and virtual
2121          * BSSes.
2122          */
2123         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2124                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2125                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2126                         sc->tx.seq_no += 0x10;
2127                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2128                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2129         }
2130
2131         /* Add the padding after the header if this is not already done */
2132         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2133         if (hdrlen & 3) {
2134                 padsize = hdrlen % 4;
2135                 if (skb_headroom(skb) < padsize)
2136                         return -1;
2137                 skb_push(skb, padsize);
2138                 memmove(skb->data, skb->data + padsize, hdrlen);
2139         }
2140
2141         /* Check if a tx queue is available */
2142
2143         txctl.txq = ath_test_get_txq(sc, skb);
2144         if (!txctl.txq)
2145                 goto exit;
2146
2147         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2148
2149         if (ath_tx_start(hw, skb, &txctl) != 0) {
2150                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2151                 goto exit;
2152         }
2153
2154         return 0;
2155 exit:
2156         dev_kfree_skb_any(skb);
2157         return 0;
2158 }
2159
2160 static void ath9k_stop(struct ieee80211_hw *hw)
2161 {
2162         struct ath_wiphy *aphy = hw->priv;
2163         struct ath_softc *sc = aphy->sc;
2164
2165         aphy->state = ATH_WIPHY_INACTIVE;
2166
2167         if (sc->sc_flags & SC_OP_INVALID) {
2168                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2169                 return;
2170         }
2171
2172         mutex_lock(&sc->mutex);
2173
2174         ieee80211_stop_queues(hw);
2175
2176         if (ath9k_wiphy_started(sc)) {
2177                 mutex_unlock(&sc->mutex);
2178                 return; /* another wiphy still in use */
2179         }
2180
2181         /* make sure h/w will not generate any interrupt
2182          * before setting the invalid flag. */
2183         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2184
2185         if (!(sc->sc_flags & SC_OP_INVALID)) {
2186                 ath_drain_all_txq(sc, false);
2187                 ath_stoprecv(sc);
2188                 ath9k_hw_phy_disable(sc->sc_ah);
2189         } else
2190                 sc->rx.rxlink = NULL;
2191
2192 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2193         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2194                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2195 #endif
2196         /* disable HAL and put h/w to sleep */
2197         ath9k_hw_disable(sc->sc_ah);
2198         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2199
2200         sc->sc_flags |= SC_OP_INVALID;
2201
2202         mutex_unlock(&sc->mutex);
2203
2204         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2205 }
2206
2207 static int ath9k_add_interface(struct ieee80211_hw *hw,
2208                                struct ieee80211_if_init_conf *conf)
2209 {
2210         struct ath_wiphy *aphy = hw->priv;
2211         struct ath_softc *sc = aphy->sc;
2212         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2213         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2214         int ret = 0;
2215
2216         mutex_lock(&sc->mutex);
2217
2218         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2219             sc->nvifs > 0) {
2220                 ret = -ENOBUFS;
2221                 goto out;
2222         }
2223
2224         switch (conf->type) {
2225         case NL80211_IFTYPE_STATION:
2226                 ic_opmode = NL80211_IFTYPE_STATION;
2227                 break;
2228         case NL80211_IFTYPE_ADHOC:
2229         case NL80211_IFTYPE_AP:
2230         case NL80211_IFTYPE_MESH_POINT:
2231                 if (sc->nbcnvifs >= ATH_BCBUF) {
2232                         ret = -ENOBUFS;
2233                         goto out;
2234                 }
2235                 ic_opmode = conf->type;
2236                 break;
2237         default:
2238                 DPRINTF(sc, ATH_DBG_FATAL,
2239                         "Interface type %d not yet supported\n", conf->type);
2240                 ret = -EOPNOTSUPP;
2241                 goto out;
2242         }
2243
2244         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2245
2246         /* Set the VIF opmode */
2247         avp->av_opmode = ic_opmode;
2248         avp->av_bslot = -1;
2249
2250         sc->nvifs++;
2251
2252         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2253                 ath9k_set_bssid_mask(hw);
2254
2255         if (sc->nvifs > 1)
2256                 goto out; /* skip global settings for secondary vif */
2257
2258         if (ic_opmode == NL80211_IFTYPE_AP) {
2259                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2260                 sc->sc_flags |= SC_OP_TSF_RESET;
2261         }
2262
2263         /* Set the device opmode */
2264         sc->sc_ah->opmode = ic_opmode;
2265
2266         /*
2267          * Enable MIB interrupts when there are hardware phy counters.
2268          * Note we only do this (at the moment) for station mode.
2269          */
2270         if ((conf->type == NL80211_IFTYPE_STATION) ||
2271             (conf->type == NL80211_IFTYPE_ADHOC) ||
2272             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2273                 if (ath9k_hw_phycounters(sc->sc_ah))
2274                         sc->imask |= ATH9K_INT_MIB;
2275                 sc->imask |= ATH9K_INT_TSFOOR;
2276         }
2277
2278         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2279
2280         if (conf->type == NL80211_IFTYPE_AP)
2281                 ath_start_ani(sc);
2282
2283 out:
2284         mutex_unlock(&sc->mutex);
2285         return ret;
2286 }
2287
2288 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2289                                    struct ieee80211_if_init_conf *conf)
2290 {
2291         struct ath_wiphy *aphy = hw->priv;
2292         struct ath_softc *sc = aphy->sc;
2293         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2294         int i;
2295
2296         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2297
2298         mutex_lock(&sc->mutex);
2299
2300         /* Stop ANI */
2301         del_timer_sync(&sc->ani.timer);
2302
2303         /* Reclaim beacon resources */
2304         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2305             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2306             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2307                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2308                 ath_beacon_return(sc, avp);
2309         }
2310
2311         sc->sc_flags &= ~SC_OP_BEACONS;
2312
2313         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2314                 if (sc->beacon.bslot[i] == conf->vif) {
2315                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2316                                "slot\n", __func__);
2317                         sc->beacon.bslot[i] = NULL;
2318                         sc->beacon.bslot_aphy[i] = NULL;
2319                 }
2320         }
2321
2322         sc->nvifs--;
2323
2324         mutex_unlock(&sc->mutex);
2325 }
2326
2327 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2328 {
2329         struct ath_wiphy *aphy = hw->priv;
2330         struct ath_softc *sc = aphy->sc;
2331         struct ieee80211_conf *conf = &hw->conf;
2332         struct ath_hw *ah = sc->sc_ah;
2333
2334         mutex_lock(&sc->mutex);
2335
2336         if (changed & IEEE80211_CONF_CHANGE_PS) {
2337                 if (conf->flags & IEEE80211_CONF_PS) {
2338                         if (!(ah->caps.hw_caps &
2339                               ATH9K_HW_CAP_AUTOSLEEP)) {
2340                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2341                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2342                                         ath9k_hw_set_interrupts(sc->sc_ah,
2343                                                         sc->imask);
2344                                 }
2345                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2346                         }
2347                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2348                 } else {
2349                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2350                         if (!(ah->caps.hw_caps &
2351                               ATH9K_HW_CAP_AUTOSLEEP)) {
2352                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2353                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2354                                                   SC_OP_WAIT_FOR_CAB |
2355                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2356                                                   SC_OP_WAIT_FOR_TX_ACK);
2357                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2358                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2359                                         ath9k_hw_set_interrupts(sc->sc_ah,
2360                                                         sc->imask);
2361                                 }
2362                         }
2363                 }
2364         }
2365
2366         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2367                 struct ieee80211_channel *curchan = hw->conf.channel;
2368                 int pos = curchan->hw_value;
2369
2370                 aphy->chan_idx = pos;
2371                 aphy->chan_is_ht = conf_is_ht(conf);
2372
2373                 if (aphy->state == ATH_WIPHY_SCAN ||
2374                     aphy->state == ATH_WIPHY_ACTIVE)
2375                         ath9k_wiphy_pause_all_forced(sc, aphy);
2376                 else {
2377                         /*
2378                          * Do not change operational channel based on a paused
2379                          * wiphy changes.
2380                          */
2381                         goto skip_chan_change;
2382                 }
2383
2384                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2385                         curchan->center_freq);
2386
2387                 /* XXX: remove me eventualy */
2388                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2389
2390                 ath_update_chainmask(sc, conf_is_ht(conf));
2391
2392                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2393                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2394                         mutex_unlock(&sc->mutex);
2395                         return -EINVAL;
2396                 }
2397         }
2398
2399 skip_chan_change:
2400         if (changed & IEEE80211_CONF_CHANGE_POWER)
2401                 sc->config.txpowlimit = 2 * conf->power_level;
2402
2403         mutex_unlock(&sc->mutex);
2404
2405         return 0;
2406 }
2407
2408 #define SUPPORTED_FILTERS                       \
2409         (FIF_PROMISC_IN_BSS |                   \
2410         FIF_ALLMULTI |                          \
2411         FIF_CONTROL |                           \
2412         FIF_OTHER_BSS |                         \
2413         FIF_BCN_PRBRESP_PROMISC |               \
2414         FIF_FCSFAIL)
2415
2416 /* FIXME: sc->sc_full_reset ? */
2417 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2418                                    unsigned int changed_flags,
2419                                    unsigned int *total_flags,
2420                                    int mc_count,
2421                                    struct dev_mc_list *mclist)
2422 {
2423         struct ath_wiphy *aphy = hw->priv;
2424         struct ath_softc *sc = aphy->sc;
2425         u32 rfilt;
2426
2427         changed_flags &= SUPPORTED_FILTERS;
2428         *total_flags &= SUPPORTED_FILTERS;
2429
2430         sc->rx.rxfilter = *total_flags;
2431         rfilt = ath_calcrxfilter(sc);
2432         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2433
2434         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2435 }
2436
2437 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2438                              struct ieee80211_vif *vif,
2439                              enum sta_notify_cmd cmd,
2440                              struct ieee80211_sta *sta)
2441 {
2442         struct ath_wiphy *aphy = hw->priv;
2443         struct ath_softc *sc = aphy->sc;
2444
2445         switch (cmd) {
2446         case STA_NOTIFY_ADD:
2447                 ath_node_attach(sc, sta);
2448                 break;
2449         case STA_NOTIFY_REMOVE:
2450                 ath_node_detach(sc, sta);
2451                 break;
2452         default:
2453                 break;
2454         }
2455 }
2456
2457 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2458                          const struct ieee80211_tx_queue_params *params)
2459 {
2460         struct ath_wiphy *aphy = hw->priv;
2461         struct ath_softc *sc = aphy->sc;
2462         struct ath9k_tx_queue_info qi;
2463         int ret = 0, qnum;
2464
2465         if (queue >= WME_NUM_AC)
2466                 return 0;
2467
2468         mutex_lock(&sc->mutex);
2469
2470         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2471
2472         qi.tqi_aifs = params->aifs;
2473         qi.tqi_cwmin = params->cw_min;
2474         qi.tqi_cwmax = params->cw_max;
2475         qi.tqi_burstTime = params->txop;
2476         qnum = ath_get_hal_qnum(queue, sc);
2477
2478         DPRINTF(sc, ATH_DBG_CONFIG,
2479                 "Configure tx [queue/halq] [%d/%d],  "
2480                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2481                 queue, qnum, params->aifs, params->cw_min,
2482                 params->cw_max, params->txop);
2483
2484         ret = ath_txq_update(sc, qnum, &qi);
2485         if (ret)
2486                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2487
2488         mutex_unlock(&sc->mutex);
2489
2490         return ret;
2491 }
2492
2493 static int ath9k_set_key(struct ieee80211_hw *hw,
2494                          enum set_key_cmd cmd,
2495                          struct ieee80211_vif *vif,
2496                          struct ieee80211_sta *sta,
2497                          struct ieee80211_key_conf *key)
2498 {
2499         struct ath_wiphy *aphy = hw->priv;
2500         struct ath_softc *sc = aphy->sc;
2501         int ret = 0;
2502
2503         if (modparam_nohwcrypt)
2504                 return -ENOSPC;
2505
2506         mutex_lock(&sc->mutex);
2507         ath9k_ps_wakeup(sc);
2508         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2509
2510         switch (cmd) {
2511         case SET_KEY:
2512                 ret = ath_key_config(sc, vif, sta, key);
2513                 if (ret >= 0) {
2514                         key->hw_key_idx = ret;
2515                         /* push IV and Michael MIC generation to stack */
2516                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2517                         if (key->alg == ALG_TKIP)
2518                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2519                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2520                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2521                         ret = 0;
2522                 }
2523                 break;
2524         case DISABLE_KEY:
2525                 ath_key_delete(sc, key);
2526                 break;
2527         default:
2528                 ret = -EINVAL;
2529         }
2530
2531         ath9k_ps_restore(sc);
2532         mutex_unlock(&sc->mutex);
2533
2534         return ret;
2535 }
2536
2537 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2538                                    struct ieee80211_vif *vif,
2539                                    struct ieee80211_bss_conf *bss_conf,
2540                                    u32 changed)
2541 {
2542         struct ath_wiphy *aphy = hw->priv;
2543         struct ath_softc *sc = aphy->sc;
2544         struct ath_hw *ah = sc->sc_ah;
2545         struct ath_vif *avp = (void *)vif->drv_priv;
2546         u32 rfilt = 0;
2547         int error, i;
2548
2549         mutex_lock(&sc->mutex);
2550
2551         /*
2552          * TODO: Need to decide which hw opmode to use for
2553          *       multi-interface cases
2554          * XXX: This belongs into add_interface!
2555          */
2556         if (vif->type == NL80211_IFTYPE_AP &&
2557             ah->opmode != NL80211_IFTYPE_AP) {
2558                 ah->opmode = NL80211_IFTYPE_STATION;
2559                 ath9k_hw_setopmode(ah);
2560                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2561                 sc->curaid = 0;
2562                 ath9k_hw_write_associd(sc);
2563                 /* Request full reset to get hw opmode changed properly */
2564                 sc->sc_flags |= SC_OP_FULL_RESET;
2565         }
2566
2567         if ((changed & BSS_CHANGED_BSSID) &&
2568             !is_zero_ether_addr(bss_conf->bssid)) {
2569                 switch (vif->type) {
2570                 case NL80211_IFTYPE_STATION:
2571                 case NL80211_IFTYPE_ADHOC:
2572                 case NL80211_IFTYPE_MESH_POINT:
2573                         /* Set BSSID */
2574                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2575                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2576                         sc->curaid = 0;
2577                         ath9k_hw_write_associd(sc);
2578
2579                         /* Set aggregation protection mode parameters */
2580                         sc->config.ath_aggr_prot = 0;
2581
2582                         DPRINTF(sc, ATH_DBG_CONFIG,
2583                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2584                                 rfilt, sc->curbssid, sc->curaid);
2585
2586                         /* need to reconfigure the beacon */
2587                         sc->sc_flags &= ~SC_OP_BEACONS ;
2588
2589                         break;
2590                 default:
2591                         break;
2592                 }
2593         }
2594
2595         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2596             (vif->type == NL80211_IFTYPE_AP) ||
2597             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2598                 if ((changed & BSS_CHANGED_BEACON) ||
2599                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2600                      bss_conf->enable_beacon)) {
2601                         /*
2602                          * Allocate and setup the beacon frame.
2603                          *
2604                          * Stop any previous beacon DMA.  This may be
2605                          * necessary, for example, when an ibss merge
2606                          * causes reconfiguration; we may be called
2607                          * with beacon transmission active.
2608                          */
2609                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2610
2611                         error = ath_beacon_alloc(aphy, vif);
2612                         if (!error)
2613                                 ath_beacon_config(sc, vif);
2614                 }
2615         }
2616
2617         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2618         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2619                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2620                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2621                                 ath9k_hw_keysetmac(sc->sc_ah,
2622                                                    (u16)i,
2623                                                    sc->curbssid);
2624         }
2625
2626         /* Only legacy IBSS for now */
2627         if (vif->type == NL80211_IFTYPE_ADHOC)
2628                 ath_update_chainmask(sc, 0);
2629
2630         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2631                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2632                         bss_conf->use_short_preamble);
2633                 if (bss_conf->use_short_preamble)
2634                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2635                 else
2636                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2637         }
2638
2639         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2640                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2641                         bss_conf->use_cts_prot);
2642                 if (bss_conf->use_cts_prot &&
2643                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2644                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2645                 else
2646                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2647         }
2648
2649         if (changed & BSS_CHANGED_ASSOC) {
2650                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2651                         bss_conf->assoc);
2652                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2653         }
2654
2655         /*
2656          * The HW TSF has to be reset when the beacon interval changes.
2657          * We set the flag here, and ath_beacon_config_ap() would take this
2658          * into account when it gets called through the subsequent
2659          * config_interface() call - with IFCC_BEACON in the changed field.
2660          */
2661
2662         if (changed & BSS_CHANGED_BEACON_INT) {
2663                 sc->sc_flags |= SC_OP_TSF_RESET;
2664                 sc->beacon_interval = bss_conf->beacon_int;
2665         }
2666
2667         mutex_unlock(&sc->mutex);
2668 }
2669
2670 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2671 {
2672         u64 tsf;
2673         struct ath_wiphy *aphy = hw->priv;
2674         struct ath_softc *sc = aphy->sc;
2675
2676         mutex_lock(&sc->mutex);
2677         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2678         mutex_unlock(&sc->mutex);
2679
2680         return tsf;
2681 }
2682
2683 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2684 {
2685         struct ath_wiphy *aphy = hw->priv;
2686         struct ath_softc *sc = aphy->sc;
2687
2688         mutex_lock(&sc->mutex);
2689         ath9k_hw_settsf64(sc->sc_ah, tsf);
2690         mutex_unlock(&sc->mutex);
2691 }
2692
2693 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2694 {
2695         struct ath_wiphy *aphy = hw->priv;
2696         struct ath_softc *sc = aphy->sc;
2697
2698         mutex_lock(&sc->mutex);
2699         ath9k_hw_reset_tsf(sc->sc_ah);
2700         mutex_unlock(&sc->mutex);
2701 }
2702
2703 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2704                               enum ieee80211_ampdu_mlme_action action,
2705                               struct ieee80211_sta *sta,
2706                               u16 tid, u16 *ssn)
2707 {
2708         struct ath_wiphy *aphy = hw->priv;
2709         struct ath_softc *sc = aphy->sc;
2710         int ret = 0;
2711
2712         switch (action) {
2713         case IEEE80211_AMPDU_RX_START:
2714                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2715                         ret = -ENOTSUPP;
2716                 break;
2717         case IEEE80211_AMPDU_RX_STOP:
2718                 break;
2719         case IEEE80211_AMPDU_TX_START:
2720                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2721                 if (ret < 0)
2722                         DPRINTF(sc, ATH_DBG_FATAL,
2723                                 "Unable to start TX aggregation\n");
2724                 else
2725                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2726                 break;
2727         case IEEE80211_AMPDU_TX_STOP:
2728                 ret = ath_tx_aggr_stop(sc, sta, tid);
2729                 if (ret < 0)
2730                         DPRINTF(sc, ATH_DBG_FATAL,
2731                                 "Unable to stop TX aggregation\n");
2732
2733                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2734                 break;
2735         case IEEE80211_AMPDU_TX_OPERATIONAL:
2736                 ath_tx_aggr_resume(sc, sta, tid);
2737                 break;
2738         default:
2739                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2740         }
2741
2742         return ret;
2743 }
2744
2745 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2746 {
2747         struct ath_wiphy *aphy = hw->priv;
2748         struct ath_softc *sc = aphy->sc;
2749
2750         if (ath9k_wiphy_scanning(sc)) {
2751                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2752                        "same time\n");
2753                 /*
2754                  * Do not allow the concurrent scanning state for now. This
2755                  * could be improved with scanning control moved into ath9k.
2756                  */
2757                 return;
2758         }
2759
2760         aphy->state = ATH_WIPHY_SCAN;
2761         ath9k_wiphy_pause_all_forced(sc, aphy);
2762
2763         mutex_lock(&sc->mutex);
2764         sc->sc_flags |= SC_OP_SCANNING;
2765         mutex_unlock(&sc->mutex);
2766 }
2767
2768 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2769 {
2770         struct ath_wiphy *aphy = hw->priv;
2771         struct ath_softc *sc = aphy->sc;
2772
2773         mutex_lock(&sc->mutex);
2774         aphy->state = ATH_WIPHY_ACTIVE;
2775         sc->sc_flags &= ~SC_OP_SCANNING;
2776         sc->sc_flags |= SC_OP_FULL_RESET;
2777         mutex_unlock(&sc->mutex);
2778 }
2779
2780 struct ieee80211_ops ath9k_ops = {
2781         .tx                 = ath9k_tx,
2782         .start              = ath9k_start,
2783         .stop               = ath9k_stop,
2784         .add_interface      = ath9k_add_interface,
2785         .remove_interface   = ath9k_remove_interface,
2786         .config             = ath9k_config,
2787         .configure_filter   = ath9k_configure_filter,
2788         .sta_notify         = ath9k_sta_notify,
2789         .conf_tx            = ath9k_conf_tx,
2790         .bss_info_changed   = ath9k_bss_info_changed,
2791         .set_key            = ath9k_set_key,
2792         .get_tsf            = ath9k_get_tsf,
2793         .set_tsf            = ath9k_set_tsf,
2794         .reset_tsf          = ath9k_reset_tsf,
2795         .ampdu_action       = ath9k_ampdu_action,
2796         .sw_scan_start      = ath9k_sw_scan_start,
2797         .sw_scan_complete   = ath9k_sw_scan_complete,
2798 };
2799
2800 static struct {
2801         u32 version;
2802         const char * name;
2803 } ath_mac_bb_names[] = {
2804         { AR_SREV_VERSION_5416_PCI,     "5416" },
2805         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2806         { AR_SREV_VERSION_9100,         "9100" },
2807         { AR_SREV_VERSION_9160,         "9160" },
2808         { AR_SREV_VERSION_9280,         "9280" },
2809         { AR_SREV_VERSION_9285,         "9285" }
2810 };
2811
2812 static struct {
2813         u16 version;
2814         const char * name;
2815 } ath_rf_names[] = {
2816         { 0,                            "5133" },
2817         { AR_RAD5133_SREV_MAJOR,        "5133" },
2818         { AR_RAD5122_SREV_MAJOR,        "5122" },
2819         { AR_RAD2133_SREV_MAJOR,        "2133" },
2820         { AR_RAD2122_SREV_MAJOR,        "2122" }
2821 };
2822
2823 /*
2824  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2825  */
2826 const char *
2827 ath_mac_bb_name(u32 mac_bb_version)
2828 {
2829         int i;
2830
2831         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2832                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2833                         return ath_mac_bb_names[i].name;
2834                 }
2835         }
2836
2837         return "????";
2838 }
2839
2840 /*
2841  * Return the RF name. "????" is returned if the RF is unknown.
2842  */
2843 const char *
2844 ath_rf_name(u16 rf_version)
2845 {
2846         int i;
2847
2848         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2849                 if (ath_rf_names[i].version == rf_version) {
2850                         return ath_rf_names[i].name;
2851                 }
2852         }
2853
2854         return "????";
2855 }
2856
2857 static int __init ath9k_init(void)
2858 {
2859         int error;
2860
2861         /* Register rate control algorithm */
2862         error = ath_rate_control_register();
2863         if (error != 0) {
2864                 printk(KERN_ERR
2865                         "ath9k: Unable to register rate control "
2866                         "algorithm: %d\n",
2867                         error);
2868                 goto err_out;
2869         }
2870
2871         error = ath9k_debug_create_root();
2872         if (error) {
2873                 printk(KERN_ERR
2874                         "ath9k: Unable to create debugfs root: %d\n",
2875                         error);
2876                 goto err_rate_unregister;
2877         }
2878
2879         error = ath_pci_init();
2880         if (error < 0) {
2881                 printk(KERN_ERR
2882                         "ath9k: No PCI devices found, driver not installed.\n");
2883                 error = -ENODEV;
2884                 goto err_remove_root;
2885         }
2886
2887         error = ath_ahb_init();
2888         if (error < 0) {
2889                 error = -ENODEV;
2890                 goto err_pci_exit;
2891         }
2892
2893         return 0;
2894
2895  err_pci_exit:
2896         ath_pci_exit();
2897
2898  err_remove_root:
2899         ath9k_debug_remove_root();
2900  err_rate_unregister:
2901         ath_rate_control_unregister();
2902  err_out:
2903         return error;
2904 }
2905 module_init(ath9k_init);
2906
2907 static void __exit ath9k_exit(void)
2908 {
2909         ath_ahb_exit();
2910         ath_pci_exit();
2911         ath9k_debug_remove_root();
2912         ath_rate_control_unregister();
2913         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2914 }
2915 module_exit(ath9k_exit);