2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/slab.h>
21 static char *dev_info = "ath9k";
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
28 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
29 module_param_named(debug, ath9k_debug, uint, 0);
30 MODULE_PARM_DESC(debug, "Debugging mask");
32 int modparam_nohwcrypt;
33 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
34 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
36 /* We use the hw_value as an index into our private channel structure */
38 #define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
44 #define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
51 /* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
55 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
72 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
76 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
107 /* Atheros hardware rate code addition for short premble */
108 #define SHPCHECK(__hw_rate, __flags) \
109 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
111 #define RATE(_bitrate, _hw_rate, _flags) { \
112 .bitrate = (_bitrate), \
114 .hw_value = (_hw_rate), \
115 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
118 static struct ieee80211_rate ath9k_legacy_rates[] = {
120 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
121 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
122 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
133 static void ath9k_deinit_softc(struct ath_softc *sc);
136 * Read and write, they both share the same lock. We do this to serialize
137 * reads and writes on Atheros 802.11n PCI devices only. This is required
138 * as the FIFO on these devices can only accept sanely 2 requests.
141 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
143 struct ath_hw *ah = (struct ath_hw *) hw_priv;
144 struct ath_common *common = ath9k_hw_common(ah);
145 struct ath_softc *sc = (struct ath_softc *) common->priv;
147 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
149 spin_lock_irqsave(&sc->sc_serial_rw, flags);
150 iowrite32(val, sc->mem + reg_offset);
151 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
153 iowrite32(val, sc->mem + reg_offset);
156 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
158 struct ath_hw *ah = (struct ath_hw *) hw_priv;
159 struct ath_common *common = ath9k_hw_common(ah);
160 struct ath_softc *sc = (struct ath_softc *) common->priv;
163 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
165 spin_lock_irqsave(&sc->sc_serial_rw, flags);
166 val = ioread32(sc->mem + reg_offset);
167 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
169 val = ioread32(sc->mem + reg_offset);
173 static const struct ath_ops ath9k_common_ops = {
174 .read = ath9k_ioread32,
175 .write = ath9k_iowrite32,
178 /**************************/
180 /**************************/
182 static void setup_ht_cap(struct ath_softc *sc,
183 struct ieee80211_sta_ht_cap *ht_info)
185 struct ath_hw *ah = sc->sc_ah;
186 struct ath_common *common = ath9k_hw_common(ah);
187 u8 tx_streams, rx_streams;
190 ht_info->ht_supported = true;
191 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
192 IEEE80211_HT_CAP_SM_PS |
193 IEEE80211_HT_CAP_SGI_40 |
194 IEEE80211_HT_CAP_DSSSCCK40;
196 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
197 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
199 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
200 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
202 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
203 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
205 if (AR_SREV_9300_20_OR_LATER(ah))
210 if (AR_SREV_9280_10_OR_LATER(ah)) {
211 if (max_streams >= 2)
212 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
213 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
216 /* set up supported mcs set */
217 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
218 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
219 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
221 ath_print(common, ATH_DBG_CONFIG,
222 "TX streams %d, RX streams: %d\n",
223 tx_streams, rx_streams);
225 if (tx_streams != rx_streams) {
226 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
227 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
228 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
231 for (i = 0; i < rx_streams; i++)
232 ht_info->mcs.rx_mask[i] = 0xff;
234 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
237 static int ath9k_reg_notifier(struct wiphy *wiphy,
238 struct regulatory_request *request)
240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
241 struct ath_wiphy *aphy = hw->priv;
242 struct ath_softc *sc = aphy->sc;
243 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
245 return ath_reg_notifier_apply(wiphy, request, reg);
249 * This function will allocate both the DMA descriptor structure, and the
250 * buffers it contains. These are used to contain the descriptors used
253 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
254 struct list_head *head, const char *name,
255 int nbuf, int ndesc, bool is_tx)
257 #define DS2PHYS(_dd, _ds) \
258 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
259 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
260 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
261 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
264 int i, bsize, error, desc_len;
266 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
269 INIT_LIST_HEAD(head);
272 desc_len = sc->sc_ah->caps.tx_desc_len;
274 desc_len = sizeof(struct ath_desc);
276 /* ath_desc must be a multiple of DWORDs */
277 if ((desc_len % 4) != 0) {
278 ath_print(common, ATH_DBG_FATAL,
279 "ath_desc not DWORD aligned\n");
280 BUG_ON((desc_len % 4) != 0);
285 dd->dd_desc_len = desc_len * nbuf * ndesc;
288 * Need additional DMA memory because we can't use
289 * descriptors that cross the 4K page boundary. Assume
290 * one skipped descriptor per 4K page.
292 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
294 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
297 while (ndesc_skipped) {
298 dma_len = ndesc_skipped * desc_len;
299 dd->dd_desc_len += dma_len;
301 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
305 /* allocate descriptors */
306 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
307 &dd->dd_desc_paddr, GFP_KERNEL);
308 if (dd->dd_desc == NULL) {
312 ds = (u8 *) dd->dd_desc;
313 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
314 name, ds, (u32) dd->dd_desc_len,
315 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
317 /* allocate buffers */
318 bsize = sizeof(struct ath_buf) * nbuf;
319 bf = kzalloc(bsize, GFP_KERNEL);
326 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
328 bf->bf_daddr = DS2PHYS(dd, ds);
330 if (!(sc->sc_ah->caps.hw_caps &
331 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
333 * Skip descriptor addresses which can cause 4KB
334 * boundary crossing (addr + length) with a 32 dword
337 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
338 BUG_ON((caddr_t) bf->bf_desc >=
339 ((caddr_t) dd->dd_desc +
342 ds += (desc_len * ndesc);
344 bf->bf_daddr = DS2PHYS(dd, ds);
347 list_add_tail(&bf->list, head);
351 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
354 memset(dd, 0, sizeof(*dd));
356 #undef ATH_DESC_4KB_BOUND_CHECK
357 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
361 static void ath9k_init_crypto(struct ath_softc *sc)
363 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
366 /* Get the hardware key cache size. */
367 common->keymax = sc->sc_ah->caps.keycache_size;
368 if (common->keymax > ATH_KEYMAX) {
369 ath_print(common, ATH_DBG_ANY,
370 "Warning, using only %u entries in %u key cache\n",
371 ATH_KEYMAX, common->keymax);
372 common->keymax = ATH_KEYMAX;
376 * Reset the key cache since some parts do not
377 * reset the contents on initial power up.
379 for (i = 0; i < common->keymax; i++)
380 ath9k_hw_keyreset(sc->sc_ah, (u16) i);
383 * Check whether the separate key cache entries
384 * are required to handle both tx+rx MIC keys.
385 * With split mic keys the number of stations is limited
386 * to 27 otherwise 59.
388 if (ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_TKIP_SPLIT, 0, NULL))
389 common->splitmic = 1;
391 /* turn on mcast key search if possible */
392 if (!ath9k_hw_getcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
393 (void)ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_MCAST_KEYSRCH,
398 static int ath9k_init_btcoex(struct ath_softc *sc)
402 switch (sc->sc_ah->btcoex_hw.scheme) {
403 case ATH_BTCOEX_CFG_NONE:
405 case ATH_BTCOEX_CFG_2WIRE:
406 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
408 case ATH_BTCOEX_CFG_3WIRE:
409 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
410 r = ath_init_btcoex_timer(sc);
413 qnum = sc->tx.hwq_map[WME_AC_BE];
414 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
415 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
425 static int ath9k_init_queues(struct ath_softc *sc)
427 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
430 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
431 sc->tx.hwq_map[i] = -1;
433 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
434 if (sc->beacon.beaconq == -1) {
435 ath_print(common, ATH_DBG_FATAL,
436 "Unable to setup a beacon xmit queue\n");
440 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
441 if (sc->beacon.cabq == NULL) {
442 ath_print(common, ATH_DBG_FATAL,
443 "Unable to setup CAB xmit queue\n");
447 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
450 if (!ath_tx_setup(sc, WME_AC_BK)) {
451 ath_print(common, ATH_DBG_FATAL,
452 "Unable to setup xmit queue for BK traffic\n");
456 if (!ath_tx_setup(sc, WME_AC_BE)) {
457 ath_print(common, ATH_DBG_FATAL,
458 "Unable to setup xmit queue for BE traffic\n");
461 if (!ath_tx_setup(sc, WME_AC_VI)) {
462 ath_print(common, ATH_DBG_FATAL,
463 "Unable to setup xmit queue for VI traffic\n");
466 if (!ath_tx_setup(sc, WME_AC_VO)) {
467 ath_print(common, ATH_DBG_FATAL,
468 "Unable to setup xmit queue for VO traffic\n");
475 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
476 if (ATH_TXQ_SETUP(sc, i))
477 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
482 static void ath9k_init_channels_rates(struct ath_softc *sc)
484 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
485 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
486 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
487 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
488 ARRAY_SIZE(ath9k_2ghz_chantable);
489 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
490 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
491 ARRAY_SIZE(ath9k_legacy_rates);
494 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
495 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
496 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
497 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
498 ARRAY_SIZE(ath9k_5ghz_chantable);
499 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
500 ath9k_legacy_rates + 4;
501 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
502 ARRAY_SIZE(ath9k_legacy_rates) - 4;
506 static void ath9k_init_misc(struct ath_softc *sc)
508 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
511 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
512 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
514 sc->config.txpowlimit = ATH_TXPOWER_MAX;
516 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
517 sc->sc_flags |= SC_OP_TXAGGR;
518 sc->sc_flags |= SC_OP_RXAGGR;
521 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
522 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
524 ath9k_hw_set_diversity(sc->sc_ah, true);
525 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
527 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
528 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
530 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
532 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
533 sc->beacon.bslot[i] = NULL;
534 sc->beacon.bslot_aphy[i] = NULL;
538 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
539 const struct ath_bus_ops *bus_ops)
541 struct ath_hw *ah = NULL;
542 struct ath_common *common;
546 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
550 ah->hw_version.devid = devid;
551 ah->hw_version.subsysid = subsysid;
554 common = ath9k_hw_common(ah);
555 common->ops = &ath9k_common_ops;
556 common->bus_ops = bus_ops;
560 common->debug_mask = ath9k_debug;
562 spin_lock_init(&sc->wiphy_lock);
563 spin_lock_init(&sc->sc_resetlock);
564 spin_lock_init(&sc->sc_serial_rw);
565 spin_lock_init(&sc->sc_pm_lock);
566 mutex_init(&sc->mutex);
567 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
568 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
572 * Cache line size is used to size and align various
573 * structures used to communicate with the hardware.
575 ath_read_cachesize(common, &csz);
576 common->cachelsz = csz << 2; /* convert to bytes */
578 /* Initializes the hardware for all supported chipsets */
579 ret = ath9k_hw_init(ah);
583 ret = ath9k_init_debug(ah);
585 ath_print(common, ATH_DBG_FATAL,
586 "Unable to create debugfs files\n");
590 ret = ath9k_init_queues(sc);
594 ret = ath9k_init_btcoex(sc);
598 ath9k_init_crypto(sc);
599 ath9k_init_channels_rates(sc);
605 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
606 if (ATH_TXQ_SETUP(sc, i))
607 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
609 ath9k_exit_debug(ah);
613 tasklet_kill(&sc->intr_tq);
614 tasklet_kill(&sc->bcon_tasklet);
622 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
626 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
627 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
628 IEEE80211_HW_SIGNAL_DBM |
629 IEEE80211_HW_SUPPORTS_PS |
630 IEEE80211_HW_PS_NULLFUNC_STACK |
631 IEEE80211_HW_SPECTRUM_MGMT |
632 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
634 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
635 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
637 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
638 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
640 hw->wiphy->interface_modes =
641 BIT(NL80211_IFTYPE_AP) |
642 BIT(NL80211_IFTYPE_STATION) |
643 BIT(NL80211_IFTYPE_ADHOC) |
644 BIT(NL80211_IFTYPE_MESH_POINT);
646 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
650 hw->channel_change_time = 5000;
651 hw->max_listen_interval = 10;
652 hw->max_rate_tries = 10;
653 hw->sta_data_size = sizeof(struct ath_node);
654 hw->vif_data_size = sizeof(struct ath_vif);
656 hw->rate_control_algorithm = "ath9k_rate_control";
658 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
659 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
660 &sc->sbands[IEEE80211_BAND_2GHZ];
661 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
662 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
663 &sc->sbands[IEEE80211_BAND_5GHZ];
665 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
666 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
667 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
668 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
669 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
672 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
675 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
676 const struct ath_bus_ops *bus_ops)
678 struct ieee80211_hw *hw = sc->hw;
679 struct ath_common *common;
682 struct ath_regulatory *reg;
684 /* Bring up device */
685 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
690 common = ath9k_hw_common(ah);
691 ath9k_set_hw_capab(sc, hw);
693 /* Initialize regulatory */
694 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
699 reg = &common->regulatory;
702 error = ath_tx_init(sc, ATH_TXBUF);
707 error = ath_rx_init(sc, ATH_RXBUF);
711 /* Register with mac80211 */
712 error = ieee80211_register_hw(hw);
716 /* Handle world regulatory */
717 if (!ath_is_world_regd(reg)) {
718 error = regulatory_hint(hw->wiphy, reg->alpha2);
723 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
724 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
725 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
726 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
729 ath_start_rfkill_poll(sc);
734 ieee80211_unregister_hw(hw);
742 ath9k_deinit_softc(sc);
747 /*****************************/
748 /* De-Initialization */
749 /*****************************/
751 static void ath9k_deinit_softc(struct ath_softc *sc)
755 if ((sc->btcoex.no_stomp_timer) &&
756 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
757 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
759 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
760 if (ATH_TXQ_SETUP(sc, i))
761 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
763 ath9k_exit_debug(sc->sc_ah);
764 ath9k_hw_deinit(sc->sc_ah);
766 tasklet_kill(&sc->intr_tq);
767 tasklet_kill(&sc->bcon_tasklet);
773 void ath9k_deinit_device(struct ath_softc *sc)
775 struct ieee80211_hw *hw = sc->hw;
780 wiphy_rfkill_stop_polling(sc->hw->wiphy);
783 for (i = 0; i < sc->num_sec_wiphy; i++) {
784 struct ath_wiphy *aphy = sc->sec_wiphy[i];
787 sc->sec_wiphy[i] = NULL;
788 ieee80211_unregister_hw(aphy->hw);
789 ieee80211_free_hw(aphy->hw);
791 kfree(sc->sec_wiphy);
793 ieee80211_unregister_hw(hw);
796 ath9k_deinit_softc(sc);
799 void ath_descdma_cleanup(struct ath_softc *sc,
800 struct ath_descdma *dd,
801 struct list_head *head)
803 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
806 INIT_LIST_HEAD(head);
807 kfree(dd->dd_bufptr);
808 memset(dd, 0, sizeof(*dd));
811 /************************/
813 /************************/
815 static int __init ath9k_init(void)
819 /* Register rate control algorithm */
820 error = ath_rate_control_register();
823 "ath9k: Unable to register rate control "
829 error = ath9k_debug_create_root();
832 "ath9k: Unable to create debugfs root: %d\n",
834 goto err_rate_unregister;
837 error = ath_pci_init();
840 "ath9k: No PCI devices found, driver not installed.\n");
842 goto err_remove_root;
845 error = ath_ahb_init();
857 ath9k_debug_remove_root();
859 ath_rate_control_unregister();
863 module_init(ath9k_init);
865 static void __exit ath9k_exit(void)
869 ath9k_debug_remove_root();
870 ath_rate_control_unregister();
871 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
873 module_exit(ath9k_exit);