2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init ath9k_init(void)
37 module_init(ath9k_init);
39 static void __exit ath9k_exit(void)
43 module_exit(ath9k_exit);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
93 else if (!ah->curchan) /* should really check for CCK instead */
94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
102 if (conf_is_ht40(conf))
106 if (IS_CHAN_HALF_RATE(ah->curchan))
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
112 common->clockrate = clockrate;
115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
117 struct ath_common *common = ath9k_hw_common(ah);
119 return usecs * common->clockrate;
122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
126 BUG_ON(timeout < AH_TIME_QUANTUM);
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
129 if ((REG_READ(ah, reg) & mask) == val)
132 udelay(AH_TIME_QUANTUM);
135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
141 EXPORT_SYMBOL(ath9k_hw_wait);
143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
154 REGWRITE_BUFFER_FLUSH(ah);
157 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
169 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 u32 frameLen, u16 rateix,
174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
180 case WLAN_RC_PHY_CCK:
181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
187 case WLAN_RC_PHY_OFDM:
188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
220 EXPORT_SYMBOL(ath9k_hw_computetxtime);
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center =
249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
256 static void ath9k_hw_read_revisions(struct ath_hw *ah)
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
283 val = REG_READ(ah, AR_SREV);
284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
289 if (!AR_SREV_9100(ah))
290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
292 ah->hw_version.macRev = val & AR_SREV_REVISION;
294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->is_pciexpress = true;
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
305 if (!AR_SREV_5416(ah))
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
321 /* This should work for all families including legacy */
322 static bool ath9k_hw_chip_test(struct ath_hw *ah)
324 struct ath_common *common = ath9k_hw_common(ah);
325 u32 regAddr[2] = { AR_STA_ID0 };
327 static const u32 patternData[4] = {
328 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
332 if (!AR_SREV_9300_20_OR_LATER(ah)) {
334 regAddr[1] = AR_PHY_BASE + (8 << 2);
338 for (i = 0; i < loop_max; i++) {
339 u32 addr = regAddr[i];
342 regHold[i] = REG_READ(ah, addr);
343 for (j = 0; j < 0x100; j++) {
344 wrData = (j << 16) | j;
345 REG_WRITE(ah, addr, wrData);
346 rdData = REG_READ(ah, addr);
347 if (rdData != wrData) {
349 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
350 addr, wrData, rdData);
354 for (j = 0; j < 4; j++) {
355 wrData = patternData[j];
356 REG_WRITE(ah, addr, wrData);
357 rdData = REG_READ(ah, addr);
358 if (wrData != rdData) {
360 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
361 addr, wrData, rdData);
365 REG_WRITE(ah, regAddr[i], regHold[i]);
372 static void ath9k_hw_init_config(struct ath_hw *ah)
376 ah->config.dma_beacon_response_time = 2;
377 ah->config.sw_beacon_response_time = 10;
378 ah->config.additional_swba_backoff = 0;
379 ah->config.ack_6mb = 0x0;
380 ah->config.cwm_ignore_extcca = 0;
381 ah->config.pcie_powersave_enable = 0;
382 ah->config.pcie_clock_req = 0;
383 ah->config.pcie_waen = 0;
384 ah->config.analog_shiftreg = 1;
385 ah->config.enable_ani = true;
387 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
388 ah->config.spurchans[i][0] = AR_NO_SPUR;
389 ah->config.spurchans[i][1] = AR_NO_SPUR;
392 /* PAPRD needs some more work to be enabled */
393 ah->config.paprd_disable = 1;
395 ah->config.rx_intr_mitigation = true;
396 ah->config.pcieSerDesWrite = true;
399 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
400 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
401 * This means we use it for all AR5416 devices, and the few
402 * minor PCI AR9280 devices out there.
404 * Serialization is required because these devices do not handle
405 * well the case of two concurrent reads/writes due to the latency
406 * involved. During one read/write another read/write can be issued
407 * on another CPU while the previous read/write may still be working
408 * on our hardware, if we hit this case the hardware poops in a loop.
409 * We prevent this by serializing reads and writes.
411 * This issue is not present on PCI-Express devices or pre-AR5416
412 * devices (legacy, 802.11abg).
414 if (num_possible_cpus() > 1)
415 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
418 static void ath9k_hw_init_defaults(struct ath_hw *ah)
420 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
422 regulatory->country_code = CTRY_DEFAULT;
423 regulatory->power_limit = MAX_RATE_POWER;
424 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
426 ah->hw_version.magic = AR5416_MAGIC;
427 ah->hw_version.subvendorid = 0;
430 ah->sta_id1_defaults =
431 AR_STA_ID1_CRPT_MIC_ENABLE |
432 AR_STA_ID1_MCAST_KSRCH;
433 if (AR_SREV_9100(ah))
434 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
435 ah->enable_32kHz_clock = DONT_USE_32KHZ;
437 ah->globaltxtimeout = (u32) -1;
438 ah->power_mode = ATH9K_PM_UNDEFINED;
441 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
443 struct ath_common *common = ath9k_hw_common(ah);
447 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
450 for (i = 0; i < 3; i++) {
451 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
453 common->macaddr[2 * i] = eeval >> 8;
454 common->macaddr[2 * i + 1] = eeval & 0xff;
456 if (sum == 0 || sum == 0xffff * 3)
457 return -EADDRNOTAVAIL;
462 static int ath9k_hw_post_init(struct ath_hw *ah)
464 struct ath_common *common = ath9k_hw_common(ah);
467 if (common->bus_ops->ath_bus_type != ATH_USB) {
468 if (!ath9k_hw_chip_test(ah))
472 if (!AR_SREV_9300_20_OR_LATER(ah)) {
473 ecode = ar9002_hw_rf_claim(ah);
478 ecode = ath9k_hw_eeprom_init(ah);
482 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
483 "Eeprom VER: %d, REV: %d\n",
484 ah->eep_ops->get_eeprom_ver(ah),
485 ah->eep_ops->get_eeprom_rev(ah));
487 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
489 ath_err(ath9k_hw_common(ah),
490 "Failed allocating banks for external radio\n");
491 ath9k_hw_rf_free_ext_banks(ah);
495 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
496 ath9k_hw_ani_setup(ah);
497 ath9k_hw_ani_init(ah);
503 static void ath9k_hw_attach_ops(struct ath_hw *ah)
505 if (AR_SREV_9300_20_OR_LATER(ah))
506 ar9003_hw_attach_ops(ah);
508 ar9002_hw_attach_ops(ah);
511 /* Called for all hardware families */
512 static int __ath9k_hw_init(struct ath_hw *ah)
514 struct ath_common *common = ath9k_hw_common(ah);
517 ath9k_hw_read_revisions(ah);
520 * Read back AR_WA into a permanent copy and set bits 14 and 17.
521 * We need to do this to avoid RMW of this register. We cannot
522 * read the reg when chip is asleep.
524 ah->WARegVal = REG_READ(ah, AR_WA);
525 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
526 AR_WA_ASPM_TIMER_BASED_DISABLE);
528 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
529 ath_err(common, "Couldn't reset chip\n");
533 ath9k_hw_init_defaults(ah);
534 ath9k_hw_init_config(ah);
536 ath9k_hw_attach_ops(ah);
538 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
539 ath_err(common, "Couldn't wakeup chip\n");
543 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
544 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
545 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
546 !ah->is_pciexpress)) {
547 ah->config.serialize_regmode =
550 ah->config.serialize_regmode =
555 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
556 ah->config.serialize_regmode);
558 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
559 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
561 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
563 switch (ah->hw_version.macVersion) {
564 case AR_SREV_VERSION_5416_PCI:
565 case AR_SREV_VERSION_5416_PCIE:
566 case AR_SREV_VERSION_9160:
567 case AR_SREV_VERSION_9100:
568 case AR_SREV_VERSION_9280:
569 case AR_SREV_VERSION_9285:
570 case AR_SREV_VERSION_9287:
571 case AR_SREV_VERSION_9271:
572 case AR_SREV_VERSION_9300:
573 case AR_SREV_VERSION_9330:
574 case AR_SREV_VERSION_9485:
575 case AR_SREV_VERSION_9340:
579 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
580 ah->hw_version.macVersion, ah->hw_version.macRev);
584 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
586 ah->is_pciexpress = false;
588 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
589 ath9k_hw_init_cal_settings(ah);
591 ah->ani_function = ATH9K_ANI_ALL;
592 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
593 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
594 if (!AR_SREV_9300_20_OR_LATER(ah))
595 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
597 ath9k_hw_init_mode_regs(ah);
600 if (ah->is_pciexpress)
601 ath9k_hw_configpcipowersave(ah, 0, 0);
603 ath9k_hw_disablepcie(ah);
605 if (!AR_SREV_9300_20_OR_LATER(ah))
606 ar9002_hw_cck_chan14_spread(ah);
608 r = ath9k_hw_post_init(ah);
612 ath9k_hw_init_mode_gain_regs(ah);
613 r = ath9k_hw_fill_cap_info(ah);
617 r = ath9k_hw_init_macaddr(ah);
619 ath_err(common, "Failed to initialize MAC address\n");
623 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
624 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
626 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
628 if (AR_SREV_9330(ah))
629 ah->bb_watchdog_timeout_ms = 85;
631 ah->bb_watchdog_timeout_ms = 25;
633 common->state = ATH_HW_INITIALIZED;
638 int ath9k_hw_init(struct ath_hw *ah)
641 struct ath_common *common = ath9k_hw_common(ah);
643 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
644 switch (ah->hw_version.devid) {
645 case AR5416_DEVID_PCI:
646 case AR5416_DEVID_PCIE:
647 case AR5416_AR9100_DEVID:
648 case AR9160_DEVID_PCI:
649 case AR9280_DEVID_PCI:
650 case AR9280_DEVID_PCIE:
651 case AR9285_DEVID_PCIE:
652 case AR9287_DEVID_PCI:
653 case AR9287_DEVID_PCIE:
654 case AR2427_DEVID_PCIE:
655 case AR9300_DEVID_PCIE:
656 case AR9300_DEVID_AR9485_PCIE:
657 case AR9300_DEVID_AR9330:
658 case AR9300_DEVID_AR9340:
661 if (common->bus_ops->ath_bus_type == ATH_USB)
663 ath_err(common, "Hardware device ID 0x%04x not supported\n",
664 ah->hw_version.devid);
668 ret = __ath9k_hw_init(ah);
671 "Unable to initialize hardware; initialization status: %d\n",
678 EXPORT_SYMBOL(ath9k_hw_init);
680 static void ath9k_hw_init_qos(struct ath_hw *ah)
682 ENABLE_REGWRITE_BUFFER(ah);
684 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
685 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
687 REG_WRITE(ah, AR_QOS_NO_ACK,
688 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
689 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
690 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
692 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
693 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
694 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
695 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
696 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
698 REGWRITE_BUFFER_FLUSH(ah);
701 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
703 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
705 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
707 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
710 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
712 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
714 static void ath9k_hw_init_pll(struct ath_hw *ah,
715 struct ath9k_channel *chan)
719 if (AR_SREV_9485(ah)) {
721 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
723 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
725 AR_CH0_DPLL2_KD, 0x40);
726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
727 AR_CH0_DPLL2_KI, 0x4);
729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
730 AR_CH0_BB_DPLL1_REFDIV, 0x5);
731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
732 AR_CH0_BB_DPLL1_NINI, 0x58);
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
734 AR_CH0_BB_DPLL1_NFRAC, 0x0);
736 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
737 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
738 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
739 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
741 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
743 /* program BB PLL phase_shift to 0x6 */
744 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
745 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
748 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
750 } else if (AR_SREV_9330(ah)) {
751 u32 ddr_dpll2, pll_control2, kd;
753 if (ah->is_clk_25mhz) {
754 ddr_dpll2 = 0x18e82f01;
755 pll_control2 = 0xe04a3d;
758 ddr_dpll2 = 0x19e82f01;
759 pll_control2 = 0x886666;
763 /* program DDR PLL ki and kd value */
764 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
766 /* program DDR PLL phase_shift */
767 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
768 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
770 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
773 /* program refdiv, nint, frac to RTC register */
774 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
776 /* program BB PLL kd and ki value */
777 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
778 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
780 /* program BB PLL phase_shift */
781 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
782 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
783 } else if (AR_SREV_9340(ah)) {
784 u32 regval, pll2_divint, pll2_divfrac, refdiv;
786 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
789 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
792 if (ah->is_clk_25mhz) {
794 pll2_divfrac = 0x1eb85;
802 regval = REG_READ(ah, AR_PHY_PLL_MODE);
803 regval |= (0x1 << 16);
804 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
807 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
808 (pll2_divint << 18) | pll2_divfrac);
811 regval = REG_READ(ah, AR_PHY_PLL_MODE);
812 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
813 (0x4 << 26) | (0x18 << 19);
814 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
815 REG_WRITE(ah, AR_PHY_PLL_MODE,
816 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
820 pll = ath9k_hw_compute_pll_control(ah, chan);
822 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
824 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
827 /* Switch the core clock for ar9271 to 117Mhz */
828 if (AR_SREV_9271(ah)) {
830 REG_WRITE(ah, 0x50040, 0x304);
833 udelay(RTC_PLL_SETTLE_DELAY);
835 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
837 if (AR_SREV_9340(ah)) {
838 if (ah->is_clk_25mhz) {
839 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
840 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
841 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
843 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
844 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
845 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
851 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
852 enum nl80211_iftype opmode)
854 u32 sync_default = AR_INTR_SYNC_DEFAULT;
855 u32 imr_reg = AR_IMR_TXERR |
861 if (AR_SREV_9340(ah))
862 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
864 if (AR_SREV_9300_20_OR_LATER(ah)) {
865 imr_reg |= AR_IMR_RXOK_HP;
866 if (ah->config.rx_intr_mitigation)
867 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
869 imr_reg |= AR_IMR_RXOK_LP;
872 if (ah->config.rx_intr_mitigation)
873 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
875 imr_reg |= AR_IMR_RXOK;
878 if (ah->config.tx_intr_mitigation)
879 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
881 imr_reg |= AR_IMR_TXOK;
883 if (opmode == NL80211_IFTYPE_AP)
884 imr_reg |= AR_IMR_MIB;
886 ENABLE_REGWRITE_BUFFER(ah);
888 REG_WRITE(ah, AR_IMR, imr_reg);
889 ah->imrs2_reg |= AR_IMR_S2_GTT;
890 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
892 if (!AR_SREV_9100(ah)) {
893 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
894 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
895 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
898 REGWRITE_BUFFER_FLUSH(ah);
900 if (AR_SREV_9300_20_OR_LATER(ah)) {
901 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
902 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
903 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
904 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
908 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
910 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
911 val = min(val, (u32) 0xFFFF);
912 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
915 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
917 u32 val = ath9k_hw_mac_to_clks(ah, us);
918 val = min(val, (u32) 0xFFFF);
919 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
922 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
924 u32 val = ath9k_hw_mac_to_clks(ah, us);
925 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
926 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
929 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
931 u32 val = ath9k_hw_mac_to_clks(ah, us);
932 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
933 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
936 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
939 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
940 "bad global tx timeout %u\n", tu);
941 ah->globaltxtimeout = (u32) -1;
944 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
945 ah->globaltxtimeout = tu;
950 void ath9k_hw_init_global_settings(struct ath_hw *ah)
952 struct ath_common *common = ath9k_hw_common(ah);
953 struct ieee80211_conf *conf = &common->hw->conf;
954 const struct ath9k_channel *chan = ah->curchan;
958 int rx_lat = 0, tx_lat = 0, eifs = 0;
961 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
967 if (ah->misc_mode != 0)
968 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
973 if (IS_CHAN_HALF_RATE(chan)) {
977 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
982 } else if (IS_CHAN_QUARTER_RATE(chan)) {
986 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
992 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS);
993 reg = REG_READ(ah, AR_USEC);
994 rx_lat = MS(reg, AR_USEC_RX_LAT);
995 tx_lat = MS(reg, AR_USEC_TX_LAT);
997 slottime = ah->slottime;
998 if (IS_CHAN_5GHZ(chan))
1004 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1005 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1008 * Workaround for early ACK timeouts, add an offset to match the
1009 * initval's 64us ack timeout value.
1010 * This was initially only meant to work around an issue with delayed
1011 * BA frames in some implementations, but it has been found to fix ACK
1012 * timeout issues in other cases as well.
1014 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1015 acktimeout += 64 - sifstime - ah->slottime;
1017 ath9k_hw_set_sifs_time(ah, sifstime);
1018 ath9k_hw_setslottime(ah, slottime);
1019 ath9k_hw_set_ack_timeout(ah, acktimeout);
1020 ath9k_hw_set_cts_timeout(ah, acktimeout);
1021 if (ah->globaltxtimeout != (u32) -1)
1022 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1024 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1025 REG_RMW(ah, AR_USEC,
1026 (common->clockrate - 1) |
1027 SM(rx_lat, AR_USEC_RX_LAT) |
1028 SM(tx_lat, AR_USEC_TX_LAT),
1029 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1032 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1034 void ath9k_hw_deinit(struct ath_hw *ah)
1036 struct ath_common *common = ath9k_hw_common(ah);
1038 if (common->state < ATH_HW_INITIALIZED)
1041 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1044 ath9k_hw_rf_free_ext_banks(ah);
1046 EXPORT_SYMBOL(ath9k_hw_deinit);
1052 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1054 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1056 if (IS_CHAN_B(chan))
1058 else if (IS_CHAN_G(chan))
1066 /****************************************/
1067 /* Reset and Channel Switching Routines */
1068 /****************************************/
1070 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1072 struct ath_common *common = ath9k_hw_common(ah);
1074 ENABLE_REGWRITE_BUFFER(ah);
1077 * set AHB_MODE not to do cacheline prefetches
1079 if (!AR_SREV_9300_20_OR_LATER(ah))
1080 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1083 * let mac dma reads be in 128 byte chunks
1085 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1087 REGWRITE_BUFFER_FLUSH(ah);
1090 * Restore TX Trigger Level to its pre-reset value.
1091 * The initial value depends on whether aggregation is enabled, and is
1092 * adjusted whenever underruns are detected.
1094 if (!AR_SREV_9300_20_OR_LATER(ah))
1095 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1097 ENABLE_REGWRITE_BUFFER(ah);
1100 * let mac dma writes be in 128 byte chunks
1102 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1105 * Setup receive FIFO threshold to hold off TX activities
1107 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1109 if (AR_SREV_9300_20_OR_LATER(ah)) {
1110 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1111 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1113 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1114 ah->caps.rx_status_len);
1118 * reduce the number of usable entries in PCU TXBUF to avoid
1119 * wrap around issues.
1121 if (AR_SREV_9285(ah)) {
1122 /* For AR9285 the number of Fifos are reduced to half.
1123 * So set the usable tx buf size also to half to
1124 * avoid data/delimiter underruns
1126 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1127 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1128 } else if (!AR_SREV_9271(ah)) {
1129 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1130 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1133 REGWRITE_BUFFER_FLUSH(ah);
1135 if (AR_SREV_9300_20_OR_LATER(ah))
1136 ath9k_hw_reset_txstatus_ring(ah);
1139 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1141 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1142 u32 set = AR_STA_ID1_KSRCH_MODE;
1145 case NL80211_IFTYPE_ADHOC:
1146 case NL80211_IFTYPE_MESH_POINT:
1147 set |= AR_STA_ID1_ADHOC;
1148 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1150 case NL80211_IFTYPE_AP:
1151 set |= AR_STA_ID1_STA_AP;
1153 case NL80211_IFTYPE_STATION:
1154 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1157 if (!ah->is_monitoring)
1161 REG_RMW(ah, AR_STA_ID1, set, mask);
1164 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1165 u32 *coef_mantissa, u32 *coef_exponent)
1167 u32 coef_exp, coef_man;
1169 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1170 if ((coef_scaled >> coef_exp) & 0x1)
1173 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1175 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1177 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1178 *coef_exponent = coef_exp - 16;
1181 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1186 if (AR_SREV_9100(ah)) {
1187 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1188 AR_RTC_DERIVED_CLK_PERIOD, 1);
1189 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1192 ENABLE_REGWRITE_BUFFER(ah);
1194 if (AR_SREV_9300_20_OR_LATER(ah)) {
1195 REG_WRITE(ah, AR_WA, ah->WARegVal);
1199 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1200 AR_RTC_FORCE_WAKE_ON_INT);
1202 if (AR_SREV_9100(ah)) {
1203 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1204 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1206 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1208 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1209 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1211 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1214 if (!AR_SREV_9300_20_OR_LATER(ah))
1216 REG_WRITE(ah, AR_RC, val);
1218 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1219 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1221 rst_flags = AR_RTC_RC_MAC_WARM;
1222 if (type == ATH9K_RESET_COLD)
1223 rst_flags |= AR_RTC_RC_MAC_COLD;
1226 if (AR_SREV_9330(ah)) {
1231 * call external reset function to reset WMAC if:
1232 * - doing a cold reset
1233 * - we have pending frames in the TX queues
1236 for (i = 0; i < AR_NUM_QCU; i++) {
1237 npend = ath9k_hw_numtxpending(ah, i);
1242 if (ah->external_reset &&
1243 (npend || type == ATH9K_RESET_COLD)) {
1246 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1247 "reset MAC via external reset\n");
1249 reset_err = ah->external_reset();
1251 ath_err(ath9k_hw_common(ah),
1252 "External reset failed, err=%d\n",
1257 REG_WRITE(ah, AR_RTC_RESET, 1);
1261 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1263 REGWRITE_BUFFER_FLUSH(ah);
1267 REG_WRITE(ah, AR_RTC_RC, 0);
1268 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1269 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1270 "RTC stuck in MAC reset\n");
1274 if (!AR_SREV_9100(ah))
1275 REG_WRITE(ah, AR_RC, 0);
1277 if (AR_SREV_9100(ah))
1283 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1285 ENABLE_REGWRITE_BUFFER(ah);
1287 if (AR_SREV_9300_20_OR_LATER(ah)) {
1288 REG_WRITE(ah, AR_WA, ah->WARegVal);
1292 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1293 AR_RTC_FORCE_WAKE_ON_INT);
1295 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1296 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1298 REG_WRITE(ah, AR_RTC_RESET, 0);
1300 REGWRITE_BUFFER_FLUSH(ah);
1302 if (!AR_SREV_9300_20_OR_LATER(ah))
1305 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1306 REG_WRITE(ah, AR_RC, 0);
1308 REG_WRITE(ah, AR_RTC_RESET, 1);
1310 if (!ath9k_hw_wait(ah,
1315 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1316 "RTC not waking up\n");
1320 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1323 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1325 if (AR_SREV_9300_20_OR_LATER(ah)) {
1326 REG_WRITE(ah, AR_WA, ah->WARegVal);
1330 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1331 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1334 case ATH9K_RESET_POWER_ON:
1335 return ath9k_hw_set_reset_power_on(ah);
1336 case ATH9K_RESET_WARM:
1337 case ATH9K_RESET_COLD:
1338 return ath9k_hw_set_reset(ah, type);
1344 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1345 struct ath9k_channel *chan)
1347 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1348 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1350 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1353 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1356 ah->chip_fullsleep = false;
1357 ath9k_hw_init_pll(ah, chan);
1358 ath9k_hw_set_rfmode(ah, chan);
1363 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1364 struct ath9k_channel *chan)
1366 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1367 struct ath_common *common = ath9k_hw_common(ah);
1368 struct ieee80211_channel *channel = chan->chan;
1372 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1373 if (ath9k_hw_numtxpending(ah, qnum)) {
1374 ath_dbg(common, ATH_DBG_QUEUE,
1375 "Transmit frames pending on queue %d\n", qnum);
1380 if (!ath9k_hw_rfbus_req(ah)) {
1381 ath_err(common, "Could not kill baseband RX\n");
1385 ath9k_hw_set_channel_regs(ah, chan);
1387 r = ath9k_hw_rf_set_freq(ah, chan);
1389 ath_err(common, "Failed to set channel\n");
1392 ath9k_hw_set_clockrate(ah);
1394 ah->eep_ops->set_txpower(ah, chan,
1395 ath9k_regd_get_ctl(regulatory, chan),
1396 channel->max_antenna_gain * 2,
1397 channel->max_power * 2,
1398 min((u32) MAX_RATE_POWER,
1399 (u32) regulatory->power_limit), false);
1401 ath9k_hw_rfbus_done(ah);
1403 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1404 ath9k_hw_set_delta_slope(ah, chan);
1406 ath9k_hw_spur_mitigate_freq(ah, chan);
1411 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1413 u32 gpio_mask = ah->gpio_mask;
1416 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1417 if (!(gpio_mask & 1))
1420 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1421 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1425 bool ath9k_hw_check_alive(struct ath_hw *ah)
1430 if (AR_SREV_9285_12_OR_LATER(ah))
1434 reg = REG_READ(ah, AR_OBS_BUS_1);
1436 if ((reg & 0x7E7FFFEF) == 0x00702400)
1439 switch (reg & 0x7E000B00) {
1447 } while (count-- > 0);
1451 EXPORT_SYMBOL(ath9k_hw_check_alive);
1453 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1454 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1456 struct ath_common *common = ath9k_hw_common(ah);
1458 struct ath9k_channel *curchan = ah->curchan;
1464 ah->txchainmask = common->tx_chainmask;
1465 ah->rxchainmask = common->rx_chainmask;
1467 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1470 if (curchan && !ah->chip_fullsleep)
1471 ath9k_hw_getnf(ah, curchan);
1473 ah->caldata = caldata;
1475 (chan->channel != caldata->channel ||
1476 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1477 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1478 /* Operating channel changed, reset channel calibration data */
1479 memset(caldata, 0, sizeof(*caldata));
1480 ath9k_init_nfcal_hist_buffer(ah, chan);
1483 if (bChannelChange &&
1484 (ah->chip_fullsleep != true) &&
1485 (ah->curchan != NULL) &&
1486 (chan->channel != ah->curchan->channel) &&
1487 ((chan->channelFlags & CHANNEL_ALL) ==
1488 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1489 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1491 if (ath9k_hw_channel_change(ah, chan)) {
1492 ath9k_hw_loadnf(ah, ah->curchan);
1493 ath9k_hw_start_nfcal(ah, true);
1494 if (AR_SREV_9271(ah))
1495 ar9002_hw_load_ani_reg(ah, chan);
1500 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1501 if (saveDefAntenna == 0)
1504 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1506 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1507 if (AR_SREV_9100(ah) ||
1508 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1509 tsf = ath9k_hw_gettsf64(ah);
1511 saveLedState = REG_READ(ah, AR_CFG_LED) &
1512 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1513 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1515 ath9k_hw_mark_phy_inactive(ah);
1517 ah->paprd_table_write_done = false;
1519 /* Only required on the first reset */
1520 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1522 AR9271_RESET_POWER_DOWN_CONTROL,
1523 AR9271_RADIO_RF_RST);
1527 if (!ath9k_hw_chip_reset(ah, chan)) {
1528 ath_err(common, "Chip reset failed\n");
1532 /* Only required on the first reset */
1533 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1534 ah->htc_reset_init = false;
1536 AR9271_RESET_POWER_DOWN_CONTROL,
1537 AR9271_GATE_MAC_CTL);
1543 ath9k_hw_settsf64(ah, tsf);
1545 if (AR_SREV_9280_20_OR_LATER(ah))
1546 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1548 if (!AR_SREV_9300_20_OR_LATER(ah))
1549 ar9002_hw_enable_async_fifo(ah);
1551 r = ath9k_hw_process_ini(ah, chan);
1556 * Some AR91xx SoC devices frequently fail to accept TSF writes
1557 * right after the chip reset. When that happens, write a new
1558 * value after the initvals have been applied, with an offset
1559 * based on measured time difference
1561 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1563 ath9k_hw_settsf64(ah, tsf);
1566 /* Setup MFP options for CCMP */
1567 if (AR_SREV_9280_20_OR_LATER(ah)) {
1568 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1569 * frames when constructing CCMP AAD. */
1570 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1572 ah->sw_mgmt_crypto = false;
1573 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1574 /* Disable hardware crypto for management frames */
1575 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1576 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1577 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1578 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1579 ah->sw_mgmt_crypto = true;
1581 ah->sw_mgmt_crypto = true;
1583 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1584 ath9k_hw_set_delta_slope(ah, chan);
1586 ath9k_hw_spur_mitigate_freq(ah, chan);
1587 ah->eep_ops->set_board_values(ah, chan);
1589 ENABLE_REGWRITE_BUFFER(ah);
1591 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1592 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1594 | AR_STA_ID1_RTS_USE_DEF
1596 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1597 | ah->sta_id1_defaults);
1598 ath_hw_setbssidmask(common);
1599 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1600 ath9k_hw_write_associd(ah);
1601 REG_WRITE(ah, AR_ISR, ~0);
1602 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1604 REGWRITE_BUFFER_FLUSH(ah);
1606 ath9k_hw_set_operating_mode(ah, ah->opmode);
1608 r = ath9k_hw_rf_set_freq(ah, chan);
1612 ath9k_hw_set_clockrate(ah);
1614 ENABLE_REGWRITE_BUFFER(ah);
1616 for (i = 0; i < AR_NUM_DCU; i++)
1617 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1619 REGWRITE_BUFFER_FLUSH(ah);
1622 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1623 ath9k_hw_resettxqueue(ah, i);
1625 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1626 ath9k_hw_ani_cache_ini_regs(ah);
1627 ath9k_hw_init_qos(ah);
1629 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1630 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1632 ath9k_hw_init_global_settings(ah);
1634 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1635 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1636 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1637 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1638 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1639 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1640 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1643 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1645 ath9k_hw_set_dma(ah);
1647 REG_WRITE(ah, AR_OBS, 8);
1649 if (ah->config.rx_intr_mitigation) {
1650 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1651 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1654 if (ah->config.tx_intr_mitigation) {
1655 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1656 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1659 ath9k_hw_init_bb(ah, chan);
1661 if (!ath9k_hw_init_cal(ah, chan))
1664 ENABLE_REGWRITE_BUFFER(ah);
1666 ath9k_hw_restore_chainmask(ah);
1667 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1669 REGWRITE_BUFFER_FLUSH(ah);
1672 * For big endian systems turn on swapping for descriptors
1674 if (AR_SREV_9100(ah)) {
1676 mask = REG_READ(ah, AR_CFG);
1677 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1678 ath_dbg(common, ATH_DBG_RESET,
1679 "CFG Byte Swap Set 0x%x\n", mask);
1682 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1683 REG_WRITE(ah, AR_CFG, mask);
1684 ath_dbg(common, ATH_DBG_RESET,
1685 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1688 if (common->bus_ops->ath_bus_type == ATH_USB) {
1689 /* Configure AR9271 target WLAN */
1690 if (AR_SREV_9271(ah))
1691 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1693 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1696 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1697 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1699 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1703 if (ah->btcoex_hw.enabled)
1704 ath9k_hw_btcoex_enable(ah);
1706 if (AR_SREV_9300_20_OR_LATER(ah)) {
1707 ar9003_hw_bb_watchdog_config(ah);
1709 ar9003_hw_disable_phy_restart(ah);
1712 ath9k_hw_apply_gpio_override(ah);
1716 EXPORT_SYMBOL(ath9k_hw_reset);
1718 /******************************/
1719 /* Power Management (Chipset) */
1720 /******************************/
1723 * Notify Power Mgt is disabled in self-generated frames.
1724 * If requested, force chip to sleep.
1726 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1728 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1731 * Clear the RTC force wake bit to allow the
1732 * mac to go to sleep.
1734 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1735 AR_RTC_FORCE_WAKE_EN);
1736 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1737 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1739 /* Shutdown chip. Active low */
1740 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1741 REG_CLR_BIT(ah, (AR_RTC_RESET),
1745 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1746 if (AR_SREV_9300_20_OR_LATER(ah))
1747 REG_WRITE(ah, AR_WA,
1748 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1752 * Notify Power Management is enabled in self-generating
1753 * frames. If request, set power mode of chip to
1754 * auto/normal. Duration in units of 128us (1/8 TU).
1756 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1758 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1760 struct ath9k_hw_capabilities *pCap = &ah->caps;
1762 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1763 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1764 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1765 AR_RTC_FORCE_WAKE_ON_INT);
1768 * Clear the RTC force wake bit to allow the
1769 * mac to go to sleep.
1771 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1772 AR_RTC_FORCE_WAKE_EN);
1776 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1777 if (AR_SREV_9300_20_OR_LATER(ah))
1778 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1781 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1786 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1787 if (AR_SREV_9300_20_OR_LATER(ah)) {
1788 REG_WRITE(ah, AR_WA, ah->WARegVal);
1793 if ((REG_READ(ah, AR_RTC_STATUS) &
1794 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1795 if (ath9k_hw_set_reset_reg(ah,
1796 ATH9K_RESET_POWER_ON) != true) {
1799 if (!AR_SREV_9300_20_OR_LATER(ah))
1800 ath9k_hw_init_pll(ah, NULL);
1802 if (AR_SREV_9100(ah))
1803 REG_SET_BIT(ah, AR_RTC_RESET,
1806 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1807 AR_RTC_FORCE_WAKE_EN);
1810 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1811 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1812 if (val == AR_RTC_STATUS_ON)
1815 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1816 AR_RTC_FORCE_WAKE_EN);
1819 ath_err(ath9k_hw_common(ah),
1820 "Failed to wakeup in %uus\n",
1821 POWER_UP_TIME / 20);
1826 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1831 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1833 struct ath_common *common = ath9k_hw_common(ah);
1834 int status = true, setChip = true;
1835 static const char *modes[] = {
1842 if (ah->power_mode == mode)
1845 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1846 modes[ah->power_mode], modes[mode]);
1849 case ATH9K_PM_AWAKE:
1850 status = ath9k_hw_set_power_awake(ah, setChip);
1852 case ATH9K_PM_FULL_SLEEP:
1853 ath9k_set_power_sleep(ah, setChip);
1854 ah->chip_fullsleep = true;
1856 case ATH9K_PM_NETWORK_SLEEP:
1857 ath9k_set_power_network_sleep(ah, setChip);
1860 ath_err(common, "Unknown power mode %u\n", mode);
1863 ah->power_mode = mode;
1866 * XXX: If this warning never comes up after a while then
1867 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1868 * ath9k_hw_setpower() return type void.
1871 if (!(ah->ah_flags & AH_UNPLUGGED))
1872 ATH_DBG_WARN_ON_ONCE(!status);
1876 EXPORT_SYMBOL(ath9k_hw_setpower);
1878 /*******************/
1879 /* Beacon Handling */
1880 /*******************/
1882 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1886 ENABLE_REGWRITE_BUFFER(ah);
1888 switch (ah->opmode) {
1889 case NL80211_IFTYPE_ADHOC:
1890 case NL80211_IFTYPE_MESH_POINT:
1891 REG_SET_BIT(ah, AR_TXCFG,
1892 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1893 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1894 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1895 flags |= AR_NDP_TIMER_EN;
1896 case NL80211_IFTYPE_AP:
1897 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1898 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1899 TU_TO_USEC(ah->config.dma_beacon_response_time));
1900 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1901 TU_TO_USEC(ah->config.sw_beacon_response_time));
1903 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1906 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1907 "%s: unsupported opmode: %d\n",
1908 __func__, ah->opmode);
1913 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1914 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1915 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1916 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1918 REGWRITE_BUFFER_FLUSH(ah);
1920 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1922 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1924 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1925 const struct ath9k_beacon_state *bs)
1927 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1928 struct ath9k_hw_capabilities *pCap = &ah->caps;
1929 struct ath_common *common = ath9k_hw_common(ah);
1931 ENABLE_REGWRITE_BUFFER(ah);
1933 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1935 REG_WRITE(ah, AR_BEACON_PERIOD,
1936 TU_TO_USEC(bs->bs_intval));
1937 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1938 TU_TO_USEC(bs->bs_intval));
1940 REGWRITE_BUFFER_FLUSH(ah);
1942 REG_RMW_FIELD(ah, AR_RSSI_THR,
1943 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1945 beaconintval = bs->bs_intval;
1947 if (bs->bs_sleepduration > beaconintval)
1948 beaconintval = bs->bs_sleepduration;
1950 dtimperiod = bs->bs_dtimperiod;
1951 if (bs->bs_sleepduration > dtimperiod)
1952 dtimperiod = bs->bs_sleepduration;
1954 if (beaconintval == dtimperiod)
1955 nextTbtt = bs->bs_nextdtim;
1957 nextTbtt = bs->bs_nexttbtt;
1959 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1960 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1961 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1962 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1964 ENABLE_REGWRITE_BUFFER(ah);
1966 REG_WRITE(ah, AR_NEXT_DTIM,
1967 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1968 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1970 REG_WRITE(ah, AR_SLEEP1,
1971 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1972 | AR_SLEEP1_ASSUME_DTIM);
1974 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1975 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1977 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1979 REG_WRITE(ah, AR_SLEEP2,
1980 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1982 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1983 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1985 REGWRITE_BUFFER_FLUSH(ah);
1987 REG_SET_BIT(ah, AR_TIMER_MODE,
1988 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1991 /* TSF Out of Range Threshold */
1992 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1994 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1996 /*******************/
1997 /* HW Capabilities */
1998 /*******************/
2000 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2002 eeprom_chainmask &= chip_chainmask;
2003 if (eeprom_chainmask)
2004 return eeprom_chainmask;
2006 return chip_chainmask;
2009 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2011 struct ath9k_hw_capabilities *pCap = &ah->caps;
2012 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2013 struct ath_common *common = ath9k_hw_common(ah);
2014 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2015 unsigned int chip_chainmask;
2018 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2020 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2021 regulatory->current_rd = eeval;
2023 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2024 if (AR_SREV_9285_12_OR_LATER(ah))
2025 eeval |= AR9285_RDEXT_DEFAULT;
2026 regulatory->current_rd_ext = eeval;
2028 if (ah->opmode != NL80211_IFTYPE_AP &&
2029 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2030 if (regulatory->current_rd == 0x64 ||
2031 regulatory->current_rd == 0x65)
2032 regulatory->current_rd += 5;
2033 else if (regulatory->current_rd == 0x41)
2034 regulatory->current_rd = 0x43;
2035 ath_dbg(common, ATH_DBG_REGULATORY,
2036 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2039 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2040 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2042 "no band has been marked as supported in EEPROM\n");
2046 if (eeval & AR5416_OPFLAGS_11A)
2047 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2049 if (eeval & AR5416_OPFLAGS_11G)
2050 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2052 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2054 else if (!AR_SREV_9280_20_OR_LATER(ah))
2056 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2061 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2063 * For AR9271 we will temporarilly uses the rx chainmax as read from
2066 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2067 !(eeval & AR5416_OPFLAGS_11A) &&
2068 !(AR_SREV_9271(ah)))
2069 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2070 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2071 else if (AR_SREV_9100(ah))
2072 pCap->rx_chainmask = 0x7;
2074 /* Use rx_chainmask from EEPROM. */
2075 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2077 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2078 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2080 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2082 /* enable key search for every frame in an aggregate */
2083 if (AR_SREV_9300_20_OR_LATER(ah))
2084 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2086 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2088 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2089 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2091 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2093 if (AR_SREV_9271(ah))
2094 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2095 else if (AR_DEVID_7010(ah))
2096 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2097 else if (AR_SREV_9285_12_OR_LATER(ah))
2098 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2099 else if (AR_SREV_9280_20_OR_LATER(ah))
2100 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2102 pCap->num_gpio_pins = AR_NUM_GPIO;
2104 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2105 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2106 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2108 pCap->rts_aggr_limit = (8 * 1024);
2111 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2112 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2113 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2115 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2116 ah->rfkill_polarity =
2117 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2119 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2122 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2123 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2125 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2127 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2128 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2130 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2132 if (common->btcoex_enabled) {
2133 if (AR_SREV_9300_20_OR_LATER(ah)) {
2134 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2135 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2136 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2137 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2138 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2139 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2140 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2142 if (AR_SREV_9285(ah)) {
2143 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2144 btcoex_hw->btpriority_gpio =
2145 ATH_BTPRIORITY_GPIO_9285;
2147 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2151 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2154 if (AR_SREV_9300_20_OR_LATER(ah)) {
2155 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2156 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2157 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2159 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2160 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2161 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2162 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2163 pCap->txs_len = sizeof(struct ar9003_txs);
2164 if (!ah->config.paprd_disable &&
2165 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2166 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2168 pCap->tx_desc_len = sizeof(struct ath_desc);
2169 if (AR_SREV_9280_20(ah))
2170 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2173 if (AR_SREV_9300_20_OR_LATER(ah))
2174 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2176 if (AR_SREV_9300_20_OR_LATER(ah))
2177 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2179 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2180 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2182 if (AR_SREV_9285(ah))
2183 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2185 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2186 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2187 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2189 if (AR_SREV_9300_20_OR_LATER(ah)) {
2190 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2191 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2195 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2196 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2198 * enable the diversity-combining algorithm only when
2199 * both enable_lna_div and enable_fast_div are set
2200 * Table for Diversity
2201 * ant_div_alt_lnaconf bit 0-1
2202 * ant_div_main_lnaconf bit 2-3
2203 * ant_div_alt_gaintb bit 4
2204 * ant_div_main_gaintb bit 5
2205 * enable_ant_div_lnadiv bit 6
2206 * enable_ant_fast_div bit 7
2208 if ((ant_div_ctl1 >> 0x6) == 0x3)
2209 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2212 if (AR_SREV_9485_10(ah)) {
2213 pCap->pcie_lcr_extsync_en = true;
2214 pCap->pcie_lcr_offset = 0x80;
2217 tx_chainmask = pCap->tx_chainmask;
2218 rx_chainmask = pCap->rx_chainmask;
2219 while (tx_chainmask || rx_chainmask) {
2220 if (tx_chainmask & BIT(0))
2221 pCap->max_txchains++;
2222 if (rx_chainmask & BIT(0))
2223 pCap->max_rxchains++;
2232 /****************************/
2233 /* GPIO / RFKILL / Antennae */
2234 /****************************/
2236 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2240 u32 gpio_shift, tmp;
2243 addr = AR_GPIO_OUTPUT_MUX3;
2245 addr = AR_GPIO_OUTPUT_MUX2;
2247 addr = AR_GPIO_OUTPUT_MUX1;
2249 gpio_shift = (gpio % 6) * 5;
2251 if (AR_SREV_9280_20_OR_LATER(ah)
2252 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2253 REG_RMW(ah, addr, (type << gpio_shift),
2254 (0x1f << gpio_shift));
2256 tmp = REG_READ(ah, addr);
2257 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2258 tmp &= ~(0x1f << gpio_shift);
2259 tmp |= (type << gpio_shift);
2260 REG_WRITE(ah, addr, tmp);
2264 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2268 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2270 if (AR_DEVID_7010(ah)) {
2272 REG_RMW(ah, AR7010_GPIO_OE,
2273 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2274 (AR7010_GPIO_OE_MASK << gpio_shift));
2278 gpio_shift = gpio << 1;
2281 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2282 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2284 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2286 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2288 #define MS_REG_READ(x, y) \
2289 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2291 if (gpio >= ah->caps.num_gpio_pins)
2294 if (AR_DEVID_7010(ah)) {
2296 val = REG_READ(ah, AR7010_GPIO_IN);
2297 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2298 } else if (AR_SREV_9300_20_OR_LATER(ah))
2299 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2300 AR_GPIO_BIT(gpio)) != 0;
2301 else if (AR_SREV_9271(ah))
2302 return MS_REG_READ(AR9271, gpio) != 0;
2303 else if (AR_SREV_9287_11_OR_LATER(ah))
2304 return MS_REG_READ(AR9287, gpio) != 0;
2305 else if (AR_SREV_9285_12_OR_LATER(ah))
2306 return MS_REG_READ(AR9285, gpio) != 0;
2307 else if (AR_SREV_9280_20_OR_LATER(ah))
2308 return MS_REG_READ(AR928X, gpio) != 0;
2310 return MS_REG_READ(AR, gpio) != 0;
2312 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2314 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2319 if (AR_DEVID_7010(ah)) {
2321 REG_RMW(ah, AR7010_GPIO_OE,
2322 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2323 (AR7010_GPIO_OE_MASK << gpio_shift));
2327 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2328 gpio_shift = 2 * gpio;
2331 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2332 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2334 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2336 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2338 if (AR_DEVID_7010(ah)) {
2340 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2345 if (AR_SREV_9271(ah))
2348 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2351 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2353 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2355 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2357 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2359 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2361 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2363 EXPORT_SYMBOL(ath9k_hw_setantenna);
2365 /*********************/
2366 /* General Operation */
2367 /*********************/
2369 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2371 u32 bits = REG_READ(ah, AR_RX_FILTER);
2372 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2374 if (phybits & AR_PHY_ERR_RADAR)
2375 bits |= ATH9K_RX_FILTER_PHYRADAR;
2376 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2377 bits |= ATH9K_RX_FILTER_PHYERR;
2381 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2383 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2387 ENABLE_REGWRITE_BUFFER(ah);
2389 REG_WRITE(ah, AR_RX_FILTER, bits);
2392 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2393 phybits |= AR_PHY_ERR_RADAR;
2394 if (bits & ATH9K_RX_FILTER_PHYERR)
2395 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2396 REG_WRITE(ah, AR_PHY_ERR, phybits);
2399 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2401 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2403 REGWRITE_BUFFER_FLUSH(ah);
2405 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2407 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2409 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2412 ath9k_hw_init_pll(ah, NULL);
2415 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2417 bool ath9k_hw_disable(struct ath_hw *ah)
2419 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2422 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2425 ath9k_hw_init_pll(ah, NULL);
2428 EXPORT_SYMBOL(ath9k_hw_disable);
2430 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2432 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2433 struct ath9k_channel *chan = ah->curchan;
2434 struct ieee80211_channel *channel = chan->chan;
2436 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2438 ah->eep_ops->set_txpower(ah, chan,
2439 ath9k_regd_get_ctl(regulatory, chan),
2440 channel->max_antenna_gain * 2,
2441 channel->max_power * 2,
2442 min((u32) MAX_RATE_POWER,
2443 (u32) regulatory->power_limit), test);
2445 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2447 void ath9k_hw_setopmode(struct ath_hw *ah)
2449 ath9k_hw_set_operating_mode(ah, ah->opmode);
2451 EXPORT_SYMBOL(ath9k_hw_setopmode);
2453 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2455 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2456 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2458 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2460 void ath9k_hw_write_associd(struct ath_hw *ah)
2462 struct ath_common *common = ath9k_hw_common(ah);
2464 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2465 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2466 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2468 EXPORT_SYMBOL(ath9k_hw_write_associd);
2470 #define ATH9K_MAX_TSF_READ 10
2472 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2474 u32 tsf_lower, tsf_upper1, tsf_upper2;
2477 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2478 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2479 tsf_lower = REG_READ(ah, AR_TSF_L32);
2480 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2481 if (tsf_upper2 == tsf_upper1)
2483 tsf_upper1 = tsf_upper2;
2486 WARN_ON( i == ATH9K_MAX_TSF_READ );
2488 return (((u64)tsf_upper1 << 32) | tsf_lower);
2490 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2492 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2494 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2495 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2497 EXPORT_SYMBOL(ath9k_hw_settsf64);
2499 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2501 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2502 AH_TSF_WRITE_TIMEOUT))
2503 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2504 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2506 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2508 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2510 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2513 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2515 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2517 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2519 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2521 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2524 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2525 macmode = AR_2040_JOINED_RX_CLEAR;
2529 REG_WRITE(ah, AR_2040_MODE, macmode);
2532 /* HW Generic timers configuration */
2534 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2536 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2537 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2538 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2539 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2540 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2541 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2542 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2543 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2544 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2545 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2546 AR_NDP2_TIMER_MODE, 0x0002},
2547 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2548 AR_NDP2_TIMER_MODE, 0x0004},
2549 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2550 AR_NDP2_TIMER_MODE, 0x0008},
2551 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2552 AR_NDP2_TIMER_MODE, 0x0010},
2553 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2554 AR_NDP2_TIMER_MODE, 0x0020},
2555 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2556 AR_NDP2_TIMER_MODE, 0x0040},
2557 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2558 AR_NDP2_TIMER_MODE, 0x0080}
2561 /* HW generic timer primitives */
2563 /* compute and clear index of rightmost 1 */
2564 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2574 return timer_table->gen_timer_index[b];
2577 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2579 return REG_READ(ah, AR_TSF_L32);
2581 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2583 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2584 void (*trigger)(void *),
2585 void (*overflow)(void *),
2589 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2590 struct ath_gen_timer *timer;
2592 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2594 if (timer == NULL) {
2595 ath_err(ath9k_hw_common(ah),
2596 "Failed to allocate memory for hw timer[%d]\n",
2601 /* allocate a hardware generic timer slot */
2602 timer_table->timers[timer_index] = timer;
2603 timer->index = timer_index;
2604 timer->trigger = trigger;
2605 timer->overflow = overflow;
2610 EXPORT_SYMBOL(ath_gen_timer_alloc);
2612 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2613 struct ath_gen_timer *timer,
2617 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2618 u32 tsf, timer_next;
2620 BUG_ON(!timer_period);
2622 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2624 tsf = ath9k_hw_gettsf32(ah);
2626 timer_next = tsf + trig_timeout;
2628 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2629 "current tsf %x period %x timer_next %x\n",
2630 tsf, timer_period, timer_next);
2633 * Program generic timer registers
2635 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2637 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2639 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2640 gen_tmr_configuration[timer->index].mode_mask);
2642 /* Enable both trigger and thresh interrupt masks */
2643 REG_SET_BIT(ah, AR_IMR_S5,
2644 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2645 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2647 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2649 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2651 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2653 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2654 (timer->index >= ATH_MAX_GEN_TIMER)) {
2658 /* Clear generic timer enable bits. */
2659 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2660 gen_tmr_configuration[timer->index].mode_mask);
2662 /* Disable both trigger and thresh interrupt masks */
2663 REG_CLR_BIT(ah, AR_IMR_S5,
2664 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2665 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2667 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2669 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2671 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2673 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2675 /* free the hardware generic timer slot */
2676 timer_table->timers[timer->index] = NULL;
2679 EXPORT_SYMBOL(ath_gen_timer_free);
2682 * Generic Timer Interrupts handling
2684 void ath_gen_timer_isr(struct ath_hw *ah)
2686 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2687 struct ath_gen_timer *timer;
2688 struct ath_common *common = ath9k_hw_common(ah);
2689 u32 trigger_mask, thresh_mask, index;
2691 /* get hardware generic timer interrupt status */
2692 trigger_mask = ah->intr_gen_timer_trigger;
2693 thresh_mask = ah->intr_gen_timer_thresh;
2694 trigger_mask &= timer_table->timer_mask.val;
2695 thresh_mask &= timer_table->timer_mask.val;
2697 trigger_mask &= ~thresh_mask;
2699 while (thresh_mask) {
2700 index = rightmost_index(timer_table, &thresh_mask);
2701 timer = timer_table->timers[index];
2703 ath_dbg(common, ATH_DBG_HWTIMER,
2704 "TSF overflow for Gen timer %d\n", index);
2705 timer->overflow(timer->arg);
2708 while (trigger_mask) {
2709 index = rightmost_index(timer_table, &trigger_mask);
2710 timer = timer_table->timers[index];
2712 ath_dbg(common, ATH_DBG_HWTIMER,
2713 "Gen timer[%d] trigger\n", index);
2714 timer->trigger(timer->arg);
2717 EXPORT_SYMBOL(ath_gen_timer_isr);
2723 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2725 ah->htc_reset_init = true;
2727 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2732 } ath_mac_bb_names[] = {
2733 /* Devices with external radios */
2734 { AR_SREV_VERSION_5416_PCI, "5416" },
2735 { AR_SREV_VERSION_5416_PCIE, "5418" },
2736 { AR_SREV_VERSION_9100, "9100" },
2737 { AR_SREV_VERSION_9160, "9160" },
2738 /* Single-chip solutions */
2739 { AR_SREV_VERSION_9280, "9280" },
2740 { AR_SREV_VERSION_9285, "9285" },
2741 { AR_SREV_VERSION_9287, "9287" },
2742 { AR_SREV_VERSION_9271, "9271" },
2743 { AR_SREV_VERSION_9300, "9300" },
2744 { AR_SREV_VERSION_9330, "9330" },
2745 { AR_SREV_VERSION_9485, "9485" },
2748 /* For devices with external radios */
2752 } ath_rf_names[] = {
2754 { AR_RAD5133_SREV_MAJOR, "5133" },
2755 { AR_RAD5122_SREV_MAJOR, "5122" },
2756 { AR_RAD2133_SREV_MAJOR, "2133" },
2757 { AR_RAD2122_SREV_MAJOR, "2122" }
2761 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2763 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2767 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2768 if (ath_mac_bb_names[i].version == mac_bb_version) {
2769 return ath_mac_bb_names[i].name;
2777 * Return the RF name. "????" is returned if the RF is unknown.
2778 * Used for devices with external radios.
2780 static const char *ath9k_hw_rf_name(u16 rf_version)
2784 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2785 if (ath_rf_names[i].version == rf_version) {
2786 return ath_rf_names[i].name;
2793 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2797 /* chipsets >= AR9280 are single-chip */
2798 if (AR_SREV_9280_20_OR_LATER(ah)) {
2799 used = snprintf(hw_name, len,
2800 "Atheros AR%s Rev:%x",
2801 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2802 ah->hw_version.macRev);
2805 used = snprintf(hw_name, len,
2806 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2807 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2808 ah->hw_version.macRev,
2809 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2810 AR_RADIO_SREV_MAJOR)),
2811 ah->hw_version.phyRev);
2814 hw_name[used] = '\0';
2816 EXPORT_SYMBOL(ath9k_hw_name);