2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init ath9k_init(void)
37 module_init(ath9k_init);
39 static void __exit ath9k_exit(void)
43 module_exit(ath9k_exit);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
59 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
61 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
65 struct ath9k_channel *chan)
67 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
72 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
80 /* You will not have this callback if using the old ANI */
81 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
84 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
87 /********************/
88 /* Helper Functions */
89 /********************/
91 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
93 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
94 struct ath_common *common = ath9k_hw_common(ah);
95 unsigned int clockrate;
97 if (!ah->curchan) /* should really check for CCK instead */
98 clockrate = ATH9K_CLOCK_RATE_CCK;
99 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
100 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
101 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
102 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
104 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
106 if (conf_is_ht40(conf))
109 common->clockrate = clockrate;
112 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
114 struct ath_common *common = ath9k_hw_common(ah);
116 return usecs * common->clockrate;
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 BUG_ON(timeout < AH_TIME_QUANTUM);
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
129 udelay(AH_TIME_QUANTUM);
132 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
138 EXPORT_SYMBOL(ath9k_hw_wait);
140 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
145 for (i = 0, retval = 0; i < n; i++) {
146 retval = (retval << 1) | (val & 1);
152 bool ath9k_get_channel_edges(struct ath_hw *ah,
156 struct ath9k_hw_capabilities *pCap = &ah->caps;
158 if (flags & CHANNEL_5GHZ) {
159 *low = pCap->low_5ghz_chan;
160 *high = pCap->high_5ghz_chan;
163 if ((flags & CHANNEL_2GHZ)) {
164 *low = pCap->low_2ghz_chan;
165 *high = pCap->high_2ghz_chan;
171 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
173 u32 frameLen, u16 rateix,
176 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
182 case WLAN_RC_PHY_CCK:
183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
189 case WLAN_RC_PHY_OFDM:
190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
214 ath_err(ath9k_hw_common(ah),
215 "Unknown phy %u (rate ix %u)\n", phy, rateix);
222 EXPORT_SYMBOL(ath9k_hw_computetxtime);
224 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
249 /* 25 MHz spacing is supported by hw but not on upper layers */
250 centers->ext_center =
251 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
258 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
265 val = REG_READ(ah, AR_SREV);
266 ah->hw_version.macVersion =
267 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
269 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
271 if (!AR_SREV_9100(ah))
272 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
274 ah->hw_version.macRev = val & AR_SREV_REVISION;
276 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
277 ah->is_pciexpress = true;
281 /************************************/
282 /* HW Attach, Detach, Init Routines */
283 /************************************/
285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
287 if (AR_SREV_9100(ah))
290 ENABLE_REGWRITE_BUFFER(ah);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
300 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
302 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
304 REGWRITE_BUFFER_FLUSH(ah);
307 /* This should work for all families including legacy */
308 static bool ath9k_hw_chip_test(struct ath_hw *ah)
310 struct ath_common *common = ath9k_hw_common(ah);
311 u32 regAddr[2] = { AR_STA_ID0 };
313 static const u32 patternData[4] = {
314 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
318 if (!AR_SREV_9300_20_OR_LATER(ah)) {
320 regAddr[1] = AR_PHY_BASE + (8 << 2);
324 for (i = 0; i < loop_max; i++) {
325 u32 addr = regAddr[i];
328 regHold[i] = REG_READ(ah, addr);
329 for (j = 0; j < 0x100; j++) {
330 wrData = (j << 16) | j;
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (rdData != wrData) {
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
340 for (j = 0; j < 4; j++) {
341 wrData = patternData[j];
342 REG_WRITE(ah, addr, wrData);
343 rdData = REG_READ(ah, addr);
344 if (wrData != rdData) {
346 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
347 addr, wrData, rdData);
351 REG_WRITE(ah, regAddr[i], regHold[i]);
358 static void ath9k_hw_init_config(struct ath_hw *ah)
362 ah->config.dma_beacon_response_time = 2;
363 ah->config.sw_beacon_response_time = 10;
364 ah->config.additional_swba_backoff = 0;
365 ah->config.ack_6mb = 0x0;
366 ah->config.cwm_ignore_extcca = 0;
367 ah->config.pcie_powersave_enable = 0;
368 ah->config.pcie_clock_req = 0;
369 ah->config.pcie_waen = 0;
370 ah->config.analog_shiftreg = 1;
371 ah->config.enable_ani = true;
373 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
374 ah->config.spurchans[i][0] = AR_NO_SPUR;
375 ah->config.spurchans[i][1] = AR_NO_SPUR;
378 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
379 ah->config.ht_enable = 1;
381 ah->config.ht_enable = 0;
383 ah->config.rx_intr_mitigation = true;
384 ah->config.pcieSerDesWrite = true;
387 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
388 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
389 * This means we use it for all AR5416 devices, and the few
390 * minor PCI AR9280 devices out there.
392 * Serialization is required because these devices do not handle
393 * well the case of two concurrent reads/writes due to the latency
394 * involved. During one read/write another read/write can be issued
395 * on another CPU while the previous read/write may still be working
396 * on our hardware, if we hit this case the hardware poops in a loop.
397 * We prevent this by serializing reads and writes.
399 * This issue is not present on PCI-Express devices or pre-AR5416
400 * devices (legacy, 802.11abg).
402 if (num_possible_cpus() > 1)
403 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
406 static void ath9k_hw_init_defaults(struct ath_hw *ah)
408 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
410 regulatory->country_code = CTRY_DEFAULT;
411 regulatory->power_limit = MAX_RATE_POWER;
412 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
414 ah->hw_version.magic = AR5416_MAGIC;
415 ah->hw_version.subvendorid = 0;
418 ah->sta_id1_defaults =
419 AR_STA_ID1_CRPT_MIC_ENABLE |
420 AR_STA_ID1_MCAST_KSRCH;
421 ah->beacon_interval = 100;
422 ah->enable_32kHz_clock = DONT_USE_32KHZ;
423 ah->slottime = (u32) -1;
424 ah->globaltxtimeout = (u32) -1;
425 ah->power_mode = ATH9K_PM_UNDEFINED;
428 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
430 struct ath_common *common = ath9k_hw_common(ah);
434 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
437 for (i = 0; i < 3; i++) {
438 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
440 common->macaddr[2 * i] = eeval >> 8;
441 common->macaddr[2 * i + 1] = eeval & 0xff;
443 if (sum == 0 || sum == 0xffff * 3)
444 return -EADDRNOTAVAIL;
449 static int ath9k_hw_post_init(struct ath_hw *ah)
453 if (!AR_SREV_9271(ah)) {
454 if (!ath9k_hw_chip_test(ah))
458 if (!AR_SREV_9300_20_OR_LATER(ah)) {
459 ecode = ar9002_hw_rf_claim(ah);
464 ecode = ath9k_hw_eeprom_init(ah);
468 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
469 "Eeprom VER: %d, REV: %d\n",
470 ah->eep_ops->get_eeprom_ver(ah),
471 ah->eep_ops->get_eeprom_rev(ah));
473 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
475 ath_err(ath9k_hw_common(ah),
476 "Failed allocating banks for external radio\n");
477 ath9k_hw_rf_free_ext_banks(ah);
481 if (!AR_SREV_9100(ah)) {
482 ath9k_hw_ani_setup(ah);
483 ath9k_hw_ani_init(ah);
489 static void ath9k_hw_attach_ops(struct ath_hw *ah)
491 if (AR_SREV_9300_20_OR_LATER(ah))
492 ar9003_hw_attach_ops(ah);
494 ar9002_hw_attach_ops(ah);
497 /* Called for all hardware families */
498 static int __ath9k_hw_init(struct ath_hw *ah)
500 struct ath_common *common = ath9k_hw_common(ah);
503 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
504 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
506 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
507 ath_err(common, "Couldn't reset chip\n");
511 ath9k_hw_init_defaults(ah);
512 ath9k_hw_init_config(ah);
514 ath9k_hw_attach_ops(ah);
516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
517 ath_err(common, "Couldn't wakeup chip\n");
521 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
522 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
523 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
524 !ah->is_pciexpress)) {
525 ah->config.serialize_regmode =
528 ah->config.serialize_regmode =
533 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
534 ah->config.serialize_regmode);
536 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
537 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
539 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
541 if (!ath9k_hw_macversion_supported(ah)) {
543 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
544 ah->hw_version.macVersion, ah->hw_version.macRev);
548 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
549 ah->is_pciexpress = false;
551 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
552 ath9k_hw_init_cal_settings(ah);
554 ah->ani_function = ATH9K_ANI_ALL;
555 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
556 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
557 if (!AR_SREV_9300_20_OR_LATER(ah))
558 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
560 ath9k_hw_init_mode_regs(ah);
563 * Read back AR_WA into a permanent copy and set bits 14 and 17.
564 * We need to do this to avoid RMW of this register. We cannot
565 * read the reg when chip is asleep.
567 ah->WARegVal = REG_READ(ah, AR_WA);
568 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
569 AR_WA_ASPM_TIMER_BASED_DISABLE);
571 if (ah->is_pciexpress)
572 ath9k_hw_configpcipowersave(ah, 0, 0);
574 ath9k_hw_disablepcie(ah);
576 if (!AR_SREV_9300_20_OR_LATER(ah))
577 ar9002_hw_cck_chan14_spread(ah);
579 r = ath9k_hw_post_init(ah);
583 ath9k_hw_init_mode_gain_regs(ah);
584 r = ath9k_hw_fill_cap_info(ah);
588 r = ath9k_hw_init_macaddr(ah);
590 ath_err(common, "Failed to initialize MAC address\n");
594 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
595 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
597 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
599 ah->bb_watchdog_timeout_ms = 25;
601 common->state = ATH_HW_INITIALIZED;
606 int ath9k_hw_init(struct ath_hw *ah)
609 struct ath_common *common = ath9k_hw_common(ah);
611 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
612 switch (ah->hw_version.devid) {
613 case AR5416_DEVID_PCI:
614 case AR5416_DEVID_PCIE:
615 case AR5416_AR9100_DEVID:
616 case AR9160_DEVID_PCI:
617 case AR9280_DEVID_PCI:
618 case AR9280_DEVID_PCIE:
619 case AR9285_DEVID_PCIE:
620 case AR9287_DEVID_PCI:
621 case AR9287_DEVID_PCIE:
622 case AR2427_DEVID_PCIE:
623 case AR9300_DEVID_PCIE:
626 if (common->bus_ops->ath_bus_type == ATH_USB)
628 ath_err(common, "Hardware device ID 0x%04x not supported\n",
629 ah->hw_version.devid);
633 ret = __ath9k_hw_init(ah);
636 "Unable to initialize hardware; initialization status: %d\n",
643 EXPORT_SYMBOL(ath9k_hw_init);
645 static void ath9k_hw_init_qos(struct ath_hw *ah)
647 ENABLE_REGWRITE_BUFFER(ah);
649 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
650 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
652 REG_WRITE(ah, AR_QOS_NO_ACK,
653 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
654 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
655 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
657 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
658 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
659 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
660 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
661 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
663 REGWRITE_BUFFER_FLUSH(ah);
666 static void ath9k_hw_init_pll(struct ath_hw *ah,
667 struct ath9k_channel *chan)
669 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
671 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
673 /* Switch the core clock for ar9271 to 117Mhz */
674 if (AR_SREV_9271(ah)) {
676 REG_WRITE(ah, 0x50040, 0x304);
679 udelay(RTC_PLL_SETTLE_DELAY);
681 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
684 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
685 enum nl80211_iftype opmode)
687 u32 imr_reg = AR_IMR_TXERR |
693 if (AR_SREV_9300_20_OR_LATER(ah)) {
694 imr_reg |= AR_IMR_RXOK_HP;
695 if (ah->config.rx_intr_mitigation)
696 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
698 imr_reg |= AR_IMR_RXOK_LP;
701 if (ah->config.rx_intr_mitigation)
702 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
704 imr_reg |= AR_IMR_RXOK;
707 if (ah->config.tx_intr_mitigation)
708 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
710 imr_reg |= AR_IMR_TXOK;
712 if (opmode == NL80211_IFTYPE_AP)
713 imr_reg |= AR_IMR_MIB;
715 ENABLE_REGWRITE_BUFFER(ah);
717 REG_WRITE(ah, AR_IMR, imr_reg);
718 ah->imrs2_reg |= AR_IMR_S2_GTT;
719 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
721 if (!AR_SREV_9100(ah)) {
722 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
723 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
724 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
727 REGWRITE_BUFFER_FLUSH(ah);
729 if (AR_SREV_9300_20_OR_LATER(ah)) {
730 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
731 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
732 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
733 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
737 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
739 u32 val = ath9k_hw_mac_to_clks(ah, us);
740 val = min(val, (u32) 0xFFFF);
741 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
744 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
746 u32 val = ath9k_hw_mac_to_clks(ah, us);
747 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
748 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
751 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
753 u32 val = ath9k_hw_mac_to_clks(ah, us);
754 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
755 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
758 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
761 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
762 "bad global tx timeout %u\n", tu);
763 ah->globaltxtimeout = (u32) -1;
766 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
767 ah->globaltxtimeout = tu;
772 void ath9k_hw_init_global_settings(struct ath_hw *ah)
774 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
779 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
782 if (ah->misc_mode != 0)
783 REG_WRITE(ah, AR_PCU_MISC,
784 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
786 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
791 /* As defined by IEEE 802.11-2007 17.3.8.6 */
792 slottime = ah->slottime + 3 * ah->coverage_class;
793 acktimeout = slottime + sifstime;
796 * Workaround for early ACK timeouts, add an offset to match the
797 * initval's 64us ack timeout value.
798 * This was initially only meant to work around an issue with delayed
799 * BA frames in some implementations, but it has been found to fix ACK
800 * timeout issues in other cases as well.
802 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
803 acktimeout += 64 - sifstime - ah->slottime;
805 ath9k_hw_setslottime(ah, slottime);
806 ath9k_hw_set_ack_timeout(ah, acktimeout);
807 ath9k_hw_set_cts_timeout(ah, acktimeout);
808 if (ah->globaltxtimeout != (u32) -1)
809 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
811 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
813 void ath9k_hw_deinit(struct ath_hw *ah)
815 struct ath_common *common = ath9k_hw_common(ah);
817 if (common->state < ATH_HW_INITIALIZED)
820 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
823 ath9k_hw_rf_free_ext_banks(ah);
825 EXPORT_SYMBOL(ath9k_hw_deinit);
831 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
833 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
837 else if (IS_CHAN_G(chan))
845 /****************************************/
846 /* Reset and Channel Switching Routines */
847 /****************************************/
849 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
851 struct ath_common *common = ath9k_hw_common(ah);
854 ENABLE_REGWRITE_BUFFER(ah);
857 * set AHB_MODE not to do cacheline prefetches
859 if (!AR_SREV_9300_20_OR_LATER(ah)) {
860 regval = REG_READ(ah, AR_AHB_MODE);
861 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
865 * let mac dma reads be in 128 byte chunks
867 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
868 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
870 REGWRITE_BUFFER_FLUSH(ah);
873 * Restore TX Trigger Level to its pre-reset value.
874 * The initial value depends on whether aggregation is enabled, and is
875 * adjusted whenever underruns are detected.
877 if (!AR_SREV_9300_20_OR_LATER(ah))
878 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
880 ENABLE_REGWRITE_BUFFER(ah);
883 * let mac dma writes be in 128 byte chunks
885 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
886 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
889 * Setup receive FIFO threshold to hold off TX activities
891 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
893 if (AR_SREV_9300_20_OR_LATER(ah)) {
894 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
895 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
897 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
898 ah->caps.rx_status_len);
902 * reduce the number of usable entries in PCU TXBUF to avoid
903 * wrap around issues.
905 if (AR_SREV_9285(ah)) {
906 /* For AR9285 the number of Fifos are reduced to half.
907 * So set the usable tx buf size also to half to
908 * avoid data/delimiter underruns
910 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
911 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
912 } else if (!AR_SREV_9271(ah)) {
913 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
914 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
917 REGWRITE_BUFFER_FLUSH(ah);
919 if (AR_SREV_9300_20_OR_LATER(ah))
920 ath9k_hw_reset_txstatus_ring(ah);
923 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
927 val = REG_READ(ah, AR_STA_ID1);
928 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
930 case NL80211_IFTYPE_AP:
931 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
932 | AR_STA_ID1_KSRCH_MODE);
933 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
935 case NL80211_IFTYPE_ADHOC:
936 case NL80211_IFTYPE_MESH_POINT:
937 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
938 | AR_STA_ID1_KSRCH_MODE);
939 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
941 case NL80211_IFTYPE_STATION:
942 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
945 if (ah->is_monitoring)
946 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
951 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
952 u32 *coef_mantissa, u32 *coef_exponent)
954 u32 coef_exp, coef_man;
956 for (coef_exp = 31; coef_exp > 0; coef_exp--)
957 if ((coef_scaled >> coef_exp) & 0x1)
960 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
962 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
964 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
965 *coef_exponent = coef_exp - 16;
968 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
973 if (AR_SREV_9100(ah)) {
974 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
975 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
976 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
977 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
978 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
981 ENABLE_REGWRITE_BUFFER(ah);
983 if (AR_SREV_9300_20_OR_LATER(ah)) {
984 REG_WRITE(ah, AR_WA, ah->WARegVal);
988 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
989 AR_RTC_FORCE_WAKE_ON_INT);
991 if (AR_SREV_9100(ah)) {
992 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
993 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
995 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
997 (AR_INTR_SYNC_LOCAL_TIMEOUT |
998 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1000 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1003 if (!AR_SREV_9300_20_OR_LATER(ah))
1005 REG_WRITE(ah, AR_RC, val);
1007 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1008 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1010 rst_flags = AR_RTC_RC_MAC_WARM;
1011 if (type == ATH9K_RESET_COLD)
1012 rst_flags |= AR_RTC_RC_MAC_COLD;
1015 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1017 REGWRITE_BUFFER_FLUSH(ah);
1021 REG_WRITE(ah, AR_RTC_RC, 0);
1022 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1023 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1024 "RTC stuck in MAC reset\n");
1028 if (!AR_SREV_9100(ah))
1029 REG_WRITE(ah, AR_RC, 0);
1031 if (AR_SREV_9100(ah))
1037 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1039 ENABLE_REGWRITE_BUFFER(ah);
1041 if (AR_SREV_9300_20_OR_LATER(ah)) {
1042 REG_WRITE(ah, AR_WA, ah->WARegVal);
1046 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1047 AR_RTC_FORCE_WAKE_ON_INT);
1049 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1050 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1052 REG_WRITE(ah, AR_RTC_RESET, 0);
1055 REGWRITE_BUFFER_FLUSH(ah);
1057 if (!AR_SREV_9300_20_OR_LATER(ah))
1060 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1061 REG_WRITE(ah, AR_RC, 0);
1063 REG_WRITE(ah, AR_RTC_RESET, 1);
1065 if (!ath9k_hw_wait(ah,
1070 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1071 "RTC not waking up\n");
1075 ath9k_hw_read_revisions(ah);
1077 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1080 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1082 if (AR_SREV_9300_20_OR_LATER(ah)) {
1083 REG_WRITE(ah, AR_WA, ah->WARegVal);
1087 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1088 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1091 case ATH9K_RESET_POWER_ON:
1092 return ath9k_hw_set_reset_power_on(ah);
1093 case ATH9K_RESET_WARM:
1094 case ATH9K_RESET_COLD:
1095 return ath9k_hw_set_reset(ah, type);
1101 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1102 struct ath9k_channel *chan)
1104 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1105 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1107 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1110 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1113 ah->chip_fullsleep = false;
1114 ath9k_hw_init_pll(ah, chan);
1115 ath9k_hw_set_rfmode(ah, chan);
1120 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1121 struct ath9k_channel *chan)
1123 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1124 struct ath_common *common = ath9k_hw_common(ah);
1125 struct ieee80211_channel *channel = chan->chan;
1129 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1130 if (ath9k_hw_numtxpending(ah, qnum)) {
1131 ath_print(common, ATH_DBG_QUEUE,
1132 "Transmit frames pending on "
1133 "queue %d\n", qnum);
1138 if (!ath9k_hw_rfbus_req(ah)) {
1139 ath_err(common, "Could not kill baseband RX\n");
1143 ath9k_hw_set_channel_regs(ah, chan);
1145 r = ath9k_hw_rf_set_freq(ah, chan);
1147 ath_err(common, "Failed to set channel\n");
1150 ath9k_hw_set_clockrate(ah);
1152 ah->eep_ops->set_txpower(ah, chan,
1153 ath9k_regd_get_ctl(regulatory, chan),
1154 channel->max_antenna_gain * 2,
1155 channel->max_power * 2,
1156 min((u32) MAX_RATE_POWER,
1157 (u32) regulatory->power_limit), false);
1159 ath9k_hw_rfbus_done(ah);
1161 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1162 ath9k_hw_set_delta_slope(ah, chan);
1164 ath9k_hw_spur_mitigate_freq(ah, chan);
1169 bool ath9k_hw_check_alive(struct ath_hw *ah)
1174 if (AR_SREV_9285_12_OR_LATER(ah))
1178 reg = REG_READ(ah, AR_OBS_BUS_1);
1180 if ((reg & 0x7E7FFFEF) == 0x00702400)
1183 switch (reg & 0x7E000B00) {
1191 } while (count-- > 0);
1195 EXPORT_SYMBOL(ath9k_hw_check_alive);
1197 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1198 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1200 struct ath_common *common = ath9k_hw_common(ah);
1202 struct ath9k_channel *curchan = ah->curchan;
1208 ah->txchainmask = common->tx_chainmask;
1209 ah->rxchainmask = common->rx_chainmask;
1211 if (!ah->chip_fullsleep) {
1212 ath9k_hw_abortpcurecv(ah);
1213 if (!ath9k_hw_stopdmarecv(ah)) {
1214 ath_print(common, ATH_DBG_XMIT,
1215 "Failed to stop receive dma\n");
1216 bChannelChange = false;
1220 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1223 if (curchan && !ah->chip_fullsleep)
1224 ath9k_hw_getnf(ah, curchan);
1226 ah->caldata = caldata;
1228 (chan->channel != caldata->channel ||
1229 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1230 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1231 /* Operating channel changed, reset channel calibration data */
1232 memset(caldata, 0, sizeof(*caldata));
1233 ath9k_init_nfcal_hist_buffer(ah, chan);
1236 if (bChannelChange &&
1237 (ah->chip_fullsleep != true) &&
1238 (ah->curchan != NULL) &&
1239 (chan->channel != ah->curchan->channel) &&
1240 ((chan->channelFlags & CHANNEL_ALL) ==
1241 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1242 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1244 if (ath9k_hw_channel_change(ah, chan)) {
1245 ath9k_hw_loadnf(ah, ah->curchan);
1246 ath9k_hw_start_nfcal(ah, true);
1247 if (AR_SREV_9271(ah))
1248 ar9002_hw_load_ani_reg(ah, chan);
1253 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1254 if (saveDefAntenna == 0)
1257 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1259 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1260 if (AR_SREV_9100(ah) ||
1261 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1262 tsf = ath9k_hw_gettsf64(ah);
1264 saveLedState = REG_READ(ah, AR_CFG_LED) &
1265 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1266 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1268 ath9k_hw_mark_phy_inactive(ah);
1270 /* Only required on the first reset */
1271 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1273 AR9271_RESET_POWER_DOWN_CONTROL,
1274 AR9271_RADIO_RF_RST);
1278 if (!ath9k_hw_chip_reset(ah, chan)) {
1279 ath_err(common, "Chip reset failed\n");
1283 /* Only required on the first reset */
1284 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1285 ah->htc_reset_init = false;
1287 AR9271_RESET_POWER_DOWN_CONTROL,
1288 AR9271_GATE_MAC_CTL);
1294 ath9k_hw_settsf64(ah, tsf);
1296 if (AR_SREV_9280_20_OR_LATER(ah))
1297 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1299 if (!AR_SREV_9300_20_OR_LATER(ah))
1300 ar9002_hw_enable_async_fifo(ah);
1302 r = ath9k_hw_process_ini(ah, chan);
1307 * Some AR91xx SoC devices frequently fail to accept TSF writes
1308 * right after the chip reset. When that happens, write a new
1309 * value after the initvals have been applied, with an offset
1310 * based on measured time difference
1312 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1314 ath9k_hw_settsf64(ah, tsf);
1317 /* Setup MFP options for CCMP */
1318 if (AR_SREV_9280_20_OR_LATER(ah)) {
1319 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1320 * frames when constructing CCMP AAD. */
1321 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1323 ah->sw_mgmt_crypto = false;
1324 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1325 /* Disable hardware crypto for management frames */
1326 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1327 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1328 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1329 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1330 ah->sw_mgmt_crypto = true;
1332 ah->sw_mgmt_crypto = true;
1334 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1335 ath9k_hw_set_delta_slope(ah, chan);
1337 ath9k_hw_spur_mitigate_freq(ah, chan);
1338 ah->eep_ops->set_board_values(ah, chan);
1340 ath9k_hw_set_operating_mode(ah, ah->opmode);
1342 ENABLE_REGWRITE_BUFFER(ah);
1344 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1345 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1347 | AR_STA_ID1_RTS_USE_DEF
1349 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1350 | ah->sta_id1_defaults);
1351 ath_hw_setbssidmask(common);
1352 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1353 ath9k_hw_write_associd(ah);
1354 REG_WRITE(ah, AR_ISR, ~0);
1355 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1357 REGWRITE_BUFFER_FLUSH(ah);
1359 r = ath9k_hw_rf_set_freq(ah, chan);
1363 ath9k_hw_set_clockrate(ah);
1365 ENABLE_REGWRITE_BUFFER(ah);
1367 for (i = 0; i < AR_NUM_DCU; i++)
1368 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1370 REGWRITE_BUFFER_FLUSH(ah);
1373 for (i = 0; i < ah->caps.total_queues; i++)
1374 ath9k_hw_resettxqueue(ah, i);
1376 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1377 ath9k_hw_ani_cache_ini_regs(ah);
1378 ath9k_hw_init_qos(ah);
1380 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1381 ath9k_enable_rfkill(ah);
1383 ath9k_hw_init_global_settings(ah);
1385 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1386 ar9002_hw_update_async_fifo(ah);
1387 ar9002_hw_enable_wep_aggregation(ah);
1390 REG_WRITE(ah, AR_STA_ID1,
1391 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1393 ath9k_hw_set_dma(ah);
1395 REG_WRITE(ah, AR_OBS, 8);
1397 if (ah->config.rx_intr_mitigation) {
1398 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1399 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1402 if (ah->config.tx_intr_mitigation) {
1403 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1404 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1407 ath9k_hw_init_bb(ah, chan);
1409 if (!ath9k_hw_init_cal(ah, chan))
1412 ENABLE_REGWRITE_BUFFER(ah);
1414 ath9k_hw_restore_chainmask(ah);
1415 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1417 REGWRITE_BUFFER_FLUSH(ah);
1420 * For big endian systems turn on swapping for descriptors
1422 if (AR_SREV_9100(ah)) {
1424 mask = REG_READ(ah, AR_CFG);
1425 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1426 ath_print(common, ATH_DBG_RESET,
1427 "CFG Byte Swap Set 0x%x\n", mask);
1430 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1431 REG_WRITE(ah, AR_CFG, mask);
1432 ath_print(common, ATH_DBG_RESET,
1433 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1436 if (common->bus_ops->ath_bus_type == ATH_USB) {
1437 /* Configure AR9271 target WLAN */
1438 if (AR_SREV_9271(ah))
1439 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1441 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1445 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1449 if (ah->btcoex_hw.enabled)
1450 ath9k_hw_btcoex_enable(ah);
1452 if (AR_SREV_9300_20_OR_LATER(ah))
1453 ar9003_hw_bb_watchdog_config(ah);
1457 EXPORT_SYMBOL(ath9k_hw_reset);
1459 /******************************/
1460 /* Power Management (Chipset) */
1461 /******************************/
1464 * Notify Power Mgt is disabled in self-generated frames.
1465 * If requested, force chip to sleep.
1467 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1469 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1472 * Clear the RTC force wake bit to allow the
1473 * mac to go to sleep.
1475 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1476 AR_RTC_FORCE_WAKE_EN);
1477 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1478 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1480 /* Shutdown chip. Active low */
1481 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1482 REG_CLR_BIT(ah, (AR_RTC_RESET),
1486 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1487 if (AR_SREV_9300_20_OR_LATER(ah))
1488 REG_WRITE(ah, AR_WA,
1489 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1493 * Notify Power Management is enabled in self-generating
1494 * frames. If request, set power mode of chip to
1495 * auto/normal. Duration in units of 128us (1/8 TU).
1497 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1499 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1501 struct ath9k_hw_capabilities *pCap = &ah->caps;
1503 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1504 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1505 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1506 AR_RTC_FORCE_WAKE_ON_INT);
1509 * Clear the RTC force wake bit to allow the
1510 * mac to go to sleep.
1512 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1513 AR_RTC_FORCE_WAKE_EN);
1517 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1518 if (AR_SREV_9300_20_OR_LATER(ah))
1519 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1522 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1527 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1528 if (AR_SREV_9300_20_OR_LATER(ah)) {
1529 REG_WRITE(ah, AR_WA, ah->WARegVal);
1534 if ((REG_READ(ah, AR_RTC_STATUS) &
1535 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1536 if (ath9k_hw_set_reset_reg(ah,
1537 ATH9K_RESET_POWER_ON) != true) {
1540 if (!AR_SREV_9300_20_OR_LATER(ah))
1541 ath9k_hw_init_pll(ah, NULL);
1543 if (AR_SREV_9100(ah))
1544 REG_SET_BIT(ah, AR_RTC_RESET,
1547 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1548 AR_RTC_FORCE_WAKE_EN);
1551 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1552 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1553 if (val == AR_RTC_STATUS_ON)
1556 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1557 AR_RTC_FORCE_WAKE_EN);
1560 ath_err(ath9k_hw_common(ah),
1561 "Failed to wakeup in %uus\n",
1562 POWER_UP_TIME / 20);
1567 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1572 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1574 struct ath_common *common = ath9k_hw_common(ah);
1575 int status = true, setChip = true;
1576 static const char *modes[] = {
1583 if (ah->power_mode == mode)
1586 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1587 modes[ah->power_mode], modes[mode]);
1590 case ATH9K_PM_AWAKE:
1591 status = ath9k_hw_set_power_awake(ah, setChip);
1593 case ATH9K_PM_FULL_SLEEP:
1594 ath9k_set_power_sleep(ah, setChip);
1595 ah->chip_fullsleep = true;
1597 case ATH9K_PM_NETWORK_SLEEP:
1598 ath9k_set_power_network_sleep(ah, setChip);
1601 ath_err(common, "Unknown power mode %u\n", mode);
1604 ah->power_mode = mode;
1608 EXPORT_SYMBOL(ath9k_hw_setpower);
1610 /*******************/
1611 /* Beacon Handling */
1612 /*******************/
1614 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1618 ah->beacon_interval = beacon_period;
1620 ENABLE_REGWRITE_BUFFER(ah);
1622 switch (ah->opmode) {
1623 case NL80211_IFTYPE_STATION:
1624 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1625 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1626 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1627 flags |= AR_TBTT_TIMER_EN;
1629 case NL80211_IFTYPE_ADHOC:
1630 case NL80211_IFTYPE_MESH_POINT:
1631 REG_SET_BIT(ah, AR_TXCFG,
1632 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1633 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1634 TU_TO_USEC(next_beacon +
1635 (ah->atim_window ? ah->
1637 flags |= AR_NDP_TIMER_EN;
1638 case NL80211_IFTYPE_AP:
1639 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1640 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1641 TU_TO_USEC(next_beacon -
1643 dma_beacon_response_time));
1644 REG_WRITE(ah, AR_NEXT_SWBA,
1645 TU_TO_USEC(next_beacon -
1647 sw_beacon_response_time));
1649 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1652 if (ah->is_monitoring) {
1653 REG_WRITE(ah, AR_NEXT_TBTT_TIMER,
1654 TU_TO_USEC(next_beacon));
1655 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1656 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1657 flags |= AR_TBTT_TIMER_EN;
1660 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1661 "%s: unsupported opmode: %d\n",
1662 __func__, ah->opmode);
1667 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1668 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1669 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1670 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1672 REGWRITE_BUFFER_FLUSH(ah);
1674 beacon_period &= ~ATH9K_BEACON_ENA;
1675 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1676 ath9k_hw_reset_tsf(ah);
1679 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1681 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1683 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1684 const struct ath9k_beacon_state *bs)
1686 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1687 struct ath9k_hw_capabilities *pCap = &ah->caps;
1688 struct ath_common *common = ath9k_hw_common(ah);
1690 ENABLE_REGWRITE_BUFFER(ah);
1692 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1694 REG_WRITE(ah, AR_BEACON_PERIOD,
1695 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1696 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1697 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1699 REGWRITE_BUFFER_FLUSH(ah);
1701 REG_RMW_FIELD(ah, AR_RSSI_THR,
1702 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1704 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1706 if (bs->bs_sleepduration > beaconintval)
1707 beaconintval = bs->bs_sleepduration;
1709 dtimperiod = bs->bs_dtimperiod;
1710 if (bs->bs_sleepduration > dtimperiod)
1711 dtimperiod = bs->bs_sleepduration;
1713 if (beaconintval == dtimperiod)
1714 nextTbtt = bs->bs_nextdtim;
1716 nextTbtt = bs->bs_nexttbtt;
1718 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1719 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1720 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1721 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1723 ENABLE_REGWRITE_BUFFER(ah);
1725 REG_WRITE(ah, AR_NEXT_DTIM,
1726 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1727 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1729 REG_WRITE(ah, AR_SLEEP1,
1730 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1731 | AR_SLEEP1_ASSUME_DTIM);
1733 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1734 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1736 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1738 REG_WRITE(ah, AR_SLEEP2,
1739 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1741 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1742 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1744 REGWRITE_BUFFER_FLUSH(ah);
1746 REG_SET_BIT(ah, AR_TIMER_MODE,
1747 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1750 /* TSF Out of Range Threshold */
1751 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
1753 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
1755 /*******************/
1756 /* HW Capabilities */
1757 /*******************/
1759 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
1761 struct ath9k_hw_capabilities *pCap = &ah->caps;
1762 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1763 struct ath_common *common = ath9k_hw_common(ah);
1764 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
1766 u16 capField = 0, eeval;
1769 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
1770 regulatory->current_rd = eeval;
1772 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
1773 if (AR_SREV_9285_12_OR_LATER(ah))
1774 eeval |= AR9285_RDEXT_DEFAULT;
1775 regulatory->current_rd_ext = eeval;
1777 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
1779 if (ah->opmode != NL80211_IFTYPE_AP &&
1780 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
1781 if (regulatory->current_rd == 0x64 ||
1782 regulatory->current_rd == 0x65)
1783 regulatory->current_rd += 5;
1784 else if (regulatory->current_rd == 0x41)
1785 regulatory->current_rd = 0x43;
1786 ath_print(common, ATH_DBG_REGULATORY,
1787 "regdomain mapped to 0x%x\n", regulatory->current_rd);
1790 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
1791 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1793 "no band has been marked as supported in EEPROM\n");
1797 if (eeval & AR5416_OPFLAGS_11A)
1798 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
1800 if (eeval & AR5416_OPFLAGS_11G)
1801 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
1803 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
1805 * For AR9271 we will temporarilly uses the rx chainmax as read from
1808 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
1809 !(eeval & AR5416_OPFLAGS_11A) &&
1810 !(AR_SREV_9271(ah)))
1811 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
1812 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1814 /* Use rx_chainmask from EEPROM. */
1815 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
1817 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
1819 /* enable key search for every frame in an aggregate */
1820 if (AR_SREV_9300_20_OR_LATER(ah))
1821 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1823 pCap->low_2ghz_chan = 2312;
1824 pCap->high_2ghz_chan = 2732;
1826 pCap->low_5ghz_chan = 4920;
1827 pCap->high_5ghz_chan = 6100;
1829 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1831 if (ah->config.ht_enable)
1832 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1834 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
1836 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1837 pCap->total_queues =
1838 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1840 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
1842 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
1843 pCap->keycache_size =
1844 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
1846 pCap->keycache_size = AR_KEYTABLE_SIZE;
1848 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
1849 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
1851 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
1853 if (AR_SREV_9271(ah))
1854 pCap->num_gpio_pins = AR9271_NUM_GPIO;
1855 else if (AR_DEVID_7010(ah))
1856 pCap->num_gpio_pins = AR7010_NUM_GPIO;
1857 else if (AR_SREV_9285_12_OR_LATER(ah))
1858 pCap->num_gpio_pins = AR9285_NUM_GPIO;
1859 else if (AR_SREV_9280_20_OR_LATER(ah))
1860 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1862 pCap->num_gpio_pins = AR_NUM_GPIO;
1864 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1865 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1866 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1868 pCap->rts_aggr_limit = (8 * 1024);
1871 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
1873 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1874 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1875 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1877 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1878 ah->rfkill_polarity =
1879 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
1881 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
1884 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
1885 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1887 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
1889 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
1890 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1892 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
1894 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
1896 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1897 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
1898 AR_EEPROM_EEREGCAP_EN_KK_U2 |
1899 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
1902 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
1903 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
1906 /* Advertise midband for AR5416 with FCC midband set in eeprom */
1907 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
1909 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
1911 pCap->num_antcfg_5ghz =
1912 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
1913 pCap->num_antcfg_2ghz =
1914 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
1916 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
1917 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1918 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
1920 if (AR_SREV_9285(ah)) {
1921 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1922 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
1924 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
1927 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
1930 if (AR_SREV_9300_20_OR_LATER(ah)) {
1931 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
1932 ATH9K_HW_CAP_FASTCLOCK;
1933 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1934 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1935 pCap->rx_status_len = sizeof(struct ar9003_rxs);
1936 pCap->tx_desc_len = sizeof(struct ar9003_txc);
1937 pCap->txs_len = sizeof(struct ar9003_txs);
1938 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
1939 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
1941 pCap->tx_desc_len = sizeof(struct ath_desc);
1942 if (AR_SREV_9280_20(ah) &&
1943 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
1944 AR5416_EEP_MINOR_VER_16) ||
1945 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
1946 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
1949 if (AR_SREV_9300_20_OR_LATER(ah))
1950 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
1952 if (AR_SREV_9300_20_OR_LATER(ah))
1953 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
1955 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
1956 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
1958 if (AR_SREV_9285(ah))
1959 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
1961 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1962 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
1963 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
1965 if (AR_SREV_9300_20_OR_LATER(ah)) {
1966 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
1967 pCap->hw_caps |= ATH9K_HW_CAP_APM;
1975 /****************************/
1976 /* GPIO / RFKILL / Antennae */
1977 /****************************/
1979 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
1983 u32 gpio_shift, tmp;
1986 addr = AR_GPIO_OUTPUT_MUX3;
1988 addr = AR_GPIO_OUTPUT_MUX2;
1990 addr = AR_GPIO_OUTPUT_MUX1;
1992 gpio_shift = (gpio % 6) * 5;
1994 if (AR_SREV_9280_20_OR_LATER(ah)
1995 || (addr != AR_GPIO_OUTPUT_MUX1)) {
1996 REG_RMW(ah, addr, (type << gpio_shift),
1997 (0x1f << gpio_shift));
1999 tmp = REG_READ(ah, addr);
2000 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2001 tmp &= ~(0x1f << gpio_shift);
2002 tmp |= (type << gpio_shift);
2003 REG_WRITE(ah, addr, tmp);
2007 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2011 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2013 if (AR_DEVID_7010(ah)) {
2015 REG_RMW(ah, AR7010_GPIO_OE,
2016 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2017 (AR7010_GPIO_OE_MASK << gpio_shift));
2021 gpio_shift = gpio << 1;
2024 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2025 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2027 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2029 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2031 #define MS_REG_READ(x, y) \
2032 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2034 if (gpio >= ah->caps.num_gpio_pins)
2037 if (AR_DEVID_7010(ah)) {
2039 val = REG_READ(ah, AR7010_GPIO_IN);
2040 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2041 } else if (AR_SREV_9300_20_OR_LATER(ah))
2042 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2043 AR_GPIO_BIT(gpio)) != 0;
2044 else if (AR_SREV_9271(ah))
2045 return MS_REG_READ(AR9271, gpio) != 0;
2046 else if (AR_SREV_9287_11_OR_LATER(ah))
2047 return MS_REG_READ(AR9287, gpio) != 0;
2048 else if (AR_SREV_9285_12_OR_LATER(ah))
2049 return MS_REG_READ(AR9285, gpio) != 0;
2050 else if (AR_SREV_9280_20_OR_LATER(ah))
2051 return MS_REG_READ(AR928X, gpio) != 0;
2053 return MS_REG_READ(AR, gpio) != 0;
2055 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2057 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2062 if (AR_DEVID_7010(ah)) {
2064 REG_RMW(ah, AR7010_GPIO_OE,
2065 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2066 (AR7010_GPIO_OE_MASK << gpio_shift));
2070 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2071 gpio_shift = 2 * gpio;
2074 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2075 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2077 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2079 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2081 if (AR_DEVID_7010(ah)) {
2083 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2088 if (AR_SREV_9271(ah))
2091 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2094 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2096 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2098 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2100 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2102 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2104 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2106 EXPORT_SYMBOL(ath9k_hw_setantenna);
2108 /*********************/
2109 /* General Operation */
2110 /*********************/
2112 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2114 u32 bits = REG_READ(ah, AR_RX_FILTER);
2115 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2117 if (phybits & AR_PHY_ERR_RADAR)
2118 bits |= ATH9K_RX_FILTER_PHYRADAR;
2119 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2120 bits |= ATH9K_RX_FILTER_PHYERR;
2124 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2126 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2130 ENABLE_REGWRITE_BUFFER(ah);
2132 REG_WRITE(ah, AR_RX_FILTER, bits);
2135 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2136 phybits |= AR_PHY_ERR_RADAR;
2137 if (bits & ATH9K_RX_FILTER_PHYERR)
2138 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2139 REG_WRITE(ah, AR_PHY_ERR, phybits);
2142 REG_WRITE(ah, AR_RXCFG,
2143 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2145 REG_WRITE(ah, AR_RXCFG,
2146 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2148 REGWRITE_BUFFER_FLUSH(ah);
2150 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2152 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2154 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2157 ath9k_hw_init_pll(ah, NULL);
2160 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2162 bool ath9k_hw_disable(struct ath_hw *ah)
2164 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2167 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2170 ath9k_hw_init_pll(ah, NULL);
2173 EXPORT_SYMBOL(ath9k_hw_disable);
2175 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2177 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2178 struct ath9k_channel *chan = ah->curchan;
2179 struct ieee80211_channel *channel = chan->chan;
2181 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2183 ah->eep_ops->set_txpower(ah, chan,
2184 ath9k_regd_get_ctl(regulatory, chan),
2185 channel->max_antenna_gain * 2,
2186 channel->max_power * 2,
2187 min((u32) MAX_RATE_POWER,
2188 (u32) regulatory->power_limit), test);
2190 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2192 void ath9k_hw_setopmode(struct ath_hw *ah)
2194 ath9k_hw_set_operating_mode(ah, ah->opmode);
2196 EXPORT_SYMBOL(ath9k_hw_setopmode);
2198 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2200 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2201 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2203 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2205 void ath9k_hw_write_associd(struct ath_hw *ah)
2207 struct ath_common *common = ath9k_hw_common(ah);
2209 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2210 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2211 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2213 EXPORT_SYMBOL(ath9k_hw_write_associd);
2215 #define ATH9K_MAX_TSF_READ 10
2217 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2219 u32 tsf_lower, tsf_upper1, tsf_upper2;
2222 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2223 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2224 tsf_lower = REG_READ(ah, AR_TSF_L32);
2225 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2226 if (tsf_upper2 == tsf_upper1)
2228 tsf_upper1 = tsf_upper2;
2231 WARN_ON( i == ATH9K_MAX_TSF_READ );
2233 return (((u64)tsf_upper1 << 32) | tsf_lower);
2235 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2237 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2239 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2240 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2242 EXPORT_SYMBOL(ath9k_hw_settsf64);
2244 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2246 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2247 AH_TSF_WRITE_TIMEOUT))
2248 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2249 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2251 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2253 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2255 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2258 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2260 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2262 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2264 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2266 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2269 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2270 macmode = AR_2040_JOINED_RX_CLEAR;
2274 REG_WRITE(ah, AR_2040_MODE, macmode);
2277 /* HW Generic timers configuration */
2279 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2281 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2282 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2283 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2284 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2285 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2286 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2287 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2288 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2289 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2290 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2291 AR_NDP2_TIMER_MODE, 0x0002},
2292 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2293 AR_NDP2_TIMER_MODE, 0x0004},
2294 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2295 AR_NDP2_TIMER_MODE, 0x0008},
2296 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2297 AR_NDP2_TIMER_MODE, 0x0010},
2298 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2299 AR_NDP2_TIMER_MODE, 0x0020},
2300 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2301 AR_NDP2_TIMER_MODE, 0x0040},
2302 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2303 AR_NDP2_TIMER_MODE, 0x0080}
2306 /* HW generic timer primitives */
2308 /* compute and clear index of rightmost 1 */
2309 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2319 return timer_table->gen_timer_index[b];
2322 static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2324 return REG_READ(ah, AR_TSF_L32);
2327 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2328 void (*trigger)(void *),
2329 void (*overflow)(void *),
2333 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2334 struct ath_gen_timer *timer;
2336 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2338 if (timer == NULL) {
2339 ath_err(ath9k_hw_common(ah),
2340 "Failed to allocate memory for hw timer[%d]\n",
2345 /* allocate a hardware generic timer slot */
2346 timer_table->timers[timer_index] = timer;
2347 timer->index = timer_index;
2348 timer->trigger = trigger;
2349 timer->overflow = overflow;
2354 EXPORT_SYMBOL(ath_gen_timer_alloc);
2356 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2357 struct ath_gen_timer *timer,
2361 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2364 BUG_ON(!timer_period);
2366 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2368 tsf = ath9k_hw_gettsf32(ah);
2370 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2371 "curent tsf %x period %x"
2372 "timer_next %x\n", tsf, timer_period, timer_next);
2375 * Pull timer_next forward if the current TSF already passed it
2376 * because of software latency
2378 if (timer_next < tsf)
2379 timer_next = tsf + timer_period;
2382 * Program generic timer registers
2384 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2386 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2388 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2389 gen_tmr_configuration[timer->index].mode_mask);
2391 /* Enable both trigger and thresh interrupt masks */
2392 REG_SET_BIT(ah, AR_IMR_S5,
2393 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2394 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2396 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2398 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2400 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2402 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2403 (timer->index >= ATH_MAX_GEN_TIMER)) {
2407 /* Clear generic timer enable bits. */
2408 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2409 gen_tmr_configuration[timer->index].mode_mask);
2411 /* Disable both trigger and thresh interrupt masks */
2412 REG_CLR_BIT(ah, AR_IMR_S5,
2413 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2414 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2416 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2418 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2420 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2422 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2424 /* free the hardware generic timer slot */
2425 timer_table->timers[timer->index] = NULL;
2428 EXPORT_SYMBOL(ath_gen_timer_free);
2431 * Generic Timer Interrupts handling
2433 void ath_gen_timer_isr(struct ath_hw *ah)
2435 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2436 struct ath_gen_timer *timer;
2437 struct ath_common *common = ath9k_hw_common(ah);
2438 u32 trigger_mask, thresh_mask, index;
2440 /* get hardware generic timer interrupt status */
2441 trigger_mask = ah->intr_gen_timer_trigger;
2442 thresh_mask = ah->intr_gen_timer_thresh;
2443 trigger_mask &= timer_table->timer_mask.val;
2444 thresh_mask &= timer_table->timer_mask.val;
2446 trigger_mask &= ~thresh_mask;
2448 while (thresh_mask) {
2449 index = rightmost_index(timer_table, &thresh_mask);
2450 timer = timer_table->timers[index];
2452 ath_print(common, ATH_DBG_HWTIMER,
2453 "TSF overflow for Gen timer %d\n", index);
2454 timer->overflow(timer->arg);
2457 while (trigger_mask) {
2458 index = rightmost_index(timer_table, &trigger_mask);
2459 timer = timer_table->timers[index];
2461 ath_print(common, ATH_DBG_HWTIMER,
2462 "Gen timer[%d] trigger\n", index);
2463 timer->trigger(timer->arg);
2466 EXPORT_SYMBOL(ath_gen_timer_isr);
2472 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2474 ah->htc_reset_init = true;
2476 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2481 } ath_mac_bb_names[] = {
2482 /* Devices with external radios */
2483 { AR_SREV_VERSION_5416_PCI, "5416" },
2484 { AR_SREV_VERSION_5416_PCIE, "5418" },
2485 { AR_SREV_VERSION_9100, "9100" },
2486 { AR_SREV_VERSION_9160, "9160" },
2487 /* Single-chip solutions */
2488 { AR_SREV_VERSION_9280, "9280" },
2489 { AR_SREV_VERSION_9285, "9285" },
2490 { AR_SREV_VERSION_9287, "9287" },
2491 { AR_SREV_VERSION_9271, "9271" },
2492 { AR_SREV_VERSION_9300, "9300" },
2495 /* For devices with external radios */
2499 } ath_rf_names[] = {
2501 { AR_RAD5133_SREV_MAJOR, "5133" },
2502 { AR_RAD5122_SREV_MAJOR, "5122" },
2503 { AR_RAD2133_SREV_MAJOR, "2133" },
2504 { AR_RAD2122_SREV_MAJOR, "2122" }
2508 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2510 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2514 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2515 if (ath_mac_bb_names[i].version == mac_bb_version) {
2516 return ath_mac_bb_names[i].name;
2524 * Return the RF name. "????" is returned if the RF is unknown.
2525 * Used for devices with external radios.
2527 static const char *ath9k_hw_rf_name(u16 rf_version)
2531 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2532 if (ath_rf_names[i].version == rf_version) {
2533 return ath_rf_names[i].name;
2540 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2544 /* chipsets >= AR9280 are single-chip */
2545 if (AR_SREV_9280_20_OR_LATER(ah)) {
2546 used = snprintf(hw_name, len,
2547 "Atheros AR%s Rev:%x",
2548 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2549 ah->hw_version.macRev);
2552 used = snprintf(hw_name, len,
2553 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2554 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2555 ah->hw_version.macRev,
2556 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2557 AR_RADIO_SREV_MAJOR)),
2558 ah->hw_version.phyRev);
2561 hw_name[used] = '\0';
2563 EXPORT_SYMBOL(ath9k_hw_name);