drivers/net/wireless/ath/ath9k/htc_drv_init.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "htc.h"
  18
  19 MODULE_AUTHOR("Atheros Communications");
  20 MODULE_LICENSE("Dual BSD/GPL");
  21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  22
  23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  24 module_param_named(debug, ath9k_debug, uint, 0);
  25 MODULE_PARM_DESC(debug, "Debugging mask");
  26
  27 int htc_modparam_nohwcrypt;
  28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  30
  31 #define CHAN2G(_freq, _idx)  { \
  32         .center_freq = (_freq), \
  33         .hw_value = (_idx), \
  34         .max_power = 20, \
  35 }
  36
  37 #define CHAN5G(_freq, _idx) { \
  38         .band = IEEE80211_BAND_5GHZ, \
  39         .center_freq = (_freq), \
  40         .hw_value = (_idx), \
  41         .max_power = 20, \
  42 }
  43
  44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
  45
  46 static struct ieee80211_channel ath9k_2ghz_channels[] = {
  47         CHAN2G(2412, 0), /* Channel 1 */
  48         CHAN2G(2417, 1), /* Channel 2 */
  49         CHAN2G(2422, 2), /* Channel 3 */
  50         CHAN2G(2427, 3), /* Channel 4 */
  51         CHAN2G(2432, 4), /* Channel 5 */
  52         CHAN2G(2437, 5), /* Channel 6 */
  53         CHAN2G(2442, 6), /* Channel 7 */
  54         CHAN2G(2447, 7), /* Channel 8 */
  55         CHAN2G(2452, 8), /* Channel 9 */
  56         CHAN2G(2457, 9), /* Channel 10 */
  57         CHAN2G(2462, 10), /* Channel 11 */
  58         CHAN2G(2467, 11), /* Channel 12 */
  59         CHAN2G(2472, 12), /* Channel 13 */
  60         CHAN2G(2484, 13), /* Channel 14 */
  61 };
  62
  63 static struct ieee80211_channel ath9k_5ghz_channels[] = {
  64         /* _We_ call this UNII 1 */
  65         CHAN5G(5180, 14), /* Channel 36 */
  66         CHAN5G(5200, 15), /* Channel 40 */
  67         CHAN5G(5220, 16), /* Channel 44 */
  68         CHAN5G(5240, 17), /* Channel 48 */
  69         /* _We_ call this UNII 2 */
  70         CHAN5G(5260, 18), /* Channel 52 */
  71         CHAN5G(5280, 19), /* Channel 56 */
  72         CHAN5G(5300, 20), /* Channel 60 */
  73         CHAN5G(5320, 21), /* Channel 64 */
  74         /* _We_ call this "Middle band" */
  75         CHAN5G(5500, 22), /* Channel 100 */
  76         CHAN5G(5520, 23), /* Channel 104 */
  77         CHAN5G(5540, 24), /* Channel 108 */
  78         CHAN5G(5560, 25), /* Channel 112 */
  79         CHAN5G(5580, 26), /* Channel 116 */
  80         CHAN5G(5600, 27), /* Channel 120 */
  81         CHAN5G(5620, 28), /* Channel 124 */
  82         CHAN5G(5640, 29), /* Channel 128 */
  83         CHAN5G(5660, 30), /* Channel 132 */
  84         CHAN5G(5680, 31), /* Channel 136 */
  85         CHAN5G(5700, 32), /* Channel 140 */
  86         /* _We_ call this UNII 3 */
  87         CHAN5G(5745, 33), /* Channel 149 */
  88         CHAN5G(5765, 34), /* Channel 153 */
  89         CHAN5G(5785, 35), /* Channel 157 */
  90         CHAN5G(5805, 36), /* Channel 161 */
  91         CHAN5G(5825, 37), /* Channel 165 */
  92 };
  93
  94 /* Atheros hardware rate code addition for short premble */
  95 #define SHPCHECK(__hw_rate, __flags) \
  96         ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  97
  98 #define RATE(_bitrate, _hw_rate, _flags) {              \
  99         .bitrate        = (_bitrate),                   \
 100         .flags          = (_flags),                     \
 101         .hw_value       = (_hw_rate),                   \
 102         .hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
 103 }
 104
 105 static struct ieee80211_rate ath9k_legacy_rates[] = {
 106         RATE(10, 0x1b, 0),
 107         RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
 108         RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
 109         RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
 110         RATE(60, 0x0b, 0),
 111         RATE(90, 0x0f, 0),
 112         RATE(120, 0x0a, 0),
 113         RATE(180, 0x0e, 0),
 114         RATE(240, 0x09, 0),
 115         RATE(360, 0x0d, 0),
 116         RATE(480, 0x08, 0),
 117         RATE(540, 0x0c, 0),
 118 };
 119
 120 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
 121 {
 122         int time_left;
 123
 124         if (atomic_read(&priv->htc->tgt_ready) > 0) {
 125                 atomic_dec(&priv->htc->tgt_ready);
 126                 return 0;
 127         }
 128
 129         /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
 130         time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
 131         if (!time_left) {
 132                 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
 133                 return -ETIMEDOUT;
 134         }
 135
 136         atomic_dec(&priv->htc->tgt_ready);
 137
 138         return 0;
 139 }
 140
 141 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
 142 {
 143         ath9k_htc_exit_debug(priv->ah);
 144         ath9k_hw_deinit(priv->ah);
 145         kfree(priv->ah);
 146         priv->ah = NULL;
 147 }
 148
 149 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
 150 {
 151         struct ieee80211_hw *hw = priv->hw;
 152
 153         wiphy_rfkill_stop_polling(hw->wiphy);
 154         ath9k_deinit_leds(priv);
 155         ieee80211_unregister_hw(hw);
 156         ath9k_rx_cleanup(priv);
 157         ath9k_tx_cleanup(priv);
 158         ath9k_deinit_priv(priv);
 159 }
 160
 161 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
 162                                         u16 service_id,
 163                                         void (*tx) (void *,
 164                                                     struct sk_buff *,
 165                                                     enum htc_endpoint_id,
 166                                                     bool txok),
 167                                         enum htc_endpoint_id *ep_id)
 168 {
 169         struct htc_service_connreq req;
 170
 171         memset(&req, 0, sizeof(struct htc_service_connreq));
 172
 173         req.service_id = service_id;
 174         req.ep_callbacks.priv = priv;
 175         req.ep_callbacks.rx = ath9k_htc_rxep;
 176         req.ep_callbacks.tx = tx;
 177
 178         return htc_connect_service(priv->htc, &req, ep_id);
 179 }
 180
 181 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
 182                                    u32 drv_info)
 183 {
 184         int ret;
 185
 186         /* WMI CMD*/
 187         ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
 188         if (ret)
 189                 goto err;
 190
 191         /* Beacon */
 192         ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
 193                                     &priv->beacon_ep);
 194         if (ret)
 195                 goto err;
 196
 197         /* CAB */
 198         ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
 199                                     &priv->cab_ep);
 200         if (ret)
 201                 goto err;
 202
 203
 204         /* UAPSD */
 205         ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
 206                                     &priv->uapsd_ep);
 207         if (ret)
 208                 goto err;
 209
 210         /* MGMT */
 211         ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
 212                                     &priv->mgmt_ep);
 213         if (ret)
 214                 goto err;
 215
 216         /* DATA BE */
 217         ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
 218                                     &priv->data_be_ep);
 219         if (ret)
 220                 goto err;
 221
 222         /* DATA BK */
 223         ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
 224                                     &priv->data_bk_ep);
 225         if (ret)
 226                 goto err;
 227
 228         /* DATA VI */
 229         ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
 230                                     &priv->data_vi_ep);
 231         if (ret)
 232                 goto err;
 233
 234         /* DATA VO */
 235         ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
 236                                     &priv->data_vo_ep);
 237         if (ret)
 238                 goto err;
 239
 240         /*
 241          * Setup required credits before initializing HTC.
 242          * This is a bit hacky, but, since queuing is done in
 243          * the HIF layer, shouldn't matter much.
 244          */
 245
 246         if (IS_AR7010_DEVICE(drv_info))
 247                 priv->htc->credits = 45;
 248         else
 249                 priv->htc->credits = 33;
 250
 251         ret = htc_init(priv->htc);
 252         if (ret)
 253                 goto err;
 254
 255         dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
 256                  priv->htc->credits);
 257
 258         return 0;
 259
 260 err:
 261         dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
 262         return ret;
 263 }
 264
 265 static int ath9k_reg_notifier(struct wiphy *wiphy,
 266                               struct regulatory_request *request)
 267 {
 268         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 269         struct ath9k_htc_priv *priv = hw->priv;
 270
 271         return ath_reg_notifier_apply(wiphy, request,
 272                                       ath9k_hw_regulatory(priv->ah));
 273 }
 274
 275 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
 276 {
 277         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 278         struct ath_common *common = ath9k_hw_common(ah);
 279         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 280         __be32 val, reg = cpu_to_be32(reg_offset);
 281         int r;
 282
 283         r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
 284                           (u8 *) &reg, sizeof(reg),
 285                           (u8 *) &val, sizeof(val),
 286                           100);
 287         if (unlikely(r)) {
 288                 ath_dbg(common, ATH_DBG_WMI,
 289                         "REGISTER READ FAILED: (0x%04x, %d)\n",
 290                         reg_offset, r);
 291                 return -EIO;
 292         }
 293
 294         return be32_to_cpu(val);
 295 }
 296
 297 static void ath9k_multi_regread(void *hw_priv, u32 *addr,
 298                                 u32 *val, u16 count)
 299 {
 300         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 301         struct ath_common *common = ath9k_hw_common(ah);
 302         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 303         __be32 tmpaddr[8];
 304         __be32 tmpval[8];
 305         int i, ret;
 306
 307        for (i = 0; i < count; i++) {
 308                tmpaddr[i] = cpu_to_be32(addr[i]);
 309        }
 310
 311        ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
 312                            (u8 *)tmpaddr , sizeof(u32) * count,
 313                            (u8 *)tmpval, sizeof(u32) * count,
 314                            100);
 315         if (unlikely(ret)) {
 316                 ath_dbg(common, ATH_DBG_WMI,
 317                         "Multiple REGISTER READ FAILED (count: %d)\n", count);
 318         }
 319
 320        for (i = 0; i < count; i++) {
 321                val[i] = be32_to_cpu(tmpval[i]);
 322        }
 323 }
 324
 325 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
 326 {
 327         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 328         struct ath_common *common = ath9k_hw_common(ah);
 329         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 330         const __be32 buf[2] = {
 331                 cpu_to_be32(reg_offset),
 332                 cpu_to_be32(val),
 333         };
 334         int r;
 335
 336         r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
 337                           (u8 *) &buf, sizeof(buf),
 338                           (u8 *) &val, sizeof(val),
 339                           100);
 340         if (unlikely(r)) {
 341                 ath_dbg(common, ATH_DBG_WMI,
 342                         "REGISTER WRITE FAILED:(0x%04x, %d)\n",
 343                         reg_offset, r);
 344         }
 345 }
 346
 347 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
 348 {
 349         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 350         struct ath_common *common = ath9k_hw_common(ah);
 351         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 352         u32 rsp_status;
 353         int r;
 354
 355         mutex_lock(&priv->wmi->multi_write_mutex);
 356
 357         /* Store the register/value */
 358         priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
 359                 cpu_to_be32(reg_offset);
 360         priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
 361                 cpu_to_be32(val);
 362
 363         priv->wmi->multi_write_idx++;
 364
 365         /* If the buffer is full, send it out. */
 366         if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
 367                 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
 368                           (u8 *) &priv->wmi->multi_write,
 369                           sizeof(struct register_write) * priv->wmi->multi_write_idx,
 370                           (u8 *) &rsp_status, sizeof(rsp_status),
 371                           100);
 372                 if (unlikely(r)) {
 373                         ath_dbg(common, ATH_DBG_WMI,
 374                                 "REGISTER WRITE FAILED, multi len: %d\n",
 375                                 priv->wmi->multi_write_idx);
 376                 }
 377                 priv->wmi->multi_write_idx = 0;
 378         }
 379
 380         mutex_unlock(&priv->wmi->multi_write_mutex);
 381 }
 382
 383 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
 384 {
 385         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 386         struct ath_common *common = ath9k_hw_common(ah);
 387         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 388
 389         if (atomic_read(&priv->wmi->mwrite_cnt))
 390                 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
 391         else
 392                 ath9k_regwrite_single(hw_priv, val, reg_offset);
 393 }
 394
 395 static void ath9k_enable_regwrite_buffer(void *hw_priv)
 396 {
 397         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 398         struct ath_common *common = ath9k_hw_common(ah);
 399         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 400
 401         atomic_inc(&priv->wmi->mwrite_cnt);
 402 }
 403
 404 static void ath9k_regwrite_flush(void *hw_priv)
 405 {
 406         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 407         struct ath_common *common = ath9k_hw_common(ah);
 408         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 409         u32 rsp_status;
 410         int r;
 411
 412         atomic_dec(&priv->wmi->mwrite_cnt);
 413
 414         mutex_lock(&priv->wmi->multi_write_mutex);
 415
 416         if (priv->wmi->multi_write_idx) {
 417                 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
 418                           (u8 *) &priv->wmi->multi_write,
 419                           sizeof(struct register_write) * priv->wmi->multi_write_idx,
 420                           (u8 *) &rsp_status, sizeof(rsp_status),
 421                           100);
 422                 if (unlikely(r)) {
 423                         ath_dbg(common, ATH_DBG_WMI,
 424                                 "REGISTER WRITE FAILED, multi len: %d\n",
 425                                 priv->wmi->multi_write_idx);
 426                 }
 427                 priv->wmi->multi_write_idx = 0;
 428         }
 429
 430         mutex_unlock(&priv->wmi->multi_write_mutex);
 431 }
 432
 433 static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
 434 {
 435         u32 val;
 436
 437         val = ath9k_regread(hw_priv, reg_offset);
 438         val &= ~clr;
 439         val |= set;
 440         ath9k_regwrite(hw_priv, val, reg_offset);
 441         return val;
 442 }
 443
 444 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
 445 {
 446         *csz = L1_CACHE_BYTES >> 2;
 447 }
 448
 449 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 450 {
 451         struct ath_hw *ah = (struct ath_hw *) common->ah;
 452
 453         (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 454
 455         if (!ath9k_hw_wait(ah,
 456                            AR_EEPROM_STATUS_DATA,
 457                            AR_EEPROM_STATUS_DATA_BUSY |
 458                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
 459                            AH_WAIT_TIMEOUT))
 460                 return false;
 461
 462         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 463                    AR_EEPROM_STATUS_DATA_VAL);
 464
 465         return true;
 466 }
 467
 468 static const struct ath_bus_ops ath9k_usb_bus_ops = {
 469         .ath_bus_type = ATH_USB,
 470         .read_cachesize = ath_usb_read_cachesize,
 471         .eeprom_read = ath_usb_eeprom_read,
 472 };
 473
 474 static void setup_ht_cap(struct ath9k_htc_priv *priv,
 475                          struct ieee80211_sta_ht_cap *ht_info)
 476 {
 477         struct ath_common *common = ath9k_hw_common(priv->ah);
 478         u8 tx_streams, rx_streams;
 479         int i;
 480
 481         ht_info->ht_supported = true;
 482         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 483                        IEEE80211_HT_CAP_SM_PS |
 484                        IEEE80211_HT_CAP_SGI_40 |
 485                        IEEE80211_HT_CAP_DSSSCCK40;
 486
 487         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
 488                 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
 489
 490         ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
 491
 492         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 493         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 494
 495         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 496
 497         /* ath9k_htc supports only 1 or 2 stream devices */
 498         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
 499         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
 500
 501         ath_dbg(common, ATH_DBG_CONFIG,
 502                 "TX streams %d, RX streams: %d\n",
 503                 tx_streams, rx_streams);
 504
 505         if (tx_streams != rx_streams) {
 506                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 507                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 508                                            IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 509         }
 510
 511         for (i = 0; i < rx_streams; i++)
 512                 ht_info->mcs.rx_mask[i] = 0xff;
 513
 514         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 515 }
 516
 517 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
 518 {
 519         struct ath_common *common = ath9k_hw_common(priv->ah);
 520         int i;
 521
 522         for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
 523                 priv->hwq_map[i] = -1;
 524
 525         priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
 526         if (priv->beaconq == -1) {
 527                 ath_err(common, "Unable to setup BEACON xmit queue\n");
 528                 goto err;
 529         }
 530
 531         priv->cabq = ath9k_htc_cabq_setup(priv);
 532         if (priv->cabq == -1) {
 533                 ath_err(common, "Unable to setup CAB xmit queue\n");
 534                 goto err;
 535         }
 536
 537         if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
 538                 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
 539                 goto err;
 540         }
 541
 542         if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
 543                 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
 544                 goto err;
 545         }
 546         if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
 547                 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
 548                 goto err;
 549         }
 550         if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
 551                 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
 552                 goto err;
 553         }
 554
 555         return 0;
 556
 557 err:
 558         return -EINVAL;
 559 }
 560
 561 static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
 562 {
 563         struct ath_common *common = ath9k_hw_common(priv->ah);
 564         int i = 0;
 565
 566         /* Get the hardware key cache size. */
 567         common->keymax = AR_KEYTABLE_SIZE;
 568
 569         if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
 570                 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
 571
 572         /*
 573          * Reset the key cache since some parts do not
 574          * reset the contents on initial power up.
 575          */
 576         for (i = 0; i < common->keymax; i++)
 577                 ath_hw_keyreset(common, (u16) i);
 578 }
 579
 580 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
 581 {
 582         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
 583                 priv->sbands[IEEE80211_BAND_2GHZ].channels =
 584                         ath9k_2ghz_channels;
 585                 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
 586                 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
 587                         ARRAY_SIZE(ath9k_2ghz_channels);
 588                 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
 589                 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
 590                         ARRAY_SIZE(ath9k_legacy_rates);
 591         }
 592
 593         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
 594                 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
 595                 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
 596                 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
 597                         ARRAY_SIZE(ath9k_5ghz_channels);
 598                 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
 599                         ath9k_legacy_rates + 4;
 600                 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
 601                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
 602         }
 603 }
 604
 605 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
 606 {
 607         struct ath_common *common = ath9k_hw_common(priv->ah);
 608
 609         common->tx_chainmask = priv->ah->caps.tx_chainmask;
 610         common->rx_chainmask = priv->ah->caps.rx_chainmask;
 611
 612         memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 613
 614         priv->ah->opmode = NL80211_IFTYPE_STATION;
 615 }
 616
 617 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
 618 {
 619         int qnum;
 620
 621         switch (priv->ah->btcoex_hw.scheme) {
 622         case ATH_BTCOEX_CFG_NONE:
 623                 break;
 624         case ATH_BTCOEX_CFG_3WIRE:
 625                 priv->ah->btcoex_hw.btactive_gpio = 7;
 626                 priv->ah->btcoex_hw.btpriority_gpio = 6;
 627                 priv->ah->btcoex_hw.wlanactive_gpio = 8;
 628                 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
 629                 ath9k_hw_btcoex_init_3wire(priv->ah);
 630                 ath_htc_init_btcoex_work(priv);
 631                 qnum = priv->hwq_map[WME_AC_BE];
 632                 ath9k_hw_init_btcoex_hw(priv->ah, qnum);
 633                 break;
 634         default:
 635                 WARN_ON(1);
 636                 break;
 637         }
 638 }
 639
 640 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
 641                            u16 devid, char *product,
 642                            u32 drv_info)
 643 {
 644         struct ath_hw *ah = NULL;
 645         struct ath_common *common;
 646         int i, ret = 0, csz = 0;
 647
 648         priv->op_flags |= OP_INVALID;
 649
 650         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 651         if (!ah)
 652                 return -ENOMEM;
 653
 654         ah->hw_version.devid = devid;
 655         ah->hw_version.subsysid = 0; /* FIXME */
 656         ah->hw_version.usbdev = drv_info;
 657         ah->ah_flags |= AH_USE_EEPROM;
 658         ah->reg_ops.read = ath9k_regread;
 659         ah->reg_ops.multi_read = ath9k_multi_regread;
 660         ah->reg_ops.write = ath9k_regwrite;
 661         ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
 662         ah->reg_ops.write_flush = ath9k_regwrite_flush;
 663         ah->reg_ops.rmw = ath9k_reg_rmw;
 664         priv->ah = ah;
 665
 666         common = ath9k_hw_common(ah);
 667         common->ops = &ah->reg_ops;
 668         common->bus_ops = &ath9k_usb_bus_ops;
 669         common->ah = ah;
 670         common->hw = priv->hw;
 671         common->priv = priv;
 672         common->debug_mask = ath9k_debug;
 673
 674         spin_lock_init(&priv->wmi->wmi_lock);
 675         spin_lock_init(&priv->beacon_lock);
 676         spin_lock_init(&priv->tx_lock);
 677         mutex_init(&priv->mutex);
 678         mutex_init(&priv->htc_pm_lock);
 679         tasklet_init(&priv->swba_tasklet, ath9k_swba_tasklet,
 680                      (unsigned long)priv);
 681         tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
 682                      (unsigned long)priv);
 683         tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet,
 684                      (unsigned long)priv);
 685         INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
 686         INIT_WORK(&priv->ps_work, ath9k_ps_work);
 687         INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
 688
 689         /*
 690          * Cache line size is used to size and align various
 691          * structures used to communicate with the hardware.
 692          */
 693         ath_read_cachesize(common, &csz);
 694         common->cachelsz = csz << 2; /* convert to bytes */
 695
 696         ret = ath9k_hw_init(ah);
 697         if (ret) {
 698                 ath_err(common,
 699                         "Unable to initialize hardware; initialization status: %d\n",
 700                         ret);
 701                 goto err_hw;
 702         }
 703
 704         ret = ath9k_htc_init_debug(ah);
 705         if (ret) {
 706                 ath_err(common, "Unable to create debugfs files\n");
 707                 goto err_debug;
 708         }
 709
 710         ret = ath9k_init_queues(priv);
 711         if (ret)
 712                 goto err_queues;
 713
 714         for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
 715                 priv->cur_beacon_conf.bslot[i] = NULL;
 716
 717         ath9k_init_crypto(priv);
 718         ath9k_init_channels_rates(priv);
 719         ath9k_init_misc(priv);
 720
 721         if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
 722                 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
 723                 ath9k_init_btcoex(priv);
 724         }
 725
 726         return 0;
 727
 728 err_queues:
 729         ath9k_htc_exit_debug(ah);
 730 err_debug:
 731         ath9k_hw_deinit(ah);
 732 err_hw:
 733
 734         kfree(ah);
 735         priv->ah = NULL;
 736
 737         return ret;
 738 }
 739
 740 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
 741                                struct ieee80211_hw *hw)
 742 {
 743         struct ath_common *common = ath9k_hw_common(priv->ah);
 744
 745         hw->flags = IEEE80211_HW_SIGNAL_DBM |
 746                 IEEE80211_HW_AMPDU_AGGREGATION |
 747                 IEEE80211_HW_SPECTRUM_MGMT |
 748                 IEEE80211_HW_HAS_RATE_CONTROL |
 749                 IEEE80211_HW_RX_INCLUDES_FCS |
 750                 IEEE80211_HW_SUPPORTS_PS |
 751                 IEEE80211_HW_PS_NULLFUNC_STACK |
 752                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
 753
 754         hw->wiphy->interface_modes =
 755                 BIT(NL80211_IFTYPE_STATION) |
 756                 BIT(NL80211_IFTYPE_ADHOC);
 757
 758         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 759
 760         hw->queues = 4;
 761         hw->channel_change_time = 5000;
 762         hw->max_listen_interval = 10;
 763         hw->vif_data_size = sizeof(struct ath9k_htc_vif);
 764         hw->sta_data_size = sizeof(struct ath9k_htc_sta);
 765
 766         /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
 767         hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
 768                 sizeof(struct htc_frame_hdr) + 4;
 769
 770         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 771                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 772                         &priv->sbands[IEEE80211_BAND_2GHZ];
 773         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 774                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 775                         &priv->sbands[IEEE80211_BAND_5GHZ];
 776
 777         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
 778                 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 779                         setup_ht_cap(priv,
 780                                      &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
 781                 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 782                         setup_ht_cap(priv,
 783                                      &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
 784         }
 785
 786         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 787 }
 788
 789 static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
 790 {
 791         struct ieee80211_hw *hw = priv->hw;
 792         struct wmi_fw_version cmd_rsp;
 793         int ret;
 794
 795         memset(&cmd_rsp, 0, sizeof(cmd_rsp));
 796
 797         WMI_CMD(WMI_GET_FW_VERSION);
 798         if (ret)
 799                 return -EINVAL;
 800
 801         priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
 802         priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
 803
 804         snprintf(hw->wiphy->fw_version, ETHTOOL_BUSINFO_LEN, "%d.%d",
 805                  priv->fw_version_major,
 806                  priv->fw_version_minor);
 807
 808         dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
 809                  priv->fw_version_major,
 810                  priv->fw_version_minor);
 811
 812         return 0;
 813 }
 814
 815 static int ath9k_init_device(struct ath9k_htc_priv *priv,
 816                              u16 devid, char *product, u32 drv_info)
 817 {
 818         struct ieee80211_hw *hw = priv->hw;
 819         struct ath_common *common;
 820         struct ath_hw *ah;
 821         int error = 0;
 822         struct ath_regulatory *reg;
 823         char hw_name[64];
 824
 825         /* Bring up device */
 826         error = ath9k_init_priv(priv, devid, product, drv_info);
 827         if (error != 0)
 828                 goto err_init;
 829
 830         ah = priv->ah;
 831         common = ath9k_hw_common(ah);
 832         ath9k_set_hw_capab(priv, hw);
 833
 834         error = ath9k_init_firmware_version(priv);
 835         if (error != 0)
 836                 goto err_fw;
 837
 838         /* Initialize regulatory */
 839         error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
 840                               ath9k_reg_notifier);
 841         if (error)
 842                 goto err_regd;
 843
 844         reg = &common->regulatory;
 845
 846         /* Setup TX */
 847         error = ath9k_tx_init(priv);
 848         if (error != 0)
 849                 goto err_tx;
 850
 851         /* Setup RX */
 852         error = ath9k_rx_init(priv);
 853         if (error != 0)
 854                 goto err_rx;
 855
 856         /* Register with mac80211 */
 857         error = ieee80211_register_hw(hw);
 858         if (error)
 859                 goto err_register;
 860
 861         /* Handle world regulatory */
 862         if (!ath_is_world_regd(reg)) {
 863                 error = regulatory_hint(hw->wiphy, reg->alpha2);
 864                 if (error)
 865                         goto err_world;
 866         }
 867
 868         ath_dbg(common, ATH_DBG_CONFIG,
 869                 "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, "
 870                 "BE:%d, BK:%d, VI:%d, VO:%d\n",
 871                 priv->wmi_cmd_ep,
 872                 priv->beacon_ep,
 873                 priv->cab_ep,
 874                 priv->uapsd_ep,
 875                 priv->mgmt_ep,
 876                 priv->data_be_ep,
 877                 priv->data_bk_ep,
 878                 priv->data_vi_ep,
 879                 priv->data_vo_ep);
 880
 881         ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
 882         wiphy_info(hw->wiphy, "%s\n", hw_name);
 883
 884         ath9k_init_leds(priv);
 885         ath9k_start_rfkill_poll(priv);
 886
 887         return 0;
 888
 889 err_world:
 890         ieee80211_unregister_hw(hw);
 891 err_register:
 892         ath9k_rx_cleanup(priv);
 893 err_rx:
 894         ath9k_tx_cleanup(priv);
 895 err_tx:
 896         /* Nothing */
 897 err_regd:
 898         /* Nothing */
 899 err_fw:
 900         ath9k_deinit_priv(priv);
 901 err_init:
 902         return error;
 903 }
 904
 905 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
 906                            u16 devid, char *product, u32 drv_info)
 907 {
 908         struct ieee80211_hw *hw;
 909         struct ath9k_htc_priv *priv;
 910         int ret;
 911
 912         hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
 913         if (!hw)
 914                 return -ENOMEM;
 915
 916         priv = hw->priv;
 917         priv->hw = hw;
 918         priv->htc = htc_handle;
 919         priv->dev = dev;
 920         htc_handle->drv_priv = priv;
 921         SET_IEEE80211_DEV(hw, priv->dev);
 922
 923         ret = ath9k_htc_wait_for_target(priv);
 924         if (ret)
 925                 goto err_free;
 926
 927         priv->wmi = ath9k_init_wmi(priv);
 928         if (!priv->wmi) {
 929                 ret = -EINVAL;
 930                 goto err_free;
 931         }
 932
 933         ret = ath9k_init_htc_services(priv, devid, drv_info);
 934         if (ret)
 935                 goto err_init;
 936
 937         ret = ath9k_init_device(priv, devid, product, drv_info);
 938         if (ret)
 939                 goto err_init;
 940
 941         return 0;
 942
 943 err_init:
 944         ath9k_deinit_wmi(priv);
 945 err_free:
 946         ieee80211_free_hw(hw);
 947         return ret;
 948 }
 949
 950 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 951 {
 952         if (htc_handle->drv_priv) {
 953
 954                 /* Check if the device has been yanked out. */
 955                 if (hotunplug)
 956                         htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
 957
 958                 ath9k_deinit_device(htc_handle->drv_priv);
 959                 ath9k_deinit_wmi(htc_handle->drv_priv);
 960                 ieee80211_free_hw(htc_handle->drv_priv->hw);
 961         }
 962 }
 963
 964 #ifdef CONFIG_PM
 965
 966 void ath9k_htc_suspend(struct htc_target *htc_handle)
 967 {
 968         ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
 969 }
 970
 971 int ath9k_htc_resume(struct htc_target *htc_handle)
 972 {
 973         struct ath9k_htc_priv *priv = htc_handle->drv_priv;
 974         int ret;
 975
 976         ret = ath9k_htc_wait_for_target(priv);
 977         if (ret)
 978                 return ret;
 979
 980         ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
 981                                       priv->ah->hw_version.usbdev);
 982         return ret;
 983 }
 984 #endif
 985
 986 static int __init ath9k_htc_init(void)
 987 {
 988         int error;
 989
 990         error = ath9k_htc_debug_create_root();
 991         if (error < 0) {
 992                 printk(KERN_ERR
 993                         "ath9k_htc: Unable to create debugfs root: %d\n",
 994                         error);
 995                 goto err_dbg;
 996         }
 997
 998         error = ath9k_hif_usb_init();
 999         if (error < 0) {
1000                 printk(KERN_ERR
1001                         "ath9k_htc: No USB devices found,"
1002                         " driver not installed.\n");
1003                 error = -ENODEV;
1004                 goto err_usb;
1005         }
1006
1007         return 0;
1008
1009 err_usb:
1010         ath9k_htc_debug_remove_root();
1011 err_dbg:
1012         return error;
1013 }
1014 module_init(ath9k_htc_init);
1015
1016 static void __exit ath9k_htc_exit(void)
1017 {
1018         ath9k_hif_usb_exit();
1019         ath9k_htc_debug_remove_root();
1020         printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
1021 }
1022 module_exit(ath9k_htc_exit);