drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19
  20 static const int firstep_table[] =
  21 /* level:  0   1   2   3   4   5   6   7   8  */
  22         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  23
  24 static const int cycpwrThr1_table[] =
  25 /* level:  0   1   2   3   4   5   6   7   8  */
  26         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  27
  28 /*
  29  * register values to turn OFDM weak signal detection OFF
  30  */
  31 static const int m1ThreshLow_off = 127;
  32 static const int m2ThreshLow_off = 127;
  33 static const int m1Thresh_off = 127;
  34 static const int m2Thresh_off = 127;
  35 static const int m2CountThr_off =  31;
  36 static const int m2CountThrLow_off =  63;
  37 static const int m1ThreshLowExt_off = 127;
  38 static const int m2ThreshLowExt_off = 127;
  39 static const int m1ThreshExt_off = 127;
  40 static const int m2ThreshExt_off = 127;
  41
  42 /**
  43  * ar9003_hw_set_channel - set channel on single-chip device
  44  * @ah: atheros hardware structure
  45  * @chan:
  46  *
  47  * This is the function to change channel on single-chip devices, that is
  48  * all devices after ar9280.
  49  *
  50  * This function takes the channel value in MHz and sets
  51  * hardware channel value. Assumes writes have been enabled to analog bus.
  52  *
  53  * Actual Expression,
  54  *
  55  * For 2GHz channel,
  56  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  57  * (freq_ref = 40MHz)
  58  *
  59  * For 5GHz channel,
  60  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  61  * (freq_ref = 40MHz/(24>>amodeRefSel))
  62  *
  63  * For 5GHz channels which are 5MHz spaced,
  64  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  65  * (freq_ref = 40MHz)
  66  */
  67 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  68 {
  69         u16 bMode, fracMode = 0, aModeRefSel = 0;
  70         u32 freq, channelSel = 0, reg32 = 0;
  71         struct chan_centers centers;
  72         int loadSynthChannel;
  73
  74         ath9k_hw_get_channel_centers(ah, chan, &centers);
  75         freq = centers.synth_center;
  76
  77         if (freq < 4800) {     /* 2 GHz, fractional mode */
  78                 if (AR_SREV_9485(ah)) {
  79                         u32 chan_frac;
  80
  81                         /*
  82                          * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
  83                          * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
  84                          * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
  85                          */
  86                         channelSel = (freq * 4) / 120;
  87                         chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
  88                         channelSel = (channelSel << 17) | chan_frac;
  89                 } else if (AR_SREV_9340(ah)) {
  90                         if (ah->is_clk_25mhz) {
  91                                 u32 chan_frac;
  92
  93                                 channelSel = (freq * 2) / 75;
  94                                 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
  95                                 channelSel = (channelSel << 17) | chan_frac;
  96                         } else
  97                                 channelSel = CHANSEL_2G(freq) >> 1;
  98                 } else
  99                         channelSel = CHANSEL_2G(freq);
 100                 /* Set to 2G mode */
 101                 bMode = 1;
 102         } else {
 103                 if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
 104                         u32 chan_frac;
 105
 106                         channelSel = (freq * 2) / 75;
 107                         chan_frac = ((freq % 75) * 0x20000) / 75;
 108                         channelSel = (channelSel << 17) | chan_frac;
 109                 } else {
 110                         channelSel = CHANSEL_5G(freq);
 111                         /* Doubler is ON, so, divide channelSel by 2. */
 112                         channelSel >>= 1;
 113                 }
 114                 /* Set to 5G mode */
 115                 bMode = 0;
 116         }
 117
 118         /* Enable fractional mode for all channels */
 119         fracMode = 1;
 120         aModeRefSel = 0;
 121         loadSynthChannel = 0;
 122
 123         reg32 = (bMode << 29);
 124         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
 125
 126         /* Enable Long shift Select for Synthesizer */
 127         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
 128                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
 129
 130         /* Program Synth. setting */
 131         reg32 = (channelSel << 2) | (fracMode << 30) |
 132                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 133         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 134
 135         /* Toggle Load Synth channel bit */
 136         loadSynthChannel = 1;
 137         reg32 = (channelSel << 2) | (fracMode << 30) |
 138                 (aModeRefSel << 28) | (loadSynthChannel << 31);
 139         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
 140
 141         ah->curchan = chan;
 142         ah->curchan_rad_index = -1;
 143
 144         return 0;
 145 }
 146
 147 /**
 148  * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
 149  * @ah: atheros hardware structure
 150  * @chan:
 151  *
 152  * For single-chip solutions. Converts to baseband spur frequency given the
 153  * input channel frequency and compute register settings below.
 154  *
 155  * Spur mitigation for MRC CCK
 156  */
 157 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 158                                             struct ath9k_channel *chan)
 159 {
 160         static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 161         int cur_bb_spur, negative = 0, cck_spur_freq;
 162         int i;
 163         int range, max_spur_cnts, synth_freq;
 164         u8 *spur_fbin_ptr = NULL;
 165
 166         /*
 167          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 168          * is out-of-band and can be ignored.
 169          */
 170
 171         if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
 172                 spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
 173                                                          IS_CHAN_2GHZ(chan));
 174                 if (spur_fbin_ptr[0] == 0) /* No spur */
 175                         return;
 176                 max_spur_cnts = 5;
 177                 if (IS_CHAN_HT40(chan)) {
 178                         range = 19;
 179                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 180                                            AR_PHY_GC_DYN2040_PRI_CH) == 0)
 181                                 synth_freq = chan->channel + 10;
 182                         else
 183                                 synth_freq = chan->channel - 10;
 184                 } else {
 185                         range = 10;
 186                         synth_freq = chan->channel;
 187                 }
 188         } else {
 189                 range = 10;
 190                 max_spur_cnts = 4;
 191                 synth_freq = chan->channel;
 192         }
 193
 194         for (i = 0; i < max_spur_cnts; i++) {
 195                 negative = 0;
 196                 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
 197                         cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
 198                                         IS_CHAN_2GHZ(chan)) - synth_freq;
 199                 else
 200                         cur_bb_spur = spur_freq[i] - synth_freq;
 201
 202                 if (cur_bb_spur < 0) {
 203                         negative = 1;
 204                         cur_bb_spur = -cur_bb_spur;
 205                 }
 206                 if (cur_bb_spur < range) {
 207                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 208
 209                         if (negative == 1)
 210                                 cck_spur_freq = -cck_spur_freq;
 211
 212                         cck_spur_freq = cck_spur_freq & 0xfffff;
 213
 214                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 215                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 216                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 217                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 218                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 219                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 220                                       0x2);
 221                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 222                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 223                                       0x1);
 224                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 225                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 226                                       cck_spur_freq);
 227
 228                         return;
 229                 }
 230         }
 231
 232         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 233                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 234         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 235                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 236         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 237                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 238 }
 239
 240 /* Clean all spur register fields */
 241 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 242 {
 243         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 244                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 245         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 246                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 247         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 248                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 249         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 250                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 251         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 252                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 253         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 254                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 255         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 256                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 257         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 258                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 259         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 260                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 261
 262         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 263                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 264         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 265                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 266         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 267                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 268         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 269                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 270         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 271                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 272         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 273                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 274         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 275                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 276         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 277                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 278         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 279                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 280         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 281                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 282 }
 283
 284 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 285                                 int freq_offset,
 286                                 int spur_freq_sd,
 287                                 int spur_delta_phase,
 288                                 int spur_subchannel_sd)
 289 {
 290         int mask_index = 0;
 291
 292         /* OFDM Spur mitigation */
 293         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 294                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 295         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 296                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 297         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 298                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 299         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 300                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 301         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 302                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 303         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 304                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 305         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 306                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 307         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 308                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 309         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 310                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 311
 312         if (REG_READ_FIELD(ah, AR_PHY_MODE,
 313                            AR_PHY_MODE_DYNAMIC) == 0x1)
 314                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 315                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 316
 317         mask_index = (freq_offset << 4) / 5;
 318         if (mask_index < 0)
 319                 mask_index = mask_index - 1;
 320
 321         mask_index = mask_index & 0x7f;
 322
 323         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 324                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 325         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 326                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 327         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 328                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 329         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 330                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 331         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 332                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 333         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 334                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 335         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 336                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 337         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 338                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 339         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 340                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 341         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 342                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 343 }
 344
 345 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 346                                      struct ath9k_channel *chan,
 347                                      int freq_offset)
 348 {
 349         int spur_freq_sd = 0;
 350         int spur_subchannel_sd = 0;
 351         int spur_delta_phase = 0;
 352
 353         if (IS_CHAN_HT40(chan)) {
 354                 if (freq_offset < 0) {
 355                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 356                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 357                                 spur_subchannel_sd = 1;
 358                         else
 359                                 spur_subchannel_sd = 0;
 360
 361                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 362
 363                 } else {
 364                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 365                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 366                                 spur_subchannel_sd = 0;
 367                         else
 368                                 spur_subchannel_sd = 1;
 369
 370                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 371
 372                 }
 373
 374                 spur_delta_phase = (freq_offset << 17) / 5;
 375
 376         } else {
 377                 spur_subchannel_sd = 0;
 378                 spur_freq_sd = (freq_offset << 9) /11;
 379                 spur_delta_phase = (freq_offset << 18) / 5;
 380         }
 381
 382         spur_freq_sd = spur_freq_sd & 0x3ff;
 383         spur_delta_phase = spur_delta_phase & 0xfffff;
 384
 385         ar9003_hw_spur_ofdm(ah,
 386                             freq_offset,
 387                             spur_freq_sd,
 388                             spur_delta_phase,
 389                             spur_subchannel_sd);
 390 }
 391
 392 /* Spur mitigation for OFDM */
 393 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 394                                          struct ath9k_channel *chan)
 395 {
 396         int synth_freq;
 397         int range = 10;
 398         int freq_offset = 0;
 399         int mode;
 400         u8* spurChansPtr;
 401         unsigned int i;
 402         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 403
 404         if (IS_CHAN_5GHZ(chan)) {
 405                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 406                 mode = 0;
 407         }
 408         else {
 409                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 410                 mode = 1;
 411         }
 412
 413         if (spurChansPtr[0] == 0)
 414                 return; /* No spur in the mode */
 415
 416         if (IS_CHAN_HT40(chan)) {
 417                 range = 19;
 418                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 419                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 420                         synth_freq = chan->channel - 10;
 421                 else
 422                         synth_freq = chan->channel + 10;
 423         } else {
 424                 range = 10;
 425                 synth_freq = chan->channel;
 426         }
 427
 428         ar9003_hw_spur_ofdm_clear(ah);
 429
 430         for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
 431                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
 432                 if (abs(freq_offset) < range) {
 433                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
 434                         break;
 435                 }
 436         }
 437 }
 438
 439 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 440                                     struct ath9k_channel *chan)
 441 {
 442         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 443         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 444 }
 445
 446 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 447                                          struct ath9k_channel *chan)
 448 {
 449         u32 pll;
 450
 451         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 452
 453         if (chan && IS_CHAN_HALF_RATE(chan))
 454                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 455         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 456                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 457
 458         pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 459
 460         return pll;
 461 }
 462
 463 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 464                                        struct ath9k_channel *chan)
 465 {
 466         u32 phymode;
 467         u32 enableDacFifo = 0;
 468
 469         enableDacFifo =
 470                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 471
 472         /* Enable 11n HT, 20 MHz */
 473         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
 474                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 475
 476         /* Configure baseband for dynamic 20/40 operation */
 477         if (IS_CHAN_HT40(chan)) {
 478                 phymode |= AR_PHY_GC_DYN2040_EN;
 479                 /* Configure control (primary) channel at +-10MHz */
 480                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 481                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 482                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 483
 484         }
 485
 486         /* make sure we preserve INI settings */
 487         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 488         /* turn off Green Field detection for STA for now */
 489         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 490
 491         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 492
 493         /* Configure MAC for 20/40 operation */
 494         ath9k_hw_set11nmac2040(ah);
 495
 496         /* global transmit timeout (25 TUs default)*/
 497         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 498         /* carrier sense timeout */
 499         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 500 }
 501
 502 static void ar9003_hw_init_bb(struct ath_hw *ah,
 503                               struct ath9k_channel *chan)
 504 {
 505         u32 synthDelay;
 506
 507         /*
 508          * Wait for the frequency synth to settle (synth goes on
 509          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 510          * Value is in 100ns increments.
 511          */
 512         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 513         if (IS_CHAN_B(chan))
 514                 synthDelay = (4 * synthDelay) / 22;
 515         else
 516                 synthDelay /= 10;
 517
 518         /* Activate the PHY (includes baseband activate + synthesizer on) */
 519         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 520
 521         /*
 522          * There is an issue if the AP starts the calibration before
 523          * the base band timeout completes.  This could result in the
 524          * rx_clear false triggering.  As a workaround we add delay an
 525          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 526          * does not happen.
 527          */
 528         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 529 }
 530
 531 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 532 {
 533         switch (rx) {
 534         case 0x5:
 535                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 536                             AR_PHY_SWAP_ALT_CHAIN);
 537         case 0x3:
 538         case 0x1:
 539         case 0x2:
 540         case 0x7:
 541                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 542                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 543                 break;
 544         default:
 545                 break;
 546         }
 547
 548         if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
 549                 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
 550         else
 551                 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 552
 553         if (tx == 0x5) {
 554                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 555                             AR_PHY_SWAP_ALT_CHAIN);
 556         }
 557 }
 558
 559 /*
 560  * Override INI values with chip specific configuration.
 561  */
 562 static void ar9003_hw_override_ini(struct ath_hw *ah)
 563 {
 564         u32 val;
 565
 566         /*
 567          * Set the RX_ABORT and RX_DIS and clear it only after
 568          * RXE is set for MAC. This prevents frames with
 569          * corrupted descriptor status.
 570          */
 571         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 572
 573         /*
 574          * For AR9280 and above, there is a new feature that allows
 575          * Multicast search based on both MAC Address and Key ID. By default,
 576          * this feature is enabled. But since the driver is not using this
 577          * feature, we switch it off; otherwise multicast search based on
 578          * MAC addr only will fail.
 579          */
 580         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 581         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 582                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 583 }
 584
 585 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 586                                struct ar5416IniArray *iniArr,
 587                                int column)
 588 {
 589         unsigned int i, regWrites = 0;
 590
 591         /* New INI format: Array may be undefined (pre, core, post arrays) */
 592         if (!iniArr->ia_array)
 593                 return;
 594
 595         /*
 596          * New INI format: Pre, core, and post arrays for a given subsystem
 597          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 598          * the array is non-modal and force the column to 1.
 599          */
 600         if (column >= iniArr->ia_columns)
 601                 column = 1;
 602
 603         for (i = 0; i < iniArr->ia_rows; i++) {
 604                 u32 reg = INI_RA(iniArr, i, 0);
 605                 u32 val = INI_RA(iniArr, i, column);
 606
 607                 REG_WRITE(ah, reg, val);
 608
 609                 DO_DELAY(regWrites);
 610         }
 611 }
 612
 613 static int ar9003_hw_process_ini(struct ath_hw *ah,
 614                                  struct ath9k_channel *chan)
 615 {
 616         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 617         unsigned int regWrites = 0, i;
 618         struct ieee80211_channel *channel = chan->chan;
 619         u32 modesIndex, freqIndex;
 620
 621         switch (chan->chanmode) {
 622         case CHANNEL_A:
 623         case CHANNEL_A_HT20:
 624                 modesIndex = 1;
 625                 freqIndex = 1;
 626                 break;
 627         case CHANNEL_A_HT40PLUS:
 628         case CHANNEL_A_HT40MINUS:
 629                 modesIndex = 2;
 630                 freqIndex = 1;
 631                 break;
 632         case CHANNEL_G:
 633         case CHANNEL_G_HT20:
 634         case CHANNEL_B:
 635                 modesIndex = 4;
 636                 freqIndex = 2;
 637                 break;
 638         case CHANNEL_G_HT40PLUS:
 639         case CHANNEL_G_HT40MINUS:
 640                 modesIndex = 3;
 641                 freqIndex = 2;
 642                 break;
 643
 644         default:
 645                 return -EINVAL;
 646         }
 647
 648         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 649                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 650                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 651                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 652                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 653         }
 654
 655         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 656         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 657
 658         /*
 659          * For 5GHz channels requiring Fast Clock, apply
 660          * different modal values.
 661          */
 662         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 663                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
 664                                 modesIndex, regWrites);
 665
 666         if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
 667                 REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
 668
 669         ar9003_hw_override_ini(ah);
 670         ar9003_hw_set_channel_regs(ah, chan);
 671         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 672
 673         /* Set TX power */
 674         ah->eep_ops->set_txpower(ah, chan,
 675                                  ath9k_regd_get_ctl(regulatory, chan),
 676                                  channel->max_antenna_gain * 2,
 677                                  channel->max_power * 2,
 678                                  min((u32) MAX_RATE_POWER,
 679                                  (u32) regulatory->power_limit), false);
 680
 681         return 0;
 682 }
 683
 684 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 685                                  struct ath9k_channel *chan)
 686 {
 687         u32 rfMode = 0;
 688
 689         if (chan == NULL)
 690                 return;
 691
 692         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 693                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 694
 695         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 696                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 697
 698         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 699 }
 700
 701 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 702 {
 703         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 704 }
 705
 706 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 707                                       struct ath9k_channel *chan)
 708 {
 709         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 710         u32 clockMhzScaled = 0x64000000;
 711         struct chan_centers centers;
 712
 713         /*
 714          * half and quarter rate can divide the scaled clock by 2 or 4
 715          * scale for selected channel bandwidth
 716          */
 717         if (IS_CHAN_HALF_RATE(chan))
 718                 clockMhzScaled = clockMhzScaled >> 1;
 719         else if (IS_CHAN_QUARTER_RATE(chan))
 720                 clockMhzScaled = clockMhzScaled >> 2;
 721
 722         /*
 723          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 724          * scaled coef to provide precision for this floating calculation
 725          */
 726         ath9k_hw_get_channel_centers(ah, chan, &centers);
 727         coef_scaled = clockMhzScaled / centers.synth_center;
 728
 729         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 730                                       &ds_coef_exp);
 731
 732         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 733                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 734         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 735                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 736
 737         /*
 738          * For Short GI,
 739          * scaled coeff is 9/10 that of normal coeff
 740          */
 741         coef_scaled = (9 * coef_scaled) / 10;
 742
 743         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 744                                       &ds_coef_exp);
 745
 746         /* for short gi */
 747         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 748                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 749         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 750                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 751 }
 752
 753 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 754 {
 755         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 756         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 757                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 758 }
 759
 760 /*
 761  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 762  * Read the phy active delay register. Value is in 100ns increments.
 763  */
 764 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 765 {
 766         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 767         if (IS_CHAN_B(ah->curchan))
 768                 synthDelay = (4 * synthDelay) / 22;
 769         else
 770                 synthDelay /= 10;
 771
 772         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 773
 774         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 775 }
 776
 777 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 778 {
 779         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 780         if (value)
 781                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 782         else
 783                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 784         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
 785 }
 786
 787 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 788                                   enum ath9k_ani_cmd cmd, int param)
 789 {
 790         struct ath_common *common = ath9k_hw_common(ah);
 791         struct ath9k_channel *chan = ah->curchan;
 792         struct ar5416AniState *aniState = &chan->ani;
 793         s32 value, value2;
 794
 795         switch (cmd & ah->ani_function) {
 796         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 797                 /*
 798                  * on == 1 means ofdm weak signal detection is ON
 799                  * on == 1 is the default, for less noise immunity
 800                  *
 801                  * on == 0 means ofdm weak signal detection is OFF
 802                  * on == 0 means more noise imm
 803                  */
 804                 u32 on = param ? 1 : 0;
 805                 /*
 806                  * make register setting for default
 807                  * (weak sig detect ON) come from INI file
 808                  */
 809                 int m1ThreshLow = on ?
 810                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
 811                 int m2ThreshLow = on ?
 812                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
 813                 int m1Thresh = on ?
 814                         aniState->iniDef.m1Thresh : m1Thresh_off;
 815                 int m2Thresh = on ?
 816                         aniState->iniDef.m2Thresh : m2Thresh_off;
 817                 int m2CountThr = on ?
 818                         aniState->iniDef.m2CountThr : m2CountThr_off;
 819                 int m2CountThrLow = on ?
 820                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
 821                 int m1ThreshLowExt = on ?
 822                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
 823                 int m2ThreshLowExt = on ?
 824                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
 825                 int m1ThreshExt = on ?
 826                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
 827                 int m2ThreshExt = on ?
 828                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
 829
 830                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 831                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 832                               m1ThreshLow);
 833                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 834                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 835                               m2ThreshLow);
 836                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 837                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
 838                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 839                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
 840                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 841                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
 842                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 843                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 844                               m2CountThrLow);
 845
 846                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 847                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
 848                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 849                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
 850                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 851                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
 852                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 853                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
 854
 855                 if (on)
 856                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 857                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 858                 else
 859                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 860                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 861
 862                 if (!on != aniState->ofdmWeakSigDetectOff) {
 863                         ath_dbg(common, ATH_DBG_ANI,
 864                                 "** ch %d: ofdm weak signal: %s=>%s\n",
 865                                 chan->channel,
 866                                 !aniState->ofdmWeakSigDetectOff ?
 867                                 "on" : "off",
 868                                 on ? "on" : "off");
 869                         if (on)
 870                                 ah->stats.ast_ani_ofdmon++;
 871                         else
 872                                 ah->stats.ast_ani_ofdmoff++;
 873                         aniState->ofdmWeakSigDetectOff = !on;
 874                 }
 875                 break;
 876         }
 877         case ATH9K_ANI_FIRSTEP_LEVEL:{
 878                 u32 level = param;
 879
 880                 if (level >= ARRAY_SIZE(firstep_table)) {
 881                         ath_dbg(common, ATH_DBG_ANI,
 882                                 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
 883                                 level, ARRAY_SIZE(firstep_table));
 884                         return false;
 885                 }
 886
 887                 /*
 888                  * make register setting relative to default
 889                  * from INI file & cap value
 890                  */
 891                 value = firstep_table[level] -
 892                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 893                         aniState->iniDef.firstep;
 894                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 895                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 896                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 897                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 898                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 899                               AR_PHY_FIND_SIG_FIRSTEP,
 900                               value);
 901                 /*
 902                  * we need to set first step low register too
 903                  * make register setting relative to default
 904                  * from INI file & cap value
 905                  */
 906                 value2 = firstep_table[level] -
 907                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
 908                          aniState->iniDef.firstepLow;
 909                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
 910                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
 911                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
 912                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
 913
 914                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
 915                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 916
 917                 if (level != aniState->firstepLevel) {
 918                         ath_dbg(common, ATH_DBG_ANI,
 919                                 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
 920                                 chan->channel,
 921                                 aniState->firstepLevel,
 922                                 level,
 923                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
 924                                 value,
 925                                 aniState->iniDef.firstep);
 926                         ath_dbg(common, ATH_DBG_ANI,
 927                                 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
 928                                 chan->channel,
 929                                 aniState->firstepLevel,
 930                                 level,
 931                                 ATH9K_ANI_FIRSTEP_LVL_NEW,
 932                                 value2,
 933                                 aniState->iniDef.firstepLow);
 934                         if (level > aniState->firstepLevel)
 935                                 ah->stats.ast_ani_stepup++;
 936                         else if (level < aniState->firstepLevel)
 937                                 ah->stats.ast_ani_stepdown++;
 938                         aniState->firstepLevel = level;
 939                 }
 940                 break;
 941         }
 942         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 943                 u32 level = param;
 944
 945                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
 946                         ath_dbg(common, ATH_DBG_ANI,
 947                                 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
 948                                 level, ARRAY_SIZE(cycpwrThr1_table));
 949                         return false;
 950                 }
 951                 /*
 952                  * make register setting relative to default
 953                  * from INI file & cap value
 954                  */
 955                 value = cycpwrThr1_table[level] -
 956                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 957                         aniState->iniDef.cycpwrThr1;
 958                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 959                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 960                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 961                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 962                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
 963                               AR_PHY_TIMING5_CYCPWR_THR1,
 964                               value);
 965
 966                 /*
 967                  * set AR_PHY_EXT_CCA for extension channel
 968                  * make register setting relative to default
 969                  * from INI file & cap value
 970                  */
 971                 value2 = cycpwrThr1_table[level] -
 972                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
 973                          aniState->iniDef.cycpwrThr1Ext;
 974                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
 975                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
 976                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
 977                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
 978                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 979                               AR_PHY_EXT_CYCPWR_THR1, value2);
 980
 981                 if (level != aniState->spurImmunityLevel) {
 982                         ath_dbg(common, ATH_DBG_ANI,
 983                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
 984                                 chan->channel,
 985                                 aniState->spurImmunityLevel,
 986                                 level,
 987                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
 988                                 value,
 989                                 aniState->iniDef.cycpwrThr1);
 990                         ath_dbg(common, ATH_DBG_ANI,
 991                                 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
 992                                 chan->channel,
 993                                 aniState->spurImmunityLevel,
 994                                 level,
 995                                 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
 996                                 value2,
 997                                 aniState->iniDef.cycpwrThr1Ext);
 998                         if (level > aniState->spurImmunityLevel)
 999                                 ah->stats.ast_ani_spurup++;
1000                         else if (level < aniState->spurImmunityLevel)
1001                                 ah->stats.ast_ani_spurdown++;
1002                         aniState->spurImmunityLevel = level;
1003                 }
1004                 break;
1005         }
1006         case ATH9K_ANI_MRC_CCK:{
1007                 /*
1008                  * is_on == 1 means MRC CCK ON (default, less noise imm)
1009                  * is_on == 0 means MRC CCK is OFF (more noise imm)
1010                  */
1011                 bool is_on = param ? 1 : 0;
1012                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1013                               AR_PHY_MRC_CCK_ENABLE, is_on);
1014                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1015                               AR_PHY_MRC_CCK_MUX_REG, is_on);
1016                 if (!is_on != aniState->mrcCCKOff) {
1017                         ath_dbg(common, ATH_DBG_ANI,
1018                                 "** ch %d: MRC CCK: %s=>%s\n",
1019                                 chan->channel,
1020                                 !aniState->mrcCCKOff ? "on" : "off",
1021                                 is_on ? "on" : "off");
1022                 if (is_on)
1023                         ah->stats.ast_ani_ccklow++;
1024                 else
1025                         ah->stats.ast_ani_cckhigh++;
1026                 aniState->mrcCCKOff = !is_on;
1027                 }
1028         break;
1029         }
1030         case ATH9K_ANI_PRESENT:
1031                 break;
1032         default:
1033                 ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
1034                 return false;
1035         }
1036
1037         ath_dbg(common, ATH_DBG_ANI,
1038                 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1039                 aniState->spurImmunityLevel,
1040                 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1041                 aniState->firstepLevel,
1042                 !aniState->mrcCCKOff ? "on" : "off",
1043                 aniState->listenTime,
1044                 aniState->ofdmPhyErrCount,
1045                 aniState->cckPhyErrCount);
1046         return true;
1047 }
1048
1049 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1050                               int16_t nfarray[NUM_NF_READINGS])
1051 {
1052 #define AR_PHY_CH_MINCCA_PWR    0x1FF00000
1053 #define AR_PHY_CH_MINCCA_PWR_S  20
1054 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1055 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1056
1057         int16_t nf;
1058         int i;
1059
1060         for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1061                 if (ah->rxchainmask & BIT(i)) {
1062                         nf = MS(REG_READ(ah, ah->nf_regs[i]),
1063                                          AR_PHY_CH_MINCCA_PWR);
1064                         nfarray[i] = sign_extend32(nf, 8);
1065
1066                         if (IS_CHAN_HT40(ah->curchan)) {
1067                                 u8 ext_idx = AR9300_MAX_CHAINS + i;
1068
1069                                 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1070                                                  AR_PHY_CH_EXT_MINCCA_PWR);
1071                                 nfarray[ext_idx] = sign_extend32(nf, 8);
1072                         }
1073                 }
1074         }
1075 }
1076
1077 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1078 {
1079         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1080         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1081         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1082         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1083         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1084         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1085 }
1086
1087 /*
1088  * Initialize the ANI register values with default (ini) values.
1089  * This routine is called during a (full) hardware reset after
1090  * all the registers are initialised from the INI.
1091  */
1092 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1093 {
1094         struct ar5416AniState *aniState;
1095         struct ath_common *common = ath9k_hw_common(ah);
1096         struct ath9k_channel *chan = ah->curchan;
1097         struct ath9k_ani_default *iniDef;
1098         u32 val;
1099
1100         aniState = &ah->curchan->ani;
1101         iniDef = &aniState->iniDef;
1102
1103         ath_dbg(common, ATH_DBG_ANI,
1104                 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1105                 ah->hw_version.macVersion,
1106                 ah->hw_version.macRev,
1107                 ah->opmode,
1108                 chan->channel,
1109                 chan->channelFlags);
1110
1111         val = REG_READ(ah, AR_PHY_SFCORR);
1112         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1113         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1114         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1115
1116         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1117         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1118         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1119         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1120
1121         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1122         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1123         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1124         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1125         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1126         iniDef->firstep = REG_READ_FIELD(ah,
1127                                          AR_PHY_FIND_SIG,
1128                                          AR_PHY_FIND_SIG_FIRSTEP);
1129         iniDef->firstepLow = REG_READ_FIELD(ah,
1130                                             AR_PHY_FIND_SIG_LOW,
1131                                             AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1132         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1133                                             AR_PHY_TIMING5,
1134                                             AR_PHY_TIMING5_CYCPWR_THR1);
1135         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1136                                                AR_PHY_EXT_CCA,
1137                                                AR_PHY_EXT_CYCPWR_THR1);
1138
1139         /* these levels just got reset to defaults by the INI */
1140         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1141         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1142         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1143         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1144 }
1145
1146 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1147                                        struct ath_hw_radar_conf *conf)
1148 {
1149         u32 radar_0 = 0, radar_1 = 0;
1150
1151         if (!conf) {
1152                 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1153                 return;
1154         }
1155
1156         radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1157         radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1158         radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1159         radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1160         radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1161         radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1162
1163         radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1164         radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1165         radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1166         radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1167         radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1168
1169         REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1170         REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1171         if (conf->ext_channel)
1172                 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1173         else
1174                 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1175 }
1176
1177 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1178 {
1179         struct ath_hw_radar_conf *conf = &ah->radar_conf;
1180
1181         conf->fir_power = -28;
1182         conf->radar_rssi = 0;
1183         conf->pulse_height = 10;
1184         conf->pulse_rssi = 24;
1185         conf->pulse_inband = 8;
1186         conf->pulse_maxlen = 255;
1187         conf->pulse_inband_step = 12;
1188         conf->radar_inband = 8;
1189 }
1190
1191 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1192 {
1193         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1194         static const u32 ar9300_cca_regs[6] = {
1195                 AR_PHY_CCA_0,
1196                 AR_PHY_CCA_1,
1197                 AR_PHY_CCA_2,
1198                 AR_PHY_EXT_CCA,
1199                 AR_PHY_EXT_CCA_1,
1200                 AR_PHY_EXT_CCA_2,
1201         };
1202
1203         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1204         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1205         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1206         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1207         priv_ops->init_bb = ar9003_hw_init_bb;
1208         priv_ops->process_ini = ar9003_hw_process_ini;
1209         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1210         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1211         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1212         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1213         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1214         priv_ops->set_diversity = ar9003_hw_set_diversity;
1215         priv_ops->ani_control = ar9003_hw_ani_control;
1216         priv_ops->do_getnf = ar9003_hw_do_getnf;
1217         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1218         priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1219
1220         ar9003_hw_set_nf_limits(ah);
1221         ar9003_hw_set_radar_conf(ah);
1222         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1223 }
1224
1225 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1226 {
1227         struct ath_common *common = ath9k_hw_common(ah);
1228         u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1229         u32 val, idle_count;
1230
1231         if (!idle_tmo_ms) {
1232                 /* disable IRQ, disable chip-reset for BB panic */
1233                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1234                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1235                           ~(AR_PHY_WATCHDOG_RST_ENABLE |
1236                             AR_PHY_WATCHDOG_IRQ_ENABLE));
1237
1238                 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1239                 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1240                           REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1241                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1242                             AR_PHY_WATCHDOG_IDLE_ENABLE));
1243
1244                 ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1245                 return;
1246         }
1247
1248         /* enable IRQ, disable chip-reset for BB watchdog */
1249         val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1250         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1251                   (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1252                   ~AR_PHY_WATCHDOG_RST_ENABLE);
1253
1254         /* bound limit to 10 secs */
1255         if (idle_tmo_ms > 10000)
1256                 idle_tmo_ms = 10000;
1257
1258         /*
1259          * The time unit for watchdog event is 2^15 44/88MHz cycles.
1260          *
1261          * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1262          * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1263          *
1264          * Given we use fast clock now in 5 GHz, these time units should
1265          * be common for both 2 GHz and 5 GHz.
1266          */
1267         idle_count = (100 * idle_tmo_ms) / 74;
1268         if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1269                 idle_count = (100 * idle_tmo_ms) / 37;
1270
1271         /*
1272          * enable watchdog in non-IDLE mode, disable in IDLE mode,
1273          * set idle time-out.
1274          */
1275         REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1276                   AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1277                   AR_PHY_WATCHDOG_IDLE_MASK |
1278                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1279
1280         ath_dbg(common, ATH_DBG_RESET,
1281                 "Enabled BB Watchdog timeout (%u ms)\n",
1282                 idle_tmo_ms);
1283 }
1284
1285 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1286 {
1287         /*
1288          * we want to avoid printing in ISR context so we save the
1289          * watchdog status to be printed later in bottom half context.
1290          */
1291         ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1292
1293         /*
1294          * the watchdog timer should reset on status read but to be sure
1295          * sure we write 0 to the watchdog status bit.
1296          */
1297         REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1298                   ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1299 }
1300
1301 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1302 {
1303         struct ath_common *common = ath9k_hw_common(ah);
1304         u32 status;
1305
1306         if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1307                 return;
1308
1309         status = ah->bb_watchdog_last_status;
1310         ath_dbg(common, ATH_DBG_RESET,
1311                 "\n==== BB update: BB status=0x%08x ====\n", status);
1312         ath_dbg(common, ATH_DBG_RESET,
1313                 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1314                 MS(status, AR_PHY_WATCHDOG_INFO),
1315                 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1316                 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1317                 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1318                 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1319                 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1320                 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1321                 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1322                 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1323
1324         ath_dbg(common, ATH_DBG_RESET,
1325                 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1326                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1327                 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1328         ath_dbg(common, ATH_DBG_RESET,
1329                 "** BB mode: BB_gen_controls=0x%08x **\n",
1330                 REG_READ(ah, AR_PHY_GEN_CTRL));
1331
1332 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1333         if (common->cc_survey.cycles)
1334                 ath_dbg(common, ATH_DBG_RESET,
1335                         "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1336                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
1337
1338         ath_dbg(common, ATH_DBG_RESET,
1339                 "==== BB update: done ====\n\n");
1340 }
1341 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);