2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/kernel.h>
21 struct ani_ofdm_level_entry {
22 int spur_immunity_level;
24 int ofdm_weak_signal_on;
27 /* values here are relative to the INI */
34 * WS: OFDM / CCK Weak Signal detection
35 * MRC-CCK: Maximal Ratio Combining for CCK
38 static const struct ani_ofdm_level_entry ofdm_level_table[] = {
40 { 0, 0, 1 }, /* lvl 0 */
41 { 1, 1, 1 }, /* lvl 1 */
42 { 2, 2, 1 }, /* lvl 2 */
43 { 3, 2, 1 }, /* lvl 3 (default) */
44 { 4, 3, 1 }, /* lvl 4 */
45 { 5, 4, 1 }, /* lvl 5 */
46 { 6, 5, 1 }, /* lvl 6 */
47 { 7, 6, 1 }, /* lvl 7 */
48 { 7, 7, 1 }, /* lvl 8 */
49 { 7, 8, 0 } /* lvl 9 */
51 #define ATH9K_ANI_OFDM_NUM_LEVEL \
52 ARRAY_SIZE(ofdm_level_table)
53 #define ATH9K_ANI_OFDM_MAX_LEVEL \
54 (ATH9K_ANI_OFDM_NUM_LEVEL-1)
55 #define ATH9K_ANI_OFDM_DEF_LEVEL \
56 3 /* default level - matches the INI settings */
59 * MRC (Maximal Ratio Combining) has always been used with multi-antenna ofdm.
60 * With OFDM for single stream you just add up all antenna inputs, you're
61 * only interested in what you get after FFT. Signal aligment is also not
62 * required for OFDM because any phase difference adds up in the frequency
65 * MRC requires extra work for use with CCK. You need to align the antenna
66 * signals from the different antenna before you can add the signals together.
67 * You need aligment of signals as CCK is in time domain, so addition can cancel
68 * your signal completely if phase is 180 degrees (think of adding sine waves).
69 * You also need to remove noise before the addition and this is where ANI
70 * MRC CCK comes into play. One of the antenna inputs may be stronger but
71 * lower SNR, so just adding after alignment can be dangerous.
73 * Regardless of alignment in time, the antenna signals add constructively after
74 * FFT and improve your reception. For more information:
76 * http://en.wikipedia.org/wiki/Maximal-ratio_combining
79 struct ani_cck_level_entry {
84 static const struct ani_cck_level_entry cck_level_table[] = {
88 { 2, 1 }, /* lvl 2 (default) */
93 { 7, 0 }, /* lvl 7 (only for high rssi) */
94 { 8, 0 } /* lvl 8 (only for high rssi) */
97 #define ATH9K_ANI_CCK_NUM_LEVEL \
98 ARRAY_SIZE(cck_level_table)
99 #define ATH9K_ANI_CCK_MAX_LEVEL \
100 (ATH9K_ANI_CCK_NUM_LEVEL-1)
101 #define ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI \
102 (ATH9K_ANI_CCK_NUM_LEVEL-3)
103 #define ATH9K_ANI_CCK_DEF_LEVEL \
104 2 /* default level - matches the INI settings */
106 /* Private to ani.c */
107 static void ath9k_hw_ani_lower_immunity(struct ath_hw *ah)
109 ath9k_hw_private_ops(ah)->ani_lower_immunity(ah);
112 static bool use_new_ani(struct ath_hw *ah)
114 return AR_SREV_9300_20_OR_LATER(ah) || modparam_force_new_ani;
117 static void ath9k_hw_update_mibstats(struct ath_hw *ah,
118 struct ath9k_mib_stats *stats)
120 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
121 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
122 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
123 stats->rts_good += REG_READ(ah, AR_RTS_OK);
124 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
127 static void ath9k_ani_restart(struct ath_hw *ah)
129 struct ar5416AniState *aniState;
130 struct ath_common *common = ath9k_hw_common(ah);
131 u32 ofdm_base = 0, cck_base = 0;
136 aniState = &ah->curchan->ani;
137 aniState->listenTime = 0;
139 if (!use_new_ani(ah)) {
140 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
141 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
144 ath_print(common, ATH_DBG_ANI,
145 "Writing ofdmbase=%u cckbase=%u\n", ofdm_base, cck_base);
147 ENABLE_REGWRITE_BUFFER(ah);
149 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
150 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
151 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
152 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
154 REGWRITE_BUFFER_FLUSH(ah);
156 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
158 aniState->ofdmPhyErrCount = 0;
159 aniState->cckPhyErrCount = 0;
162 static void ath9k_hw_ani_ofdm_err_trigger_old(struct ath_hw *ah)
164 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
165 struct ar5416AniState *aniState;
171 aniState = &ah->curchan->ani;
173 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
174 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
175 aniState->noiseImmunityLevel + 1)) {
180 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
181 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
182 aniState->spurImmunityLevel + 1)) {
187 if (ah->opmode == NL80211_IFTYPE_AP) {
188 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
189 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
190 aniState->firstepLevel + 1);
194 rssi = BEACON_RSSI(ah);
195 if (rssi > aniState->rssiThrHigh) {
196 if (!aniState->ofdmWeakSigDetectOff) {
197 if (ath9k_hw_ani_control(ah,
198 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
200 ath9k_hw_ani_control(ah,
201 ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
205 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
206 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
207 aniState->firstepLevel + 1);
210 } else if (rssi > aniState->rssiThrLow) {
211 if (aniState->ofdmWeakSigDetectOff)
212 ath9k_hw_ani_control(ah,
213 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
215 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
216 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
217 aniState->firstepLevel + 1);
220 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
222 if (!aniState->ofdmWeakSigDetectOff)
223 ath9k_hw_ani_control(ah,
224 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
226 if (aniState->firstepLevel > 0)
227 ath9k_hw_ani_control(ah,
228 ATH9K_ANI_FIRSTEP_LEVEL, 0);
234 static void ath9k_hw_ani_cck_err_trigger_old(struct ath_hw *ah)
236 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
237 struct ar5416AniState *aniState;
243 aniState = &ah->curchan->ani;
244 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
245 if (ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
246 aniState->noiseImmunityLevel + 1)) {
250 if (ah->opmode == NL80211_IFTYPE_AP) {
251 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
252 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
253 aniState->firstepLevel + 1);
257 rssi = BEACON_RSSI(ah);
258 if (rssi > aniState->rssiThrLow) {
259 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
260 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
261 aniState->firstepLevel + 1);
263 if ((conf->channel->band == IEEE80211_BAND_2GHZ) &&
265 if (aniState->firstepLevel > 0)
266 ath9k_hw_ani_control(ah,
267 ATH9K_ANI_FIRSTEP_LEVEL, 0);
272 /* Adjust the OFDM Noise Immunity Level */
273 static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
275 struct ar5416AniState *aniState = &ah->curchan->ani;
276 struct ath_common *common = ath9k_hw_common(ah);
277 const struct ani_ofdm_level_entry *entry_ofdm;
278 const struct ani_cck_level_entry *entry_cck;
280 aniState->noiseFloor = BEACON_RSSI(ah);
282 ath_print(common, ATH_DBG_ANI,
283 "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
284 aniState->ofdmNoiseImmunityLevel,
285 immunityLevel, aniState->noiseFloor,
286 aniState->rssiThrLow, aniState->rssiThrHigh);
288 aniState->ofdmNoiseImmunityLevel = immunityLevel;
290 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
291 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
293 if (aniState->spurImmunityLevel != entry_ofdm->spur_immunity_level)
294 ath9k_hw_ani_control(ah,
295 ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
296 entry_ofdm->spur_immunity_level);
298 if (aniState->firstepLevel != entry_ofdm->fir_step_level &&
299 entry_ofdm->fir_step_level >= entry_cck->fir_step_level)
300 ath9k_hw_ani_control(ah,
301 ATH9K_ANI_FIRSTEP_LEVEL,
302 entry_ofdm->fir_step_level);
304 if ((ah->opmode != NL80211_IFTYPE_STATION &&
305 ah->opmode != NL80211_IFTYPE_ADHOC) ||
306 aniState->noiseFloor <= aniState->rssiThrHigh) {
307 if (aniState->ofdmWeakSigDetectOff)
308 /* force on ofdm weak sig detect */
309 ath9k_hw_ani_control(ah,
310 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
312 else if (aniState->ofdmWeakSigDetectOff ==
313 entry_ofdm->ofdm_weak_signal_on)
314 ath9k_hw_ani_control(ah,
315 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
316 entry_ofdm->ofdm_weak_signal_on);
320 static void ath9k_hw_ani_ofdm_err_trigger_new(struct ath_hw *ah)
322 struct ar5416AniState *aniState;
327 aniState = &ah->curchan->ani;
329 if (aniState->ofdmNoiseImmunityLevel < ATH9K_ANI_OFDM_MAX_LEVEL)
330 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel + 1);
334 * Set the ANI settings to match an CCK level.
336 static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
338 struct ar5416AniState *aniState = &ah->curchan->ani;
339 struct ath_common *common = ath9k_hw_common(ah);
340 const struct ani_ofdm_level_entry *entry_ofdm;
341 const struct ani_cck_level_entry *entry_cck;
343 aniState->noiseFloor = BEACON_RSSI(ah);
344 ath_print(common, ATH_DBG_ANI,
345 "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
346 aniState->cckNoiseImmunityLevel, immunityLevel,
347 aniState->noiseFloor, aniState->rssiThrLow,
348 aniState->rssiThrHigh);
350 if ((ah->opmode == NL80211_IFTYPE_STATION ||
351 ah->opmode == NL80211_IFTYPE_ADHOC) &&
352 aniState->noiseFloor <= aniState->rssiThrLow &&
353 immunityLevel > ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI)
354 immunityLevel = ATH9K_ANI_CCK_MAX_LEVEL_LOW_RSSI;
356 aniState->cckNoiseImmunityLevel = immunityLevel;
358 entry_ofdm = &ofdm_level_table[aniState->ofdmNoiseImmunityLevel];
359 entry_cck = &cck_level_table[aniState->cckNoiseImmunityLevel];
361 if (aniState->firstepLevel != entry_cck->fir_step_level &&
362 entry_cck->fir_step_level >= entry_ofdm->fir_step_level)
363 ath9k_hw_ani_control(ah,
364 ATH9K_ANI_FIRSTEP_LEVEL,
365 entry_cck->fir_step_level);
367 /* Skip MRC CCK for pre AR9003 families */
368 if (!AR_SREV_9300_20_OR_LATER(ah))
371 if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
372 ath9k_hw_ani_control(ah,
374 entry_cck->mrc_cck_on);
377 static void ath9k_hw_ani_cck_err_trigger_new(struct ath_hw *ah)
379 struct ar5416AniState *aniState;
384 aniState = &ah->curchan->ani;
386 if (aniState->cckNoiseImmunityLevel < ATH9K_ANI_CCK_MAX_LEVEL)
387 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel + 1);
390 static void ath9k_hw_ani_lower_immunity_old(struct ath_hw *ah)
392 struct ar5416AniState *aniState;
395 aniState = &ah->curchan->ani;
397 if (ah->opmode == NL80211_IFTYPE_AP) {
398 if (aniState->firstepLevel > 0) {
399 if (ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
400 aniState->firstepLevel - 1))
404 rssi = BEACON_RSSI(ah);
405 if (rssi > aniState->rssiThrHigh) {
407 } else if (rssi > aniState->rssiThrLow) {
408 if (aniState->ofdmWeakSigDetectOff) {
409 if (ath9k_hw_ani_control(ah,
410 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
414 if (aniState->firstepLevel > 0) {
415 if (ath9k_hw_ani_control(ah,
416 ATH9K_ANI_FIRSTEP_LEVEL,
417 aniState->firstepLevel - 1) == true)
421 if (aniState->firstepLevel > 0) {
422 if (ath9k_hw_ani_control(ah,
423 ATH9K_ANI_FIRSTEP_LEVEL,
424 aniState->firstepLevel - 1) == true)
430 if (aniState->spurImmunityLevel > 0) {
431 if (ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
432 aniState->spurImmunityLevel - 1))
436 if (aniState->noiseImmunityLevel > 0) {
437 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
438 aniState->noiseImmunityLevel - 1);
444 * only lower either OFDM or CCK errors per turn
445 * we lower the other one next time
447 static void ath9k_hw_ani_lower_immunity_new(struct ath_hw *ah)
449 struct ar5416AniState *aniState;
451 aniState = &ah->curchan->ani;
453 /* lower OFDM noise immunity */
454 if (aniState->ofdmNoiseImmunityLevel > 0 &&
455 (aniState->ofdmsTurn || aniState->cckNoiseImmunityLevel == 0)) {
456 ath9k_hw_set_ofdm_nil(ah, aniState->ofdmNoiseImmunityLevel - 1);
460 /* lower CCK noise immunity */
461 if (aniState->cckNoiseImmunityLevel > 0)
462 ath9k_hw_set_cck_nil(ah, aniState->cckNoiseImmunityLevel - 1);
465 static u8 ath9k_hw_chan_2_clockrate_mhz(struct ath_hw *ah)
467 struct ath9k_channel *chan = ah->curchan;
468 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
469 u8 clockrate; /* in MHz */
471 if (!ah->curchan) /* should really check for CCK instead */
472 clockrate = ATH9K_CLOCK_RATE_CCK;
473 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
474 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
475 else if (IS_CHAN_A_FAST_CLOCK(ah, chan))
476 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
478 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
480 if (conf_is_ht40(conf))
481 return clockrate * 2;
486 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hw *ah)
491 ath9k_hw_update_cycle_counters(ah);
492 clock_rate = ath9k_hw_chan_2_clockrate_mhz(ah) * 1000;
493 listen_time = ah->listen_time / clock_rate;
499 static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
501 struct ar5416AniState *aniState;
502 struct ath9k_channel *chan = ah->curchan;
503 struct ath_common *common = ath9k_hw_common(ah);
508 aniState = &ah->curchan->ani;
510 if (ah->opmode != NL80211_IFTYPE_STATION
511 && ah->opmode != NL80211_IFTYPE_ADHOC) {
512 ath_print(common, ATH_DBG_ANI,
513 "Reset ANI state opmode %u\n", ah->opmode);
514 ah->stats.ast_ani_reset++;
516 if (ah->opmode == NL80211_IFTYPE_AP) {
518 * ath9k_hw_ani_control() will only process items set on
521 if (IS_CHAN_2GHZ(chan))
522 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
523 ATH9K_ANI_FIRSTEP_LEVEL);
525 ah->ani_function = 0;
528 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL, 0);
529 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL, 0);
530 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL, 0);
531 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
532 !ATH9K_ANI_USE_OFDM_WEAK_SIG);
533 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
534 ATH9K_ANI_CCK_WEAK_SIG_THR);
536 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) |
537 ATH9K_RX_FILTER_PHYERR);
539 ath9k_ani_restart(ah);
543 if (aniState->noiseImmunityLevel != 0)
544 ath9k_hw_ani_control(ah, ATH9K_ANI_NOISE_IMMUNITY_LEVEL,
545 aniState->noiseImmunityLevel);
546 if (aniState->spurImmunityLevel != 0)
547 ath9k_hw_ani_control(ah, ATH9K_ANI_SPUR_IMMUNITY_LEVEL,
548 aniState->spurImmunityLevel);
549 if (aniState->ofdmWeakSigDetectOff)
550 ath9k_hw_ani_control(ah, ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION,
551 !aniState->ofdmWeakSigDetectOff);
552 if (aniState->cckWeakSigThreshold)
553 ath9k_hw_ani_control(ah, ATH9K_ANI_CCK_WEAK_SIGNAL_THR,
554 aniState->cckWeakSigThreshold);
555 if (aniState->firstepLevel != 0)
556 ath9k_hw_ani_control(ah, ATH9K_ANI_FIRSTEP_LEVEL,
557 aniState->firstepLevel);
559 ath9k_hw_setrxfilter(ah, ath9k_hw_getrxfilter(ah) &
560 ~ATH9K_RX_FILTER_PHYERR);
561 ath9k_ani_restart(ah);
563 ENABLE_REGWRITE_BUFFER(ah);
565 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
566 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
568 REGWRITE_BUFFER_FLUSH(ah);
572 * Restore the ANI parameters in the HAL and reset the statistics.
573 * This routine should be called for every hardware reset and for
574 * every channel change.
576 static void ath9k_ani_reset_new(struct ath_hw *ah, bool is_scanning)
578 struct ar5416AniState *aniState = &ah->curchan->ani;
579 struct ath9k_channel *chan = ah->curchan;
580 struct ath_common *common = ath9k_hw_common(ah);
585 BUG_ON(aniState == NULL);
586 ah->stats.ast_ani_reset++;
588 /* only allow a subset of functions in AP mode */
589 if (ah->opmode == NL80211_IFTYPE_AP) {
590 if (IS_CHAN_2GHZ(chan)) {
591 ah->ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
592 ATH9K_ANI_FIRSTEP_LEVEL);
593 if (AR_SREV_9300_20_OR_LATER(ah))
594 ah->ani_function |= ATH9K_ANI_MRC_CCK;
596 ah->ani_function = 0;
599 /* always allow mode (on/off) to be controlled */
600 ah->ani_function |= ATH9K_ANI_MODE;
603 (ah->opmode != NL80211_IFTYPE_STATION &&
604 ah->opmode != NL80211_IFTYPE_ADHOC)) {
606 * If we're scanning or in AP mode, the defaults (ini)
607 * should be in place. For an AP we assume the historical
608 * levels for this channel are probably outdated so start
609 * from defaults instead.
611 if (aniState->ofdmNoiseImmunityLevel !=
612 ATH9K_ANI_OFDM_DEF_LEVEL ||
613 aniState->cckNoiseImmunityLevel !=
614 ATH9K_ANI_CCK_DEF_LEVEL) {
615 ath_print(common, ATH_DBG_ANI,
616 "Restore defaults: opmode %u "
617 "chan %d Mhz/0x%x is_scanning=%d "
623 aniState->ofdmNoiseImmunityLevel,
624 aniState->cckNoiseImmunityLevel);
626 ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
627 ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
631 * restore historical levels for this channel
633 ath_print(common, ATH_DBG_ANI,
634 "Restore history: opmode %u "
635 "chan %d Mhz/0x%x is_scanning=%d "
641 aniState->ofdmNoiseImmunityLevel,
642 aniState->cckNoiseImmunityLevel);
644 ath9k_hw_set_ofdm_nil(ah,
645 aniState->ofdmNoiseImmunityLevel);
646 ath9k_hw_set_cck_nil(ah,
647 aniState->cckNoiseImmunityLevel);
651 * enable phy counters if hw supports or if not, enable phy
652 * interrupts (so we can count each one)
654 ath9k_ani_restart(ah);
656 ENABLE_REGWRITE_BUFFER(ah);
658 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
659 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
661 REGWRITE_BUFFER_FLUSH(ah);
664 static void ath9k_hw_ani_read_counters(struct ath_hw *ah)
666 struct ath_common *common = ath9k_hw_common(ah);
667 struct ar5416AniState *aniState = &ah->curchan->ani;
670 u32 ofdmPhyErrCnt, cckPhyErrCnt;
671 u32 phyCnt1, phyCnt2;
674 listenTime = ath9k_hw_ani_get_listen_time(ah);
675 if (listenTime < 0) {
676 ah->stats.ast_ani_lneg++;
677 ath9k_ani_restart(ah);
681 if (!use_new_ani(ah)) {
682 ofdm_base = AR_PHY_COUNTMAX - ah->config.ofdm_trig_high;
683 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
686 aniState->listenTime += listenTime;
688 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
690 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
691 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
693 if (use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
694 if (phyCnt1 < ofdm_base) {
695 ath_print(common, ATH_DBG_ANI,
696 "phyCnt1 0x%x, resetting "
697 "counter value to 0x%x\n",
699 REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
700 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
701 AR_PHY_ERR_OFDM_TIMING);
703 if (phyCnt2 < cck_base) {
704 ath_print(common, ATH_DBG_ANI,
705 "phyCnt2 0x%x, resetting "
706 "counter value to 0x%x\n",
708 REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
709 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
710 AR_PHY_ERR_CCK_TIMING);
715 ofdmPhyErrCnt = phyCnt1 - ofdm_base;
716 ah->stats.ast_ani_ofdmerrs +=
717 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
718 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
720 cckPhyErrCnt = phyCnt2 - cck_base;
721 ah->stats.ast_ani_cckerrs +=
722 cckPhyErrCnt - aniState->cckPhyErrCount;
723 aniState->cckPhyErrCount = cckPhyErrCnt;
727 static void ath9k_hw_ani_monitor_old(struct ath_hw *ah,
728 struct ath9k_channel *chan)
730 struct ar5416AniState *aniState;
735 aniState = &ah->curchan->ani;
736 ath9k_hw_ani_read_counters(ah);
738 if (aniState->listenTime > 5 * ah->aniperiod) {
739 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
740 ah->config.ofdm_trig_low / 1000 &&
741 aniState->cckPhyErrCount <= aniState->listenTime *
742 ah->config.cck_trig_low / 1000)
743 ath9k_hw_ani_lower_immunity(ah);
744 ath9k_ani_restart(ah);
745 } else if (aniState->listenTime > ah->aniperiod) {
746 if (aniState->ofdmPhyErrCount > aniState->listenTime *
747 ah->config.ofdm_trig_high / 1000) {
748 ath9k_hw_ani_ofdm_err_trigger_old(ah);
749 ath9k_ani_restart(ah);
750 } else if (aniState->cckPhyErrCount >
751 aniState->listenTime * ah->config.cck_trig_high /
753 ath9k_hw_ani_cck_err_trigger_old(ah);
754 ath9k_ani_restart(ah);
759 static void ath9k_hw_ani_monitor_new(struct ath_hw *ah,
760 struct ath9k_channel *chan)
762 struct ar5416AniState *aniState;
763 struct ath_common *common = ath9k_hw_common(ah);
764 u32 ofdmPhyErrRate, cckPhyErrRate;
769 aniState = &ah->curchan->ani;
770 if (WARN_ON(!aniState))
773 ath9k_hw_ani_read_counters(ah);
775 ofdmPhyErrRate = aniState->ofdmPhyErrCount * 1000 /
776 aniState->listenTime;
777 cckPhyErrRate = aniState->cckPhyErrCount * 1000 /
778 aniState->listenTime;
780 ath_print(common, ATH_DBG_ANI,
781 "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
782 "errs=%d/s ofdm_turn=%d\n",
783 aniState->listenTime,
784 aniState->ofdmNoiseImmunityLevel,
785 ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
786 cckPhyErrRate, aniState->ofdmsTurn);
788 if (aniState->listenTime > 5 * ah->aniperiod) {
789 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
790 cckPhyErrRate <= ah->config.cck_trig_low) {
791 ath_print(common, ATH_DBG_ANI,
792 "1. listenTime=%d OFDM:%d errs=%d/s(<%d) "
793 "CCK:%d errs=%d/s(<%d) -> "
794 "ath9k_hw_ani_lower_immunity()\n",
795 aniState->listenTime,
796 aniState->ofdmNoiseImmunityLevel,
798 ah->config.ofdm_trig_low,
799 aniState->cckNoiseImmunityLevel,
801 ah->config.cck_trig_low);
802 ath9k_hw_ani_lower_immunity(ah);
803 aniState->ofdmsTurn = !aniState->ofdmsTurn;
805 ath_print(common, ATH_DBG_ANI,
806 "1 listenTime=%d ofdm=%d/s cck=%d/s - "
807 "calling ath9k_ani_restart()\n",
808 aniState->listenTime, ofdmPhyErrRate, cckPhyErrRate);
809 ath9k_ani_restart(ah);
810 } else if (aniState->listenTime > ah->aniperiod) {
811 /* check to see if need to raise immunity */
812 if (ofdmPhyErrRate > ah->config.ofdm_trig_high &&
813 (cckPhyErrRate <= ah->config.cck_trig_high ||
814 aniState->ofdmsTurn)) {
815 ath_print(common, ATH_DBG_ANI,
816 "2 listenTime=%d OFDM:%d errs=%d/s(>%d) -> "
817 "ath9k_hw_ani_ofdm_err_trigger_new()\n",
818 aniState->listenTime,
819 aniState->ofdmNoiseImmunityLevel,
821 ah->config.ofdm_trig_high);
822 ath9k_hw_ani_ofdm_err_trigger_new(ah);
823 ath9k_ani_restart(ah);
824 aniState->ofdmsTurn = false;
825 } else if (cckPhyErrRate > ah->config.cck_trig_high) {
826 ath_print(common, ATH_DBG_ANI,
827 "3 listenTime=%d CCK:%d errs=%d/s(>%d) -> "
828 "ath9k_hw_ani_cck_err_trigger_new()\n",
829 aniState->listenTime,
830 aniState->cckNoiseImmunityLevel,
832 ah->config.cck_trig_high);
833 ath9k_hw_ani_cck_err_trigger_new(ah);
834 ath9k_ani_restart(ah);
835 aniState->ofdmsTurn = true;
840 void ath9k_enable_mib_counters(struct ath_hw *ah)
842 struct ath_common *common = ath9k_hw_common(ah);
844 ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
846 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
848 ENABLE_REGWRITE_BUFFER(ah);
850 REG_WRITE(ah, AR_FILT_OFDM, 0);
851 REG_WRITE(ah, AR_FILT_CCK, 0);
852 REG_WRITE(ah, AR_MIBC,
853 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
855 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
856 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
858 REGWRITE_BUFFER_FLUSH(ah);
861 /* Freeze the MIB counters, get the stats and then clear them */
862 void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
864 struct ath_common *common = ath9k_hw_common(ah);
866 ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
868 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
869 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
870 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
871 REG_WRITE(ah, AR_FILT_OFDM, 0);
872 REG_WRITE(ah, AR_FILT_CCK, 0);
874 EXPORT_SYMBOL(ath9k_hw_disable_mib_counters);
876 void ath9k_hw_update_cycle_counters(struct ath_hw *ah)
878 struct ath_cycle_counters cc;
881 memcpy(&cc, &ah->cc, sizeof(cc));
883 /* freeze counters */
884 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
886 ah->cc.cycles = REG_READ(ah, AR_CCCNT);
887 if (ah->cc.cycles < cc.cycles) {
892 ah->cc.rx_clear = REG_READ(ah, AR_RCCNT);
893 ah->cc.rx_frame = REG_READ(ah, AR_RFCNT);
894 ah->cc.tx_frame = REG_READ(ah, AR_TFCNT);
896 /* prevent wraparound */
897 if (ah->cc.cycles & BIT(31))
900 #define CC_DELTA(_field, _reg) ah->cc_delta._field += ah->cc._field - cc._field
901 CC_DELTA(cycles, AR_CCCNT);
902 CC_DELTA(rx_frame, AR_RFCNT);
903 CC_DELTA(rx_clear, AR_RCCNT);
904 CC_DELTA(tx_frame, AR_TFCNT);
907 ah->listen_time += (ah->cc.cycles - cc.cycles) -
908 ((ah->cc.rx_frame - cc.rx_frame) +
909 (ah->cc.tx_frame - cc.tx_frame));
913 REG_WRITE(ah, AR_CCCNT, 0);
914 REG_WRITE(ah, AR_RFCNT, 0);
915 REG_WRITE(ah, AR_RCCNT, 0);
916 REG_WRITE(ah, AR_TFCNT, 0);
917 memset(&ah->cc, 0, sizeof(ah->cc));
920 /* unfreeze counters */
921 REG_WRITE(ah, AR_MIBC, 0);
925 * Process a MIB interrupt. We may potentially be invoked because
926 * any of the MIB counters overflow/trigger so don't assume we're
927 * here because a PHY error counter triggered.
929 void ath9k_hw_proc_mib_event(struct ath_hw *ah)
931 u32 phyCnt1, phyCnt2;
933 /* Reset these counters regardless */
934 REG_WRITE(ah, AR_FILT_OFDM, 0);
935 REG_WRITE(ah, AR_FILT_CCK, 0);
936 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
937 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
939 /* Clear the mib counters and save them in the stats */
940 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
944 * We must always clear the interrupt cause by
945 * resetting the phy error regs.
947 REG_WRITE(ah, AR_PHY_ERR_1, 0);
948 REG_WRITE(ah, AR_PHY_ERR_2, 0);
952 /* NB: these are not reset-on-read */
953 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
954 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
955 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
956 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
958 if (!use_new_ani(ah))
959 ath9k_hw_ani_read_counters(ah);
961 /* NB: always restart to insure the h/w counters are reset */
962 ath9k_ani_restart(ah);
965 EXPORT_SYMBOL(ath9k_hw_proc_mib_event);
967 void ath9k_hw_ani_setup(struct ath_hw *ah)
971 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
972 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
973 const int coarseLow[] = { -64, -64, -64, -64, -70 };
974 const int firpwr[] = { -78, -78, -78, -78, -80 };
976 for (i = 0; i < 5; i++) {
977 ah->totalSizeDesired[i] = totalSizeDesired[i];
978 ah->coarse_high[i] = coarseHigh[i];
979 ah->coarse_low[i] = coarseLow[i];
980 ah->firpwr[i] = firpwr[i];
984 void ath9k_hw_ani_init(struct ath_hw *ah)
986 struct ath_common *common = ath9k_hw_common(ah);
989 ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
991 if (use_new_ani(ah)) {
992 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
993 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_NEW;
995 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_NEW;
996 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_NEW;
998 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_OLD;
999 ah->config.ofdm_trig_low = ATH9K_ANI_OFDM_TRIG_LOW_OLD;
1001 ah->config.cck_trig_high = ATH9K_ANI_CCK_TRIG_HIGH_OLD;
1002 ah->config.cck_trig_low = ATH9K_ANI_CCK_TRIG_LOW_OLD;
1005 for (i = 0; i < ARRAY_SIZE(ah->channels); i++) {
1006 struct ath9k_channel *chan = &ah->channels[i];
1007 struct ar5416AniState *ani = &chan->ani;
1009 if (use_new_ani(ah)) {
1010 ani->spurImmunityLevel =
1011 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1013 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1015 if (AR_SREV_9300_20_OR_LATER(ah))
1017 !ATH9K_ANI_ENABLE_MRC_CCK;
1019 ani->mrcCCKOff = true;
1021 ani->ofdmsTurn = true;
1023 ani->spurImmunityLevel =
1024 ATH9K_ANI_SPUR_IMMUNE_LVL_OLD;
1025 ani->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_OLD;
1027 ani->cckWeakSigThreshold =
1028 ATH9K_ANI_CCK_WEAK_SIG_THR;
1031 ani->rssiThrHigh = ATH9K_ANI_RSSI_THR_HIGH;
1032 ani->rssiThrLow = ATH9K_ANI_RSSI_THR_LOW;
1033 ani->ofdmWeakSigDetectOff =
1034 !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1035 ani->cckNoiseImmunityLevel = ATH9K_ANI_CCK_DEF_LEVEL;
1039 * since we expect some ongoing maintenance on the tables, let's sanity
1040 * check here default level should not modify INI setting.
1042 if (use_new_ani(ah)) {
1043 const struct ani_ofdm_level_entry *entry_ofdm;
1044 const struct ani_cck_level_entry *entry_cck;
1046 entry_ofdm = &ofdm_level_table[ATH9K_ANI_OFDM_DEF_LEVEL];
1047 entry_cck = &cck_level_table[ATH9K_ANI_CCK_DEF_LEVEL];
1049 ah->aniperiod = ATH9K_ANI_PERIOD_NEW;
1050 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_NEW;
1052 ah->aniperiod = ATH9K_ANI_PERIOD_OLD;
1053 ah->config.ani_poll_interval = ATH9K_ANI_POLLINTERVAL_OLD;
1056 if (ah->config.enable_ani)
1057 ah->proc_phyerr |= HAL_PROCESS_ANI;
1059 ath9k_ani_restart(ah);
1060 ath9k_enable_mib_counters(ah);
1063 void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah)
1065 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1066 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1068 priv_ops->ani_reset = ath9k_ani_reset_old;
1069 priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_old;
1071 ops->ani_monitor = ath9k_hw_ani_monitor_old;
1073 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v1\n");
1076 void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah)
1078 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1079 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1081 priv_ops->ani_reset = ath9k_ani_reset_new;
1082 priv_ops->ani_lower_immunity = ath9k_hw_ani_lower_immunity_new;
1084 ops->ani_monitor = ath9k_hw_ani_monitor_new;
1086 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, "Using ANI v2\n");