4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
24 #include <linux/slab.h>
38 * Get the PHY Chip revision
40 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
47 * Set the radio chip access register
51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
62 /* ...wait until PHY is ready and read the selected radio revision */
63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
65 for (i = 0; i < 8; i++)
66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
68 if (ah->ah_version == AR5K_AR5210) {
69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
74 ((srev & 0x0f) << 4), 8);
77 /* Reset to the 5GHz mode */
78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
84 * Check if a channel is supported
86 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
88 /* Check if the channel is in our supported range */
89 if (flags & CHANNEL_2GHZ) {
90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
93 } else if (flags & CHANNEL_5GHZ)
94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
101 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
102 struct ieee80211_channel *channel)
106 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) ||
108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
113 if ((channel->center_freq % refclk_freq != 0) &&
114 ((channel->center_freq % refclk_freq < 10) ||
115 (channel->center_freq % refclk_freq > 22)))
122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
124 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
125 const struct ath5k_rf_reg *rf_regs,
126 u32 val, u8 reg_id, bool set)
128 const struct ath5k_rf_reg *rfreg = NULL;
129 u8 offset, bank, num_bits, col, position;
131 u32 mask, data, last_bit, bits_shifted, first_bit;
137 rfb = ah->ah_rf_banks;
139 for (i = 0; i < ah->ah_rf_regs_count; i++) {
140 if (rf_regs[i].index == reg_id) {
146 if (rfb == NULL || rfreg == NULL) {
147 ATH5K_PRINTF("Rf register not found!\n");
148 /* should not happen */
153 num_bits = rfreg->field.len;
154 first_bit = rfreg->field.pos;
155 col = rfreg->field.col;
157 /* first_bit is an offset from bank's
158 * start. Since we have all banks on
159 * the same array, we use this offset
160 * to mark each bank's start */
161 offset = ah->ah_offset[bank];
164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
165 ATH5K_PRINTF("invalid values at offset %u\n", offset);
169 entry = ((first_bit - 1) / 8) + offset;
170 position = (first_bit - 1) % 8;
173 data = ath5k_hw_bitswap(val, num_bits);
175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
176 position = 0, entry++) {
178 last_bit = (position + bits_left > 8) ? 8 :
179 position + bits_left;
181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
186 rfb[entry] |= ((data << position) << (col * 8)) & mask;
187 data >>= (8 - position);
189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
191 bits_shifted += last_bit - position;
194 bits_left -= 8 - position;
197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
205 * @ah: the &struct ath5k_hw
206 * @channel: the currently set channel upon reset
208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
211 * Since delta slope is floating point we split it on its exponent and
212 * mantissa and provide these values on hw.
214 * For more infos i think this patent is related
215 * http://www.freepatentsonline.com/7184495.html
217 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
218 struct ieee80211_channel *channel)
220 /* Get exponent and mantissa and set it */
221 u32 coef_scaled, coef_exp, coef_man,
222 ds_coef_exp, ds_coef_man, clock;
224 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
225 !(channel->hw_value & CHANNEL_OFDM));
228 * ALGO: coef = (5 * clock / carrier_freq) / 2
229 * we scale coef by shifting clock value by 24 for
230 * better precision since we use integers */
231 switch (ah->ah_bwmode) {
232 case AR5K_BWMODE_40MHZ:
235 case AR5K_BWMODE_10MHZ:
238 case AR5K_BWMODE_5MHZ:
245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
248 * ALGO: coef_exp = 14 - highest set bit position */
249 coef_exp = ilog2(coef_scaled);
251 /* Doesn't make sense if it's zero*/
252 if (!coef_scaled || !coef_exp)
255 /* Note: we've shifted coef_scaled by 24 */
256 coef_exp = 14 - (coef_exp - 24);
259 /* Get mantissa (significant digits)
260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
261 coef_man = coef_scaled +
262 (1 << (24 - coef_exp - 1));
264 /* Calculate delta slope coefficient exponent
265 * and mantissa (remove scaling) and set them on hw */
266 ds_coef_man = coef_man >> (24 - coef_exp);
267 ds_coef_exp = coef_exp - 16;
269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
277 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
286 /**********************\
287 * RF Gain optimization *
288 \**********************/
291 * This code is used to optimize RF gain on different environments
292 * (temperature mostly) based on feedback from a power detector.
294 * It's only used on RF5111 and RF5112, later RF chips seem to have
295 * auto adjustment on hw -notice they have a much smaller BANK 7 and
296 * no gain optimization ladder-.
298 * For more infos check out this patent doc
299 * http://www.freepatentsonline.com/7400691.html
301 * This paper describes power drops as seen on the receiver due to
303 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
304 * %20of%20Power%20Control.pdf
306 * And this is the MadWiFi bug entry related to the above
307 * http://madwifi-project.org/ticket/1659
308 * with various measurements and diagrams
310 * TODO: Deal with power drops due to probes by setting an apropriate
311 * tx power on the probe packets ! Make this part of the calibration process.
314 /* Initialize ah_gain durring attach */
315 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
317 /* Initialize the gain optimization values */
318 switch (ah->ah_radio) {
320 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
321 ah->ah_gain.g_low = 20;
322 ah->ah_gain.g_high = 35;
323 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
326 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
327 ah->ah_gain.g_low = 20;
328 ah->ah_gain.g_high = 85;
329 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
338 /* Schedule a gain probe check on the next transmited packet.
339 * That means our next packet is going to be sent with lower
340 * tx power and a Peak to Average Power Detector (PAPD) will try
341 * to measure the gain.
343 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
344 * just after we enable the probe so that we don't mess with
345 * standard traffic ? Maybe it's time to use sw interrupts and
346 * a probe tasklet !!!
348 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
351 /* Skip if gain calibration is inactive or
352 * we already handle a probe request */
353 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
356 /* Send the packet with 2dB below max power as
357 * patent doc suggest */
358 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
359 AR5K_PHY_PAPD_PROBE_TXPOWER) |
360 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
362 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
366 /* Calculate gain_F measurement correction
367 * based on the current step for RF5112 rev. 2 */
368 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
372 const struct ath5k_gain_opt *go;
373 const struct ath5k_gain_opt_step *g_step;
374 const struct ath5k_rf_reg *rf_regs;
376 /* Only RF5112 Rev. 2 supports it */
377 if ((ah->ah_radio != AR5K_RF5112) ||
378 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
381 go = &rfgain_opt_5112;
382 rf_regs = rf_regs_5112a;
383 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
385 g_step = &go->go_step[ah->ah_gain.g_step_idx];
387 if (ah->ah_rf_banks == NULL)
390 rf = ah->ah_rf_banks;
391 ah->ah_gain.g_f_corr = 0;
393 /* No VGA (Variable Gain Amplifier) override, skip */
394 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
397 /* Mix gain stepping */
398 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
400 /* Mix gain override */
401 mix = g_step->gos_param[0];
405 ah->ah_gain.g_f_corr = step * 2;
408 ah->ah_gain.g_f_corr = (step - 5) * 2;
411 ah->ah_gain.g_f_corr = step;
414 ah->ah_gain.g_f_corr = 0;
418 return ah->ah_gain.g_f_corr;
421 /* Check if current gain_F measurement is in the range of our
422 * power detector windows. If we get a measurement outside range
423 * we know it's not accurate (detectors can't measure anything outside
424 * their detection window) so we must ignore it */
425 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
427 const struct ath5k_rf_reg *rf_regs;
428 u32 step, mix_ovr, level[4];
431 if (ah->ah_rf_banks == NULL)
434 rf = ah->ah_rf_banks;
436 if (ah->ah_radio == AR5K_RF5111) {
438 rf_regs = rf_regs_5111;
439 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
441 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
445 level[1] = (step == 63) ? 50 : step + 4;
446 level[2] = (step != 63) ? 64 : level[0];
447 level[3] = level[2] + 50 ;
449 ah->ah_gain.g_high = level[3] -
450 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
451 ah->ah_gain.g_low = level[0] +
452 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
455 rf_regs = rf_regs_5112;
456 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
458 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
461 level[0] = level[2] = 0;
464 level[1] = level[3] = 83;
466 level[1] = level[3] = 107;
467 ah->ah_gain.g_high = 55;
471 return (ah->ah_gain.g_current >= level[0] &&
472 ah->ah_gain.g_current <= level[1]) ||
473 (ah->ah_gain.g_current >= level[2] &&
474 ah->ah_gain.g_current <= level[3]);
477 /* Perform gain_F adjustment by choosing the right set
478 * of parameters from RF gain optimization ladder */
479 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
481 const struct ath5k_gain_opt *go;
482 const struct ath5k_gain_opt_step *g_step;
485 switch (ah->ah_radio) {
487 go = &rfgain_opt_5111;
490 go = &rfgain_opt_5112;
496 g_step = &go->go_step[ah->ah_gain.g_step_idx];
498 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
500 /* Reached maximum */
501 if (ah->ah_gain.g_step_idx == 0)
504 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
505 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
506 ah->ah_gain.g_step_idx > 0;
507 g_step = &go->go_step[ah->ah_gain.g_step_idx])
508 ah->ah_gain.g_target -= 2 *
509 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
516 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
518 /* Reached minimum */
519 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
522 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
523 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
524 ah->ah_gain.g_step_idx < go->go_steps_count-1;
525 g_step = &go->go_step[ah->ah_gain.g_step_idx])
526 ah->ah_gain.g_target -= 2 *
527 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
535 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
536 "ret %d, gain step %u, current gain %u, target gain %u\n",
537 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
538 ah->ah_gain.g_target);
543 /* Main callback for thermal RF gain calibration engine
544 * Check for a new gain reading and schedule an adjustment
547 * TODO: Use sw interrupt to schedule reset if gain_F needs
549 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
552 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
554 if (ah->ah_rf_banks == NULL ||
555 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
556 return AR5K_RFGAIN_INACTIVE;
558 /* No check requested, either engine is inactive
559 * or an adjustment is already requested */
560 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
563 /* Read the PAPD (Peak to Average Power Detector)
565 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
567 /* No probe is scheduled, read gain_F measurement */
568 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
569 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
570 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
572 /* If tx packet is CCK correct the gain_F measurement
573 * by cck ofdm gain delta */
574 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
575 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
576 ah->ah_gain.g_current +=
577 ee->ee_cck_ofdm_gain_delta;
579 ah->ah_gain.g_current +=
580 AR5K_GAIN_CCK_PROBE_CORR;
583 /* Further correct gain_F measurement for
585 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
586 ath5k_hw_rf_gainf_corr(ah);
587 ah->ah_gain.g_current =
588 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
589 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
593 /* Check if measurement is ok and if we need
594 * to adjust gain, schedule a gain adjustment,
595 * else switch back to the acive state */
596 if (ath5k_hw_rf_check_gainf_readback(ah) &&
597 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
598 ath5k_hw_rf_gainf_adjust(ah)) {
599 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
601 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
606 return ah->ah_gain.g_state;
609 /* Write initial RF gain table to set the RF sensitivity
610 * this one works on all RF chips and has nothing to do
611 * with gain_F calibration */
612 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
614 const struct ath5k_ini_rfgain *ath5k_rfg;
615 unsigned int i, size;
617 switch (ah->ah_radio) {
619 ath5k_rfg = rfgain_5111;
620 size = ARRAY_SIZE(rfgain_5111);
623 ath5k_rfg = rfgain_5112;
624 size = ARRAY_SIZE(rfgain_5112);
627 ath5k_rfg = rfgain_2413;
628 size = ARRAY_SIZE(rfgain_2413);
631 ath5k_rfg = rfgain_2316;
632 size = ARRAY_SIZE(rfgain_2316);
635 ath5k_rfg = rfgain_5413;
636 size = ARRAY_SIZE(rfgain_5413);
640 ath5k_rfg = rfgain_2425;
641 size = ARRAY_SIZE(rfgain_2425);
648 case AR5K_INI_RFGAIN_2GHZ:
649 case AR5K_INI_RFGAIN_5GHZ:
655 for (i = 0; i < size; i++) {
657 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
658 (u32)ath5k_rfg[i].rfg_register);
666 /********************\
667 * RF Registers setup *
668 \********************/
671 * Setup RF registers by writing RF buffer on hw
673 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
674 struct ieee80211_channel *channel, unsigned int mode)
676 const struct ath5k_rf_reg *rf_regs;
677 const struct ath5k_ini_rfbuffer *ini_rfb;
678 const struct ath5k_gain_opt *go = NULL;
679 const struct ath5k_gain_opt_step *g_step;
680 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
683 int i, obdb = -1, bank = -1;
685 switch (ah->ah_radio) {
687 rf_regs = rf_regs_5111;
688 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
690 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
691 go = &rfgain_opt_5111;
694 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
695 rf_regs = rf_regs_5112a;
696 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
698 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
700 rf_regs = rf_regs_5112;
701 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
703 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
705 go = &rfgain_opt_5112;
708 rf_regs = rf_regs_2413;
709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
714 rf_regs = rf_regs_2316;
715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
720 rf_regs = rf_regs_5413;
721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
726 rf_regs = rf_regs_2425;
727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
729 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
732 rf_regs = rf_regs_2425;
733 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
734 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
736 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
739 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
746 /* If it's the first time we set RF buffer, allocate
747 * ah->ah_rf_banks based on ah->ah_rf_banks_size
749 if (ah->ah_rf_banks == NULL) {
750 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
752 if (ah->ah_rf_banks == NULL) {
753 ATH5K_ERR(ah->ah_sc, "out of memory\n");
758 /* Copy values to modify them */
759 rfb = ah->ah_rf_banks;
761 for (i = 0; i < ah->ah_rf_banks_size; i++) {
762 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
763 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
767 /* Bank changed, write down the offset */
768 if (bank != ini_rfb[i].rfb_bank) {
769 bank = ini_rfb[i].rfb_bank;
770 ah->ah_offset[bank] = i;
773 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
776 /* Set Output and Driver bias current (OB/DB) */
777 if (channel->hw_value & CHANNEL_2GHZ) {
779 if (channel->hw_value & CHANNEL_CCK)
780 ee_mode = AR5K_EEPROM_MODE_11B;
782 ee_mode = AR5K_EEPROM_MODE_11G;
784 /* For RF511X/RF211X combination we
785 * use b_OB and b_DB parameters stored
786 * in eeprom on ee->ee_ob[ee_mode][0]
788 * For all other chips we use OB/DB for 2Ghz
789 * stored in the b/g modal section just like
790 * 802.11a on ee->ee_ob[ee_mode][1] */
791 if ((ah->ah_radio == AR5K_RF5111) ||
792 (ah->ah_radio == AR5K_RF5112))
797 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
798 AR5K_RF_OB_2GHZ, true);
800 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
801 AR5K_RF_DB_2GHZ, true);
803 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
804 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
805 (ah->ah_radio == AR5K_RF5111)) {
807 /* For 11a, Turbo and XR we need to choose
808 * OB/DB based on frequency range */
809 ee_mode = AR5K_EEPROM_MODE_11A;
810 obdb = channel->center_freq >= 5725 ? 3 :
811 (channel->center_freq >= 5500 ? 2 :
812 (channel->center_freq >= 5260 ? 1 :
813 (channel->center_freq > 4000 ? 0 : -1)));
818 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
819 AR5K_RF_OB_5GHZ, true);
821 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
822 AR5K_RF_DB_5GHZ, true);
825 g_step = &go->go_step[ah->ah_gain.g_step_idx];
827 /* Set turbo mode (N/A on RF5413) */
828 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
829 (ah->ah_radio != AR5K_RF5413))
830 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
832 /* Bank Modifications (chip-specific) */
833 if (ah->ah_radio == AR5K_RF5111) {
835 /* Set gain_F settings according to current step */
836 if (channel->hw_value & CHANNEL_OFDM) {
838 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
839 AR5K_PHY_FRAME_CTL_TX_CLIP,
840 g_step->gos_param[0]);
842 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
843 AR5K_RF_PWD_90, true);
845 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
846 AR5K_RF_PWD_84, true);
848 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
849 AR5K_RF_RFGAIN_SEL, true);
851 /* We programmed gain_F parameters, switch back
853 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
859 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
860 AR5K_RF_PWD_XPD, true);
862 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
863 AR5K_RF_XPD_GAIN, true);
865 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
866 AR5K_RF_GAIN_I, true);
868 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
869 AR5K_RF_PLO_SEL, true);
871 /* Tweak power detectors for half/quarter rate support */
872 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
873 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
876 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
877 AR5K_RF_WAIT_S, true);
879 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
882 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
883 AR5K_RF_WAIT_I, true);
884 ath5k_hw_rfb_op(ah, rf_regs, 3,
885 AR5K_RF_MAX_TIME, true);
890 if (ah->ah_radio == AR5K_RF5112) {
892 /* Set gain_F settings according to current step */
893 if (channel->hw_value & CHANNEL_OFDM) {
895 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
896 AR5K_RF_MIXGAIN_OVR, true);
898 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
899 AR5K_RF_PWD_138, true);
901 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
902 AR5K_RF_PWD_137, true);
904 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
905 AR5K_RF_PWD_136, true);
907 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
908 AR5K_RF_PWD_132, true);
910 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
911 AR5K_RF_PWD_131, true);
913 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
914 AR5K_RF_PWD_130, true);
916 /* We programmed gain_F parameters, switch back
918 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
923 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
924 AR5K_RF_XPD_SEL, true);
926 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
927 /* Rev. 1 supports only one xpd */
928 ath5k_hw_rfb_op(ah, rf_regs,
929 ee->ee_x_gain[ee_mode],
930 AR5K_RF_XPD_GAIN, true);
933 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
934 if (ee->ee_pd_gains[ee_mode] > 1) {
935 ath5k_hw_rfb_op(ah, rf_regs,
937 AR5K_RF_PD_GAIN_LO, true);
938 ath5k_hw_rfb_op(ah, rf_regs,
940 AR5K_RF_PD_GAIN_HI, true);
942 ath5k_hw_rfb_op(ah, rf_regs,
944 AR5K_RF_PD_GAIN_LO, true);
945 ath5k_hw_rfb_op(ah, rf_regs,
947 AR5K_RF_PD_GAIN_HI, true);
950 /* Lower synth voltage on Rev 2 */
951 ath5k_hw_rfb_op(ah, rf_regs, 2,
952 AR5K_RF_HIGH_VC_CP, true);
954 ath5k_hw_rfb_op(ah, rf_regs, 2,
955 AR5K_RF_MID_VC_CP, true);
957 ath5k_hw_rfb_op(ah, rf_regs, 2,
958 AR5K_RF_LOW_VC_CP, true);
960 ath5k_hw_rfb_op(ah, rf_regs, 2,
961 AR5K_RF_PUSH_UP, true);
963 /* Decrease power consumption on 5213+ BaseBand */
964 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
965 ath5k_hw_rfb_op(ah, rf_regs, 1,
966 AR5K_RF_PAD2GND, true);
968 ath5k_hw_rfb_op(ah, rf_regs, 1,
969 AR5K_RF_XB2_LVL, true);
971 ath5k_hw_rfb_op(ah, rf_regs, 1,
972 AR5K_RF_XB5_LVL, true);
974 ath5k_hw_rfb_op(ah, rf_regs, 1,
975 AR5K_RF_PWD_167, true);
977 ath5k_hw_rfb_op(ah, rf_regs, 1,
978 AR5K_RF_PWD_166, true);
982 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
983 AR5K_RF_GAIN_I, true);
985 /* Tweak power detector for half/quarter rates */
986 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
987 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
990 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
993 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
994 AR5K_RF_PD_PERIOD_A, true);
995 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
996 AR5K_RF_PD_DELAY_A, true);
1001 if (ah->ah_radio == AR5K_RF5413 &&
1002 channel->hw_value & CHANNEL_2GHZ) {
1004 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
1007 /* Set optimum value for early revisions (on pci-e chips) */
1008 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1009 ah->ah_mac_srev < AR5K_SREV_AR5413)
1010 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1011 AR5K_RF_PWD_ICLOBUF_2G, true);
1015 /* Write RF banks on hw */
1016 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1018 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1025 /**************************\
1026 PHY/RF channel functions
1027 \**************************/
1030 * Convertion needed for RF5110
1032 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1037 * Convert IEEE channel/MHz to an internal channel value used
1038 * by the AR5210 chipset. This has not been verified with
1039 * newer chipsets like the AR5212A who have a completely
1040 * different RF/PHY part.
1042 athchan = (ath5k_hw_bitswap(
1043 (ieee80211_frequency_to_channel(
1044 channel->center_freq) - 24) / 2, 5)
1045 << 1) | (1 << 6) | 0x1;
1050 * Set channel on RF5110
1052 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1053 struct ieee80211_channel *channel)
1058 * Set the channel and wait
1060 data = ath5k_hw_rf5110_chan2athchan(channel);
1061 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1062 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1069 * Convertion needed for 5111
1071 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1072 struct ath5k_athchan_2ghz *athchan)
1076 /* Cast this value to catch negative channel numbers (>= -19) */
1077 channel = (int)ieee;
1080 * Map 2GHz IEEE channel to 5GHz Atheros channel
1082 if (channel <= 13) {
1083 athchan->a2_athchan = 115 + channel;
1084 athchan->a2_flags = 0x46;
1085 } else if (channel == 14) {
1086 athchan->a2_athchan = 124;
1087 athchan->a2_flags = 0x44;
1088 } else if (channel >= 15 && channel <= 26) {
1089 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1090 athchan->a2_flags = 0x46;
1098 * Set channel on 5111
1100 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1101 struct ieee80211_channel *channel)
1103 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1104 unsigned int ath5k_channel =
1105 ieee80211_frequency_to_channel(channel->center_freq);
1106 u32 data0, data1, clock;
1110 * Set the channel on the RF5111 radio
1114 if (channel->hw_value & CHANNEL_2GHZ) {
1115 /* Map 2GHz channel to 5GHz Atheros channel ID */
1116 ret = ath5k_hw_rf5111_chan2athchan(
1117 ieee80211_frequency_to_channel(channel->center_freq),
1118 &ath5k_channel_2ghz);
1122 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1123 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1127 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1129 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1130 (clock << 1) | (1 << 10) | 1;
1133 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1134 << 2) | (clock << 1) | (1 << 10) | 1;
1137 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1139 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1140 AR5K_RF_BUFFER_CONTROL_3);
1146 * Set channel on 5112 and newer
1148 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1149 struct ieee80211_channel *channel)
1151 u32 data, data0, data1, data2;
1154 data = data0 = data1 = data2 = 0;
1155 c = channel->center_freq;
1158 if (!((c - 2224) % 5)) {
1159 data0 = ((2 * (c - 704)) - 3040) / 10;
1161 } else if (!((c - 2192) % 5)) {
1162 data0 = ((2 * (c - 672)) - 3040) / 10;
1167 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1168 } else if ((c % 5) != 2 || c > 5435) {
1169 if (!(c % 20) && c >= 5120) {
1170 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1171 data2 = ath5k_hw_bitswap(3, 2);
1172 } else if (!(c % 10)) {
1173 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1174 data2 = ath5k_hw_bitswap(2, 2);
1175 } else if (!(c % 5)) {
1176 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1177 data2 = ath5k_hw_bitswap(1, 2);
1181 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1182 data2 = ath5k_hw_bitswap(0, 2);
1185 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1187 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1188 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1194 * Set the channel on the RF2425
1196 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1197 struct ieee80211_channel *channel)
1199 u32 data, data0, data2;
1202 data = data0 = data2 = 0;
1203 c = channel->center_freq;
1206 data0 = ath5k_hw_bitswap((c - 2272), 8);
1209 } else if ((c % 5) != 2 || c > 5435) {
1210 if (!(c % 20) && c < 5120)
1211 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1213 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1215 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1218 data2 = ath5k_hw_bitswap(1, 2);
1220 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1221 data2 = ath5k_hw_bitswap(0, 2);
1224 data = (data0 << 4) | data2 << 2 | 0x1001;
1226 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1227 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1233 * Set a channel on the radio chip
1235 static int ath5k_hw_channel(struct ath5k_hw *ah,
1236 struct ieee80211_channel *channel)
1240 * Check bounds supported by the PHY (we don't care about regultory
1241 * restrictions at this point). Note: hw_value already has the band
1242 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1243 * of the band by that */
1244 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1245 ATH5K_ERR(ah->ah_sc,
1246 "channel frequency (%u MHz) out of supported "
1248 channel->center_freq);
1253 * Set the channel and wait
1255 switch (ah->ah_radio) {
1257 ret = ath5k_hw_rf5110_channel(ah, channel);
1260 ret = ath5k_hw_rf5111_channel(ah, channel);
1263 ret = ath5k_hw_rf2425_channel(ah, channel);
1266 ret = ath5k_hw_rf5112_channel(ah, channel);
1273 /* Set JAPAN setting for channel 14 */
1274 if (channel->center_freq == 2484) {
1275 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1276 AR5K_PHY_CCKTXCTL_JAPAN);
1278 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1279 AR5K_PHY_CCKTXCTL_WORLD);
1282 ah->ah_current_channel = channel;
1291 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1295 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1296 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1299 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1303 ah->ah_nfcal_hist.index = 0;
1304 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1305 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1308 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1310 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1311 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1312 hist->nfval[hist->index] = noise_floor;
1315 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1317 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1321 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1322 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1323 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1324 if (sort[j] > sort[j-1]) {
1326 sort[j] = sort[j-1];
1331 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1332 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1333 "cal %d:%d\n", i, sort[i]);
1335 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1339 * When we tell the hardware to perform a noise floor calibration
1340 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1341 * sample-and-hold the minimum noise level seen at the antennas.
1342 * This value is then stored in a ring buffer of recently measured
1343 * noise floor values so we have a moving window of the last few
1346 * The median of the values in the history is then loaded into the
1347 * hardware for its own use for RSSI and CCA measurements.
1349 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1351 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1356 /* keep last value if calibration hasn't completed */
1357 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1358 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1359 "NF did not complete in calibration window\n");
1364 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1367 ee_mode = AR5K_EEPROM_MODE_11A;
1370 ee_mode = AR5K_EEPROM_MODE_11G;
1374 ee_mode = AR5K_EEPROM_MODE_11B;
1379 /* completed NF calibration, test threshold */
1380 nf = ath5k_hw_read_measured_noise_floor(ah);
1381 threshold = ee->ee_noise_floor_thr[ee_mode];
1383 if (nf > threshold) {
1384 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1385 "noise floor failure detected; "
1386 "read %d, threshold %d\n",
1389 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1392 ath5k_hw_update_nfcal_hist(ah, nf);
1393 nf = ath5k_hw_get_median_noise_floor(ah);
1395 /* load noise floor (in .5 dBm) so the hardware will use it */
1396 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1397 val |= (nf * 2) & AR5K_PHY_NF_M;
1398 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1400 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1401 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1403 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1407 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1408 * so that we're not capped by the median we just loaded.
1409 * This will be used as the initial value for the next noise
1410 * floor calibration.
1412 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1413 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1414 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1415 AR5K_PHY_AGCCTL_NF_EN |
1416 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1417 AR5K_PHY_AGCCTL_NF);
1419 ah->ah_noise_floor = nf;
1421 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1422 "noise floor calibrated: %d\n", nf);
1426 * Perform a PHY calibration on RF5110
1427 * -Fix BPSK/QAM Constellation (I/Q correction)
1429 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1430 struct ieee80211_channel *channel)
1432 u32 phy_sig, phy_agc, phy_sat, beacon;
1436 * Disable beacons and RX/TX queues, wait
1438 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1439 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1440 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1441 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1446 * Set the channel (with AGC turned off)
1448 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1450 ret = ath5k_hw_channel(ah, channel);
1453 * Activate PHY and wait
1455 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1458 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1464 * Calibrate the radio chip
1467 /* Remember normal state */
1468 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1469 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1470 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1472 /* Update radio registers */
1473 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1474 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1476 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1477 AR5K_PHY_AGCCOARSE_LO)) |
1478 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1479 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1481 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1482 AR5K_PHY_ADCSAT_THR)) |
1483 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1484 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1488 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1490 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1491 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1496 * Enable calibration and wait until completion
1498 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1500 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1501 AR5K_PHY_AGCCTL_CAL, 0, false);
1503 /* Reset to normal state */
1504 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1505 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1506 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1509 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1510 channel->center_freq);
1515 * Re-enable RX/TX and beacons
1517 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1518 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1519 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1525 * Perform I/Q calibration on RF5111/5112 and newer chips
1528 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1531 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1534 if (!ah->ah_calibration ||
1535 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1538 /* Calibration has finished, get the results and re-run */
1539 /* work around empty results which can apparently happen on 5212 */
1540 for (i = 0; i <= 10; i++) {
1541 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1542 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1543 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1544 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1545 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1550 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1552 if (ah->ah_version == AR5K_AR5211)
1553 q_coffd = q_pwr >> 6;
1555 q_coffd = q_pwr >> 7;
1557 /* protect against divide by 0 and loss of sign bits */
1558 if (i_coffd == 0 || q_coffd < 2)
1561 i_coff = (-iq_corr) / i_coffd;
1562 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1564 if (ah->ah_version == AR5K_AR5211)
1565 q_coff = (i_pwr / q_coffd) - 64;
1567 q_coff = (i_pwr / q_coffd) - 128;
1568 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1570 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1571 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1572 i_coff, q_coff, i_coffd, q_coffd);
1574 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1575 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1576 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1577 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1579 /* Re-enable calibration -if we don't we'll commit
1580 * the same values again and again */
1581 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1582 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1583 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1589 * Perform a PHY calibration
1591 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1592 struct ieee80211_channel *channel)
1596 if (ah->ah_radio == AR5K_RF5110)
1597 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1599 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1600 ath5k_hw_request_rfgain_probe(ah);
1607 /***************************\
1608 * Spur mitigation functions *
1609 \***************************/
1612 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1613 struct ieee80211_channel *channel)
1615 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1616 u32 mag_mask[4] = {0, 0, 0, 0};
1617 u32 pilot_mask[2] = {0, 0};
1618 /* Note: fbin values are scaled up by 2 */
1619 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1620 s32 spur_delta_phase, spur_freq_sigma_delta;
1621 s32 spur_offset, num_symbols_x16;
1622 u8 num_symbol_offsets, i, freq_band;
1624 /* Convert current frequency to fbin value (the same way channels
1625 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1626 * up by 2 so we can compare it later */
1627 if (channel->hw_value & CHANNEL_2GHZ) {
1628 chan_fbin = (channel->center_freq - 2300) * 10;
1629 freq_band = AR5K_EEPROM_BAND_2GHZ;
1631 chan_fbin = (channel->center_freq - 4900) * 10;
1632 freq_band = AR5K_EEPROM_BAND_5GHZ;
1635 /* Check if any spur_chan_fbin from EEPROM is
1636 * within our current channel's spur detection range */
1637 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1638 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1639 /* XXX: Half/Quarter channels ?*/
1640 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
1641 spur_detection_window *= 2;
1643 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1644 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1646 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1647 * so it's zero if we got nothing from EEPROM */
1648 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1649 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1653 if ((chan_fbin - spur_detection_window <=
1654 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1655 (chan_fbin + spur_detection_window >=
1656 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1657 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1662 /* We need to enable spur filter for this channel */
1663 if (spur_chan_fbin) {
1664 spur_offset = spur_chan_fbin - chan_fbin;
1667 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1668 * spur_delta_phase -> spur_offset / chip_freq << 11
1669 * Note: Both values have 100Hz resolution
1671 switch (ah->ah_bwmode) {
1672 case AR5K_BWMODE_40MHZ:
1673 /* Both sample_freq and chip_freq are 80MHz */
1674 spur_delta_phase = (spur_offset << 16) / 25;
1675 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1676 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
1678 case AR5K_BWMODE_10MHZ:
1679 /* Both sample_freq and chip_freq are 20MHz (?) */
1680 spur_delta_phase = (spur_offset << 18) / 25;
1681 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1682 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1683 case AR5K_BWMODE_5MHZ:
1684 /* Both sample_freq and chip_freq are 10MHz (?) */
1685 spur_delta_phase = (spur_offset << 19) / 25;
1686 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1687 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
1689 if (channel->hw_value == CHANNEL_A) {
1690 /* Both sample_freq and chip_freq are 40MHz */
1691 spur_delta_phase = (spur_offset << 17) / 25;
1692 spur_freq_sigma_delta =
1693 (spur_delta_phase >> 10);
1695 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1697 /* sample_freq -> 40MHz chip_freq -> 44MHz
1698 * (for b compatibility) */
1699 spur_delta_phase = (spur_offset << 17) / 25;
1700 spur_freq_sigma_delta =
1701 (spur_offset << 8) / 55;
1703 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1708 /* Calculate pilot and magnitude masks */
1710 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1711 * and divide by symbol_width to find how many symbols we have
1712 * Note: number of symbols is scaled up by 16 */
1713 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1715 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1716 if (!(num_symbols_x16 & 0xF))
1718 num_symbol_offsets = 3;
1721 num_symbol_offsets = 4;
1723 for (i = 0; i < num_symbol_offsets; i++) {
1725 /* Calculate pilot mask */
1727 (num_symbols_x16 / 16) + i + 25;
1729 /* Pilot magnitude mask seems to be a way to
1730 * declare the boundaries for our detection
1731 * window or something, it's 2 for the middle
1732 * value(s) where the symbol is expected to be
1733 * and 1 on the boundary values */
1735 (i == 0 || i == (num_symbol_offsets - 1))
1738 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1739 if (curr_sym_off <= 25)
1740 pilot_mask[0] |= 1 << curr_sym_off;
1741 else if (curr_sym_off >= 27)
1742 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1743 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1744 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1746 /* Calculate magnitude mask (for viterbi decoder) */
1747 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1749 plt_mag_map << (curr_sym_off + 1) * 2;
1750 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1752 plt_mag_map << (curr_sym_off - 15) * 2;
1753 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1755 plt_mag_map << (curr_sym_off - 31) * 2;
1756 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1758 plt_mag_map << (curr_sym_off - 47) * 2;
1762 /* Write settings on hw to enable spur filter */
1763 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1764 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1765 /* XXX: Self correlator also ? */
1766 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1767 AR5K_PHY_IQ_PILOT_MASK_EN |
1768 AR5K_PHY_IQ_CHAN_MASK_EN |
1769 AR5K_PHY_IQ_SPUR_FILT_EN);
1771 /* Set delta phase and freq sigma delta */
1772 ath5k_hw_reg_write(ah,
1773 AR5K_REG_SM(spur_delta_phase,
1774 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1775 AR5K_REG_SM(spur_freq_sigma_delta,
1776 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1777 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1778 AR5K_PHY_TIMING_11);
1780 /* Write pilot masks */
1781 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1782 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1783 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1786 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1787 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1788 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1791 /* Write magnitude masks */
1792 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1793 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1794 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1795 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1796 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1799 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1800 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1801 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1802 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1803 AR5K_PHY_BIN_MASK2_4_MASK_4,
1806 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1807 AR5K_PHY_IQ_SPUR_FILT_EN) {
1808 /* Clean up spur mitigation settings and disable fliter */
1809 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1810 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1811 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1812 AR5K_PHY_IQ_PILOT_MASK_EN |
1813 AR5K_PHY_IQ_CHAN_MASK_EN |
1814 AR5K_PHY_IQ_SPUR_FILT_EN);
1815 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1817 /* Clear pilot masks */
1818 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1820 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1823 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1824 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1825 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1828 /* Clear magnitude masks */
1829 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1830 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1831 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1832 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1833 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1836 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1837 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1838 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1839 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1840 AR5K_PHY_BIN_MASK2_4_MASK_4,
1850 static void /*TODO:Boundary check*/
1851 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1853 if (ah->ah_version != AR5K_AR5210)
1854 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1858 * Enable/disable fast rx antenna diversity
1861 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1864 case AR5K_EEPROM_MODE_11G:
1865 /* XXX: This is set to
1866 * disabled on initvals !!! */
1867 case AR5K_EEPROM_MODE_11A:
1869 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1870 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1872 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1873 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1875 case AR5K_EEPROM_MODE_11B:
1876 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1877 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1884 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1885 AR5K_PHY_RESTART_DIV_GC, 4);
1887 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1888 AR5K_PHY_FAST_ANT_DIV_EN);
1890 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1891 AR5K_PHY_RESTART_DIV_GC, 0);
1893 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1894 AR5K_PHY_FAST_ANT_DIV_EN);
1899 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1904 * In case a fixed antenna was set as default
1905 * use the same switch table twice.
1907 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1908 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1909 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1910 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1912 ant0 = AR5K_ANT_SWTABLE_A;
1913 ant1 = AR5K_ANT_SWTABLE_B;
1916 /* Set antenna idle switch table */
1917 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1918 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1919 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1920 AR5K_PHY_ANT_CTL_TXRX_EN));
1922 /* Set antenna switch tables */
1923 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1924 AR5K_PHY_ANT_SWITCH_TABLE_0);
1925 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1926 AR5K_PHY_ANT_SWITCH_TABLE_1);
1930 * Set antenna operating mode
1933 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1935 struct ieee80211_channel *channel = ah->ah_current_channel;
1936 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1937 bool use_def_for_sg;
1938 u8 def_ant, tx_ant, ee_mode;
1941 /* if channel is not initialized yet we can't set the antennas
1942 * so just store the mode. it will be set on the next reset */
1943 if (channel == NULL) {
1944 ah->ah_ant_mode = ant_mode;
1948 def_ant = ah->ah_def_ant;
1950 switch (channel->hw_value & CHANNEL_MODES) {
1953 ee_mode = AR5K_EEPROM_MODE_11A;
1956 ee_mode = AR5K_EEPROM_MODE_11G;
1959 ee_mode = AR5K_EEPROM_MODE_11B;
1962 ATH5K_ERR(ah->ah_sc,
1963 "invalid channel: %d\n", channel->center_freq);
1968 case AR5K_ANTMODE_DEFAULT:
1970 use_def_for_tx = false;
1971 update_def_on_tx = false;
1972 use_def_for_rts = false;
1973 use_def_for_sg = false;
1976 case AR5K_ANTMODE_FIXED_A:
1979 use_def_for_tx = true;
1980 update_def_on_tx = false;
1981 use_def_for_rts = true;
1982 use_def_for_sg = true;
1985 case AR5K_ANTMODE_FIXED_B:
1988 use_def_for_tx = true;
1989 update_def_on_tx = false;
1990 use_def_for_rts = true;
1991 use_def_for_sg = true;
1994 case AR5K_ANTMODE_SINGLE_AP:
1995 def_ant = 1; /* updated on tx */
1997 use_def_for_tx = true;
1998 update_def_on_tx = true;
1999 use_def_for_rts = true;
2000 use_def_for_sg = true;
2003 case AR5K_ANTMODE_SECTOR_AP:
2004 tx_ant = 1; /* variable */
2005 use_def_for_tx = false;
2006 update_def_on_tx = false;
2007 use_def_for_rts = true;
2008 use_def_for_sg = false;
2011 case AR5K_ANTMODE_SECTOR_STA:
2012 tx_ant = 1; /* variable */
2013 use_def_for_tx = true;
2014 update_def_on_tx = false;
2015 use_def_for_rts = true;
2016 use_def_for_sg = false;
2019 case AR5K_ANTMODE_DEBUG:
2022 use_def_for_tx = false;
2023 update_def_on_tx = false;
2024 use_def_for_rts = false;
2025 use_def_for_sg = false;
2032 ah->ah_tx_ant = tx_ant;
2033 ah->ah_ant_mode = ant_mode;
2034 ah->ah_def_ant = def_ant;
2036 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2037 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2038 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2039 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2041 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2044 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2046 ath5k_hw_set_antenna_switch(ah, ee_mode);
2047 /* Note: set diversity before default antenna
2048 * because it won't work correctly */
2049 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2050 ath5k_hw_set_def_antenna(ah, def_ant);
2063 * Do linear interpolation between two given (x, y) points
2066 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2067 s16 y_left, s16 y_right)
2071 /* Avoid divide by zero and skip interpolation
2072 * if we have the same point */
2073 if ((x_left == x_right) || (y_left == y_right))
2077 * Since we use ints and not fps, we need to scale up in
2078 * order to get a sane ratio value (or else we 'll eg. get
2079 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2080 * to have some accuracy both for 0.5 and 0.25 steps.
2082 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
2084 /* Now scale down to be in range */
2085 result = y_left + (ratio * (target - x_left) / 100);
2091 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2093 * Since we have the top of the curve and we draw the line below
2094 * until we reach 1 (1 pcdac step) we need to know which point
2095 * (x value) that is so that we don't go below y axis and have negative
2096 * pcdac values when creating the curve, or fill the table with zeroes.
2099 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2100 const s16 *pwrL, const s16 *pwrR)
2103 s16 min_pwrL, min_pwrR;
2106 /* Some vendors write the same pcdac value twice !!! */
2107 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2108 return max(pwrL[0], pwrR[0]);
2110 if (pwrL[0] == pwrL[1])
2116 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2118 stepL[0], stepL[1]);
2124 if (pwrR[0] == pwrR[1])
2130 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2132 stepR[0], stepR[1]);
2138 /* Keep the right boundary so that it works for both curves */
2139 return max(min_pwrL, min_pwrR);
2143 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2144 * Power to PCDAC curve.
2146 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2147 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2148 * PCDAC/PDADC step for each curve is 64 but we can write more than
2149 * one curves on hw so we can go up to 128 (which is the max step we
2150 * can write on the final table).
2152 * We write y values (PCDAC/PDADC steps) on hw.
2155 ath5k_create_power_curve(s16 pmin, s16 pmax,
2156 const s16 *pwr, const u8 *vpd,
2158 u8 *vpd_table, u8 type)
2160 u8 idx[2] = { 0, 1 };
2167 /* We want the whole line, so adjust boundaries
2168 * to cover the entire power range. Note that
2169 * power values are already 0.25dB so no need
2170 * to multiply pwr_i by 2 */
2171 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2177 /* Find surrounding turning points (TPs)
2178 * and interpolate between them */
2179 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2180 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2182 /* We passed the right TP, move to the next set of TPs
2183 * if we pass the last TP, extrapolate above using the last
2184 * two TPs for ratio */
2185 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2190 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2191 pwr[idx[0]], pwr[idx[1]],
2192 vpd[idx[0]], vpd[idx[1]]);
2194 /* Increase by 0.5dB
2195 * (0.25 dB units) */
2201 * Get the surrounding per-channel power calibration piers
2202 * for a given frequency so that we can interpolate between
2203 * them and come up with an apropriate dataset for our current
2207 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2208 struct ieee80211_channel *channel,
2209 struct ath5k_chan_pcal_info **pcinfo_l,
2210 struct ath5k_chan_pcal_info **pcinfo_r)
2212 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2213 struct ath5k_chan_pcal_info *pcinfo;
2216 u32 target = channel->center_freq;
2221 if (!(channel->hw_value & CHANNEL_OFDM)) {
2222 pcinfo = ee->ee_pwr_cal_b;
2223 mode = AR5K_EEPROM_MODE_11B;
2224 } else if (channel->hw_value & CHANNEL_2GHZ) {
2225 pcinfo = ee->ee_pwr_cal_g;
2226 mode = AR5K_EEPROM_MODE_11G;
2228 pcinfo = ee->ee_pwr_cal_a;
2229 mode = AR5K_EEPROM_MODE_11A;
2231 max = ee->ee_n_piers[mode] - 1;
2233 /* Frequency is below our calibrated
2234 * range. Use the lowest power curve
2236 if (target < pcinfo[0].freq) {
2241 /* Frequency is above our calibrated
2242 * range. Use the highest power curve
2244 if (target > pcinfo[max].freq) {
2245 idx_l = idx_r = max;
2249 /* Frequency is inside our calibrated
2250 * channel range. Pick the surrounding
2251 * calibration piers so that we can
2253 for (i = 0; i <= max; i++) {
2255 /* Frequency matches one of our calibration
2256 * piers, no need to interpolate, just use
2257 * that calibration pier */
2258 if (pcinfo[i].freq == target) {
2263 /* We found a calibration pier that's above
2264 * frequency, use this pier and the previous
2265 * one to interpolate */
2266 if (target < pcinfo[i].freq) {
2274 *pcinfo_l = &pcinfo[idx_l];
2275 *pcinfo_r = &pcinfo[idx_r];
2279 * Get the surrounding per-rate power calibration data
2280 * for a given frequency and interpolate between power
2281 * values to set max target power supported by hw for
2285 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2286 struct ieee80211_channel *channel,
2287 struct ath5k_rate_pcal_info *rates)
2289 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2290 struct ath5k_rate_pcal_info *rpinfo;
2293 u32 target = channel->center_freq;
2298 if (!(channel->hw_value & CHANNEL_OFDM)) {
2299 rpinfo = ee->ee_rate_tpwr_b;
2300 mode = AR5K_EEPROM_MODE_11B;
2301 } else if (channel->hw_value & CHANNEL_2GHZ) {
2302 rpinfo = ee->ee_rate_tpwr_g;
2303 mode = AR5K_EEPROM_MODE_11G;
2305 rpinfo = ee->ee_rate_tpwr_a;
2306 mode = AR5K_EEPROM_MODE_11A;
2308 max = ee->ee_rate_target_pwr_num[mode] - 1;
2310 /* Get the surrounding calibration
2311 * piers - same as above */
2312 if (target < rpinfo[0].freq) {
2317 if (target > rpinfo[max].freq) {
2318 idx_l = idx_r = max;
2322 for (i = 0; i <= max; i++) {
2324 if (rpinfo[i].freq == target) {
2329 if (target < rpinfo[i].freq) {
2337 /* Now interpolate power value, based on the frequency */
2338 rates->freq = target;
2340 rates->target_power_6to24 =
2341 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2343 rpinfo[idx_l].target_power_6to24,
2344 rpinfo[idx_r].target_power_6to24);
2346 rates->target_power_36 =
2347 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2349 rpinfo[idx_l].target_power_36,
2350 rpinfo[idx_r].target_power_36);
2352 rates->target_power_48 =
2353 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2355 rpinfo[idx_l].target_power_48,
2356 rpinfo[idx_r].target_power_48);
2358 rates->target_power_54 =
2359 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2361 rpinfo[idx_l].target_power_54,
2362 rpinfo[idx_r].target_power_54);
2366 * Get the max edge power for this channel if
2367 * we have such data from EEPROM's Conformance Test
2368 * Limits (CTL), and limit max power if needed.
2371 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2372 struct ieee80211_channel *channel)
2374 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2375 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2376 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2377 u8 *ctl_val = ee->ee_ctl;
2378 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2383 u32 target = channel->center_freq;
2385 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2387 switch (channel->hw_value & CHANNEL_MODES) {
2389 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2390 ctl_mode |= AR5K_CTL_TURBO;
2392 ctl_mode |= AR5K_CTL_11A;
2395 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2396 ctl_mode |= AR5K_CTL_TURBOG;
2398 ctl_mode |= AR5K_CTL_11G;
2401 ctl_mode |= AR5K_CTL_11B;
2409 for (i = 0; i < ee->ee_ctls; i++) {
2410 if (ctl_val[i] == ctl_mode) {
2416 /* If we have a CTL dataset available grab it and find the
2417 * edge power for our frequency */
2418 if (ctl_idx == 0xFF)
2421 /* Edge powers are sorted by frequency from lower
2422 * to higher. Each CTL corresponds to 8 edge power
2424 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2426 /* Don't do boundaries check because we
2427 * might have more that one bands defined
2430 /* Get the edge power that's closer to our
2432 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2434 if (target <= rep[rep_idx].freq)
2435 edge_pwr = (s16) rep[rep_idx].edge;
2439 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2444 * Power to PCDAC table functions
2448 * Fill Power to PCDAC table on RF5111
2450 * No further processing is needed for RF5111, the only thing we have to
2451 * do is fill the values below and above calibration range since eeprom data
2452 * may not cover the entire PCDAC table.
2455 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2458 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2459 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2460 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2461 s16 min_pwr, max_pwr;
2463 /* Get table boundaries */
2464 min_pwr = table_min[0];
2465 pcdac_0 = pcdac_tmp[0];
2467 max_pwr = table_max[0];
2468 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2470 /* Extrapolate below minimum using pcdac_0 */
2472 for (i = 0; i < min_pwr; i++)
2473 pcdac_out[pcdac_i++] = pcdac_0;
2475 /* Copy values from pcdac_tmp */
2477 for (i = 0 ; pwr_idx <= max_pwr &&
2478 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2479 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2483 /* Extrapolate above maximum */
2484 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2485 pcdac_out[pcdac_i++] = pcdac_n;
2490 * Combine available XPD Curves and fill Linear Power to PCDAC table
2493 * RFX112 can have up to 2 curves (one for low txpower range and one for
2494 * higher txpower range). We need to put them both on pcdac_out and place
2495 * them in the correct location. In case we only have one curve available
2496 * just fit it on pcdac_out (it's supposed to cover the entire range of
2497 * available pwr levels since it's always the higher power curve). Extrapolate
2498 * below and above final table if needed.
2501 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2502 s16 *table_max, u8 pdcurves)
2504 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2511 s16 mid_pwr_idx = 0;
2512 /* Edge flag turs on the 7nth bit on the PCDAC
2513 * to delcare the higher power curve (force values
2514 * to be greater than 64). If we only have one curve
2515 * we don't need to set this, if we have 2 curves and
2516 * fill the table backwards this can also be used to
2517 * switch from higher power curve to lower power curve */
2521 /* When we have only one curve available
2522 * that's the higher power curve. If we have
2523 * two curves the first is the high power curve
2524 * and the next is the low power curve. */
2526 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2527 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2528 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2529 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2531 /* If table size goes beyond 31.5dB, keep the
2532 * upper 31.5dB range when setting tx power.
2533 * Note: 126 = 31.5 dB in quarter dB steps */
2534 if (table_max[0] - table_min[1] > 126)
2535 min_pwr_idx = table_max[0] - 126;
2537 min_pwr_idx = table_min[1];
2539 /* Since we fill table backwards
2540 * start from high power curve */
2541 pcdac_tmp = pcdac_high_pwr;
2545 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2546 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2547 min_pwr_idx = table_min[0];
2548 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2549 pcdac_tmp = pcdac_high_pwr;
2553 /* This is used when setting tx power*/
2554 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2556 /* Fill Power to PCDAC table backwards */
2558 for (i = 63; i >= 0; i--) {
2559 /* Entering lower power range, reset
2560 * edge flag and set pcdac_tmp to lower
2562 if (edge_flag == 0x40 &&
2563 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2565 pcdac_tmp = pcdac_low_pwr;
2566 pwr = mid_pwr_idx/2;
2569 /* Don't go below 1, extrapolate below if we have
2570 * already swithced to the lower power curve -or
2571 * we only have one curve and edge_flag is zero
2573 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2575 pcdac_out[i] = pcdac_out[i + 1];
2581 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2583 /* Extrapolate above if pcdac is greater than
2584 * 126 -this can happen because we OR pcdac_out
2585 * value with edge_flag on high power curve */
2586 if (pcdac_out[i] > 126)
2589 /* Decrease by a 0.5dB step */
2594 /* Write PCDAC values on hw */
2596 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2598 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2602 * Write TX power values
2604 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2605 ath5k_hw_reg_write(ah,
2606 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2607 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2608 AR5K_PHY_PCDAC_TXPOWER(i));
2614 * Power to PDADC table functions
2618 * Set the gain boundaries and create final Power to PDADC table
2620 * We can have up to 4 pd curves, we need to do a simmilar process
2621 * as we do for RF5112. This time we don't have an edge_flag but we
2622 * set the gain boundaries on a separate register.
2625 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2626 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2628 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2629 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2632 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2635 /* Note: Register value is initialized on initvals
2636 * there is no feedback from hw.
2637 * XXX: What about pd_gain_overlap from EEPROM ? */
2638 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2639 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2641 /* Create final PDADC table */
2642 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2643 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2645 if (pdg == pdcurves - 1)
2646 /* 2 dB boundary stretch for last
2647 * (higher power) curve */
2648 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2650 /* Set gain boundary in the middle
2651 * between this curve and the next one */
2652 gain_boundaries[pdg] =
2653 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2655 /* Sanity check in case our 2 db stretch got out of
2657 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2658 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2660 /* For the first curve (lower power)
2661 * start from 0 dB */
2665 /* For the other curves use the gain overlap */
2666 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2669 /* Force each power step to be at least 0.5 dB */
2670 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2671 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2675 /* If pdadc_0 is negative, we need to extrapolate
2676 * below this pdgain by a number of pwr_steps */
2677 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2678 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2679 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2683 /* Set last pwr level, using gain boundaries */
2684 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2685 /* Limit it to be inside pwr range */
2686 table_size = pwr_max[pdg] - pwr_min[pdg];
2687 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2689 /* Fill pdadc_out table */
2690 while (pdadc_0 < max_idx && pdadc_i < 128)
2691 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2693 /* Need to extrapolate above this pdgain? */
2694 if (pdadc_n <= max_idx)
2697 /* Force each power step to be at least 0.5 dB */
2698 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2699 pwr_step = pdadc_tmp[table_size - 1] -
2700 pdadc_tmp[table_size - 2];
2704 /* Extrapolate above */
2705 while ((pdadc_0 < (s16) pdadc_n) &&
2706 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2707 s16 tmp = pdadc_tmp[table_size - 1] +
2708 (pdadc_0 - max_idx) * pwr_step;
2709 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2714 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2715 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2719 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2720 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2724 /* Set gain boundaries */
2725 ath5k_hw_reg_write(ah,
2726 AR5K_REG_SM(pd_gain_overlap,
2727 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2728 AR5K_REG_SM(gain_boundaries[0],
2729 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2730 AR5K_REG_SM(gain_boundaries[1],
2731 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2732 AR5K_REG_SM(gain_boundaries[2],
2733 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2734 AR5K_REG_SM(gain_boundaries[3],
2735 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2738 /* Used for setting rate power table */
2739 ah->ah_txpower.txp_min_idx = pwr_min[0];
2743 /* Write PDADC values on hw */
2745 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2746 u8 pdcurves, u8 *pdg_to_idx)
2748 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2752 /* Select the right pdgain curves */
2754 /* Clear current settings */
2755 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2756 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2757 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2758 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2759 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2762 * Use pd_gains curve from eeprom
2764 * This overrides the default setting from initvals
2765 * in case some vendors (e.g. Zcomax) don't use the default
2766 * curves. If we don't honor their settings we 'll get a
2767 * 5dB (1 * gain overlap ?) drop.
2769 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2773 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2776 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2779 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2782 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2785 * Write TX power values
2787 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2788 ath5k_hw_reg_write(ah,
2789 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2790 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2791 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2792 ((pdadc_out[4*i + 3] & 0xff) << 24),
2793 AR5K_PHY_PDADC_TXPOWER(i));
2799 * Common code for PCDAC/PDADC tables
2803 * This is the main function that uses all of the above
2804 * to set PCDAC/PDADC table on hw for the current channel.
2805 * This table is used for tx power calibration on the basband,
2806 * without it we get weird tx power levels and in some cases
2807 * distorted spectral mask
2810 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2811 struct ieee80211_channel *channel,
2812 u8 ee_mode, u8 type)
2814 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2815 struct ath5k_chan_pcal_info *pcinfo_L;
2816 struct ath5k_chan_pcal_info *pcinfo_R;
2817 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2818 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2819 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2820 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2823 u32 target = channel->center_freq;
2826 /* Get surounding freq piers for this channel */
2827 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2831 /* Loop over pd gain curves on
2832 * surounding freq piers by index */
2833 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2835 /* Fill curves in reverse order
2836 * from lower power (max gain)
2837 * to higher power. Use curve -> idx
2838 * backmapping we did on eeprom init */
2839 u8 idx = pdg_curve_to_idx[pdg];
2841 /* Grab the needed curves by index */
2842 pdg_L = &pcinfo_L->pd_curves[idx];
2843 pdg_R = &pcinfo_R->pd_curves[idx];
2845 /* Initialize the temp tables */
2846 tmpL = ah->ah_txpower.tmpL[pdg];
2847 tmpR = ah->ah_txpower.tmpR[pdg];
2849 /* Set curve's x boundaries and create
2850 * curves so that they cover the same
2851 * range (if we don't do that one table
2852 * will have values on some range and the
2853 * other one won't have any so interpolation
2855 table_min[pdg] = min(pdg_L->pd_pwr[0],
2856 pdg_R->pd_pwr[0]) / 2;
2858 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2859 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2861 /* Now create the curves on surrounding channels
2862 * and interpolate if needed to get the final
2863 * curve for this gain on this channel */
2865 case AR5K_PWRTABLE_LINEAR_PCDAC:
2866 /* Override min/max so that we don't loose
2867 * accuracy (don't divide by 2) */
2868 table_min[pdg] = min(pdg_L->pd_pwr[0],
2872 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2873 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2875 /* Override minimum so that we don't get
2876 * out of bounds while extrapolating
2877 * below. Don't do this when we have 2
2878 * curves and we are on the high power curve
2879 * because table_min is ok in this case */
2880 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2883 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2888 /* Don't go too low because we will
2889 * miss the upper part of the curve.
2890 * Note: 126 = 31.5dB (max power supported)
2891 * in 0.25dB units */
2892 if (table_max[pdg] - table_min[pdg] > 126)
2893 table_min[pdg] = table_max[pdg] - 126;
2897 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2898 case AR5K_PWRTABLE_PWR_TO_PDADC:
2900 ath5k_create_power_curve(table_min[pdg],
2904 pdg_L->pd_points, tmpL, type);
2906 /* We are in a calibration
2907 * pier, no need to interpolate
2908 * between freq piers */
2909 if (pcinfo_L == pcinfo_R)
2912 ath5k_create_power_curve(table_min[pdg],
2916 pdg_R->pd_points, tmpR, type);
2922 /* Interpolate between curves
2923 * of surounding freq piers to
2924 * get the final curve for this
2925 * pd gain. Re-use tmpL for interpolation
2927 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2928 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2929 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2930 (s16) pcinfo_L->freq,
2931 (s16) pcinfo_R->freq,
2937 /* Now we have a set of curves for this
2938 * channel on tmpL (x range is table_max - table_min
2939 * and y values are tmpL[pdg][]) sorted in the same
2940 * order as EEPROM (because we've used the backmapping).
2941 * So for RF5112 it's from higher power to lower power
2942 * and for RF2413 it's from lower power to higher power.
2943 * For RF5111 we only have one curve. */
2945 /* Fill min and max power levels for this
2946 * channel by interpolating the values on
2947 * surounding channels to complete the dataset */
2948 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2949 (s16) pcinfo_L->freq,
2950 (s16) pcinfo_R->freq,
2951 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2953 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2954 (s16) pcinfo_L->freq,
2955 (s16) pcinfo_R->freq,
2956 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2958 /* We are ready to go, fill PCDAC/PDADC
2959 * table and write settings on hardware */
2961 case AR5K_PWRTABLE_LINEAR_PCDAC:
2962 /* For RF5112 we can have one or two curves
2963 * and each curve covers a certain power lvl
2964 * range so we need to do some more processing */
2965 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2966 ee->ee_pd_gains[ee_mode]);
2968 /* Set txp.offset so that we can
2969 * match max power value with max
2971 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2973 /* Write settings on hw */
2974 ath5k_setup_pcdac_table(ah);
2976 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2977 /* We are done for RF5111 since it has only
2978 * one curve, just fit the curve on the table */
2979 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2981 /* No rate powertable adjustment for RF5111 */
2982 ah->ah_txpower.txp_min_idx = 0;
2983 ah->ah_txpower.txp_offset = 0;
2985 /* Write settings on hw */
2986 ath5k_setup_pcdac_table(ah);
2988 case AR5K_PWRTABLE_PWR_TO_PDADC:
2989 /* Set PDADC boundaries and fill
2990 * final PDADC table */
2991 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2992 ee->ee_pd_gains[ee_mode]);
2994 /* Write settings on hw */
2995 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2997 /* Set txp.offset, note that table_min
2998 * can be negative */
2999 ah->ah_txpower.txp_offset = table_min[0];
3010 * Per-rate tx power setting
3012 * This is the code that sets the desired tx power (below
3013 * maximum) on hw for each rate (we also have TPC that sets
3014 * power per packet). We do that by providing an index on the
3015 * PCDAC/PDADC table we set up.
3019 * Set rate power table
3021 * For now we only limit txpower based on maximum tx power
3022 * supported by hw (what's inside rate_info). We need to limit
3023 * this even more, based on regulatory domain etc.
3025 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3026 * and is indexed as follows:
3027 * rates[0] - rates[7] -> OFDM rates
3028 * rates[8] - rates[14] -> CCK rates
3029 * rates[15] -> XR rates (they all have the same power)
3032 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3033 struct ath5k_rate_pcal_info *rate_info,
3039 /* max_pwr is power level we got from driver/user in 0.5dB
3040 * units, switch to 0.25dB units so we can compare */
3042 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3044 /* apply rate limits */
3045 rates = ah->ah_txpower.txp_rates_power_table;
3047 /* OFDM rates 6 to 24Mb/s */
3048 for (i = 0; i < 5; i++)
3049 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3051 /* Rest OFDM rates */
3052 rates[5] = min(rates[0], rate_info->target_power_36);
3053 rates[6] = min(rates[0], rate_info->target_power_48);
3054 rates[7] = min(rates[0], rate_info->target_power_54);
3058 rates[8] = min(rates[0], rate_info->target_power_6to24);
3060 rates[9] = min(rates[0], rate_info->target_power_36);
3062 rates[10] = min(rates[0], rate_info->target_power_36);
3064 rates[11] = min(rates[0], rate_info->target_power_48);
3066 rates[12] = min(rates[0], rate_info->target_power_48);
3068 rates[13] = min(rates[0], rate_info->target_power_54);
3070 rates[14] = min(rates[0], rate_info->target_power_54);
3073 rates[15] = min(rates[0], rate_info->target_power_6to24);
3075 /* CCK rates have different peak to average ratio
3076 * so we have to tweak their power so that gainf
3077 * correction works ok. For this we use OFDM to
3078 * CCK delta from eeprom */
3079 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3080 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3081 for (i = 8; i <= 15; i++)
3082 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3084 /* Now that we have all rates setup use table offset to
3085 * match the power range set by user with the power indices
3086 * on PCDAC/PDADC table */
3087 for (i = 0; i < 16; i++) {
3088 rates[i] += ah->ah_txpower.txp_offset;
3089 /* Don't get out of bounds */
3094 /* Min/max in 0.25dB units */
3095 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3096 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
3097 ah->ah_txpower.txp_ofdm = rates[7];
3102 * Set transmission power
3105 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3106 u8 ee_mode, u8 txpower, bool fast)
3108 struct ath5k_rate_pcal_info rate_info;
3112 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3113 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3117 /* Reset TX power values */
3118 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3119 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3120 ah->ah_txpower.txp_min_pwr = 0;
3121 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3123 /* Initialize TX power table */
3124 switch (ah->ah_radio) {
3129 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3132 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3139 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3145 /* If fast is set it means we are on the same channel/mode
3146 * so there is no need to recalculate the powertable, we 'll
3147 * just use the cached one */
3149 ret = ath5k_setup_channel_powertable(ah, channel,
3155 /* Limit max power if we have a CTL available */
3156 ath5k_get_max_ctl_power(ah, channel);
3158 /* FIXME: Antenna reduction stuff */
3160 /* FIXME: Limit power on turbo modes */
3162 /* FIXME: TPC scale reduction */
3164 /* Get surounding channels for per-rate power table
3166 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3168 /* Setup rate power table */
3169 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3171 /* Write rate power table on hw */
3172 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3173 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3174 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3176 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3177 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3178 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3180 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3181 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3182 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3184 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3185 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3186 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3188 /* FIXME: TPC support */
3189 if (ah->ah_txpower.txp_tpc) {
3190 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3191 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3193 ath5k_hw_reg_write(ah,
3194 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3195 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3196 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3199 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3200 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3206 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3209 struct ieee80211_channel *channel = ah->ah_current_channel;
3212 switch (channel->hw_value & CHANNEL_MODES) {
3215 ee_mode = AR5K_EEPROM_MODE_11A;
3218 ee_mode = AR5K_EEPROM_MODE_11G;
3221 ee_mode = AR5K_EEPROM_MODE_11B;
3224 ATH5K_ERR(ah->ah_sc,
3225 "invalid channel: %d\n", channel->center_freq);
3229 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3230 "changing txpower to %d\n", txpower);
3232 return ath5k_hw_txpower(ah, channel, ee_mode, txpower, true);
3239 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3240 u8 mode, u8 ee_mode, u8 freq, bool fast)
3242 struct ieee80211_channel *curr_channel;
3249 * Sanity check for fast flag
3250 * Don't try fast channel change when changing modulation
3251 * mode/band. We check for chip compatibility on
3254 curr_channel = ah->ah_current_channel;
3255 if (fast && (channel->hw_value != curr_channel->hw_value))
3259 * On fast channel change we only set the synth parameters
3260 * while PHY is running, enable calibration and skip the rest.
3263 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3264 AR5K_PHY_RFBUS_REQ_REQUEST);
3265 for (i = 0; i < 100; i++) {
3266 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3276 * If we don't change channel/mode skip
3277 * tx powertable calculation and use the
3280 if ((channel->hw_value == curr_channel->hw_value) &&
3281 (channel->center_freq == curr_channel->center_freq))
3289 * Note: We need to do that before we set
3290 * RF buffer settings on 5211/5212+ so that we
3291 * properly set curve indices.
3293 ret = ath5k_hw_txpower(ah, channel, ee_mode,
3294 ah->ah_txpower.txp_max_pwr / 2,
3300 * For 5210 we do all initialization using
3301 * initvals, so we don't have to modify
3302 * any settings (5210 also only supports
3305 if ((ah->ah_version != AR5K_AR5210) && !fast) {
3308 * Write initial RF gain settings
3309 * This should work for both 5111/5112
3311 ret = ath5k_hw_rfgain_init(ah, freq);
3320 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3324 /* Write OFDM timings on 5212*/
3325 if (ah->ah_version == AR5K_AR5212 &&
3326 channel->hw_value & CHANNEL_OFDM) {
3328 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3332 /* Spur info is available only from EEPROM versions
3333 * greater than 5.3, but the EEPROM routines will use
3334 * static values for older versions */
3335 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3336 ath5k_hw_set_spur_mitigation_filter(ah,
3340 /*Enable/disable 802.11b mode on 5111
3341 (enable 2111 frequency converter + CCK)*/
3342 if (ah->ah_radio == AR5K_RF5111) {
3343 if (mode == AR5K_MODE_11B)
3344 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3347 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3351 } else if (ah->ah_version == AR5K_AR5210) {
3353 /* Disable phy and wait */
3354 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3358 /* Set channel on PHY */
3359 ret = ath5k_hw_channel(ah, channel);
3364 * Enable the PHY and wait until completion
3365 * This includes BaseBand and Synthesizer
3368 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3371 * On 5211+ read activation -> rx delay
3374 if (ah->ah_version != AR5K_AR5210) {
3376 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
3377 AR5K_PHY_RX_DELAY_M;
3378 delay = (channel->hw_value & CHANNEL_CCK) ?
3379 ((delay << 2) / 22) : (delay / 10);
3380 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
3382 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
3384 /* XXX: /2 on turbo ? Let's be safe
3386 udelay(100 + delay);
3393 * Release RF Bus grant
3395 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3396 AR5K_PHY_RFBUS_REQ_REQUEST);
3399 * Perform ADC test to see if baseband is ready
3400 * Set tx hold and check adc test register
3402 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3403 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3404 for (i = 0; i <= 20; i++) {
3405 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3409 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3413 * Start automatic gain control calibration
3415 * During AGC calibration RX path is re-routed to
3416 * a power detector so we don't receive anything.
3418 * This method is used to calibrate some static offsets
3419 * used together with on-the fly I/Q calibration (the
3420 * one performed via ath5k_hw_phy_calibrate), which doesn't
3421 * interrupt rx path.
3423 * While rx path is re-routed to the power detector we also
3424 * start a noise floor calibration to measure the
3425 * card's noise floor (the noise we measure when we are not
3426 * transmitting or receiving anything).
3428 * If we are in a noisy environment, AGC calibration may time
3429 * out and/or noise floor calibration might timeout.
3431 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3432 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3434 /* At the same time start I/Q calibration for QAM constellation
3435 * -no need for CCK- */
3436 ah->ah_calibration = false;
3437 if (!(mode == AR5K_MODE_11B)) {
3438 ah->ah_calibration = true;
3439 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3440 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3441 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3445 /* Wait for gain calibration to finish (we check for I/Q calibration
3446 * during ath5k_phy_calibrate) */
3447 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3448 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3449 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
3450 channel->center_freq);
3453 /* Restore antenna mode */
3454 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);