drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC
  51 #include <asm/idprom.h>
  52 #include <asm/prom.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.75"
  68 #define DRV_MODULE_RELDATE      "March 23, 2007"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 208         {}
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 212
 213 static const struct {
 214         const char string[ETH_GSTRING_LEN];
 215 } ethtool_stats_keys[TG3_NUM_STATS] = {
 216         { "rx_octets" },
 217         { "rx_fragments" },
 218         { "rx_ucast_packets" },
 219         { "rx_mcast_packets" },
 220         { "rx_bcast_packets" },
 221         { "rx_fcs_errors" },
 222         { "rx_align_errors" },
 223         { "rx_xon_pause_rcvd" },
 224         { "rx_xoff_pause_rcvd" },
 225         { "rx_mac_ctrl_rcvd" },
 226         { "rx_xoff_entered" },
 227         { "rx_frame_too_long_errors" },
 228         { "rx_jabbers" },
 229         { "rx_undersize_packets" },
 230         { "rx_in_length_errors" },
 231         { "rx_out_length_errors" },
 232         { "rx_64_or_less_octet_packets" },
 233         { "rx_65_to_127_octet_packets" },
 234         { "rx_128_to_255_octet_packets" },
 235         { "rx_256_to_511_octet_packets" },
 236         { "rx_512_to_1023_octet_packets" },
 237         { "rx_1024_to_1522_octet_packets" },
 238         { "rx_1523_to_2047_octet_packets" },
 239         { "rx_2048_to_4095_octet_packets" },
 240         { "rx_4096_to_8191_octet_packets" },
 241         { "rx_8192_to_9022_octet_packets" },
 242
 243         { "tx_octets" },
 244         { "tx_collisions" },
 245
 246         { "tx_xon_sent" },
 247         { "tx_xoff_sent" },
 248         { "tx_flow_control" },
 249         { "tx_mac_errors" },
 250         { "tx_single_collisions" },
 251         { "tx_mult_collisions" },
 252         { "tx_deferred" },
 253         { "tx_excessive_collisions" },
 254         { "tx_late_collisions" },
 255         { "tx_collide_2times" },
 256         { "tx_collide_3times" },
 257         { "tx_collide_4times" },
 258         { "tx_collide_5times" },
 259         { "tx_collide_6times" },
 260         { "tx_collide_7times" },
 261         { "tx_collide_8times" },
 262         { "tx_collide_9times" },
 263         { "tx_collide_10times" },
 264         { "tx_collide_11times" },
 265         { "tx_collide_12times" },
 266         { "tx_collide_13times" },
 267         { "tx_collide_14times" },
 268         { "tx_collide_15times" },
 269         { "tx_ucast_packets" },
 270         { "tx_mcast_packets" },
 271         { "tx_bcast_packets" },
 272         { "tx_carrier_sense_errors" },
 273         { "tx_discards" },
 274         { "tx_errors" },
 275
 276         { "dma_writeq_full" },
 277         { "dma_write_prioq_full" },
 278         { "rxbds_empty" },
 279         { "rx_discards" },
 280         { "rx_errors" },
 281         { "rx_threshold_hit" },
 282
 283         { "dma_readq_full" },
 284         { "dma_read_prioq_full" },
 285         { "tx_comp_queue_full" },
 286
 287         { "ring_set_send_prod_index" },
 288         { "ring_status_update" },
 289         { "nic_irqs" },
 290         { "nic_avoided_irqs" },
 291         { "nic_tx_threshold_hit" }
 292 };
 293
 294 static const struct {
 295         const char string[ETH_GSTRING_LEN];
 296 } ethtool_test_keys[TG3_NUM_TEST] = {
 297         { "nvram test     (online) " },
 298         { "link test      (online) " },
 299         { "register test  (offline)" },
 300         { "memory test    (offline)" },
 301         { "loopback test  (offline)" },
 302         { "interrupt test (offline)" },
 303 };
 304
 305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 306 {
 307         writel(val, tp->regs + off);
 308 }
 309
 310 static u32 tg3_read32(struct tg3 *tp, u32 off)
 311 {
 312         return (readl(tp->regs + off));
 313 }
 314
 315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 316 {
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&tp->indirect_lock, flags);
 320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 323 }
 324
 325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 326 {
 327         writel(val, tp->regs + off);
 328         readl(tp->regs + off);
 329 }
 330
 331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 332 {
 333         unsigned long flags;
 334         u32 val;
 335
 336         spin_lock_irqsave(&tp->indirect_lock, flags);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 340         return val;
 341 }
 342
 343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         unsigned long flags;
 346
 347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 349                                        TG3_64BIT_REG_LOW, val);
 350                 return;
 351         }
 352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 354                                        TG3_64BIT_REG_LOW, val);
 355                 return;
 356         }
 357
 358         spin_lock_irqsave(&tp->indirect_lock, flags);
 359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 362
 363         /* In indirect mode when disabling interrupts, we also need
 364          * to clear the interrupt bit in the GRC local ctrl register.
 365          */
 366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 367             (val == 0x1)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 370         }
 371 }
 372
 373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 374 {
 375         unsigned long flags;
 376         u32 val;
 377
 378         spin_lock_irqsave(&tp->indirect_lock, flags);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 382         return val;
 383 }
 384
 385 /* usec_wait specifies the wait time in usec when writing to certain registers
 386  * where it is unsafe to read back the register without some delay.
 387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 389  */
 390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 391 {
 392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 394                 /* Non-posted methods */
 395                 tp->write32(tp, off, val);
 396         else {
 397                 /* Posted method */
 398                 tg3_write32(tp, off, val);
 399                 if (usec_wait)
 400                         udelay(usec_wait);
 401                 tp->read32(tp, off);
 402         }
 403         /* Wait again after the read for the posted method to guarantee that
 404          * the wait time is met.
 405          */
 406         if (usec_wait)
 407                 udelay(usec_wait);
 408 }
 409
 410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         tp->write32_mbox(tp, off, val);
 413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32_mbox(tp, off);
 416 }
 417
 418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         void __iomem *mbox = tp->regs + off;
 421         writel(val, mbox);
 422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 423                 writel(val, mbox);
 424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 425                 readl(mbox);
 426 }
 427
 428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 429 {
 430         return (readl(tp->regs + off + GRCMBOX_BASE));
 431 }
 432
 433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         writel(val, tp->regs + off + GRCMBOX_BASE);
 436 }
 437
 438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 443
 444 #define tw32(reg,val)           tp->write32(tp, reg, val)
 445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 447 #define tr32(reg)               tp->read32(tp, reg)
 448
 449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         unsigned long flags;
 452
 453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 455                 return;
 456
 457         spin_lock_irqsave(&tp->indirect_lock, flags);
 458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 461
 462                 /* Always leave this as zero. */
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 464         } else {
 465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 467
 468                 /* Always leave this as zero. */
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 470         }
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 475 {
 476         unsigned long flags;
 477
 478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 480                 *val = 0;
 481                 return;
 482         }
 483
 484         spin_lock_irqsave(&tp->indirect_lock, flags);
 485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 488
 489                 /* Always leave this as zero. */
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 491         } else {
 492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 494
 495                 /* Always leave this as zero. */
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 497         }
 498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 499 }
 500
 501 static void tg3_disable_ints(struct tg3 *tp)
 502 {
 503         tw32(TG3PCI_MISC_HOST_CTRL,
 504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 506 }
 507
 508 static inline void tg3_cond_int(struct tg3 *tp)
 509 {
 510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 511             (tp->hw_status->status & SD_STATUS_UPDATED))
 512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 513         else
 514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 516 }
 517
 518 static void tg3_enable_ints(struct tg3 *tp)
 519 {
 520         tp->irq_sync = 0;
 521         wmb();
 522
 523         tw32(TG3PCI_MISC_HOST_CTRL,
 524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 526                        (tp->last_tag << 24));
 527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                                (tp->last_tag << 24));
 530         tg3_cond_int(tp);
 531 }
 532
 533 static inline unsigned int tg3_has_work(struct tg3 *tp)
 534 {
 535         struct tg3_hw_status *sblk = tp->hw_status;
 536         unsigned int work_exists = 0;
 537
 538         /* check for phy events */
 539         if (!(tp->tg3_flags &
 540               (TG3_FLAG_USE_LINKCHG_REG |
 541                TG3_FLAG_POLL_SERDES))) {
 542                 if (sblk->status & SD_STATUS_LINK_CHG)
 543                         work_exists = 1;
 544         }
 545         /* check for RX/TX work to do */
 546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 548                 work_exists = 1;
 549
 550         return work_exists;
 551 }
 552
 553 /* tg3_restart_ints
 554  *  similar to tg3_enable_ints, but it accurately determines whether there
 555  *  is new work pending and can return without flushing the PIO write
 556  *  which reenables interrupts
 557  */
 558 static void tg3_restart_ints(struct tg3 *tp)
 559 {
 560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                      tp->last_tag << 24);
 562         mmiowb();
 563
 564         /* When doing tagged status, this work check is unnecessary.
 565          * The last_tag we write above tells the chip which piece of
 566          * work we've completed.
 567          */
 568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 569             tg3_has_work(tp))
 570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 572 }
 573
 574 static inline void tg3_netif_stop(struct tg3 *tp)
 575 {
 576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 577         netif_poll_disable(tp->dev);
 578         netif_tx_disable(tp->dev);
 579 }
 580
 581 static inline void tg3_netif_start(struct tg3 *tp)
 582 {
 583         netif_wake_queue(tp->dev);
 584         /* NOTE: unconditional netif_wake_queue is only appropriate
 585          * so long as all callers are assured to have free tx slots
 586          * (such as after tg3_init_hw)
 587          */
 588         netif_poll_enable(tp->dev);
 589         tp->hw_status->status |= SD_STATUS_UPDATED;
 590         tg3_enable_ints(tp);
 591 }
 592
 593 static void tg3_switch_clocks(struct tg3 *tp)
 594 {
 595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 596         u32 orig_clock_ctrl;
 597
 598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 599                 return;
 600
 601         orig_clock_ctrl = clock_ctrl;
 602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 603                        CLOCK_CTRL_CLKRUN_OENABLE |
 604                        0x1f);
 605         tp->pci_clock_ctrl = clock_ctrl;
 606
 607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 611                 }
 612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                             clock_ctrl |
 615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 616                             40);
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 619                             40);
 620         }
 621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 622 }
 623
 624 #define PHY_BUSY_LOOPS  5000
 625
 626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 627 {
 628         u32 frame_val;
 629         unsigned int loops;
 630         int ret;
 631
 632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 633                 tw32_f(MAC_MI_MODE,
 634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 635                 udelay(80);
 636         }
 637
 638         *val = 0x0;
 639
 640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 641                       MI_COM_PHY_ADDR_MASK);
 642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 643                       MI_COM_REG_ADDR_MASK);
 644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 645
 646         tw32_f(MAC_MI_COM, frame_val);
 647
 648         loops = PHY_BUSY_LOOPS;
 649         while (loops != 0) {
 650                 udelay(10);
 651                 frame_val = tr32(MAC_MI_COM);
 652
 653                 if ((frame_val & MI_COM_BUSY) == 0) {
 654                         udelay(5);
 655                         frame_val = tr32(MAC_MI_COM);
 656                         break;
 657                 }
 658                 loops -= 1;
 659         }
 660
 661         ret = -EBUSY;
 662         if (loops != 0) {
 663                 *val = frame_val & MI_COM_DATA_MASK;
 664                 ret = 0;
 665         }
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 669                 udelay(80);
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 676 {
 677         u32 frame_val;
 678         unsigned int loops;
 679         int ret;
 680
 681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 683                 return 0;
 684
 685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 686                 tw32_f(MAC_MI_MODE,
 687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 688                 udelay(80);
 689         }
 690
 691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 692                       MI_COM_PHY_ADDR_MASK);
 693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 694                       MI_COM_REG_ADDR_MASK);
 695         frame_val |= (val & MI_COM_DATA_MASK);
 696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 697
 698         tw32_f(MAC_MI_COM, frame_val);
 699
 700         loops = PHY_BUSY_LOOPS;
 701         while (loops != 0) {
 702                 udelay(10);
 703                 frame_val = tr32(MAC_MI_COM);
 704                 if ((frame_val & MI_COM_BUSY) == 0) {
 705                         udelay(5);
 706                         frame_val = tr32(MAC_MI_COM);
 707                         break;
 708                 }
 709                 loops -= 1;
 710         }
 711
 712         ret = -EBUSY;
 713         if (loops != 0)
 714                 ret = 0;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 718                 udelay(80);
 719         }
 720
 721         return ret;
 722 }
 723
 724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 725 {
 726         u32 val;
 727
 728         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 729                 return;
 730
 731         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 732             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 733                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 734                              (val | (1 << 15) | (1 << 4)));
 735 }
 736
 737 static int tg3_bmcr_reset(struct tg3 *tp)
 738 {
 739         u32 phy_control;
 740         int limit, err;
 741
 742         /* OK, reset it, and poll the BMCR_RESET bit until it
 743          * clears or we time out.
 744          */
 745         phy_control = BMCR_RESET;
 746         err = tg3_writephy(tp, MII_BMCR, phy_control);
 747         if (err != 0)
 748                 return -EBUSY;
 749
 750         limit = 5000;
 751         while (limit--) {
 752                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 753                 if (err != 0)
 754                         return -EBUSY;
 755
 756                 if ((phy_control & BMCR_RESET) == 0) {
 757                         udelay(40);
 758                         break;
 759                 }
 760                 udelay(10);
 761         }
 762         if (limit <= 0)
 763                 return -EBUSY;
 764
 765         return 0;
 766 }
 767
 768 static int tg3_wait_macro_done(struct tg3 *tp)
 769 {
 770         int limit = 100;
 771
 772         while (limit--) {
 773                 u32 tmp32;
 774
 775                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 776                         if ((tmp32 & 0x1000) == 0)
 777                                 break;
 778                 }
 779         }
 780         if (limit <= 0)
 781                 return -EBUSY;
 782
 783         return 0;
 784 }
 785
 786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 787 {
 788         static const u32 test_pat[4][6] = {
 789         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 790         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 791         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 792         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 793         };
 794         int chan;
 795
 796         for (chan = 0; chan < 4; chan++) {
 797                 int i;
 798
 799                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 800                              (chan * 0x2000) | 0x0200);
 801                 tg3_writephy(tp, 0x16, 0x0002);
 802
 803                 for (i = 0; i < 6; i++)
 804                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 805                                      test_pat[chan][i]);
 806
 807                 tg3_writephy(tp, 0x16, 0x0202);
 808                 if (tg3_wait_macro_done(tp)) {
 809                         *resetp = 1;
 810                         return -EBUSY;
 811                 }
 812
 813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 814                              (chan * 0x2000) | 0x0200);
 815                 tg3_writephy(tp, 0x16, 0x0082);
 816                 if (tg3_wait_macro_done(tp)) {
 817                         *resetp = 1;
 818                         return -EBUSY;
 819                 }
 820
 821                 tg3_writephy(tp, 0x16, 0x0802);
 822                 if (tg3_wait_macro_done(tp)) {
 823                         *resetp = 1;
 824                         return -EBUSY;
 825                 }
 826
 827                 for (i = 0; i < 6; i += 2) {
 828                         u32 low, high;
 829
 830                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 831                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 832                             tg3_wait_macro_done(tp)) {
 833                                 *resetp = 1;
 834                                 return -EBUSY;
 835                         }
 836                         low &= 0x7fff;
 837                         high &= 0x000f;
 838                         if (low != test_pat[chan][i] ||
 839                             high != test_pat[chan][i+1]) {
 840                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 841                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 843
 844                                 return -EBUSY;
 845                         }
 846                 }
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 853 {
 854         int chan;
 855
 856         for (chan = 0; chan < 4; chan++) {
 857                 int i;
 858
 859                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 860                              (chan * 0x2000) | 0x0200);
 861                 tg3_writephy(tp, 0x16, 0x0002);
 862                 for (i = 0; i < 6; i++)
 863                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 864                 tg3_writephy(tp, 0x16, 0x0202);
 865                 if (tg3_wait_macro_done(tp))
 866                         return -EBUSY;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 873 {
 874         u32 reg32, phy9_orig;
 875         int retries, do_phy_reset, err;
 876
 877         retries = 10;
 878         do_phy_reset = 1;
 879         do {
 880                 if (do_phy_reset) {
 881                         err = tg3_bmcr_reset(tp);
 882                         if (err)
 883                                 return err;
 884                         do_phy_reset = 0;
 885                 }
 886
 887                 /* Disable transmitter and interrupt.  */
 888                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 889                         continue;
 890
 891                 reg32 |= 0x3000;
 892                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 893
 894                 /* Set full-duplex, 1000 mbps.  */
 895                 tg3_writephy(tp, MII_BMCR,
 896                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 897
 898                 /* Set to master mode.  */
 899                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 900                         continue;
 901
 902                 tg3_writephy(tp, MII_TG3_CTRL,
 903                              (MII_TG3_CTRL_AS_MASTER |
 904                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 905
 906                 /* Enable SM_DSP_CLOCK and 6dB.  */
 907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 908
 909                 /* Block the PHY control access.  */
 910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 912
 913                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 914                 if (!err)
 915                         break;
 916         } while (--retries);
 917
 918         err = tg3_phy_reset_chanpat(tp);
 919         if (err)
 920                 return err;
 921
 922         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 923         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 924
 925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 926         tg3_writephy(tp, 0x16, 0x0000);
 927
 928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 930                 /* Set Extended packet length bit for jumbo frames */
 931                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 932         }
 933         else {
 934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 935         }
 936
 937         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 938
 939         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 940                 reg32 &= ~0x3000;
 941                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 942         } else if (!err)
 943                 err = -EBUSY;
 944
 945         return err;
 946 }
 947
 948 static void tg3_link_report(struct tg3 *);
 949
 950 /* This will reset the tigon3 PHY if there is no valid
 951  * link unless the FORCE argument is non-zero.
 952  */
 953 static int tg3_phy_reset(struct tg3 *tp)
 954 {
 955         u32 phy_status;
 956         int err;
 957
 958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 959                 u32 val;
 960
 961                 val = tr32(GRC_MISC_CFG);
 962                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 963                 udelay(40);
 964         }
 965         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 966         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 967         if (err != 0)
 968                 return -EBUSY;
 969
 970         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 971                 netif_carrier_off(tp->dev);
 972                 tg3_link_report(tp);
 973         }
 974
 975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 978                 err = tg3_phy_reset_5703_4_5(tp);
 979                 if (err)
 980                         return err;
 981                 goto out;
 982         }
 983
 984         err = tg3_bmcr_reset(tp);
 985         if (err)
 986                 return err;
 987
 988 out:
 989         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 990                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 991                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 992                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 993                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 994                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 996         }
 997         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 998                 tg3_writephy(tp, 0x1c, 0x8d68);
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000         }
1001         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010         }
1011         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016                         tg3_writephy(tp, MII_TG3_TEST1,
1017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1018                 } else
1019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021         }
1022         /* Set Extended packet length bit (bit 14) on all chips that */
1023         /* support jumbo frames */
1024         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025                 /* Cannot do read-modify-write on 5401 */
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028                 u32 phy_reg;
1029
1030                 /* Set bit 14 with read-modify-write to preserve other bits */
1031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034         }
1035
1036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037          * jumbo frames transmission.
1038          */
1039         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040                 u32 phy_reg;
1041
1042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045         }
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048                 u32 phy_reg;
1049
1050                 /* adjust output voltage */
1051                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054                         u32 phy_reg2;
1055
1056                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058                         /* Enable auto-MDIX */
1059                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062                 }
1063         }
1064
1065         tg3_phy_set_wirespeed(tp);
1066         return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071         struct tg3 *tp_peer = tp;
1072
1073         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074                 return;
1075
1076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078                 struct net_device *dev_peer;
1079
1080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081                 /* remove_one() may have been run on the peer. */
1082                 if (!dev_peer)
1083                         tp_peer = tp;
1084                 else
1085                         tp_peer = netdev_priv(dev_peer);
1086         }
1087
1088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                                     (GRC_LCLCTRL_GPIO_OE0 |
1096                                      GRC_LCLCTRL_GPIO_OE1 |
1097                                      GRC_LCLCTRL_GPIO_OE2 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1100                                     100);
1101                 } else {
1102                         u32 no_gpio2;
1103                         u32 grc_local_ctrl = 0;
1104
1105                         if (tp_peer != tp &&
1106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107                                 return;
1108
1109                         /* Workaround to prevent overdrawing Amps. */
1110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111                             ASIC_REV_5714) {
1112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114                                             grc_local_ctrl, 100);
1115                         }
1116
1117                         /* On 5753 and variants, GPIO2 cannot be used. */
1118                         no_gpio2 = tp->nic_sram_data_cfg &
1119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122                                          GRC_LCLCTRL_GPIO_OE1 |
1123                                          GRC_LCLCTRL_GPIO_OE2 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1126                         if (no_gpio2) {
1127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1129                         }
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                                     grc_local_ctrl, 100);
1132
1133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136                                                     grc_local_ctrl, 100);
1137
1138                         if (!no_gpio2) {
1139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141                                             grc_local_ctrl, 100);
1142                         }
1143                 }
1144         } else {
1145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147                         if (tp_peer != tp &&
1148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149                                 return;
1150
1151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152                                     (GRC_LCLCTRL_GPIO_OE1 |
1153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156                                     GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159                                     (GRC_LCLCTRL_GPIO_OE1 |
1160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161                 }
1162         }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN     0
1168 #define RESET_KIND_INIT         1
1169 #define RESET_KIND_SUSPEND      2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183                         sg_dig_ctrl |=
1184                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187                 }
1188                 return;
1189         }
1190
1191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192                 u32 val;
1193
1194                 tg3_bmcr_reset(tp);
1195                 val = tr32(GRC_MISC_CFG);
1196                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197                 udelay(40);
1198                 return;
1199         } else {
1200                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203         }
1204
1205         /* The PHY should not be powered down on some chips because
1206          * of bugs.
1207          */
1208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212                 return;
1213         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218         u32 misc_host_ctrl;
1219         u16 power_control, power_caps;
1220         int pm = tp->pm_cap;
1221
1222         /* Make sure register accesses (indirect or otherwise)
1223          * will function correctly.
1224          */
1225         pci_write_config_dword(tp->pdev,
1226                                TG3PCI_MISC_HOST_CTRL,
1227                                tp->misc_host_ctrl);
1228
1229         pci_read_config_word(tp->pdev,
1230                              pm + PCI_PM_CTRL,
1231                              &power_control);
1232         power_control |= PCI_PM_CTRL_PME_STATUS;
1233         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234         switch (state) {
1235         case PCI_D0:
1236                 power_control |= 0;
1237                 pci_write_config_word(tp->pdev,
1238                                       pm + PCI_PM_CTRL,
1239                                       power_control);
1240                 udelay(100);    /* Delay after power state change */
1241
1242                 /* Switch out of Vaux if it is a NIC */
1243                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246                 return 0;
1247
1248         case PCI_D1:
1249                 power_control |= 1;
1250                 break;
1251
1252         case PCI_D2:
1253                 power_control |= 2;
1254                 break;
1255
1256         case PCI_D3hot:
1257                 power_control |= 3;
1258                 break;
1259
1260         default:
1261                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262                        "requested.\n",
1263                        tp->dev->name, state);
1264                 return -EINVAL;
1265         };
1266
1267         power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270         tw32(TG3PCI_MISC_HOST_CTRL,
1271              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273         if (tp->link_config.phy_is_low_power == 0) {
1274                 tp->link_config.phy_is_low_power = 1;
1275                 tp->link_config.orig_speed = tp->link_config.speed;
1276                 tp->link_config.orig_duplex = tp->link_config.duplex;
1277                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278         }
1279
1280         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281                 tp->link_config.speed = SPEED_10;
1282                 tp->link_config.duplex = DUPLEX_HALF;
1283                 tp->link_config.autoneg = AUTONEG_ENABLE;
1284                 tg3_setup_phy(tp, 0);
1285         }
1286
1287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288                 u32 val;
1289
1290                 val = tr32(GRC_VCPU_EXT_CTRL);
1291                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293                 int i;
1294                 u32 val;
1295
1296                 for (i = 0; i < 200; i++) {
1297                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299                                 break;
1300                         msleep(1);
1301                 }
1302         }
1303         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1304                                              WOL_DRV_STATE_SHUTDOWN |
1305                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1306
1307         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1308
1309         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1310                 u32 mac_mode;
1311
1312                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1313                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1314                         udelay(40);
1315
1316                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1317                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1318                         else
1319                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1320
1321                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1322                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1323                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1324                 } else {
1325                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1326                 }
1327
1328                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1329                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1330
1331                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1332                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1333                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1334
1335                 tw32_f(MAC_MODE, mac_mode);
1336                 udelay(100);
1337
1338                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1339                 udelay(10);
1340         }
1341
1342         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1343             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1344              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1345                 u32 base_val;
1346
1347                 base_val = tp->pci_clock_ctrl;
1348                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1349                              CLOCK_CTRL_TXCLK_DISABLE);
1350
1351                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1352                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1353         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1354                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1355                 /* do nothing */
1356         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1357                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1358                 u32 newbits1, newbits2;
1359
1360                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1361                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1362                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1363                                     CLOCK_CTRL_TXCLK_DISABLE |
1364                                     CLOCK_CTRL_ALTCLK);
1365                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1366                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1367                         newbits1 = CLOCK_CTRL_625_CORE;
1368                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1369                 } else {
1370                         newbits1 = CLOCK_CTRL_ALTCLK;
1371                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1372                 }
1373
1374                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1375                             40);
1376
1377                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1378                             40);
1379
1380                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1381                         u32 newbits3;
1382
1383                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1384                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1385                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1386                                             CLOCK_CTRL_TXCLK_DISABLE |
1387                                             CLOCK_CTRL_44MHZ_CORE);
1388                         } else {
1389                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1390                         }
1391
1392                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1393                                     tp->pci_clock_ctrl | newbits3, 40);
1394                 }
1395         }
1396
1397         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1398             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1399                 tg3_power_down_phy(tp);
1400
1401         tg3_frob_aux_power(tp);
1402
1403         /* Workaround for unstable PLL clock */
1404         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1405             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1406                 u32 val = tr32(0x7d00);
1407
1408                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1409                 tw32(0x7d00, val);
1410                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1411                         int err;
1412
1413                         err = tg3_nvram_lock(tp);
1414                         tg3_halt_cpu(tp, RX_CPU_BASE);
1415                         if (!err)
1416                                 tg3_nvram_unlock(tp);
1417                 }
1418         }
1419
1420         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1421
1422         /* Finally, set the new power state. */
1423         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1424         udelay(100);    /* Delay after power state change */
1425
1426         return 0;
1427 }
1428
1429 static void tg3_link_report(struct tg3 *tp)
1430 {
1431         if (!netif_carrier_ok(tp->dev)) {
1432                 if (netif_msg_link(tp))
1433                         printk(KERN_INFO PFX "%s: Link is down.\n",
1434                                tp->dev->name);
1435         } else if (netif_msg_link(tp)) {
1436                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1437                        tp->dev->name,
1438                        (tp->link_config.active_speed == SPEED_1000 ?
1439                         1000 :
1440                         (tp->link_config.active_speed == SPEED_100 ?
1441                          100 : 10)),
1442                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1443                         "full" : "half"));
1444
1445                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1446                        "%s for RX.\n",
1447                        tp->dev->name,
1448                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1449                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1450         }
1451 }
1452
1453 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1454 {
1455         u32 new_tg3_flags = 0;
1456         u32 old_rx_mode = tp->rx_mode;
1457         u32 old_tx_mode = tp->tx_mode;
1458
1459         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1460
1461                 /* Convert 1000BaseX flow control bits to 1000BaseT
1462                  * bits before resolving flow control.
1463                  */
1464                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1465                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1466                                        ADVERTISE_PAUSE_ASYM);
1467                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1468
1469                         if (local_adv & ADVERTISE_1000XPAUSE)
1470                                 local_adv |= ADVERTISE_PAUSE_CAP;
1471                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1472                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1473                         if (remote_adv & LPA_1000XPAUSE)
1474                                 remote_adv |= LPA_PAUSE_CAP;
1475                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1476                                 remote_adv |= LPA_PAUSE_ASYM;
1477                 }
1478
1479                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1480                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1481                                 if (remote_adv & LPA_PAUSE_CAP)
1482                                         new_tg3_flags |=
1483                                                 (TG3_FLAG_RX_PAUSE |
1484                                                 TG3_FLAG_TX_PAUSE);
1485                                 else if (remote_adv & LPA_PAUSE_ASYM)
1486                                         new_tg3_flags |=
1487                                                 (TG3_FLAG_RX_PAUSE);
1488                         } else {
1489                                 if (remote_adv & LPA_PAUSE_CAP)
1490                                         new_tg3_flags |=
1491                                                 (TG3_FLAG_RX_PAUSE |
1492                                                 TG3_FLAG_TX_PAUSE);
1493                         }
1494                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1495                         if ((remote_adv & LPA_PAUSE_CAP) &&
1496                         (remote_adv & LPA_PAUSE_ASYM))
1497                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1498                 }
1499
1500                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1501                 tp->tg3_flags |= new_tg3_flags;
1502         } else {
1503                 new_tg3_flags = tp->tg3_flags;
1504         }
1505
1506         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1507                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1508         else
1509                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1510
1511         if (old_rx_mode != tp->rx_mode) {
1512                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1513         }
1514
1515         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1516                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1517         else
1518                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1519
1520         if (old_tx_mode != tp->tx_mode) {
1521                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1522         }
1523 }
1524
1525 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1526 {
1527         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1528         case MII_TG3_AUX_STAT_10HALF:
1529                 *speed = SPEED_10;
1530                 *duplex = DUPLEX_HALF;
1531                 break;
1532
1533         case MII_TG3_AUX_STAT_10FULL:
1534                 *speed = SPEED_10;
1535                 *duplex = DUPLEX_FULL;
1536                 break;
1537
1538         case MII_TG3_AUX_STAT_100HALF:
1539                 *speed = SPEED_100;
1540                 *duplex = DUPLEX_HALF;
1541                 break;
1542
1543         case MII_TG3_AUX_STAT_100FULL:
1544                 *speed = SPEED_100;
1545                 *duplex = DUPLEX_FULL;
1546                 break;
1547
1548         case MII_TG3_AUX_STAT_1000HALF:
1549                 *speed = SPEED_1000;
1550                 *duplex = DUPLEX_HALF;
1551                 break;
1552
1553         case MII_TG3_AUX_STAT_1000FULL:
1554                 *speed = SPEED_1000;
1555                 *duplex = DUPLEX_FULL;
1556                 break;
1557
1558         default:
1559                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1560                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1561                                  SPEED_10;
1562                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1563                                   DUPLEX_HALF;
1564                         break;
1565                 }
1566                 *speed = SPEED_INVALID;
1567                 *duplex = DUPLEX_INVALID;
1568                 break;
1569         };
1570 }
1571
1572 static void tg3_phy_copper_begin(struct tg3 *tp)
1573 {
1574         u32 new_adv;
1575         int i;
1576
1577         if (tp->link_config.phy_is_low_power) {
1578                 /* Entering low power mode.  Disable gigabit and
1579                  * 100baseT advertisements.
1580                  */
1581                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1582
1583                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1584                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1585                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1586                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1587
1588                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1589         } else if (tp->link_config.speed == SPEED_INVALID) {
1590                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1591                         tp->link_config.advertising &=
1592                                 ~(ADVERTISED_1000baseT_Half |
1593                                   ADVERTISED_1000baseT_Full);
1594
1595                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1596                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1597                         new_adv |= ADVERTISE_10HALF;
1598                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1599                         new_adv |= ADVERTISE_10FULL;
1600                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1601                         new_adv |= ADVERTISE_100HALF;
1602                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1603                         new_adv |= ADVERTISE_100FULL;
1604                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1605
1606                 if (tp->link_config.advertising &
1607                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1608                         new_adv = 0;
1609                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1610                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1611                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1612                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1613                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1614                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1615                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1616                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1617                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1618                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1619                 } else {
1620                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1621                 }
1622         } else {
1623                 /* Asking for a specific link mode. */
1624                 if (tp->link_config.speed == SPEED_1000) {
1625                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1626                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1627
1628                         if (tp->link_config.duplex == DUPLEX_FULL)
1629                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1630                         else
1631                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1632                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1633                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1634                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1635                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1636                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1637                 } else {
1638                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1639
1640                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1641                         if (tp->link_config.speed == SPEED_100) {
1642                                 if (tp->link_config.duplex == DUPLEX_FULL)
1643                                         new_adv |= ADVERTISE_100FULL;
1644                                 else
1645                                         new_adv |= ADVERTISE_100HALF;
1646                         } else {
1647                                 if (tp->link_config.duplex == DUPLEX_FULL)
1648                                         new_adv |= ADVERTISE_10FULL;
1649                                 else
1650                                         new_adv |= ADVERTISE_10HALF;
1651                         }
1652                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1653                 }
1654         }
1655
1656         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1657             tp->link_config.speed != SPEED_INVALID) {
1658                 u32 bmcr, orig_bmcr;
1659
1660                 tp->link_config.active_speed = tp->link_config.speed;
1661                 tp->link_config.active_duplex = tp->link_config.duplex;
1662
1663                 bmcr = 0;
1664                 switch (tp->link_config.speed) {
1665                 default:
1666                 case SPEED_10:
1667                         break;
1668
1669                 case SPEED_100:
1670                         bmcr |= BMCR_SPEED100;
1671                         break;
1672
1673                 case SPEED_1000:
1674                         bmcr |= TG3_BMCR_SPEED1000;
1675                         break;
1676                 };
1677
1678                 if (tp->link_config.duplex == DUPLEX_FULL)
1679                         bmcr |= BMCR_FULLDPLX;
1680
1681                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1682                     (bmcr != orig_bmcr)) {
1683                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1684                         for (i = 0; i < 1500; i++) {
1685                                 u32 tmp;
1686
1687                                 udelay(10);
1688                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1689                                     tg3_readphy(tp, MII_BMSR, &tmp))
1690                                         continue;
1691                                 if (!(tmp & BMSR_LSTATUS)) {
1692                                         udelay(40);
1693                                         break;
1694                                 }
1695                         }
1696                         tg3_writephy(tp, MII_BMCR, bmcr);
1697                         udelay(40);
1698                 }
1699         } else {
1700                 tg3_writephy(tp, MII_BMCR,
1701                              BMCR_ANENABLE | BMCR_ANRESTART);
1702         }
1703 }
1704
1705 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1706 {
1707         int err;
1708
1709         /* Turn off tap power management. */
1710         /* Set Extended packet length bit */
1711         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1712
1713         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1714         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1715
1716         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1717         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1718
1719         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1720         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1721
1722         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1723         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1724
1725         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1726         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1727
1728         udelay(40);
1729
1730         return err;
1731 }
1732
1733 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1734 {
1735         u32 adv_reg, all_mask = 0;
1736
1737         if (mask & ADVERTISED_10baseT_Half)
1738                 all_mask |= ADVERTISE_10HALF;
1739         if (mask & ADVERTISED_10baseT_Full)
1740                 all_mask |= ADVERTISE_10FULL;
1741         if (mask & ADVERTISED_100baseT_Half)
1742                 all_mask |= ADVERTISE_100HALF;
1743         if (mask & ADVERTISED_100baseT_Full)
1744                 all_mask |= ADVERTISE_100FULL;
1745
1746         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1747                 return 0;
1748
1749         if ((adv_reg & all_mask) != all_mask)
1750                 return 0;
1751         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1752                 u32 tg3_ctrl;
1753
1754                 all_mask = 0;
1755                 if (mask & ADVERTISED_1000baseT_Half)
1756                         all_mask |= ADVERTISE_1000HALF;
1757                 if (mask & ADVERTISED_1000baseT_Full)
1758                         all_mask |= ADVERTISE_1000FULL;
1759
1760                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1761                         return 0;
1762
1763                 if ((tg3_ctrl & all_mask) != all_mask)
1764                         return 0;
1765         }
1766         return 1;
1767 }
1768
1769 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1770 {
1771         int current_link_up;
1772         u32 bmsr, dummy;
1773         u16 current_speed;
1774         u8 current_duplex;
1775         int i, err;
1776
1777         tw32(MAC_EVENT, 0);
1778
1779         tw32_f(MAC_STATUS,
1780              (MAC_STATUS_SYNC_CHANGED |
1781               MAC_STATUS_CFG_CHANGED |
1782               MAC_STATUS_MI_COMPLETION |
1783               MAC_STATUS_LNKSTATE_CHANGED));
1784         udelay(40);
1785
1786         tp->mi_mode = MAC_MI_MODE_BASE;
1787         tw32_f(MAC_MI_MODE, tp->mi_mode);
1788         udelay(80);
1789
1790         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1791
1792         /* Some third-party PHYs need to be reset on link going
1793          * down.
1794          */
1795         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1798             netif_carrier_ok(tp->dev)) {
1799                 tg3_readphy(tp, MII_BMSR, &bmsr);
1800                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1801                     !(bmsr & BMSR_LSTATUS))
1802                         force_reset = 1;
1803         }
1804         if (force_reset)
1805                 tg3_phy_reset(tp);
1806
1807         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1808                 tg3_readphy(tp, MII_BMSR, &bmsr);
1809                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1810                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1811                         bmsr = 0;
1812
1813                 if (!(bmsr & BMSR_LSTATUS)) {
1814                         err = tg3_init_5401phy_dsp(tp);
1815                         if (err)
1816                                 return err;
1817
1818                         tg3_readphy(tp, MII_BMSR, &bmsr);
1819                         for (i = 0; i < 1000; i++) {
1820                                 udelay(10);
1821                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1822                                     (bmsr & BMSR_LSTATUS)) {
1823                                         udelay(40);
1824                                         break;
1825                                 }
1826                         }
1827
1828                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1829                             !(bmsr & BMSR_LSTATUS) &&
1830                             tp->link_config.active_speed == SPEED_1000) {
1831                                 err = tg3_phy_reset(tp);
1832                                 if (!err)
1833                                         err = tg3_init_5401phy_dsp(tp);
1834                                 if (err)
1835                                         return err;
1836                         }
1837                 }
1838         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1839                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1840                 /* 5701 {A0,B0} CRC bug workaround */
1841                 tg3_writephy(tp, 0x15, 0x0a75);
1842                 tg3_writephy(tp, 0x1c, 0x8c68);
1843                 tg3_writephy(tp, 0x1c, 0x8d68);
1844                 tg3_writephy(tp, 0x1c, 0x8c68);
1845         }
1846
1847         /* Clear pending interrupts... */
1848         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850
1851         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1852                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1853         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1854                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1855
1856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1858                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1859                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1860                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1861                 else
1862                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1863         }
1864
1865         current_link_up = 0;
1866         current_speed = SPEED_INVALID;
1867         current_duplex = DUPLEX_INVALID;
1868
1869         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1870                 u32 val;
1871
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1873                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1874                 if (!(val & (1 << 10))) {
1875                         val |= (1 << 10);
1876                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1877                         goto relink;
1878                 }
1879         }
1880
1881         bmsr = 0;
1882         for (i = 0; i < 100; i++) {
1883                 tg3_readphy(tp, MII_BMSR, &bmsr);
1884                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1885                     (bmsr & BMSR_LSTATUS))
1886                         break;
1887                 udelay(40);
1888         }
1889
1890         if (bmsr & BMSR_LSTATUS) {
1891                 u32 aux_stat, bmcr;
1892
1893                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1894                 for (i = 0; i < 2000; i++) {
1895                         udelay(10);
1896                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1897                             aux_stat)
1898                                 break;
1899                 }
1900
1901                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1902                                              &current_speed,
1903                                              &current_duplex);
1904
1905                 bmcr = 0;
1906                 for (i = 0; i < 200; i++) {
1907                         tg3_readphy(tp, MII_BMCR, &bmcr);
1908                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1909                                 continue;
1910                         if (bmcr && bmcr != 0x7fff)
1911                                 break;
1912                         udelay(10);
1913                 }
1914
1915                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1916                         if (bmcr & BMCR_ANENABLE) {
1917                                 current_link_up = 1;
1918
1919                                 /* Force autoneg restart if we are exiting
1920                                  * low power mode.
1921                                  */
1922                                 if (!tg3_copper_is_advertising_all(tp,
1923                                                 tp->link_config.advertising))
1924                                         current_link_up = 0;
1925                         } else {
1926                                 current_link_up = 0;
1927                         }
1928                 } else {
1929                         if (!(bmcr & BMCR_ANENABLE) &&
1930                             tp->link_config.speed == current_speed &&
1931                             tp->link_config.duplex == current_duplex) {
1932                                 current_link_up = 1;
1933                         } else {
1934                                 current_link_up = 0;
1935                         }
1936                 }
1937
1938                 tp->link_config.active_speed = current_speed;
1939                 tp->link_config.active_duplex = current_duplex;
1940         }
1941
1942         if (current_link_up == 1 &&
1943             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1944             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1945                 u32 local_adv, remote_adv;
1946
1947                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1948                         local_adv = 0;
1949                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1950
1951                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1952                         remote_adv = 0;
1953
1954                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1955
1956                 /* If we are not advertising full pause capability,
1957                  * something is wrong.  Bring the link down and reconfigure.
1958                  */
1959                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1960                         current_link_up = 0;
1961                 } else {
1962                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1963                 }
1964         }
1965 relink:
1966         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1967                 u32 tmp;
1968
1969                 tg3_phy_copper_begin(tp);
1970
1971                 tg3_readphy(tp, MII_BMSR, &tmp);
1972                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1973                     (tmp & BMSR_LSTATUS))
1974                         current_link_up = 1;
1975         }
1976
1977         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1978         if (current_link_up == 1) {
1979                 if (tp->link_config.active_speed == SPEED_100 ||
1980                     tp->link_config.active_speed == SPEED_10)
1981                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1982                 else
1983                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1984         } else
1985                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986
1987         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1988         if (tp->link_config.active_duplex == DUPLEX_HALF)
1989                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1990
1991         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1993                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1994                     (current_link_up == 1 &&
1995                      tp->link_config.active_speed == SPEED_10))
1996                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1997         } else {
1998                 if (current_link_up == 1)
1999                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2000         }
2001
2002         /* ??? Without this setting Netgear GA302T PHY does not
2003          * ??? send/receive packets...
2004          */
2005         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2006             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2007                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2008                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2009                 udelay(80);
2010         }
2011
2012         tw32_f(MAC_MODE, tp->mac_mode);
2013         udelay(40);
2014
2015         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2016                 /* Polled via timer. */
2017                 tw32_f(MAC_EVENT, 0);
2018         } else {
2019                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2020         }
2021         udelay(40);
2022
2023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2024             current_link_up == 1 &&
2025             tp->link_config.active_speed == SPEED_1000 &&
2026             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2027              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2028                 udelay(120);
2029                 tw32_f(MAC_STATUS,
2030                      (MAC_STATUS_SYNC_CHANGED |
2031                       MAC_STATUS_CFG_CHANGED));
2032                 udelay(40);
2033                 tg3_write_mem(tp,
2034                               NIC_SRAM_FIRMWARE_MBOX,
2035                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2036         }
2037
2038         if (current_link_up != netif_carrier_ok(tp->dev)) {
2039                 if (current_link_up)
2040                         netif_carrier_on(tp->dev);
2041                 else
2042                         netif_carrier_off(tp->dev);
2043                 tg3_link_report(tp);
2044         }
2045
2046         return 0;
2047 }
2048
2049 struct tg3_fiber_aneginfo {
2050         int state;
2051 #define ANEG_STATE_UNKNOWN              0
2052 #define ANEG_STATE_AN_ENABLE            1
2053 #define ANEG_STATE_RESTART_INIT         2
2054 #define ANEG_STATE_RESTART              3
2055 #define ANEG_STATE_DISABLE_LINK_OK      4
2056 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2057 #define ANEG_STATE_ABILITY_DETECT       6
2058 #define ANEG_STATE_ACK_DETECT_INIT      7
2059 #define ANEG_STATE_ACK_DETECT           8
2060 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2061 #define ANEG_STATE_COMPLETE_ACK         10
2062 #define ANEG_STATE_IDLE_DETECT_INIT     11
2063 #define ANEG_STATE_IDLE_DETECT          12
2064 #define ANEG_STATE_LINK_OK              13
2065 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2066 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2067
2068         u32 flags;
2069 #define MR_AN_ENABLE            0x00000001
2070 #define MR_RESTART_AN           0x00000002
2071 #define MR_AN_COMPLETE          0x00000004
2072 #define MR_PAGE_RX              0x00000008
2073 #define MR_NP_LOADED            0x00000010
2074 #define MR_TOGGLE_TX            0x00000020
2075 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2076 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2077 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2078 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2079 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2080 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2081 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2082 #define MR_TOGGLE_RX            0x00002000
2083 #define MR_NP_RX                0x00004000
2084
2085 #define MR_LINK_OK              0x80000000
2086
2087         unsigned long link_time, cur_time;
2088
2089         u32 ability_match_cfg;
2090         int ability_match_count;
2091
2092         char ability_match, idle_match, ack_match;
2093
2094         u32 txconfig, rxconfig;
2095 #define ANEG_CFG_NP             0x00000080
2096 #define ANEG_CFG_ACK            0x00000040
2097 #define ANEG_CFG_RF2            0x00000020
2098 #define ANEG_CFG_RF1            0x00000010
2099 #define ANEG_CFG_PS2            0x00000001
2100 #define ANEG_CFG_PS1            0x00008000
2101 #define ANEG_CFG_HD             0x00004000
2102 #define ANEG_CFG_FD             0x00002000
2103 #define ANEG_CFG_INVAL          0x00001f06
2104
2105 };
2106 #define ANEG_OK         0
2107 #define ANEG_DONE       1
2108 #define ANEG_TIMER_ENAB 2
2109 #define ANEG_FAILED     -1
2110
2111 #define ANEG_STATE_SETTLE_TIME  10000
2112
2113 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2114                                    struct tg3_fiber_aneginfo *ap)
2115 {
2116         unsigned long delta;
2117         u32 rx_cfg_reg;
2118         int ret;
2119
2120         if (ap->state == ANEG_STATE_UNKNOWN) {
2121                 ap->rxconfig = 0;
2122                 ap->link_time = 0;
2123                 ap->cur_time = 0;
2124                 ap->ability_match_cfg = 0;
2125                 ap->ability_match_count = 0;
2126                 ap->ability_match = 0;
2127                 ap->idle_match = 0;
2128                 ap->ack_match = 0;
2129         }
2130         ap->cur_time++;
2131
2132         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2133                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2134
2135                 if (rx_cfg_reg != ap->ability_match_cfg) {
2136                         ap->ability_match_cfg = rx_cfg_reg;
2137                         ap->ability_match = 0;
2138                         ap->ability_match_count = 0;
2139                 } else {
2140                         if (++ap->ability_match_count > 1) {
2141                                 ap->ability_match = 1;
2142                                 ap->ability_match_cfg = rx_cfg_reg;
2143                         }
2144                 }
2145                 if (rx_cfg_reg & ANEG_CFG_ACK)
2146                         ap->ack_match = 1;
2147                 else
2148                         ap->ack_match = 0;
2149
2150                 ap->idle_match = 0;
2151         } else {
2152                 ap->idle_match = 1;
2153                 ap->ability_match_cfg = 0;
2154                 ap->ability_match_count = 0;
2155                 ap->ability_match = 0;
2156                 ap->ack_match = 0;
2157
2158                 rx_cfg_reg = 0;
2159         }
2160
2161         ap->rxconfig = rx_cfg_reg;
2162         ret = ANEG_OK;
2163
2164         switch(ap->state) {
2165         case ANEG_STATE_UNKNOWN:
2166                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2167                         ap->state = ANEG_STATE_AN_ENABLE;
2168
2169                 /* fallthru */
2170         case ANEG_STATE_AN_ENABLE:
2171                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2172                 if (ap->flags & MR_AN_ENABLE) {
2173                         ap->link_time = 0;
2174                         ap->cur_time = 0;
2175                         ap->ability_match_cfg = 0;
2176                         ap->ability_match_count = 0;
2177                         ap->ability_match = 0;
2178                         ap->idle_match = 0;
2179                         ap->ack_match = 0;
2180
2181                         ap->state = ANEG_STATE_RESTART_INIT;
2182                 } else {
2183                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2184                 }
2185                 break;
2186
2187         case ANEG_STATE_RESTART_INIT:
2188                 ap->link_time = ap->cur_time;
2189                 ap->flags &= ~(MR_NP_LOADED);
2190                 ap->txconfig = 0;
2191                 tw32(MAC_TX_AUTO_NEG, 0);
2192                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2193                 tw32_f(MAC_MODE, tp->mac_mode);
2194                 udelay(40);
2195
2196                 ret = ANEG_TIMER_ENAB;
2197                 ap->state = ANEG_STATE_RESTART;
2198
2199                 /* fallthru */
2200         case ANEG_STATE_RESTART:
2201                 delta = ap->cur_time - ap->link_time;
2202                 if (delta > ANEG_STATE_SETTLE_TIME) {
2203                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2204                 } else {
2205                         ret = ANEG_TIMER_ENAB;
2206                 }
2207                 break;
2208
2209         case ANEG_STATE_DISABLE_LINK_OK:
2210                 ret = ANEG_DONE;
2211                 break;
2212
2213         case ANEG_STATE_ABILITY_DETECT_INIT:
2214                 ap->flags &= ~(MR_TOGGLE_TX);
2215                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2216                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2217                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2218                 tw32_f(MAC_MODE, tp->mac_mode);
2219                 udelay(40);
2220
2221                 ap->state = ANEG_STATE_ABILITY_DETECT;
2222                 break;
2223
2224         case ANEG_STATE_ABILITY_DETECT:
2225                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2226                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2227                 }
2228                 break;
2229
2230         case ANEG_STATE_ACK_DETECT_INIT:
2231                 ap->txconfig |= ANEG_CFG_ACK;
2232                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2233                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2234                 tw32_f(MAC_MODE, tp->mac_mode);
2235                 udelay(40);
2236
2237                 ap->state = ANEG_STATE_ACK_DETECT;
2238
2239                 /* fallthru */
2240         case ANEG_STATE_ACK_DETECT:
2241                 if (ap->ack_match != 0) {
2242                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2243                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2244                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2245                         } else {
2246                                 ap->state = ANEG_STATE_AN_ENABLE;
2247                         }
2248                 } else if (ap->ability_match != 0 &&
2249                            ap->rxconfig == 0) {
2250                         ap->state = ANEG_STATE_AN_ENABLE;
2251                 }
2252                 break;
2253
2254         case ANEG_STATE_COMPLETE_ACK_INIT:
2255                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2256                         ret = ANEG_FAILED;
2257                         break;
2258                 }
2259                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2260                                MR_LP_ADV_HALF_DUPLEX |
2261                                MR_LP_ADV_SYM_PAUSE |
2262                                MR_LP_ADV_ASYM_PAUSE |
2263                                MR_LP_ADV_REMOTE_FAULT1 |
2264                                MR_LP_ADV_REMOTE_FAULT2 |
2265                                MR_LP_ADV_NEXT_PAGE |
2266                                MR_TOGGLE_RX |
2267                                MR_NP_RX);
2268                 if (ap->rxconfig & ANEG_CFG_FD)
2269                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2270                 if (ap->rxconfig & ANEG_CFG_HD)
2271                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2272                 if (ap->rxconfig & ANEG_CFG_PS1)
2273                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2274                 if (ap->rxconfig & ANEG_CFG_PS2)
2275                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2276                 if (ap->rxconfig & ANEG_CFG_RF1)
2277                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2278                 if (ap->rxconfig & ANEG_CFG_RF2)
2279                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2280                 if (ap->rxconfig & ANEG_CFG_NP)
2281                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2282
2283                 ap->link_time = ap->cur_time;
2284
2285                 ap->flags ^= (MR_TOGGLE_TX);
2286                 if (ap->rxconfig & 0x0008)
2287                         ap->flags |= MR_TOGGLE_RX;
2288                 if (ap->rxconfig & ANEG_CFG_NP)
2289                         ap->flags |= MR_NP_RX;
2290                 ap->flags |= MR_PAGE_RX;
2291
2292                 ap->state = ANEG_STATE_COMPLETE_ACK;
2293                 ret = ANEG_TIMER_ENAB;
2294                 break;
2295
2296         case ANEG_STATE_COMPLETE_ACK:
2297                 if (ap->ability_match != 0 &&
2298                     ap->rxconfig == 0) {
2299                         ap->state = ANEG_STATE_AN_ENABLE;
2300                         break;
2301                 }
2302                 delta = ap->cur_time - ap->link_time;
2303                 if (delta > ANEG_STATE_SETTLE_TIME) {
2304                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2305                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2306                         } else {
2307                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2308                                     !(ap->flags & MR_NP_RX)) {
2309                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2310                                 } else {
2311                                         ret = ANEG_FAILED;
2312                                 }
2313                         }
2314                 }
2315                 break;
2316
2317         case ANEG_STATE_IDLE_DETECT_INIT:
2318                 ap->link_time = ap->cur_time;
2319                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2320                 tw32_f(MAC_MODE, tp->mac_mode);
2321                 udelay(40);
2322
2323                 ap->state = ANEG_STATE_IDLE_DETECT;
2324                 ret = ANEG_TIMER_ENAB;
2325                 break;
2326
2327         case ANEG_STATE_IDLE_DETECT:
2328                 if (ap->ability_match != 0 &&
2329                     ap->rxconfig == 0) {
2330                         ap->state = ANEG_STATE_AN_ENABLE;
2331                         break;
2332                 }
2333                 delta = ap->cur_time - ap->link_time;
2334                 if (delta > ANEG_STATE_SETTLE_TIME) {
2335                         /* XXX another gem from the Broadcom driver :( */
2336                         ap->state = ANEG_STATE_LINK_OK;
2337                 }
2338                 break;
2339
2340         case ANEG_STATE_LINK_OK:
2341                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2342                 ret = ANEG_DONE;
2343                 break;
2344
2345         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2346                 /* ??? unimplemented */
2347                 break;
2348
2349         case ANEG_STATE_NEXT_PAGE_WAIT:
2350                 /* ??? unimplemented */
2351                 break;
2352
2353         default:
2354                 ret = ANEG_FAILED;
2355                 break;
2356         };
2357
2358         return ret;
2359 }
2360
2361 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2362 {
2363         int res = 0;
2364         struct tg3_fiber_aneginfo aninfo;
2365         int status = ANEG_FAILED;
2366         unsigned int tick;
2367         u32 tmp;
2368
2369         tw32_f(MAC_TX_AUTO_NEG, 0);
2370
2371         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2372         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2373         udelay(40);
2374
2375         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2376         udelay(40);
2377
2378         memset(&aninfo, 0, sizeof(aninfo));
2379         aninfo.flags |= MR_AN_ENABLE;
2380         aninfo.state = ANEG_STATE_UNKNOWN;
2381         aninfo.cur_time = 0;
2382         tick = 0;
2383         while (++tick < 195000) {
2384                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2385                 if (status == ANEG_DONE || status == ANEG_FAILED)
2386                         break;
2387
2388                 udelay(1);
2389         }
2390
2391         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2392         tw32_f(MAC_MODE, tp->mac_mode);
2393         udelay(40);
2394
2395         *flags = aninfo.flags;
2396
2397         if (status == ANEG_DONE &&
2398             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2399                              MR_LP_ADV_FULL_DUPLEX)))
2400                 res = 1;
2401
2402         return res;
2403 }
2404
2405 static void tg3_init_bcm8002(struct tg3 *tp)
2406 {
2407         u32 mac_status = tr32(MAC_STATUS);
2408         int i;
2409
2410         /* Reset when initting first time or we have a link. */
2411         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2412             !(mac_status & MAC_STATUS_PCS_SYNCED))
2413                 return;
2414
2415         /* Set PLL lock range. */
2416         tg3_writephy(tp, 0x16, 0x8007);
2417
2418         /* SW reset */
2419         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2420
2421         /* Wait for reset to complete. */
2422         /* XXX schedule_timeout() ... */
2423         for (i = 0; i < 500; i++)
2424                 udelay(10);
2425
2426         /* Config mode; select PMA/Ch 1 regs. */
2427         tg3_writephy(tp, 0x10, 0x8411);
2428
2429         /* Enable auto-lock and comdet, select txclk for tx. */
2430         tg3_writephy(tp, 0x11, 0x0a10);
2431
2432         tg3_writephy(tp, 0x18, 0x00a0);
2433         tg3_writephy(tp, 0x16, 0x41ff);
2434
2435         /* Assert and deassert POR. */
2436         tg3_writephy(tp, 0x13, 0x0400);
2437         udelay(40);
2438         tg3_writephy(tp, 0x13, 0x0000);
2439
2440         tg3_writephy(tp, 0x11, 0x0a50);
2441         udelay(40);
2442         tg3_writephy(tp, 0x11, 0x0a10);
2443
2444         /* Wait for signal to stabilize */
2445         /* XXX schedule_timeout() ... */
2446         for (i = 0; i < 15000; i++)
2447                 udelay(10);
2448
2449         /* Deselect the channel register so we can read the PHYID
2450          * later.
2451          */
2452         tg3_writephy(tp, 0x10, 0x8011);
2453 }
2454
2455 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2456 {
2457         u32 sg_dig_ctrl, sg_dig_status;
2458         u32 serdes_cfg, expected_sg_dig_ctrl;
2459         int workaround, port_a;
2460         int current_link_up;
2461
2462         serdes_cfg = 0;
2463         expected_sg_dig_ctrl = 0;
2464         workaround = 0;
2465         port_a = 1;
2466         current_link_up = 0;
2467
2468         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2469             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2470                 workaround = 1;
2471                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2472                         port_a = 0;
2473
2474                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2475                 /* preserve bits 20-23 for voltage regulator */
2476                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2477         }
2478
2479         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2480
2481         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2482                 if (sg_dig_ctrl & (1 << 31)) {
2483                         if (workaround) {
2484                                 u32 val = serdes_cfg;
2485
2486                                 if (port_a)
2487                                         val |= 0xc010000;
2488                                 else
2489                                         val |= 0x4010000;
2490                                 tw32_f(MAC_SERDES_CFG, val);
2491                         }
2492                         tw32_f(SG_DIG_CTRL, 0x01388400);
2493                 }
2494                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2495                         tg3_setup_flow_control(tp, 0, 0);
2496                         current_link_up = 1;
2497                 }
2498                 goto out;
2499         }
2500
2501         /* Want auto-negotiation.  */
2502         expected_sg_dig_ctrl = 0x81388400;
2503
2504         /* Pause capability */
2505         expected_sg_dig_ctrl |= (1 << 11);
2506
2507         /* Asymettric pause */
2508         expected_sg_dig_ctrl |= (1 << 12);
2509
2510         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2511                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2512                     tp->serdes_counter &&
2513                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2514                                     MAC_STATUS_RCVD_CFG)) ==
2515                      MAC_STATUS_PCS_SYNCED)) {
2516                         tp->serdes_counter--;
2517                         current_link_up = 1;
2518                         goto out;
2519                 }
2520 restart_autoneg:
2521                 if (workaround)
2522                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2523                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2524                 udelay(5);
2525                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2526
2527                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2528                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2529         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2530                                  MAC_STATUS_SIGNAL_DET)) {
2531                 sg_dig_status = tr32(SG_DIG_STATUS);
2532                 mac_status = tr32(MAC_STATUS);
2533
2534                 if ((sg_dig_status & (1 << 1)) &&
2535                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2536                         u32 local_adv, remote_adv;
2537
2538                         local_adv = ADVERTISE_PAUSE_CAP;
2539                         remote_adv = 0;
2540                         if (sg_dig_status & (1 << 19))
2541                                 remote_adv |= LPA_PAUSE_CAP;
2542                         if (sg_dig_status & (1 << 20))
2543                                 remote_adv |= LPA_PAUSE_ASYM;
2544
2545                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2546                         current_link_up = 1;
2547                         tp->serdes_counter = 0;
2548                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2549                 } else if (!(sg_dig_status & (1 << 1))) {
2550                         if (tp->serdes_counter)
2551                                 tp->serdes_counter--;
2552                         else {
2553                                 if (workaround) {
2554                                         u32 val = serdes_cfg;
2555
2556                                         if (port_a)
2557                                                 val |= 0xc010000;
2558                                         else
2559                                                 val |= 0x4010000;
2560
2561                                         tw32_f(MAC_SERDES_CFG, val);
2562                                 }
2563
2564                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2565                                 udelay(40);
2566
2567                                 /* Link parallel detection - link is up */
2568                                 /* only if we have PCS_SYNC and not */
2569                                 /* receiving config code words */
2570                                 mac_status = tr32(MAC_STATUS);
2571                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2572                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2573                                         tg3_setup_flow_control(tp, 0, 0);
2574                                         current_link_up = 1;
2575                                         tp->tg3_flags2 |=
2576                                                 TG3_FLG2_PARALLEL_DETECT;
2577                                         tp->serdes_counter =
2578                                                 SERDES_PARALLEL_DET_TIMEOUT;
2579                                 } else
2580                                         goto restart_autoneg;
2581                         }
2582                 }
2583         } else {
2584                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2585                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2586         }
2587
2588 out:
2589         return current_link_up;
2590 }
2591
2592 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2593 {
2594         int current_link_up = 0;
2595
2596         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2597                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2598                 goto out;
2599         }
2600
2601         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602                 u32 flags;
2603                 int i;
2604
2605                 if (fiber_autoneg(tp, &flags)) {
2606                         u32 local_adv, remote_adv;
2607
2608                         local_adv = ADVERTISE_PAUSE_CAP;
2609                         remote_adv = 0;
2610                         if (flags & MR_LP_ADV_SYM_PAUSE)
2611                                 remote_adv |= LPA_PAUSE_CAP;
2612                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2613                                 remote_adv |= LPA_PAUSE_ASYM;
2614
2615                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2618                         current_link_up = 1;
2619                 }
2620                 for (i = 0; i < 30; i++) {
2621                         udelay(20);
2622                         tw32_f(MAC_STATUS,
2623                                (MAC_STATUS_SYNC_CHANGED |
2624                                 MAC_STATUS_CFG_CHANGED));
2625                         udelay(40);
2626                         if ((tr32(MAC_STATUS) &
2627                              (MAC_STATUS_SYNC_CHANGED |
2628                               MAC_STATUS_CFG_CHANGED)) == 0)
2629                                 break;
2630                 }
2631
2632                 mac_status = tr32(MAC_STATUS);
2633                 if (current_link_up == 0 &&
2634                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2635                     !(mac_status & MAC_STATUS_RCVD_CFG))
2636                         current_link_up = 1;
2637         } else {
2638                 /* Forcing 1000FD link up. */
2639                 current_link_up = 1;
2640                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2641
2642                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2643                 udelay(40);
2644         }
2645
2646 out:
2647         return current_link_up;
2648 }
2649
2650 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2651 {
2652         u32 orig_pause_cfg;
2653         u16 orig_active_speed;
2654         u8 orig_active_duplex;
2655         u32 mac_status;
2656         int current_link_up;
2657         int i;
2658
2659         orig_pause_cfg =
2660                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2661                                   TG3_FLAG_TX_PAUSE));
2662         orig_active_speed = tp->link_config.active_speed;
2663         orig_active_duplex = tp->link_config.active_duplex;
2664
2665         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2666             netif_carrier_ok(tp->dev) &&
2667             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2668                 mac_status = tr32(MAC_STATUS);
2669                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2670                                MAC_STATUS_SIGNAL_DET |
2671                                MAC_STATUS_CFG_CHANGED |
2672                                MAC_STATUS_RCVD_CFG);
2673                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2674                                    MAC_STATUS_SIGNAL_DET)) {
2675                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2676                                             MAC_STATUS_CFG_CHANGED));
2677                         return 0;
2678                 }
2679         }
2680
2681         tw32_f(MAC_TX_AUTO_NEG, 0);
2682
2683         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2684         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2685         tw32_f(MAC_MODE, tp->mac_mode);
2686         udelay(40);
2687
2688         if (tp->phy_id == PHY_ID_BCM8002)
2689                 tg3_init_bcm8002(tp);
2690
2691         /* Enable link change event even when serdes polling.  */
2692         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2693         udelay(40);
2694
2695         current_link_up = 0;
2696         mac_status = tr32(MAC_STATUS);
2697
2698         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2699                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2700         else
2701                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2702
2703         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704         tw32_f(MAC_MODE, tp->mac_mode);
2705         udelay(40);
2706
2707         tp->hw_status->status =
2708                 (SD_STATUS_UPDATED |
2709                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2710
2711         for (i = 0; i < 100; i++) {
2712                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2713                                     MAC_STATUS_CFG_CHANGED));
2714                 udelay(5);
2715                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2716                                          MAC_STATUS_CFG_CHANGED |
2717                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2718                         break;
2719         }
2720
2721         mac_status = tr32(MAC_STATUS);
2722         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2723                 current_link_up = 0;
2724                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2725                     tp->serdes_counter == 0) {
2726                         tw32_f(MAC_MODE, (tp->mac_mode |
2727                                           MAC_MODE_SEND_CONFIGS));
2728                         udelay(1);
2729                         tw32_f(MAC_MODE, tp->mac_mode);
2730                 }
2731         }
2732
2733         if (current_link_up == 1) {
2734                 tp->link_config.active_speed = SPEED_1000;
2735                 tp->link_config.active_duplex = DUPLEX_FULL;
2736                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2737                                     LED_CTRL_LNKLED_OVERRIDE |
2738                                     LED_CTRL_1000MBPS_ON));
2739         } else {
2740                 tp->link_config.active_speed = SPEED_INVALID;
2741                 tp->link_config.active_duplex = DUPLEX_INVALID;
2742                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2743                                     LED_CTRL_LNKLED_OVERRIDE |
2744                                     LED_CTRL_TRAFFIC_OVERRIDE));
2745         }
2746
2747         if (current_link_up != netif_carrier_ok(tp->dev)) {
2748                 if (current_link_up)
2749                         netif_carrier_on(tp->dev);
2750                 else
2751                         netif_carrier_off(tp->dev);
2752                 tg3_link_report(tp);
2753         } else {
2754                 u32 now_pause_cfg =
2755                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2756                                          TG3_FLAG_TX_PAUSE);
2757                 if (orig_pause_cfg != now_pause_cfg ||
2758                     orig_active_speed != tp->link_config.active_speed ||
2759                     orig_active_duplex != tp->link_config.active_duplex)
2760                         tg3_link_report(tp);
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2767 {
2768         int current_link_up, err = 0;
2769         u32 bmsr, bmcr;
2770         u16 current_speed;
2771         u8 current_duplex;
2772
2773         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2774         tw32_f(MAC_MODE, tp->mac_mode);
2775         udelay(40);
2776
2777         tw32(MAC_EVENT, 0);
2778
2779         tw32_f(MAC_STATUS,
2780              (MAC_STATUS_SYNC_CHANGED |
2781               MAC_STATUS_CFG_CHANGED |
2782               MAC_STATUS_MI_COMPLETION |
2783               MAC_STATUS_LNKSTATE_CHANGED));
2784         udelay(40);
2785
2786         if (force_reset)
2787                 tg3_phy_reset(tp);
2788
2789         current_link_up = 0;
2790         current_speed = SPEED_INVALID;
2791         current_duplex = DUPLEX_INVALID;
2792
2793         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2796                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2797                         bmsr |= BMSR_LSTATUS;
2798                 else
2799                         bmsr &= ~BMSR_LSTATUS;
2800         }
2801
2802         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2803
2804         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2805             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2806                 /* do nothing, just check for link up at the end */
2807         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2808                 u32 adv, new_adv;
2809
2810                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2811                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2812                                   ADVERTISE_1000XPAUSE |
2813                                   ADVERTISE_1000XPSE_ASYM |
2814                                   ADVERTISE_SLCT);
2815
2816                 /* Always advertise symmetric PAUSE just like copper */
2817                 new_adv |= ADVERTISE_1000XPAUSE;
2818
2819                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2820                         new_adv |= ADVERTISE_1000XHALF;
2821                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2822                         new_adv |= ADVERTISE_1000XFULL;
2823
2824                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2825                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2826                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2827                         tg3_writephy(tp, MII_BMCR, bmcr);
2828
2829                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2830                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2831                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2832
2833                         return err;
2834                 }
2835         } else {
2836                 u32 new_bmcr;
2837
2838                 bmcr &= ~BMCR_SPEED1000;
2839                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2840
2841                 if (tp->link_config.duplex == DUPLEX_FULL)
2842                         new_bmcr |= BMCR_FULLDPLX;
2843
2844                 if (new_bmcr != bmcr) {
2845                         /* BMCR_SPEED1000 is a reserved bit that needs
2846                          * to be set on write.
2847                          */
2848                         new_bmcr |= BMCR_SPEED1000;
2849
2850                         /* Force a linkdown */
2851                         if (netif_carrier_ok(tp->dev)) {
2852                                 u32 adv;
2853
2854                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2855                                 adv &= ~(ADVERTISE_1000XFULL |
2856                                          ADVERTISE_1000XHALF |
2857                                          ADVERTISE_SLCT);
2858                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2859                                 tg3_writephy(tp, MII_BMCR, bmcr |
2860                                                            BMCR_ANRESTART |
2861                                                            BMCR_ANENABLE);
2862                                 udelay(10);
2863                                 netif_carrier_off(tp->dev);
2864                         }
2865                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2866                         bmcr = new_bmcr;
2867                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2870                             ASIC_REV_5714) {
2871                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2872                                         bmsr |= BMSR_LSTATUS;
2873                                 else
2874                                         bmsr &= ~BMSR_LSTATUS;
2875                         }
2876                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2877                 }
2878         }
2879
2880         if (bmsr & BMSR_LSTATUS) {
2881                 current_speed = SPEED_1000;
2882                 current_link_up = 1;
2883                 if (bmcr & BMCR_FULLDPLX)
2884                         current_duplex = DUPLEX_FULL;
2885                 else
2886                         current_duplex = DUPLEX_HALF;
2887
2888                 if (bmcr & BMCR_ANENABLE) {
2889                         u32 local_adv, remote_adv, common;
2890
2891                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2892                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2893                         common = local_adv & remote_adv;
2894                         if (common & (ADVERTISE_1000XHALF |
2895                                       ADVERTISE_1000XFULL)) {
2896                                 if (common & ADVERTISE_1000XFULL)
2897                                         current_duplex = DUPLEX_FULL;
2898                                 else
2899                                         current_duplex = DUPLEX_HALF;
2900
2901                                 tg3_setup_flow_control(tp, local_adv,
2902                                                        remote_adv);
2903                         }
2904                         else
2905                                 current_link_up = 0;
2906                 }
2907         }
2908
2909         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2910         if (tp->link_config.active_duplex == DUPLEX_HALF)
2911                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2912
2913         tw32_f(MAC_MODE, tp->mac_mode);
2914         udelay(40);
2915
2916         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2917
2918         tp->link_config.active_speed = current_speed;
2919         tp->link_config.active_duplex = current_duplex;
2920
2921         if (current_link_up != netif_carrier_ok(tp->dev)) {
2922                 if (current_link_up)
2923                         netif_carrier_on(tp->dev);
2924                 else {
2925                         netif_carrier_off(tp->dev);
2926                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927                 }
2928                 tg3_link_report(tp);
2929         }
2930         return err;
2931 }
2932
2933 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2934 {
2935         if (tp->serdes_counter) {
2936                 /* Give autoneg time to complete. */
2937                 tp->serdes_counter--;
2938                 return;
2939         }
2940         if (!netif_carrier_ok(tp->dev) &&
2941             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2942                 u32 bmcr;
2943
2944                 tg3_readphy(tp, MII_BMCR, &bmcr);
2945                 if (bmcr & BMCR_ANENABLE) {
2946                         u32 phy1, phy2;
2947
2948                         /* Select shadow register 0x1f */
2949                         tg3_writephy(tp, 0x1c, 0x7c00);
2950                         tg3_readphy(tp, 0x1c, &phy1);
2951
2952                         /* Select expansion interrupt status register */
2953                         tg3_writephy(tp, 0x17, 0x0f01);
2954                         tg3_readphy(tp, 0x15, &phy2);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956
2957                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2958                                 /* We have signal detect and not receiving
2959                                  * config code words, link is up by parallel
2960                                  * detection.
2961                                  */
2962
2963                                 bmcr &= ~BMCR_ANENABLE;
2964                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2965                                 tg3_writephy(tp, MII_BMCR, bmcr);
2966                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2967                         }
2968                 }
2969         }
2970         else if (netif_carrier_ok(tp->dev) &&
2971                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2972                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2973                 u32 phy2;
2974
2975                 /* Select expansion interrupt status register */
2976                 tg3_writephy(tp, 0x17, 0x0f01);
2977                 tg3_readphy(tp, 0x15, &phy2);
2978                 if (phy2 & 0x20) {
2979                         u32 bmcr;
2980
2981                         /* Config code words received, turn on autoneg. */
2982                         tg3_readphy(tp, MII_BMCR, &bmcr);
2983                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2984
2985                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2986
2987                 }
2988         }
2989 }
2990
2991 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2992 {
2993         int err;
2994
2995         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2996                 err = tg3_setup_fiber_phy(tp, force_reset);
2997         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2998                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2999         } else {
3000                 err = tg3_setup_copper_phy(tp, force_reset);
3001         }
3002
3003         if (tp->link_config.active_speed == SPEED_1000 &&
3004             tp->link_config.active_duplex == DUPLEX_HALF)
3005                 tw32(MAC_TX_LENGTHS,
3006                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3007                       (6 << TX_LENGTHS_IPG_SHIFT) |
3008                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3009         else
3010                 tw32(MAC_TX_LENGTHS,
3011                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3012                       (6 << TX_LENGTHS_IPG_SHIFT) |
3013                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3014
3015         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3016                 if (netif_carrier_ok(tp->dev)) {
3017                         tw32(HOSTCC_STAT_COAL_TICKS,
3018                              tp->coal.stats_block_coalesce_usecs);
3019                 } else {
3020                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3021                 }
3022         }
3023
3024         return err;
3025 }
3026
3027 /* This is called whenever we suspect that the system chipset is re-
3028  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3029  * is bogus tx completions. We try to recover by setting the
3030  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3031  * in the workqueue.
3032  */
3033 static void tg3_tx_recover(struct tg3 *tp)
3034 {
3035         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3036                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3037
3038         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3039                "mapped I/O cycles to the network device, attempting to "
3040                "recover. Please report the problem to the driver maintainer "
3041                "and include system chipset information.\n", tp->dev->name);
3042
3043         spin_lock(&tp->lock);
3044         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3045         spin_unlock(&tp->lock);
3046 }
3047
3048 static inline u32 tg3_tx_avail(struct tg3 *tp)
3049 {
3050         smp_mb();
3051         return (tp->tx_pending -
3052                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3053 }
3054
3055 /* Tigon3 never reports partial packet sends.  So we do not
3056  * need special logic to handle SKBs that have not had all
3057  * of their frags sent yet, like SunGEM does.
3058  */
3059 static void tg3_tx(struct tg3 *tp)
3060 {
3061         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3062         u32 sw_idx = tp->tx_cons;
3063
3064         while (sw_idx != hw_idx) {
3065                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3066                 struct sk_buff *skb = ri->skb;
3067                 int i, tx_bug = 0;
3068
3069                 if (unlikely(skb == NULL)) {
3070                         tg3_tx_recover(tp);
3071                         return;
3072                 }
3073
3074                 pci_unmap_single(tp->pdev,
3075                                  pci_unmap_addr(ri, mapping),
3076                                  skb_headlen(skb),
3077                                  PCI_DMA_TODEVICE);
3078
3079                 ri->skb = NULL;
3080
3081                 sw_idx = NEXT_TX(sw_idx);
3082
3083                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3084                         ri = &tp->tx_buffers[sw_idx];
3085                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3086                                 tx_bug = 1;
3087
3088                         pci_unmap_page(tp->pdev,
3089                                        pci_unmap_addr(ri, mapping),
3090                                        skb_shinfo(skb)->frags[i].size,
3091                                        PCI_DMA_TODEVICE);
3092
3093                         sw_idx = NEXT_TX(sw_idx);
3094                 }
3095
3096                 dev_kfree_skb(skb);
3097
3098                 if (unlikely(tx_bug)) {
3099                         tg3_tx_recover(tp);
3100                         return;
3101                 }
3102         }
3103
3104         tp->tx_cons = sw_idx;
3105
3106         /* Need to make the tx_cons update visible to tg3_start_xmit()
3107          * before checking for netif_queue_stopped().  Without the
3108          * memory barrier, there is a small possibility that tg3_start_xmit()
3109          * will miss it and cause the queue to be stopped forever.
3110          */
3111         smp_mb();
3112
3113         if (unlikely(netif_queue_stopped(tp->dev) &&
3114                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3115                 netif_tx_lock(tp->dev);
3116                 if (netif_queue_stopped(tp->dev) &&
3117                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3118                         netif_wake_queue(tp->dev);
3119                 netif_tx_unlock(tp->dev);
3120         }
3121 }
3122
3123 /* Returns size of skb allocated or < 0 on error.
3124  *
3125  * We only need to fill in the address because the other members
3126  * of the RX descriptor are invariant, see tg3_init_rings.
3127  *
3128  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3129  * posting buffers we only dirty the first cache line of the RX
3130  * descriptor (containing the address).  Whereas for the RX status
3131  * buffers the cpu only reads the last cacheline of the RX descriptor
3132  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3133  */
3134 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3135                             int src_idx, u32 dest_idx_unmasked)
3136 {
3137         struct tg3_rx_buffer_desc *desc;
3138         struct ring_info *map, *src_map;
3139         struct sk_buff *skb;
3140         dma_addr_t mapping;
3141         int skb_size, dest_idx;
3142
3143         src_map = NULL;
3144         switch (opaque_key) {
3145         case RXD_OPAQUE_RING_STD:
3146                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3147                 desc = &tp->rx_std[dest_idx];
3148                 map = &tp->rx_std_buffers[dest_idx];
3149                 if (src_idx >= 0)
3150                         src_map = &tp->rx_std_buffers[src_idx];
3151                 skb_size = tp->rx_pkt_buf_sz;
3152                 break;
3153
3154         case RXD_OPAQUE_RING_JUMBO:
3155                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3156                 desc = &tp->rx_jumbo[dest_idx];
3157                 map = &tp->rx_jumbo_buffers[dest_idx];
3158                 if (src_idx >= 0)
3159                         src_map = &tp->rx_jumbo_buffers[src_idx];
3160                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3161                 break;
3162
3163         default:
3164                 return -EINVAL;
3165         };
3166
3167         /* Do not overwrite any of the map or rp information
3168          * until we are sure we can commit to a new buffer.
3169          *
3170          * Callers depend upon this behavior and assume that
3171          * we leave everything unchanged if we fail.
3172          */
3173         skb = netdev_alloc_skb(tp->dev, skb_size);
3174         if (skb == NULL)
3175                 return -ENOMEM;
3176
3177         skb_reserve(skb, tp->rx_offset);
3178
3179         mapping = pci_map_single(tp->pdev, skb->data,
3180                                  skb_size - tp->rx_offset,
3181                                  PCI_DMA_FROMDEVICE);
3182
3183         map->skb = skb;
3184         pci_unmap_addr_set(map, mapping, mapping);
3185
3186         if (src_map != NULL)
3187                 src_map->skb = NULL;
3188
3189         desc->addr_hi = ((u64)mapping >> 32);
3190         desc->addr_lo = ((u64)mapping & 0xffffffff);
3191
3192         return skb_size;
3193 }
3194
3195 /* We only need to move over in the address because the other
3196  * members of the RX descriptor are invariant.  See notes above
3197  * tg3_alloc_rx_skb for full details.
3198  */
3199 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3200                            int src_idx, u32 dest_idx_unmasked)
3201 {
3202         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3203         struct ring_info *src_map, *dest_map;
3204         int dest_idx;
3205
3206         switch (opaque_key) {
3207         case RXD_OPAQUE_RING_STD:
3208                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3209                 dest_desc = &tp->rx_std[dest_idx];
3210                 dest_map = &tp->rx_std_buffers[dest_idx];
3211                 src_desc = &tp->rx_std[src_idx];
3212                 src_map = &tp->rx_std_buffers[src_idx];
3213                 break;
3214
3215         case RXD_OPAQUE_RING_JUMBO:
3216                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3217                 dest_desc = &tp->rx_jumbo[dest_idx];
3218                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3219                 src_desc = &tp->rx_jumbo[src_idx];
3220                 src_map = &tp->rx_jumbo_buffers[src_idx];
3221                 break;
3222
3223         default:
3224                 return;
3225         };
3226
3227         dest_map->skb = src_map->skb;
3228         pci_unmap_addr_set(dest_map, mapping,
3229                            pci_unmap_addr(src_map, mapping));
3230         dest_desc->addr_hi = src_desc->addr_hi;
3231         dest_desc->addr_lo = src_desc->addr_lo;
3232
3233         src_map->skb = NULL;
3234 }
3235
3236 #if TG3_VLAN_TAG_USED
3237 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3238 {
3239         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3240 }
3241 #endif
3242
3243 /* The RX ring scheme is composed of multiple rings which post fresh
3244  * buffers to the chip, and one special ring the chip uses to report
3245  * status back to the host.
3246  *
3247  * The special ring reports the status of received packets to the
3248  * host.  The chip does not write into the original descriptor the
3249  * RX buffer was obtained from.  The chip simply takes the original
3250  * descriptor as provided by the host, updates the status and length
3251  * field, then writes this into the next status ring entry.
3252  *
3253  * Each ring the host uses to post buffers to the chip is described
3254  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3255  * it is first placed into the on-chip ram.  When the packet's length
3256  * is known, it walks down the TG3_BDINFO entries to select the ring.
3257  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3258  * which is within the range of the new packet's length is chosen.
3259  *
3260  * The "separate ring for rx status" scheme may sound queer, but it makes
3261  * sense from a cache coherency perspective.  If only the host writes
3262  * to the buffer post rings, and only the chip writes to the rx status
3263  * rings, then cache lines never move beyond shared-modified state.
3264  * If both the host and chip were to write into the same ring, cache line
3265  * eviction could occur since both entities want it in an exclusive state.
3266  */
3267 static int tg3_rx(struct tg3 *tp, int budget)
3268 {
3269         u32 work_mask, rx_std_posted = 0;
3270         u32 sw_idx = tp->rx_rcb_ptr;
3271         u16 hw_idx;
3272         int received;
3273
3274         hw_idx = tp->hw_status->idx[0].rx_producer;
3275         /*
3276          * We need to order the read of hw_idx and the read of
3277          * the opaque cookie.
3278          */
3279         rmb();
3280         work_mask = 0;
3281         received = 0;
3282         while (sw_idx != hw_idx && budget > 0) {
3283                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3284                 unsigned int len;
3285                 struct sk_buff *skb;
3286                 dma_addr_t dma_addr;
3287                 u32 opaque_key, desc_idx, *post_ptr;
3288
3289                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3290                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3291                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3292                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3293                                                   mapping);
3294                         skb = tp->rx_std_buffers[desc_idx].skb;
3295                         post_ptr = &tp->rx_std_ptr;
3296                         rx_std_posted++;
3297                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3298                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3299                                                   mapping);
3300                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3301                         post_ptr = &tp->rx_jumbo_ptr;
3302                 }
3303                 else {
3304                         goto next_pkt_nopost;
3305                 }
3306
3307                 work_mask |= opaque_key;
3308
3309                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3310                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3311                 drop_it:
3312                         tg3_recycle_rx(tp, opaque_key,
3313                                        desc_idx, *post_ptr);
3314                 drop_it_no_recycle:
3315                         /* Other statistics kept track of by card. */
3316                         tp->net_stats.rx_dropped++;
3317                         goto next_pkt;
3318                 }
3319
3320                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3321
3322                 if (len > RX_COPY_THRESHOLD
3323                         && tp->rx_offset == 2
3324                         /* rx_offset != 2 iff this is a 5701 card running
3325                          * in PCI-X mode [see tg3_get_invariants()] */
3326                 ) {
3327                         int skb_size;
3328
3329                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3330                                                     desc_idx, *post_ptr);
3331                         if (skb_size < 0)
3332                                 goto drop_it;
3333
3334                         pci_unmap_single(tp->pdev, dma_addr,
3335                                          skb_size - tp->rx_offset,
3336                                          PCI_DMA_FROMDEVICE);
3337
3338                         skb_put(skb, len);
3339                 } else {
3340                         struct sk_buff *copy_skb;
3341
3342                         tg3_recycle_rx(tp, opaque_key,
3343                                        desc_idx, *post_ptr);
3344
3345                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3346                         if (copy_skb == NULL)
3347                                 goto drop_it_no_recycle;
3348
3349                         skb_reserve(copy_skb, 2);
3350                         skb_put(copy_skb, len);
3351                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3352                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3353                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3354
3355                         /* We'll reuse the original ring buffer. */
3356                         skb = copy_skb;
3357                 }
3358
3359                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3360                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3361                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3362                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3363                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3364                 else
3365                         skb->ip_summed = CHECKSUM_NONE;
3366
3367                 skb->protocol = eth_type_trans(skb, tp->dev);
3368 #if TG3_VLAN_TAG_USED
3369                 if (tp->vlgrp != NULL &&
3370                     desc->type_flags & RXD_FLAG_VLAN) {
3371                         tg3_vlan_rx(tp, skb,
3372                                     desc->err_vlan & RXD_VLAN_MASK);
3373                 } else
3374 #endif
3375                         netif_receive_skb(skb);
3376
3377                 tp->dev->last_rx = jiffies;
3378                 received++;
3379                 budget--;
3380
3381 next_pkt:
3382                 (*post_ptr)++;
3383
3384                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3385                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3386
3387                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3388                                      TG3_64BIT_REG_LOW, idx);
3389                         work_mask &= ~RXD_OPAQUE_RING_STD;
3390                         rx_std_posted = 0;
3391                 }
3392 next_pkt_nopost:
3393                 sw_idx++;
3394                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3395
3396                 /* Refresh hw_idx to see if there is new work */
3397                 if (sw_idx == hw_idx) {
3398                         hw_idx = tp->hw_status->idx[0].rx_producer;
3399                         rmb();
3400                 }
3401         }
3402
3403         /* ACK the status ring. */
3404         tp->rx_rcb_ptr = sw_idx;
3405         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3406
3407         /* Refill RX ring(s). */
3408         if (work_mask & RXD_OPAQUE_RING_STD) {
3409                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3410                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3411                              sw_idx);
3412         }
3413         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3414                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3415                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3416                              sw_idx);
3417         }
3418         mmiowb();
3419
3420         return received;
3421 }
3422
3423 static int tg3_poll(struct net_device *netdev, int *budget)
3424 {
3425         struct tg3 *tp = netdev_priv(netdev);
3426         struct tg3_hw_status *sblk = tp->hw_status;
3427         int done;
3428
3429         /* handle link change and other phy events */
3430         if (!(tp->tg3_flags &
3431               (TG3_FLAG_USE_LINKCHG_REG |
3432                TG3_FLAG_POLL_SERDES))) {
3433                 if (sblk->status & SD_STATUS_LINK_CHG) {
3434                         sblk->status = SD_STATUS_UPDATED |
3435                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3436                         spin_lock(&tp->lock);
3437                         tg3_setup_phy(tp, 0);
3438                         spin_unlock(&tp->lock);
3439                 }
3440         }
3441
3442         /* run TX completion thread */
3443         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3444                 tg3_tx(tp);
3445                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3446                         netif_rx_complete(netdev);
3447                         schedule_work(&tp->reset_task);
3448                         return 0;
3449                 }
3450         }
3451
3452         /* run RX thread, within the bounds set by NAPI.
3453          * All RX "locking" is done by ensuring outside
3454          * code synchronizes with dev->poll()
3455          */
3456         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3457                 int orig_budget = *budget;
3458                 int work_done;
3459
3460                 if (orig_budget > netdev->quota)
3461                         orig_budget = netdev->quota;
3462
3463                 work_done = tg3_rx(tp, orig_budget);
3464
3465                 *budget -= work_done;
3466                 netdev->quota -= work_done;
3467         }
3468
3469         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3470                 tp->last_tag = sblk->status_tag;
3471                 rmb();
3472         } else
3473                 sblk->status &= ~SD_STATUS_UPDATED;
3474
3475         /* if no more work, tell net stack and NIC we're done */
3476         done = !tg3_has_work(tp);
3477         if (done) {
3478                 netif_rx_complete(netdev);
3479                 tg3_restart_ints(tp);
3480         }
3481
3482         return (done ? 0 : 1);
3483 }
3484
3485 static void tg3_irq_quiesce(struct tg3 *tp)
3486 {
3487         BUG_ON(tp->irq_sync);
3488
3489         tp->irq_sync = 1;
3490         smp_mb();
3491
3492         synchronize_irq(tp->pdev->irq);
3493 }
3494
3495 static inline int tg3_irq_sync(struct tg3 *tp)
3496 {
3497         return tp->irq_sync;
3498 }
3499
3500 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3501  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3502  * with as well.  Most of the time, this is not necessary except when
3503  * shutting down the device.
3504  */
3505 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3506 {
3507         if (irq_sync)
3508                 tg3_irq_quiesce(tp);
3509         spin_lock_bh(&tp->lock);
3510 }
3511
3512 static inline void tg3_full_unlock(struct tg3 *tp)
3513 {
3514         spin_unlock_bh(&tp->lock);
3515 }
3516
3517 /* One-shot MSI handler - Chip automatically disables interrupt
3518  * after sending MSI so driver doesn't have to do it.
3519  */
3520 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3521 {
3522         struct net_device *dev = dev_id;
3523         struct tg3 *tp = netdev_priv(dev);
3524
3525         prefetch(tp->hw_status);
3526         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3527
3528         if (likely(!tg3_irq_sync(tp)))
3529                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3530
3531         return IRQ_HANDLED;
3532 }
3533
3534 /* MSI ISR - No need to check for interrupt sharing and no need to
3535  * flush status block and interrupt mailbox. PCI ordering rules
3536  * guarantee that MSI will arrive after the status block.
3537  */
3538 static irqreturn_t tg3_msi(int irq, void *dev_id)
3539 {
3540         struct net_device *dev = dev_id;
3541         struct tg3 *tp = netdev_priv(dev);
3542
3543         prefetch(tp->hw_status);
3544         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3545         /*
3546          * Writing any value to intr-mbox-0 clears PCI INTA# and
3547          * chip-internal interrupt pending events.
3548          * Writing non-zero to intr-mbox-0 additional tells the
3549          * NIC to stop sending us irqs, engaging "in-intr-handler"
3550          * event coalescing.
3551          */
3552         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3553         if (likely(!tg3_irq_sync(tp)))
3554                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3555
3556         return IRQ_RETVAL(1);
3557 }
3558
3559 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3560 {
3561         struct net_device *dev = dev_id;
3562         struct tg3 *tp = netdev_priv(dev);
3563         struct tg3_hw_status *sblk = tp->hw_status;
3564         unsigned int handled = 1;
3565
3566         /* In INTx mode, it is possible for the interrupt to arrive at
3567          * the CPU before the status block posted prior to the interrupt.
3568          * Reading the PCI State register will confirm whether the
3569          * interrupt is ours and will flush the status block.
3570          */
3571         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3572                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3573                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3574                         handled = 0;
3575                         goto out;
3576                 }
3577         }
3578
3579         /*
3580          * Writing any value to intr-mbox-0 clears PCI INTA# and
3581          * chip-internal interrupt pending events.
3582          * Writing non-zero to intr-mbox-0 additional tells the
3583          * NIC to stop sending us irqs, engaging "in-intr-handler"
3584          * event coalescing.
3585          */
3586         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3587         if (tg3_irq_sync(tp))
3588                 goto out;
3589         sblk->status &= ~SD_STATUS_UPDATED;
3590         if (likely(tg3_has_work(tp))) {
3591                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3592                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3593         } else {
3594                 /* No work, shared interrupt perhaps?  re-enable
3595                  * interrupts, and flush that PCI write
3596                  */
3597                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3598                                0x00000000);
3599         }
3600 out:
3601         return IRQ_RETVAL(handled);
3602 }
3603
3604 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3605 {
3606         struct net_device *dev = dev_id;
3607         struct tg3 *tp = netdev_priv(dev);
3608         struct tg3_hw_status *sblk = tp->hw_status;
3609         unsigned int handled = 1;
3610
3611         /* In INTx mode, it is possible for the interrupt to arrive at
3612          * the CPU before the status block posted prior to the interrupt.
3613          * Reading the PCI State register will confirm whether the
3614          * interrupt is ours and will flush the status block.
3615          */
3616         if (unlikely(sblk->status_tag == tp->last_tag)) {
3617                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3618                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3619                         handled = 0;
3620                         goto out;
3621                 }
3622         }
3623
3624         /*
3625          * writing any value to intr-mbox-0 clears PCI INTA# and
3626          * chip-internal interrupt pending events.
3627          * writing non-zero to intr-mbox-0 additional tells the
3628          * NIC to stop sending us irqs, engaging "in-intr-handler"
3629          * event coalescing.
3630          */
3631         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3632         if (tg3_irq_sync(tp))
3633                 goto out;
3634         if (netif_rx_schedule_prep(dev)) {
3635                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3636                 /* Update last_tag to mark that this status has been
3637                  * seen. Because interrupt may be shared, we may be
3638                  * racing with tg3_poll(), so only update last_tag
3639                  * if tg3_poll() is not scheduled.
3640                  */
3641                 tp->last_tag = sblk->status_tag;
3642                 __netif_rx_schedule(dev);
3643         }
3644 out:
3645         return IRQ_RETVAL(handled);
3646 }
3647
3648 /* ISR for interrupt test */
3649 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3650 {
3651         struct net_device *dev = dev_id;
3652         struct tg3 *tp = netdev_priv(dev);
3653         struct tg3_hw_status *sblk = tp->hw_status;
3654
3655         if ((sblk->status & SD_STATUS_UPDATED) ||
3656             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3657                 tg3_disable_ints(tp);
3658                 return IRQ_RETVAL(1);
3659         }
3660         return IRQ_RETVAL(0);
3661 }
3662
3663 static int tg3_init_hw(struct tg3 *, int);
3664 static int tg3_halt(struct tg3 *, int, int);
3665
3666 /* Restart hardware after configuration changes, self-test, etc.
3667  * Invoked with tp->lock held.
3668  */
3669 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3670 {
3671         int err;
3672
3673         err = tg3_init_hw(tp, reset_phy);
3674         if (err) {
3675                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3676                        "aborting.\n", tp->dev->name);
3677                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3678                 tg3_full_unlock(tp);
3679                 del_timer_sync(&tp->timer);
3680                 tp->irq_sync = 0;
3681                 netif_poll_enable(tp->dev);
3682                 dev_close(tp->dev);
3683                 tg3_full_lock(tp, 0);
3684         }
3685         return err;
3686 }
3687
3688 #ifdef CONFIG_NET_POLL_CONTROLLER
3689 static void tg3_poll_controller(struct net_device *dev)
3690 {
3691         struct tg3 *tp = netdev_priv(dev);
3692
3693         tg3_interrupt(tp->pdev->irq, dev);
3694 }
3695 #endif
3696
3697 static void tg3_reset_task(struct work_struct *work)
3698 {
3699         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3700         unsigned int restart_timer;
3701
3702         tg3_full_lock(tp, 0);
3703         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3704
3705         if (!netif_running(tp->dev)) {
3706                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3707                 tg3_full_unlock(tp);
3708                 return;
3709         }
3710
3711         tg3_full_unlock(tp);
3712
3713         tg3_netif_stop(tp);
3714
3715         tg3_full_lock(tp, 1);
3716
3717         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3718         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3719
3720         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3721                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3722                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3723                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3724                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3725         }
3726
3727         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3728         if (tg3_init_hw(tp, 1))
3729                 goto out;
3730
3731         tg3_netif_start(tp);
3732
3733         if (restart_timer)
3734                 mod_timer(&tp->timer, jiffies + 1);
3735
3736 out:
3737         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3738
3739         tg3_full_unlock(tp);
3740 }
3741
3742 static void tg3_dump_short_state(struct tg3 *tp)
3743 {
3744         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3745                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3746         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3747                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3748 }
3749
3750 static void tg3_tx_timeout(struct net_device *dev)
3751 {
3752         struct tg3 *tp = netdev_priv(dev);
3753
3754         if (netif_msg_tx_err(tp)) {
3755                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3756                        dev->name);
3757                 tg3_dump_short_state(tp);
3758         }
3759
3760         schedule_work(&tp->reset_task);
3761 }
3762
3763 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3764 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3765 {
3766         u32 base = (u32) mapping & 0xffffffff;
3767
3768         return ((base > 0xffffdcc0) &&
3769                 (base + len + 8 < base));
3770 }
3771
3772 /* Test for DMA addresses > 40-bit */
3773 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3774                                           int len)
3775 {
3776 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3777         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3778                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3779         return 0;
3780 #else
3781         return 0;
3782 #endif
3783 }
3784
3785 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3786
3787 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3788 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3789                                        u32 last_plus_one, u32 *start,
3790                                        u32 base_flags, u32 mss)
3791 {
3792         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3793         dma_addr_t new_addr = 0;
3794         u32 entry = *start;
3795         int i, ret = 0;
3796
3797         if (!new_skb) {
3798                 ret = -1;
3799         } else {
3800                 /* New SKB is guaranteed to be linear. */
3801                 entry = *start;
3802                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3803                                           PCI_DMA_TODEVICE);
3804                 /* Make sure new skb does not cross any 4G boundaries.
3805                  * Drop the packet if it does.
3806                  */
3807                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3808                         ret = -1;
3809                         dev_kfree_skb(new_skb);
3810                         new_skb = NULL;
3811                 } else {
3812                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3813                                     base_flags, 1 | (mss << 1));
3814                         *start = NEXT_TX(entry);
3815                 }
3816         }
3817
3818         /* Now clean up the sw ring entries. */
3819         i = 0;
3820         while (entry != last_plus_one) {
3821                 int len;
3822
3823                 if (i == 0)
3824                         len = skb_headlen(skb);
3825                 else
3826                         len = skb_shinfo(skb)->frags[i-1].size;
3827                 pci_unmap_single(tp->pdev,
3828                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3829                                  len, PCI_DMA_TODEVICE);
3830                 if (i == 0) {
3831                         tp->tx_buffers[entry].skb = new_skb;
3832                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3833                 } else {
3834                         tp->tx_buffers[entry].skb = NULL;
3835                 }
3836                 entry = NEXT_TX(entry);
3837                 i++;
3838         }
3839
3840         dev_kfree_skb(skb);
3841
3842         return ret;
3843 }
3844
3845 static void tg3_set_txd(struct tg3 *tp, int entry,
3846                         dma_addr_t mapping, int len, u32 flags,
3847                         u32 mss_and_is_end)
3848 {
3849         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3850         int is_end = (mss_and_is_end & 0x1);
3851         u32 mss = (mss_and_is_end >> 1);
3852         u32 vlan_tag = 0;
3853
3854         if (is_end)
3855                 flags |= TXD_FLAG_END;
3856         if (flags & TXD_FLAG_VLAN) {
3857                 vlan_tag = flags >> 16;
3858                 flags &= 0xffff;
3859         }
3860         vlan_tag |= (mss << TXD_MSS_SHIFT);
3861
3862         txd->addr_hi = ((u64) mapping >> 32);
3863         txd->addr_lo = ((u64) mapping & 0xffffffff);
3864         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3865         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3866 }
3867
3868 /* hard_start_xmit for devices that don't have any bugs and
3869  * support TG3_FLG2_HW_TSO_2 only.
3870  */
3871 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3872 {
3873         struct tg3 *tp = netdev_priv(dev);
3874         dma_addr_t mapping;
3875         u32 len, entry, base_flags, mss;
3876
3877         len = skb_headlen(skb);
3878
3879         /* We are running in BH disabled context with netif_tx_lock
3880          * and TX reclaim runs via tp->poll inside of a software
3881          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3882          * no IRQ context deadlocks to worry about either.  Rejoice!
3883          */
3884         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3885                 if (!netif_queue_stopped(dev)) {
3886                         netif_stop_queue(dev);
3887
3888                         /* This is a hard error, log it. */
3889                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3890                                "queue awake!\n", dev->name);
3891                 }
3892                 return NETDEV_TX_BUSY;
3893         }
3894
3895         entry = tp->tx_prod;
3896         base_flags = 0;
3897         mss = 0;
3898         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3899                 int tcp_opt_len, ip_tcp_len;
3900
3901                 if (skb_header_cloned(skb) &&
3902                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3903                         dev_kfree_skb(skb);
3904                         goto out_unlock;
3905                 }
3906
3907                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3908                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3909                 else {
3910                         struct iphdr *iph = ip_hdr(skb);
3911
3912                         tcp_opt_len = tcp_optlen(skb);
3913                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3914
3915                         iph->check = 0;
3916                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3917                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3918                 }
3919
3920                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3921                                TXD_FLAG_CPU_POST_DMA);
3922
3923                 tcp_hdr(skb)->check = 0;
3924
3925         }
3926         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3927                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3928 #if TG3_VLAN_TAG_USED
3929         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3930                 base_flags |= (TXD_FLAG_VLAN |
3931                                (vlan_tx_tag_get(skb) << 16));
3932 #endif
3933
3934         /* Queue skb data, a.k.a. the main skb fragment. */
3935         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3936
3937         tp->tx_buffers[entry].skb = skb;
3938         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3939
3940         tg3_set_txd(tp, entry, mapping, len, base_flags,
3941                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3942
3943         entry = NEXT_TX(entry);
3944
3945         /* Now loop through additional data fragments, and queue them. */
3946         if (skb_shinfo(skb)->nr_frags > 0) {
3947                 unsigned int i, last;
3948
3949                 last = skb_shinfo(skb)->nr_frags - 1;
3950                 for (i = 0; i <= last; i++) {
3951                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3952
3953                         len = frag->size;
3954                         mapping = pci_map_page(tp->pdev,
3955                                                frag->page,
3956                                                frag->page_offset,
3957                                                len, PCI_DMA_TODEVICE);
3958
3959                         tp->tx_buffers[entry].skb = NULL;
3960                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3961
3962                         tg3_set_txd(tp, entry, mapping, len,
3963                                     base_flags, (i == last) | (mss << 1));
3964
3965                         entry = NEXT_TX(entry);
3966                 }
3967         }
3968
3969         /* Packets are ready, update Tx producer idx local and on card. */
3970         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3971
3972         tp->tx_prod = entry;
3973         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3974                 netif_stop_queue(dev);
3975                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3976                         netif_wake_queue(tp->dev);
3977         }
3978
3979 out_unlock:
3980         mmiowb();
3981
3982         dev->trans_start = jiffies;
3983
3984         return NETDEV_TX_OK;
3985 }
3986
3987 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3988
3989 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3990  * TSO header is greater than 80 bytes.
3991  */
3992 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3993 {
3994         struct sk_buff *segs, *nskb;
3995
3996         /* Estimate the number of fragments in the worst case */
3997         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3998                 netif_stop_queue(tp->dev);
3999                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4000                         return NETDEV_TX_BUSY;
4001
4002                 netif_wake_queue(tp->dev);
4003         }
4004
4005         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4006         if (unlikely(IS_ERR(segs)))
4007                 goto tg3_tso_bug_end;
4008
4009         do {
4010                 nskb = segs;
4011                 segs = segs->next;
4012                 nskb->next = NULL;
4013                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4014         } while (segs);
4015
4016 tg3_tso_bug_end:
4017         dev_kfree_skb(skb);
4018
4019         return NETDEV_TX_OK;
4020 }
4021
4022 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4023  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4024  */
4025 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4026 {
4027         struct tg3 *tp = netdev_priv(dev);
4028         dma_addr_t mapping;
4029         u32 len, entry, base_flags, mss;
4030         int would_hit_hwbug;
4031
4032         len = skb_headlen(skb);
4033
4034         /* We are running in BH disabled context with netif_tx_lock
4035          * and TX reclaim runs via tp->poll inside of a software
4036          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4037          * no IRQ context deadlocks to worry about either.  Rejoice!
4038          */
4039         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4040                 if (!netif_queue_stopped(dev)) {
4041                         netif_stop_queue(dev);
4042
4043                         /* This is a hard error, log it. */
4044                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4045                                "queue awake!\n", dev->name);
4046                 }
4047                 return NETDEV_TX_BUSY;
4048         }
4049
4050         entry = tp->tx_prod;
4051         base_flags = 0;
4052         if (skb->ip_summed == CHECKSUM_PARTIAL)
4053                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4054         mss = 0;
4055         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4056                 struct iphdr *iph;
4057                 int tcp_opt_len, ip_tcp_len, hdr_len;
4058
4059                 if (skb_header_cloned(skb) &&
4060                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4061                         dev_kfree_skb(skb);
4062                         goto out_unlock;
4063                 }
4064
4065                 tcp_opt_len = tcp_optlen(skb);
4066                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4067
4068                 hdr_len = ip_tcp_len + tcp_opt_len;
4069                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4070                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4071                         return (tg3_tso_bug(tp, skb));
4072
4073                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4074                                TXD_FLAG_CPU_POST_DMA);
4075
4076                 iph = ip_hdr(skb);
4077                 iph->check = 0;
4078                 iph->tot_len = htons(mss + hdr_len);
4079                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4080                         tcp_hdr(skb)->check = 0;
4081                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4082                 } else
4083                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4084                                                                  iph->daddr, 0,
4085                                                                  IPPROTO_TCP,
4086                                                                  0);
4087
4088                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4089                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4090                         if (tcp_opt_len || iph->ihl > 5) {
4091                                 int tsflags;
4092
4093                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4094                                 mss |= (tsflags << 11);
4095                         }
4096                 } else {
4097                         if (tcp_opt_len || iph->ihl > 5) {
4098                                 int tsflags;
4099
4100                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4101                                 base_flags |= tsflags << 12;
4102                         }
4103                 }
4104         }
4105 #if TG3_VLAN_TAG_USED
4106         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4107                 base_flags |= (TXD_FLAG_VLAN |
4108                                (vlan_tx_tag_get(skb) << 16));
4109 #endif
4110
4111         /* Queue skb data, a.k.a. the main skb fragment. */
4112         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4113
4114         tp->tx_buffers[entry].skb = skb;
4115         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4116
4117         would_hit_hwbug = 0;
4118
4119         if (tg3_4g_overflow_test(mapping, len))
4120                 would_hit_hwbug = 1;
4121
4122         tg3_set_txd(tp, entry, mapping, len, base_flags,
4123                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4124
4125         entry = NEXT_TX(entry);
4126
4127         /* Now loop through additional data fragments, and queue them. */
4128         if (skb_shinfo(skb)->nr_frags > 0) {
4129                 unsigned int i, last;
4130
4131                 last = skb_shinfo(skb)->nr_frags - 1;
4132                 for (i = 0; i <= last; i++) {
4133                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4134
4135                         len = frag->size;
4136                         mapping = pci_map_page(tp->pdev,
4137                                                frag->page,
4138                                                frag->page_offset,
4139                                                len, PCI_DMA_TODEVICE);
4140
4141                         tp->tx_buffers[entry].skb = NULL;
4142                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4143
4144                         if (tg3_4g_overflow_test(mapping, len))
4145                                 would_hit_hwbug = 1;
4146
4147                         if (tg3_40bit_overflow_test(tp, mapping, len))
4148                                 would_hit_hwbug = 1;
4149
4150                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4151                                 tg3_set_txd(tp, entry, mapping, len,
4152                                             base_flags, (i == last)|(mss << 1));
4153                         else
4154                                 tg3_set_txd(tp, entry, mapping, len,
4155                                             base_flags, (i == last));
4156
4157                         entry = NEXT_TX(entry);
4158                 }
4159         }
4160
4161         if (would_hit_hwbug) {
4162                 u32 last_plus_one = entry;
4163                 u32 start;
4164
4165                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4166                 start &= (TG3_TX_RING_SIZE - 1);
4167
4168                 /* If the workaround fails due to memory/mapping
4169                  * failure, silently drop this packet.
4170                  */
4171                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4172                                                 &start, base_flags, mss))
4173                         goto out_unlock;
4174
4175                 entry = start;
4176         }
4177
4178         /* Packets are ready, update Tx producer idx local and on card. */
4179         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4180
4181         tp->tx_prod = entry;
4182         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4183                 netif_stop_queue(dev);
4184                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4185                         netif_wake_queue(tp->dev);
4186         }
4187
4188 out_unlock:
4189         mmiowb();
4190
4191         dev->trans_start = jiffies;
4192
4193         return NETDEV_TX_OK;
4194 }
4195
4196 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4197                                int new_mtu)
4198 {
4199         dev->mtu = new_mtu;
4200
4201         if (new_mtu > ETH_DATA_LEN) {
4202                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4203                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4204                         ethtool_op_set_tso(dev, 0);
4205                 }
4206                 else
4207                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4208         } else {
4209                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4210                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4211                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4212         }
4213 }
4214
4215 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4216 {
4217         struct tg3 *tp = netdev_priv(dev);
4218         int err;
4219
4220         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4221                 return -EINVAL;
4222
4223         if (!netif_running(dev)) {
4224                 /* We'll just catch it later when the
4225                  * device is up'd.
4226                  */
4227                 tg3_set_mtu(dev, tp, new_mtu);
4228                 return 0;
4229         }
4230
4231         tg3_netif_stop(tp);
4232
4233         tg3_full_lock(tp, 1);
4234
4235         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4236
4237         tg3_set_mtu(dev, tp, new_mtu);
4238
4239         err = tg3_restart_hw(tp, 0);
4240
4241         if (!err)
4242                 tg3_netif_start(tp);
4243
4244         tg3_full_unlock(tp);
4245
4246         return err;
4247 }
4248
4249 /* Free up pending packets in all rx/tx rings.
4250  *
4251  * The chip has been shut down and the driver detached from
4252  * the networking, so no interrupts or new tx packets will
4253  * end up in the driver.  tp->{tx,}lock is not held and we are not
4254  * in an interrupt context and thus may sleep.
4255  */
4256 static void tg3_free_rings(struct tg3 *tp)
4257 {
4258         struct ring_info *rxp;
4259         int i;
4260
4261         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4262                 rxp = &tp->rx_std_buffers[i];
4263
4264                 if (rxp->skb == NULL)
4265                         continue;
4266                 pci_unmap_single(tp->pdev,
4267                                  pci_unmap_addr(rxp, mapping),
4268                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4269                                  PCI_DMA_FROMDEVICE);
4270                 dev_kfree_skb_any(rxp->skb);
4271                 rxp->skb = NULL;
4272         }
4273
4274         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4275                 rxp = &tp->rx_jumbo_buffers[i];
4276
4277                 if (rxp->skb == NULL)
4278                         continue;
4279                 pci_unmap_single(tp->pdev,
4280                                  pci_unmap_addr(rxp, mapping),
4281                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4282                                  PCI_DMA_FROMDEVICE);
4283                 dev_kfree_skb_any(rxp->skb);
4284                 rxp->skb = NULL;
4285         }
4286
4287         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4288                 struct tx_ring_info *txp;
4289                 struct sk_buff *skb;
4290                 int j;
4291
4292                 txp = &tp->tx_buffers[i];
4293                 skb = txp->skb;
4294
4295                 if (skb == NULL) {
4296                         i++;
4297                         continue;
4298                 }
4299
4300                 pci_unmap_single(tp->pdev,
4301                                  pci_unmap_addr(txp, mapping),
4302                                  skb_headlen(skb),
4303                                  PCI_DMA_TODEVICE);
4304                 txp->skb = NULL;
4305
4306                 i++;
4307
4308                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4309                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4310                         pci_unmap_page(tp->pdev,
4311                                        pci_unmap_addr(txp, mapping),
4312                                        skb_shinfo(skb)->frags[j].size,
4313                                        PCI_DMA_TODEVICE);
4314                         i++;
4315                 }
4316
4317                 dev_kfree_skb_any(skb);
4318         }
4319 }
4320
4321 /* Initialize tx/rx rings for packet processing.
4322  *
4323  * The chip has been shut down and the driver detached from
4324  * the networking, so no interrupts or new tx packets will
4325  * end up in the driver.  tp->{tx,}lock are held and thus
4326  * we may not sleep.
4327  */
4328 static int tg3_init_rings(struct tg3 *tp)
4329 {
4330         u32 i;
4331
4332         /* Free up all the SKBs. */
4333         tg3_free_rings(tp);
4334
4335         /* Zero out all descriptors. */
4336         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4337         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4338         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4339         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4340
4341         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4342         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4343             (tp->dev->mtu > ETH_DATA_LEN))
4344                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4345
4346         /* Initialize invariants of the rings, we only set this
4347          * stuff once.  This works because the card does not
4348          * write into the rx buffer posting rings.
4349          */
4350         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4351                 struct tg3_rx_buffer_desc *rxd;
4352
4353                 rxd = &tp->rx_std[i];
4354                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4355                         << RXD_LEN_SHIFT;
4356                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4357                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4358                                (i << RXD_OPAQUE_INDEX_SHIFT));
4359         }
4360
4361         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4362                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4363                         struct tg3_rx_buffer_desc *rxd;
4364
4365                         rxd = &tp->rx_jumbo[i];
4366                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4367                                 << RXD_LEN_SHIFT;
4368                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4369                                 RXD_FLAG_JUMBO;
4370                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4371                                (i << RXD_OPAQUE_INDEX_SHIFT));
4372                 }
4373         }
4374
4375         /* Now allocate fresh SKBs for each rx ring. */
4376         for (i = 0; i < tp->rx_pending; i++) {
4377                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4378                         printk(KERN_WARNING PFX
4379                                "%s: Using a smaller RX standard ring, "
4380                                "only %d out of %d buffers were allocated "
4381                                "successfully.\n",
4382                                tp->dev->name, i, tp->rx_pending);
4383                         if (i == 0)
4384                                 return -ENOMEM;
4385                         tp->rx_pending = i;
4386                         break;
4387                 }
4388         }
4389
4390         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4391                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4392                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4393                                              -1, i) < 0) {
4394                                 printk(KERN_WARNING PFX
4395                                        "%s: Using a smaller RX jumbo ring, "
4396                                        "only %d out of %d buffers were "
4397                                        "allocated successfully.\n",
4398                                        tp->dev->name, i, tp->rx_jumbo_pending);
4399                                 if (i == 0) {
4400                                         tg3_free_rings(tp);
4401                                         return -ENOMEM;
4402                                 }
4403                                 tp->rx_jumbo_pending = i;
4404                                 break;
4405                         }
4406                 }
4407         }
4408         return 0;
4409 }
4410
4411 /*
4412  * Must not be invoked with interrupt sources disabled and
4413  * the hardware shutdown down.
4414  */
4415 static void tg3_free_consistent(struct tg3 *tp)
4416 {
4417         kfree(tp->rx_std_buffers);
4418         tp->rx_std_buffers = NULL;
4419         if (tp->rx_std) {
4420                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4421                                     tp->rx_std, tp->rx_std_mapping);
4422                 tp->rx_std = NULL;
4423         }
4424         if (tp->rx_jumbo) {
4425                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4426                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4427                 tp->rx_jumbo = NULL;
4428         }
4429         if (tp->rx_rcb) {
4430                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4431                                     tp->rx_rcb, tp->rx_rcb_mapping);
4432                 tp->rx_rcb = NULL;
4433         }
4434         if (tp->tx_ring) {
4435                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4436                         tp->tx_ring, tp->tx_desc_mapping);
4437                 tp->tx_ring = NULL;
4438         }
4439         if (tp->hw_status) {
4440                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4441                                     tp->hw_status, tp->status_mapping);
4442                 tp->hw_status = NULL;
4443         }
4444         if (tp->hw_stats) {
4445                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4446                                     tp->hw_stats, tp->stats_mapping);
4447                 tp->hw_stats = NULL;
4448         }
4449 }
4450
4451 /*
4452  * Must not be invoked with interrupt sources disabled and
4453  * the hardware shutdown down.  Can sleep.
4454  */
4455 static int tg3_alloc_consistent(struct tg3 *tp)
4456 {
4457         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4458                                       (TG3_RX_RING_SIZE +
4459                                        TG3_RX_JUMBO_RING_SIZE)) +
4460                                      (sizeof(struct tx_ring_info) *
4461                                       TG3_TX_RING_SIZE),
4462                                      GFP_KERNEL);
4463         if (!tp->rx_std_buffers)
4464                 return -ENOMEM;
4465
4466         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4467         tp->tx_buffers = (struct tx_ring_info *)
4468                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4469
4470         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4471                                           &tp->rx_std_mapping);
4472         if (!tp->rx_std)
4473                 goto err_out;
4474
4475         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4476                                             &tp->rx_jumbo_mapping);
4477
4478         if (!tp->rx_jumbo)
4479                 goto err_out;
4480
4481         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4482                                           &tp->rx_rcb_mapping);
4483         if (!tp->rx_rcb)
4484                 goto err_out;
4485
4486         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4487                                            &tp->tx_desc_mapping);
4488         if (!tp->tx_ring)
4489                 goto err_out;
4490
4491         tp->hw_status = pci_alloc_consistent(tp->pdev,
4492                                              TG3_HW_STATUS_SIZE,
4493                                              &tp->status_mapping);
4494         if (!tp->hw_status)
4495                 goto err_out;
4496
4497         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4498                                             sizeof(struct tg3_hw_stats),
4499                                             &tp->stats_mapping);
4500         if (!tp->hw_stats)
4501                 goto err_out;
4502
4503         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4504         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4505
4506         return 0;
4507
4508 err_out:
4509         tg3_free_consistent(tp);
4510         return -ENOMEM;
4511 }
4512
4513 #define MAX_WAIT_CNT 1000
4514
4515 /* To stop a block, clear the enable bit and poll till it
4516  * clears.  tp->lock is held.
4517  */
4518 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4519 {
4520         unsigned int i;
4521         u32 val;
4522
4523         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4524                 switch (ofs) {
4525                 case RCVLSC_MODE:
4526                 case DMAC_MODE:
4527                 case MBFREE_MODE:
4528                 case BUFMGR_MODE:
4529                 case MEMARB_MODE:
4530                         /* We can't enable/disable these bits of the
4531                          * 5705/5750, just say success.
4532                          */
4533                         return 0;
4534
4535                 default:
4536                         break;
4537                 };
4538         }
4539
4540         val = tr32(ofs);
4541         val &= ~enable_bit;
4542         tw32_f(ofs, val);
4543
4544         for (i = 0; i < MAX_WAIT_CNT; i++) {
4545                 udelay(100);
4546                 val = tr32(ofs);
4547                 if ((val & enable_bit) == 0)
4548                         break;
4549         }
4550
4551         if (i == MAX_WAIT_CNT && !silent) {
4552                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4553                        "ofs=%lx enable_bit=%x\n",
4554                        ofs, enable_bit);
4555                 return -ENODEV;
4556         }
4557
4558         return 0;
4559 }
4560
4561 /* tp->lock is held. */
4562 static int tg3_abort_hw(struct tg3 *tp, int silent)
4563 {
4564         int i, err;
4565
4566         tg3_disable_ints(tp);
4567
4568         tp->rx_mode &= ~RX_MODE_ENABLE;
4569         tw32_f(MAC_RX_MODE, tp->rx_mode);
4570         udelay(10);
4571
4572         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4573         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4574         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4575         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4576         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4578
4579         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4581         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4582         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4583         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4585         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4586
4587         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4588         tw32_f(MAC_MODE, tp->mac_mode);
4589         udelay(40);
4590
4591         tp->tx_mode &= ~TX_MODE_ENABLE;
4592         tw32_f(MAC_TX_MODE, tp->tx_mode);
4593
4594         for (i = 0; i < MAX_WAIT_CNT; i++) {
4595                 udelay(100);
4596                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4597                         break;
4598         }
4599         if (i >= MAX_WAIT_CNT) {
4600                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4601                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4602                        tp->dev->name, tr32(MAC_TX_MODE));
4603                 err |= -ENODEV;
4604         }
4605
4606         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4607         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4608         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4609
4610         tw32(FTQ_RESET, 0xffffffff);
4611         tw32(FTQ_RESET, 0x00000000);
4612
4613         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4614         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4615
4616         if (tp->hw_status)
4617                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4618         if (tp->hw_stats)
4619                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4620
4621         return err;
4622 }
4623
4624 /* tp->lock is held. */
4625 static int tg3_nvram_lock(struct tg3 *tp)
4626 {
4627         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4628                 int i;
4629
4630                 if (tp->nvram_lock_cnt == 0) {
4631                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4632                         for (i = 0; i < 8000; i++) {
4633                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4634                                         break;
4635                                 udelay(20);
4636                         }
4637                         if (i == 8000) {
4638                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4639                                 return -ENODEV;
4640                         }
4641                 }
4642                 tp->nvram_lock_cnt++;
4643         }
4644         return 0;
4645 }
4646
4647 /* tp->lock is held. */
4648 static void tg3_nvram_unlock(struct tg3 *tp)
4649 {
4650         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4651                 if (tp->nvram_lock_cnt > 0)
4652                         tp->nvram_lock_cnt--;
4653                 if (tp->nvram_lock_cnt == 0)
4654                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4655         }
4656 }
4657
4658 /* tp->lock is held. */
4659 static void tg3_enable_nvram_access(struct tg3 *tp)
4660 {
4661         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4662             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4663                 u32 nvaccess = tr32(NVRAM_ACCESS);
4664
4665                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4666         }
4667 }
4668
4669 /* tp->lock is held. */
4670 static void tg3_disable_nvram_access(struct tg3 *tp)
4671 {
4672         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4673             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4674                 u32 nvaccess = tr32(NVRAM_ACCESS);
4675
4676                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4677         }
4678 }
4679
4680 /* tp->lock is held. */
4681 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4682 {
4683         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4684                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4685
4686         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4687                 switch (kind) {
4688                 case RESET_KIND_INIT:
4689                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4690                                       DRV_STATE_START);
4691                         break;
4692
4693                 case RESET_KIND_SHUTDOWN:
4694                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4695                                       DRV_STATE_UNLOAD);
4696                         break;
4697
4698                 case RESET_KIND_SUSPEND:
4699                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4700                                       DRV_STATE_SUSPEND);
4701                         break;
4702
4703                 default:
4704                         break;
4705                 };
4706         }
4707 }
4708
4709 /* tp->lock is held. */
4710 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4711 {
4712         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4713                 switch (kind) {
4714                 case RESET_KIND_INIT:
4715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4716                                       DRV_STATE_START_DONE);
4717                         break;
4718
4719                 case RESET_KIND_SHUTDOWN:
4720                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4721                                       DRV_STATE_UNLOAD_DONE);
4722                         break;
4723
4724                 default:
4725                         break;
4726                 };
4727         }
4728 }
4729
4730 /* tp->lock is held. */
4731 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4732 {
4733         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4734                 switch (kind) {
4735                 case RESET_KIND_INIT:
4736                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4737                                       DRV_STATE_START);
4738                         break;
4739
4740                 case RESET_KIND_SHUTDOWN:
4741                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4742                                       DRV_STATE_UNLOAD);
4743                         break;
4744
4745                 case RESET_KIND_SUSPEND:
4746                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4747                                       DRV_STATE_SUSPEND);
4748                         break;
4749
4750                 default:
4751                         break;
4752                 };
4753         }
4754 }
4755
4756 static int tg3_poll_fw(struct tg3 *tp)
4757 {
4758         int i;
4759         u32 val;
4760
4761         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4762                 /* Wait up to 20ms for init done. */
4763                 for (i = 0; i < 200; i++) {
4764                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4765                                 return 0;
4766                         udelay(100);
4767                 }
4768                 return -ENODEV;
4769         }
4770
4771         /* Wait for firmware initialization to complete. */
4772         for (i = 0; i < 100000; i++) {
4773                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4774                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4775                         break;
4776                 udelay(10);
4777         }
4778
4779         /* Chip might not be fitted with firmware.  Some Sun onboard
4780          * parts are configured like that.  So don't signal the timeout
4781          * of the above loop as an error, but do report the lack of
4782          * running firmware once.
4783          */
4784         if (i >= 100000 &&
4785             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4786                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4787
4788                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4789                        tp->dev->name);
4790         }
4791
4792         return 0;
4793 }
4794
4795 static void tg3_stop_fw(struct tg3 *);
4796
4797 /* tp->lock is held. */
4798 static int tg3_chip_reset(struct tg3 *tp)
4799 {
4800         u32 val;
4801         void (*write_op)(struct tg3 *, u32, u32);
4802         int err;
4803
4804         tg3_nvram_lock(tp);
4805
4806         /* No matching tg3_nvram_unlock() after this because
4807          * chip reset below will undo the nvram lock.
4808          */
4809         tp->nvram_lock_cnt = 0;
4810
4811         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4812             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4814                 tw32(GRC_FASTBOOT_PC, 0);
4815
4816         /*
4817          * We must avoid the readl() that normally takes place.
4818          * It locks machines, causes machine checks, and other
4819          * fun things.  So, temporarily disable the 5701
4820          * hardware workaround, while we do the reset.
4821          */
4822         write_op = tp->write32;
4823         if (write_op == tg3_write_flush_reg32)
4824                 tp->write32 = tg3_write32;
4825
4826         /* Prevent the irq handler from reading or writing PCI registers
4827          * during chip reset when the memory enable bit in the PCI command
4828          * register may be cleared.  The chip does not generate interrupt
4829          * at this time, but the irq handler may still be called due to irq
4830          * sharing or irqpoll.
4831          */
4832         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4833         if (tp->hw_status) {
4834                 tp->hw_status->status = 0;
4835                 tp->hw_status->status_tag = 0;
4836         }
4837         tp->last_tag = 0;
4838         smp_mb();
4839         synchronize_irq(tp->pdev->irq);
4840
4841         /* do the reset */
4842         val = GRC_MISC_CFG_CORECLK_RESET;
4843
4844         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4845                 if (tr32(0x7e2c) == 0x60) {
4846                         tw32(0x7e2c, 0x20);
4847                 }
4848                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4849                         tw32(GRC_MISC_CFG, (1 << 29));
4850                         val |= (1 << 29);
4851                 }
4852         }
4853
4854         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4855                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4856                 tw32(GRC_VCPU_EXT_CTRL,
4857                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4858         }
4859
4860         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4861                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4862         tw32(GRC_MISC_CFG, val);
4863
4864         /* restore 5701 hardware bug workaround write method */
4865         tp->write32 = write_op;
4866
4867         /* Unfortunately, we have to delay before the PCI read back.
4868          * Some 575X chips even will not respond to a PCI cfg access
4869          * when the reset command is given to the chip.
4870          *
4871          * How do these hardware designers expect things to work
4872          * properly if the PCI write is posted for a long period
4873          * of time?  It is always necessary to have some method by
4874          * which a register read back can occur to push the write
4875          * out which does the reset.
4876          *
4877          * For most tg3 variants the trick below was working.
4878          * Ho hum...
4879          */
4880         udelay(120);
4881
4882         /* Flush PCI posted writes.  The normal MMIO registers
4883          * are inaccessible at this time so this is the only
4884          * way to make this reliably (actually, this is no longer
4885          * the case, see above).  I tried to use indirect
4886          * register read/write but this upset some 5701 variants.
4887          */
4888         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4889
4890         udelay(120);
4891
4892         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4893                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4894                         int i;
4895                         u32 cfg_val;
4896
4897                         /* Wait for link training to complete.  */
4898                         for (i = 0; i < 5000; i++)
4899                                 udelay(100);
4900
4901                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4902                         pci_write_config_dword(tp->pdev, 0xc4,
4903                                                cfg_val | (1 << 15));
4904                 }
4905                 /* Set PCIE max payload size and clear error status.  */
4906                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4907         }
4908
4909         /* Re-enable indirect register accesses. */
4910         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4911                                tp->misc_host_ctrl);
4912
4913         /* Set MAX PCI retry to zero. */
4914         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4915         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4916             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4917                 val |= PCISTATE_RETRY_SAME_DMA;
4918         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4919
4920         pci_restore_state(tp->pdev);
4921
4922         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4923
4924         /* Make sure PCI-X relaxed ordering bit is clear. */
4925         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4926         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4927         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4928
4929         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4930                 u32 val;
4931
4932                 /* Chip reset on 5780 will reset MSI enable bit,
4933                  * so need to restore it.
4934                  */
4935                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4936                         u16 ctrl;
4937
4938                         pci_read_config_word(tp->pdev,
4939                                              tp->msi_cap + PCI_MSI_FLAGS,
4940                                              &ctrl);
4941                         pci_write_config_word(tp->pdev,
4942                                               tp->msi_cap + PCI_MSI_FLAGS,
4943                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4944                         val = tr32(MSGINT_MODE);
4945                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4946                 }
4947
4948                 val = tr32(MEMARB_MODE);
4949                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4950
4951         } else
4952                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4953
4954         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4955                 tg3_stop_fw(tp);
4956                 tw32(0x5000, 0x400);
4957         }
4958
4959         tw32(GRC_MODE, tp->grc_mode);
4960
4961         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4962                 u32 val = tr32(0xc4);
4963
4964                 tw32(0xc4, val | (1 << 15));
4965         }
4966
4967         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4968             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4969                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4970                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4971                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4972                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4973         }
4974
4975         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4976                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4977                 tw32_f(MAC_MODE, tp->mac_mode);
4978         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4979                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4980                 tw32_f(MAC_MODE, tp->mac_mode);
4981         } else
4982                 tw32_f(MAC_MODE, 0);
4983         udelay(40);
4984
4985         err = tg3_poll_fw(tp);
4986         if (err)
4987                 return err;
4988
4989         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4990             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4991                 u32 val = tr32(0x7c00);
4992
4993                 tw32(0x7c00, val | (1 << 25));
4994         }
4995
4996         /* Reprobe ASF enable state.  */
4997         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4998         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4999         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5000         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5001                 u32 nic_cfg;
5002
5003                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5004                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5005                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5006                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5007                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5008                 }
5009         }
5010
5011         return 0;
5012 }
5013
5014 /* tp->lock is held. */
5015 static void tg3_stop_fw(struct tg3 *tp)
5016 {
5017         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5018                 u32 val;
5019                 int i;
5020
5021                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5022                 val = tr32(GRC_RX_CPU_EVENT);
5023                 val |= (1 << 14);
5024                 tw32(GRC_RX_CPU_EVENT, val);
5025
5026                 /* Wait for RX cpu to ACK the event.  */
5027                 for (i = 0; i < 100; i++) {
5028                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5029                                 break;
5030                         udelay(1);
5031                 }
5032         }
5033 }
5034
5035 /* tp->lock is held. */
5036 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5037 {
5038         int err;
5039
5040         tg3_stop_fw(tp);
5041
5042         tg3_write_sig_pre_reset(tp, kind);
5043
5044         tg3_abort_hw(tp, silent);
5045         err = tg3_chip_reset(tp);
5046
5047         tg3_write_sig_legacy(tp, kind);
5048         tg3_write_sig_post_reset(tp, kind);
5049
5050         if (err)
5051                 return err;
5052
5053         return 0;
5054 }
5055
5056 #define TG3_FW_RELEASE_MAJOR    0x0
5057 #define TG3_FW_RELASE_MINOR     0x0
5058 #define TG3_FW_RELEASE_FIX      0x0
5059 #define TG3_FW_START_ADDR       0x08000000
5060 #define TG3_FW_TEXT_ADDR        0x08000000
5061 #define TG3_FW_TEXT_LEN         0x9c0
5062 #define TG3_FW_RODATA_ADDR      0x080009c0
5063 #define TG3_FW_RODATA_LEN       0x60
5064 #define TG3_FW_DATA_ADDR        0x08000a40
5065 #define TG3_FW_DATA_LEN         0x20
5066 #define TG3_FW_SBSS_ADDR        0x08000a60
5067 #define TG3_FW_SBSS_LEN         0xc
5068 #define TG3_FW_BSS_ADDR         0x08000a70
5069 #define TG3_FW_BSS_LEN          0x10
5070
5071 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5072         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5073         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5074         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5075         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5076         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5077         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5078         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5079         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5080         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5081         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5082         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5083         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5084         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5085         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5086         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5087         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5088         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5089         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5090         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5091         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5092         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5093         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5094         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5095         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5096         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5097         0, 0, 0, 0, 0, 0,
5098         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5099         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5100         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5101         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5102         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5103         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5104         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5105         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5106         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5107         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5108         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5109         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5110         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5111         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5112         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5113         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5114         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5115         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5116         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5117         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5118         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5119         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5120         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5121         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5122         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5123         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5124         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5125         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5126         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5127         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5128         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5129         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5130         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5131         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5132         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5133         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5134         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5135         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5136         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5137         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5138         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5139         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5140         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5141         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5142         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5143         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5144         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5145         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5146         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5147         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5148         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5149         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5150         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5151         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5152         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5153         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5154         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5155         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5156         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5157         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5158         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5159         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5160         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5161         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5162         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5163 };
5164
5165 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5166         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5167         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5168         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5169         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5170         0x00000000
5171 };
5172
5173 #if 0 /* All zeros, don't eat up space with it. */
5174 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5175         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5176         0x00000000, 0x00000000, 0x00000000, 0x00000000
5177 };
5178 #endif
5179
5180 #define RX_CPU_SCRATCH_BASE     0x30000
5181 #define RX_CPU_SCRATCH_SIZE     0x04000
5182 #define TX_CPU_SCRATCH_BASE     0x34000
5183 #define TX_CPU_SCRATCH_SIZE     0x04000
5184
5185 /* tp->lock is held. */
5186 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5187 {
5188         int i;
5189
5190         BUG_ON(offset == TX_CPU_BASE &&
5191             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5192
5193         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5194                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5195
5196                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5197                 return 0;
5198         }
5199         if (offset == RX_CPU_BASE) {
5200                 for (i = 0; i < 10000; i++) {
5201                         tw32(offset + CPU_STATE, 0xffffffff);
5202                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5203                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5204                                 break;
5205                 }
5206
5207                 tw32(offset + CPU_STATE, 0xffffffff);
5208                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5209                 udelay(10);
5210         } else {
5211                 for (i = 0; i < 10000; i++) {
5212                         tw32(offset + CPU_STATE, 0xffffffff);
5213                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5214                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5215                                 break;
5216                 }
5217         }
5218
5219         if (i >= 10000) {
5220                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5221                        "and %s CPU\n",
5222                        tp->dev->name,
5223                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5224                 return -ENODEV;
5225         }
5226
5227         /* Clear firmware's nvram arbitration. */
5228         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5229                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5230         return 0;
5231 }
5232
5233 struct fw_info {
5234         unsigned int text_base;
5235         unsigned int text_len;
5236         const u32 *text_data;
5237         unsigned int rodata_base;
5238         unsigned int rodata_len;
5239         const u32 *rodata_data;
5240         unsigned int data_base;
5241         unsigned int data_len;
5242         const u32 *data_data;
5243 };
5244
5245 /* tp->lock is held. */
5246 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5247                                  int cpu_scratch_size, struct fw_info *info)
5248 {
5249         int err, lock_err, i;
5250         void (*write_op)(struct tg3 *, u32, u32);
5251
5252         if (cpu_base == TX_CPU_BASE &&
5253             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5254                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5255                        "TX cpu firmware on %s which is 5705.\n",
5256                        tp->dev->name);
5257                 return -EINVAL;
5258         }
5259
5260         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5261                 write_op = tg3_write_mem;
5262         else
5263                 write_op = tg3_write_indirect_reg32;
5264
5265         /* It is possible that bootcode is still loading at this point.
5266          * Get the nvram lock first before halting the cpu.
5267          */
5268         lock_err = tg3_nvram_lock(tp);
5269         err = tg3_halt_cpu(tp, cpu_base);
5270         if (!lock_err)
5271                 tg3_nvram_unlock(tp);
5272         if (err)
5273                 goto out;
5274
5275         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5276                 write_op(tp, cpu_scratch_base + i, 0);
5277         tw32(cpu_base + CPU_STATE, 0xffffffff);
5278         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5279         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5280                 write_op(tp, (cpu_scratch_base +
5281                               (info->text_base & 0xffff) +
5282                               (i * sizeof(u32))),
5283                          (info->text_data ?
5284                           info->text_data[i] : 0));
5285         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5286                 write_op(tp, (cpu_scratch_base +
5287                               (info->rodata_base & 0xffff) +
5288                               (i * sizeof(u32))),
5289                          (info->rodata_data ?
5290                           info->rodata_data[i] : 0));
5291         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5292                 write_op(tp, (cpu_scratch_base +
5293                               (info->data_base & 0xffff) +
5294                               (i * sizeof(u32))),
5295                          (info->data_data ?
5296                           info->data_data[i] : 0));
5297
5298         err = 0;
5299
5300 out:
5301         return err;
5302 }
5303
5304 /* tp->lock is held. */
5305 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5306 {
5307         struct fw_info info;
5308         int err, i;
5309
5310         info.text_base = TG3_FW_TEXT_ADDR;
5311         info.text_len = TG3_FW_TEXT_LEN;
5312         info.text_data = &tg3FwText[0];
5313         info.rodata_base = TG3_FW_RODATA_ADDR;
5314         info.rodata_len = TG3_FW_RODATA_LEN;
5315         info.rodata_data = &tg3FwRodata[0];
5316         info.data_base = TG3_FW_DATA_ADDR;
5317         info.data_len = TG3_FW_DATA_LEN;
5318         info.data_data = NULL;
5319
5320         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5321                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5322                                     &info);
5323         if (err)
5324                 return err;
5325
5326         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5327                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5328                                     &info);
5329         if (err)
5330                 return err;
5331
5332         /* Now startup only the RX cpu. */
5333         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5334         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5335
5336         for (i = 0; i < 5; i++) {
5337                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5338                         break;
5339                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5340                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5341                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5342                 udelay(1000);
5343         }
5344         if (i >= 5) {
5345                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5346                        "to set RX CPU PC, is %08x should be %08x\n",
5347                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5348                        TG3_FW_TEXT_ADDR);
5349                 return -ENODEV;
5350         }
5351         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5352         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5353
5354         return 0;
5355 }
5356
5357
5358 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5359 #define TG3_TSO_FW_RELASE_MINOR         0x6
5360 #define TG3_TSO_FW_RELEASE_FIX          0x0
5361 #define TG3_TSO_FW_START_ADDR           0x08000000
5362 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5363 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5364 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5365 #define TG3_TSO_FW_RODATA_LEN           0x60
5366 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5367 #define TG3_TSO_FW_DATA_LEN             0x30
5368 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5369 #define TG3_TSO_FW_SBSS_LEN             0x2c
5370 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5371 #define TG3_TSO_FW_BSS_LEN              0x894
5372
5373 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5374         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5375         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5376         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5377         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5378         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5379         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5380         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5381         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5382         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5383         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5384         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5385         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5386         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5387         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5388         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5389         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5390         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5391         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5392         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5393         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5394         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5395         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5396         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5397         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5398         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5399         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5400         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5401         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5402         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5403         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5404         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5405         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5406         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5407         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5408         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5409         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5410         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5411         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5412         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5413         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5414         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5415         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5416         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5417         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5418         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5419         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5420         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5421         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5422         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5423         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5424         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5425         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5426         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5427         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5428         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5429         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5430         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5431         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5432         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5433         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5434         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5435         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5436         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5437         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5438         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5439         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5440         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5441         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5442         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5443         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5444         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5445         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5446         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5447         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5448         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5449         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5450         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5451         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5452         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5453         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5454         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5455         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5456         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5457         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5458         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5459         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5460         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5461         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5462         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5463         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5464         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5465         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5466         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5467         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5468         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5469         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5470         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5471         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5472         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5473         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5474         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5475         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5476         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5477         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5478         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5479         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5480         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5481         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5482         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5483         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5484         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5485         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5486         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5487         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5488         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5489         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5490         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5491         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5492         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5493         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5494         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5495         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5496         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5497         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5498         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5499         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5500         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5501         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5502         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5503         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5504         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5505         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5506         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5507         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5508         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5509         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5510         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5511         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5512         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5513         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5514         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5515         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5516         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5517         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5518         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5519         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5520         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5521         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5522         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5523         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5524         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5525         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5526         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5527         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5528         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5529         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5530         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5531         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5532         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5533         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5534         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5535         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5536         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5537         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5538         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5539         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5540         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5541         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5542         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5543         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5544         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5545         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5546         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5547         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5548         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5549         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5550         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5551         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5552         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5553         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5554         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5555         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5556         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5557         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5558         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5559         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5560         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5561         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5562         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5563         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5564         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5565         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5566         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5567         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5568         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5569         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5570         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5571         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5572         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5573         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5574         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5575         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5576         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5577         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5578         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5579         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5580         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5581         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5582         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5583         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5584         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5585         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5586         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5587         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5588         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5589         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5590         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5591         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5592         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5593         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5594         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5595         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5596         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5597         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5598         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5599         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5600         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5601         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5602         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5603         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5604         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5605         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5606         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5607         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5608         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5609         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5610         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5611         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5612         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5613         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5614         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5615         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5616         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5617         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5618         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5619         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5620         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5621         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5622         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5623         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5624         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5625         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5626         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5627         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5628         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5629         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5630         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5631         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5632         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5633         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5634         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5635         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5636         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5637         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5638         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5639         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5640         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5641         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5642         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5643         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5644         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5645         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5646         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5647         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5648         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5649         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5650         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5651         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5652         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5653         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5654         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5655         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5656         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5657         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5658 };
5659
5660 static const u32 tg3TsoFwRodata[] = {
5661         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5662         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5663         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5664         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5665         0x00000000,
5666 };
5667
5668 static const u32 tg3TsoFwData[] = {
5669         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5670         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5671         0x00000000,
5672 };
5673
5674 /* 5705 needs a special version of the TSO firmware.  */
5675 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5676 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5677 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5678 #define TG3_TSO5_FW_START_ADDR          0x00010000
5679 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5680 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5681 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5682 #define TG3_TSO5_FW_RODATA_LEN          0x50
5683 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5684 #define TG3_TSO5_FW_DATA_LEN            0x20
5685 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5686 #define TG3_TSO5_FW_SBSS_LEN            0x28
5687 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5688 #define TG3_TSO5_FW_BSS_LEN             0x88
5689
5690 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5691         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5692         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5693         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5694         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5695         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5696         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5697         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5698         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5699         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5700         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5701         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5702         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5703         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5704         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5705         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5706         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5707         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5708         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5709         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5710         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5711         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5712         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5713         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5714         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5715         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5716         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5717         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5718         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5719         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5720         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5721         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5722         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5723         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5724         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5725         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5726         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5727         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5728         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5729         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5730         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5731         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5732         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5733         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5734         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5735         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5736         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5737         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5738         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5739         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5740         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5741         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5742         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5743         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5744         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5745         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5746         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5747         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5748         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5749         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5750         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5751         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5752         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5753         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5754         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5755         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5756         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5757         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5758         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5759         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5760         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5761         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5762         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5763         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5764         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5765         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5766         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5767         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5768         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5769         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5770         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5771         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5772         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5773         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5774         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5775         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5776         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5777         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5778         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5779         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5780         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5781         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5782         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5783         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5784         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5785         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5786         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5787         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5788         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5789         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5790         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5791         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5792         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5793         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5794         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5795         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5796         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5797         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5798         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5799         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5800         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5801         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5802         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5803         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5804         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5805         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5806         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5807         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5808         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5809         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5810         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5811         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5812         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5813         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5814         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5815         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5816         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5817         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5818         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5819         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5820         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5821         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5822         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5823         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5824         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5825         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5826         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5827         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5828         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5829         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5830         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5831         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5832         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5833         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5834         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5835         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5836         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5837         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5838         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5839         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5840         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5841         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5842         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5843         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5844         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5845         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5846         0x00000000, 0x00000000, 0x00000000,
5847 };
5848
5849 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5850         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5851         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5852         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5853         0x00000000, 0x00000000, 0x00000000,
5854 };
5855
5856 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5857         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5858         0x00000000, 0x00000000, 0x00000000,
5859 };
5860
5861 /* tp->lock is held. */
5862 static int tg3_load_tso_firmware(struct tg3 *tp)
5863 {
5864         struct fw_info info;
5865         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5866         int err, i;
5867
5868         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5869                 return 0;
5870
5871         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5872                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5873                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5874                 info.text_data = &tg3Tso5FwText[0];
5875                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5876                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5877                 info.rodata_data = &tg3Tso5FwRodata[0];
5878                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5879                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5880                 info.data_data = &tg3Tso5FwData[0];
5881                 cpu_base = RX_CPU_BASE;
5882                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5883                 cpu_scratch_size = (info.text_len +
5884                                     info.rodata_len +
5885                                     info.data_len +
5886                                     TG3_TSO5_FW_SBSS_LEN +
5887                                     TG3_TSO5_FW_BSS_LEN);
5888         } else {
5889                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5890                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5891                 info.text_data = &tg3TsoFwText[0];
5892                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5893                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5894                 info.rodata_data = &tg3TsoFwRodata[0];
5895                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5896                 info.data_len = TG3_TSO_FW_DATA_LEN;
5897                 info.data_data = &tg3TsoFwData[0];
5898                 cpu_base = TX_CPU_BASE;
5899                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5900                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5901         }
5902
5903         err = tg3_load_firmware_cpu(tp, cpu_base,
5904                                     cpu_scratch_base, cpu_scratch_size,
5905                                     &info);
5906         if (err)
5907                 return err;
5908
5909         /* Now startup the cpu. */
5910         tw32(cpu_base + CPU_STATE, 0xffffffff);
5911         tw32_f(cpu_base + CPU_PC,    info.text_base);
5912
5913         for (i = 0; i < 5; i++) {
5914                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5915                         break;
5916                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5917                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5918                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5919                 udelay(1000);
5920         }
5921         if (i >= 5) {
5922                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5923                        "to set CPU PC, is %08x should be %08x\n",
5924                        tp->dev->name, tr32(cpu_base + CPU_PC),
5925                        info.text_base);
5926                 return -ENODEV;
5927         }
5928         tw32(cpu_base + CPU_STATE, 0xffffffff);
5929         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5930         return 0;
5931 }
5932
5933
5934 /* tp->lock is held. */
5935 static void __tg3_set_mac_addr(struct tg3 *tp)
5936 {
5937         u32 addr_high, addr_low;
5938         int i;
5939
5940         addr_high = ((tp->dev->dev_addr[0] << 8) |
5941                      tp->dev->dev_addr[1]);
5942         addr_low = ((tp->dev->dev_addr[2] << 24) |
5943                     (tp->dev->dev_addr[3] << 16) |
5944                     (tp->dev->dev_addr[4] <<  8) |
5945                     (tp->dev->dev_addr[5] <<  0));
5946         for (i = 0; i < 4; i++) {
5947                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5948                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5949         }
5950
5951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5952             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5953                 for (i = 0; i < 12; i++) {
5954                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5955                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5956                 }
5957         }
5958
5959         addr_high = (tp->dev->dev_addr[0] +
5960                      tp->dev->dev_addr[1] +
5961                      tp->dev->dev_addr[2] +
5962                      tp->dev->dev_addr[3] +
5963                      tp->dev->dev_addr[4] +
5964                      tp->dev->dev_addr[5]) &
5965                 TX_BACKOFF_SEED_MASK;
5966         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5967 }
5968
5969 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5970 {
5971         struct tg3 *tp = netdev_priv(dev);
5972         struct sockaddr *addr = p;
5973         int err = 0;
5974
5975         if (!is_valid_ether_addr(addr->sa_data))
5976                 return -EINVAL;
5977
5978         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5979
5980         if (!netif_running(dev))
5981                 return 0;
5982
5983         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5984                 /* Reset chip so that ASF can re-init any MAC addresses it
5985                  * needs.
5986                  */
5987                 tg3_netif_stop(tp);
5988                 tg3_full_lock(tp, 1);
5989
5990                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5991                 err = tg3_restart_hw(tp, 0);
5992                 if (!err)
5993                         tg3_netif_start(tp);
5994                 tg3_full_unlock(tp);
5995         } else {
5996                 spin_lock_bh(&tp->lock);
5997                 __tg3_set_mac_addr(tp);
5998                 spin_unlock_bh(&tp->lock);
5999         }
6000
6001         return err;
6002 }
6003
6004 /* tp->lock is held. */
6005 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6006                            dma_addr_t mapping, u32 maxlen_flags,
6007                            u32 nic_addr)
6008 {
6009         tg3_write_mem(tp,
6010                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6011                       ((u64) mapping >> 32));
6012         tg3_write_mem(tp,
6013                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6014                       ((u64) mapping & 0xffffffff));
6015         tg3_write_mem(tp,
6016                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6017                        maxlen_flags);
6018
6019         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6020                 tg3_write_mem(tp,
6021                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6022                               nic_addr);
6023 }
6024
6025 static void __tg3_set_rx_mode(struct net_device *);
6026 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6027 {
6028         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6029         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6030         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6031         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6032         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6033                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6034                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6035         }
6036         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6037         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6038         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6039                 u32 val = ec->stats_block_coalesce_usecs;
6040
6041                 if (!netif_carrier_ok(tp->dev))
6042                         val = 0;
6043
6044                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6045         }
6046 }
6047
6048 /* tp->lock is held. */
6049 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6050 {
6051         u32 val, rdmac_mode;
6052         int i, err, limit;
6053
6054         tg3_disable_ints(tp);
6055
6056         tg3_stop_fw(tp);
6057
6058         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6059
6060         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6061                 tg3_abort_hw(tp, 1);
6062         }
6063
6064         if (reset_phy)
6065                 tg3_phy_reset(tp);
6066
6067         err = tg3_chip_reset(tp);
6068         if (err)
6069                 return err;
6070
6071         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6072
6073         /* This works around an issue with Athlon chipsets on
6074          * B3 tigon3 silicon.  This bit has no effect on any
6075          * other revision.  But do not set this on PCI Express
6076          * chips.
6077          */
6078         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6079                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6080         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6081
6082         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6083             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6084                 val = tr32(TG3PCI_PCISTATE);
6085                 val |= PCISTATE_RETRY_SAME_DMA;
6086                 tw32(TG3PCI_PCISTATE, val);
6087         }
6088
6089         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6090                 /* Enable some hw fixes.  */
6091                 val = tr32(TG3PCI_MSI_DATA);
6092                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6093                 tw32(TG3PCI_MSI_DATA, val);
6094         }
6095
6096         /* Descriptor ring init may make accesses to the
6097          * NIC SRAM area to setup the TX descriptors, so we
6098          * can only do this after the hardware has been
6099          * successfully reset.
6100          */
6101         err = tg3_init_rings(tp);
6102         if (err)
6103                 return err;
6104
6105         /* This value is determined during the probe time DMA
6106          * engine test, tg3_test_dma.
6107          */
6108         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6109
6110         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6111                           GRC_MODE_4X_NIC_SEND_RINGS |
6112                           GRC_MODE_NO_TX_PHDR_CSUM |
6113                           GRC_MODE_NO_RX_PHDR_CSUM);
6114         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6115
6116         /* Pseudo-header checksum is done by hardware logic and not
6117          * the offload processers, so make the chip do the pseudo-
6118          * header checksums on receive.  For transmit it is more
6119          * convenient to do the pseudo-header checksum in software
6120          * as Linux does that on transmit for us in all cases.
6121          */
6122         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6123
6124         tw32(GRC_MODE,
6125              tp->grc_mode |
6126              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6127
6128         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6129         val = tr32(GRC_MISC_CFG);
6130         val &= ~0xff;
6131         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6132         tw32(GRC_MISC_CFG, val);
6133
6134         /* Initialize MBUF/DESC pool. */
6135         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6136                 /* Do nothing.  */
6137         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6138                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6139                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6140                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6141                 else
6142                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6143                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6144                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6145         }
6146         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6147                 int fw_len;
6148
6149                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6150                           TG3_TSO5_FW_RODATA_LEN +
6151                           TG3_TSO5_FW_DATA_LEN +
6152                           TG3_TSO5_FW_SBSS_LEN +
6153                           TG3_TSO5_FW_BSS_LEN);
6154                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6155                 tw32(BUFMGR_MB_POOL_ADDR,
6156                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6157                 tw32(BUFMGR_MB_POOL_SIZE,
6158                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6159         }
6160
6161         if (tp->dev->mtu <= ETH_DATA_LEN) {
6162                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6163                      tp->bufmgr_config.mbuf_read_dma_low_water);
6164                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6165                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6166                 tw32(BUFMGR_MB_HIGH_WATER,
6167                      tp->bufmgr_config.mbuf_high_water);
6168         } else {
6169                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6170                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6171                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6172                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6173                 tw32(BUFMGR_MB_HIGH_WATER,
6174                      tp->bufmgr_config.mbuf_high_water_jumbo);
6175         }
6176         tw32(BUFMGR_DMA_LOW_WATER,
6177              tp->bufmgr_config.dma_low_water);
6178         tw32(BUFMGR_DMA_HIGH_WATER,
6179              tp->bufmgr_config.dma_high_water);
6180
6181         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6182         for (i = 0; i < 2000; i++) {
6183                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6184                         break;
6185                 udelay(10);
6186         }
6187         if (i >= 2000) {
6188                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6189                        tp->dev->name);
6190                 return -ENODEV;
6191         }
6192
6193         /* Setup replenish threshold. */
6194         val = tp->rx_pending / 8;
6195         if (val == 0)
6196                 val = 1;
6197         else if (val > tp->rx_std_max_post)
6198                 val = tp->rx_std_max_post;
6199         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6200                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6201                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6202
6203                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6204                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6205         }
6206
6207         tw32(RCVBDI_STD_THRESH, val);
6208
6209         /* Initialize TG3_BDINFO's at:
6210          *  RCVDBDI_STD_BD:     standard eth size rx ring
6211          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6212          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6213          *
6214          * like so:
6215          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6216          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6217          *                              ring attribute flags
6218          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6219          *
6220          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6221          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6222          *
6223          * The size of each ring is fixed in the firmware, but the location is
6224          * configurable.
6225          */
6226         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6227              ((u64) tp->rx_std_mapping >> 32));
6228         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6229              ((u64) tp->rx_std_mapping & 0xffffffff));
6230         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6231              NIC_SRAM_RX_BUFFER_DESC);
6232
6233         /* Don't even try to program the JUMBO/MINI buffer descriptor
6234          * configs on 5705.
6235          */
6236         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6237                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6238                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6239         } else {
6240                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6241                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6242
6243                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6244                      BDINFO_FLAGS_DISABLED);
6245
6246                 /* Setup replenish threshold. */
6247                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6248
6249                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6250                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6251                              ((u64) tp->rx_jumbo_mapping >> 32));
6252                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6253                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6254                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6255                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6256                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6257                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6258                 } else {
6259                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6260                              BDINFO_FLAGS_DISABLED);
6261                 }
6262
6263         }
6264
6265         /* There is only one send ring on 5705/5750, no need to explicitly
6266          * disable the others.
6267          */
6268         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6269                 /* Clear out send RCB ring in SRAM. */
6270                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6271                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6272                                       BDINFO_FLAGS_DISABLED);
6273         }
6274
6275         tp->tx_prod = 0;
6276         tp->tx_cons = 0;
6277         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6278         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6279
6280         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6281                        tp->tx_desc_mapping,
6282                        (TG3_TX_RING_SIZE <<
6283                         BDINFO_FLAGS_MAXLEN_SHIFT),
6284                        NIC_SRAM_TX_BUFFER_DESC);
6285
6286         /* There is only one receive return ring on 5705/5750, no need
6287          * to explicitly disable the others.
6288          */
6289         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6290                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6291                      i += TG3_BDINFO_SIZE) {
6292                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6293                                       BDINFO_FLAGS_DISABLED);
6294                 }
6295         }
6296
6297         tp->rx_rcb_ptr = 0;
6298         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6299
6300         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6301                        tp->rx_rcb_mapping,
6302                        (TG3_RX_RCB_RING_SIZE(tp) <<
6303                         BDINFO_FLAGS_MAXLEN_SHIFT),
6304                        0);
6305
6306         tp->rx_std_ptr = tp->rx_pending;
6307         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6308                      tp->rx_std_ptr);
6309
6310         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6311                                                 tp->rx_jumbo_pending : 0;
6312         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6313                      tp->rx_jumbo_ptr);
6314
6315         /* Initialize MAC address and backoff seed. */
6316         __tg3_set_mac_addr(tp);
6317
6318         /* MTU + ethernet header + FCS + optional VLAN tag */
6319         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6320
6321         /* The slot time is changed by tg3_setup_phy if we
6322          * run at gigabit with half duplex.
6323          */
6324         tw32(MAC_TX_LENGTHS,
6325              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6326              (6 << TX_LENGTHS_IPG_SHIFT) |
6327              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6328
6329         /* Receive rules. */
6330         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6331         tw32(RCVLPC_CONFIG, 0x0181);
6332
6333         /* Calculate RDMAC_MODE setting early, we need it to determine
6334          * the RCVLPC_STATE_ENABLE mask.
6335          */
6336         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6337                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6338                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6339                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6340                       RDMAC_MODE_LNGREAD_ENAB);
6341
6342         /* If statement applies to 5705 and 5750 PCI devices only */
6343         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6344              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6345             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6346                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6347                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6348                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6349                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6350                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6351                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6352                 }
6353         }
6354
6355         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6356                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6357
6358         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6359                 rdmac_mode |= (1 << 27);
6360
6361         /* Receive/send statistics. */
6362         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6363                 val = tr32(RCVLPC_STATS_ENABLE);
6364                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6365                 tw32(RCVLPC_STATS_ENABLE, val);
6366         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6367                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6368                 val = tr32(RCVLPC_STATS_ENABLE);
6369                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6370                 tw32(RCVLPC_STATS_ENABLE, val);
6371         } else {
6372                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6373         }
6374         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6375         tw32(SNDDATAI_STATSENAB, 0xffffff);
6376         tw32(SNDDATAI_STATSCTRL,
6377              (SNDDATAI_SCTRL_ENABLE |
6378               SNDDATAI_SCTRL_FASTUPD));
6379
6380         /* Setup host coalescing engine. */
6381         tw32(HOSTCC_MODE, 0);
6382         for (i = 0; i < 2000; i++) {
6383                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6384                         break;
6385                 udelay(10);
6386         }
6387
6388         __tg3_set_coalesce(tp, &tp->coal);
6389
6390         /* set status block DMA address */
6391         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6392              ((u64) tp->status_mapping >> 32));
6393         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6394              ((u64) tp->status_mapping & 0xffffffff));
6395
6396         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6397                 /* Status/statistics block address.  See tg3_timer,
6398                  * the tg3_periodic_fetch_stats call there, and
6399                  * tg3_get_stats to see how this works for 5705/5750 chips.
6400                  */
6401                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6402                      ((u64) tp->stats_mapping >> 32));
6403                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6404                      ((u64) tp->stats_mapping & 0xffffffff));
6405                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6406                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6407         }
6408
6409         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6410
6411         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6412         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6413         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6414                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6415
6416         /* Clear statistics/status block in chip, and status block in ram. */
6417         for (i = NIC_SRAM_STATS_BLK;
6418              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6419              i += sizeof(u32)) {
6420                 tg3_write_mem(tp, i, 0);
6421                 udelay(40);
6422         }
6423         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6424
6425         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6426                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6427                 /* reset to prevent losing 1st rx packet intermittently */
6428                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6429                 udelay(10);
6430         }
6431
6432         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6433                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6434         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6435         udelay(40);
6436
6437         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6438          * If TG3_FLG2_IS_NIC is zero, we should read the
6439          * register to preserve the GPIO settings for LOMs. The GPIOs,
6440          * whether used as inputs or outputs, are set by boot code after
6441          * reset.
6442          */
6443         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6444                 u32 gpio_mask;
6445
6446                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6447                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6448                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6449
6450                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6451                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6452                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6453
6454                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6455                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6456
6457                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6458
6459                 /* GPIO1 must be driven high for eeprom write protect */
6460                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6461                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6462                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6463         }
6464         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6465         udelay(100);
6466
6467         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6468         tp->last_tag = 0;
6469
6470         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6471                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6472                 udelay(40);
6473         }
6474
6475         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6476                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6477                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6478                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6479                WDMAC_MODE_LNGREAD_ENAB);
6480
6481         /* If statement applies to 5705 and 5750 PCI devices only */
6482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6483              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6484             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6485                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6486                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6487                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6488                         /* nothing */
6489                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6490                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6491                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6492                         val |= WDMAC_MODE_RX_ACCEL;
6493                 }
6494         }
6495
6496         /* Enable host coalescing bug fix */
6497         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6498             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6499                 val |= (1 << 29);
6500
6501         tw32_f(WDMAC_MODE, val);
6502         udelay(40);
6503
6504         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6505                 val = tr32(TG3PCI_X_CAPS);
6506                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6507                         val &= ~PCIX_CAPS_BURST_MASK;
6508                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6509                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6510                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6511                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6512                 }
6513                 tw32(TG3PCI_X_CAPS, val);
6514         }
6515
6516         tw32_f(RDMAC_MODE, rdmac_mode);
6517         udelay(40);
6518
6519         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6520         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6521                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6522         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6523         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6524         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6525         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6526         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6527         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6528                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6529         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6530         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6531
6532         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6533                 err = tg3_load_5701_a0_firmware_fix(tp);
6534                 if (err)
6535                         return err;
6536         }
6537
6538         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6539                 err = tg3_load_tso_firmware(tp);
6540                 if (err)
6541                         return err;
6542         }
6543
6544         tp->tx_mode = TX_MODE_ENABLE;
6545         tw32_f(MAC_TX_MODE, tp->tx_mode);
6546         udelay(100);
6547
6548         tp->rx_mode = RX_MODE_ENABLE;
6549         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6550                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6551
6552         tw32_f(MAC_RX_MODE, tp->rx_mode);
6553         udelay(10);
6554
6555         if (tp->link_config.phy_is_low_power) {
6556                 tp->link_config.phy_is_low_power = 0;
6557                 tp->link_config.speed = tp->link_config.orig_speed;
6558                 tp->link_config.duplex = tp->link_config.orig_duplex;
6559                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6560         }
6561
6562         tp->mi_mode = MAC_MI_MODE_BASE;
6563         tw32_f(MAC_MI_MODE, tp->mi_mode);
6564         udelay(80);
6565
6566         tw32(MAC_LED_CTRL, tp->led_ctrl);
6567
6568         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6569         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6570                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6571                 udelay(10);
6572         }
6573         tw32_f(MAC_RX_MODE, tp->rx_mode);
6574         udelay(10);
6575
6576         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6577                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6578                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6579                         /* Set drive transmission level to 1.2V  */
6580                         /* only if the signal pre-emphasis bit is not set  */
6581                         val = tr32(MAC_SERDES_CFG);
6582                         val &= 0xfffff000;
6583                         val |= 0x880;
6584                         tw32(MAC_SERDES_CFG, val);
6585                 }
6586                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6587                         tw32(MAC_SERDES_CFG, 0x616000);
6588         }
6589
6590         /* Prevent chip from dropping frames when flow control
6591          * is enabled.
6592          */
6593         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6594
6595         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6596             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6597                 /* Use hardware link auto-negotiation */
6598                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6599         }
6600
6601         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6602             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6603                 u32 tmp;
6604
6605                 tmp = tr32(SERDES_RX_CTRL);
6606                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6607                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6608                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6609                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6610         }
6611
6612         err = tg3_setup_phy(tp, 0);
6613         if (err)
6614                 return err;
6615
6616         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6617             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6618                 u32 tmp;
6619
6620                 /* Clear CRC stats. */
6621                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6622                         tg3_writephy(tp, MII_TG3_TEST1,
6623                                      tmp | MII_TG3_TEST1_CRC_EN);
6624                         tg3_readphy(tp, 0x14, &tmp);
6625                 }
6626         }
6627
6628         __tg3_set_rx_mode(tp->dev);
6629
6630         /* Initialize receive rules. */
6631         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6632         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6633         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6634         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6635
6636         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6637             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6638                 limit = 8;
6639         else
6640                 limit = 16;
6641         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6642                 limit -= 4;
6643         switch (limit) {
6644         case 16:
6645                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6646         case 15:
6647                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6648         case 14:
6649                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6650         case 13:
6651                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6652         case 12:
6653                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6654         case 11:
6655                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6656         case 10:
6657                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6658         case 9:
6659                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6660         case 8:
6661                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6662         case 7:
6663                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6664         case 6:
6665                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6666         case 5:
6667                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6668         case 4:
6669                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6670         case 3:
6671                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6672         case 2:
6673         case 1:
6674
6675         default:
6676                 break;
6677         };
6678
6679         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6680
6681         return 0;
6682 }
6683
6684 /* Called at device open time to get the chip ready for
6685  * packet processing.  Invoked with tp->lock held.
6686  */
6687 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6688 {
6689         int err;
6690
6691         /* Force the chip into D0. */
6692         err = tg3_set_power_state(tp, PCI_D0);
6693         if (err)
6694                 goto out;
6695
6696         tg3_switch_clocks(tp);
6697
6698         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6699
6700         err = tg3_reset_hw(tp, reset_phy);
6701
6702 out:
6703         return err;
6704 }
6705
6706 #define TG3_STAT_ADD32(PSTAT, REG) \
6707 do {    u32 __val = tr32(REG); \
6708         (PSTAT)->low += __val; \
6709         if ((PSTAT)->low < __val) \
6710                 (PSTAT)->high += 1; \
6711 } while (0)
6712
6713 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6714 {
6715         struct tg3_hw_stats *sp = tp->hw_stats;
6716
6717         if (!netif_carrier_ok(tp->dev))
6718                 return;
6719
6720         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6721         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6722         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6723         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6724         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6725         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6726         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6727         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6728         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6729         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6730         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6731         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6732         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6733
6734         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6735         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6736         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6737         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6738         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6739         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6740         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6741         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6742         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6743         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6744         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6745         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6746         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6747         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6748
6749         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6750         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6751         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6752 }
6753
6754 static void tg3_timer(unsigned long __opaque)
6755 {
6756         struct tg3 *tp = (struct tg3 *) __opaque;
6757
6758         if (tp->irq_sync)
6759                 goto restart_timer;
6760
6761         spin_lock(&tp->lock);
6762
6763         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6764                 /* All of this garbage is because when using non-tagged
6765                  * IRQ status the mailbox/status_block protocol the chip
6766                  * uses with the cpu is race prone.
6767                  */
6768                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6769                         tw32(GRC_LOCAL_CTRL,
6770                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6771                 } else {
6772                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6773                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6774                 }
6775
6776                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6777                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6778                         spin_unlock(&tp->lock);
6779                         schedule_work(&tp->reset_task);
6780                         return;
6781                 }
6782         }
6783
6784         /* This part only runs once per second. */
6785         if (!--tp->timer_counter) {
6786                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6787                         tg3_periodic_fetch_stats(tp);
6788
6789                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6790                         u32 mac_stat;
6791                         int phy_event;
6792
6793                         mac_stat = tr32(MAC_STATUS);
6794
6795                         phy_event = 0;
6796                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6797                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6798                                         phy_event = 1;
6799                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6800                                 phy_event = 1;
6801
6802                         if (phy_event)
6803                                 tg3_setup_phy(tp, 0);
6804                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6805                         u32 mac_stat = tr32(MAC_STATUS);
6806                         int need_setup = 0;
6807
6808                         if (netif_carrier_ok(tp->dev) &&
6809                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6810                                 need_setup = 1;
6811                         }
6812                         if (! netif_carrier_ok(tp->dev) &&
6813                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6814                                          MAC_STATUS_SIGNAL_DET))) {
6815                                 need_setup = 1;
6816                         }
6817                         if (need_setup) {
6818                                 if (!tp->serdes_counter) {
6819                                         tw32_f(MAC_MODE,
6820                                              (tp->mac_mode &
6821                                               ~MAC_MODE_PORT_MODE_MASK));
6822                                         udelay(40);
6823                                         tw32_f(MAC_MODE, tp->mac_mode);
6824                                         udelay(40);
6825                                 }
6826                                 tg3_setup_phy(tp, 0);
6827                         }
6828                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6829                         tg3_serdes_parallel_detect(tp);
6830
6831                 tp->timer_counter = tp->timer_multiplier;
6832         }
6833
6834         /* Heartbeat is only sent once every 2 seconds.
6835          *
6836          * The heartbeat is to tell the ASF firmware that the host
6837          * driver is still alive.  In the event that the OS crashes,
6838          * ASF needs to reset the hardware to free up the FIFO space
6839          * that may be filled with rx packets destined for the host.
6840          * If the FIFO is full, ASF will no longer function properly.
6841          *
6842          * Unintended resets have been reported on real time kernels
6843          * where the timer doesn't run on time.  Netpoll will also have
6844          * same problem.
6845          *
6846          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6847          * to check the ring condition when the heartbeat is expiring
6848          * before doing the reset.  This will prevent most unintended
6849          * resets.
6850          */
6851         if (!--tp->asf_counter) {
6852                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6853                         u32 val;
6854
6855                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6856                                       FWCMD_NICDRV_ALIVE3);
6857                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6858                         /* 5 seconds timeout */
6859                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6860                         val = tr32(GRC_RX_CPU_EVENT);
6861                         val |= (1 << 14);
6862                         tw32(GRC_RX_CPU_EVENT, val);
6863                 }
6864                 tp->asf_counter = tp->asf_multiplier;
6865         }
6866
6867         spin_unlock(&tp->lock);
6868
6869 restart_timer:
6870         tp->timer.expires = jiffies + tp->timer_offset;
6871         add_timer(&tp->timer);
6872 }
6873
6874 static int tg3_request_irq(struct tg3 *tp)
6875 {
6876         irq_handler_t fn;
6877         unsigned long flags;
6878         struct net_device *dev = tp->dev;
6879
6880         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6881                 fn = tg3_msi;
6882                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6883                         fn = tg3_msi_1shot;
6884                 flags = IRQF_SAMPLE_RANDOM;
6885         } else {
6886                 fn = tg3_interrupt;
6887                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6888                         fn = tg3_interrupt_tagged;
6889                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6890         }
6891         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6892 }
6893
6894 static int tg3_test_interrupt(struct tg3 *tp)
6895 {
6896         struct net_device *dev = tp->dev;
6897         int err, i, intr_ok = 0;
6898
6899         if (!netif_running(dev))
6900                 return -ENODEV;
6901
6902         tg3_disable_ints(tp);
6903
6904         free_irq(tp->pdev->irq, dev);
6905
6906         err = request_irq(tp->pdev->irq, tg3_test_isr,
6907                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6908         if (err)
6909                 return err;
6910
6911         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6912         tg3_enable_ints(tp);
6913
6914         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6915                HOSTCC_MODE_NOW);
6916
6917         for (i = 0; i < 5; i++) {
6918                 u32 int_mbox, misc_host_ctrl;
6919
6920                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6921                                         TG3_64BIT_REG_LOW);
6922                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6923
6924                 if ((int_mbox != 0) ||
6925                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6926                         intr_ok = 1;
6927                         break;
6928                 }
6929
6930                 msleep(10);
6931         }
6932
6933         tg3_disable_ints(tp);
6934
6935         free_irq(tp->pdev->irq, dev);
6936
6937         err = tg3_request_irq(tp);
6938
6939         if (err)
6940                 return err;
6941
6942         if (intr_ok)
6943                 return 0;
6944
6945         return -EIO;
6946 }
6947
6948 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6949  * successfully restored
6950  */
6951 static int tg3_test_msi(struct tg3 *tp)
6952 {
6953         struct net_device *dev = tp->dev;
6954         int err;
6955         u16 pci_cmd;
6956
6957         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6958                 return 0;
6959
6960         /* Turn off SERR reporting in case MSI terminates with Master
6961          * Abort.
6962          */
6963         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6964         pci_write_config_word(tp->pdev, PCI_COMMAND,
6965                               pci_cmd & ~PCI_COMMAND_SERR);
6966
6967         err = tg3_test_interrupt(tp);
6968
6969         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6970
6971         if (!err)
6972                 return 0;
6973
6974         /* other failures */
6975         if (err != -EIO)
6976                 return err;
6977
6978         /* MSI test failed, go back to INTx mode */
6979         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6980                "switching to INTx mode. Please report this failure to "
6981                "the PCI maintainer and include system chipset information.\n",
6982                        tp->dev->name);
6983
6984         free_irq(tp->pdev->irq, dev);
6985         pci_disable_msi(tp->pdev);
6986
6987         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6988
6989         err = tg3_request_irq(tp);
6990         if (err)
6991                 return err;
6992
6993         /* Need to reset the chip because the MSI cycle may have terminated
6994          * with Master Abort.
6995          */
6996         tg3_full_lock(tp, 1);
6997
6998         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6999         err = tg3_init_hw(tp, 1);
7000
7001         tg3_full_unlock(tp);
7002
7003         if (err)
7004                 free_irq(tp->pdev->irq, dev);
7005
7006         return err;
7007 }
7008
7009 static int tg3_open(struct net_device *dev)
7010 {
7011         struct tg3 *tp = netdev_priv(dev);
7012         int err;
7013
7014         netif_carrier_off(tp->dev);
7015
7016         tg3_full_lock(tp, 0);
7017
7018         err = tg3_set_power_state(tp, PCI_D0);
7019         if (err) {
7020                 tg3_full_unlock(tp);
7021                 return err;
7022         }
7023
7024         tg3_disable_ints(tp);
7025         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7026
7027         tg3_full_unlock(tp);
7028
7029         /* The placement of this call is tied
7030          * to the setup and use of Host TX descriptors.
7031          */
7032         err = tg3_alloc_consistent(tp);
7033         if (err)
7034                 return err;
7035
7036         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7037             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7038             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7039             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7040               (tp->pdev_peer == tp->pdev))) {
7041                 /* All MSI supporting chips should support tagged
7042                  * status.  Assert that this is the case.
7043                  */
7044                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7045                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7046                                "Not using MSI.\n", tp->dev->name);
7047                 } else if (pci_enable_msi(tp->pdev) == 0) {
7048                         u32 msi_mode;
7049
7050                         msi_mode = tr32(MSGINT_MODE);
7051                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7052                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7053                 }
7054         }
7055         err = tg3_request_irq(tp);
7056
7057         if (err) {
7058                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7059                         pci_disable_msi(tp->pdev);
7060                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7061                 }
7062                 tg3_free_consistent(tp);
7063                 return err;
7064         }
7065
7066         tg3_full_lock(tp, 0);
7067
7068         err = tg3_init_hw(tp, 1);
7069         if (err) {
7070                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7071                 tg3_free_rings(tp);
7072         } else {
7073                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7074                         tp->timer_offset = HZ;
7075                 else
7076                         tp->timer_offset = HZ / 10;
7077
7078                 BUG_ON(tp->timer_offset > HZ);
7079                 tp->timer_counter = tp->timer_multiplier =
7080                         (HZ / tp->timer_offset);
7081                 tp->asf_counter = tp->asf_multiplier =
7082                         ((HZ / tp->timer_offset) * 2);
7083
7084                 init_timer(&tp->timer);
7085                 tp->timer.expires = jiffies + tp->timer_offset;
7086                 tp->timer.data = (unsigned long) tp;
7087                 tp->timer.function = tg3_timer;
7088         }
7089
7090         tg3_full_unlock(tp);
7091
7092         if (err) {
7093                 free_irq(tp->pdev->irq, dev);
7094                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7095                         pci_disable_msi(tp->pdev);
7096                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7097                 }
7098                 tg3_free_consistent(tp);
7099                 return err;
7100         }
7101
7102         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7103                 err = tg3_test_msi(tp);
7104
7105                 if (err) {
7106                         tg3_full_lock(tp, 0);
7107
7108                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7109                                 pci_disable_msi(tp->pdev);
7110                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7111                         }
7112                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7113                         tg3_free_rings(tp);
7114                         tg3_free_consistent(tp);
7115
7116                         tg3_full_unlock(tp);
7117
7118                         return err;
7119                 }
7120
7121                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7122                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7123                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7124
7125                                 tw32(PCIE_TRANSACTION_CFG,
7126                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7127                         }
7128                 }
7129         }
7130
7131         tg3_full_lock(tp, 0);
7132
7133         add_timer(&tp->timer);
7134         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7135         tg3_enable_ints(tp);
7136
7137         tg3_full_unlock(tp);
7138
7139         netif_start_queue(dev);
7140
7141         return 0;
7142 }
7143
7144 #if 0
7145 /*static*/ void tg3_dump_state(struct tg3 *tp)
7146 {
7147         u32 val32, val32_2, val32_3, val32_4, val32_5;
7148         u16 val16;
7149         int i;
7150
7151         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7152         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7153         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7154                val16, val32);
7155
7156         /* MAC block */
7157         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7158                tr32(MAC_MODE), tr32(MAC_STATUS));
7159         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7160                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7161         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7162                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7163         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7164                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7165
7166         /* Send data initiator control block */
7167         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7168                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7169         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7170                tr32(SNDDATAI_STATSCTRL));
7171
7172         /* Send data completion control block */
7173         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7174
7175         /* Send BD ring selector block */
7176         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7177                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7178
7179         /* Send BD initiator control block */
7180         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7181                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7182
7183         /* Send BD completion control block */
7184         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7185
7186         /* Receive list placement control block */
7187         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7188                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7189         printk("       RCVLPC_STATSCTRL[%08x]\n",
7190                tr32(RCVLPC_STATSCTRL));
7191
7192         /* Receive data and receive BD initiator control block */
7193         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7194                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7195
7196         /* Receive data completion control block */
7197         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7198                tr32(RCVDCC_MODE));
7199
7200         /* Receive BD initiator control block */
7201         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7202                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7203
7204         /* Receive BD completion control block */
7205         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7206                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7207
7208         /* Receive list selector control block */
7209         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7210                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7211
7212         /* Mbuf cluster free block */
7213         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7214                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7215
7216         /* Host coalescing control block */
7217         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7218                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7219         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7220                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7221                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7222         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7223                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7224                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7225         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7226                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7227         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7228                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7229
7230         /* Memory arbiter control block */
7231         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7232                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7233
7234         /* Buffer manager control block */
7235         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7236                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7237         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7238                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7239         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7240                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7241                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7242                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7243
7244         /* Read DMA control block */
7245         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7246                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7247
7248         /* Write DMA control block */
7249         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7250                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7251
7252         /* DMA completion block */
7253         printk("DEBUG: DMAC_MODE[%08x]\n",
7254                tr32(DMAC_MODE));
7255
7256         /* GRC block */
7257         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7258                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7259         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7260                tr32(GRC_LOCAL_CTRL));
7261
7262         /* TG3_BDINFOs */
7263         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7264                tr32(RCVDBDI_JUMBO_BD + 0x0),
7265                tr32(RCVDBDI_JUMBO_BD + 0x4),
7266                tr32(RCVDBDI_JUMBO_BD + 0x8),
7267                tr32(RCVDBDI_JUMBO_BD + 0xc));
7268         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7269                tr32(RCVDBDI_STD_BD + 0x0),
7270                tr32(RCVDBDI_STD_BD + 0x4),
7271                tr32(RCVDBDI_STD_BD + 0x8),
7272                tr32(RCVDBDI_STD_BD + 0xc));
7273         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7274                tr32(RCVDBDI_MINI_BD + 0x0),
7275                tr32(RCVDBDI_MINI_BD + 0x4),
7276                tr32(RCVDBDI_MINI_BD + 0x8),
7277                tr32(RCVDBDI_MINI_BD + 0xc));
7278
7279         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7280         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7281         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7282         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7283         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7284                val32, val32_2, val32_3, val32_4);
7285
7286         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7287         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7288         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7289         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7290         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7291                val32, val32_2, val32_3, val32_4);
7292
7293         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7294         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7295         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7296         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7297         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7298         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7299                val32, val32_2, val32_3, val32_4, val32_5);
7300
7301         /* SW status block */
7302         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7303                tp->hw_status->status,
7304                tp->hw_status->status_tag,
7305                tp->hw_status->rx_jumbo_consumer,
7306                tp->hw_status->rx_consumer,
7307                tp->hw_status->rx_mini_consumer,
7308                tp->hw_status->idx[0].rx_producer,
7309                tp->hw_status->idx[0].tx_consumer);
7310
7311         /* SW statistics block */
7312         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7313                ((u32 *)tp->hw_stats)[0],
7314                ((u32 *)tp->hw_stats)[1],
7315                ((u32 *)tp->hw_stats)[2],
7316                ((u32 *)tp->hw_stats)[3]);
7317
7318         /* Mailboxes */
7319         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7320                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7321                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7322                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7323                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7324
7325         /* NIC side send descriptors. */
7326         for (i = 0; i < 6; i++) {
7327                 unsigned long txd;
7328
7329                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7330                         + (i * sizeof(struct tg3_tx_buffer_desc));
7331                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7332                        i,
7333                        readl(txd + 0x0), readl(txd + 0x4),
7334                        readl(txd + 0x8), readl(txd + 0xc));
7335         }
7336
7337         /* NIC side RX descriptors. */
7338         for (i = 0; i < 6; i++) {
7339                 unsigned long rxd;
7340
7341                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7342                         + (i * sizeof(struct tg3_rx_buffer_desc));
7343                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7344                        i,
7345                        readl(rxd + 0x0), readl(rxd + 0x4),
7346                        readl(rxd + 0x8), readl(rxd + 0xc));
7347                 rxd += (4 * sizeof(u32));
7348                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7349                        i,
7350                        readl(rxd + 0x0), readl(rxd + 0x4),
7351                        readl(rxd + 0x8), readl(rxd + 0xc));
7352         }
7353
7354         for (i = 0; i < 6; i++) {
7355                 unsigned long rxd;
7356
7357                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7358                         + (i * sizeof(struct tg3_rx_buffer_desc));
7359                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7360                        i,
7361                        readl(rxd + 0x0), readl(rxd + 0x4),
7362                        readl(rxd + 0x8), readl(rxd + 0xc));
7363                 rxd += (4 * sizeof(u32));
7364                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7365                        i,
7366                        readl(rxd + 0x0), readl(rxd + 0x4),
7367                        readl(rxd + 0x8), readl(rxd + 0xc));
7368         }
7369 }
7370 #endif
7371
7372 static struct net_device_stats *tg3_get_stats(struct net_device *);
7373 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7374
7375 static int tg3_close(struct net_device *dev)
7376 {
7377         struct tg3 *tp = netdev_priv(dev);
7378
7379         /* Calling flush_scheduled_work() may deadlock because
7380          * linkwatch_event() may be on the workqueue and it will try to get
7381          * the rtnl_lock which we are holding.
7382          */
7383         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7384                 msleep(1);
7385
7386         netif_stop_queue(dev);
7387
7388         del_timer_sync(&tp->timer);
7389
7390         tg3_full_lock(tp, 1);
7391 #if 0
7392         tg3_dump_state(tp);
7393 #endif
7394
7395         tg3_disable_ints(tp);
7396
7397         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7398         tg3_free_rings(tp);
7399         tp->tg3_flags &=
7400                 ~(TG3_FLAG_INIT_COMPLETE |
7401                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7402
7403         tg3_full_unlock(tp);
7404
7405         free_irq(tp->pdev->irq, dev);
7406         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7407                 pci_disable_msi(tp->pdev);
7408                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7409         }
7410
7411         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7412                sizeof(tp->net_stats_prev));
7413         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7414                sizeof(tp->estats_prev));
7415
7416         tg3_free_consistent(tp);
7417
7418         tg3_set_power_state(tp, PCI_D3hot);
7419
7420         netif_carrier_off(tp->dev);
7421
7422         return 0;
7423 }
7424
7425 static inline unsigned long get_stat64(tg3_stat64_t *val)
7426 {
7427         unsigned long ret;
7428
7429 #if (BITS_PER_LONG == 32)
7430         ret = val->low;
7431 #else
7432         ret = ((u64)val->high << 32) | ((u64)val->low);
7433 #endif
7434         return ret;
7435 }
7436
7437 static unsigned long calc_crc_errors(struct tg3 *tp)
7438 {
7439         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7440
7441         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7442             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7443              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7444                 u32 val;
7445
7446                 spin_lock_bh(&tp->lock);
7447                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7448                         tg3_writephy(tp, MII_TG3_TEST1,
7449                                      val | MII_TG3_TEST1_CRC_EN);
7450                         tg3_readphy(tp, 0x14, &val);
7451                 } else
7452                         val = 0;
7453                 spin_unlock_bh(&tp->lock);
7454
7455                 tp->phy_crc_errors += val;
7456
7457                 return tp->phy_crc_errors;
7458         }
7459
7460         return get_stat64(&hw_stats->rx_fcs_errors);
7461 }
7462
7463 #define ESTAT_ADD(member) \
7464         estats->member =        old_estats->member + \
7465                                 get_stat64(&hw_stats->member)
7466
7467 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7468 {
7469         struct tg3_ethtool_stats *estats = &tp->estats;
7470         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7471         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7472
7473         if (!hw_stats)
7474                 return old_estats;
7475
7476         ESTAT_ADD(rx_octets);
7477         ESTAT_ADD(rx_fragments);
7478         ESTAT_ADD(rx_ucast_packets);
7479         ESTAT_ADD(rx_mcast_packets);
7480         ESTAT_ADD(rx_bcast_packets);
7481         ESTAT_ADD(rx_fcs_errors);
7482         ESTAT_ADD(rx_align_errors);
7483         ESTAT_ADD(rx_xon_pause_rcvd);
7484         ESTAT_ADD(rx_xoff_pause_rcvd);
7485         ESTAT_ADD(rx_mac_ctrl_rcvd);
7486         ESTAT_ADD(rx_xoff_entered);
7487         ESTAT_ADD(rx_frame_too_long_errors);
7488         ESTAT_ADD(rx_jabbers);
7489         ESTAT_ADD(rx_undersize_packets);
7490         ESTAT_ADD(rx_in_length_errors);
7491         ESTAT_ADD(rx_out_length_errors);
7492         ESTAT_ADD(rx_64_or_less_octet_packets);
7493         ESTAT_ADD(rx_65_to_127_octet_packets);
7494         ESTAT_ADD(rx_128_to_255_octet_packets);
7495         ESTAT_ADD(rx_256_to_511_octet_packets);
7496         ESTAT_ADD(rx_512_to_1023_octet_packets);
7497         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7498         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7499         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7500         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7501         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7502
7503         ESTAT_ADD(tx_octets);
7504         ESTAT_ADD(tx_collisions);
7505         ESTAT_ADD(tx_xon_sent);
7506         ESTAT_ADD(tx_xoff_sent);
7507         ESTAT_ADD(tx_flow_control);
7508         ESTAT_ADD(tx_mac_errors);
7509         ESTAT_ADD(tx_single_collisions);
7510         ESTAT_ADD(tx_mult_collisions);
7511         ESTAT_ADD(tx_deferred);
7512         ESTAT_ADD(tx_excessive_collisions);
7513         ESTAT_ADD(tx_late_collisions);
7514         ESTAT_ADD(tx_collide_2times);
7515         ESTAT_ADD(tx_collide_3times);
7516         ESTAT_ADD(tx_collide_4times);
7517         ESTAT_ADD(tx_collide_5times);
7518         ESTAT_ADD(tx_collide_6times);
7519         ESTAT_ADD(tx_collide_7times);
7520         ESTAT_ADD(tx_collide_8times);
7521         ESTAT_ADD(tx_collide_9times);
7522         ESTAT_ADD(tx_collide_10times);
7523         ESTAT_ADD(tx_collide_11times);
7524         ESTAT_ADD(tx_collide_12times);
7525         ESTAT_ADD(tx_collide_13times);
7526         ESTAT_ADD(tx_collide_14times);
7527         ESTAT_ADD(tx_collide_15times);
7528         ESTAT_ADD(tx_ucast_packets);
7529         ESTAT_ADD(tx_mcast_packets);
7530         ESTAT_ADD(tx_bcast_packets);
7531         ESTAT_ADD(tx_carrier_sense_errors);
7532         ESTAT_ADD(tx_discards);
7533         ESTAT_ADD(tx_errors);
7534
7535         ESTAT_ADD(dma_writeq_full);
7536         ESTAT_ADD(dma_write_prioq_full);
7537         ESTAT_ADD(rxbds_empty);
7538         ESTAT_ADD(rx_discards);
7539         ESTAT_ADD(rx_errors);
7540         ESTAT_ADD(rx_threshold_hit);
7541
7542         ESTAT_ADD(dma_readq_full);
7543         ESTAT_ADD(dma_read_prioq_full);
7544         ESTAT_ADD(tx_comp_queue_full);
7545
7546         ESTAT_ADD(ring_set_send_prod_index);
7547         ESTAT_ADD(ring_status_update);
7548         ESTAT_ADD(nic_irqs);
7549         ESTAT_ADD(nic_avoided_irqs);
7550         ESTAT_ADD(nic_tx_threshold_hit);
7551
7552         return estats;
7553 }
7554
7555 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7556 {
7557         struct tg3 *tp = netdev_priv(dev);
7558         struct net_device_stats *stats = &tp->net_stats;
7559         struct net_device_stats *old_stats = &tp->net_stats_prev;
7560         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7561
7562         if (!hw_stats)
7563                 return old_stats;
7564
7565         stats->rx_packets = old_stats->rx_packets +
7566                 get_stat64(&hw_stats->rx_ucast_packets) +
7567                 get_stat64(&hw_stats->rx_mcast_packets) +
7568                 get_stat64(&hw_stats->rx_bcast_packets);
7569
7570         stats->tx_packets = old_stats->tx_packets +
7571                 get_stat64(&hw_stats->tx_ucast_packets) +
7572                 get_stat64(&hw_stats->tx_mcast_packets) +
7573                 get_stat64(&hw_stats->tx_bcast_packets);
7574
7575         stats->rx_bytes = old_stats->rx_bytes +
7576                 get_stat64(&hw_stats->rx_octets);
7577         stats->tx_bytes = old_stats->tx_bytes +
7578                 get_stat64(&hw_stats->tx_octets);
7579
7580         stats->rx_errors = old_stats->rx_errors +
7581                 get_stat64(&hw_stats->rx_errors);
7582         stats->tx_errors = old_stats->tx_errors +
7583                 get_stat64(&hw_stats->tx_errors) +
7584                 get_stat64(&hw_stats->tx_mac_errors) +
7585                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7586                 get_stat64(&hw_stats->tx_discards);
7587
7588         stats->multicast = old_stats->multicast +
7589                 get_stat64(&hw_stats->rx_mcast_packets);
7590         stats->collisions = old_stats->collisions +
7591                 get_stat64(&hw_stats->tx_collisions);
7592
7593         stats->rx_length_errors = old_stats->rx_length_errors +
7594                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7595                 get_stat64(&hw_stats->rx_undersize_packets);
7596
7597         stats->rx_over_errors = old_stats->rx_over_errors +
7598                 get_stat64(&hw_stats->rxbds_empty);
7599         stats->rx_frame_errors = old_stats->rx_frame_errors +
7600                 get_stat64(&hw_stats->rx_align_errors);
7601         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7602                 get_stat64(&hw_stats->tx_discards);
7603         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7604                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7605
7606         stats->rx_crc_errors = old_stats->rx_crc_errors +
7607                 calc_crc_errors(tp);
7608
7609         stats->rx_missed_errors = old_stats->rx_missed_errors +
7610                 get_stat64(&hw_stats->rx_discards);
7611
7612         return stats;
7613 }
7614
7615 static inline u32 calc_crc(unsigned char *buf, int len)
7616 {
7617         u32 reg;
7618         u32 tmp;
7619         int j, k;
7620
7621         reg = 0xffffffff;
7622
7623         for (j = 0; j < len; j++) {
7624                 reg ^= buf[j];
7625
7626                 for (k = 0; k < 8; k++) {
7627                         tmp = reg & 0x01;
7628
7629                         reg >>= 1;
7630
7631                         if (tmp) {
7632                                 reg ^= 0xedb88320;
7633                         }
7634                 }
7635         }
7636
7637         return ~reg;
7638 }
7639
7640 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7641 {
7642         /* accept or reject all multicast frames */
7643         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7644         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7645         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7646         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7647 }
7648
7649 static void __tg3_set_rx_mode(struct net_device *dev)
7650 {
7651         struct tg3 *tp = netdev_priv(dev);
7652         u32 rx_mode;
7653
7654         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7655                                   RX_MODE_KEEP_VLAN_TAG);
7656
7657         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7658          * flag clear.
7659          */
7660 #if TG3_VLAN_TAG_USED
7661         if (!tp->vlgrp &&
7662             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7663                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7664 #else
7665         /* By definition, VLAN is disabled always in this
7666          * case.
7667          */
7668         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7669                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7670 #endif
7671
7672         if (dev->flags & IFF_PROMISC) {
7673                 /* Promiscuous mode. */
7674                 rx_mode |= RX_MODE_PROMISC;
7675         } else if (dev->flags & IFF_ALLMULTI) {
7676                 /* Accept all multicast. */
7677                 tg3_set_multi (tp, 1);
7678         } else if (dev->mc_count < 1) {
7679                 /* Reject all multicast. */
7680                 tg3_set_multi (tp, 0);
7681         } else {
7682                 /* Accept one or more multicast(s). */
7683                 struct dev_mc_list *mclist;
7684                 unsigned int i;
7685                 u32 mc_filter[4] = { 0, };
7686                 u32 regidx;
7687                 u32 bit;
7688                 u32 crc;
7689
7690                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7691                      i++, mclist = mclist->next) {
7692
7693                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7694                         bit = ~crc & 0x7f;
7695                         regidx = (bit & 0x60) >> 5;
7696                         bit &= 0x1f;
7697                         mc_filter[regidx] |= (1 << bit);
7698                 }
7699
7700                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7701                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7702                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7703                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7704         }
7705
7706         if (rx_mode != tp->rx_mode) {
7707                 tp->rx_mode = rx_mode;
7708                 tw32_f(MAC_RX_MODE, rx_mode);
7709                 udelay(10);
7710         }
7711 }
7712
7713 static void tg3_set_rx_mode(struct net_device *dev)
7714 {
7715         struct tg3 *tp = netdev_priv(dev);
7716
7717         if (!netif_running(dev))
7718                 return;
7719
7720         tg3_full_lock(tp, 0);
7721         __tg3_set_rx_mode(dev);
7722         tg3_full_unlock(tp);
7723 }
7724
7725 #define TG3_REGDUMP_LEN         (32 * 1024)
7726
7727 static int tg3_get_regs_len(struct net_device *dev)
7728 {
7729         return TG3_REGDUMP_LEN;
7730 }
7731
7732 static void tg3_get_regs(struct net_device *dev,
7733                 struct ethtool_regs *regs, void *_p)
7734 {
7735         u32 *p = _p;
7736         struct tg3 *tp = netdev_priv(dev);
7737         u8 *orig_p = _p;
7738         int i;
7739
7740         regs->version = 0;
7741
7742         memset(p, 0, TG3_REGDUMP_LEN);
7743
7744         if (tp->link_config.phy_is_low_power)
7745                 return;
7746
7747         tg3_full_lock(tp, 0);
7748
7749 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7750 #define GET_REG32_LOOP(base,len)                \
7751 do {    p = (u32 *)(orig_p + (base));           \
7752         for (i = 0; i < len; i += 4)            \
7753                 __GET_REG32((base) + i);        \
7754 } while (0)
7755 #define GET_REG32_1(reg)                        \
7756 do {    p = (u32 *)(orig_p + (reg));            \
7757         __GET_REG32((reg));                     \
7758 } while (0)
7759
7760         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7761         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7762         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7763         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7764         GET_REG32_1(SNDDATAC_MODE);
7765         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7766         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7767         GET_REG32_1(SNDBDC_MODE);
7768         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7769         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7770         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7771         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7772         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7773         GET_REG32_1(RCVDCC_MODE);
7774         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7775         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7776         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7777         GET_REG32_1(MBFREE_MODE);
7778         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7779         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7780         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7781         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7782         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7783         GET_REG32_1(RX_CPU_MODE);
7784         GET_REG32_1(RX_CPU_STATE);
7785         GET_REG32_1(RX_CPU_PGMCTR);
7786         GET_REG32_1(RX_CPU_HWBKPT);
7787         GET_REG32_1(TX_CPU_MODE);
7788         GET_REG32_1(TX_CPU_STATE);
7789         GET_REG32_1(TX_CPU_PGMCTR);
7790         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7791         GET_REG32_LOOP(FTQ_RESET, 0x120);
7792         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7793         GET_REG32_1(DMAC_MODE);
7794         GET_REG32_LOOP(GRC_MODE, 0x4c);
7795         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7796                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7797
7798 #undef __GET_REG32
7799 #undef GET_REG32_LOOP
7800 #undef GET_REG32_1
7801
7802         tg3_full_unlock(tp);
7803 }
7804
7805 static int tg3_get_eeprom_len(struct net_device *dev)
7806 {
7807         struct tg3 *tp = netdev_priv(dev);
7808
7809         return tp->nvram_size;
7810 }
7811
7812 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7813 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7814
7815 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7816 {
7817         struct tg3 *tp = netdev_priv(dev);
7818         int ret;
7819         u8  *pd;
7820         u32 i, offset, len, val, b_offset, b_count;
7821
7822         if (tp->link_config.phy_is_low_power)
7823                 return -EAGAIN;
7824
7825         offset = eeprom->offset;
7826         len = eeprom->len;
7827         eeprom->len = 0;
7828
7829         eeprom->magic = TG3_EEPROM_MAGIC;
7830
7831         if (offset & 3) {
7832                 /* adjustments to start on required 4 byte boundary */
7833                 b_offset = offset & 3;
7834                 b_count = 4 - b_offset;
7835                 if (b_count > len) {
7836                         /* i.e. offset=1 len=2 */
7837                         b_count = len;
7838                 }
7839                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7840                 if (ret)
7841                         return ret;
7842                 val = cpu_to_le32(val);
7843                 memcpy(data, ((char*)&val) + b_offset, b_count);
7844                 len -= b_count;
7845                 offset += b_count;
7846                 eeprom->len += b_count;
7847         }
7848
7849         /* read bytes upto the last 4 byte boundary */
7850         pd = &data[eeprom->len];
7851         for (i = 0; i < (len - (len & 3)); i += 4) {
7852                 ret = tg3_nvram_read(tp, offset + i, &val);
7853                 if (ret) {
7854                         eeprom->len += i;
7855                         return ret;
7856                 }
7857                 val = cpu_to_le32(val);
7858                 memcpy(pd + i, &val, 4);
7859         }
7860         eeprom->len += i;
7861
7862         if (len & 3) {
7863                 /* read last bytes not ending on 4 byte boundary */
7864                 pd = &data[eeprom->len];
7865                 b_count = len & 3;
7866                 b_offset = offset + len - b_count;
7867                 ret = tg3_nvram_read(tp, b_offset, &val);
7868                 if (ret)
7869                         return ret;
7870                 val = cpu_to_le32(val);
7871                 memcpy(pd, ((char*)&val), b_count);
7872                 eeprom->len += b_count;
7873         }
7874         return 0;
7875 }
7876
7877 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7878
7879 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7880 {
7881         struct tg3 *tp = netdev_priv(dev);
7882         int ret;
7883         u32 offset, len, b_offset, odd_len, start, end;
7884         u8 *buf;
7885
7886         if (tp->link_config.phy_is_low_power)
7887                 return -EAGAIN;
7888
7889         if (eeprom->magic != TG3_EEPROM_MAGIC)
7890                 return -EINVAL;
7891
7892         offset = eeprom->offset;
7893         len = eeprom->len;
7894
7895         if ((b_offset = (offset & 3))) {
7896                 /* adjustments to start on required 4 byte boundary */
7897                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7898                 if (ret)
7899                         return ret;
7900                 start = cpu_to_le32(start);
7901                 len += b_offset;
7902                 offset &= ~3;
7903                 if (len < 4)
7904                         len = 4;
7905         }
7906
7907         odd_len = 0;
7908         if (len & 3) {
7909                 /* adjustments to end on required 4 byte boundary */
7910                 odd_len = 1;
7911                 len = (len + 3) & ~3;
7912                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7913                 if (ret)
7914                         return ret;
7915                 end = cpu_to_le32(end);
7916         }
7917
7918         buf = data;
7919         if (b_offset || odd_len) {
7920                 buf = kmalloc(len, GFP_KERNEL);
7921                 if (buf == 0)
7922                         return -ENOMEM;
7923                 if (b_offset)
7924                         memcpy(buf, &start, 4);
7925                 if (odd_len)
7926                         memcpy(buf+len-4, &end, 4);
7927                 memcpy(buf + b_offset, data, eeprom->len);
7928         }
7929
7930         ret = tg3_nvram_write_block(tp, offset, len, buf);
7931
7932         if (buf != data)
7933                 kfree(buf);
7934
7935         return ret;
7936 }
7937
7938 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7939 {
7940         struct tg3 *tp = netdev_priv(dev);
7941
7942         cmd->supported = (SUPPORTED_Autoneg);
7943
7944         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7945                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7946                                    SUPPORTED_1000baseT_Full);
7947
7948         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7949                 cmd->supported |= (SUPPORTED_100baseT_Half |
7950                                   SUPPORTED_100baseT_Full |
7951                                   SUPPORTED_10baseT_Half |
7952                                   SUPPORTED_10baseT_Full |
7953                                   SUPPORTED_MII);
7954                 cmd->port = PORT_TP;
7955         } else {
7956                 cmd->supported |= SUPPORTED_FIBRE;
7957                 cmd->port = PORT_FIBRE;
7958         }
7959
7960         cmd->advertising = tp->link_config.advertising;
7961         if (netif_running(dev)) {
7962                 cmd->speed = tp->link_config.active_speed;
7963                 cmd->duplex = tp->link_config.active_duplex;
7964         }
7965         cmd->phy_address = PHY_ADDR;
7966         cmd->transceiver = 0;
7967         cmd->autoneg = tp->link_config.autoneg;
7968         cmd->maxtxpkt = 0;
7969         cmd->maxrxpkt = 0;
7970         return 0;
7971 }
7972
7973 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7974 {
7975         struct tg3 *tp = netdev_priv(dev);
7976
7977         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7978                 /* These are the only valid advertisement bits allowed.  */
7979                 if (cmd->autoneg == AUTONEG_ENABLE &&
7980                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7981                                           ADVERTISED_1000baseT_Full |
7982                                           ADVERTISED_Autoneg |
7983                                           ADVERTISED_FIBRE)))
7984                         return -EINVAL;
7985                 /* Fiber can only do SPEED_1000.  */
7986                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7987                          (cmd->speed != SPEED_1000))
7988                         return -EINVAL;
7989         /* Copper cannot force SPEED_1000.  */
7990         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7991                    (cmd->speed == SPEED_1000))
7992                 return -EINVAL;
7993         else if ((cmd->speed == SPEED_1000) &&
7994                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7995                 return -EINVAL;
7996
7997         tg3_full_lock(tp, 0);
7998
7999         tp->link_config.autoneg = cmd->autoneg;
8000         if (cmd->autoneg == AUTONEG_ENABLE) {
8001                 tp->link_config.advertising = cmd->advertising;
8002                 tp->link_config.speed = SPEED_INVALID;
8003                 tp->link_config.duplex = DUPLEX_INVALID;
8004         } else {
8005                 tp->link_config.advertising = 0;
8006                 tp->link_config.speed = cmd->speed;
8007                 tp->link_config.duplex = cmd->duplex;
8008         }
8009
8010         tp->link_config.orig_speed = tp->link_config.speed;
8011         tp->link_config.orig_duplex = tp->link_config.duplex;
8012         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8013
8014         if (netif_running(dev))
8015                 tg3_setup_phy(tp, 1);
8016
8017         tg3_full_unlock(tp);
8018
8019         return 0;
8020 }
8021
8022 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8023 {
8024         struct tg3 *tp = netdev_priv(dev);
8025
8026         strcpy(info->driver, DRV_MODULE_NAME);
8027         strcpy(info->version, DRV_MODULE_VERSION);
8028         strcpy(info->fw_version, tp->fw_ver);
8029         strcpy(info->bus_info, pci_name(tp->pdev));
8030 }
8031
8032 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8033 {
8034         struct tg3 *tp = netdev_priv(dev);
8035
8036         wol->supported = WAKE_MAGIC;
8037         wol->wolopts = 0;
8038         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8039                 wol->wolopts = WAKE_MAGIC;
8040         memset(&wol->sopass, 0, sizeof(wol->sopass));
8041 }
8042
8043 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8044 {
8045         struct tg3 *tp = netdev_priv(dev);
8046
8047         if (wol->wolopts & ~WAKE_MAGIC)
8048                 return -EINVAL;
8049         if ((wol->wolopts & WAKE_MAGIC) &&
8050             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8051             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8052                 return -EINVAL;
8053
8054         spin_lock_bh(&tp->lock);
8055         if (wol->wolopts & WAKE_MAGIC)
8056                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8057         else
8058                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8059         spin_unlock_bh(&tp->lock);
8060
8061         return 0;
8062 }
8063
8064 static u32 tg3_get_msglevel(struct net_device *dev)
8065 {
8066         struct tg3 *tp = netdev_priv(dev);
8067         return tp->msg_enable;
8068 }
8069
8070 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8071 {
8072         struct tg3 *tp = netdev_priv(dev);
8073         tp->msg_enable = value;
8074 }
8075
8076 static int tg3_set_tso(struct net_device *dev, u32 value)
8077 {
8078         struct tg3 *tp = netdev_priv(dev);
8079
8080         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8081                 if (value)
8082                         return -EINVAL;
8083                 return 0;
8084         }
8085         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8086             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8087                 if (value)
8088                         dev->features |= NETIF_F_TSO6;
8089                 else
8090                         dev->features &= ~NETIF_F_TSO6;
8091         }
8092         return ethtool_op_set_tso(dev, value);
8093 }
8094
8095 static int tg3_nway_reset(struct net_device *dev)
8096 {
8097         struct tg3 *tp = netdev_priv(dev);
8098         u32 bmcr;
8099         int r;
8100
8101         if (!netif_running(dev))
8102                 return -EAGAIN;
8103
8104         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8105                 return -EINVAL;
8106
8107         spin_lock_bh(&tp->lock);
8108         r = -EINVAL;
8109         tg3_readphy(tp, MII_BMCR, &bmcr);
8110         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8111             ((bmcr & BMCR_ANENABLE) ||
8112              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8113                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8114                                            BMCR_ANENABLE);
8115                 r = 0;
8116         }
8117         spin_unlock_bh(&tp->lock);
8118
8119         return r;
8120 }
8121
8122 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8123 {
8124         struct tg3 *tp = netdev_priv(dev);
8125
8126         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8127         ering->rx_mini_max_pending = 0;
8128         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8129                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8130         else
8131                 ering->rx_jumbo_max_pending = 0;
8132
8133         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8134
8135         ering->rx_pending = tp->rx_pending;
8136         ering->rx_mini_pending = 0;
8137         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8138                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8139         else
8140                 ering->rx_jumbo_pending = 0;
8141
8142         ering->tx_pending = tp->tx_pending;
8143 }
8144
8145 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8146 {
8147         struct tg3 *tp = netdev_priv(dev);
8148         int irq_sync = 0, err = 0;
8149
8150         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8151             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8152             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8153             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8154             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8155              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8156                 return -EINVAL;
8157
8158         if (netif_running(dev)) {
8159                 tg3_netif_stop(tp);
8160                 irq_sync = 1;
8161         }
8162
8163         tg3_full_lock(tp, irq_sync);
8164
8165         tp->rx_pending = ering->rx_pending;
8166
8167         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8168             tp->rx_pending > 63)
8169                 tp->rx_pending = 63;
8170         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8171         tp->tx_pending = ering->tx_pending;
8172
8173         if (netif_running(dev)) {
8174                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8175                 err = tg3_restart_hw(tp, 1);
8176                 if (!err)
8177                         tg3_netif_start(tp);
8178         }
8179
8180         tg3_full_unlock(tp);
8181
8182         return err;
8183 }
8184
8185 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8186 {
8187         struct tg3 *tp = netdev_priv(dev);
8188
8189         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8190         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8191         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8192 }
8193
8194 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8195 {
8196         struct tg3 *tp = netdev_priv(dev);
8197         int irq_sync = 0, err = 0;
8198
8199         if (netif_running(dev)) {
8200                 tg3_netif_stop(tp);
8201                 irq_sync = 1;
8202         }
8203
8204         tg3_full_lock(tp, irq_sync);
8205
8206         if (epause->autoneg)
8207                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8208         else
8209                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8210         if (epause->rx_pause)
8211                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8212         else
8213                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8214         if (epause->tx_pause)
8215                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8216         else
8217                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8218
8219         if (netif_running(dev)) {
8220                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8221                 err = tg3_restart_hw(tp, 1);
8222                 if (!err)
8223                         tg3_netif_start(tp);
8224         }
8225
8226         tg3_full_unlock(tp);
8227
8228         return err;
8229 }
8230
8231 static u32 tg3_get_rx_csum(struct net_device *dev)
8232 {
8233         struct tg3 *tp = netdev_priv(dev);
8234         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8235 }
8236
8237 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8238 {
8239         struct tg3 *tp = netdev_priv(dev);
8240
8241         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8242                 if (data != 0)
8243                         return -EINVAL;
8244                 return 0;
8245         }
8246
8247         spin_lock_bh(&tp->lock);
8248         if (data)
8249                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8250         else
8251                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8252         spin_unlock_bh(&tp->lock);
8253
8254         return 0;
8255 }
8256
8257 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8258 {
8259         struct tg3 *tp = netdev_priv(dev);
8260
8261         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8262                 if (data != 0)
8263                         return -EINVAL;
8264                 return 0;
8265         }
8266
8267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8268             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8269                 ethtool_op_set_tx_hw_csum(dev, data);
8270         else
8271                 ethtool_op_set_tx_csum(dev, data);
8272
8273         return 0;
8274 }
8275
8276 static int tg3_get_stats_count (struct net_device *dev)
8277 {
8278         return TG3_NUM_STATS;
8279 }
8280
8281 static int tg3_get_test_count (struct net_device *dev)
8282 {
8283         return TG3_NUM_TEST;
8284 }
8285
8286 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8287 {
8288         switch (stringset) {
8289         case ETH_SS_STATS:
8290                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8291                 break;
8292         case ETH_SS_TEST:
8293                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8294                 break;
8295         default:
8296                 WARN_ON(1);     /* we need a WARN() */
8297                 break;
8298         }
8299 }
8300
8301 static int tg3_phys_id(struct net_device *dev, u32 data)
8302 {
8303         struct tg3 *tp = netdev_priv(dev);
8304         int i;
8305
8306         if (!netif_running(tp->dev))
8307                 return -EAGAIN;
8308
8309         if (data == 0)
8310                 data = 2;
8311
8312         for (i = 0; i < (data * 2); i++) {
8313                 if ((i % 2) == 0)
8314                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8315                                            LED_CTRL_1000MBPS_ON |
8316                                            LED_CTRL_100MBPS_ON |
8317                                            LED_CTRL_10MBPS_ON |
8318                                            LED_CTRL_TRAFFIC_OVERRIDE |
8319                                            LED_CTRL_TRAFFIC_BLINK |
8320                                            LED_CTRL_TRAFFIC_LED);
8321
8322                 else
8323                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8324                                            LED_CTRL_TRAFFIC_OVERRIDE);
8325
8326                 if (msleep_interruptible(500))
8327                         break;
8328         }
8329         tw32(MAC_LED_CTRL, tp->led_ctrl);
8330         return 0;
8331 }
8332
8333 static void tg3_get_ethtool_stats (struct net_device *dev,
8334                                    struct ethtool_stats *estats, u64 *tmp_stats)
8335 {
8336         struct tg3 *tp = netdev_priv(dev);
8337         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8338 }
8339
8340 #define NVRAM_TEST_SIZE 0x100
8341 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8342 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8343 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8344
8345 static int tg3_test_nvram(struct tg3 *tp)
8346 {
8347         u32 *buf, csum, magic;
8348         int i, j, err = 0, size;
8349
8350         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8351                 return -EIO;
8352
8353         if (magic == TG3_EEPROM_MAGIC)
8354                 size = NVRAM_TEST_SIZE;
8355         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8356                 if ((magic & 0xe00000) == 0x200000)
8357                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8358                 else
8359                         return 0;
8360         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8361                 size = NVRAM_SELFBOOT_HW_SIZE;
8362         else
8363                 return -EIO;
8364
8365         buf = kmalloc(size, GFP_KERNEL);
8366         if (buf == NULL)
8367                 return -ENOMEM;
8368
8369         err = -EIO;
8370         for (i = 0, j = 0; i < size; i += 4, j++) {
8371                 u32 val;
8372
8373                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8374                         break;
8375                 buf[j] = cpu_to_le32(val);
8376         }
8377         if (i < size)
8378                 goto out;
8379
8380         /* Selfboot format */
8381         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8382             TG3_EEPROM_MAGIC_FW) {
8383                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8384
8385                 for (i = 0; i < size; i++)
8386                         csum8 += buf8[i];
8387
8388                 if (csum8 == 0) {
8389                         err = 0;
8390                         goto out;
8391                 }
8392
8393                 err = -EIO;
8394                 goto out;
8395         }
8396
8397         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8398             TG3_EEPROM_MAGIC_HW) {
8399                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8400                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8401                 u8 *buf8 = (u8 *) buf;
8402                 int j, k;
8403
8404                 /* Separate the parity bits and the data bytes.  */
8405                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8406                         if ((i == 0) || (i == 8)) {
8407                                 int l;
8408                                 u8 msk;
8409
8410                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8411                                         parity[k++] = buf8[i] & msk;
8412                                 i++;
8413                         }
8414                         else if (i == 16) {
8415                                 int l;
8416                                 u8 msk;
8417
8418                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8419                                         parity[k++] = buf8[i] & msk;
8420                                 i++;
8421
8422                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8423                                         parity[k++] = buf8[i] & msk;
8424                                 i++;
8425                         }
8426                         data[j++] = buf8[i];
8427                 }
8428
8429                 err = -EIO;
8430                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8431                         u8 hw8 = hweight8(data[i]);
8432
8433                         if ((hw8 & 0x1) && parity[i])
8434                                 goto out;
8435                         else if (!(hw8 & 0x1) && !parity[i])
8436                                 goto out;
8437                 }
8438                 err = 0;
8439                 goto out;
8440         }
8441
8442         /* Bootstrap checksum at offset 0x10 */
8443         csum = calc_crc((unsigned char *) buf, 0x10);
8444         if(csum != cpu_to_le32(buf[0x10/4]))
8445                 goto out;
8446
8447         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8448         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8449         if (csum != cpu_to_le32(buf[0xfc/4]))
8450                  goto out;
8451
8452         err = 0;
8453
8454 out:
8455         kfree(buf);
8456         return err;
8457 }
8458
8459 #define TG3_SERDES_TIMEOUT_SEC  2
8460 #define TG3_COPPER_TIMEOUT_SEC  6
8461
8462 static int tg3_test_link(struct tg3 *tp)
8463 {
8464         int i, max;
8465
8466         if (!netif_running(tp->dev))
8467                 return -ENODEV;
8468
8469         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8470                 max = TG3_SERDES_TIMEOUT_SEC;
8471         else
8472                 max = TG3_COPPER_TIMEOUT_SEC;
8473
8474         for (i = 0; i < max; i++) {
8475                 if (netif_carrier_ok(tp->dev))
8476                         return 0;
8477
8478                 if (msleep_interruptible(1000))
8479                         break;
8480         }
8481
8482         return -EIO;
8483 }
8484
8485 /* Only test the commonly used registers */
8486 static int tg3_test_registers(struct tg3 *tp)
8487 {
8488         int i, is_5705, is_5750;
8489         u32 offset, read_mask, write_mask, val, save_val, read_val;
8490         static struct {
8491                 u16 offset;
8492                 u16 flags;
8493 #define TG3_FL_5705     0x1
8494 #define TG3_FL_NOT_5705 0x2
8495 #define TG3_FL_NOT_5788 0x4
8496 #define TG3_FL_NOT_5750 0x8
8497                 u32 read_mask;
8498                 u32 write_mask;
8499         } reg_tbl[] = {
8500                 /* MAC Control Registers */
8501                 { MAC_MODE, TG3_FL_NOT_5705,
8502                         0x00000000, 0x00ef6f8c },
8503                 { MAC_MODE, TG3_FL_5705,
8504                         0x00000000, 0x01ef6b8c },
8505                 { MAC_STATUS, TG3_FL_NOT_5705,
8506                         0x03800107, 0x00000000 },
8507                 { MAC_STATUS, TG3_FL_5705,
8508                         0x03800100, 0x00000000 },
8509                 { MAC_ADDR_0_HIGH, 0x0000,
8510                         0x00000000, 0x0000ffff },
8511                 { MAC_ADDR_0_LOW, 0x0000,
8512                         0x00000000, 0xffffffff },
8513                 { MAC_RX_MTU_SIZE, 0x0000,
8514                         0x00000000, 0x0000ffff },
8515                 { MAC_TX_MODE, 0x0000,
8516                         0x00000000, 0x00000070 },
8517                 { MAC_TX_LENGTHS, 0x0000,
8518                         0x00000000, 0x00003fff },
8519                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8520                         0x00000000, 0x000007fc },
8521                 { MAC_RX_MODE, TG3_FL_5705,
8522                         0x00000000, 0x000007dc },
8523                 { MAC_HASH_REG_0, 0x0000,
8524                         0x00000000, 0xffffffff },
8525                 { MAC_HASH_REG_1, 0x0000,
8526                         0x00000000, 0xffffffff },
8527                 { MAC_HASH_REG_2, 0x0000,
8528                         0x00000000, 0xffffffff },
8529                 { MAC_HASH_REG_3, 0x0000,
8530                         0x00000000, 0xffffffff },
8531
8532                 /* Receive Data and Receive BD Initiator Control Registers. */
8533                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8534                         0x00000000, 0xffffffff },
8535                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8536                         0x00000000, 0xffffffff },
8537                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8538                         0x00000000, 0x00000003 },
8539                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8540                         0x00000000, 0xffffffff },
8541                 { RCVDBDI_STD_BD+0, 0x0000,
8542                         0x00000000, 0xffffffff },
8543                 { RCVDBDI_STD_BD+4, 0x0000,
8544                         0x00000000, 0xffffffff },
8545                 { RCVDBDI_STD_BD+8, 0x0000,
8546                         0x00000000, 0xffff0002 },
8547                 { RCVDBDI_STD_BD+0xc, 0x0000,
8548                         0x00000000, 0xffffffff },
8549
8550                 /* Receive BD Initiator Control Registers. */
8551                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8552                         0x00000000, 0xffffffff },
8553                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8554                         0x00000000, 0x000003ff },
8555                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8556                         0x00000000, 0xffffffff },
8557
8558                 /* Host Coalescing Control Registers. */
8559                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8560                         0x00000000, 0x00000004 },
8561                 { HOSTCC_MODE, TG3_FL_5705,
8562                         0x00000000, 0x000000f6 },
8563                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8564                         0x00000000, 0xffffffff },
8565                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8566                         0x00000000, 0x000003ff },
8567                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8568                         0x00000000, 0xffffffff },
8569                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8570                         0x00000000, 0x000003ff },
8571                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8572                         0x00000000, 0xffffffff },
8573                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8574                         0x00000000, 0x000000ff },
8575                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8576                         0x00000000, 0xffffffff },
8577                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8578                         0x00000000, 0x000000ff },
8579                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8580                         0x00000000, 0xffffffff },
8581                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8582                         0x00000000, 0xffffffff },
8583                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8584                         0x00000000, 0xffffffff },
8585                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8586                         0x00000000, 0x000000ff },
8587                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8588                         0x00000000, 0xffffffff },
8589                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8590                         0x00000000, 0x000000ff },
8591                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8592                         0x00000000, 0xffffffff },
8593                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8594                         0x00000000, 0xffffffff },
8595                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8596                         0x00000000, 0xffffffff },
8597                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8598                         0x00000000, 0xffffffff },
8599                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8600                         0x00000000, 0xffffffff },
8601                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8602                         0xffffffff, 0x00000000 },
8603                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8604                         0xffffffff, 0x00000000 },
8605
8606                 /* Buffer Manager Control Registers. */
8607                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8608                         0x00000000, 0x007fff80 },
8609                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8610                         0x00000000, 0x007fffff },
8611                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8612                         0x00000000, 0x0000003f },
8613                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8614                         0x00000000, 0x000001ff },
8615                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8616                         0x00000000, 0x000001ff },
8617                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8618                         0xffffffff, 0x00000000 },
8619                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8620                         0xffffffff, 0x00000000 },
8621
8622                 /* Mailbox Registers */
8623                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8624                         0x00000000, 0x000001ff },
8625                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8626                         0x00000000, 0x000001ff },
8627                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8628                         0x00000000, 0x000007ff },
8629                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8630                         0x00000000, 0x000001ff },
8631
8632                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8633         };
8634
8635         is_5705 = is_5750 = 0;
8636         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8637                 is_5705 = 1;
8638                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8639                         is_5750 = 1;
8640         }
8641
8642         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8643                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8644                         continue;
8645
8646                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8647                         continue;
8648
8649                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8650                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8651                         continue;
8652
8653                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8654                         continue;
8655
8656                 offset = (u32) reg_tbl[i].offset;
8657                 read_mask = reg_tbl[i].read_mask;
8658                 write_mask = reg_tbl[i].write_mask;
8659
8660                 /* Save the original register content */
8661                 save_val = tr32(offset);
8662
8663                 /* Determine the read-only value. */
8664                 read_val = save_val & read_mask;
8665
8666                 /* Write zero to the register, then make sure the read-only bits
8667                  * are not changed and the read/write bits are all zeros.
8668                  */
8669                 tw32(offset, 0);
8670
8671                 val = tr32(offset);
8672
8673                 /* Test the read-only and read/write bits. */
8674                 if (((val & read_mask) != read_val) || (val & write_mask))
8675                         goto out;
8676
8677                 /* Write ones to all the bits defined by RdMask and WrMask, then
8678                  * make sure the read-only bits are not changed and the
8679                  * read/write bits are all ones.
8680                  */
8681                 tw32(offset, read_mask | write_mask);
8682
8683                 val = tr32(offset);
8684
8685                 /* Test the read-only bits. */
8686                 if ((val & read_mask) != read_val)
8687                         goto out;
8688
8689                 /* Test the read/write bits. */
8690                 if ((val & write_mask) != write_mask)
8691                         goto out;
8692
8693                 tw32(offset, save_val);
8694         }
8695
8696         return 0;
8697
8698 out:
8699         if (netif_msg_hw(tp))
8700                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8701                        offset);
8702         tw32(offset, save_val);
8703         return -EIO;
8704 }
8705
8706 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8707 {
8708         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8709         int i;
8710         u32 j;
8711
8712         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8713                 for (j = 0; j < len; j += 4) {
8714                         u32 val;
8715
8716                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8717                         tg3_read_mem(tp, offset + j, &val);
8718                         if (val != test_pattern[i])
8719                                 return -EIO;
8720                 }
8721         }
8722         return 0;
8723 }
8724
8725 static int tg3_test_memory(struct tg3 *tp)
8726 {
8727         static struct mem_entry {
8728                 u32 offset;
8729                 u32 len;
8730         } mem_tbl_570x[] = {
8731                 { 0x00000000, 0x00b50},
8732                 { 0x00002000, 0x1c000},
8733                 { 0xffffffff, 0x00000}
8734         }, mem_tbl_5705[] = {
8735                 { 0x00000100, 0x0000c},
8736                 { 0x00000200, 0x00008},
8737                 { 0x00004000, 0x00800},
8738                 { 0x00006000, 0x01000},
8739                 { 0x00008000, 0x02000},
8740                 { 0x00010000, 0x0e000},
8741                 { 0xffffffff, 0x00000}
8742         }, mem_tbl_5755[] = {
8743                 { 0x00000200, 0x00008},
8744                 { 0x00004000, 0x00800},
8745                 { 0x00006000, 0x00800},
8746                 { 0x00008000, 0x02000},
8747                 { 0x00010000, 0x0c000},
8748                 { 0xffffffff, 0x00000}
8749         }, mem_tbl_5906[] = {
8750                 { 0x00000200, 0x00008},
8751                 { 0x00004000, 0x00400},
8752                 { 0x00006000, 0x00400},
8753                 { 0x00008000, 0x01000},
8754                 { 0x00010000, 0x01000},
8755                 { 0xffffffff, 0x00000}
8756         };
8757         struct mem_entry *mem_tbl;
8758         int err = 0;
8759         int i;
8760
8761         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8762                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8763                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8764                         mem_tbl = mem_tbl_5755;
8765                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8766                         mem_tbl = mem_tbl_5906;
8767                 else
8768                         mem_tbl = mem_tbl_5705;
8769         } else
8770                 mem_tbl = mem_tbl_570x;
8771
8772         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8773                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8774                     mem_tbl[i].len)) != 0)
8775                         break;
8776         }
8777
8778         return err;
8779 }
8780
8781 #define TG3_MAC_LOOPBACK        0
8782 #define TG3_PHY_LOOPBACK        1
8783
8784 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8785 {
8786         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8787         u32 desc_idx;
8788         struct sk_buff *skb, *rx_skb;
8789         u8 *tx_data;
8790         dma_addr_t map;
8791         int num_pkts, tx_len, rx_len, i, err;
8792         struct tg3_rx_buffer_desc *desc;
8793
8794         if (loopback_mode == TG3_MAC_LOOPBACK) {
8795                 /* HW errata - mac loopback fails in some cases on 5780.
8796                  * Normal traffic and PHY loopback are not affected by
8797                  * errata.
8798                  */
8799                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8800                         return 0;
8801
8802                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8803                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8804                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8805                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8806                 else
8807                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8808                 tw32(MAC_MODE, mac_mode);
8809         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8810                 u32 val;
8811
8812                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8813                         u32 phytest;
8814
8815                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8816                                 u32 phy;
8817
8818                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8819                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8820                                 if (!tg3_readphy(tp, 0x1b, &phy))
8821                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8822                                 if (!tg3_readphy(tp, 0x10, &phy))
8823                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8824                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8825                         }
8826                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8827                 } else
8828                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8829
8830                 tg3_writephy(tp, MII_BMCR, val);
8831                 udelay(40);
8832
8833                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8834                            MAC_MODE_LINK_POLARITY;
8835                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8836                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8837                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8838                 } else
8839                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8840
8841                 /* reset to prevent losing 1st rx packet intermittently */
8842                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8843                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8844                         udelay(10);
8845                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8846                 }
8847                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8848                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8849                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8850                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8851                 }
8852                 tw32(MAC_MODE, mac_mode);
8853         }
8854         else
8855                 return -EINVAL;
8856
8857         err = -EIO;
8858
8859         tx_len = 1514;
8860         skb = netdev_alloc_skb(tp->dev, tx_len);
8861         if (!skb)
8862                 return -ENOMEM;
8863
8864         tx_data = skb_put(skb, tx_len);
8865         memcpy(tx_data, tp->dev->dev_addr, 6);
8866         memset(tx_data + 6, 0x0, 8);
8867
8868         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8869
8870         for (i = 14; i < tx_len; i++)
8871                 tx_data[i] = (u8) (i & 0xff);
8872
8873         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8874
8875         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8876              HOSTCC_MODE_NOW);
8877
8878         udelay(10);
8879
8880         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8881
8882         num_pkts = 0;
8883
8884         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8885
8886         tp->tx_prod++;
8887         num_pkts++;
8888
8889         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8890                      tp->tx_prod);
8891         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8892
8893         udelay(10);
8894
8895         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8896         for (i = 0; i < 25; i++) {
8897                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8898                        HOSTCC_MODE_NOW);
8899
8900                 udelay(10);
8901
8902                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8903                 rx_idx = tp->hw_status->idx[0].rx_producer;
8904                 if ((tx_idx == tp->tx_prod) &&
8905                     (rx_idx == (rx_start_idx + num_pkts)))
8906                         break;
8907         }
8908
8909         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8910         dev_kfree_skb(skb);
8911
8912         if (tx_idx != tp->tx_prod)
8913                 goto out;
8914
8915         if (rx_idx != rx_start_idx + num_pkts)
8916                 goto out;
8917
8918         desc = &tp->rx_rcb[rx_start_idx];
8919         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8920         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8921         if (opaque_key != RXD_OPAQUE_RING_STD)
8922                 goto out;
8923
8924         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8925             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8926                 goto out;
8927
8928         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8929         if (rx_len != tx_len)
8930                 goto out;
8931
8932         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8933
8934         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8935         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8936
8937         for (i = 14; i < tx_len; i++) {
8938                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8939                         goto out;
8940         }
8941         err = 0;
8942
8943         /* tg3_free_rings will unmap and free the rx_skb */
8944 out:
8945         return err;
8946 }
8947
8948 #define TG3_MAC_LOOPBACK_FAILED         1
8949 #define TG3_PHY_LOOPBACK_FAILED         2
8950 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8951                                          TG3_PHY_LOOPBACK_FAILED)
8952
8953 static int tg3_test_loopback(struct tg3 *tp)
8954 {
8955         int err = 0;
8956
8957         if (!netif_running(tp->dev))
8958                 return TG3_LOOPBACK_FAILED;
8959
8960         err = tg3_reset_hw(tp, 1);
8961         if (err)
8962                 return TG3_LOOPBACK_FAILED;
8963
8964         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8965                 err |= TG3_MAC_LOOPBACK_FAILED;
8966         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8967                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8968                         err |= TG3_PHY_LOOPBACK_FAILED;
8969         }
8970
8971         return err;
8972 }
8973
8974 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8975                           u64 *data)
8976 {
8977         struct tg3 *tp = netdev_priv(dev);
8978
8979         if (tp->link_config.phy_is_low_power)
8980                 tg3_set_power_state(tp, PCI_D0);
8981
8982         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8983
8984         if (tg3_test_nvram(tp) != 0) {
8985                 etest->flags |= ETH_TEST_FL_FAILED;
8986                 data[0] = 1;
8987         }
8988         if (tg3_test_link(tp) != 0) {
8989                 etest->flags |= ETH_TEST_FL_FAILED;
8990                 data[1] = 1;
8991         }
8992         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8993                 int err, irq_sync = 0;
8994
8995                 if (netif_running(dev)) {
8996                         tg3_netif_stop(tp);
8997                         irq_sync = 1;
8998                 }
8999
9000                 tg3_full_lock(tp, irq_sync);
9001
9002                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9003                 err = tg3_nvram_lock(tp);
9004                 tg3_halt_cpu(tp, RX_CPU_BASE);
9005                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9006                         tg3_halt_cpu(tp, TX_CPU_BASE);
9007                 if (!err)
9008                         tg3_nvram_unlock(tp);
9009
9010                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9011                         tg3_phy_reset(tp);
9012
9013                 if (tg3_test_registers(tp) != 0) {
9014                         etest->flags |= ETH_TEST_FL_FAILED;
9015                         data[2] = 1;
9016                 }
9017                 if (tg3_test_memory(tp) != 0) {
9018                         etest->flags |= ETH_TEST_FL_FAILED;
9019                         data[3] = 1;
9020                 }
9021                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9022                         etest->flags |= ETH_TEST_FL_FAILED;
9023
9024                 tg3_full_unlock(tp);
9025
9026                 if (tg3_test_interrupt(tp) != 0) {
9027                         etest->flags |= ETH_TEST_FL_FAILED;
9028                         data[5] = 1;
9029                 }
9030
9031                 tg3_full_lock(tp, 0);
9032
9033                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9034                 if (netif_running(dev)) {
9035                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9036                         if (!tg3_restart_hw(tp, 1))
9037                                 tg3_netif_start(tp);
9038                 }
9039
9040                 tg3_full_unlock(tp);
9041         }
9042         if (tp->link_config.phy_is_low_power)
9043                 tg3_set_power_state(tp, PCI_D3hot);
9044
9045 }
9046
9047 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9048 {
9049         struct mii_ioctl_data *data = if_mii(ifr);
9050         struct tg3 *tp = netdev_priv(dev);
9051         int err;
9052
9053         switch(cmd) {
9054         case SIOCGMIIPHY:
9055                 data->phy_id = PHY_ADDR;
9056
9057                 /* fallthru */
9058         case SIOCGMIIREG: {
9059                 u32 mii_regval;
9060
9061                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9062                         break;                  /* We have no PHY */
9063
9064                 if (tp->link_config.phy_is_low_power)
9065                         return -EAGAIN;
9066
9067                 spin_lock_bh(&tp->lock);
9068                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9069                 spin_unlock_bh(&tp->lock);
9070
9071                 data->val_out = mii_regval;
9072
9073                 return err;
9074         }
9075
9076         case SIOCSMIIREG:
9077                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9078                         break;                  /* We have no PHY */
9079
9080                 if (!capable(CAP_NET_ADMIN))
9081                         return -EPERM;
9082
9083                 if (tp->link_config.phy_is_low_power)
9084                         return -EAGAIN;
9085
9086                 spin_lock_bh(&tp->lock);
9087                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9088                 spin_unlock_bh(&tp->lock);
9089
9090                 return err;
9091
9092         default:
9093                 /* do nothing */
9094                 break;
9095         }
9096         return -EOPNOTSUPP;
9097 }
9098
9099 #if TG3_VLAN_TAG_USED
9100 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9101 {
9102         struct tg3 *tp = netdev_priv(dev);
9103
9104         if (netif_running(dev))
9105                 tg3_netif_stop(tp);
9106
9107         tg3_full_lock(tp, 0);
9108
9109         tp->vlgrp = grp;
9110
9111         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9112         __tg3_set_rx_mode(dev);
9113
9114         tg3_full_unlock(tp);
9115
9116         if (netif_running(dev))
9117                 tg3_netif_start(tp);
9118 }
9119
9120 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9121 {
9122         struct tg3 *tp = netdev_priv(dev);
9123
9124         if (netif_running(dev))
9125                 tg3_netif_stop(tp);
9126
9127         tg3_full_lock(tp, 0);
9128         vlan_group_set_device(tp->vlgrp, vid, NULL);
9129         tg3_full_unlock(tp);
9130
9131         if (netif_running(dev))
9132                 tg3_netif_start(tp);
9133 }
9134 #endif
9135
9136 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9137 {
9138         struct tg3 *tp = netdev_priv(dev);
9139
9140         memcpy(ec, &tp->coal, sizeof(*ec));
9141         return 0;
9142 }
9143
9144 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9145 {
9146         struct tg3 *tp = netdev_priv(dev);
9147         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9148         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9149
9150         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9151                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9152                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9153                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9154                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9155         }
9156
9157         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9158             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9159             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9160             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9161             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9162             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9163             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9164             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9165             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9166             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9167                 return -EINVAL;
9168
9169         /* No rx interrupts will be generated if both are zero */
9170         if ((ec->rx_coalesce_usecs == 0) &&
9171             (ec->rx_max_coalesced_frames == 0))
9172                 return -EINVAL;
9173
9174         /* No tx interrupts will be generated if both are zero */
9175         if ((ec->tx_coalesce_usecs == 0) &&
9176             (ec->tx_max_coalesced_frames == 0))
9177                 return -EINVAL;
9178
9179         /* Only copy relevant parameters, ignore all others. */
9180         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9181         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9182         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9183         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9184         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9185         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9186         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9187         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9188         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9189
9190         if (netif_running(dev)) {
9191                 tg3_full_lock(tp, 0);
9192                 __tg3_set_coalesce(tp, &tp->coal);
9193                 tg3_full_unlock(tp);
9194         }
9195         return 0;
9196 }
9197
9198 static const struct ethtool_ops tg3_ethtool_ops = {
9199         .get_settings           = tg3_get_settings,
9200         .set_settings           = tg3_set_settings,
9201         .get_drvinfo            = tg3_get_drvinfo,
9202         .get_regs_len           = tg3_get_regs_len,
9203         .get_regs               = tg3_get_regs,
9204         .get_wol                = tg3_get_wol,
9205         .set_wol                = tg3_set_wol,
9206         .get_msglevel           = tg3_get_msglevel,
9207         .set_msglevel           = tg3_set_msglevel,
9208         .nway_reset             = tg3_nway_reset,
9209         .get_link               = ethtool_op_get_link,
9210         .get_eeprom_len         = tg3_get_eeprom_len,
9211         .get_eeprom             = tg3_get_eeprom,
9212         .set_eeprom             = tg3_set_eeprom,
9213         .get_ringparam          = tg3_get_ringparam,
9214         .set_ringparam          = tg3_set_ringparam,
9215         .get_pauseparam         = tg3_get_pauseparam,
9216         .set_pauseparam         = tg3_set_pauseparam,
9217         .get_rx_csum            = tg3_get_rx_csum,
9218         .set_rx_csum            = tg3_set_rx_csum,
9219         .get_tx_csum            = ethtool_op_get_tx_csum,
9220         .set_tx_csum            = tg3_set_tx_csum,
9221         .get_sg                 = ethtool_op_get_sg,
9222         .set_sg                 = ethtool_op_set_sg,
9223         .get_tso                = ethtool_op_get_tso,
9224         .set_tso                = tg3_set_tso,
9225         .self_test_count        = tg3_get_test_count,
9226         .self_test              = tg3_self_test,
9227         .get_strings            = tg3_get_strings,
9228         .phys_id                = tg3_phys_id,
9229         .get_stats_count        = tg3_get_stats_count,
9230         .get_ethtool_stats      = tg3_get_ethtool_stats,
9231         .get_coalesce           = tg3_get_coalesce,
9232         .set_coalesce           = tg3_set_coalesce,
9233         .get_perm_addr          = ethtool_op_get_perm_addr,
9234 };
9235
9236 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9237 {
9238         u32 cursize, val, magic;
9239
9240         tp->nvram_size = EEPROM_CHIP_SIZE;
9241
9242         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9243                 return;
9244
9245         if ((magic != TG3_EEPROM_MAGIC) &&
9246             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9247             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9248                 return;
9249
9250         /*
9251          * Size the chip by reading offsets at increasing powers of two.
9252          * When we encounter our validation signature, we know the addressing
9253          * has wrapped around, and thus have our chip size.
9254          */
9255         cursize = 0x10;
9256
9257         while (cursize < tp->nvram_size) {
9258                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9259                         return;
9260
9261                 if (val == magic)
9262                         break;
9263
9264                 cursize <<= 1;
9265         }
9266
9267         tp->nvram_size = cursize;
9268 }
9269
9270 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9271 {
9272         u32 val;
9273
9274         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9275                 return;
9276
9277         /* Selfboot format */
9278         if (val != TG3_EEPROM_MAGIC) {
9279                 tg3_get_eeprom_size(tp);
9280                 return;
9281         }
9282
9283         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9284                 if (val != 0) {
9285                         tp->nvram_size = (val >> 16) * 1024;
9286                         return;
9287                 }
9288         }
9289         tp->nvram_size = 0x80000;
9290 }
9291
9292 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9293 {
9294         u32 nvcfg1;
9295
9296         nvcfg1 = tr32(NVRAM_CFG1);
9297         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9298                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9299         }
9300         else {
9301                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9302                 tw32(NVRAM_CFG1, nvcfg1);
9303         }
9304
9305         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9306             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9307                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9308                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9309                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9310                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9311                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9312                                 break;
9313                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9314                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9315                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9316                                 break;
9317                         case FLASH_VENDOR_ATMEL_EEPROM:
9318                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9319                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9320                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9321                                 break;
9322                         case FLASH_VENDOR_ST:
9323                                 tp->nvram_jedecnum = JEDEC_ST;
9324                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9325                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9326                                 break;
9327                         case FLASH_VENDOR_SAIFUN:
9328                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9329                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9330                                 break;
9331                         case FLASH_VENDOR_SST_SMALL:
9332                         case FLASH_VENDOR_SST_LARGE:
9333                                 tp->nvram_jedecnum = JEDEC_SST;
9334                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9335                                 break;
9336                 }
9337         }
9338         else {
9339                 tp->nvram_jedecnum = JEDEC_ATMEL;
9340                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9341                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9342         }
9343 }
9344
9345 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9346 {
9347         u32 nvcfg1;
9348
9349         nvcfg1 = tr32(NVRAM_CFG1);
9350
9351         /* NVRAM protection for TPM */
9352         if (nvcfg1 & (1 << 27))
9353                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9354
9355         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9356                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9357                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9358                         tp->nvram_jedecnum = JEDEC_ATMEL;
9359                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9360                         break;
9361                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9362                         tp->nvram_jedecnum = JEDEC_ATMEL;
9363                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9364                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9365                         break;
9366                 case FLASH_5752VENDOR_ST_M45PE10:
9367                 case FLASH_5752VENDOR_ST_M45PE20:
9368                 case FLASH_5752VENDOR_ST_M45PE40:
9369                         tp->nvram_jedecnum = JEDEC_ST;
9370                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9371                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9372                         break;
9373         }
9374
9375         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9376                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9377                         case FLASH_5752PAGE_SIZE_256:
9378                                 tp->nvram_pagesize = 256;
9379                                 break;
9380                         case FLASH_5752PAGE_SIZE_512:
9381                                 tp->nvram_pagesize = 512;
9382                                 break;
9383                         case FLASH_5752PAGE_SIZE_1K:
9384                                 tp->nvram_pagesize = 1024;
9385                                 break;
9386                         case FLASH_5752PAGE_SIZE_2K:
9387                                 tp->nvram_pagesize = 2048;
9388                                 break;
9389                         case FLASH_5752PAGE_SIZE_4K:
9390                                 tp->nvram_pagesize = 4096;
9391                                 break;
9392                         case FLASH_5752PAGE_SIZE_264:
9393                                 tp->nvram_pagesize = 264;
9394                                 break;
9395                 }
9396         }
9397         else {
9398                 /* For eeprom, set pagesize to maximum eeprom size */
9399                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9400
9401                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9402                 tw32(NVRAM_CFG1, nvcfg1);
9403         }
9404 }
9405
9406 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9407 {
9408         u32 nvcfg1, protect = 0;
9409
9410         nvcfg1 = tr32(NVRAM_CFG1);
9411
9412         /* NVRAM protection for TPM */
9413         if (nvcfg1 & (1 << 27)) {
9414                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9415                 protect = 1;
9416         }
9417
9418         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9419         switch (nvcfg1) {
9420                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9421                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9422                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9423                         tp->nvram_jedecnum = JEDEC_ATMEL;
9424                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9425                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9426                         tp->nvram_pagesize = 264;
9427                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9428                                 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9429                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9430                                 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9431                         else
9432                                 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9433                         break;
9434                 case FLASH_5752VENDOR_ST_M45PE10:
9435                 case FLASH_5752VENDOR_ST_M45PE20:
9436                 case FLASH_5752VENDOR_ST_M45PE40:
9437                         tp->nvram_jedecnum = JEDEC_ST;
9438                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9439                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9440                         tp->nvram_pagesize = 256;
9441                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9442                                 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9443                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9444                                 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9445                         else
9446                                 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9447                         break;
9448         }
9449 }
9450
9451 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9452 {
9453         u32 nvcfg1;
9454
9455         nvcfg1 = tr32(NVRAM_CFG1);
9456
9457         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9458                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9459                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9460                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9461                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9462                         tp->nvram_jedecnum = JEDEC_ATMEL;
9463                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9464                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9465
9466                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9467                         tw32(NVRAM_CFG1, nvcfg1);
9468                         break;
9469                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9470                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9471                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9472                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9473                         tp->nvram_jedecnum = JEDEC_ATMEL;
9474                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9475                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9476                         tp->nvram_pagesize = 264;
9477                         break;
9478                 case FLASH_5752VENDOR_ST_M45PE10:
9479                 case FLASH_5752VENDOR_ST_M45PE20:
9480                 case FLASH_5752VENDOR_ST_M45PE40:
9481                         tp->nvram_jedecnum = JEDEC_ST;
9482                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9483                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9484                         tp->nvram_pagesize = 256;
9485                         break;
9486         }
9487 }
9488
9489 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9490 {
9491         tp->nvram_jedecnum = JEDEC_ATMEL;
9492         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9493         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9494 }
9495
9496 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9497 static void __devinit tg3_nvram_init(struct tg3 *tp)
9498 {
9499         tw32_f(GRC_EEPROM_ADDR,
9500              (EEPROM_ADDR_FSM_RESET |
9501               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9502                EEPROM_ADDR_CLKPERD_SHIFT)));
9503
9504         msleep(1);
9505
9506         /* Enable seeprom accesses. */
9507         tw32_f(GRC_LOCAL_CTRL,
9508              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9509         udelay(100);
9510
9511         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9512             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9513                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9514
9515                 if (tg3_nvram_lock(tp)) {
9516                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9517                                "tg3_nvram_init failed.\n", tp->dev->name);
9518                         return;
9519                 }
9520                 tg3_enable_nvram_access(tp);
9521
9522                 tp->nvram_size = 0;
9523
9524                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9525                         tg3_get_5752_nvram_info(tp);
9526                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9527                         tg3_get_5755_nvram_info(tp);
9528                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9529                         tg3_get_5787_nvram_info(tp);
9530                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9531                         tg3_get_5906_nvram_info(tp);
9532                 else
9533                         tg3_get_nvram_info(tp);
9534
9535                 if (tp->nvram_size == 0)
9536                         tg3_get_nvram_size(tp);
9537
9538                 tg3_disable_nvram_access(tp);
9539                 tg3_nvram_unlock(tp);
9540
9541         } else {
9542                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9543
9544                 tg3_get_eeprom_size(tp);
9545         }
9546 }
9547
9548 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9549                                         u32 offset, u32 *val)
9550 {
9551         u32 tmp;
9552         int i;
9553
9554         if (offset > EEPROM_ADDR_ADDR_MASK ||
9555             (offset % 4) != 0)
9556                 return -EINVAL;
9557
9558         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9559                                         EEPROM_ADDR_DEVID_MASK |
9560                                         EEPROM_ADDR_READ);
9561         tw32(GRC_EEPROM_ADDR,
9562              tmp |
9563              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9564              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9565               EEPROM_ADDR_ADDR_MASK) |
9566              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9567
9568         for (i = 0; i < 1000; i++) {
9569                 tmp = tr32(GRC_EEPROM_ADDR);
9570
9571                 if (tmp & EEPROM_ADDR_COMPLETE)
9572                         break;
9573                 msleep(1);
9574         }
9575         if (!(tmp & EEPROM_ADDR_COMPLETE))
9576                 return -EBUSY;
9577
9578         *val = tr32(GRC_EEPROM_DATA);
9579         return 0;
9580 }
9581
9582 #define NVRAM_CMD_TIMEOUT 10000
9583
9584 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9585 {
9586         int i;
9587
9588         tw32(NVRAM_CMD, nvram_cmd);
9589         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9590                 udelay(10);
9591                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9592                         udelay(10);
9593                         break;
9594                 }
9595         }
9596         if (i == NVRAM_CMD_TIMEOUT) {
9597                 return -EBUSY;
9598         }
9599         return 0;
9600 }
9601
9602 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9603 {
9604         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9605             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9606             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9607             (tp->nvram_jedecnum == JEDEC_ATMEL))
9608
9609                 addr = ((addr / tp->nvram_pagesize) <<
9610                         ATMEL_AT45DB0X1B_PAGE_POS) +
9611                        (addr % tp->nvram_pagesize);
9612
9613         return addr;
9614 }
9615
9616 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9617 {
9618         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9619             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9620             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9621             (tp->nvram_jedecnum == JEDEC_ATMEL))
9622
9623                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9624                         tp->nvram_pagesize) +
9625                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9626
9627         return addr;
9628 }
9629
9630 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9631 {
9632         int ret;
9633
9634         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9635                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9636
9637         offset = tg3_nvram_phys_addr(tp, offset);
9638
9639         if (offset > NVRAM_ADDR_MSK)
9640                 return -EINVAL;
9641
9642         ret = tg3_nvram_lock(tp);
9643         if (ret)
9644                 return ret;
9645
9646         tg3_enable_nvram_access(tp);
9647
9648         tw32(NVRAM_ADDR, offset);
9649         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9650                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9651
9652         if (ret == 0)
9653                 *val = swab32(tr32(NVRAM_RDDATA));
9654
9655         tg3_disable_nvram_access(tp);
9656
9657         tg3_nvram_unlock(tp);
9658
9659         return ret;
9660 }
9661
9662 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9663 {
9664         int err;
9665         u32 tmp;
9666
9667         err = tg3_nvram_read(tp, offset, &tmp);
9668         *val = swab32(tmp);
9669         return err;
9670 }
9671
9672 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9673                                     u32 offset, u32 len, u8 *buf)
9674 {
9675         int i, j, rc = 0;
9676         u32 val;
9677
9678         for (i = 0; i < len; i += 4) {
9679                 u32 addr, data;
9680
9681                 addr = offset + i;
9682
9683                 memcpy(&data, buf + i, 4);
9684
9685                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9686
9687                 val = tr32(GRC_EEPROM_ADDR);
9688                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9689
9690                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9691                         EEPROM_ADDR_READ);
9692                 tw32(GRC_EEPROM_ADDR, val |
9693                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9694                         (addr & EEPROM_ADDR_ADDR_MASK) |
9695                         EEPROM_ADDR_START |
9696                         EEPROM_ADDR_WRITE);
9697
9698                 for (j = 0; j < 1000; j++) {
9699                         val = tr32(GRC_EEPROM_ADDR);
9700
9701                         if (val & EEPROM_ADDR_COMPLETE)
9702                                 break;
9703                         msleep(1);
9704                 }
9705                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9706                         rc = -EBUSY;
9707                         break;
9708                 }
9709         }
9710
9711         return rc;
9712 }
9713
9714 /* offset and length are dword aligned */
9715 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9716                 u8 *buf)
9717 {
9718         int ret = 0;
9719         u32 pagesize = tp->nvram_pagesize;
9720         u32 pagemask = pagesize - 1;
9721         u32 nvram_cmd;
9722         u8 *tmp;
9723
9724         tmp = kmalloc(pagesize, GFP_KERNEL);
9725         if (tmp == NULL)
9726                 return -ENOMEM;
9727
9728         while (len) {
9729                 int j;
9730                 u32 phy_addr, page_off, size;
9731
9732                 phy_addr = offset & ~pagemask;
9733
9734                 for (j = 0; j < pagesize; j += 4) {
9735                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9736                                                 (u32 *) (tmp + j))))
9737                                 break;
9738                 }
9739                 if (ret)
9740                         break;
9741
9742                 page_off = offset & pagemask;
9743                 size = pagesize;
9744                 if (len < size)
9745                         size = len;
9746
9747                 len -= size;
9748
9749                 memcpy(tmp + page_off, buf, size);
9750
9751                 offset = offset + (pagesize - page_off);
9752
9753                 tg3_enable_nvram_access(tp);
9754
9755                 /*
9756                  * Before we can erase the flash page, we need
9757                  * to issue a special "write enable" command.
9758                  */
9759                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9760
9761                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9762                         break;
9763
9764                 /* Erase the target page */
9765                 tw32(NVRAM_ADDR, phy_addr);
9766
9767                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9768                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9769
9770                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9771                         break;
9772
9773                 /* Issue another write enable to start the write. */
9774                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9775
9776                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9777                         break;
9778
9779                 for (j = 0; j < pagesize; j += 4) {
9780                         u32 data;
9781
9782                         data = *((u32 *) (tmp + j));
9783                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9784
9785                         tw32(NVRAM_ADDR, phy_addr + j);
9786
9787                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9788                                 NVRAM_CMD_WR;
9789
9790                         if (j == 0)
9791                                 nvram_cmd |= NVRAM_CMD_FIRST;
9792                         else if (j == (pagesize - 4))
9793                                 nvram_cmd |= NVRAM_CMD_LAST;
9794
9795                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9796                                 break;
9797                 }
9798                 if (ret)
9799                         break;
9800         }
9801
9802         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9803         tg3_nvram_exec_cmd(tp, nvram_cmd);
9804
9805         kfree(tmp);
9806
9807         return ret;
9808 }
9809
9810 /* offset and length are dword aligned */
9811 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9812                 u8 *buf)
9813 {
9814         int i, ret = 0;
9815
9816         for (i = 0; i < len; i += 4, offset += 4) {
9817                 u32 data, page_off, phy_addr, nvram_cmd;
9818
9819                 memcpy(&data, buf + i, 4);
9820                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9821
9822                 page_off = offset % tp->nvram_pagesize;
9823
9824                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9825
9826                 tw32(NVRAM_ADDR, phy_addr);
9827
9828                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9829
9830                 if ((page_off == 0) || (i == 0))
9831                         nvram_cmd |= NVRAM_CMD_FIRST;
9832                 if (page_off == (tp->nvram_pagesize - 4))
9833                         nvram_cmd |= NVRAM_CMD_LAST;
9834
9835                 if (i == (len - 4))
9836                         nvram_cmd |= NVRAM_CMD_LAST;
9837
9838                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9839                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9840                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9841                     (tp->nvram_jedecnum == JEDEC_ST) &&
9842                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9843
9844                         if ((ret = tg3_nvram_exec_cmd(tp,
9845                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9846                                 NVRAM_CMD_DONE)))
9847
9848                                 break;
9849                 }
9850                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9851                         /* We always do complete word writes to eeprom. */
9852                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9853                 }
9854
9855                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9856                         break;
9857         }
9858         return ret;
9859 }
9860
9861 /* offset and length are dword aligned */
9862 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9863 {
9864         int ret;
9865
9866         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9867                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9868                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9869                 udelay(40);
9870         }
9871
9872         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9873                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9874         }
9875         else {
9876                 u32 grc_mode;
9877
9878                 ret = tg3_nvram_lock(tp);
9879                 if (ret)
9880                         return ret;
9881
9882                 tg3_enable_nvram_access(tp);
9883                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9884                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9885                         tw32(NVRAM_WRITE1, 0x406);
9886
9887                 grc_mode = tr32(GRC_MODE);
9888                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9889
9890                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9891                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9892
9893                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9894                                 buf);
9895                 }
9896                 else {
9897                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9898                                 buf);
9899                 }
9900
9901                 grc_mode = tr32(GRC_MODE);
9902                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9903
9904                 tg3_disable_nvram_access(tp);
9905                 tg3_nvram_unlock(tp);
9906         }
9907
9908         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9909                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9910                 udelay(40);
9911         }
9912
9913         return ret;
9914 }
9915
9916 struct subsys_tbl_ent {
9917         u16 subsys_vendor, subsys_devid;
9918         u32 phy_id;
9919 };
9920
9921 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9922         /* Broadcom boards. */
9923         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9924         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9925         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9926         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9927         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9928         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9929         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9930         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9931         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9932         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9933         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9934
9935         /* 3com boards. */
9936         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9937         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9938         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9939         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9940         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9941
9942         /* DELL boards. */
9943         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9944         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9945         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9946         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9947
9948         /* Compaq boards. */
9949         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9950         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9951         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9952         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9953         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9954
9955         /* IBM boards. */
9956         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9957 };
9958
9959 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9960 {
9961         int i;
9962
9963         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9964                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9965                      tp->pdev->subsystem_vendor) &&
9966                     (subsys_id_to_phy_id[i].subsys_devid ==
9967                      tp->pdev->subsystem_device))
9968                         return &subsys_id_to_phy_id[i];
9969         }
9970         return NULL;
9971 }
9972
9973 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9974 {
9975         u32 val;
9976         u16 pmcsr;
9977
9978         /* On some early chips the SRAM cannot be accessed in D3hot state,
9979          * so need make sure we're in D0.
9980          */
9981         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9982         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9983         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9984         msleep(1);
9985
9986         /* Make sure register accesses (indirect or otherwise)
9987          * will function correctly.
9988          */
9989         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9990                                tp->misc_host_ctrl);
9991
9992         /* The memory arbiter has to be enabled in order for SRAM accesses
9993          * to succeed.  Normally on powerup the tg3 chip firmware will make
9994          * sure it is enabled, but other entities such as system netboot
9995          * code might disable it.
9996          */
9997         val = tr32(MEMARB_MODE);
9998         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9999
10000         tp->phy_id = PHY_ID_INVALID;
10001         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10002
10003         /* Assume an onboard device by default.  */
10004         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10005
10006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10007                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10008                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10009                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10010                 }
10011                 return;
10012         }
10013
10014         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10015         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10016                 u32 nic_cfg, led_cfg;
10017                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10018                 int eeprom_phy_serdes = 0;
10019
10020                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10021                 tp->nic_sram_data_cfg = nic_cfg;
10022
10023                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10024                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10025                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10026                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10027                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10028                     (ver > 0) && (ver < 0x100))
10029                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10030
10031                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10032                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10033                         eeprom_phy_serdes = 1;
10034
10035                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10036                 if (nic_phy_id != 0) {
10037                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10038                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10039
10040                         eeprom_phy_id  = (id1 >> 16) << 10;
10041                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10042                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10043                 } else
10044                         eeprom_phy_id = 0;
10045
10046                 tp->phy_id = eeprom_phy_id;
10047                 if (eeprom_phy_serdes) {
10048                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10049                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10050                         else
10051                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10052                 }
10053
10054                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10055                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10056                                     SHASTA_EXT_LED_MODE_MASK);
10057                 else
10058                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10059
10060                 switch (led_cfg) {
10061                 default:
10062                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10063                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10064                         break;
10065
10066                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10067                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10068                         break;
10069
10070                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10071                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10072
10073                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10074                          * read on some older 5700/5701 bootcode.
10075                          */
10076                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10077                             ASIC_REV_5700 ||
10078                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10079                             ASIC_REV_5701)
10080                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10081
10082                         break;
10083
10084                 case SHASTA_EXT_LED_SHARED:
10085                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10086                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10087                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10088                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10089                                                  LED_CTRL_MODE_PHY_2);
10090                         break;
10091
10092                 case SHASTA_EXT_LED_MAC:
10093                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10094                         break;
10095
10096                 case SHASTA_EXT_LED_COMBO:
10097                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10098                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10099                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10100                                                  LED_CTRL_MODE_PHY_2);
10101                         break;
10102
10103                 };
10104
10105                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10106                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10107                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10108                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10109
10110                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10111                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10112                         if ((tp->pdev->subsystem_vendor ==
10113                              PCI_VENDOR_ID_ARIMA) &&
10114                             (tp->pdev->subsystem_device == 0x205a ||
10115                              tp->pdev->subsystem_device == 0x2063))
10116                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10117                 } else {
10118                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10119                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10120                 }
10121
10122                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10123                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10124                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10125                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10126                 }
10127                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10128                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10129
10130                 if (cfg2 & (1 << 17))
10131                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10132
10133                 /* serdes signal pre-emphasis in register 0x590 set by */
10134                 /* bootcode if bit 18 is set */
10135                 if (cfg2 & (1 << 18))
10136                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10137         }
10138 }
10139
10140 static int __devinit tg3_phy_probe(struct tg3 *tp)
10141 {
10142         u32 hw_phy_id_1, hw_phy_id_2;
10143         u32 hw_phy_id, hw_phy_id_masked;
10144         int err;
10145
10146         /* Reading the PHY ID register can conflict with ASF
10147          * firwmare access to the PHY hardware.
10148          */
10149         err = 0;
10150         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10151                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10152         } else {
10153                 /* Now read the physical PHY_ID from the chip and verify
10154                  * that it is sane.  If it doesn't look good, we fall back
10155                  * to either the hard-coded table based PHY_ID and failing
10156                  * that the value found in the eeprom area.
10157                  */
10158                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10159                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10160
10161                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10162                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10163                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10164
10165                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10166         }
10167
10168         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10169                 tp->phy_id = hw_phy_id;
10170                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10171                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10172                 else
10173                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10174         } else {
10175                 if (tp->phy_id != PHY_ID_INVALID) {
10176                         /* Do nothing, phy ID already set up in
10177                          * tg3_get_eeprom_hw_cfg().
10178                          */
10179                 } else {
10180                         struct subsys_tbl_ent *p;
10181
10182                         /* No eeprom signature?  Try the hardcoded
10183                          * subsys device table.
10184                          */
10185                         p = lookup_by_subsys(tp);
10186                         if (!p)
10187                                 return -ENODEV;
10188
10189                         tp->phy_id = p->phy_id;
10190                         if (!tp->phy_id ||
10191                             tp->phy_id == PHY_ID_BCM8002)
10192                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10193                 }
10194         }
10195
10196         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10197             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10198                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10199
10200                 tg3_readphy(tp, MII_BMSR, &bmsr);
10201                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10202                     (bmsr & BMSR_LSTATUS))
10203                         goto skip_phy_reset;
10204
10205                 err = tg3_phy_reset(tp);
10206                 if (err)
10207                         return err;
10208
10209                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10210                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10211                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10212                 tg3_ctrl = 0;
10213                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10214                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10215                                     MII_TG3_CTRL_ADV_1000_FULL);
10216                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10217                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10218                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10219                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10220                 }
10221
10222                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10223                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10224                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10225                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10226                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10227
10228                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10229                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10230
10231                         tg3_writephy(tp, MII_BMCR,
10232                                      BMCR_ANENABLE | BMCR_ANRESTART);
10233                 }
10234                 tg3_phy_set_wirespeed(tp);
10235
10236                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10237                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10238                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10239         }
10240
10241 skip_phy_reset:
10242         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10243                 err = tg3_init_5401phy_dsp(tp);
10244                 if (err)
10245                         return err;
10246         }
10247
10248         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10249                 err = tg3_init_5401phy_dsp(tp);
10250         }
10251
10252         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10253                 tp->link_config.advertising =
10254                         (ADVERTISED_1000baseT_Half |
10255                          ADVERTISED_1000baseT_Full |
10256                          ADVERTISED_Autoneg |
10257                          ADVERTISED_FIBRE);
10258         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10259                 tp->link_config.advertising &=
10260                         ~(ADVERTISED_1000baseT_Half |
10261                           ADVERTISED_1000baseT_Full);
10262
10263         return err;
10264 }
10265
10266 static void __devinit tg3_read_partno(struct tg3 *tp)
10267 {
10268         unsigned char vpd_data[256];
10269         unsigned int i;
10270         u32 magic;
10271
10272         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10273                 goto out_not_found;
10274
10275         if (magic == TG3_EEPROM_MAGIC) {
10276                 for (i = 0; i < 256; i += 4) {
10277                         u32 tmp;
10278
10279                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10280                                 goto out_not_found;
10281
10282                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10283                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10284                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10285                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10286                 }
10287         } else {
10288                 int vpd_cap;
10289
10290                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10291                 for (i = 0; i < 256; i += 4) {
10292                         u32 tmp, j = 0;
10293                         u16 tmp16;
10294
10295                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10296                                               i);
10297                         while (j++ < 100) {
10298                                 pci_read_config_word(tp->pdev, vpd_cap +
10299                                                      PCI_VPD_ADDR, &tmp16);
10300                                 if (tmp16 & 0x8000)
10301                                         break;
10302                                 msleep(1);
10303                         }
10304                         if (!(tmp16 & 0x8000))
10305                                 goto out_not_found;
10306
10307                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10308                                               &tmp);
10309                         tmp = cpu_to_le32(tmp);
10310                         memcpy(&vpd_data[i], &tmp, 4);
10311                 }
10312         }
10313
10314         /* Now parse and find the part number. */
10315         for (i = 0; i < 254; ) {
10316                 unsigned char val = vpd_data[i];
10317                 unsigned int block_end;
10318
10319                 if (val == 0x82 || val == 0x91) {
10320                         i = (i + 3 +
10321                              (vpd_data[i + 1] +
10322                               (vpd_data[i + 2] << 8)));
10323                         continue;
10324                 }
10325
10326                 if (val != 0x90)
10327                         goto out_not_found;
10328
10329                 block_end = (i + 3 +
10330                              (vpd_data[i + 1] +
10331                               (vpd_data[i + 2] << 8)));
10332                 i += 3;
10333
10334                 if (block_end > 256)
10335                         goto out_not_found;
10336
10337                 while (i < (block_end - 2)) {
10338                         if (vpd_data[i + 0] == 'P' &&
10339                             vpd_data[i + 1] == 'N') {
10340                                 int partno_len = vpd_data[i + 2];
10341
10342                                 i += 3;
10343                                 if (partno_len > 24 || (partno_len + i) > 256)
10344                                         goto out_not_found;
10345
10346                                 memcpy(tp->board_part_number,
10347                                        &vpd_data[i], partno_len);
10348
10349                                 /* Success. */
10350                                 return;
10351                         }
10352                         i += 3 + vpd_data[i + 2];
10353                 }
10354
10355                 /* Part number not found. */
10356                 goto out_not_found;
10357         }
10358
10359 out_not_found:
10360         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10361                 strcpy(tp->board_part_number, "BCM95906");
10362         else
10363                 strcpy(tp->board_part_number, "none");
10364 }
10365
10366 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10367 {
10368         u32 val, offset, start;
10369
10370         if (tg3_nvram_read_swab(tp, 0, &val))
10371                 return;
10372
10373         if (val != TG3_EEPROM_MAGIC)
10374                 return;
10375
10376         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10377             tg3_nvram_read_swab(tp, 0x4, &start))
10378                 return;
10379
10380         offset = tg3_nvram_logical_addr(tp, offset);
10381         if (tg3_nvram_read_swab(tp, offset, &val))
10382                 return;
10383
10384         if ((val & 0xfc000000) == 0x0c000000) {
10385                 u32 ver_offset, addr;
10386                 int i;
10387
10388                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10389                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10390                         return;
10391
10392                 if (val != 0)
10393                         return;
10394
10395                 addr = offset + ver_offset - start;
10396                 for (i = 0; i < 16; i += 4) {
10397                         if (tg3_nvram_read(tp, addr + i, &val))
10398                                 return;
10399
10400                         val = cpu_to_le32(val);
10401                         memcpy(tp->fw_ver + i, &val, 4);
10402                 }
10403         }
10404 }
10405
10406 static int __devinit tg3_get_invariants(struct tg3 *tp)
10407 {
10408         static struct pci_device_id write_reorder_chipsets[] = {
10409                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10410                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10411                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10412                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10413                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10414                              PCI_DEVICE_ID_VIA_8385_0) },
10415                 { },
10416         };
10417         u32 misc_ctrl_reg;
10418         u32 cacheline_sz_reg;
10419         u32 pci_state_reg, grc_misc_cfg;
10420         u32 val;
10421         u16 pci_cmd;
10422         int err, pcie_cap;
10423
10424         /* Force memory write invalidate off.  If we leave it on,
10425          * then on 5700_BX chips we have to enable a workaround.
10426          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10427          * to match the cacheline size.  The Broadcom driver have this
10428          * workaround but turns MWI off all the times so never uses
10429          * it.  This seems to suggest that the workaround is insufficient.
10430          */
10431         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10432         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10433         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10434
10435         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10436          * has the register indirect write enable bit set before
10437          * we try to access any of the MMIO registers.  It is also
10438          * critical that the PCI-X hw workaround situation is decided
10439          * before that as well.
10440          */
10441         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10442                               &misc_ctrl_reg);
10443
10444         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10445                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10446
10447         /* Wrong chip ID in 5752 A0. This code can be removed later
10448          * as A0 is not in production.
10449          */
10450         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10451                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10452
10453         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10454          * we need to disable memory and use config. cycles
10455          * only to access all registers. The 5702/03 chips
10456          * can mistakenly decode the special cycles from the
10457          * ICH chipsets as memory write cycles, causing corruption
10458          * of register and memory space. Only certain ICH bridges
10459          * will drive special cycles with non-zero data during the
10460          * address phase which can fall within the 5703's address
10461          * range. This is not an ICH bug as the PCI spec allows
10462          * non-zero address during special cycles. However, only
10463          * these ICH bridges are known to drive non-zero addresses
10464          * during special cycles.
10465          *
10466          * Since special cycles do not cross PCI bridges, we only
10467          * enable this workaround if the 5703 is on the secondary
10468          * bus of these ICH bridges.
10469          */
10470         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10471             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10472                 static struct tg3_dev_id {
10473                         u32     vendor;
10474                         u32     device;
10475                         u32     rev;
10476                 } ich_chipsets[] = {
10477                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10478                           PCI_ANY_ID },
10479                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10480                           PCI_ANY_ID },
10481                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10482                           0xa },
10483                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10484                           PCI_ANY_ID },
10485                         { },
10486                 };
10487                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10488                 struct pci_dev *bridge = NULL;
10489
10490                 while (pci_id->vendor != 0) {
10491                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10492                                                 bridge);
10493                         if (!bridge) {
10494                                 pci_id++;
10495                                 continue;
10496                         }
10497                         if (pci_id->rev != PCI_ANY_ID) {
10498                                 u8 rev;
10499
10500                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10501                                                      &rev);
10502                                 if (rev > pci_id->rev)
10503                                         continue;
10504                         }
10505                         if (bridge->subordinate &&
10506                             (bridge->subordinate->number ==
10507                              tp->pdev->bus->number)) {
10508
10509                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10510                                 pci_dev_put(bridge);
10511                                 break;
10512                         }
10513                 }
10514         }
10515
10516         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10517          * DMA addresses > 40-bit. This bridge may have other additional
10518          * 57xx devices behind it in some 4-port NIC designs for example.
10519          * Any tg3 device found behind the bridge will also need the 40-bit
10520          * DMA workaround.
10521          */
10522         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10523             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10524                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10525                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10526                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10527         }
10528         else {
10529                 struct pci_dev *bridge = NULL;
10530
10531                 do {
10532                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10533                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10534                                                 bridge);
10535                         if (bridge && bridge->subordinate &&
10536                             (bridge->subordinate->number <=
10537                              tp->pdev->bus->number) &&
10538                             (bridge->subordinate->subordinate >=
10539                              tp->pdev->bus->number)) {
10540                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10541                                 pci_dev_put(bridge);
10542                                 break;
10543                         }
10544                 } while (bridge);
10545         }
10546
10547         /* Initialize misc host control in PCI block. */
10548         tp->misc_host_ctrl |= (misc_ctrl_reg &
10549                                MISC_HOST_CTRL_CHIPREV);
10550         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10551                                tp->misc_host_ctrl);
10552
10553         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10554                               &cacheline_sz_reg);
10555
10556         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10557         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10558         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10559         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10560
10561         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10562             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10563             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10564             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10565             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10566             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10567                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10568
10569         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10570             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10571                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10572
10573         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10574                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10575                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10576                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10577                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10578                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10579                 } else {
10580                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10581                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10582                                 ASIC_REV_5750 &&
10583                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10584                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10585                 }
10586         }
10587
10588         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10589             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10590             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10591             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10592             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10593             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10594                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10595
10596         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10597         if (pcie_cap != 0) {
10598                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10599                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10600                         u16 lnkctl;
10601
10602                         pci_read_config_word(tp->pdev,
10603                                              pcie_cap + PCI_EXP_LNKCTL,
10604                                              &lnkctl);
10605                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10606                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10607                 }
10608         }
10609
10610         /* If we have an AMD 762 or VIA K8T800 chipset, write
10611          * reordering to the mailbox registers done by the host
10612          * controller can cause major troubles.  We read back from
10613          * every mailbox register write to force the writes to be
10614          * posted to the chip in order.
10615          */
10616         if (pci_dev_present(write_reorder_chipsets) &&
10617             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10618                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10619
10620         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10621             tp->pci_lat_timer < 64) {
10622                 tp->pci_lat_timer = 64;
10623
10624                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10625                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10626                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10627                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10628
10629                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10630                                        cacheline_sz_reg);
10631         }
10632
10633         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10634                               &pci_state_reg);
10635
10636         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10637                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10638
10639                 /* If this is a 5700 BX chipset, and we are in PCI-X
10640                  * mode, enable register write workaround.
10641                  *
10642                  * The workaround is to use indirect register accesses
10643                  * for all chip writes not to mailbox registers.
10644                  */
10645                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10646                         u32 pm_reg;
10647                         u16 pci_cmd;
10648
10649                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10650
10651                         /* The chip can have it's power management PCI config
10652                          * space registers clobbered due to this bug.
10653                          * So explicitly force the chip into D0 here.
10654                          */
10655                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10656                                               &pm_reg);
10657                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10658                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10659                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10660                                                pm_reg);
10661
10662                         /* Also, force SERR#/PERR# in PCI command. */
10663                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10664                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10665                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10666                 }
10667         }
10668
10669         /* 5700 BX chips need to have their TX producer index mailboxes
10670          * written twice to workaround a bug.
10671          */
10672         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10673                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10674
10675         /* Back to back register writes can cause problems on this chip,
10676          * the workaround is to read back all reg writes except those to
10677          * mailbox regs.  See tg3_write_indirect_reg32().
10678          *
10679          * PCI Express 5750_A0 rev chips need this workaround too.
10680          */
10681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10682             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10683              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10684                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10685
10686         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10687                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10688         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10689                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10690
10691         /* Chip-specific fixup from Broadcom driver */
10692         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10693             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10694                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10695                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10696         }
10697
10698         /* Default fast path register access methods */
10699         tp->read32 = tg3_read32;
10700         tp->write32 = tg3_write32;
10701         tp->read32_mbox = tg3_read32;
10702         tp->write32_mbox = tg3_write32;
10703         tp->write32_tx_mbox = tg3_write32;
10704         tp->write32_rx_mbox = tg3_write32;
10705
10706         /* Various workaround register access methods */
10707         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10708                 tp->write32 = tg3_write_indirect_reg32;
10709         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10710                 tp->write32 = tg3_write_flush_reg32;
10711
10712         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10713             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10714                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10715                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10716                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10717         }
10718
10719         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10720                 tp->read32 = tg3_read_indirect_reg32;
10721                 tp->write32 = tg3_write_indirect_reg32;
10722                 tp->read32_mbox = tg3_read_indirect_mbox;
10723                 tp->write32_mbox = tg3_write_indirect_mbox;
10724                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10725                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10726
10727                 iounmap(tp->regs);
10728                 tp->regs = NULL;
10729
10730                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10731                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10732                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10733         }
10734         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10735                 tp->read32_mbox = tg3_read32_mbox_5906;
10736                 tp->write32_mbox = tg3_write32_mbox_5906;
10737                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10738                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10739         }
10740
10741         if (tp->write32 == tg3_write_indirect_reg32 ||
10742             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10743              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10744               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10745                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10746
10747         /* Get eeprom hw config before calling tg3_set_power_state().
10748          * In particular, the TG3_FLG2_IS_NIC flag must be
10749          * determined before calling tg3_set_power_state() so that
10750          * we know whether or not to switch out of Vaux power.
10751          * When the flag is set, it means that GPIO1 is used for eeprom
10752          * write protect and also implies that it is a LOM where GPIOs
10753          * are not used to switch power.
10754          */
10755         tg3_get_eeprom_hw_cfg(tp);
10756
10757         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10758          * GPIO1 driven high will bring 5700's external PHY out of reset.
10759          * It is also used as eeprom write protect on LOMs.
10760          */
10761         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10762         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10763             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10764                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10765                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10766         /* Unused GPIO3 must be driven as output on 5752 because there
10767          * are no pull-up resistors on unused GPIO pins.
10768          */
10769         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10770                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10771
10772         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10773                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10774
10775         /* Force the chip into D0. */
10776         err = tg3_set_power_state(tp, PCI_D0);
10777         if (err) {
10778                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10779                        pci_name(tp->pdev));
10780                 return err;
10781         }
10782
10783         /* 5700 B0 chips do not support checksumming correctly due
10784          * to hardware bugs.
10785          */
10786         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10787                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10788
10789         /* Derive initial jumbo mode from MTU assigned in
10790          * ether_setup() via the alloc_etherdev() call
10791          */
10792         if (tp->dev->mtu > ETH_DATA_LEN &&
10793             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10794                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10795
10796         /* Determine WakeOnLan speed to use. */
10797         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10798             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10799             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10800             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10801                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10802         } else {
10803                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10804         }
10805
10806         /* A few boards don't want Ethernet@WireSpeed phy feature */
10807         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10808             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10809              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10810              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10811             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10812             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10813                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10814
10815         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10816             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10817                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10818         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10819                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10820
10821         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10822                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10823                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10824                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10825                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10826                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10827                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10828                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10829                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10830                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10831         }
10832
10833         tp->coalesce_mode = 0;
10834         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10835             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10836                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10837
10838         /* Initialize MAC MI mode, polling disabled. */
10839         tw32_f(MAC_MI_MODE, tp->mi_mode);
10840         udelay(80);
10841
10842         /* Initialize data/descriptor byte/word swapping. */
10843         val = tr32(GRC_MODE);
10844         val &= GRC_MODE_HOST_STACKUP;
10845         tw32(GRC_MODE, val | tp->grc_mode);
10846
10847         tg3_switch_clocks(tp);
10848
10849         /* Clear this out for sanity. */
10850         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10851
10852         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10853                               &pci_state_reg);
10854         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10855             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10856                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10857
10858                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10859                     chiprevid == CHIPREV_ID_5701_B0 ||
10860                     chiprevid == CHIPREV_ID_5701_B2 ||
10861                     chiprevid == CHIPREV_ID_5701_B5) {
10862                         void __iomem *sram_base;
10863
10864                         /* Write some dummy words into the SRAM status block
10865                          * area, see if it reads back correctly.  If the return
10866                          * value is bad, force enable the PCIX workaround.
10867                          */
10868                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10869
10870                         writel(0x00000000, sram_base);
10871                         writel(0x00000000, sram_base + 4);
10872                         writel(0xffffffff, sram_base + 4);
10873                         if (readl(sram_base) != 0x00000000)
10874                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10875                 }
10876         }
10877
10878         udelay(50);
10879         tg3_nvram_init(tp);
10880
10881         grc_misc_cfg = tr32(GRC_MISC_CFG);
10882         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10883
10884         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10885             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10886              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10887                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10888
10889         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10890             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10891                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10892         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10893                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10894                                       HOSTCC_MODE_CLRTICK_TXBD);
10895
10896                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10897                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10898                                        tp->misc_host_ctrl);
10899         }
10900
10901         /* these are limited to 10/100 only */
10902         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10903              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10904             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10905              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10906              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10907               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10908               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10909             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10910              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10911               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10912               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10913             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10914                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10915
10916         err = tg3_phy_probe(tp);
10917         if (err) {
10918                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10919                        pci_name(tp->pdev), err);
10920                 /* ... but do not return immediately ... */
10921         }
10922
10923         tg3_read_partno(tp);
10924         tg3_read_fw_ver(tp);
10925
10926         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10927                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10928         } else {
10929                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10930                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10931                 else
10932                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10933         }
10934
10935         /* 5700 {AX,BX} chips have a broken status block link
10936          * change bit implementation, so we must use the
10937          * status register in those cases.
10938          */
10939         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10940                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10941         else
10942                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10943
10944         /* The led_ctrl is set during tg3_phy_probe, here we might
10945          * have to force the link status polling mechanism based
10946          * upon subsystem IDs.
10947          */
10948         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10949             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10950                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10951                                   TG3_FLAG_USE_LINKCHG_REG);
10952         }
10953
10954         /* For all SERDES we poll the MAC status register. */
10955         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10956                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10957         else
10958                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10959
10960         /* All chips before 5787 can get confused if TX buffers
10961          * straddle the 4GB address boundary in some cases.
10962          */
10963         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10964             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10965             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10966                 tp->dev->hard_start_xmit = tg3_start_xmit;
10967         else
10968                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10969
10970         tp->rx_offset = 2;
10971         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10972             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10973                 tp->rx_offset = 0;
10974
10975         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10976
10977         /* Increment the rx prod index on the rx std ring by at most
10978          * 8 for these chips to workaround hw errata.
10979          */
10980         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10981             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10982             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10983                 tp->rx_std_max_post = 8;
10984
10985         /* By default, disable wake-on-lan.  User can change this
10986          * using ETHTOOL_SWOL.
10987          */
10988         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10989
10990         return err;
10991 }
10992
10993 #ifdef CONFIG_SPARC
10994 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10995 {
10996         struct net_device *dev = tp->dev;
10997         struct pci_dev *pdev = tp->pdev;
10998         struct device_node *dp = pci_device_to_OF_node(pdev);
10999         const unsigned char *addr;
11000         int len;
11001
11002         addr = of_get_property(dp, "local-mac-address", &len);
11003         if (addr && len == 6) {
11004                 memcpy(dev->dev_addr, addr, 6);
11005                 memcpy(dev->perm_addr, dev->dev_addr, 6);
11006                 return 0;
11007         }
11008         return -ENODEV;
11009 }
11010
11011 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11012 {
11013         struct net_device *dev = tp->dev;
11014
11015         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11016         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11017         return 0;
11018 }
11019 #endif
11020
11021 static int __devinit tg3_get_device_address(struct tg3 *tp)
11022 {
11023         struct net_device *dev = tp->dev;
11024         u32 hi, lo, mac_offset;
11025         int addr_ok = 0;
11026
11027 #ifdef CONFIG_SPARC
11028         if (!tg3_get_macaddr_sparc(tp))
11029                 return 0;
11030 #endif
11031
11032         mac_offset = 0x7c;
11033         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11034             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11035                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11036                         mac_offset = 0xcc;
11037                 if (tg3_nvram_lock(tp))
11038                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11039                 else
11040                         tg3_nvram_unlock(tp);
11041         }
11042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11043                 mac_offset = 0x10;
11044
11045         /* First try to get it from MAC address mailbox. */
11046         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11047         if ((hi >> 16) == 0x484b) {
11048                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11049                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11050
11051                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11052                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11053                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11054                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11055                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11056
11057                 /* Some old bootcode may report a 0 MAC address in SRAM */
11058                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11059         }
11060         if (!addr_ok) {
11061                 /* Next, try NVRAM. */
11062                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11063                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11064                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11065                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11066                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11067                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11068                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11069                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11070                 }
11071                 /* Finally just fetch it out of the MAC control regs. */
11072                 else {
11073                         hi = tr32(MAC_ADDR_0_HIGH);
11074                         lo = tr32(MAC_ADDR_0_LOW);
11075
11076                         dev->dev_addr[5] = lo & 0xff;
11077                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11078                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11079                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11080                         dev->dev_addr[1] = hi & 0xff;
11081                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11082                 }
11083         }
11084
11085         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11086 #ifdef CONFIG_SPARC64
11087                 if (!tg3_get_default_macaddr_sparc(tp))
11088                         return 0;
11089 #endif
11090                 return -EINVAL;
11091         }
11092         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11093         return 0;
11094 }
11095
11096 #define BOUNDARY_SINGLE_CACHELINE       1
11097 #define BOUNDARY_MULTI_CACHELINE        2
11098
11099 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11100 {
11101         int cacheline_size;
11102         u8 byte;
11103         int goal;
11104
11105         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11106         if (byte == 0)
11107                 cacheline_size = 1024;
11108         else
11109                 cacheline_size = (int) byte * 4;
11110
11111         /* On 5703 and later chips, the boundary bits have no
11112          * effect.
11113          */
11114         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11115             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11116             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11117                 goto out;
11118
11119 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11120         goal = BOUNDARY_MULTI_CACHELINE;
11121 #else
11122 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11123         goal = BOUNDARY_SINGLE_CACHELINE;
11124 #else
11125         goal = 0;
11126 #endif
11127 #endif
11128
11129         if (!goal)
11130                 goto out;
11131
11132         /* PCI controllers on most RISC systems tend to disconnect
11133          * when a device tries to burst across a cache-line boundary.
11134          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11135          *
11136          * Unfortunately, for PCI-E there are only limited
11137          * write-side controls for this, and thus for reads
11138          * we will still get the disconnects.  We'll also waste
11139          * these PCI cycles for both read and write for chips
11140          * other than 5700 and 5701 which do not implement the
11141          * boundary bits.
11142          */
11143         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11144             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11145                 switch (cacheline_size) {
11146                 case 16:
11147                 case 32:
11148                 case 64:
11149                 case 128:
11150                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11151                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11152                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11153                         } else {
11154                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11155                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11156                         }
11157                         break;
11158
11159                 case 256:
11160                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11161                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11162                         break;
11163
11164                 default:
11165                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11166                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11167                         break;
11168                 };
11169         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11170                 switch (cacheline_size) {
11171                 case 16:
11172                 case 32:
11173                 case 64:
11174                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11175                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11176                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11177                                 break;
11178                         }
11179                         /* fallthrough */
11180                 case 128:
11181                 default:
11182                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11183                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11184                         break;
11185                 };
11186         } else {
11187                 switch (cacheline_size) {
11188                 case 16:
11189                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11190                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11191                                         DMA_RWCTRL_WRITE_BNDRY_16);
11192                                 break;
11193                         }
11194                         /* fallthrough */
11195                 case 32:
11196                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11197                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11198                                         DMA_RWCTRL_WRITE_BNDRY_32);
11199                                 break;
11200                         }
11201                         /* fallthrough */
11202                 case 64:
11203                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11204                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11205                                         DMA_RWCTRL_WRITE_BNDRY_64);
11206                                 break;
11207                         }
11208                         /* fallthrough */
11209                 case 128:
11210                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11211                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11212                                         DMA_RWCTRL_WRITE_BNDRY_128);
11213                                 break;
11214                         }
11215                         /* fallthrough */
11216                 case 256:
11217                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11218                                 DMA_RWCTRL_WRITE_BNDRY_256);
11219                         break;
11220                 case 512:
11221                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11222                                 DMA_RWCTRL_WRITE_BNDRY_512);
11223                         break;
11224                 case 1024:
11225                 default:
11226                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11227                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11228                         break;
11229                 };
11230         }
11231
11232 out:
11233         return val;
11234 }
11235
11236 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11237 {
11238         struct tg3_internal_buffer_desc test_desc;
11239         u32 sram_dma_descs;
11240         int i, ret;
11241
11242         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11243
11244         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11245         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11246         tw32(RDMAC_STATUS, 0);
11247         tw32(WDMAC_STATUS, 0);
11248
11249         tw32(BUFMGR_MODE, 0);
11250         tw32(FTQ_RESET, 0);
11251
11252         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11253         test_desc.addr_lo = buf_dma & 0xffffffff;
11254         test_desc.nic_mbuf = 0x00002100;
11255         test_desc.len = size;
11256
11257         /*
11258          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11259          * the *second* time the tg3 driver was getting loaded after an
11260          * initial scan.
11261          *
11262          * Broadcom tells me:
11263          *   ...the DMA engine is connected to the GRC block and a DMA
11264          *   reset may affect the GRC block in some unpredictable way...
11265          *   The behavior of resets to individual blocks has not been tested.
11266          *
11267          * Broadcom noted the GRC reset will also reset all sub-components.
11268          */
11269         if (to_device) {
11270                 test_desc.cqid_sqid = (13 << 8) | 2;
11271
11272                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11273                 udelay(40);
11274         } else {
11275                 test_desc.cqid_sqid = (16 << 8) | 7;
11276
11277                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11278                 udelay(40);
11279         }
11280         test_desc.flags = 0x00000005;
11281
11282         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11283                 u32 val;
11284
11285                 val = *(((u32 *)&test_desc) + i);
11286                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11287                                        sram_dma_descs + (i * sizeof(u32)));
11288                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11289         }
11290         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11291
11292         if (to_device) {
11293                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11294         } else {
11295                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11296         }
11297
11298         ret = -ENODEV;
11299         for (i = 0; i < 40; i++) {
11300                 u32 val;
11301
11302                 if (to_device)
11303                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11304                 else
11305                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11306                 if ((val & 0xffff) == sram_dma_descs) {
11307                         ret = 0;
11308                         break;
11309                 }
11310
11311                 udelay(100);
11312         }
11313
11314         return ret;
11315 }
11316
11317 #define TEST_BUFFER_SIZE        0x2000
11318
11319 static int __devinit tg3_test_dma(struct tg3 *tp)
11320 {
11321         dma_addr_t buf_dma;
11322         u32 *buf, saved_dma_rwctrl;
11323         int ret;
11324
11325         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11326         if (!buf) {
11327                 ret = -ENOMEM;
11328                 goto out_nofree;
11329         }
11330
11331         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11332                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11333
11334         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11335
11336         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11337                 /* DMA read watermark not used on PCIE */
11338                 tp->dma_rwctrl |= 0x00180000;
11339         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11340                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11341                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11342                         tp->dma_rwctrl |= 0x003f0000;
11343                 else
11344                         tp->dma_rwctrl |= 0x003f000f;
11345         } else {
11346                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11347                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11348                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11349                         u32 read_water = 0x7;
11350
11351                         /* If the 5704 is behind the EPB bridge, we can
11352                          * do the less restrictive ONE_DMA workaround for
11353                          * better performance.
11354                          */
11355                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11356                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11357                                 tp->dma_rwctrl |= 0x8000;
11358                         else if (ccval == 0x6 || ccval == 0x7)
11359                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11360
11361                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11362                                 read_water = 4;
11363                         /* Set bit 23 to enable PCIX hw bug fix */
11364                         tp->dma_rwctrl |=
11365                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11366                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11367                                 (1 << 23);
11368                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11369                         /* 5780 always in PCIX mode */
11370                         tp->dma_rwctrl |= 0x00144000;
11371                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11372                         /* 5714 always in PCIX mode */
11373                         tp->dma_rwctrl |= 0x00148000;
11374                 } else {
11375                         tp->dma_rwctrl |= 0x001b000f;
11376                 }
11377         }
11378
11379         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11380             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11381                 tp->dma_rwctrl &= 0xfffffff0;
11382
11383         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11384             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11385                 /* Remove this if it causes problems for some boards. */
11386                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11387
11388                 /* On 5700/5701 chips, we need to set this bit.
11389                  * Otherwise the chip will issue cacheline transactions
11390                  * to streamable DMA memory with not all the byte
11391                  * enables turned on.  This is an error on several
11392                  * RISC PCI controllers, in particular sparc64.
11393                  *
11394                  * On 5703/5704 chips, this bit has been reassigned
11395                  * a different meaning.  In particular, it is used
11396                  * on those chips to enable a PCI-X workaround.
11397                  */
11398                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11399         }
11400
11401         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11402
11403 #if 0
11404         /* Unneeded, already done by tg3_get_invariants.  */
11405         tg3_switch_clocks(tp);
11406 #endif
11407
11408         ret = 0;
11409         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11410             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11411                 goto out;
11412
11413         /* It is best to perform DMA test with maximum write burst size
11414          * to expose the 5700/5701 write DMA bug.
11415          */
11416         saved_dma_rwctrl = tp->dma_rwctrl;
11417         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11418         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11419
11420         while (1) {
11421                 u32 *p = buf, i;
11422
11423                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11424                         p[i] = i;
11425
11426                 /* Send the buffer to the chip. */
11427                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11428                 if (ret) {
11429                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11430                         break;
11431                 }
11432
11433 #if 0
11434                 /* validate data reached card RAM correctly. */
11435                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11436                         u32 val;
11437                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11438                         if (le32_to_cpu(val) != p[i]) {
11439                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11440                                 /* ret = -ENODEV here? */
11441                         }
11442                         p[i] = 0;
11443                 }
11444 #endif
11445                 /* Now read it back. */
11446                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11447                 if (ret) {
11448                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11449
11450                         break;
11451                 }
11452
11453                 /* Verify it. */
11454                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11455                         if (p[i] == i)
11456                                 continue;
11457
11458                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11459                             DMA_RWCTRL_WRITE_BNDRY_16) {
11460                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11461                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11462                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11463                                 break;
11464                         } else {
11465                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11466                                 ret = -ENODEV;
11467                                 goto out;
11468                         }
11469                 }
11470
11471                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11472                         /* Success. */
11473                         ret = 0;
11474                         break;
11475                 }
11476         }
11477         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11478             DMA_RWCTRL_WRITE_BNDRY_16) {
11479                 static struct pci_device_id dma_wait_state_chipsets[] = {
11480                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11481                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11482                         { },
11483                 };
11484
11485                 /* DMA test passed without adjusting DMA boundary,
11486                  * now look for chipsets that are known to expose the
11487                  * DMA bug without failing the test.
11488                  */
11489                 if (pci_dev_present(dma_wait_state_chipsets)) {
11490                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11491                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11492                 }
11493                 else
11494                         /* Safe to use the calculated DMA boundary. */
11495                         tp->dma_rwctrl = saved_dma_rwctrl;
11496
11497                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11498         }
11499
11500 out:
11501         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11502 out_nofree:
11503         return ret;
11504 }
11505
11506 static void __devinit tg3_init_link_config(struct tg3 *tp)
11507 {
11508         tp->link_config.advertising =
11509                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11510                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11511                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11512                  ADVERTISED_Autoneg | ADVERTISED_MII);
11513         tp->link_config.speed = SPEED_INVALID;
11514         tp->link_config.duplex = DUPLEX_INVALID;
11515         tp->link_config.autoneg = AUTONEG_ENABLE;
11516         tp->link_config.active_speed = SPEED_INVALID;
11517         tp->link_config.active_duplex = DUPLEX_INVALID;
11518         tp->link_config.phy_is_low_power = 0;
11519         tp->link_config.orig_speed = SPEED_INVALID;
11520         tp->link_config.orig_duplex = DUPLEX_INVALID;
11521         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11522 }
11523
11524 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11525 {
11526         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11527                 tp->bufmgr_config.mbuf_read_dma_low_water =
11528                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11529                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11530                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11531                 tp->bufmgr_config.mbuf_high_water =
11532                         DEFAULT_MB_HIGH_WATER_5705;
11533                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11534                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11535                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11536                         tp->bufmgr_config.mbuf_high_water =
11537                                 DEFAULT_MB_HIGH_WATER_5906;
11538                 }
11539
11540                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11541                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11542                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11543                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11544                 tp->bufmgr_config.mbuf_high_water_jumbo =
11545                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11546         } else {
11547                 tp->bufmgr_config.mbuf_read_dma_low_water =
11548                         DEFAULT_MB_RDMA_LOW_WATER;
11549                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11550                         DEFAULT_MB_MACRX_LOW_WATER;
11551                 tp->bufmgr_config.mbuf_high_water =
11552                         DEFAULT_MB_HIGH_WATER;
11553
11554                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11555                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11556                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11557                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11558                 tp->bufmgr_config.mbuf_high_water_jumbo =
11559                         DEFAULT_MB_HIGH_WATER_JUMBO;
11560         }
11561
11562         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11563         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11564 }
11565
11566 static char * __devinit tg3_phy_string(struct tg3 *tp)
11567 {
11568         switch (tp->phy_id & PHY_ID_MASK) {
11569         case PHY_ID_BCM5400:    return "5400";
11570         case PHY_ID_BCM5401:    return "5401";
11571         case PHY_ID_BCM5411:    return "5411";
11572         case PHY_ID_BCM5701:    return "5701";
11573         case PHY_ID_BCM5703:    return "5703";
11574         case PHY_ID_BCM5704:    return "5704";
11575         case PHY_ID_BCM5705:    return "5705";
11576         case PHY_ID_BCM5750:    return "5750";
11577         case PHY_ID_BCM5752:    return "5752";
11578         case PHY_ID_BCM5714:    return "5714";
11579         case PHY_ID_BCM5780:    return "5780";
11580         case PHY_ID_BCM5755:    return "5755";
11581         case PHY_ID_BCM5787:    return "5787";
11582         case PHY_ID_BCM5756:    return "5722/5756";
11583         case PHY_ID_BCM5906:    return "5906";
11584         case PHY_ID_BCM8002:    return "8002/serdes";
11585         case 0:                 return "serdes";
11586         default:                return "unknown";
11587         };
11588 }
11589
11590 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11591 {
11592         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11593                 strcpy(str, "PCI Express");
11594                 return str;
11595         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11596                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11597
11598                 strcpy(str, "PCIX:");
11599
11600                 if ((clock_ctrl == 7) ||
11601                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11602                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11603                         strcat(str, "133MHz");
11604                 else if (clock_ctrl == 0)
11605                         strcat(str, "33MHz");
11606                 else if (clock_ctrl == 2)
11607                         strcat(str, "50MHz");
11608                 else if (clock_ctrl == 4)
11609                         strcat(str, "66MHz");
11610                 else if (clock_ctrl == 6)
11611                         strcat(str, "100MHz");
11612         } else {
11613                 strcpy(str, "PCI:");
11614                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11615                         strcat(str, "66MHz");
11616                 else
11617                         strcat(str, "33MHz");
11618         }
11619         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11620                 strcat(str, ":32-bit");
11621         else
11622                 strcat(str, ":64-bit");
11623         return str;
11624 }
11625
11626 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11627 {
11628         struct pci_dev *peer;
11629         unsigned int func, devnr = tp->pdev->devfn & ~7;
11630
11631         for (func = 0; func < 8; func++) {
11632                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11633                 if (peer && peer != tp->pdev)
11634                         break;
11635                 pci_dev_put(peer);
11636         }
11637         /* 5704 can be configured in single-port mode, set peer to
11638          * tp->pdev in that case.
11639          */
11640         if (!peer) {
11641                 peer = tp->pdev;
11642                 return peer;
11643         }
11644
11645         /*
11646          * We don't need to keep the refcount elevated; there's no way
11647          * to remove one half of this device without removing the other
11648          */
11649         pci_dev_put(peer);
11650
11651         return peer;
11652 }
11653
11654 static void __devinit tg3_init_coal(struct tg3 *tp)
11655 {
11656         struct ethtool_coalesce *ec = &tp->coal;
11657
11658         memset(ec, 0, sizeof(*ec));
11659         ec->cmd = ETHTOOL_GCOALESCE;
11660         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11661         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11662         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11663         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11664         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11665         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11666         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11667         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11668         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11669
11670         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11671                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11672                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11673                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11674                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11675                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11676         }
11677
11678         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11679                 ec->rx_coalesce_usecs_irq = 0;
11680                 ec->tx_coalesce_usecs_irq = 0;
11681                 ec->stats_block_coalesce_usecs = 0;
11682         }
11683 }
11684
11685 static int __devinit tg3_init_one(struct pci_dev *pdev,
11686                                   const struct pci_device_id *ent)
11687 {
11688         static int tg3_version_printed = 0;
11689         unsigned long tg3reg_base, tg3reg_len;
11690         struct net_device *dev;
11691         struct tg3 *tp;
11692         int i, err, pm_cap;
11693         char str[40];
11694         u64 dma_mask, persist_dma_mask;
11695
11696         if (tg3_version_printed++ == 0)
11697                 printk(KERN_INFO "%s", version);
11698
11699         err = pci_enable_device(pdev);
11700         if (err) {
11701                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11702                        "aborting.\n");
11703                 return err;
11704         }
11705
11706         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11707                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11708                        "base address, aborting.\n");
11709                 err = -ENODEV;
11710                 goto err_out_disable_pdev;
11711         }
11712
11713         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11714         if (err) {
11715                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11716                        "aborting.\n");
11717                 goto err_out_disable_pdev;
11718         }
11719
11720         pci_set_master(pdev);
11721
11722         /* Find power-management capability. */
11723         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11724         if (pm_cap == 0) {
11725                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11726                        "aborting.\n");
11727                 err = -EIO;
11728                 goto err_out_free_res;
11729         }
11730
11731         tg3reg_base = pci_resource_start(pdev, 0);
11732         tg3reg_len = pci_resource_len(pdev, 0);
11733
11734         dev = alloc_etherdev(sizeof(*tp));
11735         if (!dev) {
11736                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11737                 err = -ENOMEM;
11738                 goto err_out_free_res;
11739         }
11740
11741         SET_MODULE_OWNER(dev);
11742         SET_NETDEV_DEV(dev, &pdev->dev);
11743
11744 #if TG3_VLAN_TAG_USED
11745         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11746         dev->vlan_rx_register = tg3_vlan_rx_register;
11747         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11748 #endif
11749
11750         tp = netdev_priv(dev);
11751         tp->pdev = pdev;
11752         tp->dev = dev;
11753         tp->pm_cap = pm_cap;
11754         tp->mac_mode = TG3_DEF_MAC_MODE;
11755         tp->rx_mode = TG3_DEF_RX_MODE;
11756         tp->tx_mode = TG3_DEF_TX_MODE;
11757         tp->mi_mode = MAC_MI_MODE_BASE;
11758         if (tg3_debug > 0)
11759                 tp->msg_enable = tg3_debug;
11760         else
11761                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11762
11763         /* The word/byte swap controls here control register access byte
11764          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11765          * setting below.
11766          */
11767         tp->misc_host_ctrl =
11768                 MISC_HOST_CTRL_MASK_PCI_INT |
11769                 MISC_HOST_CTRL_WORD_SWAP |
11770                 MISC_HOST_CTRL_INDIR_ACCESS |
11771                 MISC_HOST_CTRL_PCISTATE_RW;
11772
11773         /* The NONFRM (non-frame) byte/word swap controls take effect
11774          * on descriptor entries, anything which isn't packet data.
11775          *
11776          * The StrongARM chips on the board (one for tx, one for rx)
11777          * are running in big-endian mode.
11778          */
11779         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11780                         GRC_MODE_WSWAP_NONFRM_DATA);
11781 #ifdef __BIG_ENDIAN
11782         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11783 #endif
11784         spin_lock_init(&tp->lock);
11785         spin_lock_init(&tp->indirect_lock);
11786         INIT_WORK(&tp->reset_task, tg3_reset_task);
11787
11788         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11789         if (tp->regs == 0UL) {
11790                 printk(KERN_ERR PFX "Cannot map device registers, "
11791                        "aborting.\n");
11792                 err = -ENOMEM;
11793                 goto err_out_free_dev;
11794         }
11795
11796         tg3_init_link_config(tp);
11797
11798         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11799         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11800         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11801
11802         dev->open = tg3_open;
11803         dev->stop = tg3_close;
11804         dev->get_stats = tg3_get_stats;
11805         dev->set_multicast_list = tg3_set_rx_mode;
11806         dev->set_mac_address = tg3_set_mac_addr;
11807         dev->do_ioctl = tg3_ioctl;
11808         dev->tx_timeout = tg3_tx_timeout;
11809         dev->poll = tg3_poll;
11810         dev->ethtool_ops = &tg3_ethtool_ops;
11811         dev->weight = 64;
11812         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11813         dev->change_mtu = tg3_change_mtu;
11814         dev->irq = pdev->irq;
11815 #ifdef CONFIG_NET_POLL_CONTROLLER
11816         dev->poll_controller = tg3_poll_controller;
11817 #endif
11818
11819         err = tg3_get_invariants(tp);
11820         if (err) {
11821                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11822                        "aborting.\n");
11823                 goto err_out_iounmap;
11824         }
11825
11826         /* The EPB bridge inside 5714, 5715, and 5780 and any
11827          * device behind the EPB cannot support DMA addresses > 40-bit.
11828          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11829          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11830          * do DMA address check in tg3_start_xmit().
11831          */
11832         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11833                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11834         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11835                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11836 #ifdef CONFIG_HIGHMEM
11837                 dma_mask = DMA_64BIT_MASK;
11838 #endif
11839         } else
11840                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11841
11842         /* Configure DMA attributes. */
11843         if (dma_mask > DMA_32BIT_MASK) {
11844                 err = pci_set_dma_mask(pdev, dma_mask);
11845                 if (!err) {
11846                         dev->features |= NETIF_F_HIGHDMA;
11847                         err = pci_set_consistent_dma_mask(pdev,
11848                                                           persist_dma_mask);
11849                         if (err < 0) {
11850                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11851                                        "DMA for consistent allocations\n");
11852                                 goto err_out_iounmap;
11853                         }
11854                 }
11855         }
11856         if (err || dma_mask == DMA_32BIT_MASK) {
11857                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11858                 if (err) {
11859                         printk(KERN_ERR PFX "No usable DMA configuration, "
11860                                "aborting.\n");
11861                         goto err_out_iounmap;
11862                 }
11863         }
11864
11865         tg3_init_bufmgr_config(tp);
11866
11867         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11868                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11869         }
11870         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11872             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11873             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11874             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11875                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11876         } else {
11877                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11878         }
11879
11880         /* TSO is on by default on chips that support hardware TSO.
11881          * Firmware TSO on older chips gives lower performance, so it
11882          * is off by default, but can be enabled using ethtool.
11883          */
11884         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11885                 dev->features |= NETIF_F_TSO;
11886                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11887                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11888                         dev->features |= NETIF_F_TSO6;
11889         }
11890
11891
11892         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11893             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11894             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11895                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11896                 tp->rx_pending = 63;
11897         }
11898
11899         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11900             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11901                 tp->pdev_peer = tg3_find_peer(tp);
11902
11903         err = tg3_get_device_address(tp);
11904         if (err) {
11905                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11906                        "aborting.\n");
11907                 goto err_out_iounmap;
11908         }
11909
11910         /*
11911          * Reset chip in case UNDI or EFI driver did not shutdown
11912          * DMA self test will enable WDMAC and we'll see (spurious)
11913          * pending DMA on the PCI bus at that point.
11914          */
11915         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11916             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11917                 pci_save_state(tp->pdev);
11918                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11919                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11920         }
11921
11922         err = tg3_test_dma(tp);
11923         if (err) {
11924                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11925                 goto err_out_iounmap;
11926         }
11927
11928         /* Tigon3 can do ipv4 only... and some chips have buggy
11929          * checksumming.
11930          */
11931         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11932                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11933                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11934                         dev->features |= NETIF_F_HW_CSUM;
11935                 else
11936                         dev->features |= NETIF_F_IP_CSUM;
11937                 dev->features |= NETIF_F_SG;
11938                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11939         } else
11940                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11941
11942         /* flow control autonegotiation is default behavior */
11943         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11944
11945         tg3_init_coal(tp);
11946
11947         /* Now that we have fully setup the chip, save away a snapshot
11948          * of the PCI config space.  We need to restore this after
11949          * GRC_MISC_CFG core clock resets and some resume events.
11950          */
11951         pci_save_state(tp->pdev);
11952
11953         pci_set_drvdata(pdev, dev);
11954
11955         err = register_netdev(dev);
11956         if (err) {
11957                 printk(KERN_ERR PFX "Cannot register net device, "
11958                        "aborting.\n");
11959                 goto err_out_iounmap;
11960         }
11961
11962         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11963                dev->name,
11964                tp->board_part_number,
11965                tp->pci_chip_rev_id,
11966                tg3_phy_string(tp),
11967                tg3_bus_string(tp, str),
11968                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11969                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11970                  "10/100/1000Base-T")));
11971
11972         for (i = 0; i < 6; i++)
11973                 printk("%2.2x%c", dev->dev_addr[i],
11974                        i == 5 ? '\n' : ':');
11975
11976         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11977                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
11978                dev->name,
11979                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11980                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11981                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11982                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11983                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11984                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11985         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11986                dev->name, tp->dma_rwctrl,
11987                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11988                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11989
11990         return 0;
11991
11992 err_out_iounmap:
11993         if (tp->regs) {
11994                 iounmap(tp->regs);
11995                 tp->regs = NULL;
11996         }
11997
11998 err_out_free_dev:
11999         free_netdev(dev);
12000
12001 err_out_free_res:
12002         pci_release_regions(pdev);
12003
12004 err_out_disable_pdev:
12005         pci_disable_device(pdev);
12006         pci_set_drvdata(pdev, NULL);
12007         return err;
12008 }
12009
12010 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12011 {
12012         struct net_device *dev = pci_get_drvdata(pdev);
12013
12014         if (dev) {
12015                 struct tg3 *tp = netdev_priv(dev);
12016
12017                 flush_scheduled_work();
12018                 unregister_netdev(dev);
12019                 if (tp->regs) {
12020                         iounmap(tp->regs);
12021                         tp->regs = NULL;
12022                 }
12023                 free_netdev(dev);
12024                 pci_release_regions(pdev);
12025                 pci_disable_device(pdev);
12026                 pci_set_drvdata(pdev, NULL);
12027         }
12028 }
12029
12030 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12031 {
12032         struct net_device *dev = pci_get_drvdata(pdev);
12033         struct tg3 *tp = netdev_priv(dev);
12034         int err;
12035
12036         if (!netif_running(dev))
12037                 return 0;
12038
12039         flush_scheduled_work();
12040         tg3_netif_stop(tp);
12041
12042         del_timer_sync(&tp->timer);
12043
12044         tg3_full_lock(tp, 1);
12045         tg3_disable_ints(tp);
12046         tg3_full_unlock(tp);
12047
12048         netif_device_detach(dev);
12049
12050         tg3_full_lock(tp, 0);
12051         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12052         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12053         tg3_full_unlock(tp);
12054
12055         /* Save MSI address and data for resume.  */
12056         pci_save_state(pdev);
12057
12058         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12059         if (err) {
12060                 tg3_full_lock(tp, 0);
12061
12062                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12063                 if (tg3_restart_hw(tp, 1))
12064                         goto out;
12065
12066                 tp->timer.expires = jiffies + tp->timer_offset;
12067                 add_timer(&tp->timer);
12068
12069                 netif_device_attach(dev);
12070                 tg3_netif_start(tp);
12071
12072 out:
12073                 tg3_full_unlock(tp);
12074         }
12075
12076         return err;
12077 }
12078
12079 static int tg3_resume(struct pci_dev *pdev)
12080 {
12081         struct net_device *dev = pci_get_drvdata(pdev);
12082         struct tg3 *tp = netdev_priv(dev);
12083         int err;
12084
12085         if (!netif_running(dev))
12086                 return 0;
12087
12088         pci_restore_state(tp->pdev);
12089
12090         err = tg3_set_power_state(tp, PCI_D0);
12091         if (err)
12092                 return err;
12093
12094         netif_device_attach(dev);
12095
12096         tg3_full_lock(tp, 0);
12097
12098         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12099         err = tg3_restart_hw(tp, 1);
12100         if (err)
12101                 goto out;
12102
12103         tp->timer.expires = jiffies + tp->timer_offset;
12104         add_timer(&tp->timer);
12105
12106         tg3_netif_start(tp);
12107
12108 out:
12109         tg3_full_unlock(tp);
12110
12111         return err;
12112 }
12113
12114 static struct pci_driver tg3_driver = {
12115         .name           = DRV_MODULE_NAME,
12116         .id_table       = tg3_pci_tbl,
12117         .probe          = tg3_init_one,
12118         .remove         = __devexit_p(tg3_remove_one),
12119         .suspend        = tg3_suspend,
12120         .resume         = tg3_resume
12121 };
12122
12123 static int __init tg3_init(void)
12124 {
12125         return pci_register_driver(&tg3_driver);
12126 }
12127
12128 static void __exit tg3_cleanup(void)
12129 {
12130         pci_unregister_driver(&tg3_driver);
12131 }
12132
12133 module_init(tg3_init);
12134 module_exit(tg3_cleanup);