1 // SPDX-License-Identifier: GPL-2.0+
3 * sh_eth.c - Driver for Renesas ethernet controller.
5 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
6 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
7 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
8 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
20 #include <asm/cache.h>
21 #include <linux/errno.h>
27 #include <linux/mii.h>
33 #ifndef CONFIG_SH_ETHER_USE_PORT
34 # error "Please define CONFIG_SH_ETHER_USE_PORT"
36 #ifndef CONFIG_SH_ETHER_PHY_ADDR
37 # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
40 #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
41 !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
42 #define flush_cache_wback(addr, len) \
43 flush_dcache_range((unsigned long)addr, \
44 (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
46 #define flush_cache_wback(...)
49 #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
50 #define invalidate_cache(addr, len) \
52 unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
53 unsigned long start, end; \
55 start = (unsigned long)addr; \
57 start &= ~(line_size - 1); \
58 end = ((end + line_size - 1) & ~(line_size - 1)); \
60 invalidate_dcache_range(start, end); \
63 #define invalidate_cache(...)
66 #define TIMEOUT_CNT 1000
68 static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
71 struct sh_eth_info *port_info = ð->port_info[eth->port];
73 if (!packet || len > 0xffff) {
74 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
79 /* packet must be a 4 byte boundary */
80 if ((uintptr_t)packet & 3) {
81 printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
87 /* Update tx descriptor */
88 flush_cache_wback(packet, len);
89 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
90 port_info->tx_desc_cur->td1 = len << 16;
91 /* Must preserve the end of descriptor list indication */
92 if (port_info->tx_desc_cur->td0 & TD_TDLE)
93 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
95 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
97 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
99 /* Restart the transmitter if disabled */
100 if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
101 sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
103 /* Wait until packet is transmitted */
104 timeout = TIMEOUT_CNT;
106 invalidate_cache(port_info->tx_desc_cur,
107 sizeof(struct tx_desc_s));
109 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
112 printf(SHETHER_NAME ": transmit timeout\n");
117 port_info->tx_desc_cur++;
118 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
119 port_info->tx_desc_cur = port_info->tx_desc_base;
125 static int sh_eth_recv_start(struct sh_eth_dev *eth)
127 struct sh_eth_info *port_info = ð->port_info[eth->port];
129 /* Check if the rx descriptor is ready */
130 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
131 if (port_info->rx_desc_cur->rd0 & RD_RACT)
134 /* Check for errors */
135 if (port_info->rx_desc_cur->rd0 & RD_RFE)
138 return port_info->rx_desc_cur->rd1 & 0xffff;
141 static void sh_eth_recv_finish(struct sh_eth_dev *eth)
143 struct sh_eth_info *port_info = ð->port_info[eth->port];
145 /* Make current descriptor available again */
146 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
147 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
149 port_info->rx_desc_cur->rd0 = RD_RACT;
151 flush_cache_wback(port_info->rx_desc_cur,
152 sizeof(struct rx_desc_s));
154 /* Point to the next descriptor */
155 port_info->rx_desc_cur++;
156 if (port_info->rx_desc_cur >=
157 port_info->rx_desc_base + NUM_RX_DESC)
158 port_info->rx_desc_cur = port_info->rx_desc_base;
161 static int sh_eth_reset(struct sh_eth_dev *eth)
163 struct sh_eth_info *port_info = ð->port_info[eth->port];
164 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
167 /* Start e-dmac transmitter and receiver */
168 sh_eth_write(port_info, EDSR_ENALL, EDSR);
170 /* Perform a software reset and wait for it to complete */
171 sh_eth_write(port_info, EDMR_SRST, EDMR);
172 for (i = 0; i < TIMEOUT_CNT; i++) {
173 if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
178 if (i == TIMEOUT_CNT) {
179 printf(SHETHER_NAME ": Software reset timeout\n");
185 sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
187 sh_eth_write(port_info,
188 sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
194 static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
197 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
198 struct sh_eth_info *port_info = ð->port_info[eth->port];
199 struct tx_desc_s *cur_tx_desc;
202 * Allocate rx descriptors. They must be aligned to size of struct
205 port_info->tx_desc_alloc =
206 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
207 if (!port_info->tx_desc_alloc) {
208 printf(SHETHER_NAME ": memalign failed\n");
213 flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
215 /* Make sure we use a P2 address (non-cacheable) */
216 port_info->tx_desc_base =
217 (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
218 port_info->tx_desc_cur = port_info->tx_desc_base;
220 /* Initialize all descriptors */
221 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
222 cur_tx_desc++, i++) {
223 cur_tx_desc->td0 = 0x00;
224 cur_tx_desc->td1 = 0x00;
225 cur_tx_desc->td2 = 0x00;
228 /* Mark the end of the descriptors */
230 cur_tx_desc->td0 |= TD_TDLE;
233 * Point the controller to the tx descriptor list. Must use physical
236 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
237 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
238 sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
239 sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
240 sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
247 static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
250 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
251 struct sh_eth_info *port_info = ð->port_info[eth->port];
252 struct rx_desc_s *cur_rx_desc;
256 * Allocate rx descriptors. They must be aligned to size of struct
259 port_info->rx_desc_alloc =
260 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
261 if (!port_info->rx_desc_alloc) {
262 printf(SHETHER_NAME ": memalign failed\n");
267 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
269 /* Make sure we use a P2 address (non-cacheable) */
270 port_info->rx_desc_base =
271 (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
273 port_info->rx_desc_cur = port_info->rx_desc_base;
276 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
277 * aligned and in P2 area.
279 port_info->rx_buf_alloc =
280 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
281 if (!port_info->rx_buf_alloc) {
282 printf(SHETHER_NAME ": alloc failed\n");
287 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
289 /* Initialize all descriptors */
290 for (cur_rx_desc = port_info->rx_desc_base,
291 rx_buf = port_info->rx_buf_base, i = 0;
292 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
293 cur_rx_desc->rd0 = RD_RACT;
294 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
295 cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
298 /* Mark the end of the descriptors */
300 cur_rx_desc->rd0 |= RD_RDLE;
302 /* Point the controller to the rx descriptor list */
303 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
304 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
305 sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
306 sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
307 sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
313 free(port_info->rx_desc_alloc);
314 port_info->rx_desc_alloc = NULL;
320 static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
322 struct sh_eth_info *port_info = ð->port_info[eth->port];
324 if (port_info->tx_desc_alloc) {
325 free(port_info->tx_desc_alloc);
326 port_info->tx_desc_alloc = NULL;
330 static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
332 struct sh_eth_info *port_info = ð->port_info[eth->port];
334 if (port_info->rx_desc_alloc) {
335 free(port_info->rx_desc_alloc);
336 port_info->rx_desc_alloc = NULL;
339 if (port_info->rx_buf_alloc) {
340 free(port_info->rx_buf_alloc);
341 port_info->rx_buf_alloc = NULL;
345 static int sh_eth_desc_init(struct sh_eth_dev *eth)
349 ret = sh_eth_tx_desc_init(eth);
353 ret = sh_eth_rx_desc_init(eth);
359 sh_eth_tx_desc_free(eth);
365 static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
370 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
371 sh_eth_write(port_info, val, MAHR);
373 val = (mac[4] << 8) | mac[5];
374 sh_eth_write(port_info, val, MALR);
377 static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
379 struct sh_eth_info *port_info = ð->port_info[eth->port];
382 /* Configure e-dmac registers */
383 edmr = sh_eth_read(port_info, EDMR);
384 edmr &= ~EMDR_DESC_R;
385 edmr |= EMDR_DESC | EDMR_EL;
386 #if defined(CONFIG_R8A77980)
389 sh_eth_write(port_info, edmr, EDMR);
391 sh_eth_write(port_info, 0, EESIPR);
392 sh_eth_write(port_info, 0, TRSCER);
393 sh_eth_write(port_info, 0, TFTR);
394 sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
395 sh_eth_write(port_info, RMCR_RST, RMCR);
396 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
397 sh_eth_write(port_info, 0, RPADIR);
399 sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
401 /* Configure e-mac registers */
402 sh_eth_write(port_info, 0, ECSIPR);
404 /* Set Mac address */
405 sh_eth_write_hwaddr(port_info, mac);
407 sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
408 #if defined(SH_ETH_TYPE_GETHER)
409 sh_eth_write(port_info, 0, PIPR);
411 #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
412 sh_eth_write(port_info, APR_AP, APR);
413 sh_eth_write(port_info, MPR_MP, MPR);
414 sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
417 #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
418 sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
419 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
420 sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
424 static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
426 struct sh_eth_info *port_info = ð->port_info[eth->port];
427 struct phy_device *phy = port_info->phydev;
431 /* Set the transfer speed */
432 if (phy->speed == 100) {
433 printf(SHETHER_NAME ": 100Base/");
434 #if defined(SH_ETH_TYPE_GETHER)
435 sh_eth_write(port_info, GECMR_100B, GECMR);
436 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
437 sh_eth_write(port_info, 1, RTRATE);
438 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
441 } else if (phy->speed == 10) {
442 printf(SHETHER_NAME ": 10Base/");
443 #if defined(SH_ETH_TYPE_GETHER)
444 sh_eth_write(port_info, GECMR_10B, GECMR);
445 #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
446 sh_eth_write(port_info, 0, RTRATE);
449 #if defined(SH_ETH_TYPE_GETHER)
450 else if (phy->speed == 1000) {
451 printf(SHETHER_NAME ": 1000Base/");
452 sh_eth_write(port_info, GECMR_1000B, GECMR);
456 /* Check if full duplex mode is supported by the phy */
459 sh_eth_write(port_info,
460 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
464 sh_eth_write(port_info,
465 val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
472 static void sh_eth_start(struct sh_eth_dev *eth)
474 struct sh_eth_info *port_info = ð->port_info[eth->port];
477 * Enable the e-dmac receiver only. The transmitter will be enabled when
478 * we have something to transmit
480 sh_eth_write(port_info, EDRRR_R, EDRRR);
483 static void sh_eth_stop(struct sh_eth_dev *eth)
485 struct sh_eth_info *port_info = ð->port_info[eth->port];
487 sh_eth_write(port_info, ~EDRRR_R, EDRRR);
490 static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
494 ret = sh_eth_reset(eth);
498 ret = sh_eth_desc_init(eth);
502 sh_eth_mac_regs_config(eth, mac);
507 static int sh_eth_start_common(struct sh_eth_dev *eth)
509 struct sh_eth_info *port_info = ð->port_info[eth->port];
512 ret = phy_startup(port_info->phydev);
514 printf(SHETHER_NAME ": phy startup failure\n");
518 ret = sh_eth_phy_regs_config(eth);
527 #ifndef CONFIG_DM_ETH
528 static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
531 struct sh_eth_info *port_info = ð->port_info[eth->port];
532 struct eth_device *dev = port_info->dev;
533 struct phy_device *phydev;
535 phydev = phy_connect(
536 miiphy_get_dev_by_name(dev->name),
537 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
538 port_info->phydev = phydev;
544 static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
546 struct sh_eth_dev *eth = dev->priv;
548 return sh_eth_send_common(eth, packet, len);
551 static int sh_eth_recv_common(struct sh_eth_dev *eth)
554 struct sh_eth_info *port_info = ð->port_info[eth->port];
555 uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
557 len = sh_eth_recv_start(eth);
559 invalidate_cache(packet, len);
560 net_process_received_packet(packet, len);
561 sh_eth_recv_finish(eth);
565 /* Restart the receiver if disabled */
566 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
567 sh_eth_write(port_info, EDRRR_R, EDRRR);
572 static int sh_eth_recv_legacy(struct eth_device *dev)
574 struct sh_eth_dev *eth = dev->priv;
576 return sh_eth_recv_common(eth);
579 static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
581 struct sh_eth_dev *eth = dev->priv;
584 ret = sh_eth_init_common(eth, dev->enetaddr);
588 ret = sh_eth_phy_config_legacy(eth);
590 printf(SHETHER_NAME ": phy config timeout\n");
594 ret = sh_eth_start_common(eth);
601 sh_eth_tx_desc_free(eth);
602 sh_eth_rx_desc_free(eth);
606 void sh_eth_halt_legacy(struct eth_device *dev)
608 struct sh_eth_dev *eth = dev->priv;
613 int sh_eth_initialize(bd_t *bd)
616 struct sh_eth_dev *eth = NULL;
617 struct eth_device *dev = NULL;
618 struct mii_dev *mdiodev;
620 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
622 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
627 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
629 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
633 memset(dev, 0, sizeof(struct eth_device));
634 memset(eth, 0, sizeof(struct sh_eth_dev));
636 eth->port = CONFIG_SH_ETHER_USE_PORT;
637 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
638 eth->port_info[eth->port].iobase =
639 (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
641 dev->priv = (void *)eth;
643 dev->init = sh_eth_init_legacy;
644 dev->halt = sh_eth_halt_legacy;
645 dev->send = sh_eth_send_legacy;
646 dev->recv = sh_eth_recv_legacy;
647 eth->port_info[eth->port].dev = dev;
649 strcpy(dev->name, SHETHER_NAME);
651 /* Register Device to EtherNet subsystem */
654 bb_miiphy_buses[0].priv = eth;
655 mdiodev = mdio_alloc();
658 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
659 mdiodev->read = bb_miiphy_read;
660 mdiodev->write = bb_miiphy_write;
662 ret = mdio_register(mdiodev);
666 if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
667 puts("Please set MAC address\n");
678 printf(SHETHER_NAME ": Failed\n");
682 #else /* CONFIG_DM_ETH */
684 struct sh_ether_priv {
685 struct sh_eth_dev shdev;
690 struct gpio_desc reset_gpio;
693 static int sh_ether_send(struct udevice *dev, void *packet, int len)
695 struct sh_ether_priv *priv = dev_get_priv(dev);
696 struct sh_eth_dev *eth = &priv->shdev;
698 return sh_eth_send_common(eth, packet, len);
701 static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
703 struct sh_ether_priv *priv = dev_get_priv(dev);
704 struct sh_eth_dev *eth = &priv->shdev;
705 struct sh_eth_info *port_info = ð->port_info[eth->port];
706 uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
709 len = sh_eth_recv_start(eth);
711 invalidate_cache(packet, len);
718 /* Restart the receiver if disabled */
719 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
720 sh_eth_write(port_info, EDRRR_R, EDRRR);
726 static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
728 struct sh_ether_priv *priv = dev_get_priv(dev);
729 struct sh_eth_dev *eth = &priv->shdev;
730 struct sh_eth_info *port_info = ð->port_info[eth->port];
732 sh_eth_recv_finish(eth);
734 /* Restart the receiver if disabled */
735 if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
736 sh_eth_write(port_info, EDRRR_R, EDRRR);
741 static int sh_ether_write_hwaddr(struct udevice *dev)
743 struct sh_ether_priv *priv = dev_get_priv(dev);
744 struct sh_eth_dev *eth = &priv->shdev;
745 struct sh_eth_info *port_info = ð->port_info[eth->port];
746 struct eth_pdata *pdata = dev_get_platdata(dev);
748 sh_eth_write_hwaddr(port_info, pdata->enetaddr);
753 static int sh_eth_phy_config(struct udevice *dev)
755 struct sh_ether_priv *priv = dev_get_priv(dev);
756 struct eth_pdata *pdata = dev_get_platdata(dev);
757 struct sh_eth_dev *eth = &priv->shdev;
759 struct sh_eth_info *port_info = ð->port_info[eth->port];
760 struct phy_device *phydev;
761 int mask = 0xffffffff;
763 phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
767 phy_connect_dev(phydev, dev);
769 port_info->phydev = phydev;
775 static int sh_ether_start(struct udevice *dev)
777 struct sh_ether_priv *priv = dev_get_priv(dev);
778 struct eth_pdata *pdata = dev_get_platdata(dev);
779 struct sh_eth_dev *eth = &priv->shdev;
782 ret = sh_eth_init_common(eth, pdata->enetaddr);
786 ret = sh_eth_start_common(eth);
793 sh_eth_tx_desc_free(eth);
794 sh_eth_rx_desc_free(eth);
798 static void sh_ether_stop(struct udevice *dev)
800 struct sh_ether_priv *priv = dev_get_priv(dev);
801 struct sh_eth_dev *eth = &priv->shdev;
802 struct sh_eth_info *port_info = ð->port_info[eth->port];
804 phy_shutdown(port_info->phydev);
805 sh_eth_stop(&priv->shdev);
808 static int sh_ether_probe(struct udevice *udev)
810 struct eth_pdata *pdata = dev_get_platdata(udev);
811 struct sh_ether_priv *priv = dev_get_priv(udev);
812 struct sh_eth_dev *eth = &priv->shdev;
813 struct ofnode_phandle_args phandle_args;
814 struct mii_dev *mdiodev;
817 priv->iobase = pdata->iobase;
819 #if CONFIG_IS_ENABLED(CLK)
820 ret = clk_get_by_index(udev, 0, &priv->clk);
825 ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
827 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
828 &priv->reset_gpio, GPIOD_IS_OUT);
831 if (!dm_gpio_is_valid(&priv->reset_gpio)) {
832 gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
836 mdiodev = mdio_alloc();
842 mdiodev->read = bb_miiphy_read;
843 mdiodev->write = bb_miiphy_write;
844 bb_miiphy_buses[0].priv = eth;
845 snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
847 ret = mdio_register(mdiodev);
849 goto err_mdio_register;
851 priv->bus = miiphy_get_dev_by_name(udev->name);
853 eth->port = CONFIG_SH_ETHER_USE_PORT;
854 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
855 eth->port_info[eth->port].iobase =
856 (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
858 #if CONFIG_IS_ENABLED(CLK)
859 ret = clk_enable(&priv->clk);
861 goto err_mdio_register;
864 ret = sh_eth_init_common(eth, pdata->enetaddr);
868 ret = sh_eth_phy_config(udev);
870 printf(SHETHER_NAME ": phy config timeout\n");
877 #if CONFIG_IS_ENABLED(CLK)
878 clk_disable(&priv->clk);
885 static int sh_ether_remove(struct udevice *udev)
887 struct sh_ether_priv *priv = dev_get_priv(udev);
888 struct sh_eth_dev *eth = &priv->shdev;
889 struct sh_eth_info *port_info = ð->port_info[eth->port];
891 #if CONFIG_IS_ENABLED(CLK)
892 clk_disable(&priv->clk);
894 free(port_info->phydev);
895 mdio_unregister(priv->bus);
896 mdio_free(priv->bus);
898 if (dm_gpio_is_valid(&priv->reset_gpio))
899 dm_gpio_free(udev, &priv->reset_gpio);
904 static const struct eth_ops sh_ether_ops = {
905 .start = sh_ether_start,
906 .send = sh_ether_send,
907 .recv = sh_ether_recv,
908 .free_pkt = sh_ether_free_pkt,
909 .stop = sh_ether_stop,
910 .write_hwaddr = sh_ether_write_hwaddr,
913 int sh_ether_ofdata_to_platdata(struct udevice *dev)
915 struct eth_pdata *pdata = dev_get_platdata(dev);
916 const char *phy_mode;
920 pdata->iobase = devfdt_get_addr(dev);
921 pdata->phy_interface = -1;
922 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
925 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
926 if (pdata->phy_interface == -1) {
927 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
931 pdata->max_speed = 1000;
932 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
934 pdata->max_speed = fdt32_to_cpu(*cell);
936 sprintf(bb_miiphy_buses[0].name, dev->name);
941 static const struct udevice_id sh_ether_ids[] = {
942 { .compatible = "renesas,ether-r7s72100" },
943 { .compatible = "renesas,ether-r8a7790" },
944 { .compatible = "renesas,ether-r8a7791" },
945 { .compatible = "renesas,ether-r8a7793" },
946 { .compatible = "renesas,ether-r8a7794" },
947 { .compatible = "renesas,gether-r8a77980" },
951 U_BOOT_DRIVER(eth_sh_ether) = {
954 .of_match = sh_ether_ids,
955 .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
956 .probe = sh_ether_probe,
957 .remove = sh_ether_remove,
958 .ops = &sh_ether_ops,
959 .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
960 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
961 .flags = DM_FLAG_ALLOC_PRIV_DMA,
965 /******* for bb_miiphy *******/
966 static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
971 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
973 struct sh_eth_dev *eth = bus->priv;
974 struct sh_eth_info *port_info = ð->port_info[eth->port];
976 sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
981 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
983 struct sh_eth_dev *eth = bus->priv;
984 struct sh_eth_info *port_info = ð->port_info[eth->port];
986 sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
991 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
993 struct sh_eth_dev *eth = bus->priv;
994 struct sh_eth_info *port_info = ð->port_info[eth->port];
997 sh_eth_write(port_info,
998 sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
1000 sh_eth_write(port_info,
1001 sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
1006 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
1008 struct sh_eth_dev *eth = bus->priv;
1009 struct sh_eth_info *port_info = ð->port_info[eth->port];
1011 *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
1016 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
1018 struct sh_eth_dev *eth = bus->priv;
1019 struct sh_eth_info *port_info = ð->port_info[eth->port];
1022 sh_eth_write(port_info,
1023 sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
1025 sh_eth_write(port_info,
1026 sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
1031 static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
1038 struct bb_miiphy_bus bb_miiphy_buses[] = {
1041 .init = sh_eth_bb_init,
1042 .mdio_active = sh_eth_bb_mdio_active,
1043 .mdio_tristate = sh_eth_bb_mdio_tristate,
1044 .set_mdio = sh_eth_bb_set_mdio,
1045 .get_mdio = sh_eth_bb_get_mdio,
1046 .set_mdc = sh_eth_bb_set_mdc,
1047 .delay = sh_eth_bb_delay,
1051 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);