1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2009 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
13 #include <linux/timer.h>
14 #include <linux/delay.h>
20 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \
24 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \
25 (1 << LOOPBACK_PMAPMD) | \
26 (1 << LOOPBACK_PHYXS_WS))
28 /****************************************************************************/
29 /* Quake-specific MDIO registers */
30 #define MDIO_QUAKE_LED0_REG (0xD006)
33 #define PCS_FW_HEARTBEAT_REG 0xd7ee
34 #define PCS_FW_HEARTB_LBN 0
35 #define PCS_FW_HEARTB_WIDTH 8
36 #define PCS_FW_PRODUCT_CODE_1 0xd7f0
37 #define PCS_FW_VERSION_1 0xd7f3
38 #define PCS_FW_BUILD_1 0xd7f6
39 #define PCS_UC8051_STATUS_REG 0xd7fd
40 #define PCS_UC_STATUS_LBN 0
41 #define PCS_UC_STATUS_WIDTH 8
42 #define PCS_UC_STATUS_FW_SAVE 0x20
43 #define PMA_PMD_FTX_CTRL2_REG 0xc309
44 #define PMA_PMD_FTX_STATIC_LBN 13
45 #define PMA_PMD_VEND1_REG 0xc001
46 #define PMA_PMD_VEND1_LBTXD_LBN 15
47 #define PCS_VEND1_REG 0xc000
48 #define PCS_VEND1_LBTXD_LBN 5
50 void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
52 int addr = MDIO_QUAKE_LED0_REG + led;
53 efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
56 struct qt202x_phy_data {
57 enum efx_phy_mode phy_mode;
58 bool bug17190_in_bad_state;
59 unsigned long bug17190_timer;
63 #define QT2022C2_MAX_RESET_TIME 500
64 #define QT2022C2_RESET_WAIT 10
66 #define BUG17190_INTERVAL (2 * HZ)
68 static int qt2025c_wait_reset(struct efx_nic *efx)
70 unsigned long timeout = jiffies + 10 * HZ;
71 int reg, old_counter = 0;
73 /* Wait for firmware heartbeat to start */
76 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
79 counter = ((reg >> PCS_FW_HEARTB_LBN) &
80 ((1 << PCS_FW_HEARTB_WIDTH) - 1));
82 old_counter = counter;
83 else if (counter != old_counter)
85 if (time_after(jiffies, timeout))
90 /* Wait for firmware status to look good */
92 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
96 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
97 PCS_UC_STATUS_FW_SAVE)
99 if (time_after(jiffies, timeout))
107 static void qt2025c_firmware_id(struct efx_nic *efx)
109 struct qt202x_phy_data *phy_data = efx->phy_data;
113 for (i = 0; i < sizeof(firmware_id); i++)
114 firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
115 PCS_FW_PRODUCT_CODE_1 + i);
116 EFX_INFO(efx, "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
117 (firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
118 firmware_id[3] >> 4, firmware_id[3] & 0xf,
119 firmware_id[4], firmware_id[5],
120 firmware_id[6], firmware_id[7], firmware_id[8]);
121 phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
122 ((firmware_id[3] & 0x0f) << 16) |
123 (firmware_id[4] << 8) | firmware_id[5];
126 static void qt2025c_bug17190_workaround(struct efx_nic *efx)
128 struct qt202x_phy_data *phy_data = efx->phy_data;
130 /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
131 * layers up, but PCS down (no block_lock). If we notice this state
132 * persisting for a couple of seconds, we switch PMA/PMD loopback
133 * briefly on and then off again, which is normally sufficient to
136 if (efx->link_state.up ||
137 !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
138 phy_data->bug17190_in_bad_state = false;
142 if (!phy_data->bug17190_in_bad_state) {
143 phy_data->bug17190_in_bad_state = true;
144 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
148 if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
149 EFX_LOG(efx, "bashing QT2025C PMA/PMD\n");
150 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
151 MDIO_PMA_CTRL1_LOOPBACK, true);
153 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
154 MDIO_PMA_CTRL1_LOOPBACK, false);
155 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
159 static int qt2025c_select_phy_mode(struct efx_nic *efx)
161 struct qt202x_phy_data *phy_data = efx->phy_data;
162 struct falcon_board *board = falcon_board(efx);
164 uint16_t phy_op_mode;
166 /* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
167 * Self-Configure mode. Don't attempt any switching if we encounter
169 if (phy_data->firmware_ver < 0x02000100)
172 /* In general we will get optimal behaviour in "SFP+ Self-Configure"
173 * mode; however, that powers down most of the PHY when no module is
174 * present, so we must use a different mode (any fixed mode will do)
175 * to be sure that loopbacks will work. */
176 phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
178 /* Only change mode if really necessary */
179 reg = efx_mdio_read(efx, 1, 0xc319);
180 if ((reg & 0x0038) == phy_op_mode)
182 EFX_LOG(efx, "Switching PHY to mode 0x%04x\n", phy_op_mode);
184 /* This sequence replicates the register writes configured in the boot
185 * EEPROM (including the differences between board revisions), except
186 * that the operating mode is changed, and the PHY is prevented from
187 * unnecessarily reloading the main firmware image again. */
188 efx_mdio_write(efx, 1, 0xc300, 0x0000);
189 /* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
190 * STOPs onto the firmware/module I2C bus to reset it, varies across
191 * board revisions, as the bus is connected to different GPIO/LED
192 * outputs on the PHY.) */
193 if (board->major == 0 && board->minor < 2) {
194 efx_mdio_write(efx, 1, 0xc303, 0x4498);
195 for (i = 0; i < 9; i++) {
196 efx_mdio_write(efx, 1, 0xc303, 0x4488);
197 efx_mdio_write(efx, 1, 0xc303, 0x4480);
198 efx_mdio_write(efx, 1, 0xc303, 0x4490);
199 efx_mdio_write(efx, 1, 0xc303, 0x4498);
202 efx_mdio_write(efx, 1, 0xc303, 0x0920);
203 efx_mdio_write(efx, 1, 0xd008, 0x0004);
204 for (i = 0; i < 9; i++) {
205 efx_mdio_write(efx, 1, 0xc303, 0x0900);
206 efx_mdio_write(efx, 1, 0xd008, 0x0005);
207 efx_mdio_write(efx, 1, 0xc303, 0x0920);
208 efx_mdio_write(efx, 1, 0xd008, 0x0004);
210 efx_mdio_write(efx, 1, 0xc303, 0x4900);
212 efx_mdio_write(efx, 1, 0xc303, 0x4900);
213 efx_mdio_write(efx, 1, 0xc302, 0x0004);
214 efx_mdio_write(efx, 1, 0xc316, 0x0013);
215 efx_mdio_write(efx, 1, 0xc318, 0x0054);
216 efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
217 efx_mdio_write(efx, 1, 0xc31a, 0x0098);
218 efx_mdio_write(efx, 3, 0x0026, 0x0e00);
219 efx_mdio_write(efx, 3, 0x0027, 0x0013);
220 efx_mdio_write(efx, 3, 0x0028, 0xa528);
221 efx_mdio_write(efx, 1, 0xd006, 0x000a);
222 efx_mdio_write(efx, 1, 0xd007, 0x0009);
223 efx_mdio_write(efx, 1, 0xd008, 0x0004);
224 /* This additional write is not present in the boot EEPROM. It
225 * prevents the PHY's internal boot ROM doing another pointless (and
226 * slow) reload of the firmware image (the microcontroller's code
227 * memory is not affected by the microcontroller reset). */
228 efx_mdio_write(efx, 1, 0xc317, 0x00ff);
229 efx_mdio_write(efx, 1, 0xc300, 0x0002);
232 /* Restart microcontroller execution from RAM */
233 efx_mdio_write(efx, 3, 0xe854, 0x00c0);
234 efx_mdio_write(efx, 3, 0xe854, 0x0040);
237 /* Wait for the microcontroller to be ready again */
238 rc = qt2025c_wait_reset(efx);
240 EFX_ERR(efx, "PHY microcontroller reset during mode switch "
248 static int qt202x_reset_phy(struct efx_nic *efx)
252 if (efx->phy_type == PHY_TYPE_QT2025C) {
253 /* Wait for the reset triggered by falcon_reset_hw()
255 rc = qt2025c_wait_reset(efx);
259 /* Reset the PHYXS MMD. This is documented as doing
260 * a complete soft reset. */
261 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
262 QT2022C2_MAX_RESET_TIME /
264 QT2022C2_RESET_WAIT);
269 /* Wait 250ms for the PHY to complete bootup */
272 /* Check that all the MMDs we expect are present and responding. We
273 * expect faults on some if the link is down, but not on the PHY XS */
274 rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS);
278 falcon_board(efx)->type->init_phy(efx);
283 EFX_ERR(efx, "PHY reset timed out\n");
287 static int qt202x_phy_probe(struct efx_nic *efx)
289 struct qt202x_phy_data *phy_data;
291 phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
294 efx->phy_data = phy_data;
295 phy_data->phy_mode = efx->phy_mode;
296 phy_data->bug17190_in_bad_state = false;
297 phy_data->bug17190_timer = 0;
299 efx->mdio.mmds = QT202X_REQUIRED_DEVS;
300 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
301 efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
305 static int qt202x_phy_init(struct efx_nic *efx)
310 rc = qt202x_reset_phy(efx);
312 EFX_ERR(efx, "PHY init failed\n");
316 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
317 EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
318 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
319 efx_mdio_id_rev(devid));
321 if (efx->phy_type == PHY_TYPE_QT2025C)
322 qt2025c_firmware_id(efx);
327 static int qt202x_link_ok(struct efx_nic *efx)
329 return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
332 static bool qt202x_phy_poll(struct efx_nic *efx)
334 bool was_up = efx->link_state.up;
336 efx->link_state.up = qt202x_link_ok(efx);
337 efx->link_state.speed = 10000;
338 efx->link_state.fd = true;
339 efx->link_state.fc = efx->wanted_fc;
341 if (efx->phy_type == PHY_TYPE_QT2025C)
342 qt2025c_bug17190_workaround(efx);
344 return efx->link_state.up != was_up;
347 static int qt202x_phy_reconfigure(struct efx_nic *efx)
349 struct qt202x_phy_data *phy_data = efx->phy_data;
351 if (efx->phy_type == PHY_TYPE_QT2025C) {
352 int rc = qt2025c_select_phy_mode(efx);
356 /* There are several different register bits which can
357 * disable TX (and save power) on direct-attach cables
358 * or optical transceivers, varying somewhat between
359 * firmware versions. Only 'static mode' appears to
360 * cover everything. */
362 &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
363 PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
364 efx->phy_mode & PHY_MODE_TX_DISABLED ||
365 efx->phy_mode & PHY_MODE_LOW_POWER ||
366 efx->loopback_mode == LOOPBACK_PCS ||
367 efx->loopback_mode == LOOPBACK_PMAPMD);
369 /* Reset the PHY when moving from tx off to tx on */
370 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
371 (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
372 qt202x_reset_phy(efx);
374 efx_mdio_transmit_disable(efx);
377 efx_mdio_phy_reconfigure(efx);
379 phy_data->phy_mode = efx->phy_mode;
384 static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
386 mdio45_ethtool_gset(&efx->mdio, ecmd);
389 static void qt202x_phy_remove(struct efx_nic *efx)
391 /* Free the context block */
392 kfree(efx->phy_data);
393 efx->phy_data = NULL;
396 struct efx_phy_operations falcon_qt202x_phy_ops = {
397 .probe = qt202x_phy_probe,
398 .init = qt202x_phy_init,
399 .reconfigure = qt202x_phy_reconfigure,
400 .poll = qt202x_phy_poll,
401 .fini = efx_port_dummy_op_void,
402 .remove = qt202x_phy_remove,
403 .get_settings = qt202x_phy_get_settings,
404 .set_settings = efx_mdio_set_settings,