drivers/net/sfc/nic.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2011 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include "net_driver.h"
  17 #include "bitfield.h"
  18 #include "efx.h"
  19 #include "nic.h"
  20 #include "regs.h"
  21 #include "io.h"
  22 #include "workarounds.h"
  23
  24 /**************************************************************************
  25  *
  26  * Configurable values
  27  *
  28  **************************************************************************
  29  */
  30
  31 /* This is set to 16 for a good reason.  In summary, if larger than
  32  * 16, the descriptor cache holds more than a default socket
  33  * buffer's worth of packets (for UDP we can only have at most one
  34  * socket buffer's worth outstanding).  This combined with the fact
  35  * that we only get 1 TX event per descriptor cache means the NIC
  36  * goes idle.
  37  */
  38 #define TX_DC_ENTRIES 16
  39 #define TX_DC_ENTRIES_ORDER 1
  40
  41 #define RX_DC_ENTRIES 64
  42 #define RX_DC_ENTRIES_ORDER 3
  43
  44 /* RX FIFO XOFF watermark
  45  *
  46  * When the amount of the RX FIFO increases used increases past this
  47  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  48  * This also has an effect on RX/TX arbitration
  49  */
  50 int efx_nic_rx_xoff_thresh = -1;
  51 module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644);
  52 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  53
  54 /* RX FIFO XON watermark
  55  *
  56  * When the amount of the RX FIFO used decreases below this
  57  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  58  * This also has an effect on RX/TX arbitration
  59  */
  60 int efx_nic_rx_xon_thresh = -1;
  61 module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644);
  62 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  63
  64 /* If EFX_MAX_INT_ERRORS internal errors occur within
  65  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  66  * disable it.
  67  */
  68 #define EFX_INT_ERROR_EXPIRE 3600
  69 #define EFX_MAX_INT_ERRORS 5
  70
  71 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
  72  */
  73 #define EFX_FLUSH_INTERVAL 10
  74 #define EFX_FLUSH_POLL_COUNT 100
  75
  76 /* Size and alignment of special buffers (4KB) */
  77 #define EFX_BUF_SIZE 4096
  78
  79 /* Depth of RX flush request fifo */
  80 #define EFX_RX_FLUSH_COUNT 4
  81
  82 /* Generated event code for efx_generate_test_event() */
  83 #define EFX_CHANNEL_MAGIC_TEST(_channel)        \
  84         (0x00010100 + (_channel)->channel)
  85
  86 /* Generated event code for efx_generate_fill_event() */
  87 #define EFX_CHANNEL_MAGIC_FILL(_channel)        \
  88         (0x00010200 + (_channel)->channel)
  89
  90 /**************************************************************************
  91  *
  92  * Solarstorm hardware access
  93  *
  94  **************************************************************************/
  95
  96 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  97                                      unsigned int index)
  98 {
  99         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
 100                         value, index);
 101 }
 102
 103 /* Read the current event from the event queue */
 104 static inline efx_qword_t *efx_event(struct efx_channel *channel,
 105                                      unsigned int index)
 106 {
 107         return ((efx_qword_t *) (channel->eventq.addr)) + index;
 108 }
 109
 110 /* See if an event is present
 111  *
 112  * We check both the high and low dword of the event for all ones.  We
 113  * wrote all ones when we cleared the event, and no valid event can
 114  * have all ones in either its high or low dwords.  This approach is
 115  * robust against reordering.
 116  *
 117  * Note that using a single 64-bit comparison is incorrect; even
 118  * though the CPU read will be atomic, the DMA write may not be.
 119  */
 120 static inline int efx_event_present(efx_qword_t *event)
 121 {
 122         return !(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 123                   EFX_DWORD_IS_ALL_ONES(event->dword[1]));
 124 }
 125
 126 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
 127                                      const efx_oword_t *mask)
 128 {
 129         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
 130                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
 131 }
 132
 133 int efx_nic_test_registers(struct efx_nic *efx,
 134                            const struct efx_nic_register_test *regs,
 135                            size_t n_regs)
 136 {
 137         unsigned address = 0, i, j;
 138         efx_oword_t mask, imask, original, reg, buf;
 139
 140         /* Falcon should be in loopback to isolate the XMAC from the PHY */
 141         WARN_ON(!LOOPBACK_INTERNAL(efx));
 142
 143         for (i = 0; i < n_regs; ++i) {
 144                 address = regs[i].address;
 145                 mask = imask = regs[i].mask;
 146                 EFX_INVERT_OWORD(imask);
 147
 148                 efx_reado(efx, &original, address);
 149
 150                 /* bit sweep on and off */
 151                 for (j = 0; j < 128; j++) {
 152                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 153                                 continue;
 154
 155                         /* Test this testable bit can be set in isolation */
 156                         EFX_AND_OWORD(reg, original, mask);
 157                         EFX_SET_OWORD32(reg, j, j, 1);
 158
 159                         efx_writeo(efx, &reg, address);
 160                         efx_reado(efx, &buf, address);
 161
 162                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 163                                 goto fail;
 164
 165                         /* Test this testable bit can be cleared in isolation */
 166                         EFX_OR_OWORD(reg, original, mask);
 167                         EFX_SET_OWORD32(reg, j, j, 0);
 168
 169                         efx_writeo(efx, &reg, address);
 170                         efx_reado(efx, &buf, address);
 171
 172                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 173                                 goto fail;
 174                 }
 175
 176                 efx_writeo(efx, &original, address);
 177         }
 178
 179         return 0;
 180
 181 fail:
 182         netif_err(efx, hw, efx->net_dev,
 183                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 184                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 185                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 186         return -EIO;
 187 }
 188
 189 /**************************************************************************
 190  *
 191  * Special buffer handling
 192  * Special buffers are used for event queues and the TX and RX
 193  * descriptor rings.
 194  *
 195  *************************************************************************/
 196
 197 /*
 198  * Initialise a special buffer
 199  *
 200  * This will define a buffer (previously allocated via
 201  * efx_alloc_special_buffer()) in the buffer table, allowing
 202  * it to be used for event queues, descriptor rings etc.
 203  */
 204 static void
 205 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 206 {
 207         efx_qword_t buf_desc;
 208         int index;
 209         dma_addr_t dma_addr;
 210         int i;
 211
 212         EFX_BUG_ON_PARANOID(!buffer->addr);
 213
 214         /* Write buffer descriptors to NIC */
 215         for (i = 0; i < buffer->entries; i++) {
 216                 index = buffer->index + i;
 217                 dma_addr = buffer->dma_addr + (i * 4096);
 218                 netif_dbg(efx, probe, efx->net_dev,
 219                           "mapping special buffer %d at %llx\n",
 220                           index, (unsigned long long)dma_addr);
 221                 EFX_POPULATE_QWORD_3(buf_desc,
 222                                      FRF_AZ_BUF_ADR_REGION, 0,
 223                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 224                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 225                 efx_write_buf_tbl(efx, &buf_desc, index);
 226         }
 227 }
 228
 229 /* Unmaps a buffer and clears the buffer table entries */
 230 static void
 231 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 232 {
 233         efx_oword_t buf_tbl_upd;
 234         unsigned int start = buffer->index;
 235         unsigned int end = (buffer->index + buffer->entries - 1);
 236
 237         if (!buffer->entries)
 238                 return;
 239
 240         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
 241                   buffer->index, buffer->index + buffer->entries - 1);
 242
 243         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 244                              FRF_AZ_BUF_UPD_CMD, 0,
 245                              FRF_AZ_BUF_CLR_CMD, 1,
 246                              FRF_AZ_BUF_CLR_END_ID, end,
 247                              FRF_AZ_BUF_CLR_START_ID, start);
 248         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 249 }
 250
 251 /*
 252  * Allocate a new special buffer
 253  *
 254  * This allocates memory for a new buffer, clears it and allocates a
 255  * new buffer ID range.  It does not write into the buffer table.
 256  *
 257  * This call will allocate 4KB buffers, since 8KB buffers can't be
 258  * used for event queues and descriptor rings.
 259  */
 260 static int efx_alloc_special_buffer(struct efx_nic *efx,
 261                                     struct efx_special_buffer *buffer,
 262                                     unsigned int len)
 263 {
 264         len = ALIGN(len, EFX_BUF_SIZE);
 265
 266         buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
 267                                           &buffer->dma_addr, GFP_KERNEL);
 268         if (!buffer->addr)
 269                 return -ENOMEM;
 270         buffer->len = len;
 271         buffer->entries = len / EFX_BUF_SIZE;
 272         BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
 273
 274         /* All zeros is a potentially valid event so memset to 0xff */
 275         memset(buffer->addr, 0xff, len);
 276
 277         /* Select new buffer ID */
 278         buffer->index = efx->next_buffer_table;
 279         efx->next_buffer_table += buffer->entries;
 280
 281         netif_dbg(efx, probe, efx->net_dev,
 282                   "allocating special buffers %d-%d at %llx+%x "
 283                   "(virt %p phys %llx)\n", buffer->index,
 284                   buffer->index + buffer->entries - 1,
 285                   (u64)buffer->dma_addr, len,
 286                   buffer->addr, (u64)virt_to_phys(buffer->addr));
 287
 288         return 0;
 289 }
 290
 291 static void
 292 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 293 {
 294         if (!buffer->addr)
 295                 return;
 296
 297         netif_dbg(efx, hw, efx->net_dev,
 298                   "deallocating special buffers %d-%d at %llx+%x "
 299                   "(virt %p phys %llx)\n", buffer->index,
 300                   buffer->index + buffer->entries - 1,
 301                   (u64)buffer->dma_addr, buffer->len,
 302                   buffer->addr, (u64)virt_to_phys(buffer->addr));
 303
 304         dma_free_coherent(&efx->pci_dev->dev, buffer->len, buffer->addr,
 305                           buffer->dma_addr);
 306         buffer->addr = NULL;
 307         buffer->entries = 0;
 308 }
 309
 310 /**************************************************************************
 311  *
 312  * Generic buffer handling
 313  * These buffers are used for interrupt status and MAC stats
 314  *
 315  **************************************************************************/
 316
 317 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
 318                          unsigned int len)
 319 {
 320         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 321                                             &buffer->dma_addr);
 322         if (!buffer->addr)
 323                 return -ENOMEM;
 324         buffer->len = len;
 325         memset(buffer->addr, 0, len);
 326         return 0;
 327 }
 328
 329 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 330 {
 331         if (buffer->addr) {
 332                 pci_free_consistent(efx->pci_dev, buffer->len,
 333                                     buffer->addr, buffer->dma_addr);
 334                 buffer->addr = NULL;
 335         }
 336 }
 337
 338 /**************************************************************************
 339  *
 340  * TX path
 341  *
 342  **************************************************************************/
 343
 344 /* Returns a pointer to the specified transmit descriptor in the TX
 345  * descriptor queue belonging to the specified channel.
 346  */
 347 static inline efx_qword_t *
 348 efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
 349 {
 350         return ((efx_qword_t *) (tx_queue->txd.addr)) + index;
 351 }
 352
 353 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 354 static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
 355 {
 356         unsigned write_ptr;
 357         efx_dword_t reg;
 358
 359         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 360         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 361         efx_writed_page(tx_queue->efx, &reg,
 362                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 363 }
 364
 365 /* Write pointer and first descriptor for TX descriptor ring */
 366 static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue,
 367                                     const efx_qword_t *txd)
 368 {
 369         unsigned write_ptr;
 370         efx_oword_t reg;
 371
 372         BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
 373         BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
 374
 375         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 376         EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
 377                              FRF_AZ_TX_DESC_WPTR, write_ptr);
 378         reg.qword[0] = *txd;
 379         efx_writeo_page(tx_queue->efx, &reg,
 380                         FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
 381 }
 382
 383 static inline bool
 384 efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count)
 385 {
 386         unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
 387
 388         if (empty_read_count == 0)
 389                 return false;
 390
 391         tx_queue->empty_read_count = 0;
 392         return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
 393 }
 394
 395 /* For each entry inserted into the software descriptor ring, create a
 396  * descriptor in the hardware TX descriptor ring (in host memory), and
 397  * write a doorbell.
 398  */
 399 void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
 400 {
 401
 402         struct efx_tx_buffer *buffer;
 403         efx_qword_t *txd;
 404         unsigned write_ptr;
 405         unsigned old_write_count = tx_queue->write_count;
 406
 407         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 408
 409         do {
 410                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 411                 buffer = &tx_queue->buffer[write_ptr];
 412                 txd = efx_tx_desc(tx_queue, write_ptr);
 413                 ++tx_queue->write_count;
 414
 415                 /* Create TX descriptor ring entry */
 416                 EFX_POPULATE_QWORD_4(*txd,
 417                                      FSF_AZ_TX_KER_CONT, buffer->continuation,
 418                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 419                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 420                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 421         } while (tx_queue->write_count != tx_queue->insert_count);
 422
 423         wmb(); /* Ensure descriptors are written before they are fetched */
 424
 425         if (efx_may_push_tx_desc(tx_queue, old_write_count)) {
 426                 txd = efx_tx_desc(tx_queue,
 427                                   old_write_count & tx_queue->ptr_mask);
 428                 efx_push_tx_desc(tx_queue, txd);
 429                 ++tx_queue->pushes;
 430         } else {
 431                 efx_notify_tx_desc(tx_queue);
 432         }
 433 }
 434
 435 /* Allocate hardware resources for a TX queue */
 436 int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
 437 {
 438         struct efx_nic *efx = tx_queue->efx;
 439         unsigned entries;
 440
 441         entries = tx_queue->ptr_mask + 1;
 442         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 443                                         entries * sizeof(efx_qword_t));
 444 }
 445
 446 void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
 447 {
 448         struct efx_nic *efx = tx_queue->efx;
 449         efx_oword_t reg;
 450
 451         tx_queue->flushed = FLUSH_NONE;
 452
 453         /* Pin TX descriptor ring */
 454         efx_init_special_buffer(efx, &tx_queue->txd);
 455
 456         /* Push TX descriptor ring to card */
 457         EFX_POPULATE_OWORD_10(reg,
 458                               FRF_AZ_TX_DESCQ_EN, 1,
 459                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 460                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 461                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 462                               FRF_AZ_TX_DESCQ_EVQ_ID,
 463                               tx_queue->channel->channel,
 464                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 465                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 466                               FRF_AZ_TX_DESCQ_SIZE,
 467                               __ffs(tx_queue->txd.entries),
 468                               FRF_AZ_TX_DESCQ_TYPE, 0,
 469                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 470
 471         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 472                 int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
 473                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 474                 EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS,
 475                                     !csum);
 476         }
 477
 478         efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
 479                          tx_queue->queue);
 480
 481         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
 482                 /* Only 128 bits in this register */
 483                 BUILD_BUG_ON(EFX_MAX_TX_QUEUES > 128);
 484
 485                 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
 486                 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
 487                         clear_bit_le(tx_queue->queue, (void *)&reg);
 488                 else
 489                         set_bit_le(tx_queue->queue, (void *)&reg);
 490                 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
 491         }
 492
 493         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
 494                 EFX_POPULATE_OWORD_1(reg,
 495                                      FRF_BZ_TX_PACE,
 496                                      (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
 497                                      FFE_BZ_TX_PACE_OFF :
 498                                      FFE_BZ_TX_PACE_RESERVED);
 499                 efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL,
 500                                  tx_queue->queue);
 501         }
 502 }
 503
 504 static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
 505 {
 506         struct efx_nic *efx = tx_queue->efx;
 507         efx_oword_t tx_flush_descq;
 508
 509         tx_queue->flushed = FLUSH_PENDING;
 510
 511         /* Post a flush command */
 512         EFX_POPULATE_OWORD_2(tx_flush_descq,
 513                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 514                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 515         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 516 }
 517
 518 void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
 519 {
 520         struct efx_nic *efx = tx_queue->efx;
 521         efx_oword_t tx_desc_ptr;
 522
 523         /* The queue should have been flushed */
 524         WARN_ON(tx_queue->flushed != FLUSH_DONE);
 525
 526         /* Remove TX descriptor ring from card */
 527         EFX_ZERO_OWORD(tx_desc_ptr);
 528         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 529                          tx_queue->queue);
 530
 531         /* Unpin TX descriptor ring */
 532         efx_fini_special_buffer(efx, &tx_queue->txd);
 533 }
 534
 535 /* Free buffers backing TX queue */
 536 void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
 537 {
 538         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 539 }
 540
 541 /**************************************************************************
 542  *
 543  * RX path
 544  *
 545  **************************************************************************/
 546
 547 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 548 static inline efx_qword_t *
 549 efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
 550 {
 551         return ((efx_qword_t *) (rx_queue->rxd.addr)) + index;
 552 }
 553
 554 /* This creates an entry in the RX descriptor queue */
 555 static inline void
 556 efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 557 {
 558         struct efx_rx_buffer *rx_buf;
 559         efx_qword_t *rxd;
 560
 561         rxd = efx_rx_desc(rx_queue, index);
 562         rx_buf = efx_rx_buffer(rx_queue, index);
 563         EFX_POPULATE_QWORD_3(*rxd,
 564                              FSF_AZ_RX_KER_BUF_SIZE,
 565                              rx_buf->len -
 566                              rx_queue->efx->type->rx_buffer_padding,
 567                              FSF_AZ_RX_KER_BUF_REGION, 0,
 568                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 569 }
 570
 571 /* This writes to the RX_DESC_WPTR register for the specified receive
 572  * descriptor ring.
 573  */
 574 void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
 575 {
 576         struct efx_nic *efx = rx_queue->efx;
 577         efx_dword_t reg;
 578         unsigned write_ptr;
 579
 580         while (rx_queue->notified_count != rx_queue->added_count) {
 581                 efx_build_rx_desc(
 582                         rx_queue,
 583                         rx_queue->notified_count & rx_queue->ptr_mask);
 584                 ++rx_queue->notified_count;
 585         }
 586
 587         wmb();
 588         write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
 589         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 590         efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
 591                         efx_rx_queue_index(rx_queue));
 592 }
 593
 594 int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
 595 {
 596         struct efx_nic *efx = rx_queue->efx;
 597         unsigned entries;
 598
 599         entries = rx_queue->ptr_mask + 1;
 600         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 601                                         entries * sizeof(efx_qword_t));
 602 }
 603
 604 void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
 605 {
 606         efx_oword_t rx_desc_ptr;
 607         struct efx_nic *efx = rx_queue->efx;
 608         bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
 609         bool iscsi_digest_en = is_b0;
 610
 611         netif_dbg(efx, hw, efx->net_dev,
 612                   "RX queue %d ring in special buffers %d-%d\n",
 613                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
 614                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 615
 616         rx_queue->flushed = FLUSH_NONE;
 617
 618         /* Pin RX descriptor ring */
 619         efx_init_special_buffer(efx, &rx_queue->rxd);
 620
 621         /* Push RX descriptor ring to card */
 622         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 623                               FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
 624                               FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
 625                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 626                               FRF_AZ_RX_DESCQ_EVQ_ID,
 627                               efx_rx_queue_channel(rx_queue)->channel,
 628                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 629                               FRF_AZ_RX_DESCQ_LABEL,
 630                               efx_rx_queue_index(rx_queue),
 631                               FRF_AZ_RX_DESCQ_SIZE,
 632                               __ffs(rx_queue->rxd.entries),
 633                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 634                               /* For >=B0 this is scatter so disable */
 635                               FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
 636                               FRF_AZ_RX_DESCQ_EN, 1);
 637         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 638                          efx_rx_queue_index(rx_queue));
 639 }
 640
 641 static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
 642 {
 643         struct efx_nic *efx = rx_queue->efx;
 644         efx_oword_t rx_flush_descq;
 645
 646         rx_queue->flushed = FLUSH_PENDING;
 647
 648         /* Post a flush command */
 649         EFX_POPULATE_OWORD_2(rx_flush_descq,
 650                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 651                              FRF_AZ_RX_FLUSH_DESCQ,
 652                              efx_rx_queue_index(rx_queue));
 653         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 654 }
 655
 656 void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
 657 {
 658         efx_oword_t rx_desc_ptr;
 659         struct efx_nic *efx = rx_queue->efx;
 660
 661         /* The queue should already have been flushed */
 662         WARN_ON(rx_queue->flushed != FLUSH_DONE);
 663
 664         /* Remove RX descriptor ring from card */
 665         EFX_ZERO_OWORD(rx_desc_ptr);
 666         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 667                          efx_rx_queue_index(rx_queue));
 668
 669         /* Unpin RX descriptor ring */
 670         efx_fini_special_buffer(efx, &rx_queue->rxd);
 671 }
 672
 673 /* Free buffers backing RX queue */
 674 void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
 675 {
 676         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 677 }
 678
 679 /**************************************************************************
 680  *
 681  * Event queue processing
 682  * Event queues are processed by per-channel tasklets.
 683  *
 684  **************************************************************************/
 685
 686 /* Update a channel's event queue's read pointer (RPTR) register
 687  *
 688  * This writes the EVQ_RPTR_REG register for the specified channel's
 689  * event queue.
 690  */
 691 void efx_nic_eventq_read_ack(struct efx_channel *channel)
 692 {
 693         efx_dword_t reg;
 694         struct efx_nic *efx = channel->efx;
 695
 696         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
 697         efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 698                          channel->channel);
 699 }
 700
 701 /* Use HW to insert a SW defined event */
 702 static void efx_generate_event(struct efx_channel *channel, efx_qword_t *event)
 703 {
 704         efx_oword_t drv_ev_reg;
 705
 706         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 707                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 708         drv_ev_reg.u32[0] = event->u32[0];
 709         drv_ev_reg.u32[1] = event->u32[1];
 710         drv_ev_reg.u32[2] = 0;
 711         drv_ev_reg.u32[3] = 0;
 712         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
 713         efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
 714 }
 715
 716 /* Handle a transmit completion event
 717  *
 718  * The NIC batches TX completion events; the message we receive is of
 719  * the form "complete all TX events up to this index".
 720  */
 721 static int
 722 efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 723 {
 724         unsigned int tx_ev_desc_ptr;
 725         unsigned int tx_ev_q_label;
 726         struct efx_tx_queue *tx_queue;
 727         struct efx_nic *efx = channel->efx;
 728         int tx_packets = 0;
 729
 730         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 731                 /* Transmit completion */
 732                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 733                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 734                 tx_queue = efx_channel_get_tx_queue(
 735                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 736                 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
 737                               tx_queue->ptr_mask);
 738                 channel->irq_mod_score += tx_packets;
 739                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 740         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 741                 /* Rewrite the FIFO write pointer */
 742                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 743                 tx_queue = efx_channel_get_tx_queue(
 744                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 745
 746                 if (efx_dev_registered(efx))
 747                         netif_tx_lock(efx->net_dev);
 748                 efx_notify_tx_desc(tx_queue);
 749                 if (efx_dev_registered(efx))
 750                         netif_tx_unlock(efx->net_dev);
 751         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
 752                    EFX_WORKAROUND_10727(efx)) {
 753                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 754         } else {
 755                 netif_err(efx, tx_err, efx->net_dev,
 756                           "channel %d unexpected TX event "
 757                           EFX_QWORD_FMT"\n", channel->channel,
 758                           EFX_QWORD_VAL(*event));
 759         }
 760
 761         return tx_packets;
 762 }
 763
 764 /* Detect errors included in the rx_evt_pkt_ok bit. */
 765 static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 766                                  const efx_qword_t *event,
 767                                  bool *rx_ev_pkt_ok,
 768                                  bool *discard)
 769 {
 770         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 771         struct efx_nic *efx = rx_queue->efx;
 772         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 773         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 774         bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 775         bool rx_ev_other_err, rx_ev_pause_frm;
 776         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 777         unsigned rx_ev_pkt_type;
 778
 779         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 780         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 781         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 782         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 783         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 784                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 785         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 786                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 787         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 788                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 789         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 790         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 791         rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
 792                           0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
 793         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 794
 795         /* Every error apart from tobe_disc and pause_frm */
 796         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 797                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 798                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 799
 800         /* Count errors that are not in MAC stats.  Ignore expected
 801          * checksum errors during self-test. */
 802         if (rx_ev_frm_trunc)
 803                 ++channel->n_rx_frm_trunc;
 804         else if (rx_ev_tobe_disc)
 805                 ++channel->n_rx_tobe_disc;
 806         else if (!efx->loopback_selftest) {
 807                 if (rx_ev_ip_hdr_chksum_err)
 808                         ++channel->n_rx_ip_hdr_chksum_err;
 809                 else if (rx_ev_tcp_udp_chksum_err)
 810                         ++channel->n_rx_tcp_udp_chksum_err;
 811         }
 812
 813         /* The frame must be discarded if any of these are true. */
 814         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 815                     rx_ev_tobe_disc | rx_ev_pause_frm);
 816
 817         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 818          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 819          * to a FIFO overflow.
 820          */
 821 #ifdef EFX_ENABLE_DEBUG
 822         if (rx_ev_other_err && net_ratelimit()) {
 823                 netif_dbg(efx, rx_err, efx->net_dev,
 824                           " RX queue %d unexpected RX event "
 825                           EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
 826                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
 827                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 828                           rx_ev_ip_hdr_chksum_err ?
 829                           " [IP_HDR_CHKSUM_ERR]" : "",
 830                           rx_ev_tcp_udp_chksum_err ?
 831                           " [TCP_UDP_CHKSUM_ERR]" : "",
 832                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 833                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 834                           rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 835                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 836                           rx_ev_pause_frm ? " [PAUSE]" : "");
 837         }
 838 #endif
 839 }
 840
 841 /* Handle receive events that are not in-order. */
 842 static void
 843 efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 844 {
 845         struct efx_nic *efx = rx_queue->efx;
 846         unsigned expected, dropped;
 847
 848         expected = rx_queue->removed_count & rx_queue->ptr_mask;
 849         dropped = (index - expected) & rx_queue->ptr_mask;
 850         netif_info(efx, rx_err, efx->net_dev,
 851                    "dropped %d events (index=%d expected=%d)\n",
 852                    dropped, index, expected);
 853
 854         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
 855                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
 856 }
 857
 858 /* Handle a packet received event
 859  *
 860  * The NIC gives a "discard" flag if it's a unicast packet with the
 861  * wrong destination address
 862  * Also "is multicast" and "matches multicast filter" flags can be used to
 863  * discard non-matching multicast packets.
 864  */
 865 static void
 866 efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 867 {
 868         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 869         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 870         unsigned expected_ptr;
 871         bool rx_ev_pkt_ok, discard = false, checksummed;
 872         struct efx_rx_queue *rx_queue;
 873         struct efx_nic *efx = channel->efx;
 874
 875         /* Basic packet information */
 876         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
 877         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
 878         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 879         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
 880         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
 881         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 882                 channel->channel);
 883
 884         rx_queue = efx_channel_get_rx_queue(channel);
 885
 886         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 887         expected_ptr = rx_queue->removed_count & rx_queue->ptr_mask;
 888         if (unlikely(rx_ev_desc_ptr != expected_ptr))
 889                 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
 890
 891         if (likely(rx_ev_pkt_ok)) {
 892                 /* If packet is marked as OK and packet type is TCP/IP or
 893                  * UDP/IP, then we can rely on the hardware checksum.
 894                  */
 895                 checksummed =
 896                         likely(efx->rx_checksum_enabled) &&
 897                         (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
 898                          rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP);
 899         } else {
 900                 efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard);
 901                 checksummed = false;
 902         }
 903
 904         /* Detect multicast packets that didn't match the filter */
 905         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 906         if (rx_ev_mcast_pkt) {
 907                 unsigned int rx_ev_mcast_hash_match =
 908                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
 909
 910                 if (unlikely(!rx_ev_mcast_hash_match)) {
 911                         ++channel->n_rx_mcast_mismatch;
 912                         discard = true;
 913                 }
 914         }
 915
 916         channel->irq_mod_score += 2;
 917
 918         /* Handle received packet */
 919         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
 920                       checksummed, discard);
 921 }
 922
 923 static void
 924 efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
 925 {
 926         struct efx_nic *efx = channel->efx;
 927         unsigned code;
 928
 929         code = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
 930         if (code == EFX_CHANNEL_MAGIC_TEST(channel))
 931                 ++channel->magic_count;
 932         else if (code == EFX_CHANNEL_MAGIC_FILL(channel))
 933                 /* The queue must be empty, so we won't receive any rx
 934                  * events, so efx_process_channel() won't refill the
 935                  * queue. Refill it here */
 936                 efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel));
 937         else
 938                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
 939                           "generated event "EFX_QWORD_FMT"\n",
 940                           channel->channel, EFX_QWORD_VAL(*event));
 941 }
 942
 943 static void
 944 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
 945 {
 946         struct efx_nic *efx = channel->efx;
 947         unsigned int ev_sub_code;
 948         unsigned int ev_sub_data;
 949
 950         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
 951         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
 952
 953         switch (ev_sub_code) {
 954         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
 955                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
 956                            channel->channel, ev_sub_data);
 957                 break;
 958         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
 959                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
 960                            channel->channel, ev_sub_data);
 961                 break;
 962         case FSE_AZ_EVQ_INIT_DONE_EV:
 963                 netif_dbg(efx, hw, efx->net_dev,
 964                           "channel %d EVQ %d initialised\n",
 965                           channel->channel, ev_sub_data);
 966                 break;
 967         case FSE_AZ_SRM_UPD_DONE_EV:
 968                 netif_vdbg(efx, hw, efx->net_dev,
 969                            "channel %d SRAM update done\n", channel->channel);
 970                 break;
 971         case FSE_AZ_WAKE_UP_EV:
 972                 netif_vdbg(efx, hw, efx->net_dev,
 973                            "channel %d RXQ %d wakeup event\n",
 974                            channel->channel, ev_sub_data);
 975                 break;
 976         case FSE_AZ_TIMER_EV:
 977                 netif_vdbg(efx, hw, efx->net_dev,
 978                            "channel %d RX queue %d timer expired\n",
 979                            channel->channel, ev_sub_data);
 980                 break;
 981         case FSE_AA_RX_RECOVER_EV:
 982                 netif_err(efx, rx_err, efx->net_dev,
 983                           "channel %d seen DRIVER RX_RESET event. "
 984                         "Resetting.\n", channel->channel);
 985                 atomic_inc(&efx->rx_reset);
 986                 efx_schedule_reset(efx,
 987                                    EFX_WORKAROUND_6555(efx) ?
 988                                    RESET_TYPE_RX_RECOVERY :
 989                                    RESET_TYPE_DISABLE);
 990                 break;
 991         case FSE_BZ_RX_DSC_ERROR_EV:
 992                 netif_err(efx, rx_err, efx->net_dev,
 993                           "RX DMA Q %d reports descriptor fetch error."
 994                           " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
 995                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
 996                 break;
 997         case FSE_BZ_TX_DSC_ERROR_EV:
 998                 netif_err(efx, tx_err, efx->net_dev,
 999                           "TX DMA Q %d reports descriptor fetch error."
1000                           " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1001                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1002                 break;
1003         default:
1004                 netif_vdbg(efx, hw, efx->net_dev,
1005                            "channel %d unknown driver event code %d "
1006                            "data %04x\n", channel->channel, ev_sub_code,
1007                            ev_sub_data);
1008                 break;
1009         }
1010 }
1011
1012 int efx_nic_process_eventq(struct efx_channel *channel, int budget)
1013 {
1014         struct efx_nic *efx = channel->efx;
1015         unsigned int read_ptr;
1016         efx_qword_t event, *p_event;
1017         int ev_code;
1018         int tx_packets = 0;
1019         int spent = 0;
1020
1021         read_ptr = channel->eventq_read_ptr;
1022
1023         for (;;) {
1024                 p_event = efx_event(channel, read_ptr);
1025                 event = *p_event;
1026
1027                 if (!efx_event_present(&event))
1028                         /* End of events */
1029                         break;
1030
1031                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1032                            "channel %d event is "EFX_QWORD_FMT"\n",
1033                            channel->channel, EFX_QWORD_VAL(event));
1034
1035                 /* Clear this event by marking it all ones */
1036                 EFX_SET_QWORD(*p_event);
1037
1038                 /* Increment read pointer */
1039                 read_ptr = (read_ptr + 1) & channel->eventq_mask;
1040
1041                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1042
1043                 switch (ev_code) {
1044                 case FSE_AZ_EV_CODE_RX_EV:
1045                         efx_handle_rx_event(channel, &event);
1046                         if (++spent == budget)
1047                                 goto out;
1048                         break;
1049                 case FSE_AZ_EV_CODE_TX_EV:
1050                         tx_packets += efx_handle_tx_event(channel, &event);
1051                         if (tx_packets > efx->txq_entries) {
1052                                 spent = budget;
1053                                 goto out;
1054                         }
1055                         break;
1056                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1057                         efx_handle_generated_event(channel, &event);
1058                         break;
1059                 case FSE_AZ_EV_CODE_DRIVER_EV:
1060                         efx_handle_driver_event(channel, &event);
1061                         break;
1062                 case FSE_CZ_EV_CODE_MCDI_EV:
1063                         efx_mcdi_process_event(channel, &event);
1064                         break;
1065                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1066                         if (efx->type->handle_global_event &&
1067                             efx->type->handle_global_event(channel, &event))
1068                                 break;
1069                         /* else fall through */
1070                 default:
1071                         netif_err(channel->efx, hw, channel->efx->net_dev,
1072                                   "channel %d unknown event type %d (data "
1073                                   EFX_QWORD_FMT ")\n", channel->channel,
1074                                   ev_code, EFX_QWORD_VAL(event));
1075                 }
1076         }
1077
1078 out:
1079         channel->eventq_read_ptr = read_ptr;
1080         return spent;
1081 }
1082
1083
1084 /* Allocate buffer table entries for event queue */
1085 int efx_nic_probe_eventq(struct efx_channel *channel)
1086 {
1087         struct efx_nic *efx = channel->efx;
1088         unsigned entries;
1089
1090         entries = channel->eventq_mask + 1;
1091         return efx_alloc_special_buffer(efx, &channel->eventq,
1092                                         entries * sizeof(efx_qword_t));
1093 }
1094
1095 void efx_nic_init_eventq(struct efx_channel *channel)
1096 {
1097         efx_oword_t reg;
1098         struct efx_nic *efx = channel->efx;
1099
1100         netif_dbg(efx, hw, efx->net_dev,
1101                   "channel %d event queue in special buffers %d-%d\n",
1102                   channel->channel, channel->eventq.index,
1103                   channel->eventq.index + channel->eventq.entries - 1);
1104
1105         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
1106                 EFX_POPULATE_OWORD_3(reg,
1107                                      FRF_CZ_TIMER_Q_EN, 1,
1108                                      FRF_CZ_HOST_NOTIFY_MODE, 0,
1109                                      FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1110                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1111         }
1112
1113         /* Pin event queue buffer */
1114         efx_init_special_buffer(efx, &channel->eventq);
1115
1116         /* Fill event queue with all ones (i.e. empty events) */
1117         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1118
1119         /* Push event queue to card */
1120         EFX_POPULATE_OWORD_3(reg,
1121                              FRF_AZ_EVQ_EN, 1,
1122                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1123                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1124         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1125                          channel->channel);
1126
1127         efx->type->push_irq_moderation(channel);
1128 }
1129
1130 void efx_nic_fini_eventq(struct efx_channel *channel)
1131 {
1132         efx_oword_t reg;
1133         struct efx_nic *efx = channel->efx;
1134
1135         /* Remove event queue from card */
1136         EFX_ZERO_OWORD(reg);
1137         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1138                          channel->channel);
1139         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1140                 efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1141
1142         /* Unpin event queue */
1143         efx_fini_special_buffer(efx, &channel->eventq);
1144 }
1145
1146 /* Free buffers backing event queue */
1147 void efx_nic_remove_eventq(struct efx_channel *channel)
1148 {
1149         efx_free_special_buffer(channel->efx, &channel->eventq);
1150 }
1151
1152
1153 void efx_nic_generate_test_event(struct efx_channel *channel)
1154 {
1155         unsigned int magic = EFX_CHANNEL_MAGIC_TEST(channel);
1156         efx_qword_t test_event;
1157
1158         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1159                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1160                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1161         efx_generate_event(channel, &test_event);
1162 }
1163
1164 void efx_nic_generate_fill_event(struct efx_channel *channel)
1165 {
1166         unsigned int magic = EFX_CHANNEL_MAGIC_FILL(channel);
1167         efx_qword_t test_event;
1168
1169         EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1170                              FSE_AZ_EV_CODE_DRV_GEN_EV,
1171                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1172         efx_generate_event(channel, &test_event);
1173 }
1174
1175 /**************************************************************************
1176  *
1177  * Flush handling
1178  *
1179  **************************************************************************/
1180
1181
1182 static void efx_poll_flush_events(struct efx_nic *efx)
1183 {
1184         struct efx_channel *channel = efx_get_channel(efx, 0);
1185         struct efx_tx_queue *tx_queue;
1186         struct efx_rx_queue *rx_queue;
1187         unsigned int read_ptr = channel->eventq_read_ptr;
1188         unsigned int end_ptr = (read_ptr - 1) & channel->eventq_mask;
1189
1190         do {
1191                 efx_qword_t *event = efx_event(channel, read_ptr);
1192                 int ev_code, ev_sub_code, ev_queue;
1193                 bool ev_failed;
1194
1195                 if (!efx_event_present(event))
1196                         break;
1197
1198                 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1199                 ev_sub_code = EFX_QWORD_FIELD(*event,
1200                                               FSF_AZ_DRIVER_EV_SUBCODE);
1201                 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1202                     ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1203                         ev_queue = EFX_QWORD_FIELD(*event,
1204                                                    FSF_AZ_DRIVER_EV_SUBDATA);
1205                         if (ev_queue < EFX_TXQ_TYPES * efx->n_tx_channels) {
1206                                 tx_queue = efx_get_tx_queue(
1207                                         efx, ev_queue / EFX_TXQ_TYPES,
1208                                         ev_queue % EFX_TXQ_TYPES);
1209                                 tx_queue->flushed = FLUSH_DONE;
1210                         }
1211                 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1212                            ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1213                         ev_queue = EFX_QWORD_FIELD(
1214                                 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1215                         ev_failed = EFX_QWORD_FIELD(
1216                                 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1217                         if (ev_queue < efx->n_rx_channels) {
1218                                 rx_queue = efx_get_rx_queue(efx, ev_queue);
1219                                 rx_queue->flushed =
1220                                         ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1221                         }
1222                 }
1223
1224                 /* We're about to destroy the queue anyway, so
1225                  * it's ok to throw away every non-flush event */
1226                 EFX_SET_QWORD(*event);
1227
1228                 read_ptr = (read_ptr + 1) & channel->eventq_mask;
1229         } while (read_ptr != end_ptr);
1230
1231         channel->eventq_read_ptr = read_ptr;
1232 }
1233
1234 /* Handle tx and rx flushes at the same time, since they run in
1235  * parallel in the hardware and there's no reason for us to
1236  * serialise them */
1237 int efx_nic_flush_queues(struct efx_nic *efx)
1238 {
1239         struct efx_channel *channel;
1240         struct efx_rx_queue *rx_queue;
1241         struct efx_tx_queue *tx_queue;
1242         int i, tx_pending, rx_pending;
1243
1244         /* If necessary prepare the hardware for flushing */
1245         efx->type->prepare_flush(efx);
1246
1247         /* Flush all tx queues in parallel */
1248         efx_for_each_channel(channel, efx) {
1249                 efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
1250                         if (tx_queue->initialised)
1251                                 efx_flush_tx_queue(tx_queue);
1252                 }
1253         }
1254
1255         /* The hardware supports four concurrent rx flushes, each of which may
1256          * need to be retried if there is an outstanding descriptor fetch */
1257         for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) {
1258                 rx_pending = tx_pending = 0;
1259                 efx_for_each_channel(channel, efx) {
1260                         efx_for_each_channel_rx_queue(rx_queue, channel) {
1261                                 if (rx_queue->flushed == FLUSH_PENDING)
1262                                         ++rx_pending;
1263                         }
1264                 }
1265                 efx_for_each_channel(channel, efx) {
1266                         efx_for_each_channel_rx_queue(rx_queue, channel) {
1267                                 if (rx_pending == EFX_RX_FLUSH_COUNT)
1268                                         break;
1269                                 if (rx_queue->flushed == FLUSH_FAILED ||
1270                                     rx_queue->flushed == FLUSH_NONE) {
1271                                         efx_flush_rx_queue(rx_queue);
1272                                         ++rx_pending;
1273                                 }
1274                         }
1275                         efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
1276                                 if (tx_queue->initialised &&
1277                                     tx_queue->flushed != FLUSH_DONE)
1278                                         ++tx_pending;
1279                         }
1280                 }
1281
1282                 if (rx_pending == 0 && tx_pending == 0)
1283                         return 0;
1284
1285                 msleep(EFX_FLUSH_INTERVAL);
1286                 efx_poll_flush_events(efx);
1287         }
1288
1289         /* Mark the queues as all flushed. We're going to return failure
1290          * leading to a reset, or fake up success anyway */
1291         efx_for_each_channel(channel, efx) {
1292                 efx_for_each_possible_channel_tx_queue(tx_queue, channel) {
1293                         if (tx_queue->initialised &&
1294                             tx_queue->flushed != FLUSH_DONE)
1295                                 netif_err(efx, hw, efx->net_dev,
1296                                           "tx queue %d flush command timed out\n",
1297                                           tx_queue->queue);
1298                         tx_queue->flushed = FLUSH_DONE;
1299                 }
1300                 efx_for_each_channel_rx_queue(rx_queue, channel) {
1301                         if (rx_queue->flushed != FLUSH_DONE)
1302                                 netif_err(efx, hw, efx->net_dev,
1303                                           "rx queue %d flush command timed out\n",
1304                                           efx_rx_queue_index(rx_queue));
1305                         rx_queue->flushed = FLUSH_DONE;
1306                 }
1307         }
1308
1309         return -ETIMEDOUT;
1310 }
1311
1312 /**************************************************************************
1313  *
1314  * Hardware interrupts
1315  * The hardware interrupt handler does very little work; all the event
1316  * queue processing is carried out by per-channel tasklets.
1317  *
1318  **************************************************************************/
1319
1320 /* Enable/disable/generate interrupts */
1321 static inline void efx_nic_interrupts(struct efx_nic *efx,
1322                                       bool enabled, bool force)
1323 {
1324         efx_oword_t int_en_reg_ker;
1325
1326         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1327                              FRF_AZ_KER_INT_LEVE_SEL, efx->fatal_irq_level,
1328                              FRF_AZ_KER_INT_KER, force,
1329                              FRF_AZ_DRV_INT_EN_KER, enabled);
1330         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1331 }
1332
1333 void efx_nic_enable_interrupts(struct efx_nic *efx)
1334 {
1335         struct efx_channel *channel;
1336
1337         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1338         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1339
1340         /* Enable interrupts */
1341         efx_nic_interrupts(efx, true, false);
1342
1343         /* Force processing of all the channels to get the EVQ RPTRs up to
1344            date */
1345         efx_for_each_channel(channel, efx)
1346                 efx_schedule_channel(channel);
1347 }
1348
1349 void efx_nic_disable_interrupts(struct efx_nic *efx)
1350 {
1351         /* Disable interrupts */
1352         efx_nic_interrupts(efx, false, false);
1353 }
1354
1355 /* Generate a test interrupt
1356  * Interrupt must already have been enabled, otherwise nasty things
1357  * may happen.
1358  */
1359 void efx_nic_generate_interrupt(struct efx_nic *efx)
1360 {
1361         efx_nic_interrupts(efx, true, true);
1362 }
1363
1364 /* Process a fatal interrupt
1365  * Disable bus mastering ASAP and schedule a reset
1366  */
1367 irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1368 {
1369         struct falcon_nic_data *nic_data = efx->nic_data;
1370         efx_oword_t *int_ker = efx->irq_status.addr;
1371         efx_oword_t fatal_intr;
1372         int error, mem_perr;
1373
1374         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1375         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1376
1377         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1378                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1379                   EFX_OWORD_VAL(fatal_intr),
1380                   error ? "disabling bus mastering" : "no recognised error");
1381
1382         /* If this is a memory parity error dump which blocks are offending */
1383         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1384                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1385         if (mem_perr) {
1386                 efx_oword_t reg;
1387                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1388                 netif_err(efx, hw, efx->net_dev,
1389                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1390                           EFX_OWORD_VAL(reg));
1391         }
1392
1393         /* Disable both devices */
1394         pci_clear_master(efx->pci_dev);
1395         if (efx_nic_is_dual_func(efx))
1396                 pci_clear_master(nic_data->pci_dev2);
1397         efx_nic_disable_interrupts(efx);
1398
1399         /* Count errors and reset or disable the NIC accordingly */
1400         if (efx->int_error_count == 0 ||
1401             time_after(jiffies, efx->int_error_expire)) {
1402                 efx->int_error_count = 0;
1403                 efx->int_error_expire =
1404                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1405         }
1406         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1407                 netif_err(efx, hw, efx->net_dev,
1408                           "SYSTEM ERROR - reset scheduled\n");
1409                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1410         } else {
1411                 netif_err(efx, hw, efx->net_dev,
1412                           "SYSTEM ERROR - max number of errors seen."
1413                           "NIC will be disabled\n");
1414                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1415         }
1416
1417         return IRQ_HANDLED;
1418 }
1419
1420 /* Handle a legacy interrupt
1421  * Acknowledges the interrupt and schedule event queue processing.
1422  */
1423 static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1424 {
1425         struct efx_nic *efx = dev_id;
1426         efx_oword_t *int_ker = efx->irq_status.addr;
1427         irqreturn_t result = IRQ_NONE;
1428         struct efx_channel *channel;
1429         efx_dword_t reg;
1430         u32 queues;
1431         int syserr;
1432
1433         /* Could this be ours?  If interrupts are disabled then the
1434          * channel state may not be valid.
1435          */
1436         if (!efx->legacy_irq_enabled)
1437                 return result;
1438
1439         /* Read the ISR which also ACKs the interrupts */
1440         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1441         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1442
1443         /* Check to see if we have a serious error condition */
1444         if (queues & (1U << efx->fatal_irq_level)) {
1445                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1446                 if (unlikely(syserr))
1447                         return efx_nic_fatal_interrupt(efx);
1448         }
1449
1450         if (queues != 0) {
1451                 if (EFX_WORKAROUND_15783(efx))
1452                         efx->irq_zero_count = 0;
1453
1454                 /* Schedule processing of any interrupting queues */
1455                 efx_for_each_channel(channel, efx) {
1456                         if (queues & 1)
1457                                 efx_schedule_channel(channel);
1458                         queues >>= 1;
1459                 }
1460                 result = IRQ_HANDLED;
1461
1462         } else if (EFX_WORKAROUND_15783(efx)) {
1463                 efx_qword_t *event;
1464
1465                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1466                  * because this might be a shared interrupt. */
1467                 if (efx->irq_zero_count++ == 0)
1468                         result = IRQ_HANDLED;
1469
1470                 /* Ensure we schedule or rearm all event queues */
1471                 efx_for_each_channel(channel, efx) {
1472                         event = efx_event(channel, channel->eventq_read_ptr);
1473                         if (efx_event_present(event))
1474                                 efx_schedule_channel(channel);
1475                         else
1476                                 efx_nic_eventq_read_ack(channel);
1477                 }
1478         }
1479
1480         if (result == IRQ_HANDLED) {
1481                 efx->last_irq_cpu = raw_smp_processor_id();
1482                 netif_vdbg(efx, intr, efx->net_dev,
1483                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1484                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1485         }
1486
1487         return result;
1488 }
1489
1490 /* Handle an MSI interrupt
1491  *
1492  * Handle an MSI hardware interrupt.  This routine schedules event
1493  * queue processing.  No interrupt acknowledgement cycle is necessary.
1494  * Also, we never need to check that the interrupt is for us, since
1495  * MSI interrupts cannot be shared.
1496  */
1497 static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1498 {
1499         struct efx_channel *channel = *(struct efx_channel **)dev_id;
1500         struct efx_nic *efx = channel->efx;
1501         efx_oword_t *int_ker = efx->irq_status.addr;
1502         int syserr;
1503
1504         efx->last_irq_cpu = raw_smp_processor_id();
1505         netif_vdbg(efx, intr, efx->net_dev,
1506                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1507                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1508
1509         /* Check to see if we have a serious error condition */
1510         if (channel->channel == efx->fatal_irq_level) {
1511                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1512                 if (unlikely(syserr))
1513                         return efx_nic_fatal_interrupt(efx);
1514         }
1515
1516         /* Schedule processing of the channel */
1517         efx_schedule_channel(channel);
1518
1519         return IRQ_HANDLED;
1520 }
1521
1522
1523 /* Setup RSS indirection table.
1524  * This maps from the hash value of the packet to RXQ
1525  */
1526 void efx_nic_push_rx_indir_table(struct efx_nic *efx)
1527 {
1528         size_t i = 0;
1529         efx_dword_t dword;
1530
1531         if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1532                 return;
1533
1534         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1535                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1536
1537         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1538                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1539                                      efx->rx_indir_table[i]);
1540                 efx_writed_table(efx, &dword, FR_BZ_RX_INDIRECTION_TBL, i);
1541         }
1542 }
1543
1544 /* Hook interrupt handler(s)
1545  * Try MSI and then legacy interrupts.
1546  */
1547 int efx_nic_init_interrupt(struct efx_nic *efx)
1548 {
1549         struct efx_channel *channel;
1550         int rc;
1551
1552         if (!EFX_INT_MODE_USE_MSI(efx)) {
1553                 irq_handler_t handler;
1554                 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1555                         handler = efx_legacy_interrupt;
1556                 else
1557                         handler = falcon_legacy_interrupt_a1;
1558
1559                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1560                                  efx->name, efx);
1561                 if (rc) {
1562                         netif_err(efx, drv, efx->net_dev,
1563                                   "failed to hook legacy IRQ %d\n",
1564                                   efx->pci_dev->irq);
1565                         goto fail1;
1566                 }
1567                 return 0;
1568         }
1569
1570         /* Hook MSI or MSI-X interrupt */
1571         efx_for_each_channel(channel, efx) {
1572                 rc = request_irq(channel->irq, efx_msi_interrupt,
1573                                  IRQF_PROBE_SHARED, /* Not shared */
1574                                  efx->channel_name[channel->channel],
1575                                  &efx->channel[channel->channel]);
1576                 if (rc) {
1577                         netif_err(efx, drv, efx->net_dev,
1578                                   "failed to hook IRQ %d\n", channel->irq);
1579                         goto fail2;
1580                 }
1581         }
1582
1583         return 0;
1584
1585  fail2:
1586         efx_for_each_channel(channel, efx)
1587                 free_irq(channel->irq, &efx->channel[channel->channel]);
1588  fail1:
1589         return rc;
1590 }
1591
1592 void efx_nic_fini_interrupt(struct efx_nic *efx)
1593 {
1594         struct efx_channel *channel;
1595         efx_oword_t reg;
1596
1597         /* Disable MSI/MSI-X interrupts */
1598         efx_for_each_channel(channel, efx) {
1599                 if (channel->irq)
1600                         free_irq(channel->irq, &efx->channel[channel->channel]);
1601         }
1602
1603         /* ACK legacy interrupt */
1604         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1605                 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1606         else
1607                 falcon_irq_ack_a1(efx);
1608
1609         /* Disable legacy interrupt */
1610         if (efx->legacy_irq)
1611                 free_irq(efx->legacy_irq, efx);
1612 }
1613
1614 u32 efx_nic_fpga_ver(struct efx_nic *efx)
1615 {
1616         efx_oword_t altera_build;
1617         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1618         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1619 }
1620
1621 void efx_nic_init_common(struct efx_nic *efx)
1622 {
1623         efx_oword_t temp;
1624
1625         /* Set positions of descriptor caches in SRAM. */
1626         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
1627                              efx->type->tx_dc_base / 8);
1628         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1629         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
1630                              efx->type->rx_dc_base / 8);
1631         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1632
1633         /* Set TX descriptor cache size. */
1634         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1635         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1636         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1637
1638         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1639          * this allows most efficient prefetching.
1640          */
1641         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1642         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1643         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1644         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1645         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1646
1647         /* Program INT_KER address */
1648         EFX_POPULATE_OWORD_2(temp,
1649                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1650                              EFX_INT_MODE_USE_MSI(efx),
1651                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1652         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1653
1654         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1655                 /* Use an interrupt level unused by event queues */
1656                 efx->fatal_irq_level = 0x1f;
1657         else
1658                 /* Use a valid MSI-X vector */
1659                 efx->fatal_irq_level = 0;
1660
1661         /* Enable all the genuinely fatal interrupts.  (They are still
1662          * masked by the overall interrupt mask, controlled by
1663          * falcon_interrupts()).
1664          *
1665          * Note: All other fatal interrupts are enabled
1666          */
1667         EFX_POPULATE_OWORD_3(temp,
1668                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1669                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1670                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1671         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0)
1672                 EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1673         EFX_INVERT_OWORD(temp);
1674         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1675
1676         efx_nic_push_rx_indir_table(efx);
1677
1678         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1679          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1680          */
1681         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1682         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1683         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1684         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1685         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1686         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1687         /* Enable SW_EV to inherit in char driver - assume harmless here */
1688         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1689         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1690         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1691         /* Disable hardware watchdog which can misfire */
1692         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1693         /* Squash TX of packets of 16 bytes or less */
1694         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1695                 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1696         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1697
1698         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1699                 EFX_POPULATE_OWORD_4(temp,
1700                                      /* Default values */
1701                                      FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1702                                      FRF_BZ_TX_PACE_SB_AF, 0xb,
1703                                      FRF_BZ_TX_PACE_FB_BASE, 0,
1704                                      /* Allow large pace values in the
1705                                       * fast bin. */
1706                                      FRF_BZ_TX_PACE_BIN_TH,
1707                                      FFE_BZ_TX_PACE_RESERVED);
1708                 efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1709         }
1710 }
1711
1712 /* Register dump */
1713
1714 #define REGISTER_REVISION_A     1
1715 #define REGISTER_REVISION_B     2
1716 #define REGISTER_REVISION_C     3
1717 #define REGISTER_REVISION_Z     3       /* latest revision */
1718
1719 struct efx_nic_reg {
1720         u32 offset:24;
1721         u32 min_revision:2, max_revision:2;
1722 };
1723
1724 #define REGISTER(name, min_rev, max_rev) {                              \
1725         FR_ ## min_rev ## max_rev ## _ ## name,                         \
1726         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev    \
1727 }
1728 #define REGISTER_AA(name) REGISTER(name, A, A)
1729 #define REGISTER_AB(name) REGISTER(name, A, B)
1730 #define REGISTER_AZ(name) REGISTER(name, A, Z)
1731 #define REGISTER_BB(name) REGISTER(name, B, B)
1732 #define REGISTER_BZ(name) REGISTER(name, B, Z)
1733 #define REGISTER_CZ(name) REGISTER(name, C, Z)
1734
1735 static const struct efx_nic_reg efx_nic_regs[] = {
1736         REGISTER_AZ(ADR_REGION),
1737         REGISTER_AZ(INT_EN_KER),
1738         REGISTER_BZ(INT_EN_CHAR),
1739         REGISTER_AZ(INT_ADR_KER),
1740         REGISTER_BZ(INT_ADR_CHAR),
1741         /* INT_ACK_KER is WO */
1742         /* INT_ISR0 is RC */
1743         REGISTER_AZ(HW_INIT),
1744         REGISTER_CZ(USR_EV_CFG),
1745         REGISTER_AB(EE_SPI_HCMD),
1746         REGISTER_AB(EE_SPI_HADR),
1747         REGISTER_AB(EE_SPI_HDATA),
1748         REGISTER_AB(EE_BASE_PAGE),
1749         REGISTER_AB(EE_VPD_CFG0),
1750         /* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */
1751         /* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */
1752         /* PCIE_CORE_INDIRECT is indirect */
1753         REGISTER_AB(NIC_STAT),
1754         REGISTER_AB(GPIO_CTL),
1755         REGISTER_AB(GLB_CTL),
1756         /* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */
1757         REGISTER_BZ(DP_CTRL),
1758         REGISTER_AZ(MEM_STAT),
1759         REGISTER_AZ(CS_DEBUG),
1760         REGISTER_AZ(ALTERA_BUILD),
1761         REGISTER_AZ(CSR_SPARE),
1762         REGISTER_AB(PCIE_SD_CTL0123),
1763         REGISTER_AB(PCIE_SD_CTL45),
1764         REGISTER_AB(PCIE_PCS_CTL_STAT),
1765         /* DEBUG_DATA_OUT is not used */
1766         /* DRV_EV is WO */
1767         REGISTER_AZ(EVQ_CTL),
1768         REGISTER_AZ(EVQ_CNT1),
1769         REGISTER_AZ(EVQ_CNT2),
1770         REGISTER_AZ(BUF_TBL_CFG),
1771         REGISTER_AZ(SRM_RX_DC_CFG),
1772         REGISTER_AZ(SRM_TX_DC_CFG),
1773         REGISTER_AZ(SRM_CFG),
1774         /* BUF_TBL_UPD is WO */
1775         REGISTER_AZ(SRM_UPD_EVQ),
1776         REGISTER_AZ(SRAM_PARITY),
1777         REGISTER_AZ(RX_CFG),
1778         REGISTER_BZ(RX_FILTER_CTL),
1779         /* RX_FLUSH_DESCQ is WO */
1780         REGISTER_AZ(RX_DC_CFG),
1781         REGISTER_AZ(RX_DC_PF_WM),
1782         REGISTER_BZ(RX_RSS_TKEY),
1783         /* RX_NODESC_DROP is RC */
1784         REGISTER_AA(RX_SELF_RST),
1785         /* RX_DEBUG, RX_PUSH_DROP are not used */
1786         REGISTER_CZ(RX_RSS_IPV6_REG1),
1787         REGISTER_CZ(RX_RSS_IPV6_REG2),
1788         REGISTER_CZ(RX_RSS_IPV6_REG3),
1789         /* TX_FLUSH_DESCQ is WO */
1790         REGISTER_AZ(TX_DC_CFG),
1791         REGISTER_AA(TX_CHKSM_CFG),
1792         REGISTER_AZ(TX_CFG),
1793         /* TX_PUSH_DROP is not used */
1794         REGISTER_AZ(TX_RESERVED),
1795         REGISTER_BZ(TX_PACE),
1796         /* TX_PACE_DROP_QID is RC */
1797         REGISTER_BB(TX_VLAN),
1798         REGISTER_BZ(TX_IPFIL_PORTEN),
1799         REGISTER_AB(MD_TXD),
1800         REGISTER_AB(MD_RXD),
1801         REGISTER_AB(MD_CS),
1802         REGISTER_AB(MD_PHY_ADR),
1803         REGISTER_AB(MD_ID),
1804         /* MD_STAT is RC */
1805         REGISTER_AB(MAC_STAT_DMA),
1806         REGISTER_AB(MAC_CTRL),
1807         REGISTER_BB(GEN_MODE),
1808         REGISTER_AB(MAC_MC_HASH_REG0),
1809         REGISTER_AB(MAC_MC_HASH_REG1),
1810         REGISTER_AB(GM_CFG1),
1811         REGISTER_AB(GM_CFG2),
1812         /* GM_IPG and GM_HD are not used */
1813         REGISTER_AB(GM_MAX_FLEN),
1814         /* GM_TEST is not used */
1815         REGISTER_AB(GM_ADR1),
1816         REGISTER_AB(GM_ADR2),
1817         REGISTER_AB(GMF_CFG0),
1818         REGISTER_AB(GMF_CFG1),
1819         REGISTER_AB(GMF_CFG2),
1820         REGISTER_AB(GMF_CFG3),
1821         REGISTER_AB(GMF_CFG4),
1822         REGISTER_AB(GMF_CFG5),
1823         REGISTER_BB(TX_SRC_MAC_CTL),
1824         REGISTER_AB(XM_ADR_LO),
1825         REGISTER_AB(XM_ADR_HI),
1826         REGISTER_AB(XM_GLB_CFG),
1827         REGISTER_AB(XM_TX_CFG),
1828         REGISTER_AB(XM_RX_CFG),
1829         REGISTER_AB(XM_MGT_INT_MASK),
1830         REGISTER_AB(XM_FC),
1831         REGISTER_AB(XM_PAUSE_TIME),
1832         REGISTER_AB(XM_TX_PARAM),
1833         REGISTER_AB(XM_RX_PARAM),
1834         /* XM_MGT_INT_MSK (note no 'A') is RC */
1835         REGISTER_AB(XX_PWR_RST),
1836         REGISTER_AB(XX_SD_CTL),
1837         REGISTER_AB(XX_TXDRV_CTL),
1838         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
1839         /* XX_CORE_STAT is partly RC */
1840 };
1841
1842 struct efx_nic_reg_table {
1843         u32 offset:24;
1844         u32 min_revision:2, max_revision:2;
1845         u32 step:6, rows:21;
1846 };
1847
1848 #define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \
1849         offset,                                                         \
1850         REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev,   \
1851         step, rows                                                      \
1852 }
1853 #define REGISTER_TABLE(name, min_rev, max_rev)                          \
1854         REGISTER_TABLE_DIMENSIONS(                                      \
1855                 name, FR_ ## min_rev ## max_rev ## _ ## name,           \
1856                 min_rev, max_rev,                                       \
1857                 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP,        \
1858                 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
1859 #define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A)
1860 #define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z)
1861 #define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B)
1862 #define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z)
1863 #define REGISTER_TABLE_BB_CZ(name)                                      \
1864         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B,           \
1865                                   FR_BZ_ ## name ## _STEP,              \
1866                                   FR_BB_ ## name ## _ROWS),             \
1867         REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z,           \
1868                                   FR_BZ_ ## name ## _STEP,              \
1869                                   FR_CZ_ ## name ## _ROWS)
1870 #define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z)
1871
1872 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
1873         /* DRIVER is not used */
1874         /* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */
1875         REGISTER_TABLE_BB(TX_IPFIL_TBL),
1876         REGISTER_TABLE_BB(TX_SRC_MAC_TBL),
1877         REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),
1878         REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),
1879         REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),
1880         REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),
1881         REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),
1882         REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),
1883         /* We can't reasonably read all of the buffer table (up to 8MB!).
1884          * However this driver will only use a few entries.  Reading
1885          * 1K entries allows for some expansion of queue count and
1886          * size before we need to change the version. */
1887         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
1888                                   A, A, 8, 1024),
1889         REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
1890                                   B, Z, 8, 1024),
1891         REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
1892         REGISTER_TABLE_BB_CZ(TIMER_TBL),
1893         REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
1894         REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),
1895         /* TX_FILTER_TBL0 is huge and not used by this driver */
1896         REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),
1897         REGISTER_TABLE_CZ(MC_TREG_SMEM),
1898         /* MSIX_PBA_TABLE is not mapped */
1899         /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
1900         REGISTER_TABLE_BZ(RX_FILTER_TBL0),
1901 };
1902
1903 size_t efx_nic_get_regs_len(struct efx_nic *efx)
1904 {
1905         const struct efx_nic_reg *reg;
1906         const struct efx_nic_reg_table *table;
1907         size_t len = 0;
1908
1909         for (reg = efx_nic_regs;
1910              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
1911              reg++)
1912                 if (efx->type->revision >= reg->min_revision &&
1913                     efx->type->revision <= reg->max_revision)
1914                         len += sizeof(efx_oword_t);
1915
1916         for (table = efx_nic_reg_tables;
1917              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
1918              table++)
1919                 if (efx->type->revision >= table->min_revision &&
1920                     efx->type->revision <= table->max_revision)
1921                         len += table->rows * min_t(size_t, table->step, 16);
1922
1923         return len;
1924 }
1925
1926 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
1927 {
1928         const struct efx_nic_reg *reg;
1929         const struct efx_nic_reg_table *table;
1930
1931         for (reg = efx_nic_regs;
1932              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
1933              reg++) {
1934                 if (efx->type->revision >= reg->min_revision &&
1935                     efx->type->revision <= reg->max_revision) {
1936                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
1937                         buf += sizeof(efx_oword_t);
1938                 }
1939         }
1940
1941         for (table = efx_nic_reg_tables;
1942              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
1943              table++) {
1944                 size_t size, i;
1945
1946                 if (!(efx->type->revision >= table->min_revision &&
1947                       efx->type->revision <= table->max_revision))
1948                         continue;
1949
1950                 size = min_t(size_t, table->step, 16);
1951
1952                 for (i = 0; i < table->rows; i++) {
1953                         switch (table->step) {
1954                         case 4: /* 32-bit register or SRAM */
1955                                 efx_readd_table(efx, buf, table->offset, i);
1956                                 break;
1957                         case 8: /* 64-bit SRAM */
1958                                 efx_sram_readq(efx,
1959                                                efx->membase + table->offset,
1960                                                buf, i);
1961                                 break;
1962                         case 16: /* 128-bit register */
1963                                 efx_reado_table(efx, buf, table->offset, i);
1964                                 break;
1965                         case 32: /* 128-bit register, interleaved */
1966                                 efx_reado_table(efx, buf, table->offset, 2 * i);
1967                                 break;
1968                         default:
1969                                 WARN_ON(1);
1970                                 return;
1971                         }
1972                         buf += size;
1973                 }
1974         }
1975 }