1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "net_driver.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
30 #include "workarounds.h"
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
43 struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
46 struct i2c_algo_bit_data i2c_data;
49 /**************************************************************************
53 **************************************************************************
56 static int disable_dma_stats;
58 /* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
73 /* RX FIFO XOFF watermark
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
79 static int rx_xoff_thresh_bytes = -1;
80 module_param(rx_xoff_thresh_bytes, int, 0644);
81 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
83 /* RX FIFO XON watermark
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
89 static int rx_xon_thresh_bytes = -1;
90 module_param(rx_xon_thresh_bytes, int, 0644);
91 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
93 /* TX descriptor ring size - min 512 max 4k */
94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95 #define FALCON_TXD_RING_SIZE 1024
96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
98 /* RX descriptor ring size - min 512 max 4k */
99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100 #define FALCON_RXD_RING_SIZE 1024
101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
103 /* Event queue size - max 32k */
104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
105 #define FALCON_EVQ_SIZE 4096
106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
108 /* Max number of internal errors. After this resets will not be performed */
109 #define FALCON_MAX_INT_ERRORS 4
111 /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
113 #define FALCON_FLUSH_INTERVAL 10
114 #define FALCON_FLUSH_POLL_COUNT 100
116 /**************************************************************************
120 **************************************************************************
123 /* DMA address mask */
124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
126 /* TX DMA length mask (13-bit) */
127 #define FALCON_TX_DMA_MASK (4096 - 1)
129 /* Size and alignment of special buffers (4KB) */
130 #define FALCON_BUF_SIZE 4096
132 /* Dummy SRAM size code */
133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
142 #define FALCON_IS_DUAL_FUNC(efx) \
143 (falcon_rev(efx) < FALCON_REV_B0)
145 /**************************************************************************
147 * Falcon hardware access
149 **************************************************************************/
151 /* Read the current event from the event queue */
152 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
155 return (((efx_qword_t *) (channel->eventq.addr)) + index);
158 /* See if an event is present
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
168 static inline int falcon_event_present(efx_qword_t *event)
170 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
174 /**************************************************************************
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
180 **************************************************************************
182 static void falcon_setsda(void *data, int state)
184 struct efx_nic *efx = (struct efx_nic *)data;
187 falcon_read(efx, ®, GPIO_CTL_REG_KER);
188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189 falcon_write(efx, ®, GPIO_CTL_REG_KER);
192 static void falcon_setscl(void *data, int state)
194 struct efx_nic *efx = (struct efx_nic *)data;
197 falcon_read(efx, ®, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, ®, GPIO_CTL_REG_KER);
202 static int falcon_getsda(void *data)
204 struct efx_nic *efx = (struct efx_nic *)data;
207 falcon_read(efx, ®, GPIO_CTL_REG_KER);
208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
211 static int falcon_getscl(void *data)
213 struct efx_nic *efx = (struct efx_nic *)data;
216 falcon_read(efx, ®, GPIO_CTL_REG_KER);
217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
220 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221 .setsda = falcon_setsda,
222 .setscl = falcon_setscl,
223 .getsda = falcon_getsda,
224 .getscl = falcon_getscl,
226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout = DIV_ROUND_UP(HZ, 20),
230 /**************************************************************************
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
236 *************************************************************************/
239 * Initialise a Falcon special buffer
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
246 falcon_init_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer)
249 efx_qword_t buf_desc;
254 EFX_BUG_ON_PARANOID(!buffer->addr);
256 /* Write buffer descriptors to NIC */
257 for (i = 0; i < buffer->entries; i++) {
258 index = buffer->index + i;
259 dma_addr = buffer->dma_addr + (i * 4096);
260 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261 index, (unsigned long long)dma_addr);
262 EFX_POPULATE_QWORD_4(buf_desc,
263 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
265 BUF_ADR_FBUF, (dma_addr >> 12),
266 BUF_OWNER_ID_FBUF, 0);
267 falcon_write_sram(efx, &buf_desc, index);
271 /* Unmaps a buffer from Falcon and clears the buffer table entries */
273 falcon_fini_special_buffer(struct efx_nic *efx,
274 struct efx_special_buffer *buffer)
276 efx_oword_t buf_tbl_upd;
277 unsigned int start = buffer->index;
278 unsigned int end = (buffer->index + buffer->entries - 1);
280 if (!buffer->entries)
283 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
284 buffer->index, buffer->index + buffer->entries - 1);
286 EFX_POPULATE_OWORD_4(buf_tbl_upd,
290 BUF_CLR_START_ID, start);
291 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
295 * Allocate a new Falcon special buffer
297 * This allocates memory for a new buffer, clears it and allocates a
298 * new buffer ID range. It does not write into Falcon's buffer table.
300 * This call will allocate 4KB buffers, since Falcon can't use 8KB
301 * buffers for event queues and descriptor rings.
303 static int falcon_alloc_special_buffer(struct efx_nic *efx,
304 struct efx_special_buffer *buffer,
307 struct falcon_nic_data *nic_data = efx->nic_data;
309 len = ALIGN(len, FALCON_BUF_SIZE);
311 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
316 buffer->entries = len / FALCON_BUF_SIZE;
317 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
319 /* All zeros is a potentially valid event so memset to 0xff */
320 memset(buffer->addr, 0xff, len);
322 /* Select new buffer ID */
323 buffer->index = nic_data->next_buffer_table;
324 nic_data->next_buffer_table += buffer->entries;
326 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
327 "(virt %p phys %lx)\n", buffer->index,
328 buffer->index + buffer->entries - 1,
329 (unsigned long long)buffer->dma_addr, len,
330 buffer->addr, virt_to_phys(buffer->addr));
335 static void falcon_free_special_buffer(struct efx_nic *efx,
336 struct efx_special_buffer *buffer)
341 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
342 "(virt %p phys %lx)\n", buffer->index,
343 buffer->index + buffer->entries - 1,
344 (unsigned long long)buffer->dma_addr, buffer->len,
345 buffer->addr, virt_to_phys(buffer->addr));
347 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
353 /**************************************************************************
355 * Falcon generic buffer handling
356 * These buffers are used for interrupt status and MAC stats
358 **************************************************************************/
360 static int falcon_alloc_buffer(struct efx_nic *efx,
361 struct efx_buffer *buffer, unsigned int len)
363 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
368 memset(buffer->addr, 0, len);
372 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
375 pci_free_consistent(efx->pci_dev, buffer->len,
376 buffer->addr, buffer->dma_addr);
381 /**************************************************************************
385 **************************************************************************/
387 /* Returns a pointer to the specified transmit descriptor in the TX
388 * descriptor queue belonging to the specified channel.
390 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
393 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
396 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
397 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
402 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
403 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
404 falcon_writel_page(tx_queue->efx, ®,
405 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
409 /* For each entry inserted into the software descriptor ring, create a
410 * descriptor in the hardware TX descriptor ring (in host memory), and
413 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
416 struct efx_tx_buffer *buffer;
420 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
423 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
424 buffer = &tx_queue->buffer[write_ptr];
425 txd = falcon_tx_desc(tx_queue, write_ptr);
426 ++tx_queue->write_count;
428 /* Create TX descriptor ring entry */
429 EFX_POPULATE_QWORD_5(*txd,
431 TX_KER_CONT, buffer->continuation,
432 TX_KER_BYTE_CNT, buffer->len,
433 TX_KER_BUF_REGION, 0,
434 TX_KER_BUF_ADR, buffer->dma_addr);
435 } while (tx_queue->write_count != tx_queue->insert_count);
437 wmb(); /* Ensure descriptors are written before they are fetched */
438 falcon_notify_tx_desc(tx_queue);
441 /* Allocate hardware resources for a TX queue */
442 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
444 struct efx_nic *efx = tx_queue->efx;
445 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
446 FALCON_TXD_RING_SIZE *
447 sizeof(efx_qword_t));
450 void falcon_init_tx(struct efx_tx_queue *tx_queue)
452 efx_oword_t tx_desc_ptr;
453 struct efx_nic *efx = tx_queue->efx;
455 tx_queue->flushed = false;
457 /* Pin TX descriptor ring */
458 falcon_init_special_buffer(efx, &tx_queue->txd);
460 /* Push TX descriptor ring to card */
461 EFX_POPULATE_OWORD_10(tx_desc_ptr,
465 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
466 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
467 TX_DESCQ_OWNER_ID, 0,
468 TX_DESCQ_LABEL, tx_queue->queue,
469 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
471 TX_NON_IP_DROP_DIS_B0, 1);
473 if (falcon_rev(efx) >= FALCON_REV_B0) {
474 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
475 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
476 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
479 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
482 if (falcon_rev(efx) < FALCON_REV_B0) {
485 /* Only 128 bits in this register */
486 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
488 falcon_read(efx, ®, TX_CHKSM_CFG_REG_KER_A1);
489 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
490 clear_bit_le(tx_queue->queue, (void *)®);
492 set_bit_le(tx_queue->queue, (void *)®);
493 falcon_write(efx, ®, TX_CHKSM_CFG_REG_KER_A1);
497 static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
499 struct efx_nic *efx = tx_queue->efx;
500 efx_oword_t tx_flush_descq;
502 /* Post a flush command */
503 EFX_POPULATE_OWORD_2(tx_flush_descq,
504 TX_FLUSH_DESCQ_CMD, 1,
505 TX_FLUSH_DESCQ, tx_queue->queue);
506 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
509 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
511 struct efx_nic *efx = tx_queue->efx;
512 efx_oword_t tx_desc_ptr;
514 /* The queue should have been flushed */
515 WARN_ON(!tx_queue->flushed);
517 /* Remove TX descriptor ring from card */
518 EFX_ZERO_OWORD(tx_desc_ptr);
519 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
522 /* Unpin TX descriptor ring */
523 falcon_fini_special_buffer(efx, &tx_queue->txd);
526 /* Free buffers backing TX queue */
527 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
529 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
532 /**************************************************************************
536 **************************************************************************/
538 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
539 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
542 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
545 /* This creates an entry in the RX descriptor queue */
546 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
549 struct efx_rx_buffer *rx_buf;
552 rxd = falcon_rx_desc(rx_queue, index);
553 rx_buf = efx_rx_buffer(rx_queue, index);
554 EFX_POPULATE_QWORD_3(*rxd,
557 rx_queue->efx->type->rx_buffer_padding,
558 RX_KER_BUF_REGION, 0,
559 RX_KER_BUF_ADR, rx_buf->dma_addr);
562 /* This writes to the RX_DESC_WPTR register for the specified receive
565 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
570 while (rx_queue->notified_count != rx_queue->added_count) {
571 falcon_build_rx_desc(rx_queue,
572 rx_queue->notified_count &
573 FALCON_RXD_RING_MASK);
574 ++rx_queue->notified_count;
578 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
579 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
580 falcon_writel_page(rx_queue->efx, ®,
581 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
584 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
586 struct efx_nic *efx = rx_queue->efx;
587 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
588 FALCON_RXD_RING_SIZE *
589 sizeof(efx_qword_t));
592 void falcon_init_rx(struct efx_rx_queue *rx_queue)
594 efx_oword_t rx_desc_ptr;
595 struct efx_nic *efx = rx_queue->efx;
596 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
597 bool iscsi_digest_en = is_b0;
599 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
600 rx_queue->queue, rx_queue->rxd.index,
601 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
603 rx_queue->flushed = false;
605 /* Pin RX descriptor ring */
606 falcon_init_special_buffer(efx, &rx_queue->rxd);
608 /* Push RX descriptor ring to card */
609 EFX_POPULATE_OWORD_10(rx_desc_ptr,
610 RX_ISCSI_DDIG_EN, iscsi_digest_en,
611 RX_ISCSI_HDIG_EN, iscsi_digest_en,
612 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
613 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
614 RX_DESCQ_OWNER_ID, 0,
615 RX_DESCQ_LABEL, rx_queue->queue,
616 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
617 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
618 /* For >=B0 this is scatter so disable */
619 RX_DESCQ_JUMBO, !is_b0,
621 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
625 static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
627 struct efx_nic *efx = rx_queue->efx;
628 efx_oword_t rx_flush_descq;
630 /* Post a flush command */
631 EFX_POPULATE_OWORD_2(rx_flush_descq,
632 RX_FLUSH_DESCQ_CMD, 1,
633 RX_FLUSH_DESCQ, rx_queue->queue);
634 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
637 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
639 efx_oword_t rx_desc_ptr;
640 struct efx_nic *efx = rx_queue->efx;
642 /* The queue should already have been flushed */
643 WARN_ON(!rx_queue->flushed);
645 /* Remove RX descriptor ring from card */
646 EFX_ZERO_OWORD(rx_desc_ptr);
647 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
650 /* Unpin RX descriptor ring */
651 falcon_fini_special_buffer(efx, &rx_queue->rxd);
654 /* Free buffers backing RX queue */
655 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
657 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
660 /**************************************************************************
662 * Falcon event queue processing
663 * Event queues are processed by per-channel tasklets.
665 **************************************************************************/
667 /* Update a channel's event queue's read pointer (RPTR) register
669 * This writes the EVQ_RPTR_REG register for the specified channel's
672 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
673 * whereas channel->eventq_read_ptr contains the index of the "next to
676 void falcon_eventq_read_ack(struct efx_channel *channel)
679 struct efx_nic *efx = channel->efx;
681 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
682 falcon_writel_table(efx, ®, efx->type->evq_rptr_tbl_base,
686 /* Use HW to insert a SW defined event */
687 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
689 efx_oword_t drv_ev_reg;
691 EFX_POPULATE_OWORD_2(drv_ev_reg,
692 DRV_EV_QID, channel->channel,
694 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
695 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
698 /* Handle a transmit completion event
700 * Falcon batches TX completion events; the message we receive is of
701 * the form "complete all TX events up to this index".
703 static void falcon_handle_tx_event(struct efx_channel *channel,
706 unsigned int tx_ev_desc_ptr;
707 unsigned int tx_ev_q_label;
708 struct efx_tx_queue *tx_queue;
709 struct efx_nic *efx = channel->efx;
711 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
712 /* Transmit completion */
713 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
714 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
715 tx_queue = &efx->tx_queue[tx_ev_q_label];
716 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
717 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
718 /* Rewrite the FIFO write pointer */
719 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
720 tx_queue = &efx->tx_queue[tx_ev_q_label];
722 if (efx_dev_registered(efx))
723 netif_tx_lock(efx->net_dev);
724 falcon_notify_tx_desc(tx_queue);
725 if (efx_dev_registered(efx))
726 netif_tx_unlock(efx->net_dev);
727 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
728 EFX_WORKAROUND_10727(efx)) {
729 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
731 EFX_ERR(efx, "channel %d unexpected TX event "
732 EFX_QWORD_FMT"\n", channel->channel,
733 EFX_QWORD_VAL(*event));
737 /* Detect errors included in the rx_evt_pkt_ok bit. */
738 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
739 const efx_qword_t *event,
743 struct efx_nic *efx = rx_queue->efx;
744 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
745 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
746 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
747 bool rx_ev_other_err, rx_ev_pause_frm;
748 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
749 unsigned rx_ev_pkt_type;
751 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
752 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
753 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
754 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
755 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
756 RX_EV_BUF_OWNER_ID_ERR);
757 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
758 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
759 RX_EV_IP_HDR_CHKSUM_ERR);
760 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
761 RX_EV_TCP_UDP_CHKSUM_ERR);
762 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
763 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
764 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
765 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
766 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
768 /* Every error apart from tobe_disc and pause_frm */
769 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
770 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
771 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
773 /* Count errors that are not in MAC stats. */
775 ++rx_queue->channel->n_rx_frm_trunc;
776 else if (rx_ev_tobe_disc)
777 ++rx_queue->channel->n_rx_tobe_disc;
778 else if (rx_ev_ip_hdr_chksum_err)
779 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
780 else if (rx_ev_tcp_udp_chksum_err)
781 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
782 if (rx_ev_ip_frag_err)
783 ++rx_queue->channel->n_rx_ip_frag_err;
785 /* The frame must be discarded if any of these are true. */
786 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
787 rx_ev_tobe_disc | rx_ev_pause_frm);
789 /* TOBE_DISC is expected on unicast mismatches; don't print out an
790 * error message. FRM_TRUNC indicates RXDP dropped the packet due
791 * to a FIFO overflow.
793 #ifdef EFX_ENABLE_DEBUG
794 if (rx_ev_other_err) {
795 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
796 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
797 rx_queue->queue, EFX_QWORD_VAL(*event),
798 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
799 rx_ev_ip_hdr_chksum_err ?
800 " [IP_HDR_CHKSUM_ERR]" : "",
801 rx_ev_tcp_udp_chksum_err ?
802 " [TCP_UDP_CHKSUM_ERR]" : "",
803 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
804 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
805 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
806 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
807 rx_ev_pause_frm ? " [PAUSE]" : "");
811 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
812 efx->phy_type == PHY_TYPE_10XPRESS))
813 tenxpress_crc_err(efx);
816 /* Handle receive events that are not in-order. */
817 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
820 struct efx_nic *efx = rx_queue->efx;
821 unsigned expected, dropped;
823 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
824 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
825 FALCON_RXD_RING_MASK);
826 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
827 dropped, index, expected);
829 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
830 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
833 /* Handle a packet received event
835 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
836 * wrong destination address
837 * Also "is multicast" and "matches multicast filter" flags can be used to
838 * discard non-matching multicast packets.
840 static void falcon_handle_rx_event(struct efx_channel *channel,
841 const efx_qword_t *event)
843 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
844 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
845 unsigned expected_ptr;
846 bool rx_ev_pkt_ok, discard = false, checksummed;
847 struct efx_rx_queue *rx_queue;
848 struct efx_nic *efx = channel->efx;
850 /* Basic packet information */
851 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
852 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
853 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
854 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
855 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
856 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
858 rx_queue = &efx->rx_queue[channel->channel];
860 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
861 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
862 if (unlikely(rx_ev_desc_ptr != expected_ptr))
863 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
865 if (likely(rx_ev_pkt_ok)) {
866 /* If packet is marked as OK and packet type is TCP/IPv4 or
867 * UDP/IPv4, then we can rely on the hardware checksum.
869 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
871 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
876 /* Detect multicast packets that didn't match the filter */
877 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
878 if (rx_ev_mcast_pkt) {
879 unsigned int rx_ev_mcast_hash_match =
880 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
882 if (unlikely(!rx_ev_mcast_hash_match))
886 /* Handle received packet */
887 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
888 checksummed, discard);
891 /* Global events are basically PHY events */
892 static void falcon_handle_global_event(struct efx_channel *channel,
895 struct efx_nic *efx = channel->efx;
896 bool is_phy_event = false, handled = false;
898 /* Check for interrupt on either port. Some boards have a
899 * single PHY wired to the interrupt line for port 1. */
900 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
901 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
902 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
905 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
906 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0))
910 efx->phy_op->clear_interrupt(efx);
911 queue_work(efx->workqueue, &efx->reconfigure_work);
915 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
916 EFX_ERR(efx, "channel %d seen global RX_RESET "
917 "event. Resetting.\n", channel->channel);
919 atomic_inc(&efx->rx_reset);
920 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
921 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
926 EFX_ERR(efx, "channel %d unknown global event "
927 EFX_QWORD_FMT "\n", channel->channel,
928 EFX_QWORD_VAL(*event));
931 static void falcon_handle_driver_event(struct efx_channel *channel,
934 struct efx_nic *efx = channel->efx;
935 unsigned int ev_sub_code;
936 unsigned int ev_sub_data;
938 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
939 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
941 switch (ev_sub_code) {
942 case TX_DESCQ_FLS_DONE_EV_DECODE:
943 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
944 channel->channel, ev_sub_data);
946 case RX_DESCQ_FLS_DONE_EV_DECODE:
947 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
948 channel->channel, ev_sub_data);
950 case EVQ_INIT_DONE_EV_DECODE:
951 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
952 channel->channel, ev_sub_data);
954 case SRM_UPD_DONE_EV_DECODE:
955 EFX_TRACE(efx, "channel %d SRAM update done\n",
958 case WAKE_UP_EV_DECODE:
959 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
960 channel->channel, ev_sub_data);
962 case TIMER_EV_DECODE:
963 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
964 channel->channel, ev_sub_data);
966 case RX_RECOVERY_EV_DECODE:
967 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
968 "Resetting.\n", channel->channel);
969 atomic_inc(&efx->rx_reset);
970 efx_schedule_reset(efx,
971 EFX_WORKAROUND_6555(efx) ?
972 RESET_TYPE_RX_RECOVERY :
975 case RX_DSC_ERROR_EV_DECODE:
976 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
977 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
978 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
980 case TX_DSC_ERROR_EV_DECODE:
981 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
982 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
983 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
986 EFX_TRACE(efx, "channel %d unknown driver event code %d "
987 "data %04x\n", channel->channel, ev_sub_code,
993 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
995 unsigned int read_ptr;
996 efx_qword_t event, *p_event;
1000 read_ptr = channel->eventq_read_ptr;
1003 p_event = falcon_event(channel, read_ptr);
1006 if (!falcon_event_present(&event))
1010 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1011 channel->channel, EFX_QWORD_VAL(event));
1013 /* Clear this event by marking it all ones */
1014 EFX_SET_QWORD(*p_event);
1016 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1019 case RX_IP_EV_DECODE:
1020 falcon_handle_rx_event(channel, &event);
1023 case TX_IP_EV_DECODE:
1024 falcon_handle_tx_event(channel, &event);
1026 case DRV_GEN_EV_DECODE:
1027 channel->eventq_magic
1028 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1029 EFX_LOG(channel->efx, "channel %d received generated "
1030 "event "EFX_QWORD_FMT"\n", channel->channel,
1031 EFX_QWORD_VAL(event));
1033 case GLOBAL_EV_DECODE:
1034 falcon_handle_global_event(channel, &event);
1036 case DRIVER_EV_DECODE:
1037 falcon_handle_driver_event(channel, &event);
1040 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1041 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1042 ev_code, EFX_QWORD_VAL(event));
1045 /* Increment read pointer */
1046 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1048 } while (rx_packets < rx_quota);
1050 channel->eventq_read_ptr = read_ptr;
1054 void falcon_set_int_moderation(struct efx_channel *channel)
1056 efx_dword_t timer_cmd;
1057 struct efx_nic *efx = channel->efx;
1059 /* Set timer register */
1060 if (channel->irq_moderation) {
1061 /* Round to resolution supported by hardware. The value we
1062 * program is based at 0. So actual interrupt moderation
1063 * achieved is ((x + 1) * res).
1065 unsigned int res = 5;
1066 channel->irq_moderation -= (channel->irq_moderation % res);
1067 if (channel->irq_moderation < res)
1068 channel->irq_moderation = res;
1069 EFX_POPULATE_DWORD_2(timer_cmd,
1070 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1072 (channel->irq_moderation / res) - 1);
1074 EFX_POPULATE_DWORD_2(timer_cmd,
1075 TIMER_MODE, TIMER_MODE_DIS,
1078 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1083 /* Allocate buffer table entries for event queue */
1084 int falcon_probe_eventq(struct efx_channel *channel)
1086 struct efx_nic *efx = channel->efx;
1087 unsigned int evq_size;
1089 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1090 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1093 void falcon_init_eventq(struct efx_channel *channel)
1095 efx_oword_t evq_ptr;
1096 struct efx_nic *efx = channel->efx;
1098 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1099 channel->channel, channel->eventq.index,
1100 channel->eventq.index + channel->eventq.entries - 1);
1102 /* Pin event queue buffer */
1103 falcon_init_special_buffer(efx, &channel->eventq);
1105 /* Fill event queue with all ones (i.e. empty events) */
1106 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1108 /* Push event queue to card */
1109 EFX_POPULATE_OWORD_3(evq_ptr,
1111 EVQ_SIZE, FALCON_EVQ_ORDER,
1112 EVQ_BUF_BASE_ID, channel->eventq.index);
1113 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1116 falcon_set_int_moderation(channel);
1119 void falcon_fini_eventq(struct efx_channel *channel)
1121 efx_oword_t eventq_ptr;
1122 struct efx_nic *efx = channel->efx;
1124 /* Remove event queue from card */
1125 EFX_ZERO_OWORD(eventq_ptr);
1126 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1129 /* Unpin event queue */
1130 falcon_fini_special_buffer(efx, &channel->eventq);
1133 /* Free buffers backing event queue */
1134 void falcon_remove_eventq(struct efx_channel *channel)
1136 falcon_free_special_buffer(channel->efx, &channel->eventq);
1140 /* Generates a test event on the event queue. A subsequent call to
1141 * process_eventq() should pick up the event and place the value of
1142 * "magic" into channel->eventq_magic;
1144 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1146 efx_qword_t test_event;
1148 EFX_POPULATE_QWORD_2(test_event,
1149 EV_CODE, DRV_GEN_EV_DECODE,
1151 falcon_generate_event(channel, &test_event);
1154 /**************************************************************************
1158 **************************************************************************/
1161 static void falcon_poll_flush_events(struct efx_nic *efx)
1163 struct efx_channel *channel = &efx->channel[0];
1164 struct efx_tx_queue *tx_queue;
1165 struct efx_rx_queue *rx_queue;
1166 unsigned int read_ptr, i;
1168 read_ptr = channel->eventq_read_ptr;
1169 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1170 efx_qword_t *event = falcon_event(channel, read_ptr);
1171 int ev_code, ev_sub_code, ev_queue;
1173 if (!falcon_event_present(event))
1176 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1177 if (ev_code != DRIVER_EV_DECODE)
1180 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1181 switch (ev_sub_code) {
1182 case TX_DESCQ_FLS_DONE_EV_DECODE:
1183 ev_queue = EFX_QWORD_FIELD(*event,
1184 DRIVER_EV_TX_DESCQ_ID);
1185 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1186 tx_queue = efx->tx_queue + ev_queue;
1187 tx_queue->flushed = true;
1190 case RX_DESCQ_FLS_DONE_EV_DECODE:
1191 ev_queue = EFX_QWORD_FIELD(*event,
1192 DRIVER_EV_RX_DESCQ_ID);
1193 ev_failed = EFX_QWORD_FIELD(*event,
1194 DRIVER_EV_RX_FLUSH_FAIL);
1195 if (ev_queue < efx->n_rx_queues) {
1196 rx_queue = efx->rx_queue + ev_queue;
1198 /* retry the rx flush */
1200 falcon_flush_rx_queue(rx_queue);
1202 rx_queue->flushed = true;
1207 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1211 /* Handle tx and rx flushes at the same time, since they run in
1212 * parallel in the hardware and there's no reason for us to
1214 int falcon_flush_queues(struct efx_nic *efx)
1216 struct efx_rx_queue *rx_queue;
1217 struct efx_tx_queue *tx_queue;
1221 /* Issue flush requests */
1222 efx_for_each_tx_queue(tx_queue, efx) {
1223 tx_queue->flushed = false;
1224 falcon_flush_tx_queue(tx_queue);
1226 efx_for_each_rx_queue(rx_queue, efx) {
1227 rx_queue->flushed = false;
1228 falcon_flush_rx_queue(rx_queue);
1231 /* Poll the evq looking for flush completions. Since we're not pushing
1232 * any more rx or tx descriptors at this point, we're in no danger of
1233 * overflowing the evq whilst we wait */
1234 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1235 msleep(FALCON_FLUSH_INTERVAL);
1236 falcon_poll_flush_events(efx);
1238 /* Check if every queue has been succesfully flushed */
1239 outstanding = false;
1240 efx_for_each_tx_queue(tx_queue, efx)
1241 outstanding |= !tx_queue->flushed;
1242 efx_for_each_rx_queue(rx_queue, efx)
1243 outstanding |= !rx_queue->flushed;
1248 /* Mark the queues as all flushed. We're going to return failure
1249 * leading to a reset, or fake up success anyway. "flushed" now
1250 * indicates that we tried to flush. */
1251 efx_for_each_tx_queue(tx_queue, efx) {
1252 if (!tx_queue->flushed)
1253 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1255 tx_queue->flushed = true;
1257 efx_for_each_rx_queue(rx_queue, efx) {
1258 if (!rx_queue->flushed)
1259 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1261 rx_queue->flushed = true;
1264 if (EFX_WORKAROUND_7803(efx))
1270 /**************************************************************************
1272 * Falcon hardware interrupts
1273 * The hardware interrupt handler does very little work; all the event
1274 * queue processing is carried out by per-channel tasklets.
1276 **************************************************************************/
1278 /* Enable/disable/generate Falcon interrupts */
1279 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1282 efx_oword_t int_en_reg_ker;
1284 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1286 DRV_INT_EN_KER, enabled);
1287 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1290 void falcon_enable_interrupts(struct efx_nic *efx)
1292 efx_oword_t int_adr_reg_ker;
1293 struct efx_channel *channel;
1295 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1296 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1298 /* Program address */
1299 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1300 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1301 INT_ADR_KER, efx->irq_status.dma_addr);
1302 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1304 /* Enable interrupts */
1305 falcon_interrupts(efx, 1, 0);
1307 /* Force processing of all the channels to get the EVQ RPTRs up to
1309 efx_for_each_channel(channel, efx)
1310 efx_schedule_channel(channel);
1313 void falcon_disable_interrupts(struct efx_nic *efx)
1315 /* Disable interrupts */
1316 falcon_interrupts(efx, 0, 0);
1319 /* Generate a Falcon test interrupt
1320 * Interrupt must already have been enabled, otherwise nasty things
1323 void falcon_generate_interrupt(struct efx_nic *efx)
1325 falcon_interrupts(efx, 1, 1);
1328 /* Acknowledge a legacy interrupt from Falcon
1330 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1332 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1333 * BIU. Interrupt acknowledge is read sensitive so must write instead
1334 * (then read to ensure the BIU collector is flushed)
1336 * NB most hardware supports MSI interrupts
1338 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1342 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1343 falcon_writel(efx, ®, INT_ACK_REG_KER_A1);
1344 falcon_readl(efx, ®, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1347 /* Process a fatal interrupt
1348 * Disable bus mastering ASAP and schedule a reset
1350 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1352 struct falcon_nic_data *nic_data = efx->nic_data;
1353 efx_oword_t *int_ker = efx->irq_status.addr;
1354 efx_oword_t fatal_intr;
1355 int error, mem_perr;
1356 static int n_int_errors;
1358 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1359 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1361 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1362 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1363 EFX_OWORD_VAL(fatal_intr),
1364 error ? "disabling bus mastering" : "no recognised error");
1368 /* If this is a memory parity error dump which blocks are offending */
1369 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1372 falcon_read(efx, ®, MEM_STAT_REG_KER);
1373 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1374 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1377 /* Disable DMA bus mastering on both devices */
1378 pci_disable_device(efx->pci_dev);
1379 if (FALCON_IS_DUAL_FUNC(efx))
1380 pci_disable_device(nic_data->pci_dev2);
1382 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1383 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1384 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1386 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1387 "NIC will be disabled\n");
1388 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1394 /* Handle a legacy interrupt from Falcon
1395 * Acknowledges the interrupt and schedule event queue processing.
1397 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1399 struct efx_nic *efx = dev_id;
1400 efx_oword_t *int_ker = efx->irq_status.addr;
1401 struct efx_channel *channel;
1406 /* Read the ISR which also ACKs the interrupts */
1407 falcon_readl(efx, ®, INT_ISR0_B0);
1408 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1410 /* Check to see if we have a serious error condition */
1411 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1412 if (unlikely(syserr))
1413 return falcon_fatal_interrupt(efx);
1418 efx->last_irq_cpu = raw_smp_processor_id();
1419 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1420 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1422 /* Schedule processing of any interrupting queues */
1423 channel = &efx->channel[0];
1426 efx_schedule_channel(channel);
1435 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1437 struct efx_nic *efx = dev_id;
1438 efx_oword_t *int_ker = efx->irq_status.addr;
1439 struct efx_channel *channel;
1443 /* Check to see if this is our interrupt. If it isn't, we
1444 * exit without having touched the hardware.
1446 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1447 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1448 raw_smp_processor_id());
1451 efx->last_irq_cpu = raw_smp_processor_id();
1452 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1453 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1455 /* Check to see if we have a serious error condition */
1456 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1457 if (unlikely(syserr))
1458 return falcon_fatal_interrupt(efx);
1460 /* Determine interrupting queues, clear interrupt status
1461 * register and acknowledge the device interrupt.
1463 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1464 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1465 EFX_ZERO_OWORD(*int_ker);
1466 wmb(); /* Ensure the vector is cleared before interrupt ack */
1467 falcon_irq_ack_a1(efx);
1469 /* Schedule processing of any interrupting queues */
1470 channel = &efx->channel[0];
1473 efx_schedule_channel(channel);
1481 /* Handle an MSI interrupt from Falcon
1483 * Handle an MSI hardware interrupt. This routine schedules event
1484 * queue processing. No interrupt acknowledgement cycle is necessary.
1485 * Also, we never need to check that the interrupt is for us, since
1486 * MSI interrupts cannot be shared.
1488 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1490 struct efx_channel *channel = dev_id;
1491 struct efx_nic *efx = channel->efx;
1492 efx_oword_t *int_ker = efx->irq_status.addr;
1495 efx->last_irq_cpu = raw_smp_processor_id();
1496 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1497 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1499 /* Check to see if we have a serious error condition */
1500 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1501 if (unlikely(syserr))
1502 return falcon_fatal_interrupt(efx);
1504 /* Schedule processing of the channel */
1505 efx_schedule_channel(channel);
1511 /* Setup RSS indirection table.
1512 * This maps from the hash value of the packet to RXQ
1514 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1517 unsigned long offset;
1520 if (falcon_rev(efx) < FALCON_REV_B0)
1523 for (offset = RX_RSS_INDIR_TBL_B0;
1524 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1526 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1527 i % efx->n_rx_queues);
1528 falcon_writel(efx, &dword, offset);
1533 /* Hook interrupt handler(s)
1534 * Try MSI and then legacy interrupts.
1536 int falcon_init_interrupt(struct efx_nic *efx)
1538 struct efx_channel *channel;
1541 if (!EFX_INT_MODE_USE_MSI(efx)) {
1542 irq_handler_t handler;
1543 if (falcon_rev(efx) >= FALCON_REV_B0)
1544 handler = falcon_legacy_interrupt_b0;
1546 handler = falcon_legacy_interrupt_a1;
1548 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1551 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1558 /* Hook MSI or MSI-X interrupt */
1559 efx_for_each_channel(channel, efx) {
1560 rc = request_irq(channel->irq, falcon_msi_interrupt,
1561 IRQF_PROBE_SHARED, /* Not shared */
1562 efx->name, channel);
1564 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1572 efx_for_each_channel(channel, efx)
1573 free_irq(channel->irq, channel);
1578 void falcon_fini_interrupt(struct efx_nic *efx)
1580 struct efx_channel *channel;
1583 /* Disable MSI/MSI-X interrupts */
1584 efx_for_each_channel(channel, efx) {
1586 free_irq(channel->irq, channel);
1589 /* ACK legacy interrupt */
1590 if (falcon_rev(efx) >= FALCON_REV_B0)
1591 falcon_read(efx, ®, INT_ISR0_B0);
1593 falcon_irq_ack_a1(efx);
1595 /* Disable legacy interrupt */
1596 if (efx->legacy_irq)
1597 free_irq(efx->legacy_irq, efx);
1600 /**************************************************************************
1604 **************************************************************************
1607 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1609 /* Wait for SPI command completion */
1610 static int falcon_spi_wait(struct efx_nic *efx)
1612 unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
1614 bool cmd_en, timer_active;
1617 falcon_read(efx, ®, EE_SPI_HCMD_REG_KER);
1618 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1619 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1620 if (!cmd_en && !timer_active)
1622 if (time_after_eq(jiffies, timeout)) {
1623 EFX_ERR(efx, "timed out waiting for SPI\n");
1630 static int falcon_spi_cmd(const struct efx_spi_device *spi,
1631 unsigned int command, int address,
1632 const void *in, void *out, unsigned int len)
1634 struct efx_nic *efx = spi->efx;
1635 bool addressed = (address >= 0);
1636 bool reading = (out != NULL);
1640 /* Input validation */
1641 if (len > FALCON_SPI_MAX_LEN)
1644 /* Check SPI not currently being accessed */
1645 rc = falcon_spi_wait(efx);
1649 /* Program address register, if we have an address */
1651 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1652 falcon_write(efx, ®, EE_SPI_HADR_REG_KER);
1655 /* Program data register, if we have data */
1657 memcpy(®, in, len);
1658 falcon_write(efx, ®, EE_SPI_HDATA_REG_KER);
1661 /* Issue read/write command */
1662 EFX_POPULATE_OWORD_7(reg,
1663 EE_SPI_HCMD_CMD_EN, 1,
1664 EE_SPI_HCMD_SF_SEL, spi->device_id,
1665 EE_SPI_HCMD_DABCNT, len,
1666 EE_SPI_HCMD_READ, reading,
1667 EE_SPI_HCMD_DUBCNT, 0,
1669 (addressed ? spi->addr_len : 0),
1670 EE_SPI_HCMD_ENC, command);
1671 falcon_write(efx, ®, EE_SPI_HCMD_REG_KER);
1673 /* Wait for read/write to complete */
1674 rc = falcon_spi_wait(efx);
1680 falcon_read(efx, ®, EE_SPI_HDATA_REG_KER);
1681 memcpy(out, ®, len);
1688 falcon_spi_write_limit(const struct efx_spi_device *spi, unsigned int start)
1690 return min(FALCON_SPI_MAX_LEN,
1691 (spi->block_size - (start & (spi->block_size - 1))));
1695 efx_spi_munge_command(const struct efx_spi_device *spi,
1696 const u8 command, const unsigned int address)
1698 return command | (((address >> 8) & spi->munge_address) << 3);
1702 static int falcon_spi_fast_wait(const struct efx_spi_device *spi)
1707 /* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
1708 for (i = 0; i < 50; i++) {
1711 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1712 &status, sizeof(status));
1715 if (!(status & SPI_STATUS_NRDY))
1719 "timed out waiting for device %d last status=0x%02x\n",
1720 spi->device_id, status);
1724 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1725 size_t len, size_t *retlen, u8 *buffer)
1727 unsigned int command, block_len, pos = 0;
1731 block_len = min((unsigned int)len - pos,
1732 FALCON_SPI_MAX_LEN);
1734 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1735 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1736 buffer + pos, block_len);
1741 /* Avoid locking up the system */
1743 if (signal_pending(current)) {
1754 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1755 size_t len, size_t *retlen, const u8 *buffer)
1757 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1758 unsigned int command, block_len, pos = 0;
1762 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1766 block_len = min((unsigned int)len - pos,
1767 falcon_spi_write_limit(spi, start + pos));
1768 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1769 rc = falcon_spi_cmd(spi, command, start + pos,
1770 buffer + pos, NULL, block_len);
1774 rc = falcon_spi_fast_wait(spi);
1778 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1779 rc = falcon_spi_cmd(spi, command, start + pos,
1780 NULL, verify_buffer, block_len);
1781 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1788 /* Avoid locking up the system */
1790 if (signal_pending(current)) {
1801 /**************************************************************************
1805 **************************************************************************
1807 void falcon_drain_tx_fifo(struct efx_nic *efx)
1812 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1813 (efx->loopback_mode != LOOPBACK_NONE))
1816 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1817 /* There is no point in draining more than once */
1818 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1821 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1822 * the drain sequence with the statistics fetch */
1823 spin_lock(&efx->stats_lock);
1825 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1826 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1828 /* Reset the MAC and EM block. */
1829 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1830 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1831 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1832 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1833 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1837 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1838 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1839 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1840 !EFX_OWORD_FIELD(temp, RST_EM)) {
1841 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1846 EFX_ERR(efx, "MAC reset failed\n");
1853 spin_unlock(&efx->stats_lock);
1855 /* If we've reset the EM block and the link is up, then
1856 * we'll have to kick the XAUI link so the PHY can recover */
1857 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1858 falcon_reset_xaui(efx);
1861 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1865 if (falcon_rev(efx) < FALCON_REV_B0)
1868 /* Isolate the MAC -> RX */
1869 falcon_read(efx, &temp, RX_CFG_REG_KER);
1870 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1871 falcon_write(efx, &temp, RX_CFG_REG_KER);
1874 falcon_drain_tx_fifo(efx);
1877 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1883 if (efx->link_options & GM_LPA_10000)
1885 else if (efx->link_options & GM_LPA_1000)
1887 else if (efx->link_options & GM_LPA_100)
1891 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1892 * as advertised. Disable to ensure packets are not
1893 * indefinitely held and TX queue can be flushed at any point
1894 * while the link is down. */
1895 EFX_POPULATE_OWORD_5(reg,
1896 MAC_XOFF_VAL, 0xffff /* max pause time */,
1898 MAC_UC_PROM, efx->promiscuous,
1899 MAC_LINK_STATUS, 1, /* always set */
1900 MAC_SPEED, link_speed);
1901 /* On B0, MAC backpressure can be disabled and packets get
1903 if (falcon_rev(efx) >= FALCON_REV_B0) {
1904 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1908 falcon_write(efx, ®, MAC0_CTRL_REG_KER);
1910 /* Restore the multicast hash registers. */
1911 falcon_set_multicast_hash(efx);
1913 /* Transmission of pause frames when RX crosses the threshold is
1914 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1915 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1916 tx_fc = !!(efx->flow_control & EFX_FC_TX);
1917 falcon_read(efx, ®, RX_CFG_REG_KER);
1918 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1920 /* Unisolate the MAC -> RX */
1921 if (falcon_rev(efx) >= FALCON_REV_B0)
1922 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1923 falcon_write(efx, ®, RX_CFG_REG_KER);
1926 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1932 if (disable_dma_stats)
1935 /* Statistics fetch will fail if the MAC is in TX drain */
1936 if (falcon_rev(efx) >= FALCON_REV_B0) {
1938 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1939 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1943 dma_done = (efx->stats_buffer.addr + done_offset);
1944 *dma_done = FALCON_STATS_NOT_DONE;
1945 wmb(); /* ensure done flag is clear */
1947 /* Initiate DMA transfer of stats */
1948 EFX_POPULATE_OWORD_2(reg,
1949 MAC_STAT_DMA_CMD, 1,
1951 efx->stats_buffer.dma_addr);
1952 falcon_write(efx, ®, MAC0_STAT_DMA_REG_KER);
1954 /* Wait for transfer to complete */
1955 for (i = 0; i < 400; i++) {
1956 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
1957 rmb(); /* Ensure the stats are valid. */
1963 EFX_ERR(efx, "timed out waiting for statistics\n");
1967 /**************************************************************************
1969 * PHY access via GMII
1971 **************************************************************************
1974 /* Use the top bit of the MII PHY id to indicate the PHY type
1975 * (1G/10G), with the remaining bits as the actual PHY id.
1977 * This allows us to avoid leaking information from the mii_if_info
1978 * structure into other data structures.
1980 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1981 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1982 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1983 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1984 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1987 /* Packing the clause 45 port and device fields into a single value */
1988 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1989 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1990 #define MD_DEV_ADR_COMP_LBN 0
1991 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1994 /* Wait for GMII access to complete */
1995 static int falcon_gmii_wait(struct efx_nic *efx)
1997 efx_dword_t md_stat;
2000 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
2001 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2002 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2003 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2004 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2005 EFX_ERR(efx, "error from GMII access "
2007 EFX_DWORD_VAL(md_stat));
2014 EFX_ERR(efx, "timed out waiting for GMII\n");
2018 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2019 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2020 int addr, int value)
2022 struct efx_nic *efx = netdev_priv(net_dev);
2023 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2026 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2027 * chosen so that the only current user, Falcon, can take the
2028 * packed value and use them directly.
2029 * Fail to build if this assumption is broken.
2031 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2032 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2033 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2034 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2036 if (phy_id2 == PHY_ADDR_INVALID)
2039 /* See falcon_mdio_read for an explanation. */
2040 if (!(phy_id & FALCON_PHY_ID_10G)) {
2041 int mmd = ffs(efx->phy_op->mmds) - 1;
2042 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2043 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2044 & FALCON_PHY_ID_ID_MASK;
2047 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2050 spin_lock_bh(&efx->phy_lock);
2052 /* Check MII not currently being accessed */
2053 if (falcon_gmii_wait(efx) != 0)
2056 /* Write the address/ID register */
2057 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2058 falcon_write(efx, ®, MD_PHY_ADR_REG_KER);
2060 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2061 falcon_write(efx, ®, MD_ID_REG_KER);
2064 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2065 falcon_write(efx, ®, MD_TXD_REG_KER);
2067 EFX_POPULATE_OWORD_2(reg,
2070 falcon_write(efx, ®, MD_CS_REG_KER);
2072 /* Wait for data to be written */
2073 if (falcon_gmii_wait(efx) != 0) {
2074 /* Abort the write operation */
2075 EFX_POPULATE_OWORD_2(reg,
2078 falcon_write(efx, ®, MD_CS_REG_KER);
2083 spin_unlock_bh(&efx->phy_lock);
2086 /* Reads a GMII register from a PHY connected to Falcon. If no value
2087 * could be read, -1 will be returned. */
2088 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2090 struct efx_nic *efx = netdev_priv(net_dev);
2091 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2095 if (phy_addr == PHY_ADDR_INVALID)
2098 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2099 * but the generic Linux code does not make any distinction or have
2100 * any state for this.
2101 * We spot the case where someone tried to talk 22 to a 45 PHY and
2102 * redirect the request to the lowest numbered MMD as a clause45
2103 * request. This is enough to allow simple queries like id and link
2104 * state to succeed. TODO: We may need to do more in future.
2106 if (!(phy_id & FALCON_PHY_ID_10G)) {
2107 int mmd = ffs(efx->phy_op->mmds) - 1;
2108 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2109 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2110 & FALCON_PHY_ID_ID_MASK;
2113 spin_lock_bh(&efx->phy_lock);
2115 /* Check MII not currently being accessed */
2116 if (falcon_gmii_wait(efx) != 0)
2119 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2120 falcon_write(efx, ®, MD_PHY_ADR_REG_KER);
2122 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2123 falcon_write(efx, ®, MD_ID_REG_KER);
2125 /* Request data to be read */
2126 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2127 falcon_write(efx, ®, MD_CS_REG_KER);
2129 /* Wait for data to become available */
2130 value = falcon_gmii_wait(efx);
2132 falcon_read(efx, ®, MD_RXD_REG_KER);
2133 value = EFX_OWORD_FIELD(reg, MD_RXD);
2134 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2135 phy_id, addr, value);
2137 /* Abort the read operation */
2138 EFX_POPULATE_OWORD_2(reg,
2141 falcon_write(efx, ®, MD_CS_REG_KER);
2143 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2144 "error %d\n", phy_id, addr, value);
2148 spin_unlock_bh(&efx->phy_lock);
2153 static void falcon_init_mdio(struct mii_if_info *gmii)
2155 gmii->mdio_read = falcon_mdio_read;
2156 gmii->mdio_write = falcon_mdio_write;
2157 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2158 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2161 static int falcon_probe_phy(struct efx_nic *efx)
2163 switch (efx->phy_type) {
2164 case PHY_TYPE_10XPRESS:
2165 efx->phy_op = &falcon_tenxpress_phy_ops;
2168 efx->phy_op = &falcon_xfp_phy_ops;
2171 EFX_ERR(efx, "Unknown PHY type %d\n",
2176 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2180 /* This call is responsible for hooking in the MAC and PHY operations */
2181 int falcon_probe_port(struct efx_nic *efx)
2185 /* Hook in PHY operations table */
2186 rc = falcon_probe_phy(efx);
2190 /* Set up GMII structure for PHY */
2191 efx->mii.supports_gmii = true;
2192 falcon_init_mdio(&efx->mii);
2194 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2195 if (falcon_rev(efx) >= FALCON_REV_B0)
2196 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2198 efx->flow_control = EFX_FC_RX;
2200 /* Allocate buffer for stats */
2201 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2202 FALCON_MAC_STATS_SIZE);
2205 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2206 (unsigned long long)efx->stats_buffer.dma_addr,
2207 efx->stats_buffer.addr,
2208 virt_to_phys(efx->stats_buffer.addr));
2213 void falcon_remove_port(struct efx_nic *efx)
2215 falcon_free_buffer(efx, &efx->stats_buffer);
2218 /**************************************************************************
2220 * Multicast filtering
2222 **************************************************************************
2225 void falcon_set_multicast_hash(struct efx_nic *efx)
2227 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2229 /* Broadcast packets go through the multicast hash filter.
2230 * ether_crc_le() of the broadcast address is 0xbe2612ff
2231 * so we always add bit 0xff to the mask.
2233 set_bit_le(0xff, mc_hash->byte);
2235 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2236 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2240 /**************************************************************************
2244 **************************************************************************/
2246 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2248 struct falcon_nvconfig *nvconfig;
2249 struct efx_spi_device *spi;
2251 int rc, magic_num, struct_ver;
2252 __le16 *word, *limit;
2255 region = kmalloc(NVCONFIG_END, GFP_KERNEL);
2258 nvconfig = region + NVCONFIG_OFFSET;
2260 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2261 rc = falcon_spi_read(spi, 0, NVCONFIG_END, NULL, region);
2263 EFX_ERR(efx, "Failed to read %s\n",
2264 efx->spi_flash ? "flash" : "EEPROM");
2269 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2270 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2273 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2274 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2277 if (struct_ver < 2) {
2278 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2280 } else if (struct_ver < 4) {
2281 word = &nvconfig->board_magic_num;
2282 limit = (__le16 *) (nvconfig + 1);
2285 limit = region + NVCONFIG_END;
2287 for (csum = 0; word < limit; ++word)
2288 csum += le16_to_cpu(*word);
2290 if (~csum & 0xffff) {
2291 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2297 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2304 /* Registers tested in the falcon register test */
2308 } efx_test_registers[] = {
2309 { ADR_REGION_REG_KER,
2310 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2312 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2314 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2316 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2317 { MAC0_CTRL_REG_KER,
2318 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2319 { SRM_TX_DC_CFG_REG_KER,
2320 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2321 { RX_DC_CFG_REG_KER,
2322 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2323 { RX_DC_PF_WM_REG_KER,
2324 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2326 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2328 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2330 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2332 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2334 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2336 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2338 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2340 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2343 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2344 const efx_oword_t *mask)
2346 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2347 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2350 int falcon_test_registers(struct efx_nic *efx)
2352 unsigned address = 0, i, j;
2353 efx_oword_t mask, imask, original, reg, buf;
2355 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2356 WARN_ON(!LOOPBACK_INTERNAL(efx));
2358 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2359 address = efx_test_registers[i].address;
2360 mask = imask = efx_test_registers[i].mask;
2361 EFX_INVERT_OWORD(imask);
2363 falcon_read(efx, &original, address);
2365 /* bit sweep on and off */
2366 for (j = 0; j < 128; j++) {
2367 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2370 /* Test this testable bit can be set in isolation */
2371 EFX_AND_OWORD(reg, original, mask);
2372 EFX_SET_OWORD32(reg, j, j, 1);
2374 falcon_write(efx, ®, address);
2375 falcon_read(efx, &buf, address);
2377 if (efx_masked_compare_oword(®, &buf, &mask))
2380 /* Test this testable bit can be cleared in isolation */
2381 EFX_OR_OWORD(reg, original, mask);
2382 EFX_SET_OWORD32(reg, j, j, 0);
2384 falcon_write(efx, ®, address);
2385 falcon_read(efx, &buf, address);
2387 if (efx_masked_compare_oword(®, &buf, &mask))
2391 falcon_write(efx, &original, address);
2397 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2398 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2399 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2403 /**************************************************************************
2407 **************************************************************************
2410 /* Resets NIC to known state. This routine must be called in process
2411 * context and is allowed to sleep. */
2412 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2414 struct falcon_nic_data *nic_data = efx->nic_data;
2415 efx_oword_t glb_ctl_reg_ker;
2418 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2420 /* Initiate device reset */
2421 if (method == RESET_TYPE_WORLD) {
2422 rc = pci_save_state(efx->pci_dev);
2424 EFX_ERR(efx, "failed to backup PCI state of primary "
2425 "function prior to hardware reset\n");
2428 if (FALCON_IS_DUAL_FUNC(efx)) {
2429 rc = pci_save_state(nic_data->pci_dev2);
2431 EFX_ERR(efx, "failed to backup PCI state of "
2432 "secondary function prior to "
2433 "hardware reset\n");
2438 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2439 EXT_PHY_RST_DUR, 0x7,
2442 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2443 EXCLUDE_FROM_RESET : 0);
2445 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2446 EXT_PHY_RST_CTL, reset_phy,
2447 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2448 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2449 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2450 EE_RST_CTL, EXCLUDE_FROM_RESET,
2451 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2454 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2456 EFX_LOG(efx, "waiting for hardware reset\n");
2457 schedule_timeout_uninterruptible(HZ / 20);
2459 /* Restore PCI configuration if needed */
2460 if (method == RESET_TYPE_WORLD) {
2461 if (FALCON_IS_DUAL_FUNC(efx)) {
2462 rc = pci_restore_state(nic_data->pci_dev2);
2464 EFX_ERR(efx, "failed to restore PCI config for "
2465 "the secondary function\n");
2469 rc = pci_restore_state(efx->pci_dev);
2471 EFX_ERR(efx, "failed to restore PCI config for the "
2472 "primary function\n");
2475 EFX_LOG(efx, "successfully restored PCI config\n");
2478 /* Assert that reset complete */
2479 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2480 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2482 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2485 EFX_LOG(efx, "hardware reset complete\n");
2489 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2492 pci_restore_state(efx->pci_dev);
2499 /* Zeroes out the SRAM contents. This routine must be called in
2500 * process context and is allowed to sleep.
2502 static int falcon_reset_sram(struct efx_nic *efx)
2504 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2507 /* Set the SRAM wake/sleep GPIO appropriately. */
2508 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2509 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2510 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2511 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2513 /* Initiate SRAM reset */
2514 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2515 SRAM_OOB_BT_INIT_EN, 1,
2516 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2517 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2519 /* Wait for SRAM reset to complete */
2522 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2524 /* SRAM reset is slow; expect around 16ms */
2525 schedule_timeout_uninterruptible(HZ / 50);
2527 /* Check for reset complete */
2528 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2529 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2530 EFX_LOG(efx, "SRAM reset complete\n");
2534 } while (++count < 20); /* wait upto 0.4 sec */
2536 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2540 static int falcon_spi_device_init(struct efx_nic *efx,
2541 struct efx_spi_device **spi_device_ret,
2542 unsigned int device_id, u32 device_type)
2544 struct efx_spi_device *spi_device;
2546 if (device_type != 0) {
2547 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2550 spi_device->device_id = device_id;
2552 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2553 spi_device->addr_len =
2554 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2555 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2556 spi_device->addr_len == 1);
2557 spi_device->block_size =
2558 1 << SPI_DEV_TYPE_FIELD(device_type,
2559 SPI_DEV_TYPE_BLOCK_SIZE);
2561 spi_device->efx = efx;
2566 kfree(*spi_device_ret);
2567 *spi_device_ret = spi_device;
2572 static void falcon_remove_spi_devices(struct efx_nic *efx)
2574 kfree(efx->spi_eeprom);
2575 efx->spi_eeprom = NULL;
2576 kfree(efx->spi_flash);
2577 efx->spi_flash = NULL;
2580 /* Extract non-volatile configuration */
2581 static int falcon_probe_nvconfig(struct efx_nic *efx)
2583 struct falcon_nvconfig *nvconfig;
2587 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2591 rc = falcon_read_nvram(efx, nvconfig);
2592 if (rc == -EINVAL) {
2593 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2594 efx->phy_type = PHY_TYPE_NONE;
2595 efx->mii.phy_id = PHY_ADDR_INVALID;
2601 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2602 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2604 efx->phy_type = v2->port0_phy_type;
2605 efx->mii.phy_id = v2->port0_phy_addr;
2606 board_rev = le16_to_cpu(v2->board_revision);
2608 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2609 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2610 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2611 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2616 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2624 /* Read the MAC addresses */
2625 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2627 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2629 efx_set_board_info(efx, board_rev);
2635 falcon_remove_spi_devices(efx);
2641 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2642 * count, port speed). Set workaround and feature flags accordingly.
2644 static int falcon_probe_nic_variant(struct efx_nic *efx)
2646 efx_oword_t altera_build;
2648 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2649 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2650 EFX_ERR(efx, "Falcon FPGA not supported\n");
2654 switch (falcon_rev(efx)) {
2657 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2660 case FALCON_REV_A1:{
2661 efx_oword_t nic_stat;
2663 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2665 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2666 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2669 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2670 EFX_ERR(efx, "1G mode not supported\n");
2680 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2687 /* Probe all SPI devices on the NIC */
2688 static void falcon_probe_spi_devices(struct efx_nic *efx)
2690 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2691 bool has_flash, has_eeprom, boot_is_external;
2693 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2694 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2695 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2697 has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
2698 has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
2699 boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
2702 /* Default flash SPI device: Atmel AT25F1024
2703 * 128 KB, 24-bit address, 32 KB erase block,
2706 u32 flash_device_type =
2707 (17 << SPI_DEV_TYPE_SIZE_LBN)
2708 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2709 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
2710 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
2711 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2713 falcon_spi_device_init(efx, &efx->spi_flash,
2714 EE_SPI_FLASH, flash_device_type);
2716 if (!boot_is_external) {
2717 /* Disable VPD and set clock dividers to safe
2718 * values for initial programming.
2720 EFX_LOG(efx, "Booted from internal ASIC settings;"
2721 " setting SPI config\n");
2722 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2723 /* 125 MHz / 7 ~= 20 MHz */
2725 /* 125 MHz / 63 ~= 2 MHz */
2726 EE_EE_CLOCK_DIV, 63);
2727 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2732 u32 eeprom_device_type;
2734 /* If it has no flash, it must have a large EEPROM
2735 * for chip config; otherwise check whether 9-bit
2736 * addressing is used for VPD configuration
2739 (!boot_is_external ||
2740 EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
2741 /* Default SPI device: Atmel AT25040 or similar
2742 * 512 B, 9-bit address, 8 B write block
2744 eeprom_device_type =
2745 (9 << SPI_DEV_TYPE_SIZE_LBN)
2746 | (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2747 | (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2749 /* "Large" SPI device: Atmel AT25640 or similar
2750 * 8 KB, 16-bit address, 32 B write block
2752 eeprom_device_type =
2753 (13 << SPI_DEV_TYPE_SIZE_LBN)
2754 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2755 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2758 falcon_spi_device_init(efx, &efx->spi_eeprom,
2759 EE_SPI_EEPROM, eeprom_device_type);
2762 EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
2763 (has_flash ? "present" : "absent"),
2764 (has_eeprom ? "present" : "absent"));
2767 int falcon_probe_nic(struct efx_nic *efx)
2769 struct falcon_nic_data *nic_data;
2772 /* Allocate storage for hardware specific data */
2773 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2776 efx->nic_data = nic_data;
2778 /* Determine number of ports etc. */
2779 rc = falcon_probe_nic_variant(efx);
2783 /* Probe secondary function if expected */
2784 if (FALCON_IS_DUAL_FUNC(efx)) {
2785 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2787 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2789 if (dev->bus == efx->pci_dev->bus &&
2790 dev->devfn == efx->pci_dev->devfn + 1) {
2791 nic_data->pci_dev2 = dev;
2795 if (!nic_data->pci_dev2) {
2796 EFX_ERR(efx, "failed to find secondary function\n");
2802 /* Now we can reset the NIC */
2803 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2805 EFX_ERR(efx, "failed to reset NIC\n");
2809 /* Allocate memory for INT_KER */
2810 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2813 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2815 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2816 (unsigned long long)efx->irq_status.dma_addr,
2817 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2819 falcon_probe_spi_devices(efx);
2821 /* Read in the non-volatile configuration */
2822 rc = falcon_probe_nvconfig(efx);
2826 /* Initialise I2C adapter */
2827 efx->i2c_adap.owner = THIS_MODULE;
2828 nic_data->i2c_data = falcon_i2c_bit_operations;
2829 nic_data->i2c_data.data = efx;
2830 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2831 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2832 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2833 rc = i2c_bit_add_bus(&efx->i2c_adap);
2840 falcon_remove_spi_devices(efx);
2841 falcon_free_buffer(efx, &efx->irq_status);
2844 if (nic_data->pci_dev2) {
2845 pci_dev_put(nic_data->pci_dev2);
2846 nic_data->pci_dev2 = NULL;
2850 kfree(efx->nic_data);
2854 /* This call performs hardware-specific global initialisation, such as
2855 * defining the descriptor cache sizes and number of RSS channels.
2856 * It does not set up any buffers, descriptor rings or event queues.
2858 int falcon_init_nic(struct efx_nic *efx)
2864 /* Set up the address region register. This is only needed
2865 * for the B0 FPGA, but since we are just pushing in the
2866 * reset defaults this may as well be unconditional. */
2867 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2868 ADR_REGION1, (1 << 16),
2869 ADR_REGION2, (2 << 16),
2870 ADR_REGION3, (3 << 16));
2871 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2873 /* Use on-chip SRAM */
2874 falcon_read(efx, &temp, NIC_STAT_REG);
2875 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2876 falcon_write(efx, &temp, NIC_STAT_REG);
2878 /* Set buffer table mode */
2879 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2880 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2882 rc = falcon_reset_sram(efx);
2886 /* Set positions of descriptor caches in SRAM. */
2887 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2888 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2889 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2890 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2892 /* Set TX descriptor cache size. */
2893 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2894 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2895 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2897 /* Set RX descriptor cache size. Set low watermark to size-8, as
2898 * this allows most efficient prefetching.
2900 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2901 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2902 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2903 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2904 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2906 /* Clear the parity enables on the TX data fifos as
2907 * they produce false parity errors because of timing issues
2909 if (EFX_WORKAROUND_5129(efx)) {
2910 falcon_read(efx, &temp, SPARE_REG_KER);
2911 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2912 falcon_write(efx, &temp, SPARE_REG_KER);
2915 /* Enable all the genuinely fatal interrupts. (They are still
2916 * masked by the overall interrupt mask, controlled by
2917 * falcon_interrupts()).
2919 * Note: All other fatal interrupts are enabled
2921 EFX_POPULATE_OWORD_3(temp,
2922 ILL_ADR_INT_KER_EN, 1,
2923 RBUF_OWN_INT_KER_EN, 1,
2924 TBUF_OWN_INT_KER_EN, 1);
2925 EFX_INVERT_OWORD(temp);
2926 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2928 if (EFX_WORKAROUND_7244(efx)) {
2929 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2930 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2931 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2932 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2933 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2934 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2937 falcon_setup_rss_indir_table(efx);
2939 /* Setup RX. Wait for descriptor is broken and must
2940 * be disabled. RXDP recovery shouldn't be needed, but is.
2942 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2943 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2944 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2945 if (EFX_WORKAROUND_5583(efx))
2946 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2947 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2949 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2950 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2952 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2953 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2954 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2955 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2956 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2957 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2958 /* Enable SW_EV to inherit in char driver - assume harmless here */
2959 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2960 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2961 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2962 /* Squash TX of packets of 16 bytes or less */
2963 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2964 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2965 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2967 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2968 * descriptors (which is bad).
2970 falcon_read(efx, &temp, TX_CFG_REG_KER);
2971 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2972 falcon_write(efx, &temp, TX_CFG_REG_KER);
2975 falcon_read(efx, &temp, RX_CFG_REG_KER);
2976 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2977 if (EFX_WORKAROUND_7575(efx))
2978 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2980 if (falcon_rev(efx) >= FALCON_REV_B0)
2981 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2983 /* RX FIFO flow control thresholds */
2984 thresh = ((rx_xon_thresh_bytes >= 0) ?
2985 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2986 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2987 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2988 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2989 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2990 /* RX control FIFO thresholds [32 entries] */
2991 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
2992 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
2993 falcon_write(efx, &temp, RX_CFG_REG_KER);
2995 /* Set destination of both TX and RX Flush events */
2996 if (falcon_rev(efx) >= FALCON_REV_B0) {
2997 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2998 falcon_write(efx, &temp, DP_CTRL_REG);
3004 void falcon_remove_nic(struct efx_nic *efx)
3006 struct falcon_nic_data *nic_data = efx->nic_data;
3009 rc = i2c_del_adapter(&efx->i2c_adap);
3012 falcon_remove_spi_devices(efx);
3013 falcon_free_buffer(efx, &efx->irq_status);
3015 falcon_reset_hw(efx, RESET_TYPE_ALL);
3017 /* Release the second function after the reset */
3018 if (nic_data->pci_dev2) {
3019 pci_dev_put(nic_data->pci_dev2);
3020 nic_data->pci_dev2 = NULL;
3023 /* Tear down the private nic state */
3024 kfree(efx->nic_data);
3025 efx->nic_data = NULL;
3028 void falcon_update_nic_stats(struct efx_nic *efx)
3032 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3033 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3036 /**************************************************************************
3038 * Revision-dependent attributes used by efx.c
3040 **************************************************************************
3043 struct efx_nic_type falcon_a_nic_type = {
3045 .mem_map_size = 0x20000,
3046 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3047 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3048 .buf_tbl_base = BUF_TBL_KER_A1,
3049 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3050 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3051 .txd_ring_mask = FALCON_TXD_RING_MASK,
3052 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3053 .evq_size = FALCON_EVQ_SIZE,
3054 .max_dma_mask = FALCON_DMA_MASK,
3055 .tx_dma_mask = FALCON_TX_DMA_MASK,
3056 .bug5391_mask = 0xf,
3057 .rx_xoff_thresh = 2048,
3058 .rx_xon_thresh = 512,
3059 .rx_buffer_padding = 0x24,
3060 .max_interrupt_mode = EFX_INT_MODE_MSI,
3061 .phys_addr_channels = 4,
3064 struct efx_nic_type falcon_b_nic_type = {
3066 /* Map everything up to and including the RSS indirection
3067 * table. Don't map MSI-X table, MSI-X PBA since Linux
3068 * requires that they not be mapped. */
3069 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3070 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3071 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3072 .buf_tbl_base = BUF_TBL_KER_B0,
3073 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3074 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3075 .txd_ring_mask = FALCON_TXD_RING_MASK,
3076 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3077 .evq_size = FALCON_EVQ_SIZE,
3078 .max_dma_mask = FALCON_DMA_MASK,
3079 .tx_dma_mask = FALCON_TX_DMA_MASK,
3081 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3082 .rx_xon_thresh = 27648, /* ~3*max MTU */
3083 .rx_buffer_padding = 0,
3084 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3085 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3086 * interrupt handler only supports 32