2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/firmware.h>
29 #include <linux/pci-aspm.h>
30 #include <linux/prefetch.h>
32 #include <asm/system.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define assert(expr) \
49 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
50 #expr,__FILE__,__func__,__LINE__); \
52 #define dprintk(fmt, args...) \
53 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
55 #define assert(expr) do {} while (0)
56 #define dprintk(fmt, args...) do {} while (0)
57 #endif /* RTL8169_DEBUG */
59 #define R8169_MSG_DEFAULT \
60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
62 #define TX_BUFFS_AVAIL(tp) \
63 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
67 static const int multicast_filter_limit = 32;
69 /* MAC address length */
70 #define MAC_ADDR_LEN 6
72 #define MAX_READ_REQUEST_SHIFT 12
73 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
74 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
76 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
77 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
79 #define R8169_REGS_SIZE 256
80 #define R8169_NAPI_WEIGHT 64
81 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
82 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
84 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
85 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
87 #define RTL8169_TX_TIMEOUT (6*HZ)
88 #define RTL8169_PHY_TIMEOUT (10*HZ)
90 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
91 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
92 #define RTL_EEPROM_SIG_ADDR 0x0000
94 /* write/read MMIO register */
95 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
96 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
97 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
98 #define RTL_R8(reg) readb (ioaddr + (reg))
99 #define RTL_R16(reg) readw (ioaddr + (reg))
100 #define RTL_R32(reg) readl (ioaddr + (reg))
103 RTL_GIGA_MAC_VER_01 = 0,
136 RTL_GIGA_MAC_NONE = 0xff,
139 enum rtl_tx_desc_version {
144 #define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
147 static const struct {
149 enum rtl_tx_desc_version txd_version;
151 } rtl_chip_infos[] = {
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
229 static void rtl_hw_start_8169(struct net_device *);
230 static void rtl_hw_start_8168(struct net_device *);
231 static void rtl_hw_start_8101(struct net_device *);
233 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
239 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
240 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
242 { PCI_VENDOR_ID_LINKSYS, 0x1032,
243 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
245 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
249 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
251 static int rx_buf_sz = 16383;
258 MAC0 = 0, /* Ethernet hardware address. */
260 MAR0 = 8, /* Multicast filter. */
261 CounterAddrLow = 0x10,
262 CounterAddrHigh = 0x14,
263 TxDescStartAddrLow = 0x20,
264 TxDescStartAddrHigh = 0x24,
265 TxHDescStartAddrLow = 0x28,
266 TxHDescStartAddrHigh = 0x2c,
276 #define RTL_RX_CONFIG_MASK 0xff7e1880u
292 RxDescAddrLow = 0xe4,
293 RxDescAddrHigh = 0xe8,
294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
296 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
300 #define TxPacketMax (8064 >> 7)
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
305 FuncForceEvent = 0xfc,
308 enum rtl8110_registers {
314 enum rtl8168_8101_registers {
317 #define CSIAR_FLAG 0x80000000
318 #define CSIAR_WRITE_CMD 0x80000000
319 #define CSIAR_BYTE_ENABLE 0x0f
320 #define CSIAR_BYTE_ENABLE_SHIFT 12
321 #define CSIAR_ADDR_MASK 0x0fff
324 #define EPHYAR_FLAG 0x80000000
325 #define EPHYAR_WRITE_CMD 0x80000000
326 #define EPHYAR_REG_MASK 0x1f
327 #define EPHYAR_REG_SHIFT 16
328 #define EPHYAR_DATA_MASK 0xffff
330 #define PM_SWITCH (1 << 6)
332 #define FIX_NAK_1 (1 << 4)
333 #define FIX_NAK_2 (1 << 3)
336 #define EN_NDP (1 << 3)
337 #define EN_OOB_RESET (1 << 2)
339 #define EFUSEAR_FLAG 0x80000000
340 #define EFUSEAR_WRITE_CMD 0x80000000
341 #define EFUSEAR_READ_CMD 0x00000000
342 #define EFUSEAR_REG_MASK 0x03ff
343 #define EFUSEAR_REG_SHIFT 8
344 #define EFUSEAR_DATA_MASK 0xff
347 enum rtl8168_registers {
350 #define ERIAR_FLAG 0x80000000
351 #define ERIAR_WRITE_CMD 0x80000000
352 #define ERIAR_READ_CMD 0x00000000
353 #define ERIAR_ADDR_BYTE_ALIGN 4
354 #define ERIAR_EXGMAC 0
357 #define ERIAR_TYPE_SHIFT 16
358 #define ERIAR_BYTEEN 0x0f
359 #define ERIAR_BYTEEN_SHIFT 12
360 EPHY_RXER_NUM = 0x7c,
361 OCPDR = 0xb0, /* OCP GPHY access */
362 #define OCPDR_WRITE_CMD 0x80000000
363 #define OCPDR_READ_CMD 0x00000000
364 #define OCPDR_REG_MASK 0x7f
365 #define OCPDR_GPHY_REG_SHIFT 16
366 #define OCPDR_DATA_MASK 0xffff
368 #define OCPAR_FLAG 0x80000000
369 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
370 #define OCPAR_GPHY_READ_CMD 0x0000f060
371 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
372 MISC = 0xf0, /* 8168e only. */
373 #define TXPLA_RST (1 << 29)
376 enum rtl_register_content {
377 /* InterruptStatusBits */
381 TxDescUnavail = 0x0080,
403 /* TXPoll register p.5 */
404 HPQ = 0x80, /* Poll cmd on the high prio queue */
405 NPQ = 0x40, /* Poll cmd on the low prio queue */
406 FSWInt = 0x01, /* Forced software interrupt */
410 Cfg9346_Unlock = 0xc0,
415 AcceptBroadcast = 0x08,
416 AcceptMulticast = 0x04,
418 AcceptAllPhys = 0x01,
425 TxInterFrameGapShift = 24,
426 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
428 /* Config1 register p.24 */
431 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
432 Speed_down = (1 << 4),
436 PMEnable = (1 << 0), /* Power Management Enable */
438 /* Config2 register p. 25 */
439 PCI_Clock_66MHz = 0x01,
440 PCI_Clock_33MHz = 0x00,
442 /* Config3 register p.25 */
443 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
444 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
445 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
447 /* Config5 register p.27 */
448 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
449 MWF = (1 << 5), /* Accept Multicast wakeup frame */
450 UWF = (1 << 4), /* Accept Unicast wakeup frame */
452 LanWake = (1 << 1), /* LanWake enable/disable */
453 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
456 TBIReset = 0x80000000,
457 TBILoopback = 0x40000000,
458 TBINwEnable = 0x20000000,
459 TBINwRestart = 0x10000000,
460 TBILinkOk = 0x02000000,
461 TBINwComplete = 0x01000000,
464 EnableBist = (1 << 15), // 8168 8101
465 Mac_dbgo_oe = (1 << 14), // 8168 8101
466 Normal_mode = (1 << 13), // unused
467 Force_half_dup = (1 << 12), // 8168 8101
468 Force_rxflow_en = (1 << 11), // 8168 8101
469 Force_txflow_en = (1 << 10), // 8168 8101
470 Cxpl_dbg_sel = (1 << 9), // 8168 8101
471 ASF = (1 << 8), // 8168 8101
472 PktCntrDisable = (1 << 7), // 8168 8101
473 Mac_dbgo_sel = 0x001c, // 8168
478 INTT_0 = 0x0000, // 8168
479 INTT_1 = 0x0001, // 8168
480 INTT_2 = 0x0002, // 8168
481 INTT_3 = 0x0003, // 8168
483 /* rtl8169_PHYstatus */
494 TBILinkOK = 0x02000000,
496 /* DumpCounterCommand */
501 /* First doubleword. */
502 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
503 RingEnd = (1 << 30), /* End of descriptor ring */
504 FirstFrag = (1 << 29), /* First segment of a packet */
505 LastFrag = (1 << 28), /* Final segment of a packet */
509 enum rtl_tx_desc_bit {
510 /* First doubleword. */
511 TD_LSO = (1 << 27), /* Large Send Offload */
512 #define TD_MSS_MAX 0x07ffu /* MSS value */
514 /* Second doubleword. */
515 TxVlanTag = (1 << 17), /* Add VLAN tag */
518 /* 8169, 8168b and 810x except 8102e. */
519 enum rtl_tx_desc_bit_0 {
520 /* First doubleword. */
521 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
522 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
523 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
524 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
527 /* 8102e, 8168c and beyond. */
528 enum rtl_tx_desc_bit_1 {
529 /* Second doubleword. */
530 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
531 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
532 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
533 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
536 static const struct rtl_tx_desc_info {
543 } tx_desc_info [] = {
546 .udp = TD0_IP_CS | TD0_UDP_CS,
547 .tcp = TD0_IP_CS | TD0_TCP_CS
549 .mss_shift = TD0_MSS_SHIFT,
554 .udp = TD1_IP_CS | TD1_UDP_CS,
555 .tcp = TD1_IP_CS | TD1_TCP_CS
557 .mss_shift = TD1_MSS_SHIFT,
562 enum rtl_rx_desc_bit {
564 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
565 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
567 #define RxProtoUDP (PID1)
568 #define RxProtoTCP (PID0)
569 #define RxProtoIP (PID1 | PID0)
570 #define RxProtoMask RxProtoIP
572 IPFail = (1 << 16), /* IP checksum failed */
573 UDPFail = (1 << 15), /* UDP/IP checksum failed */
574 TCPFail = (1 << 14), /* TCP/IP checksum failed */
575 RxVlanTag = (1 << 16), /* VLAN tag available */
578 #define RsvdMask 0x3fffc000
595 u8 __pad[sizeof(void *) - sizeof(u32)];
599 RTL_FEATURE_WOL = (1 << 0),
600 RTL_FEATURE_MSI = (1 << 1),
601 RTL_FEATURE_GMII = (1 << 2),
604 struct rtl8169_counters {
611 __le32 tx_one_collision;
612 __le32 tx_multi_collision;
620 struct rtl8169_private {
621 void __iomem *mmio_addr; /* memory map physical address */
622 struct pci_dev *pci_dev;
623 struct net_device *dev;
624 struct napi_struct napi;
629 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
630 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
633 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
634 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
635 dma_addr_t TxPhyAddr;
636 dma_addr_t RxPhyAddr;
637 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
638 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
639 struct timer_list timer;
646 void (*write)(void __iomem *, int, int);
647 int (*read)(void __iomem *, int);
650 struct pll_power_ops {
651 void (*down)(struct rtl8169_private *);
652 void (*up)(struct rtl8169_private *);
655 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
656 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
657 void (*phy_reset_enable)(struct rtl8169_private *tp);
658 void (*hw_start)(struct net_device *);
659 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
660 unsigned int (*link_ok)(void __iomem *);
661 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
663 struct delayed_work task;
666 struct mii_if_info mii;
667 struct rtl8169_counters counters;
671 const struct firmware *fw;
673 #define RTL_VER_SIZE 32
675 char version[RTL_VER_SIZE];
677 struct rtl_fw_phy_action {
682 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
685 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
686 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
687 module_param(use_dac, int, 0);
688 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
689 module_param_named(debug, debug.msg_enable, int, 0);
690 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
691 MODULE_LICENSE("GPL");
692 MODULE_VERSION(RTL8169_VERSION);
693 MODULE_FIRMWARE(FIRMWARE_8168D_1);
694 MODULE_FIRMWARE(FIRMWARE_8168D_2);
695 MODULE_FIRMWARE(FIRMWARE_8168E_1);
696 MODULE_FIRMWARE(FIRMWARE_8168E_2);
697 MODULE_FIRMWARE(FIRMWARE_8105E_1);
699 static int rtl8169_open(struct net_device *dev);
700 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
701 struct net_device *dev);
702 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
703 static int rtl8169_init_ring(struct net_device *dev);
704 static void rtl_hw_start(struct net_device *dev);
705 static int rtl8169_close(struct net_device *dev);
706 static void rtl_set_rx_mode(struct net_device *dev);
707 static void rtl8169_tx_timeout(struct net_device *dev);
708 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
709 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
710 void __iomem *, u32 budget);
711 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
712 static void rtl8169_down(struct net_device *dev);
713 static void rtl8169_rx_clear(struct rtl8169_private *tp);
714 static int rtl8169_poll(struct napi_struct *napi, int budget);
716 static const unsigned int rtl8169_rx_config =
717 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
719 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
721 void __iomem *ioaddr = tp->mmio_addr;
724 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
725 for (i = 0; i < 20; i++) {
727 if (RTL_R32(OCPAR) & OCPAR_FLAG)
730 return RTL_R32(OCPDR);
733 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
735 void __iomem *ioaddr = tp->mmio_addr;
738 RTL_W32(OCPDR, data);
739 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
740 for (i = 0; i < 20; i++) {
742 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
747 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
749 void __iomem *ioaddr = tp->mmio_addr;
753 RTL_W32(ERIAR, 0x800010e8);
755 for (i = 0; i < 5; i++) {
757 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
761 ocp_write(tp, 0x1, 0x30, 0x00000001);
764 #define OOB_CMD_RESET 0x00
765 #define OOB_CMD_DRIVER_START 0x05
766 #define OOB_CMD_DRIVER_STOP 0x06
768 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
770 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
773 static void rtl8168_driver_start(struct rtl8169_private *tp)
778 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
780 reg = rtl8168_get_ocp_reg(tp);
782 for (i = 0; i < 10; i++) {
784 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
789 static void rtl8168_driver_stop(struct rtl8169_private *tp)
794 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
796 reg = rtl8168_get_ocp_reg(tp);
798 for (i = 0; i < 10; i++) {
800 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
805 static int r8168dp_check_dash(struct rtl8169_private *tp)
807 u16 reg = rtl8168_get_ocp_reg(tp);
809 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
812 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
816 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
818 for (i = 20; i > 0; i--) {
820 * Check if the RTL8169 has completed writing to the specified
823 if (!(RTL_R32(PHYAR) & 0x80000000))
828 * According to hardware specs a 20us delay is required after write
829 * complete indication, but before sending next command.
834 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
838 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
840 for (i = 20; i > 0; i--) {
842 * Check if the RTL8169 has completed retrieving data from
843 * the specified MII register.
845 if (RTL_R32(PHYAR) & 0x80000000) {
846 value = RTL_R32(PHYAR) & 0xffff;
852 * According to hardware specs a 20us delay is required after read
853 * complete indication, but before sending next command.
860 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
864 RTL_W32(OCPDR, data |
865 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
866 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
867 RTL_W32(EPHY_RXER_NUM, 0);
869 for (i = 0; i < 100; i++) {
871 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
876 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
878 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
879 (value & OCPDR_DATA_MASK));
882 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
886 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
889 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
890 RTL_W32(EPHY_RXER_NUM, 0);
892 for (i = 0; i < 100; i++) {
894 if (RTL_R32(OCPAR) & OCPAR_FLAG)
898 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
901 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
903 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
905 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
908 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
910 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
913 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
915 r8168dp_2_mdio_start(ioaddr);
917 r8169_mdio_write(ioaddr, reg_addr, value);
919 r8168dp_2_mdio_stop(ioaddr);
922 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
926 r8168dp_2_mdio_start(ioaddr);
928 value = r8169_mdio_read(ioaddr, reg_addr);
930 r8168dp_2_mdio_stop(ioaddr);
935 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
937 tp->mdio_ops.write(tp->mmio_addr, location, val);
940 static int rtl_readphy(struct rtl8169_private *tp, int location)
942 return tp->mdio_ops.read(tp->mmio_addr, location);
945 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
947 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
950 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
954 val = rtl_readphy(tp, reg_addr);
955 rtl_writephy(tp, reg_addr, (val | p) & ~m);
958 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
961 struct rtl8169_private *tp = netdev_priv(dev);
963 rtl_writephy(tp, location, val);
966 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
968 struct rtl8169_private *tp = netdev_priv(dev);
970 return rtl_readphy(tp, location);
973 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
977 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
978 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
980 for (i = 0; i < 100; i++) {
981 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
987 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
992 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
994 for (i = 0; i < 100; i++) {
995 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
996 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1005 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1009 RTL_W32(CSIDR, value);
1010 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1011 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1013 for (i = 0; i < 100; i++) {
1014 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1020 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1025 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1026 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1028 for (i = 0; i < 100; i++) {
1029 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1030 value = RTL_R32(CSIDR);
1039 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1044 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1046 for (i = 0; i < 300; i++) {
1047 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1048 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1057 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1059 RTL_W16(IntrMask, 0x0000);
1061 RTL_W16(IntrStatus, 0xffff);
1064 static void rtl8169_asic_down(void __iomem *ioaddr)
1066 RTL_W8(ChipCmd, 0x00);
1067 rtl8169_irq_mask_and_ack(ioaddr);
1071 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1073 void __iomem *ioaddr = tp->mmio_addr;
1075 return RTL_R32(TBICSR) & TBIReset;
1078 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1080 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1083 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1085 return RTL_R32(TBICSR) & TBILinkOk;
1088 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1090 return RTL_R8(PHYstatus) & LinkStatus;
1093 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1095 void __iomem *ioaddr = tp->mmio_addr;
1097 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1100 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1104 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1105 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1108 static void __rtl8169_check_link_status(struct net_device *dev,
1109 struct rtl8169_private *tp,
1110 void __iomem *ioaddr, bool pm)
1112 unsigned long flags;
1114 spin_lock_irqsave(&tp->lock, flags);
1115 if (tp->link_ok(ioaddr)) {
1116 /* This is to cancel a scheduled suspend if there's one. */
1118 pm_request_resume(&tp->pci_dev->dev);
1119 netif_carrier_on(dev);
1120 if (net_ratelimit())
1121 netif_info(tp, ifup, dev, "link up\n");
1123 netif_carrier_off(dev);
1124 netif_info(tp, ifdown, dev, "link down\n");
1126 pm_schedule_suspend(&tp->pci_dev->dev, 100);
1128 spin_unlock_irqrestore(&tp->lock, flags);
1131 static void rtl8169_check_link_status(struct net_device *dev,
1132 struct rtl8169_private *tp,
1133 void __iomem *ioaddr)
1135 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1138 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1140 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1142 void __iomem *ioaddr = tp->mmio_addr;
1146 options = RTL_R8(Config1);
1147 if (!(options & PMEnable))
1150 options = RTL_R8(Config3);
1151 if (options & LinkUp)
1152 wolopts |= WAKE_PHY;
1153 if (options & MagicPacket)
1154 wolopts |= WAKE_MAGIC;
1156 options = RTL_R8(Config5);
1158 wolopts |= WAKE_UCAST;
1160 wolopts |= WAKE_BCAST;
1162 wolopts |= WAKE_MCAST;
1167 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1169 struct rtl8169_private *tp = netdev_priv(dev);
1171 spin_lock_irq(&tp->lock);
1173 wol->supported = WAKE_ANY;
1174 wol->wolopts = __rtl8169_get_wol(tp);
1176 spin_unlock_irq(&tp->lock);
1179 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1181 void __iomem *ioaddr = tp->mmio_addr;
1183 static const struct {
1188 { WAKE_ANY, Config1, PMEnable },
1189 { WAKE_PHY, Config3, LinkUp },
1190 { WAKE_MAGIC, Config3, MagicPacket },
1191 { WAKE_UCAST, Config5, UWF },
1192 { WAKE_BCAST, Config5, BWF },
1193 { WAKE_MCAST, Config5, MWF },
1194 { WAKE_ANY, Config5, LanWake }
1197 RTL_W8(Cfg9346, Cfg9346_Unlock);
1199 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1200 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1201 if (wolopts & cfg[i].opt)
1202 options |= cfg[i].mask;
1203 RTL_W8(cfg[i].reg, options);
1206 RTL_W8(Cfg9346, Cfg9346_Lock);
1209 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1211 struct rtl8169_private *tp = netdev_priv(dev);
1213 spin_lock_irq(&tp->lock);
1216 tp->features |= RTL_FEATURE_WOL;
1218 tp->features &= ~RTL_FEATURE_WOL;
1219 __rtl8169_set_wol(tp, wol->wolopts);
1220 spin_unlock_irq(&tp->lock);
1222 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1227 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1229 return rtl_chip_infos[tp->mac_version].fw_name;
1232 static void rtl8169_get_drvinfo(struct net_device *dev,
1233 struct ethtool_drvinfo *info)
1235 struct rtl8169_private *tp = netdev_priv(dev);
1236 struct rtl_fw *rtl_fw = tp->rtl_fw;
1238 strcpy(info->driver, MODULENAME);
1239 strcpy(info->version, RTL8169_VERSION);
1240 strcpy(info->bus_info, pci_name(tp->pci_dev));
1241 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1242 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1246 static int rtl8169_get_regs_len(struct net_device *dev)
1248 return R8169_REGS_SIZE;
1251 static int rtl8169_set_speed_tbi(struct net_device *dev,
1252 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1254 struct rtl8169_private *tp = netdev_priv(dev);
1255 void __iomem *ioaddr = tp->mmio_addr;
1259 reg = RTL_R32(TBICSR);
1260 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1261 (duplex == DUPLEX_FULL)) {
1262 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1263 } else if (autoneg == AUTONEG_ENABLE)
1264 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1266 netif_warn(tp, link, dev,
1267 "incorrect speed setting refused in TBI mode\n");
1274 static int rtl8169_set_speed_xmii(struct net_device *dev,
1275 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1277 struct rtl8169_private *tp = netdev_priv(dev);
1278 int giga_ctrl, bmcr;
1281 rtl_writephy(tp, 0x1f, 0x0000);
1283 if (autoneg == AUTONEG_ENABLE) {
1286 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1287 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1288 ADVERTISE_100HALF | ADVERTISE_100FULL);
1290 if (adv & ADVERTISED_10baseT_Half)
1291 auto_nego |= ADVERTISE_10HALF;
1292 if (adv & ADVERTISED_10baseT_Full)
1293 auto_nego |= ADVERTISE_10FULL;
1294 if (adv & ADVERTISED_100baseT_Half)
1295 auto_nego |= ADVERTISE_100HALF;
1296 if (adv & ADVERTISED_100baseT_Full)
1297 auto_nego |= ADVERTISE_100FULL;
1299 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1301 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1302 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1304 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1305 if (tp->mii.supports_gmii) {
1306 if (adv & ADVERTISED_1000baseT_Half)
1307 giga_ctrl |= ADVERTISE_1000HALF;
1308 if (adv & ADVERTISED_1000baseT_Full)
1309 giga_ctrl |= ADVERTISE_1000FULL;
1310 } else if (adv & (ADVERTISED_1000baseT_Half |
1311 ADVERTISED_1000baseT_Full)) {
1312 netif_info(tp, link, dev,
1313 "PHY does not support 1000Mbps\n");
1317 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1319 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1320 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1324 if (speed == SPEED_10)
1326 else if (speed == SPEED_100)
1327 bmcr = BMCR_SPEED100;
1331 if (duplex == DUPLEX_FULL)
1332 bmcr |= BMCR_FULLDPLX;
1335 rtl_writephy(tp, MII_BMCR, bmcr);
1337 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1338 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1339 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1340 rtl_writephy(tp, 0x17, 0x2138);
1341 rtl_writephy(tp, 0x0e, 0x0260);
1343 rtl_writephy(tp, 0x17, 0x2108);
1344 rtl_writephy(tp, 0x0e, 0x0000);
1353 static int rtl8169_set_speed(struct net_device *dev,
1354 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1356 struct rtl8169_private *tp = netdev_priv(dev);
1359 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1363 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1364 (advertising & ADVERTISED_1000baseT_Full)) {
1365 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1371 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1373 struct rtl8169_private *tp = netdev_priv(dev);
1374 unsigned long flags;
1377 del_timer_sync(&tp->timer);
1379 spin_lock_irqsave(&tp->lock, flags);
1380 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1381 cmd->duplex, cmd->advertising);
1382 spin_unlock_irqrestore(&tp->lock, flags);
1387 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1389 if (dev->mtu > TD_MSS_MAX)
1390 features &= ~NETIF_F_ALL_TSO;
1395 static int rtl8169_set_features(struct net_device *dev, u32 features)
1397 struct rtl8169_private *tp = netdev_priv(dev);
1398 void __iomem *ioaddr = tp->mmio_addr;
1399 unsigned long flags;
1401 spin_lock_irqsave(&tp->lock, flags);
1403 if (features & NETIF_F_RXCSUM)
1404 tp->cp_cmd |= RxChkSum;
1406 tp->cp_cmd &= ~RxChkSum;
1408 if (dev->features & NETIF_F_HW_VLAN_RX)
1409 tp->cp_cmd |= RxVlan;
1411 tp->cp_cmd &= ~RxVlan;
1413 RTL_W16(CPlusCmd, tp->cp_cmd);
1416 spin_unlock_irqrestore(&tp->lock, flags);
1421 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1422 struct sk_buff *skb)
1424 return (vlan_tx_tag_present(skb)) ?
1425 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1428 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1430 u32 opts2 = le32_to_cpu(desc->opts2);
1432 if (opts2 & RxVlanTag)
1433 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1438 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1440 struct rtl8169_private *tp = netdev_priv(dev);
1441 void __iomem *ioaddr = tp->mmio_addr;
1445 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1446 cmd->port = PORT_FIBRE;
1447 cmd->transceiver = XCVR_INTERNAL;
1449 status = RTL_R32(TBICSR);
1450 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1451 cmd->autoneg = !!(status & TBINwEnable);
1453 ethtool_cmd_speed_set(cmd, SPEED_1000);
1454 cmd->duplex = DUPLEX_FULL; /* Always set */
1459 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1461 struct rtl8169_private *tp = netdev_priv(dev);
1463 return mii_ethtool_gset(&tp->mii, cmd);
1466 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1468 struct rtl8169_private *tp = netdev_priv(dev);
1469 unsigned long flags;
1472 spin_lock_irqsave(&tp->lock, flags);
1474 rc = tp->get_settings(dev, cmd);
1476 spin_unlock_irqrestore(&tp->lock, flags);
1480 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1483 struct rtl8169_private *tp = netdev_priv(dev);
1484 unsigned long flags;
1486 if (regs->len > R8169_REGS_SIZE)
1487 regs->len = R8169_REGS_SIZE;
1489 spin_lock_irqsave(&tp->lock, flags);
1490 memcpy_fromio(p, tp->mmio_addr, regs->len);
1491 spin_unlock_irqrestore(&tp->lock, flags);
1494 static u32 rtl8169_get_msglevel(struct net_device *dev)
1496 struct rtl8169_private *tp = netdev_priv(dev);
1498 return tp->msg_enable;
1501 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1503 struct rtl8169_private *tp = netdev_priv(dev);
1505 tp->msg_enable = value;
1508 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1515 "tx_single_collisions",
1516 "tx_multi_collisions",
1524 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1528 return ARRAY_SIZE(rtl8169_gstrings);
1534 static void rtl8169_update_counters(struct net_device *dev)
1536 struct rtl8169_private *tp = netdev_priv(dev);
1537 void __iomem *ioaddr = tp->mmio_addr;
1538 struct device *d = &tp->pci_dev->dev;
1539 struct rtl8169_counters *counters;
1545 * Some chips are unable to dump tally counters when the receiver
1548 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1551 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1555 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1556 cmd = (u64)paddr & DMA_BIT_MASK(32);
1557 RTL_W32(CounterAddrLow, cmd);
1558 RTL_W32(CounterAddrLow, cmd | CounterDump);
1561 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1562 memcpy(&tp->counters, counters, sizeof(*counters));
1568 RTL_W32(CounterAddrLow, 0);
1569 RTL_W32(CounterAddrHigh, 0);
1571 dma_free_coherent(d, sizeof(*counters), counters, paddr);
1574 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1575 struct ethtool_stats *stats, u64 *data)
1577 struct rtl8169_private *tp = netdev_priv(dev);
1581 rtl8169_update_counters(dev);
1583 data[0] = le64_to_cpu(tp->counters.tx_packets);
1584 data[1] = le64_to_cpu(tp->counters.rx_packets);
1585 data[2] = le64_to_cpu(tp->counters.tx_errors);
1586 data[3] = le32_to_cpu(tp->counters.rx_errors);
1587 data[4] = le16_to_cpu(tp->counters.rx_missed);
1588 data[5] = le16_to_cpu(tp->counters.align_errors);
1589 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1590 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1591 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1592 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1593 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1594 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1595 data[12] = le16_to_cpu(tp->counters.tx_underun);
1598 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1602 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1607 static const struct ethtool_ops rtl8169_ethtool_ops = {
1608 .get_drvinfo = rtl8169_get_drvinfo,
1609 .get_regs_len = rtl8169_get_regs_len,
1610 .get_link = ethtool_op_get_link,
1611 .get_settings = rtl8169_get_settings,
1612 .set_settings = rtl8169_set_settings,
1613 .get_msglevel = rtl8169_get_msglevel,
1614 .set_msglevel = rtl8169_set_msglevel,
1615 .get_regs = rtl8169_get_regs,
1616 .get_wol = rtl8169_get_wol,
1617 .set_wol = rtl8169_set_wol,
1618 .get_strings = rtl8169_get_strings,
1619 .get_sset_count = rtl8169_get_sset_count,
1620 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1623 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1624 struct net_device *dev, u8 default_version)
1626 void __iomem *ioaddr = tp->mmio_addr;
1628 * The driver currently handles the 8168Bf and the 8168Be identically
1629 * but they can be identified more specifically through the test below
1632 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1634 * Same thing for the 8101Eb and the 8101Ec:
1636 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1638 static const struct {
1644 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1645 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1646 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1649 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1650 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1651 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1653 /* 8168DP family. */
1654 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1655 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1656 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
1659 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
1660 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1661 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1662 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1663 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1664 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1665 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1666 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1667 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1670 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1671 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1672 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1673 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1676 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
1677 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1678 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1679 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
1680 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1681 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1682 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1683 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1684 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1685 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1686 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1687 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1688 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1689 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1690 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1691 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1692 /* FIXME: where did these entries come from ? -- FR */
1693 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1694 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1697 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1698 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1699 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1700 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1701 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1702 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1705 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1709 reg = RTL_R32(TxConfig);
1710 while ((reg & p->mask) != p->val)
1712 tp->mac_version = p->mac_version;
1714 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1715 netif_notice(tp, probe, dev,
1716 "unknown MAC, using family default\n");
1717 tp->mac_version = default_version;
1721 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1723 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1731 static void rtl_writephy_batch(struct rtl8169_private *tp,
1732 const struct phy_reg *regs, int len)
1735 rtl_writephy(tp, regs->reg, regs->val);
1740 #define PHY_READ 0x00000000
1741 #define PHY_DATA_OR 0x10000000
1742 #define PHY_DATA_AND 0x20000000
1743 #define PHY_BJMPN 0x30000000
1744 #define PHY_READ_EFUSE 0x40000000
1745 #define PHY_READ_MAC_BYTE 0x50000000
1746 #define PHY_WRITE_MAC_BYTE 0x60000000
1747 #define PHY_CLEAR_READCOUNT 0x70000000
1748 #define PHY_WRITE 0x80000000
1749 #define PHY_READCOUNT_EQ_SKIP 0x90000000
1750 #define PHY_COMP_EQ_SKIPN 0xa0000000
1751 #define PHY_COMP_NEQ_SKIPN 0xb0000000
1752 #define PHY_WRITE_PREVIOUS 0xc0000000
1753 #define PHY_SKIPN 0xd0000000
1754 #define PHY_DELAY_MS 0xe0000000
1755 #define PHY_WRITE_ERI_WORD 0xf0000000
1757 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1759 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1761 const struct firmware *fw = rtl_fw->fw;
1762 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1763 char *version = rtl_fw->version;
1766 if (fw->size < FW_OPCODE_SIZE)
1769 if (fw->size % FW_OPCODE_SIZE)
1772 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1774 pa->code = (__le32 *)fw->data;
1775 pa->size = fw->size / FW_OPCODE_SIZE;
1777 version[RTL_VER_SIZE - 1] = 0;
1784 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1786 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1787 struct net_device *dev = tp->dev;
1791 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1792 netif_err(tp, probe, dev, "invalid firwmare\n");
1796 for (index = 0; index < pa->size; index++) {
1797 u32 action = le32_to_cpu(pa->code[index]);
1798 u32 regno = (action & 0x0fff0000) >> 16;
1800 switch(action & 0xf0000000) {
1804 case PHY_READ_EFUSE:
1805 case PHY_CLEAR_READCOUNT:
1807 case PHY_WRITE_PREVIOUS:
1812 if (regno > index) {
1813 netif_err(tp, probe, tp->dev,
1814 "Out of range of firmware\n");
1818 case PHY_READCOUNT_EQ_SKIP:
1819 if (index + 2 >= pa->size) {
1820 netif_err(tp, probe, tp->dev,
1821 "Out of range of firmware\n");
1825 case PHY_COMP_EQ_SKIPN:
1826 case PHY_COMP_NEQ_SKIPN:
1828 if (index + 1 + regno >= pa->size) {
1829 netif_err(tp, probe, tp->dev,
1830 "Out of range of firmware\n");
1835 case PHY_READ_MAC_BYTE:
1836 case PHY_WRITE_MAC_BYTE:
1837 case PHY_WRITE_ERI_WORD:
1839 netif_err(tp, probe, tp->dev,
1840 "Invalid action 0x%08x\n", action);
1848 for (index = 0; index < pa->size; ) {
1849 u32 action = le32_to_cpu(pa->code[index]);
1850 u32 data = action & 0x0000ffff;
1851 u32 regno = (action & 0x0fff0000) >> 16;
1856 switch(action & 0xf0000000) {
1858 predata = rtl_readphy(tp, regno);
1873 case PHY_READ_EFUSE:
1874 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1877 case PHY_CLEAR_READCOUNT:
1882 rtl_writephy(tp, regno, data);
1885 case PHY_READCOUNT_EQ_SKIP:
1886 index += (count == data) ? 2 : 1;
1888 case PHY_COMP_EQ_SKIPN:
1889 if (predata == data)
1893 case PHY_COMP_NEQ_SKIPN:
1894 if (predata != data)
1898 case PHY_WRITE_PREVIOUS:
1899 rtl_writephy(tp, regno, predata);
1910 case PHY_READ_MAC_BYTE:
1911 case PHY_WRITE_MAC_BYTE:
1912 case PHY_WRITE_ERI_WORD:
1919 static void rtl_release_firmware(struct rtl8169_private *tp)
1921 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1922 release_firmware(tp->rtl_fw->fw);
1925 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
1928 static void rtl_apply_firmware(struct rtl8169_private *tp)
1930 struct rtl_fw *rtl_fw = tp->rtl_fw;
1932 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1933 if (!IS_ERR_OR_NULL(rtl_fw))
1934 rtl_phy_write_fw(tp, rtl_fw);
1937 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1939 if (rtl_readphy(tp, reg) != val)
1940 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1942 rtl_apply_firmware(tp);
1945 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1947 static const struct phy_reg phy_reg_init[] = {
2009 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2012 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2014 static const struct phy_reg phy_reg_init[] = {
2020 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2023 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2025 struct pci_dev *pdev = tp->pci_dev;
2026 u16 vendor_id, device_id;
2028 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2029 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2031 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2034 rtl_writephy(tp, 0x1f, 0x0001);
2035 rtl_writephy(tp, 0x10, 0xf01b);
2036 rtl_writephy(tp, 0x1f, 0x0000);
2039 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2041 static const struct phy_reg phy_reg_init[] = {
2081 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2083 rtl8169scd_hw_phy_config_quirk(tp);
2086 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2088 static const struct phy_reg phy_reg_init[] = {
2136 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2139 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2141 static const struct phy_reg phy_reg_init[] = {
2146 rtl_writephy(tp, 0x1f, 0x0001);
2147 rtl_patchphy(tp, 0x16, 1 << 0);
2149 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2152 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2154 static const struct phy_reg phy_reg_init[] = {
2160 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2163 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2165 static const struct phy_reg phy_reg_init[] = {
2173 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2176 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2178 static const struct phy_reg phy_reg_init[] = {
2184 rtl_writephy(tp, 0x1f, 0x0000);
2185 rtl_patchphy(tp, 0x14, 1 << 5);
2186 rtl_patchphy(tp, 0x0d, 1 << 5);
2188 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2191 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2193 static const struct phy_reg phy_reg_init[] = {
2213 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2215 rtl_patchphy(tp, 0x14, 1 << 5);
2216 rtl_patchphy(tp, 0x0d, 1 << 5);
2217 rtl_writephy(tp, 0x1f, 0x0000);
2220 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2222 static const struct phy_reg phy_reg_init[] = {
2240 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2242 rtl_patchphy(tp, 0x16, 1 << 0);
2243 rtl_patchphy(tp, 0x14, 1 << 5);
2244 rtl_patchphy(tp, 0x0d, 1 << 5);
2245 rtl_writephy(tp, 0x1f, 0x0000);
2248 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2250 static const struct phy_reg phy_reg_init[] = {
2262 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2264 rtl_patchphy(tp, 0x16, 1 << 0);
2265 rtl_patchphy(tp, 0x14, 1 << 5);
2266 rtl_patchphy(tp, 0x0d, 1 << 5);
2267 rtl_writephy(tp, 0x1f, 0x0000);
2270 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2272 rtl8168c_3_hw_phy_config(tp);
2275 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2277 static const struct phy_reg phy_reg_init_0[] = {
2278 /* Channel Estimation */
2299 * Enhance line driver power
2308 * Can not link to 1Gbps with bad cable
2309 * Decrease SNR threshold form 21.07dB to 19.04dB
2317 void __iomem *ioaddr = tp->mmio_addr;
2319 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2323 * Fine Tune Switching regulator parameter
2325 rtl_writephy(tp, 0x1f, 0x0002);
2326 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2327 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2329 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2330 static const struct phy_reg phy_reg_init[] = {
2340 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2342 val = rtl_readphy(tp, 0x0d);
2344 if ((val & 0x00ff) != 0x006c) {
2345 static const u32 set[] = {
2346 0x0065, 0x0066, 0x0067, 0x0068,
2347 0x0069, 0x006a, 0x006b, 0x006c
2351 rtl_writephy(tp, 0x1f, 0x0002);
2354 for (i = 0; i < ARRAY_SIZE(set); i++)
2355 rtl_writephy(tp, 0x0d, val | set[i]);
2358 static const struct phy_reg phy_reg_init[] = {
2366 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2369 /* RSET couple improve */
2370 rtl_writephy(tp, 0x1f, 0x0002);
2371 rtl_patchphy(tp, 0x0d, 0x0300);
2372 rtl_patchphy(tp, 0x0f, 0x0010);
2374 /* Fine tune PLL performance */
2375 rtl_writephy(tp, 0x1f, 0x0002);
2376 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2377 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2379 rtl_writephy(tp, 0x1f, 0x0005);
2380 rtl_writephy(tp, 0x05, 0x001b);
2382 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2384 rtl_writephy(tp, 0x1f, 0x0000);
2387 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2389 static const struct phy_reg phy_reg_init_0[] = {
2390 /* Channel Estimation */
2411 * Enhance line driver power
2420 * Can not link to 1Gbps with bad cable
2421 * Decrease SNR threshold form 21.07dB to 19.04dB
2429 void __iomem *ioaddr = tp->mmio_addr;
2431 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2433 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2434 static const struct phy_reg phy_reg_init[] = {
2445 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2447 val = rtl_readphy(tp, 0x0d);
2448 if ((val & 0x00ff) != 0x006c) {
2449 static const u32 set[] = {
2450 0x0065, 0x0066, 0x0067, 0x0068,
2451 0x0069, 0x006a, 0x006b, 0x006c
2455 rtl_writephy(tp, 0x1f, 0x0002);
2458 for (i = 0; i < ARRAY_SIZE(set); i++)
2459 rtl_writephy(tp, 0x0d, val | set[i]);
2462 static const struct phy_reg phy_reg_init[] = {
2470 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2473 /* Fine tune PLL performance */
2474 rtl_writephy(tp, 0x1f, 0x0002);
2475 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2476 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2478 /* Switching regulator Slew rate */
2479 rtl_writephy(tp, 0x1f, 0x0002);
2480 rtl_patchphy(tp, 0x0f, 0x0017);
2482 rtl_writephy(tp, 0x1f, 0x0005);
2483 rtl_writephy(tp, 0x05, 0x001b);
2485 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2487 rtl_writephy(tp, 0x1f, 0x0000);
2490 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2492 static const struct phy_reg phy_reg_init[] = {
2548 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2551 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2553 static const struct phy_reg phy_reg_init[] = {
2563 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2564 rtl_patchphy(tp, 0x0d, 1 << 5);
2567 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2569 static const struct phy_reg phy_reg_init[] = {
2570 /* Enable Delay cap */
2576 /* Channel estimation fine tune */
2585 /* Update PFM & 10M TX idle timer */
2597 rtl_apply_firmware(tp);
2599 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2601 /* DCO enable for 10M IDLE Power */
2602 rtl_writephy(tp, 0x1f, 0x0007);
2603 rtl_writephy(tp, 0x1e, 0x0023);
2604 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2605 rtl_writephy(tp, 0x1f, 0x0000);
2607 /* For impedance matching */
2608 rtl_writephy(tp, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2610 rtl_writephy(tp, 0x1f, 0x0000);
2612 /* PHY auto speed down */
2613 rtl_writephy(tp, 0x1f, 0x0007);
2614 rtl_writephy(tp, 0x1e, 0x002d);
2615 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2616 rtl_writephy(tp, 0x1f, 0x0000);
2617 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2619 rtl_writephy(tp, 0x1f, 0x0005);
2620 rtl_writephy(tp, 0x05, 0x8b86);
2621 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2622 rtl_writephy(tp, 0x1f, 0x0000);
2624 rtl_writephy(tp, 0x1f, 0x0005);
2625 rtl_writephy(tp, 0x05, 0x8b85);
2626 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2627 rtl_writephy(tp, 0x1f, 0x0007);
2628 rtl_writephy(tp, 0x1e, 0x0020);
2629 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2630 rtl_writephy(tp, 0x1f, 0x0006);
2631 rtl_writephy(tp, 0x00, 0x5a00);
2632 rtl_writephy(tp, 0x1f, 0x0000);
2633 rtl_writephy(tp, 0x0d, 0x0007);
2634 rtl_writephy(tp, 0x0e, 0x003c);
2635 rtl_writephy(tp, 0x0d, 0x4007);
2636 rtl_writephy(tp, 0x0e, 0x0000);
2637 rtl_writephy(tp, 0x0d, 0x0000);
2640 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2642 static const struct phy_reg phy_reg_init[] = {
2649 rtl_writephy(tp, 0x1f, 0x0000);
2650 rtl_patchphy(tp, 0x11, 1 << 12);
2651 rtl_patchphy(tp, 0x19, 1 << 13);
2652 rtl_patchphy(tp, 0x10, 1 << 15);
2654 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2657 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2659 static const struct phy_reg phy_reg_init[] = {
2673 /* Disable ALDPS before ram code */
2674 rtl_writephy(tp, 0x1f, 0x0000);
2675 rtl_writephy(tp, 0x18, 0x0310);
2678 rtl_apply_firmware(tp);
2680 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2683 static void rtl_hw_phy_config(struct net_device *dev)
2685 struct rtl8169_private *tp = netdev_priv(dev);
2687 rtl8169_print_mac_version(tp);
2689 switch (tp->mac_version) {
2690 case RTL_GIGA_MAC_VER_01:
2692 case RTL_GIGA_MAC_VER_02:
2693 case RTL_GIGA_MAC_VER_03:
2694 rtl8169s_hw_phy_config(tp);
2696 case RTL_GIGA_MAC_VER_04:
2697 rtl8169sb_hw_phy_config(tp);
2699 case RTL_GIGA_MAC_VER_05:
2700 rtl8169scd_hw_phy_config(tp);
2702 case RTL_GIGA_MAC_VER_06:
2703 rtl8169sce_hw_phy_config(tp);
2705 case RTL_GIGA_MAC_VER_07:
2706 case RTL_GIGA_MAC_VER_08:
2707 case RTL_GIGA_MAC_VER_09:
2708 rtl8102e_hw_phy_config(tp);
2710 case RTL_GIGA_MAC_VER_11:
2711 rtl8168bb_hw_phy_config(tp);
2713 case RTL_GIGA_MAC_VER_12:
2714 rtl8168bef_hw_phy_config(tp);
2716 case RTL_GIGA_MAC_VER_17:
2717 rtl8168bef_hw_phy_config(tp);
2719 case RTL_GIGA_MAC_VER_18:
2720 rtl8168cp_1_hw_phy_config(tp);
2722 case RTL_GIGA_MAC_VER_19:
2723 rtl8168c_1_hw_phy_config(tp);
2725 case RTL_GIGA_MAC_VER_20:
2726 rtl8168c_2_hw_phy_config(tp);
2728 case RTL_GIGA_MAC_VER_21:
2729 rtl8168c_3_hw_phy_config(tp);
2731 case RTL_GIGA_MAC_VER_22:
2732 rtl8168c_4_hw_phy_config(tp);
2734 case RTL_GIGA_MAC_VER_23:
2735 case RTL_GIGA_MAC_VER_24:
2736 rtl8168cp_2_hw_phy_config(tp);
2738 case RTL_GIGA_MAC_VER_25:
2739 rtl8168d_1_hw_phy_config(tp);
2741 case RTL_GIGA_MAC_VER_26:
2742 rtl8168d_2_hw_phy_config(tp);
2744 case RTL_GIGA_MAC_VER_27:
2745 rtl8168d_3_hw_phy_config(tp);
2747 case RTL_GIGA_MAC_VER_28:
2748 rtl8168d_4_hw_phy_config(tp);
2750 case RTL_GIGA_MAC_VER_29:
2751 case RTL_GIGA_MAC_VER_30:
2752 rtl8105e_hw_phy_config(tp);
2754 case RTL_GIGA_MAC_VER_31:
2757 case RTL_GIGA_MAC_VER_32:
2758 case RTL_GIGA_MAC_VER_33:
2759 rtl8168e_hw_phy_config(tp);
2767 static void rtl8169_phy_timer(unsigned long __opaque)
2769 struct net_device *dev = (struct net_device *)__opaque;
2770 struct rtl8169_private *tp = netdev_priv(dev);
2771 struct timer_list *timer = &tp->timer;
2772 void __iomem *ioaddr = tp->mmio_addr;
2773 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2775 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2777 spin_lock_irq(&tp->lock);
2779 if (tp->phy_reset_pending(tp)) {
2781 * A busy loop could burn quite a few cycles on nowadays CPU.
2782 * Let's delay the execution of the timer for a few ticks.
2788 if (tp->link_ok(ioaddr))
2791 netif_warn(tp, link, dev, "PHY reset until link up\n");
2793 tp->phy_reset_enable(tp);
2796 mod_timer(timer, jiffies + timeout);
2798 spin_unlock_irq(&tp->lock);
2801 #ifdef CONFIG_NET_POLL_CONTROLLER
2803 * Polling 'interrupt' - used by things like netconsole to send skbs
2804 * without having to re-enable interrupts. It's not called while
2805 * the interrupt routine is executing.
2807 static void rtl8169_netpoll(struct net_device *dev)
2809 struct rtl8169_private *tp = netdev_priv(dev);
2810 struct pci_dev *pdev = tp->pci_dev;
2812 disable_irq(pdev->irq);
2813 rtl8169_interrupt(pdev->irq, dev);
2814 enable_irq(pdev->irq);
2818 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2819 void __iomem *ioaddr)
2822 pci_release_regions(pdev);
2823 pci_clear_mwi(pdev);
2824 pci_disable_device(pdev);
2828 static void rtl8169_phy_reset(struct net_device *dev,
2829 struct rtl8169_private *tp)
2833 tp->phy_reset_enable(tp);
2834 for (i = 0; i < 100; i++) {
2835 if (!tp->phy_reset_pending(tp))
2839 netif_err(tp, link, dev, "PHY reset failed\n");
2842 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2844 void __iomem *ioaddr = tp->mmio_addr;
2846 rtl_hw_phy_config(dev);
2848 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2849 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2853 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2855 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2856 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2858 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2859 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2861 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2862 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2865 rtl8169_phy_reset(dev, tp);
2867 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2868 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2869 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2870 (tp->mii.supports_gmii ?
2871 ADVERTISED_1000baseT_Half |
2872 ADVERTISED_1000baseT_Full : 0));
2874 if (RTL_R8(PHYstatus) & TBI_Enable)
2875 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2878 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2880 void __iomem *ioaddr = tp->mmio_addr;
2884 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2885 high = addr[4] | (addr[5] << 8);
2887 spin_lock_irq(&tp->lock);
2889 RTL_W8(Cfg9346, Cfg9346_Unlock);
2891 RTL_W32(MAC4, high);
2897 RTL_W8(Cfg9346, Cfg9346_Lock);
2899 spin_unlock_irq(&tp->lock);
2902 static int rtl_set_mac_address(struct net_device *dev, void *p)
2904 struct rtl8169_private *tp = netdev_priv(dev);
2905 struct sockaddr *addr = p;
2907 if (!is_valid_ether_addr(addr->sa_data))
2908 return -EADDRNOTAVAIL;
2910 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2912 rtl_rar_set(tp, dev->dev_addr);
2917 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2919 struct rtl8169_private *tp = netdev_priv(dev);
2920 struct mii_ioctl_data *data = if_mii(ifr);
2922 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2925 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2926 struct mii_ioctl_data *data, int cmd)
2930 data->phy_id = 32; /* Internal PHY */
2934 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2938 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2944 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2949 static const struct rtl_cfg_info {
2950 void (*hw_start)(struct net_device *);
2951 unsigned int region;
2957 } rtl_cfg_infos [] = {
2959 .hw_start = rtl_hw_start_8169,
2962 .intr_event = SYSErr | LinkChg | RxOverflow |
2963 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2964 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2965 .features = RTL_FEATURE_GMII,
2966 .default_ver = RTL_GIGA_MAC_VER_01,
2969 .hw_start = rtl_hw_start_8168,
2972 .intr_event = SYSErr | LinkChg | RxOverflow |
2973 TxErr | TxOK | RxOK | RxErr,
2974 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2975 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2976 .default_ver = RTL_GIGA_MAC_VER_11,
2979 .hw_start = rtl_hw_start_8101,
2982 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2983 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2984 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2985 .features = RTL_FEATURE_MSI,
2986 .default_ver = RTL_GIGA_MAC_VER_13,
2990 /* Cfg9346_Unlock assumed. */
2991 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2992 const struct rtl_cfg_info *cfg)
2997 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2998 if (cfg->features & RTL_FEATURE_MSI) {
2999 if (pci_enable_msi(pdev)) {
3000 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3003 msi = RTL_FEATURE_MSI;
3006 RTL_W8(Config2, cfg2);
3010 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3012 if (tp->features & RTL_FEATURE_MSI) {
3013 pci_disable_msi(pdev);
3014 tp->features &= ~RTL_FEATURE_MSI;
3018 static const struct net_device_ops rtl8169_netdev_ops = {
3019 .ndo_open = rtl8169_open,
3020 .ndo_stop = rtl8169_close,
3021 .ndo_get_stats = rtl8169_get_stats,
3022 .ndo_start_xmit = rtl8169_start_xmit,
3023 .ndo_tx_timeout = rtl8169_tx_timeout,
3024 .ndo_validate_addr = eth_validate_addr,
3025 .ndo_change_mtu = rtl8169_change_mtu,
3026 .ndo_fix_features = rtl8169_fix_features,
3027 .ndo_set_features = rtl8169_set_features,
3028 .ndo_set_mac_address = rtl_set_mac_address,
3029 .ndo_do_ioctl = rtl8169_ioctl,
3030 .ndo_set_multicast_list = rtl_set_rx_mode,
3031 #ifdef CONFIG_NET_POLL_CONTROLLER
3032 .ndo_poll_controller = rtl8169_netpoll,
3037 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3039 struct mdio_ops *ops = &tp->mdio_ops;
3041 switch (tp->mac_version) {
3042 case RTL_GIGA_MAC_VER_27:
3043 ops->write = r8168dp_1_mdio_write;
3044 ops->read = r8168dp_1_mdio_read;
3046 case RTL_GIGA_MAC_VER_28:
3047 case RTL_GIGA_MAC_VER_31:
3048 ops->write = r8168dp_2_mdio_write;
3049 ops->read = r8168dp_2_mdio_read;
3052 ops->write = r8169_mdio_write;
3053 ops->read = r8169_mdio_read;
3058 static void r810x_phy_power_down(struct rtl8169_private *tp)
3060 rtl_writephy(tp, 0x1f, 0x0000);
3061 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3064 static void r810x_phy_power_up(struct rtl8169_private *tp)
3066 rtl_writephy(tp, 0x1f, 0x0000);
3067 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3070 static void r810x_pll_power_down(struct rtl8169_private *tp)
3072 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3073 rtl_writephy(tp, 0x1f, 0x0000);
3074 rtl_writephy(tp, MII_BMCR, 0x0000);
3078 r810x_phy_power_down(tp);
3081 static void r810x_pll_power_up(struct rtl8169_private *tp)
3083 r810x_phy_power_up(tp);
3086 static void r8168_phy_power_up(struct rtl8169_private *tp)
3088 rtl_writephy(tp, 0x1f, 0x0000);
3089 switch (tp->mac_version) {
3090 case RTL_GIGA_MAC_VER_11:
3091 case RTL_GIGA_MAC_VER_12:
3092 case RTL_GIGA_MAC_VER_17:
3093 case RTL_GIGA_MAC_VER_18:
3094 case RTL_GIGA_MAC_VER_19:
3095 case RTL_GIGA_MAC_VER_20:
3096 case RTL_GIGA_MAC_VER_21:
3097 case RTL_GIGA_MAC_VER_22:
3098 case RTL_GIGA_MAC_VER_23:
3099 case RTL_GIGA_MAC_VER_24:
3100 case RTL_GIGA_MAC_VER_25:
3101 case RTL_GIGA_MAC_VER_26:
3102 case RTL_GIGA_MAC_VER_27:
3103 case RTL_GIGA_MAC_VER_28:
3104 case RTL_GIGA_MAC_VER_31:
3105 rtl_writephy(tp, 0x0e, 0x0000);
3110 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3113 static void r8168_phy_power_down(struct rtl8169_private *tp)
3115 rtl_writephy(tp, 0x1f, 0x0000);
3116 switch (tp->mac_version) {
3117 case RTL_GIGA_MAC_VER_32:
3118 case RTL_GIGA_MAC_VER_33:
3119 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3122 case RTL_GIGA_MAC_VER_11:
3123 case RTL_GIGA_MAC_VER_12:
3124 case RTL_GIGA_MAC_VER_17:
3125 case RTL_GIGA_MAC_VER_18:
3126 case RTL_GIGA_MAC_VER_19:
3127 case RTL_GIGA_MAC_VER_20:
3128 case RTL_GIGA_MAC_VER_21:
3129 case RTL_GIGA_MAC_VER_22:
3130 case RTL_GIGA_MAC_VER_23:
3131 case RTL_GIGA_MAC_VER_24:
3132 case RTL_GIGA_MAC_VER_25:
3133 case RTL_GIGA_MAC_VER_26:
3134 case RTL_GIGA_MAC_VER_27:
3135 case RTL_GIGA_MAC_VER_28:
3136 case RTL_GIGA_MAC_VER_31:
3137 rtl_writephy(tp, 0x0e, 0x0200);
3139 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3144 static void r8168_pll_power_down(struct rtl8169_private *tp)
3146 void __iomem *ioaddr = tp->mmio_addr;
3148 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3149 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3150 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3151 r8168dp_check_dash(tp)) {
3155 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3156 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3157 (RTL_R16(CPlusCmd) & ASF)) {
3161 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3162 tp->mac_version == RTL_GIGA_MAC_VER_33)
3163 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3165 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3166 rtl_writephy(tp, 0x1f, 0x0000);
3167 rtl_writephy(tp, MII_BMCR, 0x0000);
3169 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3170 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3174 r8168_phy_power_down(tp);
3176 switch (tp->mac_version) {
3177 case RTL_GIGA_MAC_VER_25:
3178 case RTL_GIGA_MAC_VER_26:
3179 case RTL_GIGA_MAC_VER_27:
3180 case RTL_GIGA_MAC_VER_28:
3181 case RTL_GIGA_MAC_VER_31:
3182 case RTL_GIGA_MAC_VER_32:
3183 case RTL_GIGA_MAC_VER_33:
3184 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3189 static void r8168_pll_power_up(struct rtl8169_private *tp)
3191 void __iomem *ioaddr = tp->mmio_addr;
3193 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3194 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3195 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3196 r8168dp_check_dash(tp)) {
3200 switch (tp->mac_version) {
3201 case RTL_GIGA_MAC_VER_25:
3202 case RTL_GIGA_MAC_VER_26:
3203 case RTL_GIGA_MAC_VER_27:
3204 case RTL_GIGA_MAC_VER_28:
3205 case RTL_GIGA_MAC_VER_31:
3206 case RTL_GIGA_MAC_VER_32:
3207 case RTL_GIGA_MAC_VER_33:
3208 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3212 r8168_phy_power_up(tp);
3215 static void rtl_pll_power_op(struct rtl8169_private *tp,
3216 void (*op)(struct rtl8169_private *))
3222 static void rtl_pll_power_down(struct rtl8169_private *tp)
3224 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3227 static void rtl_pll_power_up(struct rtl8169_private *tp)
3229 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3232 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3234 struct pll_power_ops *ops = &tp->pll_power_ops;
3236 switch (tp->mac_version) {
3237 case RTL_GIGA_MAC_VER_07:
3238 case RTL_GIGA_MAC_VER_08:
3239 case RTL_GIGA_MAC_VER_09:
3240 case RTL_GIGA_MAC_VER_10:
3241 case RTL_GIGA_MAC_VER_16:
3242 case RTL_GIGA_MAC_VER_29:
3243 case RTL_GIGA_MAC_VER_30:
3244 ops->down = r810x_pll_power_down;
3245 ops->up = r810x_pll_power_up;
3248 case RTL_GIGA_MAC_VER_11:
3249 case RTL_GIGA_MAC_VER_12:
3250 case RTL_GIGA_MAC_VER_17:
3251 case RTL_GIGA_MAC_VER_18:
3252 case RTL_GIGA_MAC_VER_19:
3253 case RTL_GIGA_MAC_VER_20:
3254 case RTL_GIGA_MAC_VER_21:
3255 case RTL_GIGA_MAC_VER_22:
3256 case RTL_GIGA_MAC_VER_23:
3257 case RTL_GIGA_MAC_VER_24:
3258 case RTL_GIGA_MAC_VER_25:
3259 case RTL_GIGA_MAC_VER_26:
3260 case RTL_GIGA_MAC_VER_27:
3261 case RTL_GIGA_MAC_VER_28:
3262 case RTL_GIGA_MAC_VER_31:
3263 case RTL_GIGA_MAC_VER_32:
3264 case RTL_GIGA_MAC_VER_33:
3265 ops->down = r8168_pll_power_down;
3266 ops->up = r8168_pll_power_up;
3276 static void rtl_hw_reset(struct rtl8169_private *tp)
3278 void __iomem *ioaddr = tp->mmio_addr;
3281 /* Soft reset the chip. */
3282 RTL_W8(ChipCmd, CmdReset);
3284 /* Check that the chip has finished the reset. */
3285 for (i = 0; i < 100; i++) {
3286 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3288 msleep_interruptible(1);
3292 static int __devinit
3293 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3295 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3296 const unsigned int region = cfg->region;
3297 struct rtl8169_private *tp;
3298 struct mii_if_info *mii;
3299 struct net_device *dev;
3300 void __iomem *ioaddr;
3304 if (netif_msg_drv(&debug)) {
3305 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3306 MODULENAME, RTL8169_VERSION);
3309 dev = alloc_etherdev(sizeof (*tp));
3311 if (netif_msg_drv(&debug))
3312 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3317 SET_NETDEV_DEV(dev, &pdev->dev);
3318 dev->netdev_ops = &rtl8169_netdev_ops;
3319 tp = netdev_priv(dev);
3322 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3326 mii->mdio_read = rtl_mdio_read;
3327 mii->mdio_write = rtl_mdio_write;
3328 mii->phy_id_mask = 0x1f;
3329 mii->reg_num_mask = 0x1f;
3330 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3332 /* disable ASPM completely as that cause random device stop working
3333 * problems as well as full system hangs for some PCIe devices users */
3334 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3335 PCIE_LINK_STATE_CLKPM);
3337 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3338 rc = pci_enable_device(pdev);
3340 netif_err(tp, probe, dev, "enable failure\n");
3341 goto err_out_free_dev_1;
3344 if (pci_set_mwi(pdev) < 0)
3345 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3347 /* make sure PCI base addr 1 is MMIO */
3348 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3349 netif_err(tp, probe, dev,
3350 "region #%d not an MMIO resource, aborting\n",
3356 /* check for weird/broken PCI region reporting */
3357 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3358 netif_err(tp, probe, dev,
3359 "Invalid PCI region size(s), aborting\n");
3364 rc = pci_request_regions(pdev, MODULENAME);
3366 netif_err(tp, probe, dev, "could not request regions\n");
3370 tp->cp_cmd = RxChkSum;
3372 if ((sizeof(dma_addr_t) > 4) &&
3373 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3374 tp->cp_cmd |= PCIDAC;
3375 dev->features |= NETIF_F_HIGHDMA;
3377 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3379 netif_err(tp, probe, dev, "DMA configuration failed\n");
3380 goto err_out_free_res_3;
3384 /* ioremap MMIO region */
3385 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3387 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3389 goto err_out_free_res_3;
3391 tp->mmio_addr = ioaddr;
3393 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3395 netif_info(tp, probe, dev, "no PCI Express capability\n");
3397 RTL_W16(IntrMask, 0x0000);
3401 RTL_W16(IntrStatus, 0xffff);
3403 pci_set_master(pdev);
3405 /* Identify chip attached to board */
3406 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3409 * Pretend we are using VLANs; This bypasses a nasty bug where
3410 * Interrupts stop flowing on high load on 8110SCd controllers.
3412 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3413 tp->cp_cmd |= RxVlan;
3415 rtl_init_mdio_ops(tp);
3416 rtl_init_pll_power_ops(tp);
3418 rtl8169_print_mac_version(tp);
3420 chipset = tp->mac_version;
3421 tp->txd_version = rtl_chip_infos[chipset].txd_version;
3423 RTL_W8(Cfg9346, Cfg9346_Unlock);
3424 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3425 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3426 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3427 tp->features |= RTL_FEATURE_WOL;
3428 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3429 tp->features |= RTL_FEATURE_WOL;
3430 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3431 RTL_W8(Cfg9346, Cfg9346_Lock);
3433 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3434 (RTL_R8(PHYstatus) & TBI_Enable)) {
3435 tp->set_speed = rtl8169_set_speed_tbi;
3436 tp->get_settings = rtl8169_gset_tbi;
3437 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3438 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3439 tp->link_ok = rtl8169_tbi_link_ok;
3440 tp->do_ioctl = rtl_tbi_ioctl;
3442 tp->set_speed = rtl8169_set_speed_xmii;
3443 tp->get_settings = rtl8169_gset_xmii;
3444 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3445 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3446 tp->link_ok = rtl8169_xmii_link_ok;
3447 tp->do_ioctl = rtl_xmii_ioctl;
3450 spin_lock_init(&tp->lock);
3452 /* Get MAC address */
3453 for (i = 0; i < MAC_ADDR_LEN; i++)
3454 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3455 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3457 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3458 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3459 dev->irq = pdev->irq;
3460 dev->base_addr = (unsigned long) ioaddr;
3462 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3464 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3465 * properly for all devices */
3466 dev->features |= NETIF_F_RXCSUM |
3467 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3469 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3470 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3471 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3474 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3475 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3476 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3478 tp->intr_mask = 0xffff;
3479 tp->hw_start = cfg->hw_start;
3480 tp->intr_event = cfg->intr_event;
3481 tp->napi_event = cfg->napi_event;
3483 init_timer(&tp->timer);
3484 tp->timer.data = (unsigned long) dev;
3485 tp->timer.function = rtl8169_phy_timer;
3487 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3489 rc = register_netdev(dev);
3493 pci_set_drvdata(pdev, dev);
3495 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3496 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3497 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3499 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3500 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3501 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3502 rtl8168_driver_start(tp);
3505 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3507 if (pci_dev_run_wake(pdev))
3508 pm_runtime_put_noidle(&pdev->dev);
3510 netif_carrier_off(dev);
3516 rtl_disable_msi(pdev, tp);
3519 pci_release_regions(pdev);
3521 pci_clear_mwi(pdev);
3522 pci_disable_device(pdev);
3528 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3530 struct net_device *dev = pci_get_drvdata(pdev);
3531 struct rtl8169_private *tp = netdev_priv(dev);
3533 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3534 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3535 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3536 rtl8168_driver_stop(tp);
3539 cancel_delayed_work_sync(&tp->task);
3541 unregister_netdev(dev);
3543 rtl_release_firmware(tp);
3545 if (pci_dev_run_wake(pdev))
3546 pm_runtime_get_noresume(&pdev->dev);
3548 /* restore original MAC address */
3549 rtl_rar_set(tp, dev->perm_addr);
3551 rtl_disable_msi(pdev, tp);
3552 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3553 pci_set_drvdata(pdev, NULL);
3556 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3558 struct rtl_fw *rtl_fw;
3562 name = rtl_lookup_firmware_name(tp);
3564 goto out_no_firmware;
3566 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3570 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3574 tp->rtl_fw = rtl_fw;
3581 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3588 static void rtl_request_firmware(struct rtl8169_private *tp)
3590 if (IS_ERR(tp->rtl_fw))
3591 rtl_request_uncached_firmware(tp);
3594 static int rtl8169_open(struct net_device *dev)
3596 struct rtl8169_private *tp = netdev_priv(dev);
3597 void __iomem *ioaddr = tp->mmio_addr;
3598 struct pci_dev *pdev = tp->pci_dev;
3599 int retval = -ENOMEM;
3601 pm_runtime_get_sync(&pdev->dev);
3604 * Rx and Tx desscriptors needs 256 bytes alignment.
3605 * dma_alloc_coherent provides more.
3607 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3608 &tp->TxPhyAddr, GFP_KERNEL);
3609 if (!tp->TxDescArray)
3610 goto err_pm_runtime_put;
3612 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3613 &tp->RxPhyAddr, GFP_KERNEL);
3614 if (!tp->RxDescArray)
3617 retval = rtl8169_init_ring(dev);
3621 INIT_DELAYED_WORK(&tp->task, NULL);
3625 rtl_request_firmware(tp);
3627 retval = request_irq(dev->irq, rtl8169_interrupt,
3628 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3631 goto err_release_fw_2;
3633 napi_enable(&tp->napi);
3635 rtl8169_init_phy(dev, tp);
3637 rtl8169_set_features(dev, dev->features);
3639 rtl_pll_power_up(tp);
3643 tp->saved_wolopts = 0;
3644 pm_runtime_put_noidle(&pdev->dev);
3646 rtl8169_check_link_status(dev, tp, ioaddr);
3651 rtl_release_firmware(tp);
3652 rtl8169_rx_clear(tp);
3654 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3656 tp->RxDescArray = NULL;
3658 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3660 tp->TxDescArray = NULL;
3662 pm_runtime_put_noidle(&pdev->dev);
3666 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3668 void __iomem *ioaddr = tp->mmio_addr;
3670 /* Disable interrupts */
3671 rtl8169_irq_mask_and_ack(ioaddr);
3673 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3674 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3675 tp->mac_version == RTL_GIGA_MAC_VER_31) {
3676 while (RTL_R8(TxPoll) & NPQ)
3681 /* Reset the chipset */
3682 RTL_W8(ChipCmd, CmdReset);
3688 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3690 void __iomem *ioaddr = tp->mmio_addr;
3691 u32 cfg = rtl8169_rx_config;
3693 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3694 RTL_W32(RxConfig, cfg);
3696 /* Set DMA burst size and Interframe Gap Time */
3697 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3698 (InterFrameGap << TxInterFrameGapShift));
3701 static void rtl_hw_start(struct net_device *dev)
3703 struct rtl8169_private *tp = netdev_priv(dev);
3709 netif_start_queue(dev);
3712 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3713 void __iomem *ioaddr)
3716 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3717 * register to be written before TxDescAddrLow to work.
3718 * Switching from MMIO to I/O access fixes the issue as well.
3720 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3721 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3722 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3723 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3726 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3730 cmd = RTL_R16(CPlusCmd);
3731 RTL_W16(CPlusCmd, cmd);
3735 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3737 /* Low hurts. Let's disable the filtering. */
3738 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3741 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3743 static const struct {
3748 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3749 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3750 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3751 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3756 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3757 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3758 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3759 RTL_W32(0x7c, p->val);
3765 static void rtl_hw_start_8169(struct net_device *dev)
3767 struct rtl8169_private *tp = netdev_priv(dev);
3768 void __iomem *ioaddr = tp->mmio_addr;
3769 struct pci_dev *pdev = tp->pci_dev;
3771 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3772 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3773 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3776 RTL_W8(Cfg9346, Cfg9346_Unlock);
3777 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3778 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3779 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3780 tp->mac_version == RTL_GIGA_MAC_VER_04)
3781 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3783 RTL_W8(EarlyTxThres, NoEarlyTx);
3785 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3787 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3788 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3789 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3790 tp->mac_version == RTL_GIGA_MAC_VER_04)
3791 rtl_set_rx_tx_config_registers(tp);
3793 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3795 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3796 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3797 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3798 "Bit-3 and bit-14 MUST be 1\n");
3799 tp->cp_cmd |= (1 << 14);
3802 RTL_W16(CPlusCmd, tp->cp_cmd);
3804 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3807 * Undocumented corner. Supposedly:
3808 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3810 RTL_W16(IntrMitigate, 0x0000);
3812 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3814 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3815 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3816 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3817 tp->mac_version != RTL_GIGA_MAC_VER_04) {
3818 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3819 rtl_set_rx_tx_config_registers(tp);
3822 RTL_W8(Cfg9346, Cfg9346_Lock);
3824 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3827 RTL_W32(RxMissed, 0);
3829 rtl_set_rx_mode(dev);
3831 /* no early-rx interrupts */
3832 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3834 /* Enable all known interrupts by setting the interrupt mask. */
3835 RTL_W16(IntrMask, tp->intr_event);
3838 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3840 struct net_device *dev = pci_get_drvdata(pdev);
3841 struct rtl8169_private *tp = netdev_priv(dev);
3842 int cap = tp->pcie_cap;
3847 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3848 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3849 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3853 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3857 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3858 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3861 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3863 rtl_csi_access_enable(ioaddr, 0x17000000);
3866 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3868 rtl_csi_access_enable(ioaddr, 0x27000000);
3872 unsigned int offset;
3877 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3882 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3883 rtl_ephy_write(ioaddr, e->offset, w);
3888 static void rtl_disable_clock_request(struct pci_dev *pdev)
3890 struct net_device *dev = pci_get_drvdata(pdev);
3891 struct rtl8169_private *tp = netdev_priv(dev);
3892 int cap = tp->pcie_cap;
3897 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3898 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3899 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3903 static void rtl_enable_clock_request(struct pci_dev *pdev)
3905 struct net_device *dev = pci_get_drvdata(pdev);
3906 struct rtl8169_private *tp = netdev_priv(dev);
3907 int cap = tp->pcie_cap;
3912 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3913 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3914 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3918 #define R8168_CPCMD_QUIRK_MASK (\
3929 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3931 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3933 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3935 rtl_tx_performance_tweak(pdev,
3936 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3939 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3941 rtl_hw_start_8168bb(ioaddr, pdev);
3943 RTL_W8(MaxTxPacketSize, TxPacketMax);
3945 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3948 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3950 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3952 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3954 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3956 rtl_disable_clock_request(pdev);
3958 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3961 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3963 static const struct ephy_info e_info_8168cp[] = {
3964 { 0x01, 0, 0x0001 },
3965 { 0x02, 0x0800, 0x1000 },
3966 { 0x03, 0, 0x0042 },
3967 { 0x06, 0x0080, 0x0000 },
3971 rtl_csi_access_enable_2(ioaddr);
3973 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3975 __rtl_hw_start_8168cp(ioaddr, pdev);
3978 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3980 rtl_csi_access_enable_2(ioaddr);
3982 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3984 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3986 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3989 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3991 rtl_csi_access_enable_2(ioaddr);
3993 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3996 RTL_W8(DBG_REG, 0x20);
3998 RTL_W8(MaxTxPacketSize, TxPacketMax);
4000 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4002 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4005 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4007 static const struct ephy_info e_info_8168c_1[] = {
4008 { 0x02, 0x0800, 0x1000 },
4009 { 0x03, 0, 0x0002 },
4010 { 0x06, 0x0080, 0x0000 }
4013 rtl_csi_access_enable_2(ioaddr);
4015 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4017 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4019 __rtl_hw_start_8168cp(ioaddr, pdev);
4022 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4024 static const struct ephy_info e_info_8168c_2[] = {
4025 { 0x01, 0, 0x0001 },
4026 { 0x03, 0x0400, 0x0220 }
4029 rtl_csi_access_enable_2(ioaddr);
4031 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4033 __rtl_hw_start_8168cp(ioaddr, pdev);
4036 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4038 rtl_hw_start_8168c_2(ioaddr, pdev);
4041 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4043 rtl_csi_access_enable_2(ioaddr);
4045 __rtl_hw_start_8168cp(ioaddr, pdev);
4048 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4050 rtl_csi_access_enable_2(ioaddr);
4052 rtl_disable_clock_request(pdev);
4054 RTL_W8(MaxTxPacketSize, TxPacketMax);
4056 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4058 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4061 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4063 rtl_csi_access_enable_1(ioaddr);
4065 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4067 RTL_W8(MaxTxPacketSize, TxPacketMax);
4069 rtl_disable_clock_request(pdev);
4072 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4074 static const struct ephy_info e_info_8168d_4[] = {
4076 { 0x19, 0x20, 0x50 },
4081 rtl_csi_access_enable_1(ioaddr);
4083 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4085 RTL_W8(MaxTxPacketSize, TxPacketMax);
4087 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4088 const struct ephy_info *e = e_info_8168d_4 + i;
4091 w = rtl_ephy_read(ioaddr, e->offset);
4092 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4095 rtl_enable_clock_request(pdev);
4098 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4100 static const struct ephy_info e_info_8168e[] = {
4101 { 0x00, 0x0200, 0x0100 },
4102 { 0x00, 0x0000, 0x0004 },
4103 { 0x06, 0x0002, 0x0001 },
4104 { 0x06, 0x0000, 0x0030 },
4105 { 0x07, 0x0000, 0x2000 },
4106 { 0x00, 0x0000, 0x0020 },
4107 { 0x03, 0x5800, 0x2000 },
4108 { 0x03, 0x0000, 0x0001 },
4109 { 0x01, 0x0800, 0x1000 },
4110 { 0x07, 0x0000, 0x4000 },
4111 { 0x1e, 0x0000, 0x2000 },
4112 { 0x19, 0xffff, 0xfe6c },
4113 { 0x0a, 0x0000, 0x0040 }
4116 rtl_csi_access_enable_2(ioaddr);
4118 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4120 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4122 RTL_W8(MaxTxPacketSize, TxPacketMax);
4124 rtl_disable_clock_request(pdev);
4126 /* Reset tx FIFO pointer */
4127 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4128 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4130 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4133 static void rtl_hw_start_8168(struct net_device *dev)
4135 struct rtl8169_private *tp = netdev_priv(dev);
4136 void __iomem *ioaddr = tp->mmio_addr;
4137 struct pci_dev *pdev = tp->pci_dev;
4139 RTL_W8(Cfg9346, Cfg9346_Unlock);
4141 RTL_W8(MaxTxPacketSize, TxPacketMax);
4143 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4145 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4147 RTL_W16(CPlusCmd, tp->cp_cmd);
4149 RTL_W16(IntrMitigate, 0x5151);
4151 /* Work around for RxFIFO overflow. */
4152 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4153 tp->mac_version == RTL_GIGA_MAC_VER_22) {
4154 tp->intr_event |= RxFIFOOver | PCSTimeout;
4155 tp->intr_event &= ~RxOverflow;
4158 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4160 rtl_set_rx_mode(dev);
4162 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4163 (InterFrameGap << TxInterFrameGapShift));
4167 switch (tp->mac_version) {
4168 case RTL_GIGA_MAC_VER_11:
4169 rtl_hw_start_8168bb(ioaddr, pdev);
4172 case RTL_GIGA_MAC_VER_12:
4173 case RTL_GIGA_MAC_VER_17:
4174 rtl_hw_start_8168bef(ioaddr, pdev);
4177 case RTL_GIGA_MAC_VER_18:
4178 rtl_hw_start_8168cp_1(ioaddr, pdev);
4181 case RTL_GIGA_MAC_VER_19:
4182 rtl_hw_start_8168c_1(ioaddr, pdev);
4185 case RTL_GIGA_MAC_VER_20:
4186 rtl_hw_start_8168c_2(ioaddr, pdev);
4189 case RTL_GIGA_MAC_VER_21:
4190 rtl_hw_start_8168c_3(ioaddr, pdev);
4193 case RTL_GIGA_MAC_VER_22:
4194 rtl_hw_start_8168c_4(ioaddr, pdev);
4197 case RTL_GIGA_MAC_VER_23:
4198 rtl_hw_start_8168cp_2(ioaddr, pdev);
4201 case RTL_GIGA_MAC_VER_24:
4202 rtl_hw_start_8168cp_3(ioaddr, pdev);
4205 case RTL_GIGA_MAC_VER_25:
4206 case RTL_GIGA_MAC_VER_26:
4207 case RTL_GIGA_MAC_VER_27:
4208 rtl_hw_start_8168d(ioaddr, pdev);
4211 case RTL_GIGA_MAC_VER_28:
4212 rtl_hw_start_8168d_4(ioaddr, pdev);
4215 case RTL_GIGA_MAC_VER_31:
4216 rtl_hw_start_8168dp(ioaddr, pdev);
4219 case RTL_GIGA_MAC_VER_32:
4220 case RTL_GIGA_MAC_VER_33:
4221 rtl_hw_start_8168e(ioaddr, pdev);
4225 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4226 dev->name, tp->mac_version);
4230 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4232 RTL_W8(Cfg9346, Cfg9346_Lock);
4234 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4236 RTL_W16(IntrMask, tp->intr_event);
4239 #define R810X_CPCMD_QUIRK_MASK (\
4250 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4252 static const struct ephy_info e_info_8102e_1[] = {
4253 { 0x01, 0, 0x6e65 },
4254 { 0x02, 0, 0x091f },
4255 { 0x03, 0, 0xc2f9 },
4256 { 0x06, 0, 0xafb5 },
4257 { 0x07, 0, 0x0e00 },
4258 { 0x19, 0, 0xec80 },
4259 { 0x01, 0, 0x2e65 },
4264 rtl_csi_access_enable_2(ioaddr);
4266 RTL_W8(DBG_REG, FIX_NAK_1);
4268 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4271 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4272 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4274 cfg1 = RTL_R8(Config1);
4275 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4276 RTL_W8(Config1, cfg1 & ~LEDS0);
4278 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4281 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4283 rtl_csi_access_enable_2(ioaddr);
4285 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4287 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4288 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4291 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4293 rtl_hw_start_8102e_2(ioaddr, pdev);
4295 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4298 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4300 static const struct ephy_info e_info_8105e_1[] = {
4301 { 0x07, 0, 0x4000 },
4302 { 0x19, 0, 0x0200 },
4303 { 0x19, 0, 0x0020 },
4304 { 0x1e, 0, 0x2000 },
4305 { 0x03, 0, 0x0001 },
4306 { 0x19, 0, 0x0100 },
4307 { 0x19, 0, 0x0004 },
4311 /* Force LAN exit from ASPM if Rx/Tx are not idle */
4312 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4314 /* Disable Early Tally Counter */
4315 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4317 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4318 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4320 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4323 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4325 rtl_hw_start_8105e_1(ioaddr, pdev);
4326 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4329 static void rtl_hw_start_8101(struct net_device *dev)
4331 struct rtl8169_private *tp = netdev_priv(dev);
4332 void __iomem *ioaddr = tp->mmio_addr;
4333 struct pci_dev *pdev = tp->pci_dev;
4335 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4336 tp->mac_version == RTL_GIGA_MAC_VER_16) {
4337 int cap = tp->pcie_cap;
4340 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4341 PCI_EXP_DEVCTL_NOSNOOP_EN);
4345 RTL_W8(Cfg9346, Cfg9346_Unlock);
4347 switch (tp->mac_version) {
4348 case RTL_GIGA_MAC_VER_07:
4349 rtl_hw_start_8102e_1(ioaddr, pdev);
4352 case RTL_GIGA_MAC_VER_08:
4353 rtl_hw_start_8102e_3(ioaddr, pdev);
4356 case RTL_GIGA_MAC_VER_09:
4357 rtl_hw_start_8102e_2(ioaddr, pdev);
4360 case RTL_GIGA_MAC_VER_29:
4361 rtl_hw_start_8105e_1(ioaddr, pdev);
4363 case RTL_GIGA_MAC_VER_30:
4364 rtl_hw_start_8105e_2(ioaddr, pdev);
4368 RTL_W8(Cfg9346, Cfg9346_Lock);
4370 RTL_W8(MaxTxPacketSize, TxPacketMax);
4372 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4374 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4375 RTL_W16(CPlusCmd, tp->cp_cmd);
4377 RTL_W16(IntrMitigate, 0x0000);
4379 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4381 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4382 rtl_set_rx_tx_config_registers(tp);
4386 rtl_set_rx_mode(dev);
4388 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4390 RTL_W16(IntrMask, tp->intr_event);
4393 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4395 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4399 netdev_update_features(dev);
4404 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4406 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4407 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4410 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4411 void **data_buff, struct RxDesc *desc)
4413 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4418 rtl8169_make_unusable_by_asic(desc);
4421 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4423 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4425 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4428 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4431 desc->addr = cpu_to_le64(mapping);
4433 rtl8169_mark_to_asic(desc, rx_buf_sz);
4436 static inline void *rtl8169_align(void *data)
4438 return (void *)ALIGN((long)data, 16);
4441 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4442 struct RxDesc *desc)
4446 struct device *d = &tp->pci_dev->dev;
4447 struct net_device *dev = tp->dev;
4448 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4450 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4454 if (rtl8169_align(data) != data) {
4456 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4461 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4463 if (unlikely(dma_mapping_error(d, mapping))) {
4464 if (net_ratelimit())
4465 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4469 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4477 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4481 for (i = 0; i < NUM_RX_DESC; i++) {
4482 if (tp->Rx_databuff[i]) {
4483 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4484 tp->RxDescArray + i);
4489 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4491 desc->opts1 |= cpu_to_le32(RingEnd);
4494 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4498 for (i = 0; i < NUM_RX_DESC; i++) {
4501 if (tp->Rx_databuff[i])
4504 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4506 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4509 tp->Rx_databuff[i] = data;
4512 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4516 rtl8169_rx_clear(tp);
4520 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4522 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4525 static int rtl8169_init_ring(struct net_device *dev)
4527 struct rtl8169_private *tp = netdev_priv(dev);
4529 rtl8169_init_ring_indexes(tp);
4531 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4532 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4534 return rtl8169_rx_fill(tp);
4537 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4538 struct TxDesc *desc)
4540 unsigned int len = tx_skb->len;
4542 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4550 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4555 for (i = 0; i < n; i++) {
4556 unsigned int entry = (start + i) % NUM_TX_DESC;
4557 struct ring_info *tx_skb = tp->tx_skb + entry;
4558 unsigned int len = tx_skb->len;
4561 struct sk_buff *skb = tx_skb->skb;
4563 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4564 tp->TxDescArray + entry);
4566 tp->dev->stats.tx_dropped++;
4574 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4576 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4577 tp->cur_tx = tp->dirty_tx = 0;
4580 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4582 struct rtl8169_private *tp = netdev_priv(dev);
4584 PREPARE_DELAYED_WORK(&tp->task, task);
4585 schedule_delayed_work(&tp->task, 4);
4588 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4590 struct rtl8169_private *tp = netdev_priv(dev);
4591 void __iomem *ioaddr = tp->mmio_addr;
4593 synchronize_irq(dev->irq);
4595 /* Wait for any pending NAPI task to complete */
4596 napi_disable(&tp->napi);
4598 rtl8169_irq_mask_and_ack(ioaddr);
4600 tp->intr_mask = 0xffff;
4601 RTL_W16(IntrMask, tp->intr_event);
4602 napi_enable(&tp->napi);
4605 static void rtl8169_reinit_task(struct work_struct *work)
4607 struct rtl8169_private *tp =
4608 container_of(work, struct rtl8169_private, task.work);
4609 struct net_device *dev = tp->dev;
4614 if (!netif_running(dev))
4617 rtl8169_wait_for_quiescence(dev);
4620 ret = rtl8169_open(dev);
4621 if (unlikely(ret < 0)) {
4622 if (net_ratelimit())
4623 netif_err(tp, drv, dev,
4624 "reinit failure (status = %d). Rescheduling\n",
4626 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4633 static void rtl8169_reset_task(struct work_struct *work)
4635 struct rtl8169_private *tp =
4636 container_of(work, struct rtl8169_private, task.work);
4637 struct net_device *dev = tp->dev;
4642 if (!netif_running(dev))
4645 rtl8169_wait_for_quiescence(dev);
4647 for (i = 0; i < NUM_RX_DESC; i++)
4648 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4650 rtl8169_tx_clear(tp);
4652 rtl8169_init_ring_indexes(tp);
4654 netif_wake_queue(dev);
4655 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4661 static void rtl8169_tx_timeout(struct net_device *dev)
4663 struct rtl8169_private *tp = netdev_priv(dev);
4665 rtl8169_hw_reset(tp);
4667 /* Let's wait a bit while any (async) irq lands on */
4668 rtl8169_schedule_work(dev, rtl8169_reset_task);
4671 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4674 struct skb_shared_info *info = skb_shinfo(skb);
4675 unsigned int cur_frag, entry;
4676 struct TxDesc * uninitialized_var(txd);
4677 struct device *d = &tp->pci_dev->dev;
4680 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4681 skb_frag_t *frag = info->frags + cur_frag;
4686 entry = (entry + 1) % NUM_TX_DESC;
4688 txd = tp->TxDescArray + entry;
4690 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4691 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4692 if (unlikely(dma_mapping_error(d, mapping))) {
4693 if (net_ratelimit())
4694 netif_err(tp, drv, tp->dev,
4695 "Failed to map TX fragments DMA!\n");
4699 /* Anti gcc 2.95.3 bugware (sic) */
4700 status = opts[0] | len |
4701 (RingEnd * !((entry + 1) % NUM_TX_DESC));
4703 txd->opts1 = cpu_to_le32(status);
4704 txd->opts2 = cpu_to_le32(opts[1]);
4705 txd->addr = cpu_to_le64(mapping);
4707 tp->tx_skb[entry].len = len;
4711 tp->tx_skb[entry].skb = skb;
4712 txd->opts1 |= cpu_to_le32(LastFrag);
4718 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4722 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4723 struct sk_buff *skb, u32 *opts)
4725 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4726 u32 mss = skb_shinfo(skb)->gso_size;
4727 int offset = info->opts_offset;
4731 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4732 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4733 const struct iphdr *ip = ip_hdr(skb);
4735 if (ip->protocol == IPPROTO_TCP)
4736 opts[offset] |= info->checksum.tcp;
4737 else if (ip->protocol == IPPROTO_UDP)
4738 opts[offset] |= info->checksum.udp;
4744 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4745 struct net_device *dev)
4747 struct rtl8169_private *tp = netdev_priv(dev);
4748 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4749 struct TxDesc *txd = tp->TxDescArray + entry;
4750 void __iomem *ioaddr = tp->mmio_addr;
4751 struct device *d = &tp->pci_dev->dev;
4757 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4758 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4762 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4765 len = skb_headlen(skb);
4766 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4767 if (unlikely(dma_mapping_error(d, mapping))) {
4768 if (net_ratelimit())
4769 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4773 tp->tx_skb[entry].len = len;
4774 txd->addr = cpu_to_le64(mapping);
4776 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4779 rtl8169_tso_csum(tp, skb, opts);
4781 frags = rtl8169_xmit_frags(tp, skb, opts);
4785 opts[0] |= FirstFrag;
4787 opts[0] |= FirstFrag | LastFrag;
4788 tp->tx_skb[entry].skb = skb;
4791 txd->opts2 = cpu_to_le32(opts[1]);
4795 /* Anti gcc 2.95.3 bugware (sic) */
4796 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4797 txd->opts1 = cpu_to_le32(status);
4799 tp->cur_tx += frags + 1;
4803 RTL_W8(TxPoll, NPQ);
4805 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4806 netif_stop_queue(dev);
4808 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4809 netif_wake_queue(dev);
4812 return NETDEV_TX_OK;
4815 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4818 dev->stats.tx_dropped++;
4819 return NETDEV_TX_OK;
4822 netif_stop_queue(dev);
4823 dev->stats.tx_dropped++;
4824 return NETDEV_TX_BUSY;
4827 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4829 struct rtl8169_private *tp = netdev_priv(dev);
4830 struct pci_dev *pdev = tp->pci_dev;
4831 u16 pci_status, pci_cmd;
4833 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4834 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4836 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4837 pci_cmd, pci_status);
4840 * The recovery sequence below admits a very elaborated explanation:
4841 * - it seems to work;
4842 * - I did not see what else could be done;
4843 * - it makes iop3xx happy.
4845 * Feel free to adjust to your needs.
4847 if (pdev->broken_parity_status)
4848 pci_cmd &= ~PCI_COMMAND_PARITY;
4850 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4852 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4854 pci_write_config_word(pdev, PCI_STATUS,
4855 pci_status & (PCI_STATUS_DETECTED_PARITY |
4856 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4857 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4859 /* The infamous DAC f*ckup only happens at boot time */
4860 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4861 void __iomem *ioaddr = tp->mmio_addr;
4863 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4864 tp->cp_cmd &= ~PCIDAC;
4865 RTL_W16(CPlusCmd, tp->cp_cmd);
4866 dev->features &= ~NETIF_F_HIGHDMA;
4869 rtl8169_hw_reset(tp);
4871 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4874 static void rtl8169_tx_interrupt(struct net_device *dev,
4875 struct rtl8169_private *tp,
4876 void __iomem *ioaddr)
4878 unsigned int dirty_tx, tx_left;
4880 dirty_tx = tp->dirty_tx;
4882 tx_left = tp->cur_tx - dirty_tx;
4884 while (tx_left > 0) {
4885 unsigned int entry = dirty_tx % NUM_TX_DESC;
4886 struct ring_info *tx_skb = tp->tx_skb + entry;
4890 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4891 if (status & DescOwn)
4894 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4895 tp->TxDescArray + entry);
4896 if (status & LastFrag) {
4897 dev->stats.tx_packets++;
4898 dev->stats.tx_bytes += tx_skb->skb->len;
4899 dev_kfree_skb(tx_skb->skb);
4906 if (tp->dirty_tx != dirty_tx) {
4907 tp->dirty_tx = dirty_tx;
4909 if (netif_queue_stopped(dev) &&
4910 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4911 netif_wake_queue(dev);
4914 * 8168 hack: TxPoll requests are lost when the Tx packets are
4915 * too close. Let's kick an extra TxPoll request when a burst
4916 * of start_xmit activity is detected (if it is not detected,
4917 * it is slow enough). -- FR
4920 if (tp->cur_tx != dirty_tx)
4921 RTL_W8(TxPoll, NPQ);
4925 static inline int rtl8169_fragmented_frame(u32 status)
4927 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4930 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4932 u32 status = opts1 & RxProtoMask;
4934 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4935 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4936 skb->ip_summed = CHECKSUM_UNNECESSARY;
4938 skb_checksum_none_assert(skb);
4941 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4942 struct rtl8169_private *tp,
4946 struct sk_buff *skb;
4947 struct device *d = &tp->pci_dev->dev;
4949 data = rtl8169_align(data);
4950 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4952 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4954 memcpy(skb->data, data, pkt_size);
4955 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4960 static int rtl8169_rx_interrupt(struct net_device *dev,
4961 struct rtl8169_private *tp,
4962 void __iomem *ioaddr, u32 budget)
4964 unsigned int cur_rx, rx_left;
4967 cur_rx = tp->cur_rx;
4968 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4969 rx_left = min(rx_left, budget);
4971 for (; rx_left > 0; rx_left--, cur_rx++) {
4972 unsigned int entry = cur_rx % NUM_RX_DESC;
4973 struct RxDesc *desc = tp->RxDescArray + entry;
4977 status = le32_to_cpu(desc->opts1);
4979 if (status & DescOwn)
4981 if (unlikely(status & RxRES)) {
4982 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4984 dev->stats.rx_errors++;
4985 if (status & (RxRWT | RxRUNT))
4986 dev->stats.rx_length_errors++;
4988 dev->stats.rx_crc_errors++;
4989 if (status & RxFOVF) {
4990 rtl8169_schedule_work(dev, rtl8169_reset_task);
4991 dev->stats.rx_fifo_errors++;
4993 rtl8169_mark_to_asic(desc, rx_buf_sz);
4995 struct sk_buff *skb;
4996 dma_addr_t addr = le64_to_cpu(desc->addr);
4997 int pkt_size = (status & 0x00001FFF) - 4;
5000 * The driver does not support incoming fragmented
5001 * frames. They are seen as a symptom of over-mtu
5004 if (unlikely(rtl8169_fragmented_frame(status))) {
5005 dev->stats.rx_dropped++;
5006 dev->stats.rx_length_errors++;
5007 rtl8169_mark_to_asic(desc, rx_buf_sz);
5011 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5012 tp, pkt_size, addr);
5013 rtl8169_mark_to_asic(desc, rx_buf_sz);
5015 dev->stats.rx_dropped++;
5019 rtl8169_rx_csum(skb, status);
5020 skb_put(skb, pkt_size);
5021 skb->protocol = eth_type_trans(skb, dev);
5023 rtl8169_rx_vlan_tag(desc, skb);
5025 napi_gro_receive(&tp->napi, skb);
5027 dev->stats.rx_bytes += pkt_size;
5028 dev->stats.rx_packets++;
5031 /* Work around for AMD plateform. */
5032 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5033 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5039 count = cur_rx - tp->cur_rx;
5040 tp->cur_rx = cur_rx;
5042 tp->dirty_rx += count;
5047 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5049 struct net_device *dev = dev_instance;
5050 struct rtl8169_private *tp = netdev_priv(dev);
5051 void __iomem *ioaddr = tp->mmio_addr;
5055 /* loop handling interrupts until we have no new ones or
5056 * we hit a invalid/hotplug case.
5058 status = RTL_R16(IntrStatus);
5059 while (status && status != 0xffff) {
5062 /* Handle all of the error cases first. These will reset
5063 * the chip, so just exit the loop.
5065 if (unlikely(!netif_running(dev))) {
5066 rtl8169_asic_down(ioaddr);
5070 if (unlikely(status & RxFIFOOver)) {
5071 switch (tp->mac_version) {
5072 /* Work around for rx fifo overflow */
5073 case RTL_GIGA_MAC_VER_11:
5074 case RTL_GIGA_MAC_VER_22:
5075 case RTL_GIGA_MAC_VER_26:
5076 netif_stop_queue(dev);
5077 rtl8169_tx_timeout(dev);
5079 /* Testers needed. */
5080 case RTL_GIGA_MAC_VER_17:
5081 case RTL_GIGA_MAC_VER_19:
5082 case RTL_GIGA_MAC_VER_20:
5083 case RTL_GIGA_MAC_VER_21:
5084 case RTL_GIGA_MAC_VER_23:
5085 case RTL_GIGA_MAC_VER_24:
5086 case RTL_GIGA_MAC_VER_27:
5087 case RTL_GIGA_MAC_VER_28:
5088 case RTL_GIGA_MAC_VER_31:
5089 /* Experimental science. Pktgen proof. */
5090 case RTL_GIGA_MAC_VER_12:
5091 case RTL_GIGA_MAC_VER_25:
5092 if (status == RxFIFOOver)
5100 if (unlikely(status & SYSErr)) {
5101 rtl8169_pcierr_interrupt(dev);
5105 if (status & LinkChg)
5106 __rtl8169_check_link_status(dev, tp, ioaddr, true);
5108 /* We need to see the lastest version of tp->intr_mask to
5109 * avoid ignoring an MSI interrupt and having to wait for
5110 * another event which may never come.
5113 if (status & tp->intr_mask & tp->napi_event) {
5114 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5115 tp->intr_mask = ~tp->napi_event;
5117 if (likely(napi_schedule_prep(&tp->napi)))
5118 __napi_schedule(&tp->napi);
5120 netif_info(tp, intr, dev,
5121 "interrupt %04x in poll\n", status);
5124 /* We only get a new MSI interrupt when all active irq
5125 * sources on the chip have been acknowledged. So, ack
5126 * everything we've seen and check if new sources have become
5127 * active to avoid blocking all interrupts from the chip.
5130 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5131 status = RTL_R16(IntrStatus);
5134 return IRQ_RETVAL(handled);
5137 static int rtl8169_poll(struct napi_struct *napi, int budget)
5139 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5140 struct net_device *dev = tp->dev;
5141 void __iomem *ioaddr = tp->mmio_addr;
5144 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5145 rtl8169_tx_interrupt(dev, tp, ioaddr);
5147 if (work_done < budget) {
5148 napi_complete(napi);
5150 /* We need for force the visibility of tp->intr_mask
5151 * for other CPUs, as we can loose an MSI interrupt
5152 * and potentially wait for a retransmit timeout if we don't.
5153 * The posted write to IntrMask is safe, as it will
5154 * eventually make it to the chip and we won't loose anything
5157 tp->intr_mask = 0xffff;
5159 RTL_W16(IntrMask, tp->intr_event);
5165 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5167 struct rtl8169_private *tp = netdev_priv(dev);
5169 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5172 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5173 RTL_W32(RxMissed, 0);
5176 static void rtl8169_down(struct net_device *dev)
5178 struct rtl8169_private *tp = netdev_priv(dev);
5179 void __iomem *ioaddr = tp->mmio_addr;
5181 del_timer_sync(&tp->timer);
5183 netif_stop_queue(dev);
5185 napi_disable(&tp->napi);
5187 spin_lock_irq(&tp->lock);
5189 rtl8169_asic_down(ioaddr);
5191 * At this point device interrupts can not be enabled in any function,
5192 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5193 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5195 rtl8169_rx_missed(dev, ioaddr);
5197 spin_unlock_irq(&tp->lock);
5199 synchronize_irq(dev->irq);
5201 /* Give a racing hard_start_xmit a few cycles to complete. */
5202 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
5204 rtl8169_tx_clear(tp);
5206 rtl8169_rx_clear(tp);
5208 rtl_pll_power_down(tp);
5211 static int rtl8169_close(struct net_device *dev)
5213 struct rtl8169_private *tp = netdev_priv(dev);
5214 struct pci_dev *pdev = tp->pci_dev;
5216 pm_runtime_get_sync(&pdev->dev);
5218 /* Update counters before going down */
5219 rtl8169_update_counters(dev);
5223 free_irq(dev->irq, dev);
5225 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5227 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5229 tp->TxDescArray = NULL;
5230 tp->RxDescArray = NULL;
5232 pm_runtime_put_sync(&pdev->dev);
5237 static void rtl_set_rx_mode(struct net_device *dev)
5239 struct rtl8169_private *tp = netdev_priv(dev);
5240 void __iomem *ioaddr = tp->mmio_addr;
5241 unsigned long flags;
5242 u32 mc_filter[2]; /* Multicast hash filter */
5246 if (dev->flags & IFF_PROMISC) {
5247 /* Unconditionally log net taps. */
5248 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5250 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5252 mc_filter[1] = mc_filter[0] = 0xffffffff;
5253 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5254 (dev->flags & IFF_ALLMULTI)) {
5255 /* Too many to filter perfectly -- accept all multicasts. */
5256 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5257 mc_filter[1] = mc_filter[0] = 0xffffffff;
5259 struct netdev_hw_addr *ha;
5261 rx_mode = AcceptBroadcast | AcceptMyPhys;
5262 mc_filter[1] = mc_filter[0] = 0;
5263 netdev_for_each_mc_addr(ha, dev) {
5264 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5265 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5266 rx_mode |= AcceptMulticast;
5270 spin_lock_irqsave(&tp->lock, flags);
5272 tmp = rtl8169_rx_config | rx_mode |
5273 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5275 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5276 u32 data = mc_filter[0];
5278 mc_filter[0] = swab32(mc_filter[1]);
5279 mc_filter[1] = swab32(data);
5282 RTL_W32(MAR0 + 4, mc_filter[1]);
5283 RTL_W32(MAR0 + 0, mc_filter[0]);
5285 RTL_W32(RxConfig, tmp);
5287 spin_unlock_irqrestore(&tp->lock, flags);
5291 * rtl8169_get_stats - Get rtl8169 read/write statistics
5292 * @dev: The Ethernet Device to get statistics for
5294 * Get TX/RX statistics for rtl8169
5296 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5298 struct rtl8169_private *tp = netdev_priv(dev);
5299 void __iomem *ioaddr = tp->mmio_addr;
5300 unsigned long flags;
5302 if (netif_running(dev)) {
5303 spin_lock_irqsave(&tp->lock, flags);
5304 rtl8169_rx_missed(dev, ioaddr);
5305 spin_unlock_irqrestore(&tp->lock, flags);
5311 static void rtl8169_net_suspend(struct net_device *dev)
5313 struct rtl8169_private *tp = netdev_priv(dev);
5315 if (!netif_running(dev))
5318 rtl_pll_power_down(tp);
5320 netif_device_detach(dev);
5321 netif_stop_queue(dev);
5326 static int rtl8169_suspend(struct device *device)
5328 struct pci_dev *pdev = to_pci_dev(device);
5329 struct net_device *dev = pci_get_drvdata(pdev);
5331 rtl8169_net_suspend(dev);
5336 static void __rtl8169_resume(struct net_device *dev)
5338 struct rtl8169_private *tp = netdev_priv(dev);
5340 netif_device_attach(dev);
5342 rtl_pll_power_up(tp);
5344 rtl8169_schedule_work(dev, rtl8169_reset_task);
5347 static int rtl8169_resume(struct device *device)
5349 struct pci_dev *pdev = to_pci_dev(device);
5350 struct net_device *dev = pci_get_drvdata(pdev);
5351 struct rtl8169_private *tp = netdev_priv(dev);
5353 rtl8169_init_phy(dev, tp);
5355 if (netif_running(dev))
5356 __rtl8169_resume(dev);
5361 static int rtl8169_runtime_suspend(struct device *device)
5363 struct pci_dev *pdev = to_pci_dev(device);
5364 struct net_device *dev = pci_get_drvdata(pdev);
5365 struct rtl8169_private *tp = netdev_priv(dev);
5367 if (!tp->TxDescArray)
5370 spin_lock_irq(&tp->lock);
5371 tp->saved_wolopts = __rtl8169_get_wol(tp);
5372 __rtl8169_set_wol(tp, WAKE_ANY);
5373 spin_unlock_irq(&tp->lock);
5375 rtl8169_net_suspend(dev);
5380 static int rtl8169_runtime_resume(struct device *device)
5382 struct pci_dev *pdev = to_pci_dev(device);
5383 struct net_device *dev = pci_get_drvdata(pdev);
5384 struct rtl8169_private *tp = netdev_priv(dev);
5386 if (!tp->TxDescArray)
5389 spin_lock_irq(&tp->lock);
5390 __rtl8169_set_wol(tp, tp->saved_wolopts);
5391 tp->saved_wolopts = 0;
5392 spin_unlock_irq(&tp->lock);
5394 rtl8169_init_phy(dev, tp);
5396 __rtl8169_resume(dev);
5401 static int rtl8169_runtime_idle(struct device *device)
5403 struct pci_dev *pdev = to_pci_dev(device);
5404 struct net_device *dev = pci_get_drvdata(pdev);
5405 struct rtl8169_private *tp = netdev_priv(dev);
5407 return tp->TxDescArray ? -EBUSY : 0;
5410 static const struct dev_pm_ops rtl8169_pm_ops = {
5411 .suspend = rtl8169_suspend,
5412 .resume = rtl8169_resume,
5413 .freeze = rtl8169_suspend,
5414 .thaw = rtl8169_resume,
5415 .poweroff = rtl8169_suspend,
5416 .restore = rtl8169_resume,
5417 .runtime_suspend = rtl8169_runtime_suspend,
5418 .runtime_resume = rtl8169_runtime_resume,
5419 .runtime_idle = rtl8169_runtime_idle,
5422 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5424 #else /* !CONFIG_PM */
5426 #define RTL8169_PM_OPS NULL
5428 #endif /* !CONFIG_PM */
5430 static void rtl_shutdown(struct pci_dev *pdev)
5432 struct net_device *dev = pci_get_drvdata(pdev);
5433 struct rtl8169_private *tp = netdev_priv(dev);
5434 void __iomem *ioaddr = tp->mmio_addr;
5436 rtl8169_net_suspend(dev);
5438 /* Restore original MAC address */
5439 rtl_rar_set(tp, dev->perm_addr);
5441 spin_lock_irq(&tp->lock);
5443 rtl8169_asic_down(ioaddr);
5445 spin_unlock_irq(&tp->lock);
5447 if (system_state == SYSTEM_POWER_OFF) {
5448 /* WoL fails with some 8168 when the receiver is disabled. */
5449 if (tp->features & RTL_FEATURE_WOL) {
5450 pci_clear_master(pdev);
5452 RTL_W8(ChipCmd, CmdRxEnb);
5457 pci_wake_from_d3(pdev, true);
5458 pci_set_power_state(pdev, PCI_D3hot);
5462 static struct pci_driver rtl8169_pci_driver = {
5464 .id_table = rtl8169_pci_tbl,
5465 .probe = rtl8169_init_one,
5466 .remove = __devexit_p(rtl8169_remove_one),
5467 .shutdown = rtl_shutdown,
5468 .driver.pm = RTL8169_PM_OPS,
5471 static int __init rtl8169_init_module(void)
5473 return pci_register_driver(&rtl8169_pci_driver);
5476 static void __exit rtl8169_cleanup_module(void)
5478 pci_unregister_driver(&rtl8169_pci_driver);
5481 module_init(rtl8169_init_module);
5482 module_exit(rtl8169_cleanup_module);