2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
113 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
114 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
115 RTL_GIGA_MAC_VER_23 = 0x17 // 8168CP
118 #define _R(NAME,MAC,MASK) \
119 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
121 static const struct {
124 u32 RxConfigMask; /* Clears the bits supported by this chip */
125 } rtl_chip_info[] = {
126 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
127 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
128 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
129 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
130 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
131 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
132 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
133 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
134 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
136 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
137 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
138 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
139 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
140 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
143 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
144 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
145 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880) // PCI-E
158 static void rtl_hw_start_8169(struct net_device *);
159 static void rtl_hw_start_8168(struct net_device *);
160 static void rtl_hw_start_8101(struct net_device *);
162 static struct pci_device_id rtl8169_pci_tbl[] = {
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
170 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032,
172 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
174 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
178 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
180 static int rx_copybreak = 200;
187 MAC0 = 0, /* Ethernet hardware address. */
189 MAR0 = 8, /* Multicast filter. */
190 CounterAddrLow = 0x10,
191 CounterAddrHigh = 0x14,
192 TxDescStartAddrLow = 0x20,
193 TxDescStartAddrHigh = 0x24,
194 TxHDescStartAddrLow = 0x28,
195 TxHDescStartAddrHigh = 0x2c,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
227 enum rtl8110_registers {
233 enum rtl8168_8101_registers {
236 #define CSIAR_FLAG 0x80000000
237 #define CSIAR_WRITE_CMD 0x80000000
238 #define CSIAR_BYTE_ENABLE 0x0f
239 #define CSIAR_BYTE_ENABLE_SHIFT 12
240 #define CSIAR_ADDR_MASK 0x0fff
243 #define EPHYAR_FLAG 0x80000000
244 #define EPHYAR_WRITE_CMD 0x80000000
245 #define EPHYAR_REG_MASK 0x1f
246 #define EPHYAR_REG_SHIFT 16
247 #define EPHYAR_DATA_MASK 0xffff
249 #define FIX_NAK_1 (1 << 4)
250 #define FIX_NAK_2 (1 << 3)
253 enum rtl_register_content {
254 /* InterruptStatusBits */
258 TxDescUnavail = 0x0080,
280 /* TXPoll register p.5 */
281 HPQ = 0x80, /* Poll cmd on the high prio queue */
282 NPQ = 0x40, /* Poll cmd on the low prio queue */
283 FSWInt = 0x01, /* Forced software interrupt */
287 Cfg9346_Unlock = 0xc0,
292 AcceptBroadcast = 0x08,
293 AcceptMulticast = 0x04,
295 AcceptAllPhys = 0x01,
302 TxInterFrameGapShift = 24,
303 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
305 /* Config1 register p.24 */
308 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
309 Speed_down = (1 << 4),
313 PMEnable = (1 << 0), /* Power Management Enable */
315 /* Config2 register p. 25 */
316 PCI_Clock_66MHz = 0x01,
317 PCI_Clock_33MHz = 0x00,
319 /* Config3 register p.25 */
320 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
321 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
322 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
324 /* Config5 register p.27 */
325 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
326 MWF = (1 << 5), /* Accept Multicast wakeup frame */
327 UWF = (1 << 4), /* Accept Unicast wakeup frame */
328 LanWake = (1 << 1), /* LanWake enable/disable */
329 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
332 TBIReset = 0x80000000,
333 TBILoopback = 0x40000000,
334 TBINwEnable = 0x20000000,
335 TBINwRestart = 0x10000000,
336 TBILinkOk = 0x02000000,
337 TBINwComplete = 0x01000000,
340 EnableBist = (1 << 15), // 8168 8101
341 Mac_dbgo_oe = (1 << 14), // 8168 8101
342 Normal_mode = (1 << 13), // unused
343 Force_half_dup = (1 << 12), // 8168 8101
344 Force_rxflow_en = (1 << 11), // 8168 8101
345 Force_txflow_en = (1 << 10), // 8168 8101
346 Cxpl_dbg_sel = (1 << 9), // 8168 8101
347 ASF = (1 << 8), // 8168 8101
348 PktCntrDisable = (1 << 7), // 8168 8101
349 Mac_dbgo_sel = 0x001c, // 8168
354 INTT_0 = 0x0000, // 8168
355 INTT_1 = 0x0001, // 8168
356 INTT_2 = 0x0002, // 8168
357 INTT_3 = 0x0003, // 8168
359 /* rtl8169_PHYstatus */
370 TBILinkOK = 0x02000000,
372 /* DumpCounterCommand */
376 enum desc_status_bit {
377 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
378 RingEnd = (1 << 30), /* End of descriptor ring */
379 FirstFrag = (1 << 29), /* First segment of a packet */
380 LastFrag = (1 << 28), /* Final segment of a packet */
383 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
384 MSSShift = 16, /* MSS value position */
385 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
386 IPCS = (1 << 18), /* Calculate IP checksum */
387 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
388 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
389 TxVlanTag = (1 << 17), /* Add VLAN tag */
392 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
393 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
395 #define RxProtoUDP (PID1)
396 #define RxProtoTCP (PID0)
397 #define RxProtoIP (PID1 | PID0)
398 #define RxProtoMask RxProtoIP
400 IPFail = (1 << 16), /* IP checksum failed */
401 UDPFail = (1 << 15), /* UDP/IP checksum failed */
402 TCPFail = (1 << 14), /* TCP/IP checksum failed */
403 RxVlanTag = (1 << 16), /* VLAN tag available */
406 #define RsvdMask 0x3fffc000
423 u8 __pad[sizeof(void *) - sizeof(u32)];
427 RTL_FEATURE_WOL = (1 << 0),
428 RTL_FEATURE_MSI = (1 << 1),
429 RTL_FEATURE_GMII = (1 << 2),
432 struct rtl8169_private {
433 void __iomem *mmio_addr; /* memory map physical address */
434 struct pci_dev *pci_dev; /* Index of PCI device */
435 struct net_device *dev;
436 struct napi_struct napi;
437 spinlock_t lock; /* spin lock flag */
441 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
442 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
445 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
446 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
447 dma_addr_t TxPhyAddr;
448 dma_addr_t RxPhyAddr;
449 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
450 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
453 struct timer_list timer;
458 int phy_auto_nego_reg;
459 int phy_1000_ctrl_reg;
460 #ifdef CONFIG_R8169_VLAN
461 struct vlan_group *vlgrp;
463 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
464 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
465 void (*phy_reset_enable)(void __iomem *);
466 void (*hw_start)(struct net_device *);
467 unsigned int (*phy_reset_pending)(void __iomem *);
468 unsigned int (*link_ok)(void __iomem *);
470 struct delayed_work task;
473 struct mii_if_info mii;
476 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
477 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
478 module_param(rx_copybreak, int, 0);
479 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
480 module_param(use_dac, int, 0);
481 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
482 module_param_named(debug, debug.msg_enable, int, 0);
483 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
484 MODULE_LICENSE("GPL");
485 MODULE_VERSION(RTL8169_VERSION);
487 static int rtl8169_open(struct net_device *dev);
488 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
489 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
490 static int rtl8169_init_ring(struct net_device *dev);
491 static void rtl_hw_start(struct net_device *dev);
492 static int rtl8169_close(struct net_device *dev);
493 static void rtl_set_rx_mode(struct net_device *dev);
494 static void rtl8169_tx_timeout(struct net_device *dev);
495 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
496 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
497 void __iomem *, u32 budget);
498 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
499 static void rtl8169_down(struct net_device *dev);
500 static void rtl8169_rx_clear(struct rtl8169_private *tp);
501 static int rtl8169_poll(struct napi_struct *napi, int budget);
503 static const unsigned int rtl8169_rx_config =
504 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
506 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
510 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
512 for (i = 20; i > 0; i--) {
514 * Check if the RTL8169 has completed writing to the specified
517 if (!(RTL_R32(PHYAR) & 0x80000000))
523 static int mdio_read(void __iomem *ioaddr, int reg_addr)
527 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
529 for (i = 20; i > 0; i--) {
531 * Check if the RTL8169 has completed retrieving data from
532 * the specified MII register.
534 if (RTL_R32(PHYAR) & 0x80000000) {
535 value = RTL_R32(PHYAR) & 0xffff;
543 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
545 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
548 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
551 struct rtl8169_private *tp = netdev_priv(dev);
552 void __iomem *ioaddr = tp->mmio_addr;
554 mdio_write(ioaddr, location, val);
557 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
559 struct rtl8169_private *tp = netdev_priv(dev);
560 void __iomem *ioaddr = tp->mmio_addr;
562 return mdio_read(ioaddr, location);
565 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
569 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
570 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
572 for (i = 0; i < 100; i++) {
573 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
579 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
584 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
586 for (i = 0; i < 100; i++) {
587 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
588 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
597 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
601 RTL_W32(CSIDR, value);
602 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
603 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
605 for (i = 0; i < 100; i++) {
606 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
612 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
617 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
618 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
620 for (i = 0; i < 100; i++) {
621 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
622 value = RTL_R32(CSIDR);
631 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
633 RTL_W16(IntrMask, 0x0000);
635 RTL_W16(IntrStatus, 0xffff);
638 static void rtl8169_asic_down(void __iomem *ioaddr)
640 RTL_W8(ChipCmd, 0x00);
641 rtl8169_irq_mask_and_ack(ioaddr);
645 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
647 return RTL_R32(TBICSR) & TBIReset;
650 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
652 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
655 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
657 return RTL_R32(TBICSR) & TBILinkOk;
660 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
662 return RTL_R8(PHYstatus) & LinkStatus;
665 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
667 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
670 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
674 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
675 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
678 static void rtl8169_check_link_status(struct net_device *dev,
679 struct rtl8169_private *tp,
680 void __iomem *ioaddr)
684 spin_lock_irqsave(&tp->lock, flags);
685 if (tp->link_ok(ioaddr)) {
686 netif_carrier_on(dev);
687 if (netif_msg_ifup(tp))
688 printk(KERN_INFO PFX "%s: link up\n", dev->name);
690 if (netif_msg_ifdown(tp))
691 printk(KERN_INFO PFX "%s: link down\n", dev->name);
692 netif_carrier_off(dev);
694 spin_unlock_irqrestore(&tp->lock, flags);
697 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
699 struct rtl8169_private *tp = netdev_priv(dev);
700 void __iomem *ioaddr = tp->mmio_addr;
705 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
706 wol->supported = WAKE_ANY;
708 spin_lock_irq(&tp->lock);
710 options = RTL_R8(Config1);
711 if (!(options & PMEnable))
714 options = RTL_R8(Config3);
715 if (options & LinkUp)
716 wol->wolopts |= WAKE_PHY;
717 if (options & MagicPacket)
718 wol->wolopts |= WAKE_MAGIC;
720 options = RTL_R8(Config5);
722 wol->wolopts |= WAKE_UCAST;
724 wol->wolopts |= WAKE_BCAST;
726 wol->wolopts |= WAKE_MCAST;
729 spin_unlock_irq(&tp->lock);
732 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
734 struct rtl8169_private *tp = netdev_priv(dev);
735 void __iomem *ioaddr = tp->mmio_addr;
742 { WAKE_ANY, Config1, PMEnable },
743 { WAKE_PHY, Config3, LinkUp },
744 { WAKE_MAGIC, Config3, MagicPacket },
745 { WAKE_UCAST, Config5, UWF },
746 { WAKE_BCAST, Config5, BWF },
747 { WAKE_MCAST, Config5, MWF },
748 { WAKE_ANY, Config5, LanWake }
751 spin_lock_irq(&tp->lock);
753 RTL_W8(Cfg9346, Cfg9346_Unlock);
755 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
756 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
757 if (wol->wolopts & cfg[i].opt)
758 options |= cfg[i].mask;
759 RTL_W8(cfg[i].reg, options);
762 RTL_W8(Cfg9346, Cfg9346_Lock);
765 tp->features |= RTL_FEATURE_WOL;
767 tp->features &= ~RTL_FEATURE_WOL;
768 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
770 spin_unlock_irq(&tp->lock);
775 static void rtl8169_get_drvinfo(struct net_device *dev,
776 struct ethtool_drvinfo *info)
778 struct rtl8169_private *tp = netdev_priv(dev);
780 strcpy(info->driver, MODULENAME);
781 strcpy(info->version, RTL8169_VERSION);
782 strcpy(info->bus_info, pci_name(tp->pci_dev));
785 static int rtl8169_get_regs_len(struct net_device *dev)
787 return R8169_REGS_SIZE;
790 static int rtl8169_set_speed_tbi(struct net_device *dev,
791 u8 autoneg, u16 speed, u8 duplex)
793 struct rtl8169_private *tp = netdev_priv(dev);
794 void __iomem *ioaddr = tp->mmio_addr;
798 reg = RTL_R32(TBICSR);
799 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
800 (duplex == DUPLEX_FULL)) {
801 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
802 } else if (autoneg == AUTONEG_ENABLE)
803 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
805 if (netif_msg_link(tp)) {
806 printk(KERN_WARNING "%s: "
807 "incorrect speed setting refused in TBI mode\n",
816 static int rtl8169_set_speed_xmii(struct net_device *dev,
817 u8 autoneg, u16 speed, u8 duplex)
819 struct rtl8169_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->mmio_addr;
821 int auto_nego, giga_ctrl;
823 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
824 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
825 ADVERTISE_100HALF | ADVERTISE_100FULL);
826 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
827 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
829 if (autoneg == AUTONEG_ENABLE) {
830 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
831 ADVERTISE_100HALF | ADVERTISE_100FULL);
832 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
834 if (speed == SPEED_10)
835 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
836 else if (speed == SPEED_100)
837 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
838 else if (speed == SPEED_1000)
839 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
841 if (duplex == DUPLEX_HALF)
842 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
844 if (duplex == DUPLEX_FULL)
845 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
847 /* This tweak comes straight from Realtek's driver. */
848 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
849 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
850 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
851 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
855 /* The 8100e/8101e/8102e do Fast Ethernet only. */
856 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
858 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
859 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
860 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
861 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
862 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
863 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
864 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
865 netif_msg_link(tp)) {
866 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
869 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
872 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
874 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
875 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
876 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
879 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
881 mdio_write(ioaddr, 0x1f, 0x0000);
882 mdio_write(ioaddr, 0x0e, 0x0000);
885 tp->phy_auto_nego_reg = auto_nego;
886 tp->phy_1000_ctrl_reg = giga_ctrl;
888 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
889 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
890 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
894 static int rtl8169_set_speed(struct net_device *dev,
895 u8 autoneg, u16 speed, u8 duplex)
897 struct rtl8169_private *tp = netdev_priv(dev);
900 ret = tp->set_speed(dev, autoneg, speed, duplex);
902 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
903 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
908 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
910 struct rtl8169_private *tp = netdev_priv(dev);
914 spin_lock_irqsave(&tp->lock, flags);
915 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
916 spin_unlock_irqrestore(&tp->lock, flags);
921 static u32 rtl8169_get_rx_csum(struct net_device *dev)
923 struct rtl8169_private *tp = netdev_priv(dev);
925 return tp->cp_cmd & RxChkSum;
928 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
930 struct rtl8169_private *tp = netdev_priv(dev);
931 void __iomem *ioaddr = tp->mmio_addr;
934 spin_lock_irqsave(&tp->lock, flags);
937 tp->cp_cmd |= RxChkSum;
939 tp->cp_cmd &= ~RxChkSum;
941 RTL_W16(CPlusCmd, tp->cp_cmd);
944 spin_unlock_irqrestore(&tp->lock, flags);
949 #ifdef CONFIG_R8169_VLAN
951 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
954 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
955 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
958 static void rtl8169_vlan_rx_register(struct net_device *dev,
959 struct vlan_group *grp)
961 struct rtl8169_private *tp = netdev_priv(dev);
962 void __iomem *ioaddr = tp->mmio_addr;
965 spin_lock_irqsave(&tp->lock, flags);
968 tp->cp_cmd |= RxVlan;
970 tp->cp_cmd &= ~RxVlan;
971 RTL_W16(CPlusCmd, tp->cp_cmd);
973 spin_unlock_irqrestore(&tp->lock, flags);
976 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
979 u32 opts2 = le32_to_cpu(desc->opts2);
980 struct vlan_group *vlgrp = tp->vlgrp;
983 if (vlgrp && (opts2 & RxVlanTag)) {
984 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
992 #else /* !CONFIG_R8169_VLAN */
994 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1000 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1001 struct sk_buff *skb)
1008 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1010 struct rtl8169_private *tp = netdev_priv(dev);
1011 void __iomem *ioaddr = tp->mmio_addr;
1015 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1016 cmd->port = PORT_FIBRE;
1017 cmd->transceiver = XCVR_INTERNAL;
1019 status = RTL_R32(TBICSR);
1020 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1021 cmd->autoneg = !!(status & TBINwEnable);
1023 cmd->speed = SPEED_1000;
1024 cmd->duplex = DUPLEX_FULL; /* Always set */
1029 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1031 struct rtl8169_private *tp = netdev_priv(dev);
1033 return mii_ethtool_gset(&tp->mii, cmd);
1036 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1038 struct rtl8169_private *tp = netdev_priv(dev);
1039 unsigned long flags;
1042 spin_lock_irqsave(&tp->lock, flags);
1044 rc = tp->get_settings(dev, cmd);
1046 spin_unlock_irqrestore(&tp->lock, flags);
1050 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1053 struct rtl8169_private *tp = netdev_priv(dev);
1054 unsigned long flags;
1056 if (regs->len > R8169_REGS_SIZE)
1057 regs->len = R8169_REGS_SIZE;
1059 spin_lock_irqsave(&tp->lock, flags);
1060 memcpy_fromio(p, tp->mmio_addr, regs->len);
1061 spin_unlock_irqrestore(&tp->lock, flags);
1064 static u32 rtl8169_get_msglevel(struct net_device *dev)
1066 struct rtl8169_private *tp = netdev_priv(dev);
1068 return tp->msg_enable;
1071 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1073 struct rtl8169_private *tp = netdev_priv(dev);
1075 tp->msg_enable = value;
1078 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1085 "tx_single_collisions",
1086 "tx_multi_collisions",
1094 struct rtl8169_counters {
1100 __le16 align_errors;
1101 __le32 tx_one_collision;
1102 __le32 tx_multi_collision;
1104 __le64 rx_broadcast;
1105 __le32 rx_multicast;
1110 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1114 return ARRAY_SIZE(rtl8169_gstrings);
1120 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1121 struct ethtool_stats *stats, u64 *data)
1123 struct rtl8169_private *tp = netdev_priv(dev);
1124 void __iomem *ioaddr = tp->mmio_addr;
1125 struct rtl8169_counters *counters;
1131 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1135 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1136 cmd = (u64)paddr & DMA_32BIT_MASK;
1137 RTL_W32(CounterAddrLow, cmd);
1138 RTL_W32(CounterAddrLow, cmd | CounterDump);
1140 while (RTL_R32(CounterAddrLow) & CounterDump) {
1141 if (msleep_interruptible(1))
1145 RTL_W32(CounterAddrLow, 0);
1146 RTL_W32(CounterAddrHigh, 0);
1148 data[0] = le64_to_cpu(counters->tx_packets);
1149 data[1] = le64_to_cpu(counters->rx_packets);
1150 data[2] = le64_to_cpu(counters->tx_errors);
1151 data[3] = le32_to_cpu(counters->rx_errors);
1152 data[4] = le16_to_cpu(counters->rx_missed);
1153 data[5] = le16_to_cpu(counters->align_errors);
1154 data[6] = le32_to_cpu(counters->tx_one_collision);
1155 data[7] = le32_to_cpu(counters->tx_multi_collision);
1156 data[8] = le64_to_cpu(counters->rx_unicast);
1157 data[9] = le64_to_cpu(counters->rx_broadcast);
1158 data[10] = le32_to_cpu(counters->rx_multicast);
1159 data[11] = le16_to_cpu(counters->tx_aborted);
1160 data[12] = le16_to_cpu(counters->tx_underun);
1162 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1165 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1169 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1174 static const struct ethtool_ops rtl8169_ethtool_ops = {
1175 .get_drvinfo = rtl8169_get_drvinfo,
1176 .get_regs_len = rtl8169_get_regs_len,
1177 .get_link = ethtool_op_get_link,
1178 .get_settings = rtl8169_get_settings,
1179 .set_settings = rtl8169_set_settings,
1180 .get_msglevel = rtl8169_get_msglevel,
1181 .set_msglevel = rtl8169_set_msglevel,
1182 .get_rx_csum = rtl8169_get_rx_csum,
1183 .set_rx_csum = rtl8169_set_rx_csum,
1184 .set_tx_csum = ethtool_op_set_tx_csum,
1185 .set_sg = ethtool_op_set_sg,
1186 .set_tso = ethtool_op_set_tso,
1187 .get_regs = rtl8169_get_regs,
1188 .get_wol = rtl8169_get_wol,
1189 .set_wol = rtl8169_set_wol,
1190 .get_strings = rtl8169_get_strings,
1191 .get_sset_count = rtl8169_get_sset_count,
1192 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1195 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1196 int bitnum, int bitval)
1200 val = mdio_read(ioaddr, reg);
1201 val = (bitval == 1) ?
1202 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1203 mdio_write(ioaddr, reg, val & 0xffff);
1206 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1207 void __iomem *ioaddr)
1210 * The driver currently handles the 8168Bf and the 8168Be identically
1211 * but they can be identified more specifically through the test below
1214 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1216 * Same thing for the 8101Eb and the 8101Ec:
1218 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1226 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1227 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1228 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1229 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1230 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1231 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1232 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1235 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1236 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1237 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1238 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1241 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1242 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1243 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1244 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1245 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1246 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1247 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1248 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1249 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1250 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1251 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1252 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1253 /* FIXME: where did these entries come from ? -- FR */
1254 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1255 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1258 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1259 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1260 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1261 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1262 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1263 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1265 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1269 reg = RTL_R32(TxConfig);
1270 while ((reg & p->mask) != p->val)
1272 tp->mac_version = p->mac_version;
1274 if (p->mask == 0x00000000) {
1275 struct pci_dev *pdev = tp->pci_dev;
1277 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1281 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1283 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1291 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1294 mdio_write(ioaddr, regs->reg, regs->val);
1299 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1302 u16 regs[5]; /* Beware of bit-sign propagation */
1303 } phy_magic[5] = { {
1304 { 0x0000, //w 4 15 12 0
1305 0x00a1, //w 3 15 0 00a1
1306 0x0008, //w 2 15 0 0008
1307 0x1020, //w 1 15 0 1020
1308 0x1000 } },{ //w 0 15 0 1000
1309 { 0x7000, //w 4 15 12 7
1310 0xff41, //w 3 15 0 ff41
1311 0xde60, //w 2 15 0 de60
1312 0x0140, //w 1 15 0 0140
1313 0x0077 } },{ //w 0 15 0 0077
1314 { 0xa000, //w 4 15 12 a
1315 0xdf01, //w 3 15 0 df01
1316 0xdf20, //w 2 15 0 df20
1317 0xff95, //w 1 15 0 ff95
1318 0xfa00 } },{ //w 0 15 0 fa00
1319 { 0xb000, //w 4 15 12 b
1320 0xff41, //w 3 15 0 ff41
1321 0xde20, //w 2 15 0 de20
1322 0x0140, //w 1 15 0 0140
1323 0x00bb } },{ //w 0 15 0 00bb
1324 { 0xf000, //w 4 15 12 f
1325 0xdf01, //w 3 15 0 df01
1326 0xdf20, //w 2 15 0 df20
1327 0xff95, //w 1 15 0 ff95
1328 0xbf00 } //w 0 15 0 bf00
1333 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1334 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1335 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1336 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1338 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1341 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1342 mdio_write(ioaddr, pos, val);
1344 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1345 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1346 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1348 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1351 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1353 struct phy_reg phy_reg_init[] = {
1359 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1362 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1364 struct phy_reg phy_reg_init[] = {
1369 mdio_write(ioaddr, 0x1f, 0x0001);
1370 mdio_patch(ioaddr, 0x16, 1 << 0);
1372 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1375 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1377 struct phy_reg phy_reg_init[] = {
1383 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1386 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1388 struct phy_reg phy_reg_init[] = {
1396 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1399 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1401 struct phy_reg phy_reg_init[] = {
1407 mdio_write(ioaddr, 0x1f, 0x0000);
1408 mdio_patch(ioaddr, 0x14, 1 << 5);
1409 mdio_patch(ioaddr, 0x0d, 1 << 5);
1411 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1414 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1416 struct phy_reg phy_reg_init[] = {
1436 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1438 mdio_patch(ioaddr, 0x14, 1 << 5);
1439 mdio_patch(ioaddr, 0x0d, 1 << 5);
1440 mdio_write(ioaddr, 0x1f, 0x0000);
1443 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1445 struct phy_reg phy_reg_init[] = {
1463 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1465 mdio_patch(ioaddr, 0x16, 1 << 0);
1466 mdio_patch(ioaddr, 0x14, 1 << 5);
1467 mdio_patch(ioaddr, 0x0d, 1 << 5);
1468 mdio_write(ioaddr, 0x1f, 0x0000);
1471 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1473 struct phy_reg phy_reg_init[] = {
1485 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1487 mdio_patch(ioaddr, 0x16, 1 << 0);
1488 mdio_patch(ioaddr, 0x14, 1 << 5);
1489 mdio_patch(ioaddr, 0x0d, 1 << 5);
1490 mdio_write(ioaddr, 0x1f, 0x0000);
1493 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1495 rtl8168c_3_hw_phy_config(ioaddr);
1498 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1500 struct phy_reg phy_reg_init[] = {
1507 mdio_write(ioaddr, 0x1f, 0x0000);
1508 mdio_patch(ioaddr, 0x11, 1 << 12);
1509 mdio_patch(ioaddr, 0x19, 1 << 13);
1511 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1514 static void rtl_hw_phy_config(struct net_device *dev)
1516 struct rtl8169_private *tp = netdev_priv(dev);
1517 void __iomem *ioaddr = tp->mmio_addr;
1519 rtl8169_print_mac_version(tp);
1521 switch (tp->mac_version) {
1522 case RTL_GIGA_MAC_VER_01:
1524 case RTL_GIGA_MAC_VER_02:
1525 case RTL_GIGA_MAC_VER_03:
1526 rtl8169s_hw_phy_config(ioaddr);
1528 case RTL_GIGA_MAC_VER_04:
1529 rtl8169sb_hw_phy_config(ioaddr);
1531 case RTL_GIGA_MAC_VER_07:
1532 case RTL_GIGA_MAC_VER_08:
1533 case RTL_GIGA_MAC_VER_09:
1534 rtl8102e_hw_phy_config(ioaddr);
1536 case RTL_GIGA_MAC_VER_11:
1537 rtl8168bb_hw_phy_config(ioaddr);
1539 case RTL_GIGA_MAC_VER_12:
1540 rtl8168bef_hw_phy_config(ioaddr);
1542 case RTL_GIGA_MAC_VER_17:
1543 rtl8168bef_hw_phy_config(ioaddr);
1545 case RTL_GIGA_MAC_VER_18:
1546 rtl8168cp_1_hw_phy_config(ioaddr);
1548 case RTL_GIGA_MAC_VER_19:
1549 rtl8168c_1_hw_phy_config(ioaddr);
1551 case RTL_GIGA_MAC_VER_20:
1552 rtl8168c_2_hw_phy_config(ioaddr);
1554 case RTL_GIGA_MAC_VER_21:
1555 rtl8168c_3_hw_phy_config(ioaddr);
1557 case RTL_GIGA_MAC_VER_22:
1558 rtl8168c_4_hw_phy_config(ioaddr);
1560 case RTL_GIGA_MAC_VER_23:
1561 rtl8168cp_2_hw_phy_config(ioaddr);
1569 static void rtl8169_phy_timer(unsigned long __opaque)
1571 struct net_device *dev = (struct net_device *)__opaque;
1572 struct rtl8169_private *tp = netdev_priv(dev);
1573 struct timer_list *timer = &tp->timer;
1574 void __iomem *ioaddr = tp->mmio_addr;
1575 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1577 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1579 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1582 spin_lock_irq(&tp->lock);
1584 if (tp->phy_reset_pending(ioaddr)) {
1586 * A busy loop could burn quite a few cycles on nowadays CPU.
1587 * Let's delay the execution of the timer for a few ticks.
1593 if (tp->link_ok(ioaddr))
1596 if (netif_msg_link(tp))
1597 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1599 tp->phy_reset_enable(ioaddr);
1602 mod_timer(timer, jiffies + timeout);
1604 spin_unlock_irq(&tp->lock);
1607 static inline void rtl8169_delete_timer(struct net_device *dev)
1609 struct rtl8169_private *tp = netdev_priv(dev);
1610 struct timer_list *timer = &tp->timer;
1612 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1615 del_timer_sync(timer);
1618 static inline void rtl8169_request_timer(struct net_device *dev)
1620 struct rtl8169_private *tp = netdev_priv(dev);
1621 struct timer_list *timer = &tp->timer;
1623 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1626 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1629 #ifdef CONFIG_NET_POLL_CONTROLLER
1631 * Polling 'interrupt' - used by things like netconsole to send skbs
1632 * without having to re-enable interrupts. It's not called while
1633 * the interrupt routine is executing.
1635 static void rtl8169_netpoll(struct net_device *dev)
1637 struct rtl8169_private *tp = netdev_priv(dev);
1638 struct pci_dev *pdev = tp->pci_dev;
1640 disable_irq(pdev->irq);
1641 rtl8169_interrupt(pdev->irq, dev);
1642 enable_irq(pdev->irq);
1646 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1647 void __iomem *ioaddr)
1650 pci_release_regions(pdev);
1651 pci_disable_device(pdev);
1655 static void rtl8169_phy_reset(struct net_device *dev,
1656 struct rtl8169_private *tp)
1658 void __iomem *ioaddr = tp->mmio_addr;
1661 tp->phy_reset_enable(ioaddr);
1662 for (i = 0; i < 100; i++) {
1663 if (!tp->phy_reset_pending(ioaddr))
1667 if (netif_msg_link(tp))
1668 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1671 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1673 void __iomem *ioaddr = tp->mmio_addr;
1675 rtl_hw_phy_config(dev);
1677 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1678 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1682 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1684 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1685 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1687 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1688 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1690 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1691 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1694 rtl8169_phy_reset(dev, tp);
1697 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1698 * only 8101. Don't panic.
1700 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1702 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1703 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1706 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1708 void __iomem *ioaddr = tp->mmio_addr;
1712 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1713 high = addr[4] | (addr[5] << 8);
1715 spin_lock_irq(&tp->lock);
1717 RTL_W8(Cfg9346, Cfg9346_Unlock);
1719 RTL_W32(MAC4, high);
1720 RTL_W8(Cfg9346, Cfg9346_Lock);
1722 spin_unlock_irq(&tp->lock);
1725 static int rtl_set_mac_address(struct net_device *dev, void *p)
1727 struct rtl8169_private *tp = netdev_priv(dev);
1728 struct sockaddr *addr = p;
1730 if (!is_valid_ether_addr(addr->sa_data))
1731 return -EADDRNOTAVAIL;
1733 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1735 rtl_rar_set(tp, dev->dev_addr);
1740 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1742 struct rtl8169_private *tp = netdev_priv(dev);
1743 struct mii_ioctl_data *data = if_mii(ifr);
1745 if (!netif_running(dev))
1750 data->phy_id = 32; /* Internal PHY */
1754 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1758 if (!capable(CAP_NET_ADMIN))
1760 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1766 static const struct rtl_cfg_info {
1767 void (*hw_start)(struct net_device *);
1768 unsigned int region;
1773 } rtl_cfg_infos [] = {
1775 .hw_start = rtl_hw_start_8169,
1778 .intr_event = SYSErr | LinkChg | RxOverflow |
1779 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1780 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1781 .features = RTL_FEATURE_GMII
1784 .hw_start = rtl_hw_start_8168,
1787 .intr_event = SYSErr | LinkChg | RxOverflow |
1788 TxErr | TxOK | RxOK | RxErr,
1789 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1790 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1793 .hw_start = rtl_hw_start_8101,
1796 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1797 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1798 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1799 .features = RTL_FEATURE_MSI
1803 /* Cfg9346_Unlock assumed. */
1804 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1805 const struct rtl_cfg_info *cfg)
1810 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1811 if (cfg->features & RTL_FEATURE_MSI) {
1812 if (pci_enable_msi(pdev)) {
1813 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1816 msi = RTL_FEATURE_MSI;
1819 RTL_W8(Config2, cfg2);
1823 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1825 if (tp->features & RTL_FEATURE_MSI) {
1826 pci_disable_msi(pdev);
1827 tp->features &= ~RTL_FEATURE_MSI;
1831 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1833 int ret, count = 100;
1837 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1843 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1846 } while (!(status & PCI_VPD_ADDR_F) && --count);
1848 if (!(status & PCI_VPD_ADDR_F))
1851 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1855 *val = cpu_to_le32(value);
1860 static void rtl_init_mac_address(struct rtl8169_private *tp,
1861 void __iomem *ioaddr)
1863 struct pci_dev *pdev = tp->pci_dev;
1867 DECLARE_MAC_BUF(buf);
1869 cfg1 = RTL_R8(Config1);
1870 if (!(cfg1 & VPD)) {
1871 dprintk("VPD access not enabled, enabling\n");
1872 RTL_W8(Cfg9346, Cfg9346_Unlock);
1873 RTL_W8(Config1, cfg1 | VPD);
1874 RTL_W8(Cfg9346, Cfg9346_Lock);
1877 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1881 /* MAC address is stored in EEPROM at offset 0x0e
1882 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1883 * address as defined in the PCI 2.2 Specifications, but the VPD data
1884 * is always consecutive 4-byte data starting from the VPD address
1887 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1888 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1889 dprintk("Reading MAC address from EEPROM failed\n");
1893 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1895 /* Write MAC address */
1896 rtl_rar_set(tp, mac);
1899 static int __devinit
1900 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1902 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1903 const unsigned int region = cfg->region;
1904 struct rtl8169_private *tp;
1905 struct mii_if_info *mii;
1906 struct net_device *dev;
1907 void __iomem *ioaddr;
1911 if (netif_msg_drv(&debug)) {
1912 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1913 MODULENAME, RTL8169_VERSION);
1916 dev = alloc_etherdev(sizeof (*tp));
1918 if (netif_msg_drv(&debug))
1919 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1924 SET_NETDEV_DEV(dev, &pdev->dev);
1925 tp = netdev_priv(dev);
1928 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1932 mii->mdio_read = rtl_mdio_read;
1933 mii->mdio_write = rtl_mdio_write;
1934 mii->phy_id_mask = 0x1f;
1935 mii->reg_num_mask = 0x1f;
1936 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1938 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1939 rc = pci_enable_device(pdev);
1941 if (netif_msg_probe(tp))
1942 dev_err(&pdev->dev, "enable failure\n");
1943 goto err_out_free_dev_1;
1946 rc = pci_set_mwi(pdev);
1948 goto err_out_disable_2;
1950 /* make sure PCI base addr 1 is MMIO */
1951 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1952 if (netif_msg_probe(tp)) {
1954 "region #%d not an MMIO resource, aborting\n",
1961 /* check for weird/broken PCI region reporting */
1962 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1963 if (netif_msg_probe(tp)) {
1965 "Invalid PCI region size(s), aborting\n");
1971 rc = pci_request_regions(pdev, MODULENAME);
1973 if (netif_msg_probe(tp))
1974 dev_err(&pdev->dev, "could not request regions.\n");
1978 tp->cp_cmd = PCIMulRW | RxChkSum;
1980 if ((sizeof(dma_addr_t) > 4) &&
1981 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1982 tp->cp_cmd |= PCIDAC;
1983 dev->features |= NETIF_F_HIGHDMA;
1985 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1987 if (netif_msg_probe(tp)) {
1989 "DMA configuration failed.\n");
1991 goto err_out_free_res_4;
1995 pci_set_master(pdev);
1997 /* ioremap MMIO region */
1998 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2000 if (netif_msg_probe(tp))
2001 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2003 goto err_out_free_res_4;
2006 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2007 if (!tp->pcie_cap && netif_msg_probe(tp))
2008 dev_info(&pdev->dev, "no PCI Express capability\n");
2010 /* Unneeded ? Don't mess with Mrs. Murphy. */
2011 rtl8169_irq_mask_and_ack(ioaddr);
2013 /* Soft reset the chip. */
2014 RTL_W8(ChipCmd, CmdReset);
2016 /* Check that the chip has finished the reset. */
2017 for (i = 0; i < 100; i++) {
2018 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2020 msleep_interruptible(1);
2023 /* Identify chip attached to board */
2024 rtl8169_get_mac_version(tp, ioaddr);
2026 rtl8169_print_mac_version(tp);
2028 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2029 if (tp->mac_version == rtl_chip_info[i].mac_version)
2032 if (i == ARRAY_SIZE(rtl_chip_info)) {
2033 /* Unknown chip: assume array element #0, original RTL-8169 */
2034 if (netif_msg_probe(tp)) {
2035 dev_printk(KERN_DEBUG, &pdev->dev,
2036 "unknown chip version, assuming %s\n",
2037 rtl_chip_info[0].name);
2043 RTL_W8(Cfg9346, Cfg9346_Unlock);
2044 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2045 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2046 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2047 tp->features |= RTL_FEATURE_WOL;
2048 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2049 tp->features |= RTL_FEATURE_WOL;
2050 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2051 RTL_W8(Cfg9346, Cfg9346_Lock);
2053 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2054 (RTL_R8(PHYstatus) & TBI_Enable)) {
2055 tp->set_speed = rtl8169_set_speed_tbi;
2056 tp->get_settings = rtl8169_gset_tbi;
2057 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2058 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2059 tp->link_ok = rtl8169_tbi_link_ok;
2061 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2063 tp->set_speed = rtl8169_set_speed_xmii;
2064 tp->get_settings = rtl8169_gset_xmii;
2065 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2066 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2067 tp->link_ok = rtl8169_xmii_link_ok;
2069 dev->do_ioctl = rtl8169_ioctl;
2072 spin_lock_init(&tp->lock);
2074 rtl_init_mac_address(tp, ioaddr);
2076 /* Get MAC address */
2077 for (i = 0; i < MAC_ADDR_LEN; i++)
2078 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2079 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2081 dev->open = rtl8169_open;
2082 dev->hard_start_xmit = rtl8169_start_xmit;
2083 dev->get_stats = rtl8169_get_stats;
2084 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2085 dev->stop = rtl8169_close;
2086 dev->tx_timeout = rtl8169_tx_timeout;
2087 dev->set_multicast_list = rtl_set_rx_mode;
2088 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2089 dev->irq = pdev->irq;
2090 dev->base_addr = (unsigned long) ioaddr;
2091 dev->change_mtu = rtl8169_change_mtu;
2092 dev->set_mac_address = rtl_set_mac_address;
2094 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2096 #ifdef CONFIG_R8169_VLAN
2097 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2098 dev->vlan_rx_register = rtl8169_vlan_rx_register;
2101 #ifdef CONFIG_NET_POLL_CONTROLLER
2102 dev->poll_controller = rtl8169_netpoll;
2105 tp->intr_mask = 0xffff;
2106 tp->mmio_addr = ioaddr;
2107 tp->align = cfg->align;
2108 tp->hw_start = cfg->hw_start;
2109 tp->intr_event = cfg->intr_event;
2110 tp->napi_event = cfg->napi_event;
2112 init_timer(&tp->timer);
2113 tp->timer.data = (unsigned long) dev;
2114 tp->timer.function = rtl8169_phy_timer;
2116 rc = register_netdev(dev);
2120 pci_set_drvdata(pdev, dev);
2122 if (netif_msg_probe(tp)) {
2123 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2125 printk(KERN_INFO "%s: %s at 0x%lx, "
2126 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2127 "XID %08x IRQ %d\n",
2129 rtl_chip_info[tp->chipset].name,
2131 dev->dev_addr[0], dev->dev_addr[1],
2132 dev->dev_addr[2], dev->dev_addr[3],
2133 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2136 rtl8169_init_phy(dev, tp);
2137 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2143 rtl_disable_msi(pdev, tp);
2146 pci_release_regions(pdev);
2148 pci_clear_mwi(pdev);
2150 pci_disable_device(pdev);
2156 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2158 struct net_device *dev = pci_get_drvdata(pdev);
2159 struct rtl8169_private *tp = netdev_priv(dev);
2161 flush_scheduled_work();
2163 unregister_netdev(dev);
2164 rtl_disable_msi(pdev, tp);
2165 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2166 pci_set_drvdata(pdev, NULL);
2169 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2170 struct net_device *dev)
2172 unsigned int mtu = dev->mtu;
2174 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2177 static int rtl8169_open(struct net_device *dev)
2179 struct rtl8169_private *tp = netdev_priv(dev);
2180 struct pci_dev *pdev = tp->pci_dev;
2181 int retval = -ENOMEM;
2184 rtl8169_set_rxbufsize(tp, dev);
2187 * Rx and Tx desscriptors needs 256 bytes alignment.
2188 * pci_alloc_consistent provides more.
2190 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2192 if (!tp->TxDescArray)
2195 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2197 if (!tp->RxDescArray)
2200 retval = rtl8169_init_ring(dev);
2204 INIT_DELAYED_WORK(&tp->task, NULL);
2208 retval = request_irq(dev->irq, rtl8169_interrupt,
2209 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2212 goto err_release_ring_2;
2214 napi_enable(&tp->napi);
2218 rtl8169_request_timer(dev);
2220 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2225 rtl8169_rx_clear(tp);
2227 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2230 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2235 static void rtl8169_hw_reset(void __iomem *ioaddr)
2237 /* Disable interrupts */
2238 rtl8169_irq_mask_and_ack(ioaddr);
2240 /* Reset the chipset */
2241 RTL_W8(ChipCmd, CmdReset);
2247 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2249 void __iomem *ioaddr = tp->mmio_addr;
2250 u32 cfg = rtl8169_rx_config;
2252 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2253 RTL_W32(RxConfig, cfg);
2255 /* Set DMA burst size and Interframe Gap Time */
2256 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2257 (InterFrameGap << TxInterFrameGapShift));
2260 static void rtl_hw_start(struct net_device *dev)
2262 struct rtl8169_private *tp = netdev_priv(dev);
2263 void __iomem *ioaddr = tp->mmio_addr;
2266 /* Soft reset the chip. */
2267 RTL_W8(ChipCmd, CmdReset);
2269 /* Check that the chip has finished the reset. */
2270 for (i = 0; i < 100; i++) {
2271 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2273 msleep_interruptible(1);
2278 netif_start_queue(dev);
2282 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2283 void __iomem *ioaddr)
2286 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2287 * register to be written before TxDescAddrLow to work.
2288 * Switching from MMIO to I/O access fixes the issue as well.
2290 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2291 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2292 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2293 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2296 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2300 cmd = RTL_R16(CPlusCmd);
2301 RTL_W16(CPlusCmd, cmd);
2305 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2307 /* Low hurts. Let's disable the filtering. */
2308 RTL_W16(RxMaxSize, 16383);
2311 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2318 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2319 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2320 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2321 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2326 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2327 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2328 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2329 RTL_W32(0x7c, p->val);
2335 static void rtl_hw_start_8169(struct net_device *dev)
2337 struct rtl8169_private *tp = netdev_priv(dev);
2338 void __iomem *ioaddr = tp->mmio_addr;
2339 struct pci_dev *pdev = tp->pci_dev;
2341 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2342 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2343 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2346 RTL_W8(Cfg9346, Cfg9346_Unlock);
2347 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2348 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2349 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2350 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2351 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2353 RTL_W8(EarlyTxThres, EarlyTxThld);
2355 rtl_set_rx_max_size(ioaddr);
2357 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2358 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2359 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2360 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2361 rtl_set_rx_tx_config_registers(tp);
2363 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2365 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2366 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2367 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2368 "Bit-3 and bit-14 MUST be 1\n");
2369 tp->cp_cmd |= (1 << 14);
2372 RTL_W16(CPlusCmd, tp->cp_cmd);
2374 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2377 * Undocumented corner. Supposedly:
2378 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2380 RTL_W16(IntrMitigate, 0x0000);
2382 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2384 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2385 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2386 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2387 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2388 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2389 rtl_set_rx_tx_config_registers(tp);
2392 RTL_W8(Cfg9346, Cfg9346_Lock);
2394 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2397 RTL_W32(RxMissed, 0);
2399 rtl_set_rx_mode(dev);
2401 /* no early-rx interrupts */
2402 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2404 /* Enable all known interrupts by setting the interrupt mask. */
2405 RTL_W16(IntrMask, tp->intr_event);
2408 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2410 struct net_device *dev = pci_get_drvdata(pdev);
2411 struct rtl8169_private *tp = netdev_priv(dev);
2412 int cap = tp->pcie_cap;
2417 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2418 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2419 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2423 static void rtl_csi_access_enable(void __iomem *ioaddr)
2427 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2428 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2432 unsigned int offset;
2437 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2442 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2443 rtl_ephy_write(ioaddr, e->offset, w);
2448 static void rtl_disable_clock_request(struct pci_dev *pdev)
2450 struct net_device *dev = pci_get_drvdata(pdev);
2451 struct rtl8169_private *tp = netdev_priv(dev);
2452 int cap = tp->pcie_cap;
2457 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2458 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2459 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2463 #define R8168_CPCMD_QUIRK_MASK (\
2474 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2476 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2478 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2480 rtl_tx_performance_tweak(pdev,
2481 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2484 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2486 rtl_hw_start_8168bb(ioaddr, pdev);
2488 RTL_W8(EarlyTxThres, EarlyTxThld);
2490 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2493 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2495 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2497 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2499 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2501 rtl_disable_clock_request(pdev);
2503 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2506 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2508 static struct ephy_info e_info_8168cp[] = {
2509 { 0x01, 0, 0x0001 },
2510 { 0x02, 0x0800, 0x1000 },
2511 { 0x03, 0, 0x0042 },
2512 { 0x06, 0x0080, 0x0000 },
2516 rtl_csi_access_enable(ioaddr);
2518 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2520 __rtl_hw_start_8168cp(ioaddr, pdev);
2523 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2525 rtl_csi_access_enable(ioaddr);
2527 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2529 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2531 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2534 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2536 static struct ephy_info e_info_8168c_1[] = {
2537 { 0x02, 0x0800, 0x1000 },
2538 { 0x03, 0, 0x0002 },
2539 { 0x06, 0x0080, 0x0000 }
2542 rtl_csi_access_enable(ioaddr);
2544 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2546 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2548 __rtl_hw_start_8168cp(ioaddr, pdev);
2551 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2553 static struct ephy_info e_info_8168c_2[] = {
2554 { 0x01, 0, 0x0001 },
2555 { 0x03, 0x0400, 0x0220 }
2558 rtl_csi_access_enable(ioaddr);
2560 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2562 __rtl_hw_start_8168cp(ioaddr, pdev);
2565 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2567 rtl_hw_start_8168c_2(ioaddr, pdev);
2570 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2572 rtl_csi_access_enable(ioaddr);
2574 __rtl_hw_start_8168cp(ioaddr, pdev);
2577 static void rtl_hw_start_8168(struct net_device *dev)
2579 struct rtl8169_private *tp = netdev_priv(dev);
2580 void __iomem *ioaddr = tp->mmio_addr;
2581 struct pci_dev *pdev = tp->pci_dev;
2583 RTL_W8(Cfg9346, Cfg9346_Unlock);
2585 RTL_W8(EarlyTxThres, EarlyTxThld);
2587 rtl_set_rx_max_size(ioaddr);
2589 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2591 RTL_W16(CPlusCmd, tp->cp_cmd);
2593 RTL_W16(IntrMitigate, 0x5151);
2595 /* Work around for RxFIFO overflow. */
2596 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2597 tp->intr_event |= RxFIFOOver | PCSTimeout;
2598 tp->intr_event &= ~RxOverflow;
2601 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2603 rtl_set_rx_mode(dev);
2605 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2606 (InterFrameGap << TxInterFrameGapShift));
2610 switch (tp->mac_version) {
2611 case RTL_GIGA_MAC_VER_11:
2612 rtl_hw_start_8168bb(ioaddr, pdev);
2615 case RTL_GIGA_MAC_VER_12:
2616 case RTL_GIGA_MAC_VER_17:
2617 rtl_hw_start_8168bef(ioaddr, pdev);
2620 case RTL_GIGA_MAC_VER_18:
2621 rtl_hw_start_8168cp_1(ioaddr, pdev);
2624 case RTL_GIGA_MAC_VER_19:
2625 rtl_hw_start_8168c_1(ioaddr, pdev);
2628 case RTL_GIGA_MAC_VER_20:
2629 rtl_hw_start_8168c_2(ioaddr, pdev);
2632 case RTL_GIGA_MAC_VER_21:
2633 rtl_hw_start_8168c_3(ioaddr, pdev);
2636 case RTL_GIGA_MAC_VER_22:
2637 rtl_hw_start_8168c_4(ioaddr, pdev);
2640 case RTL_GIGA_MAC_VER_23:
2641 rtl_hw_start_8168cp_2(ioaddr, pdev);
2645 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2646 dev->name, tp->mac_version);
2650 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2652 RTL_W8(Cfg9346, Cfg9346_Lock);
2654 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2656 RTL_W16(IntrMask, tp->intr_event);
2659 #define R810X_CPCMD_QUIRK_MASK (\
2671 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2673 static struct ephy_info e_info_8102e_1[] = {
2674 { 0x01, 0, 0x6e65 },
2675 { 0x02, 0, 0x091f },
2676 { 0x03, 0, 0xc2f9 },
2677 { 0x06, 0, 0xafb5 },
2678 { 0x07, 0, 0x0e00 },
2679 { 0x19, 0, 0xec80 },
2680 { 0x01, 0, 0x2e65 },
2685 rtl_csi_access_enable(ioaddr);
2687 RTL_W8(DBG_REG, FIX_NAK_1);
2689 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2692 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2693 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2695 cfg1 = RTL_R8(Config1);
2696 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2697 RTL_W8(Config1, cfg1 & ~LEDS0);
2699 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2701 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2704 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2706 rtl_csi_access_enable(ioaddr);
2708 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2710 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2711 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2713 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2716 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2718 rtl_hw_start_8102e_2(ioaddr, pdev);
2720 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2723 static void rtl_hw_start_8101(struct net_device *dev)
2725 struct rtl8169_private *tp = netdev_priv(dev);
2726 void __iomem *ioaddr = tp->mmio_addr;
2727 struct pci_dev *pdev = tp->pci_dev;
2729 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2730 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2731 int cap = tp->pcie_cap;
2734 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2735 PCI_EXP_DEVCTL_NOSNOOP_EN);
2739 switch (tp->mac_version) {
2740 case RTL_GIGA_MAC_VER_07:
2741 rtl_hw_start_8102e_1(ioaddr, pdev);
2744 case RTL_GIGA_MAC_VER_08:
2745 rtl_hw_start_8102e_3(ioaddr, pdev);
2748 case RTL_GIGA_MAC_VER_09:
2749 rtl_hw_start_8102e_2(ioaddr, pdev);
2753 RTL_W8(Cfg9346, Cfg9346_Unlock);
2755 RTL_W8(EarlyTxThres, EarlyTxThld);
2757 rtl_set_rx_max_size(ioaddr);
2759 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2761 RTL_W16(CPlusCmd, tp->cp_cmd);
2763 RTL_W16(IntrMitigate, 0x0000);
2765 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2767 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2768 rtl_set_rx_tx_config_registers(tp);
2770 RTL_W8(Cfg9346, Cfg9346_Lock);
2774 rtl_set_rx_mode(dev);
2776 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2778 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2780 RTL_W16(IntrMask, tp->intr_event);
2783 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2785 struct rtl8169_private *tp = netdev_priv(dev);
2788 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2793 if (!netif_running(dev))
2798 rtl8169_set_rxbufsize(tp, dev);
2800 ret = rtl8169_init_ring(dev);
2804 napi_enable(&tp->napi);
2808 rtl8169_request_timer(dev);
2814 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2816 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2817 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2820 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2821 struct sk_buff **sk_buff, struct RxDesc *desc)
2823 struct pci_dev *pdev = tp->pci_dev;
2825 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2826 PCI_DMA_FROMDEVICE);
2827 dev_kfree_skb(*sk_buff);
2829 rtl8169_make_unusable_by_asic(desc);
2832 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2834 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2836 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2839 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2842 desc->addr = cpu_to_le64(mapping);
2844 rtl8169_mark_to_asic(desc, rx_buf_sz);
2847 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2848 struct net_device *dev,
2849 struct RxDesc *desc, int rx_buf_sz,
2852 struct sk_buff *skb;
2856 pad = align ? align : NET_IP_ALIGN;
2858 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2862 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2864 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2865 PCI_DMA_FROMDEVICE);
2867 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2872 rtl8169_make_unusable_by_asic(desc);
2876 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2880 for (i = 0; i < NUM_RX_DESC; i++) {
2881 if (tp->Rx_skbuff[i]) {
2882 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2883 tp->RxDescArray + i);
2888 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2893 for (cur = start; end - cur != 0; cur++) {
2894 struct sk_buff *skb;
2895 unsigned int i = cur % NUM_RX_DESC;
2897 WARN_ON((s32)(end - cur) < 0);
2899 if (tp->Rx_skbuff[i])
2902 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2903 tp->RxDescArray + i,
2904 tp->rx_buf_sz, tp->align);
2908 tp->Rx_skbuff[i] = skb;
2913 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2915 desc->opts1 |= cpu_to_le32(RingEnd);
2918 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2920 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2923 static int rtl8169_init_ring(struct net_device *dev)
2925 struct rtl8169_private *tp = netdev_priv(dev);
2927 rtl8169_init_ring_indexes(tp);
2929 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2930 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2932 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2935 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2940 rtl8169_rx_clear(tp);
2944 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2945 struct TxDesc *desc)
2947 unsigned int len = tx_skb->len;
2949 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2956 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2960 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2961 unsigned int entry = i % NUM_TX_DESC;
2962 struct ring_info *tx_skb = tp->tx_skb + entry;
2963 unsigned int len = tx_skb->len;
2966 struct sk_buff *skb = tx_skb->skb;
2968 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2969 tp->TxDescArray + entry);
2974 tp->dev->stats.tx_dropped++;
2977 tp->cur_tx = tp->dirty_tx = 0;
2980 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2982 struct rtl8169_private *tp = netdev_priv(dev);
2984 PREPARE_DELAYED_WORK(&tp->task, task);
2985 schedule_delayed_work(&tp->task, 4);
2988 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2990 struct rtl8169_private *tp = netdev_priv(dev);
2991 void __iomem *ioaddr = tp->mmio_addr;
2993 synchronize_irq(dev->irq);
2995 /* Wait for any pending NAPI task to complete */
2996 napi_disable(&tp->napi);
2998 rtl8169_irq_mask_and_ack(ioaddr);
3000 tp->intr_mask = 0xffff;
3001 RTL_W16(IntrMask, tp->intr_event);
3002 napi_enable(&tp->napi);
3005 static void rtl8169_reinit_task(struct work_struct *work)
3007 struct rtl8169_private *tp =
3008 container_of(work, struct rtl8169_private, task.work);
3009 struct net_device *dev = tp->dev;
3014 if (!netif_running(dev))
3017 rtl8169_wait_for_quiescence(dev);
3020 ret = rtl8169_open(dev);
3021 if (unlikely(ret < 0)) {
3022 if (net_ratelimit() && netif_msg_drv(tp)) {
3023 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3024 " Rescheduling.\n", dev->name, ret);
3026 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3033 static void rtl8169_reset_task(struct work_struct *work)
3035 struct rtl8169_private *tp =
3036 container_of(work, struct rtl8169_private, task.work);
3037 struct net_device *dev = tp->dev;
3041 if (!netif_running(dev))
3044 rtl8169_wait_for_quiescence(dev);
3046 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3047 rtl8169_tx_clear(tp);
3049 if (tp->dirty_rx == tp->cur_rx) {
3050 rtl8169_init_ring_indexes(tp);
3052 netif_wake_queue(dev);
3053 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3055 if (net_ratelimit() && netif_msg_intr(tp)) {
3056 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3059 rtl8169_schedule_work(dev, rtl8169_reset_task);
3066 static void rtl8169_tx_timeout(struct net_device *dev)
3068 struct rtl8169_private *tp = netdev_priv(dev);
3070 rtl8169_hw_reset(tp->mmio_addr);
3072 /* Let's wait a bit while any (async) irq lands on */
3073 rtl8169_schedule_work(dev, rtl8169_reset_task);
3076 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3079 struct skb_shared_info *info = skb_shinfo(skb);
3080 unsigned int cur_frag, entry;
3081 struct TxDesc * uninitialized_var(txd);
3084 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3085 skb_frag_t *frag = info->frags + cur_frag;
3090 entry = (entry + 1) % NUM_TX_DESC;
3092 txd = tp->TxDescArray + entry;
3094 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3095 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3097 /* anti gcc 2.95.3 bugware (sic) */
3098 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3100 txd->opts1 = cpu_to_le32(status);
3101 txd->addr = cpu_to_le64(mapping);
3103 tp->tx_skb[entry].len = len;
3107 tp->tx_skb[entry].skb = skb;
3108 txd->opts1 |= cpu_to_le32(LastFrag);
3114 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3116 if (dev->features & NETIF_F_TSO) {
3117 u32 mss = skb_shinfo(skb)->gso_size;
3120 return LargeSend | ((mss & MSSMask) << MSSShift);
3122 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3123 const struct iphdr *ip = ip_hdr(skb);
3125 if (ip->protocol == IPPROTO_TCP)
3126 return IPCS | TCPCS;
3127 else if (ip->protocol == IPPROTO_UDP)
3128 return IPCS | UDPCS;
3129 WARN_ON(1); /* we need a WARN() */
3134 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3136 struct rtl8169_private *tp = netdev_priv(dev);
3137 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3138 struct TxDesc *txd = tp->TxDescArray + entry;
3139 void __iomem *ioaddr = tp->mmio_addr;
3143 int ret = NETDEV_TX_OK;
3145 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3146 if (netif_msg_drv(tp)) {
3148 "%s: BUG! Tx Ring full when queue awake!\n",
3154 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3157 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3159 frags = rtl8169_xmit_frags(tp, skb, opts1);
3161 len = skb_headlen(skb);
3166 if (unlikely(len < ETH_ZLEN)) {
3167 if (skb_padto(skb, ETH_ZLEN))
3168 goto err_update_stats;
3172 opts1 |= FirstFrag | LastFrag;
3173 tp->tx_skb[entry].skb = skb;
3176 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3178 tp->tx_skb[entry].len = len;
3179 txd->addr = cpu_to_le64(mapping);
3180 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3184 /* anti gcc 2.95.3 bugware (sic) */
3185 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3186 txd->opts1 = cpu_to_le32(status);
3188 dev->trans_start = jiffies;
3190 tp->cur_tx += frags + 1;
3194 RTL_W8(TxPoll, NPQ); /* set polling bit */
3196 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3197 netif_stop_queue(dev);
3199 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3200 netif_wake_queue(dev);
3207 netif_stop_queue(dev);
3208 ret = NETDEV_TX_BUSY;
3210 dev->stats.tx_dropped++;
3214 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3216 struct rtl8169_private *tp = netdev_priv(dev);
3217 struct pci_dev *pdev = tp->pci_dev;
3218 void __iomem *ioaddr = tp->mmio_addr;
3219 u16 pci_status, pci_cmd;
3221 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3222 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3224 if (netif_msg_intr(tp)) {
3226 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3227 dev->name, pci_cmd, pci_status);
3231 * The recovery sequence below admits a very elaborated explanation:
3232 * - it seems to work;
3233 * - I did not see what else could be done;
3234 * - it makes iop3xx happy.
3236 * Feel free to adjust to your needs.
3238 if (pdev->broken_parity_status)
3239 pci_cmd &= ~PCI_COMMAND_PARITY;
3241 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3243 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3245 pci_write_config_word(pdev, PCI_STATUS,
3246 pci_status & (PCI_STATUS_DETECTED_PARITY |
3247 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3248 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3250 /* The infamous DAC f*ckup only happens at boot time */
3251 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3252 if (netif_msg_intr(tp))
3253 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3254 tp->cp_cmd &= ~PCIDAC;
3255 RTL_W16(CPlusCmd, tp->cp_cmd);
3256 dev->features &= ~NETIF_F_HIGHDMA;
3259 rtl8169_hw_reset(ioaddr);
3261 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3264 static void rtl8169_tx_interrupt(struct net_device *dev,
3265 struct rtl8169_private *tp,
3266 void __iomem *ioaddr)
3268 unsigned int dirty_tx, tx_left;
3270 dirty_tx = tp->dirty_tx;
3272 tx_left = tp->cur_tx - dirty_tx;
3274 while (tx_left > 0) {
3275 unsigned int entry = dirty_tx % NUM_TX_DESC;
3276 struct ring_info *tx_skb = tp->tx_skb + entry;
3277 u32 len = tx_skb->len;
3281 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3282 if (status & DescOwn)
3285 dev->stats.tx_bytes += len;
3286 dev->stats.tx_packets++;
3288 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3290 if (status & LastFrag) {
3291 dev_kfree_skb_irq(tx_skb->skb);
3298 if (tp->dirty_tx != dirty_tx) {
3299 tp->dirty_tx = dirty_tx;
3301 if (netif_queue_stopped(dev) &&
3302 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3303 netif_wake_queue(dev);
3306 * 8168 hack: TxPoll requests are lost when the Tx packets are
3307 * too close. Let's kick an extra TxPoll request when a burst
3308 * of start_xmit activity is detected (if it is not detected,
3309 * it is slow enough). -- FR
3312 if (tp->cur_tx != dirty_tx)
3313 RTL_W8(TxPoll, NPQ);
3317 static inline int rtl8169_fragmented_frame(u32 status)
3319 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3322 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3324 u32 opts1 = le32_to_cpu(desc->opts1);
3325 u32 status = opts1 & RxProtoMask;
3327 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3328 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3329 ((status == RxProtoIP) && !(opts1 & IPFail)))
3330 skb->ip_summed = CHECKSUM_UNNECESSARY;
3332 skb->ip_summed = CHECKSUM_NONE;
3335 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3336 struct rtl8169_private *tp, int pkt_size,
3339 struct sk_buff *skb;
3342 if (pkt_size >= rx_copybreak)
3345 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3349 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3350 PCI_DMA_FROMDEVICE);
3351 skb_reserve(skb, NET_IP_ALIGN);
3352 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3359 static int rtl8169_rx_interrupt(struct net_device *dev,
3360 struct rtl8169_private *tp,
3361 void __iomem *ioaddr, u32 budget)
3363 unsigned int cur_rx, rx_left;
3364 unsigned int delta, count;
3366 cur_rx = tp->cur_rx;
3367 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3368 rx_left = min(rx_left, budget);
3370 for (; rx_left > 0; rx_left--, cur_rx++) {
3371 unsigned int entry = cur_rx % NUM_RX_DESC;
3372 struct RxDesc *desc = tp->RxDescArray + entry;
3376 status = le32_to_cpu(desc->opts1);
3378 if (status & DescOwn)
3380 if (unlikely(status & RxRES)) {
3381 if (netif_msg_rx_err(tp)) {
3383 "%s: Rx ERROR. status = %08x\n",
3386 dev->stats.rx_errors++;
3387 if (status & (RxRWT | RxRUNT))
3388 dev->stats.rx_length_errors++;
3390 dev->stats.rx_crc_errors++;
3391 if (status & RxFOVF) {
3392 rtl8169_schedule_work(dev, rtl8169_reset_task);
3393 dev->stats.rx_fifo_errors++;
3395 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3397 struct sk_buff *skb = tp->Rx_skbuff[entry];
3398 dma_addr_t addr = le64_to_cpu(desc->addr);
3399 int pkt_size = (status & 0x00001FFF) - 4;
3400 struct pci_dev *pdev = tp->pci_dev;
3403 * The driver does not support incoming fragmented
3404 * frames. They are seen as a symptom of over-mtu
3407 if (unlikely(rtl8169_fragmented_frame(status))) {
3408 dev->stats.rx_dropped++;
3409 dev->stats.rx_length_errors++;
3410 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3414 rtl8169_rx_csum(skb, desc);
3416 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3417 pci_dma_sync_single_for_device(pdev, addr,
3418 pkt_size, PCI_DMA_FROMDEVICE);
3419 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3421 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3422 PCI_DMA_FROMDEVICE);
3423 tp->Rx_skbuff[entry] = NULL;
3426 skb_put(skb, pkt_size);
3427 skb->protocol = eth_type_trans(skb, dev);
3429 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3430 netif_receive_skb(skb);
3432 dev->last_rx = jiffies;
3433 dev->stats.rx_bytes += pkt_size;
3434 dev->stats.rx_packets++;
3437 /* Work around for AMD plateform. */
3438 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3439 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3445 count = cur_rx - tp->cur_rx;
3446 tp->cur_rx = cur_rx;
3448 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3449 if (!delta && count && netif_msg_intr(tp))
3450 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3451 tp->dirty_rx += delta;
3454 * FIXME: until there is periodic timer to try and refill the ring,
3455 * a temporary shortage may definitely kill the Rx process.
3456 * - disable the asic to try and avoid an overflow and kick it again
3458 * - how do others driver handle this condition (Uh oh...).
3460 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3461 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3466 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3468 struct net_device *dev = dev_instance;
3469 struct rtl8169_private *tp = netdev_priv(dev);
3470 void __iomem *ioaddr = tp->mmio_addr;
3474 status = RTL_R16(IntrStatus);
3476 /* hotplug/major error/no more work/shared irq */
3477 if ((status == 0xffff) || !status)
3482 if (unlikely(!netif_running(dev))) {
3483 rtl8169_asic_down(ioaddr);
3487 status &= tp->intr_mask;
3489 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3491 if (!(status & tp->intr_event))
3494 /* Work around for rx fifo overflow */
3495 if (unlikely(status & RxFIFOOver) &&
3496 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3497 netif_stop_queue(dev);
3498 rtl8169_tx_timeout(dev);
3502 if (unlikely(status & SYSErr)) {
3503 rtl8169_pcierr_interrupt(dev);
3507 if (status & LinkChg)
3508 rtl8169_check_link_status(dev, tp, ioaddr);
3510 if (status & tp->napi_event) {
3511 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3512 tp->intr_mask = ~tp->napi_event;
3514 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3515 __netif_rx_schedule(dev, &tp->napi);
3516 else if (netif_msg_intr(tp)) {
3517 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3522 return IRQ_RETVAL(handled);
3525 static int rtl8169_poll(struct napi_struct *napi, int budget)
3527 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3528 struct net_device *dev = tp->dev;
3529 void __iomem *ioaddr = tp->mmio_addr;
3532 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3533 rtl8169_tx_interrupt(dev, tp, ioaddr);
3535 if (work_done < budget) {
3536 netif_rx_complete(dev, napi);
3537 tp->intr_mask = 0xffff;
3539 * 20040426: the barrier is not strictly required but the
3540 * behavior of the irq handler could be less predictable
3541 * without it. Btw, the lack of flush for the posted pci
3542 * write is safe - FR
3545 RTL_W16(IntrMask, tp->intr_event);
3551 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3553 struct rtl8169_private *tp = netdev_priv(dev);
3555 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3558 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3559 RTL_W32(RxMissed, 0);
3562 static void rtl8169_down(struct net_device *dev)
3564 struct rtl8169_private *tp = netdev_priv(dev);
3565 void __iomem *ioaddr = tp->mmio_addr;
3566 unsigned int intrmask;
3568 rtl8169_delete_timer(dev);
3570 netif_stop_queue(dev);
3572 napi_disable(&tp->napi);
3575 spin_lock_irq(&tp->lock);
3577 rtl8169_asic_down(ioaddr);
3579 rtl8169_rx_missed(dev, ioaddr);
3581 spin_unlock_irq(&tp->lock);
3583 synchronize_irq(dev->irq);
3585 /* Give a racing hard_start_xmit a few cycles to complete. */
3586 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3589 * And now for the 50k$ question: are IRQ disabled or not ?
3591 * Two paths lead here:
3593 * -> netif_running() is available to sync the current code and the
3594 * IRQ handler. See rtl8169_interrupt for details.
3595 * 2) dev->change_mtu
3596 * -> rtl8169_poll can not be issued again and re-enable the
3597 * interruptions. Let's simply issue the IRQ down sequence again.
3599 * No loop if hotpluged or major error (0xffff).
3601 intrmask = RTL_R16(IntrMask);
3602 if (intrmask && (intrmask != 0xffff))
3605 rtl8169_tx_clear(tp);
3607 rtl8169_rx_clear(tp);
3610 static int rtl8169_close(struct net_device *dev)
3612 struct rtl8169_private *tp = netdev_priv(dev);
3613 struct pci_dev *pdev = tp->pci_dev;
3617 free_irq(dev->irq, dev);
3619 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3621 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3623 tp->TxDescArray = NULL;
3624 tp->RxDescArray = NULL;
3629 static void rtl_set_rx_mode(struct net_device *dev)
3631 struct rtl8169_private *tp = netdev_priv(dev);
3632 void __iomem *ioaddr = tp->mmio_addr;
3633 unsigned long flags;
3634 u32 mc_filter[2]; /* Multicast hash filter */
3638 if (dev->flags & IFF_PROMISC) {
3639 /* Unconditionally log net taps. */
3640 if (netif_msg_link(tp)) {
3641 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3645 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3647 mc_filter[1] = mc_filter[0] = 0xffffffff;
3648 } else if ((dev->mc_count > multicast_filter_limit)
3649 || (dev->flags & IFF_ALLMULTI)) {
3650 /* Too many to filter perfectly -- accept all multicasts. */
3651 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3652 mc_filter[1] = mc_filter[0] = 0xffffffff;
3654 struct dev_mc_list *mclist;
3657 rx_mode = AcceptBroadcast | AcceptMyPhys;
3658 mc_filter[1] = mc_filter[0] = 0;
3659 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3660 i++, mclist = mclist->next) {
3661 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3662 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3663 rx_mode |= AcceptMulticast;
3667 spin_lock_irqsave(&tp->lock, flags);
3669 tmp = rtl8169_rx_config | rx_mode |
3670 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3672 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3673 u32 data = mc_filter[0];
3675 mc_filter[0] = swab32(mc_filter[1]);
3676 mc_filter[1] = swab32(data);
3679 RTL_W32(MAR0 + 0, mc_filter[0]);
3680 RTL_W32(MAR0 + 4, mc_filter[1]);
3682 RTL_W32(RxConfig, tmp);
3684 spin_unlock_irqrestore(&tp->lock, flags);
3688 * rtl8169_get_stats - Get rtl8169 read/write statistics
3689 * @dev: The Ethernet Device to get statistics for
3691 * Get TX/RX statistics for rtl8169
3693 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3695 struct rtl8169_private *tp = netdev_priv(dev);
3696 void __iomem *ioaddr = tp->mmio_addr;
3697 unsigned long flags;
3699 if (netif_running(dev)) {
3700 spin_lock_irqsave(&tp->lock, flags);
3701 rtl8169_rx_missed(dev, ioaddr);
3702 spin_unlock_irqrestore(&tp->lock, flags);
3710 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3712 struct net_device *dev = pci_get_drvdata(pdev);
3713 struct rtl8169_private *tp = netdev_priv(dev);
3714 void __iomem *ioaddr = tp->mmio_addr;
3716 if (!netif_running(dev))
3717 goto out_pci_suspend;
3719 netif_device_detach(dev);
3720 netif_stop_queue(dev);
3722 spin_lock_irq(&tp->lock);
3724 rtl8169_asic_down(ioaddr);
3726 rtl8169_rx_missed(dev, ioaddr);
3728 spin_unlock_irq(&tp->lock);
3731 pci_save_state(pdev);
3732 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3733 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3734 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3739 static int rtl8169_resume(struct pci_dev *pdev)
3741 struct net_device *dev = pci_get_drvdata(pdev);
3743 pci_set_power_state(pdev, PCI_D0);
3744 pci_restore_state(pdev);
3745 pci_enable_wake(pdev, PCI_D0, 0);
3747 if (!netif_running(dev))
3750 netif_device_attach(dev);
3752 rtl8169_schedule_work(dev, rtl8169_reset_task);
3757 #endif /* CONFIG_PM */
3759 static struct pci_driver rtl8169_pci_driver = {
3761 .id_table = rtl8169_pci_tbl,
3762 .probe = rtl8169_init_one,
3763 .remove = __devexit_p(rtl8169_remove_one),
3765 .suspend = rtl8169_suspend,
3766 .resume = rtl8169_resume,
3770 static int __init rtl8169_init_module(void)
3772 return pci_register_driver(&rtl8169_pci_driver);
3775 static void __exit rtl8169_cleanup_module(void)
3777 pci_unregister_driver(&rtl8169_pci_driver);
3780 module_init(rtl8169_init_module);
3781 module_exit(rtl8169_cleanup_module);