drivers/net/phy/micrel.c

   1 /*
   2  * drivers/net/phy/micrel.c
   3  *
   4  * Driver for Micrel PHYs
   5  *
   6  * Author: David J. Choi
   7  *
   8  * Copyright (c) 2010-2013 Micrel, Inc.
   9  * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  * Support : Micrel Phys:
  17  *              Giga phys: ksz9021, ksz9031
  18  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  19  *                         ksz8021, ksz8031, ksz8051,
  20  *                         ksz8081, ksz8091,
  21  *                         ksz8061,
  22  *              Switch : ksz8873, ksz886x
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/phy.h>
  28 #include <linux/micrel_phy.h>
  29 #include <linux/of.h>
  30 #include <linux/clk.h>
  31
  32 /* Operation Mode Strap Override */
  33 #define MII_KSZPHY_OMSO                         0x16
  34 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  35 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  36 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  37 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  38
  39 /* general Interrupt control/status reg in vendor specific block. */
  40 #define MII_KSZPHY_INTCS                        0x1B
  41 #define KSZPHY_INTCS_JABBER                     BIT(15)
  42 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  43 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  44 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  45 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  46 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  47 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  48 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  49 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  50                                                 KSZPHY_INTCS_LINK_DOWN)
  51
  52 /* PHY Control 1 */
  53 #define MII_KSZPHY_CTRL_1                       0x1e
  54
  55 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
  56 #define MII_KSZPHY_CTRL_2                       0x1f
  57 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
  58 /* bitmap of PHY register to set interrupt mode */
  59 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
  60 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
  61
  62 /* Write/read to/from extended registers */
  63 #define MII_KSZPHY_EXTREG                       0x0b
  64 #define KSZPHY_EXTREG_WRITE                     0x8000
  65
  66 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
  67 #define MII_KSZPHY_EXTREG_READ                  0x0d
  68
  69 /* Extended registers */
  70 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
  71 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
  72 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
  73
  74 #define PS_TO_REG                               200
  75
  76 struct kszphy_type {
  77         u32 led_mode_reg;
  78         u16 interrupt_level_mask;
  79         bool has_broadcast_disable;
  80         bool has_nand_tree_disable;
  81         bool has_rmii_ref_clk_sel;
  82 };
  83
  84 struct kszphy_priv {
  85         const struct kszphy_type *type;
  86         int led_mode;
  87         bool rmii_ref_clk_sel;
  88         bool rmii_ref_clk_sel_val;
  89 };
  90
  91 static const struct kszphy_type ksz8021_type = {
  92         .led_mode_reg           = MII_KSZPHY_CTRL_2,
  93         .has_broadcast_disable  = true,
  94         .has_nand_tree_disable  = true,
  95         .has_rmii_ref_clk_sel   = true,
  96 };
  97
  98 static const struct kszphy_type ksz8041_type = {
  99         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 100 };
 101
 102 static const struct kszphy_type ksz8051_type = {
 103         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 104         .has_nand_tree_disable  = true,
 105 };
 106
 107 static const struct kszphy_type ksz8081_type = {
 108         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 109         .has_broadcast_disable  = true,
 110         .has_nand_tree_disable  = true,
 111         .has_rmii_ref_clk_sel   = true,
 112 };
 113
 114 static const struct kszphy_type ks8737_type = {
 115         .interrupt_level_mask   = BIT(14),
 116 };
 117
 118 static const struct kszphy_type ksz9021_type = {
 119         .interrupt_level_mask   = BIT(14),
 120 };
 121
 122 static int kszphy_extended_write(struct phy_device *phydev,
 123                                 u32 regnum, u16 val)
 124 {
 125         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 126         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 127 }
 128
 129 static int kszphy_extended_read(struct phy_device *phydev,
 130                                 u32 regnum)
 131 {
 132         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 133         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 134 }
 135
 136 static int kszphy_ack_interrupt(struct phy_device *phydev)
 137 {
 138         /* bit[7..0] int status, which is a read and clear register. */
 139         int rc;
 140
 141         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 142
 143         return (rc < 0) ? rc : 0;
 144 }
 145
 146 static int kszphy_config_intr(struct phy_device *phydev)
 147 {
 148         const struct kszphy_type *type = phydev->drv->driver_data;
 149         int temp;
 150         u16 mask;
 151
 152         if (type && type->interrupt_level_mask)
 153                 mask = type->interrupt_level_mask;
 154         else
 155                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 156
 157         /* set the interrupt pin active low */
 158         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 159         if (temp < 0)
 160                 return temp;
 161         temp &= ~mask;
 162         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 163
 164         /* enable / disable interrupts */
 165         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 166                 temp = KSZPHY_INTCS_ALL;
 167         else
 168                 temp = 0;
 169
 170         return phy_write(phydev, MII_KSZPHY_INTCS, temp);
 171 }
 172
 173 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 174 {
 175         int ctrl;
 176
 177         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 178         if (ctrl < 0)
 179                 return ctrl;
 180
 181         if (val)
 182                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 183         else
 184                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 185
 186         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 187 }
 188
 189 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 190 {
 191         int rc, temp, shift;
 192
 193         switch (reg) {
 194         case MII_KSZPHY_CTRL_1:
 195                 shift = 14;
 196                 break;
 197         case MII_KSZPHY_CTRL_2:
 198                 shift = 4;
 199                 break;
 200         default:
 201                 return -EINVAL;
 202         }
 203
 204         temp = phy_read(phydev, reg);
 205         if (temp < 0) {
 206                 rc = temp;
 207                 goto out;
 208         }
 209
 210         temp &= ~(3 << shift);
 211         temp |= val << shift;
 212         rc = phy_write(phydev, reg, temp);
 213 out:
 214         if (rc < 0)
 215                 dev_err(&phydev->dev, "failed to set led mode\n");
 216
 217         return rc;
 218 }
 219
 220 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 221  * unique (non-broadcast) address on a shared bus.
 222  */
 223 static int kszphy_broadcast_disable(struct phy_device *phydev)
 224 {
 225         int ret;
 226
 227         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 228         if (ret < 0)
 229                 goto out;
 230
 231         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 232 out:
 233         if (ret)
 234                 dev_err(&phydev->dev, "failed to disable broadcast address\n");
 235
 236         return ret;
 237 }
 238
 239 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 240 {
 241         int ret;
 242
 243         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 244         if (ret < 0)
 245                 goto out;
 246
 247         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 248                 return 0;
 249
 250         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 251                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 252 out:
 253         if (ret)
 254                 dev_err(&phydev->dev, "failed to disable NAND tree mode\n");
 255
 256         return ret;
 257 }
 258
 259 static int kszphy_config_init(struct phy_device *phydev)
 260 {
 261         struct kszphy_priv *priv = phydev->priv;
 262         const struct kszphy_type *type;
 263         int ret;
 264
 265         if (!priv)
 266                 return 0;
 267
 268         type = priv->type;
 269
 270         if (type->has_broadcast_disable)
 271                 kszphy_broadcast_disable(phydev);
 272
 273         if (type->has_nand_tree_disable)
 274                 kszphy_nand_tree_disable(phydev);
 275
 276         if (priv->rmii_ref_clk_sel) {
 277                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 278                 if (ret) {
 279                         dev_err(&phydev->dev, "failed to set rmii reference clock\n");
 280                         return ret;
 281                 }
 282         }
 283
 284         if (priv->led_mode >= 0)
 285                 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
 286
 287         return 0;
 288 }
 289
 290 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 291                                        const struct device_node *of_node,
 292                                        u16 reg,
 293                                        const char *field1, const char *field2,
 294                                        const char *field3, const char *field4)
 295 {
 296         int val1 = -1;
 297         int val2 = -2;
 298         int val3 = -3;
 299         int val4 = -4;
 300         int newval;
 301         int matches = 0;
 302
 303         if (!of_property_read_u32(of_node, field1, &val1))
 304                 matches++;
 305
 306         if (!of_property_read_u32(of_node, field2, &val2))
 307                 matches++;
 308
 309         if (!of_property_read_u32(of_node, field3, &val3))
 310                 matches++;
 311
 312         if (!of_property_read_u32(of_node, field4, &val4))
 313                 matches++;
 314
 315         if (!matches)
 316                 return 0;
 317
 318         if (matches < 4)
 319                 newval = kszphy_extended_read(phydev, reg);
 320         else
 321                 newval = 0;
 322
 323         if (val1 != -1)
 324                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 325
 326         if (val2 != -2)
 327                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 328
 329         if (val3 != -3)
 330                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 331
 332         if (val4 != -4)
 333                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 334
 335         return kszphy_extended_write(phydev, reg, newval);
 336 }
 337
 338 static int ksz9021_config_init(struct phy_device *phydev)
 339 {
 340         const struct device *dev = &phydev->dev;
 341         const struct device_node *of_node = dev->of_node;
 342
 343         if (!of_node && dev->parent->of_node)
 344                 of_node = dev->parent->of_node;
 345
 346         if (of_node) {
 347                 ksz9021_load_values_from_of(phydev, of_node,
 348                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 349                                     "txen-skew-ps", "txc-skew-ps",
 350                                     "rxdv-skew-ps", "rxc-skew-ps");
 351                 ksz9021_load_values_from_of(phydev, of_node,
 352                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 353                                     "rxd0-skew-ps", "rxd1-skew-ps",
 354                                     "rxd2-skew-ps", "rxd3-skew-ps");
 355                 ksz9021_load_values_from_of(phydev, of_node,
 356                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 357                                     "txd0-skew-ps", "txd1-skew-ps",
 358                                     "txd2-skew-ps", "txd3-skew-ps");
 359         }
 360         return 0;
 361 }
 362
 363 #define MII_KSZ9031RN_MMD_CTRL_REG      0x0d
 364 #define MII_KSZ9031RN_MMD_REGDATA_REG   0x0e
 365 #define OP_DATA                         1
 366 #define KSZ9031_PS_TO_REG               60
 367
 368 /* Extended registers */
 369 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 370 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 371 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 372 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 373
 374 static int ksz9031_extended_write(struct phy_device *phydev,
 375                                   u8 mode, u32 dev_addr, u32 regnum, u16 val)
 376 {
 377         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 378         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 379         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 380         return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
 381 }
 382
 383 static int ksz9031_extended_read(struct phy_device *phydev,
 384                                  u8 mode, u32 dev_addr, u32 regnum)
 385 {
 386         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
 387         phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
 388         phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
 389         return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
 390 }
 391
 392 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 393                                        const struct device_node *of_node,
 394                                        u16 reg, size_t field_sz,
 395                                        const char *field[], u8 numfields)
 396 {
 397         int val[4] = {-1, -2, -3, -4};
 398         int matches = 0;
 399         u16 mask;
 400         u16 maxval;
 401         u16 newval;
 402         int i;
 403
 404         for (i = 0; i < numfields; i++)
 405                 if (!of_property_read_u32(of_node, field[i], val + i))
 406                         matches++;
 407
 408         if (!matches)
 409                 return 0;
 410
 411         if (matches < numfields)
 412                 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
 413         else
 414                 newval = 0;
 415
 416         maxval = (field_sz == 4) ? 0xf : 0x1f;
 417         for (i = 0; i < numfields; i++)
 418                 if (val[i] != -(i + 1)) {
 419                         mask = 0xffff;
 420                         mask ^= maxval << (field_sz * i);
 421                         newval = (newval & mask) |
 422                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 423                                         << (field_sz * i));
 424                 }
 425
 426         return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
 427 }
 428
 429 static int ksz9031_config_init(struct phy_device *phydev)
 430 {
 431         const struct device *dev = &phydev->dev;
 432         const struct device_node *of_node = dev->of_node;
 433         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
 434         static const char *rx_data_skews[4] = {
 435                 "rxd0-skew-ps", "rxd1-skew-ps",
 436                 "rxd2-skew-ps", "rxd3-skew-ps"
 437         };
 438         static const char *tx_data_skews[4] = {
 439                 "txd0-skew-ps", "txd1-skew-ps",
 440                 "txd2-skew-ps", "txd3-skew-ps"
 441         };
 442         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
 443
 444         if (!of_node && dev->parent->of_node)
 445                 of_node = dev->parent->of_node;
 446
 447         if (of_node) {
 448                 ksz9031_of_load_skew_values(phydev, of_node,
 449                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
 450                                 clk_skews, 2);
 451
 452                 ksz9031_of_load_skew_values(phydev, of_node,
 453                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
 454                                 control_skews, 2);
 455
 456                 ksz9031_of_load_skew_values(phydev, of_node,
 457                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
 458                                 rx_data_skews, 4);
 459
 460                 ksz9031_of_load_skew_values(phydev, of_node,
 461                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
 462                                 tx_data_skews, 4);
 463         }
 464         return 0;
 465 }
 466
 467 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
 468 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
 469 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
 470 static int ksz8873mll_read_status(struct phy_device *phydev)
 471 {
 472         int regval;
 473
 474         /* dummy read */
 475         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 476
 477         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
 478
 479         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
 480                 phydev->duplex = DUPLEX_HALF;
 481         else
 482                 phydev->duplex = DUPLEX_FULL;
 483
 484         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
 485                 phydev->speed = SPEED_10;
 486         else
 487                 phydev->speed = SPEED_100;
 488
 489         phydev->link = 1;
 490         phydev->pause = phydev->asym_pause = 0;
 491
 492         return 0;
 493 }
 494
 495 static int ksz8873mll_config_aneg(struct phy_device *phydev)
 496 {
 497         return 0;
 498 }
 499
 500 /* This routine returns -1 as an indication to the caller that the
 501  * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
 502  * MMD extended PHY registers.
 503  */
 504 static int
 505 ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 506                       int regnum)
 507 {
 508         return -1;
 509 }
 510
 511 /* This routine does nothing since the Micrel ksz9021 does not support
 512  * standard IEEE MMD extended PHY registers.
 513  */
 514 static void
 515 ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
 516                       int regnum, u32 val)
 517 {
 518 }
 519
 520 static int kszphy_probe(struct phy_device *phydev)
 521 {
 522         const struct kszphy_type *type = phydev->drv->driver_data;
 523         const struct device_node *np = phydev->dev.of_node;
 524         struct kszphy_priv *priv;
 525         struct clk *clk;
 526         int ret;
 527
 528         priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL);
 529         if (!priv)
 530                 return -ENOMEM;
 531
 532         phydev->priv = priv;
 533
 534         priv->type = type;
 535
 536         if (type->led_mode_reg) {
 537                 ret = of_property_read_u32(np, "micrel,led-mode",
 538                                 &priv->led_mode);
 539                 if (ret)
 540                         priv->led_mode = -1;
 541
 542                 if (priv->led_mode > 3) {
 543                         dev_err(&phydev->dev, "invalid led mode: 0x%02x\n",
 544                                         priv->led_mode);
 545                         priv->led_mode = -1;
 546                 }
 547         } else {
 548                 priv->led_mode = -1;
 549         }
 550
 551         clk = devm_clk_get(&phydev->dev, "rmii-ref");
 552         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
 553         if (!IS_ERR_OR_NULL(clk)) {
 554                 unsigned long rate = clk_get_rate(clk);
 555                 bool rmii_ref_clk_sel_25_mhz;
 556
 557                 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
 558                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
 559                                 "micrel,rmii-reference-clock-select-25-mhz");
 560
 561                 if (rate > 24500000 && rate < 25500000) {
 562                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
 563                 } else if (rate > 49500000 && rate < 50500000) {
 564                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
 565                 } else {
 566                         dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate);
 567                         return -EINVAL;
 568                 }
 569         }
 570
 571         /* Support legacy board-file configuration */
 572         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
 573                 priv->rmii_ref_clk_sel = true;
 574                 priv->rmii_ref_clk_sel_val = true;
 575         }
 576
 577         return 0;
 578 }
 579
 580 static struct phy_driver ksphy_driver[] = {
 581 {
 582         .phy_id         = PHY_ID_KS8737,
 583         .phy_id_mask    = 0x00fffff0,
 584         .name           = "Micrel KS8737",
 585         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 586         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 587         .driver_data    = &ks8737_type,
 588         .config_init    = kszphy_config_init,
 589         .config_aneg    = genphy_config_aneg,
 590         .read_status    = genphy_read_status,
 591         .ack_interrupt  = kszphy_ack_interrupt,
 592         .config_intr    = kszphy_config_intr,
 593         .suspend        = genphy_suspend,
 594         .resume         = genphy_resume,
 595         .driver         = { .owner = THIS_MODULE,},
 596 }, {
 597         .phy_id         = PHY_ID_KSZ8021,
 598         .phy_id_mask    = 0x00ffffff,
 599         .name           = "Micrel KSZ8021 or KSZ8031",
 600         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 601                            SUPPORTED_Asym_Pause),
 602         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 603         .driver_data    = &ksz8021_type,
 604         .probe          = kszphy_probe,
 605         .config_init    = kszphy_config_init,
 606         .config_aneg    = genphy_config_aneg,
 607         .read_status    = genphy_read_status,
 608         .ack_interrupt  = kszphy_ack_interrupt,
 609         .config_intr    = kszphy_config_intr,
 610         .suspend        = genphy_suspend,
 611         .resume         = genphy_resume,
 612         .driver         = { .owner = THIS_MODULE,},
 613 }, {
 614         .phy_id         = PHY_ID_KSZ8031,
 615         .phy_id_mask    = 0x00ffffff,
 616         .name           = "Micrel KSZ8031",
 617         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
 618                            SUPPORTED_Asym_Pause),
 619         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 620         .driver_data    = &ksz8021_type,
 621         .probe          = kszphy_probe,
 622         .config_init    = kszphy_config_init,
 623         .config_aneg    = genphy_config_aneg,
 624         .read_status    = genphy_read_status,
 625         .ack_interrupt  = kszphy_ack_interrupt,
 626         .config_intr    = kszphy_config_intr,
 627         .suspend        = genphy_suspend,
 628         .resume         = genphy_resume,
 629         .driver         = { .owner = THIS_MODULE,},
 630 }, {
 631         .phy_id         = PHY_ID_KSZ8041,
 632         .phy_id_mask    = 0x00fffff0,
 633         .name           = "Micrel KSZ8041",
 634         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 635                                 | SUPPORTED_Asym_Pause),
 636         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 637         .driver_data    = &ksz8041_type,
 638         .probe          = kszphy_probe,
 639         .config_init    = kszphy_config_init,
 640         .config_aneg    = genphy_config_aneg,
 641         .read_status    = genphy_read_status,
 642         .ack_interrupt  = kszphy_ack_interrupt,
 643         .config_intr    = kszphy_config_intr,
 644         .suspend        = genphy_suspend,
 645         .resume         = genphy_resume,
 646         .driver         = { .owner = THIS_MODULE,},
 647 }, {
 648         .phy_id         = PHY_ID_KSZ8041RNLI,
 649         .phy_id_mask    = 0x00fffff0,
 650         .name           = "Micrel KSZ8041RNLI",
 651         .features       = PHY_BASIC_FEATURES |
 652                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
 653         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 654         .driver_data    = &ksz8041_type,
 655         .probe          = kszphy_probe,
 656         .config_init    = kszphy_config_init,
 657         .config_aneg    = genphy_config_aneg,
 658         .read_status    = genphy_read_status,
 659         .ack_interrupt  = kszphy_ack_interrupt,
 660         .config_intr    = kszphy_config_intr,
 661         .suspend        = genphy_suspend,
 662         .resume         = genphy_resume,
 663         .driver         = { .owner = THIS_MODULE,},
 664 }, {
 665         .phy_id         = PHY_ID_KSZ8051,
 666         .phy_id_mask    = 0x00fffff0,
 667         .name           = "Micrel KSZ8051",
 668         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
 669                                 | SUPPORTED_Asym_Pause),
 670         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 671         .driver_data    = &ksz8051_type,
 672         .probe          = kszphy_probe,
 673         .config_init    = kszphy_config_init,
 674         .config_aneg    = genphy_config_aneg,
 675         .read_status    = genphy_read_status,
 676         .ack_interrupt  = kszphy_ack_interrupt,
 677         .config_intr    = kszphy_config_intr,
 678         .suspend        = genphy_suspend,
 679         .resume         = genphy_resume,
 680         .driver         = { .owner = THIS_MODULE,},
 681 }, {
 682         .phy_id         = PHY_ID_KSZ8001,
 683         .name           = "Micrel KSZ8001 or KS8721",
 684         .phy_id_mask    = 0x00ffffff,
 685         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 686         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 687         .driver_data    = &ksz8041_type,
 688         .probe          = kszphy_probe,
 689         .config_init    = kszphy_config_init,
 690         .config_aneg    = genphy_config_aneg,
 691         .read_status    = genphy_read_status,
 692         .ack_interrupt  = kszphy_ack_interrupt,
 693         .config_intr    = kszphy_config_intr,
 694         .suspend        = genphy_suspend,
 695         .resume         = genphy_resume,
 696         .driver         = { .owner = THIS_MODULE,},
 697 }, {
 698         .phy_id         = PHY_ID_KSZ8081,
 699         .name           = "Micrel KSZ8081 or KSZ8091",
 700         .phy_id_mask    = 0x00fffff0,
 701         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 702         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 703         .driver_data    = &ksz8081_type,
 704         .probe          = kszphy_probe,
 705         .config_init    = kszphy_config_init,
 706         .config_aneg    = genphy_config_aneg,
 707         .read_status    = genphy_read_status,
 708         .ack_interrupt  = kszphy_ack_interrupt,
 709         .config_intr    = kszphy_config_intr,
 710         .suspend        = genphy_suspend,
 711         .resume         = genphy_resume,
 712         .driver         = { .owner = THIS_MODULE,},
 713 }, {
 714         .phy_id         = PHY_ID_KSZ8061,
 715         .name           = "Micrel KSZ8061",
 716         .phy_id_mask    = 0x00fffff0,
 717         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 718         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 719         .config_init    = kszphy_config_init,
 720         .config_aneg    = genphy_config_aneg,
 721         .read_status    = genphy_read_status,
 722         .ack_interrupt  = kszphy_ack_interrupt,
 723         .config_intr    = kszphy_config_intr,
 724         .suspend        = genphy_suspend,
 725         .resume         = genphy_resume,
 726         .driver         = { .owner = THIS_MODULE,},
 727 }, {
 728         .phy_id         = PHY_ID_KSZ9021,
 729         .phy_id_mask    = 0x000ffffe,
 730         .name           = "Micrel KSZ9021 Gigabit PHY",
 731         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 732         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 733         .driver_data    = &ksz9021_type,
 734         .config_init    = ksz9021_config_init,
 735         .config_aneg    = genphy_config_aneg,
 736         .read_status    = genphy_read_status,
 737         .ack_interrupt  = kszphy_ack_interrupt,
 738         .config_intr    = kszphy_config_intr,
 739         .suspend        = genphy_suspend,
 740         .resume         = genphy_resume,
 741         .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
 742         .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
 743         .driver         = { .owner = THIS_MODULE, },
 744 }, {
 745         .phy_id         = PHY_ID_KSZ9031,
 746         .phy_id_mask    = 0x00fffff0,
 747         .name           = "Micrel KSZ9031 Gigabit PHY",
 748         .features       = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
 749         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 750         .driver_data    = &ksz9021_type,
 751         .config_init    = ksz9031_config_init,
 752         .config_aneg    = genphy_config_aneg,
 753         .read_status    = genphy_read_status,
 754         .ack_interrupt  = kszphy_ack_interrupt,
 755         .config_intr    = kszphy_config_intr,
 756         .suspend        = genphy_suspend,
 757         .resume         = genphy_resume,
 758         .driver         = { .owner = THIS_MODULE, },
 759 }, {
 760         .phy_id         = PHY_ID_KSZ8873MLL,
 761         .phy_id_mask    = 0x00fffff0,
 762         .name           = "Micrel KSZ8873MLL Switch",
 763         .features       = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
 764         .flags          = PHY_HAS_MAGICANEG,
 765         .config_init    = kszphy_config_init,
 766         .config_aneg    = ksz8873mll_config_aneg,
 767         .read_status    = ksz8873mll_read_status,
 768         .suspend        = genphy_suspend,
 769         .resume         = genphy_resume,
 770         .driver         = { .owner = THIS_MODULE, },
 771 }, {
 772         .phy_id         = PHY_ID_KSZ886X,
 773         .phy_id_mask    = 0x00fffff0,
 774         .name           = "Micrel KSZ886X Switch",
 775         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
 776         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
 777         .config_init    = kszphy_config_init,
 778         .config_aneg    = genphy_config_aneg,
 779         .read_status    = genphy_read_status,
 780         .suspend        = genphy_suspend,
 781         .resume         = genphy_resume,
 782         .driver         = { .owner = THIS_MODULE, },
 783 } };
 784
 785 module_phy_driver(ksphy_driver);
 786
 787 MODULE_DESCRIPTION("Micrel PHY driver");
 788 MODULE_AUTHOR("David J. Choi");
 789 MODULE_LICENSE("GPL");
 790
 791 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
 792         { PHY_ID_KSZ9021, 0x000ffffe },
 793         { PHY_ID_KSZ9031, 0x00fffff0 },
 794         { PHY_ID_KSZ8001, 0x00ffffff },
 795         { PHY_ID_KS8737, 0x00fffff0 },
 796         { PHY_ID_KSZ8021, 0x00ffffff },
 797         { PHY_ID_KSZ8031, 0x00ffffff },
 798         { PHY_ID_KSZ8041, 0x00fffff0 },
 799         { PHY_ID_KSZ8051, 0x00fffff0 },
 800         { PHY_ID_KSZ8061, 0x00fffff0 },
 801         { PHY_ID_KSZ8081, 0x00fffff0 },
 802         { PHY_ID_KSZ8873MLL, 0x00fffff0 },
 803         { PHY_ID_KSZ886X, 0x00fffff0 },
 804         { }
 805 };
 806
 807 MODULE_DEVICE_TABLE(mdio, micrel_tbl);