2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
53 /* Static function declarations */
54 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
55 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
56 static void eth_port_set_multicast_list(struct net_device *);
57 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
59 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
61 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
62 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
63 static int mv643xx_eth_open(struct net_device *);
64 static int mv643xx_eth_stop(struct net_device *);
65 static int mv643xx_eth_change_mtu(struct net_device *, int);
66 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
67 static void eth_port_init_mac_tables(unsigned int eth_port_num);
69 static int mv643xx_poll(struct napi_struct *napi, int budget);
71 static int ethernet_phy_get(unsigned int eth_port_num);
72 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
73 static int ethernet_phy_detect(unsigned int eth_port_num);
74 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
75 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
76 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
77 static const struct ethtool_ops mv643xx_ethtool_ops;
79 static char mv643xx_driver_name[] = "mv643xx_eth";
80 static char mv643xx_driver_version[] = "1.0";
82 static void __iomem *mv643xx_eth_shared_base;
84 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
85 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
87 static inline u32 mv_read(int offset)
89 void __iomem *reg_base;
91 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
93 return readl(reg_base + offset);
96 static inline void mv_write(int offset, u32 data)
98 void __iomem *reg_base;
100 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
101 writel(data, reg_base + offset);
105 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
107 * Input : pointer to ethernet interface network device structure
109 * Output : 0 upon success, -EINVAL upon failure
111 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
113 if ((new_mtu > 9500) || (new_mtu < 64))
118 * Stop then re-open the interface. This will allocate RX skb's with
120 * There is a possible danger that the open will not successed, due
121 * to memory is full, which might fail the open function.
123 if (netif_running(dev)) {
124 mv643xx_eth_stop(dev);
125 if (mv643xx_eth_open(dev))
127 "%s: Fatal error on opening device\n",
135 * mv643xx_eth_rx_refill_descs
137 * Fills / refills RX queue on a certain gigabit ethernet port
139 * Input : pointer to ethernet interface network device structure
142 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
144 struct mv643xx_private *mp = netdev_priv(dev);
145 struct pkt_info pkt_info;
149 while (mp->rx_desc_count < mp->rx_ring_size) {
150 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
154 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
156 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
157 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
158 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
159 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
160 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
161 pkt_info.return_info = skb;
162 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
164 "%s: Error allocating RX Ring\n", dev->name);
167 skb_reserve(skb, ETH_HW_IP_ALIGN);
170 * If RX ring is empty of SKB, set a timer to try allocating
171 * again at a later time.
173 if (mp->rx_desc_count == 0) {
174 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
175 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
176 add_timer(&mp->timeout);
181 * mv643xx_eth_rx_refill_descs_timer_wrapper
183 * Timer routine to wake up RX queue filling task. This function is
184 * used only in case the RX queue is empty, and all alloc_skb has
185 * failed (due to out of memory event).
187 * Input : pointer to ethernet interface network device structure
190 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
192 mv643xx_eth_rx_refill_descs((struct net_device *)data);
196 * mv643xx_eth_update_mac_address
198 * Update the MAC address of the port in the address table
200 * Input : pointer to ethernet interface network device structure
203 static void mv643xx_eth_update_mac_address(struct net_device *dev)
205 struct mv643xx_private *mp = netdev_priv(dev);
206 unsigned int port_num = mp->port_num;
208 eth_port_init_mac_tables(port_num);
209 eth_port_uc_addr_set(port_num, dev->dev_addr);
213 * mv643xx_eth_set_rx_mode
215 * Change from promiscuos to regular rx mode
217 * Input : pointer to ethernet interface network device structure
220 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
222 struct mv643xx_private *mp = netdev_priv(dev);
225 config_reg = mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num));
226 if (dev->flags & IFF_PROMISC)
227 config_reg |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
229 config_reg &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
230 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), config_reg);
232 eth_port_set_multicast_list(dev);
236 * mv643xx_eth_set_mac_address
238 * Change the interface's mac address.
239 * No special hardware thing should be done because interface is always
240 * put in promiscuous mode.
242 * Input : pointer to ethernet interface network device structure and
243 * a pointer to the designated entry to be added to the cache.
244 * Output : zero upon success, negative upon failure
246 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
250 for (i = 0; i < 6; i++)
251 /* +2 is for the offset of the HW addr type */
252 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
253 mv643xx_eth_update_mac_address(dev);
258 * mv643xx_eth_tx_timeout
260 * Called upon a timeout on transmitting a packet
262 * Input : pointer to ethernet interface network device structure.
265 static void mv643xx_eth_tx_timeout(struct net_device *dev)
267 struct mv643xx_private *mp = netdev_priv(dev);
269 printk(KERN_INFO "%s: TX timeout ", dev->name);
271 /* Do the reset outside of interrupt context */
272 schedule_work(&mp->tx_timeout_task);
276 * mv643xx_eth_tx_timeout_task
278 * Actual routine to reset the adapter when a timeout on Tx has occurred
280 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
282 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
284 struct net_device *dev = mp->mii.dev; /* yuck */
286 if (!netif_running(dev))
289 netif_stop_queue(dev);
291 eth_port_reset(mp->port_num);
294 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
295 netif_wake_queue(dev);
299 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
301 * If force is non-zero, frees uncompleted descriptors as well
303 int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
305 struct mv643xx_private *mp = netdev_priv(dev);
306 struct eth_tx_desc *desc;
315 while (mp->tx_desc_count > 0) {
316 spin_lock_irqsave(&mp->lock, flags);
318 /* tx_desc_count might have changed before acquiring the lock */
319 if (mp->tx_desc_count <= 0) {
320 spin_unlock_irqrestore(&mp->lock, flags);
324 tx_index = mp->tx_used_desc_q;
325 desc = &mp->p_tx_desc_area[tx_index];
326 cmd_sts = desc->cmd_sts;
328 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
329 spin_unlock_irqrestore(&mp->lock, flags);
333 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
336 addr = desc->buf_ptr;
337 count = desc->byte_cnt;
338 skb = mp->tx_skb[tx_index];
340 mp->tx_skb[tx_index] = NULL;
342 if (cmd_sts & ETH_ERROR_SUMMARY) {
343 printk("%s: Error in TX\n", dev->name);
344 mp->stats.tx_errors++;
347 spin_unlock_irqrestore(&mp->lock, flags);
349 if (cmd_sts & ETH_TX_FIRST_DESC)
350 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
352 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
355 dev_kfree_skb_irq(skb);
363 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
365 struct mv643xx_private *mp = netdev_priv(dev);
367 if (mv643xx_eth_free_tx_descs(dev, 0) &&
368 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
369 netif_wake_queue(dev);
372 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
374 mv643xx_eth_free_tx_descs(dev, 1);
378 * mv643xx_eth_receive
380 * This function is forward packets that are received from the port's
381 * queues toward kernel core or FastRoute them to another interface.
383 * Input : dev - a pointer to the required interface
384 * max - maximum number to receive (0 means unlimted)
386 * Output : number of served packets
388 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
390 struct mv643xx_private *mp = netdev_priv(dev);
391 struct net_device_stats *stats = &mp->stats;
392 unsigned int received_packets = 0;
394 struct pkt_info pkt_info;
396 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
397 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
404 * Note byte count includes 4 byte CRC count
407 stats->rx_bytes += pkt_info.byte_cnt;
408 skb = pkt_info.return_info;
410 * In case received a packet without first / last bits on OR
411 * the error summary bit is on, the packets needs to be dropeed.
413 if (((pkt_info.cmd_sts
414 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
415 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
416 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
418 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
419 ETH_RX_LAST_DESC)) !=
420 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
423 "%s: Received packet spread "
424 "on multiple descriptors\n",
427 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
430 dev_kfree_skb_irq(skb);
433 * The -4 is for the CRC in the trailer of the
436 skb_put(skb, pkt_info.byte_cnt - 4);
438 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
439 skb->ip_summed = CHECKSUM_UNNECESSARY;
441 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
443 skb->protocol = eth_type_trans(skb, dev);
445 netif_receive_skb(skb);
450 dev->last_rx = jiffies;
452 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
454 return received_packets;
457 /* Set the mv643xx port configuration register for the speed/duplex mode. */
458 static void mv643xx_eth_update_pscr(struct net_device *dev,
459 struct ethtool_cmd *ecmd)
461 struct mv643xx_private *mp = netdev_priv(dev);
462 int port_num = mp->port_num;
466 o_pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
469 /* clear speed, duplex and rx buffer size fields */
470 n_pscr &= ~(MV643XX_ETH_SET_MII_SPEED_TO_100 |
471 MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
472 MV643XX_ETH_SET_FULL_DUPLEX_MODE |
473 MV643XX_ETH_MAX_RX_PACKET_MASK);
475 if (ecmd->duplex == DUPLEX_FULL)
476 n_pscr |= MV643XX_ETH_SET_FULL_DUPLEX_MODE;
478 if (ecmd->speed == SPEED_1000)
479 n_pscr |= MV643XX_ETH_SET_GMII_SPEED_TO_1000 |
480 MV643XX_ETH_MAX_RX_PACKET_9700BYTE;
482 if (ecmd->speed == SPEED_100)
483 n_pscr |= MV643XX_ETH_SET_MII_SPEED_TO_100;
484 n_pscr |= MV643XX_ETH_MAX_RX_PACKET_1522BYTE;
487 if (n_pscr != o_pscr) {
488 if ((o_pscr & MV643XX_ETH_SERIAL_PORT_ENABLE) == 0)
489 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
492 queues = mv643xx_eth_port_disable_tx(port_num);
494 o_pscr &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
495 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
497 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
499 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
502 mv643xx_eth_port_enable_tx(port_num, queues);
508 * mv643xx_eth_int_handler
510 * Main interrupt handler for the gigbit ethernet ports
512 * Input : irq - irq number (not used)
513 * dev_id - a pointer to the required interface's data structure
518 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
520 struct net_device *dev = (struct net_device *)dev_id;
521 struct mv643xx_private *mp = netdev_priv(dev);
522 u32 eth_int_cause, eth_int_cause_ext = 0;
523 unsigned int port_num = mp->port_num;
525 /* Read interrupt cause registers */
526 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
528 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
529 eth_int_cause_ext = mv_read(
530 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
531 ETH_INT_UNMASK_ALL_EXT;
532 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num),
536 /* PHY status changed */
537 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
538 struct ethtool_cmd cmd;
540 if (mii_link_ok(&mp->mii)) {
541 mii_ethtool_gset(&mp->mii, &cmd);
542 mv643xx_eth_update_pscr(dev, &cmd);
543 mv643xx_eth_port_enable_tx(port_num,
544 ETH_TX_QUEUES_ENABLED);
545 if (!netif_carrier_ok(dev)) {
546 netif_carrier_on(dev);
547 if (mp->tx_ring_size - mp->tx_desc_count >=
549 netif_wake_queue(dev);
551 } else if (netif_carrier_ok(dev)) {
552 netif_stop_queue(dev);
553 netif_carrier_off(dev);
558 if (eth_int_cause & ETH_INT_CAUSE_RX) {
559 /* schedule the NAPI poll routine to maintain port */
560 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
562 /* wait for previous write to complete */
563 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
565 netif_rx_schedule(dev, &mp->napi);
568 if (eth_int_cause & ETH_INT_CAUSE_RX)
569 mv643xx_eth_receive_queue(dev, INT_MAX);
571 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
572 mv643xx_eth_free_completed_tx_descs(dev);
575 * If no real interrupt occured, exit.
576 * This can happen when using gigE interrupt coalescing mechanism.
578 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
587 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
590 * This routine sets the RX coalescing interrupt mechanism parameter.
591 * This parameter is a timeout counter, that counts in 64 t_clk
592 * chunks ; that when timeout event occurs a maskable interrupt
594 * The parameter is calculated using the tClk of the MV-643xx chip
595 * , and the required delay of the interrupt in usec.
598 * unsigned int eth_port_num Ethernet port number
599 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
600 * unsigned int delay Delay in usec
603 * Interrupt coalescing mechanism value is set in MV-643xx chip.
606 * The interrupt coalescing value set in the gigE port.
609 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
610 unsigned int t_clk, unsigned int delay)
612 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
614 /* Set RX Coalescing mechanism */
615 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
616 ((coal & 0x3fff) << 8) |
617 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
625 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
628 * This routine sets the TX coalescing interrupt mechanism parameter.
629 * This parameter is a timeout counter, that counts in 64 t_clk
630 * chunks ; that when timeout event occurs a maskable interrupt
632 * The parameter is calculated using the t_cLK frequency of the
633 * MV-643xx chip and the required delay in the interrupt in uSec
636 * unsigned int eth_port_num Ethernet port number
637 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
638 * unsigned int delay Delay in uSeconds
641 * Interrupt coalescing mechanism value is set in MV-643xx chip.
644 * The interrupt coalescing value set in the gigE port.
647 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
648 unsigned int t_clk, unsigned int delay)
651 coal = ((t_clk / 1000000) * delay) / 64;
652 /* Set TX Coalescing mechanism */
653 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
659 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
662 * This function prepares a Rx chained list of descriptors and packet
663 * buffers in a form of a ring. The routine must be called after port
664 * initialization routine and before port start routine.
665 * The Ethernet SDMA engine uses CPU bus addresses to access the various
666 * devices in the system (i.e. DRAM). This function uses the ethernet
667 * struct 'virtual to physical' routine (set by the user) to set the ring
668 * with physical addresses.
671 * struct mv643xx_private *mp Ethernet Port Control srtuct.
674 * The routine updates the Ethernet port control struct with information
675 * regarding the Rx descriptors and buffers.
680 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
682 volatile struct eth_rx_desc *p_rx_desc;
683 int rx_desc_num = mp->rx_ring_size;
686 /* initialize the next_desc_ptr links in the Rx descriptors ring */
687 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
688 for (i = 0; i < rx_desc_num; i++) {
689 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
690 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
693 /* Save Rx desc pointer to driver struct. */
694 mp->rx_curr_desc_q = 0;
695 mp->rx_used_desc_q = 0;
697 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
701 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
704 * This function prepares a Tx chained list of descriptors and packet
705 * buffers in a form of a ring. The routine must be called after port
706 * initialization routine and before port start routine.
707 * The Ethernet SDMA engine uses CPU bus addresses to access the various
708 * devices in the system (i.e. DRAM). This function uses the ethernet
709 * struct 'virtual to physical' routine (set by the user) to set the ring
710 * with physical addresses.
713 * struct mv643xx_private *mp Ethernet Port Control srtuct.
716 * The routine updates the Ethernet port control struct with information
717 * regarding the Tx descriptors and buffers.
722 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
724 int tx_desc_num = mp->tx_ring_size;
725 struct eth_tx_desc *p_tx_desc;
728 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
729 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
730 for (i = 0; i < tx_desc_num; i++) {
731 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
732 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
735 mp->tx_curr_desc_q = 0;
736 mp->tx_used_desc_q = 0;
738 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
741 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
743 struct mv643xx_private *mp = netdev_priv(dev);
746 spin_lock_irq(&mp->lock);
747 err = mii_ethtool_sset(&mp->mii, cmd);
748 spin_unlock_irq(&mp->lock);
753 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
755 struct mv643xx_private *mp = netdev_priv(dev);
758 spin_lock_irq(&mp->lock);
759 err = mii_ethtool_gset(&mp->mii, cmd);
760 spin_unlock_irq(&mp->lock);
762 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
763 cmd->supported &= ~SUPPORTED_1000baseT_Half;
764 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
772 * This function is called when openning the network device. The function
773 * should initialize all the hardware, initialize cyclic Rx/Tx
774 * descriptors chain and buffers and allocate an IRQ to the network
777 * Input : a pointer to the network device structure
779 * Output : zero of success , nonzero if fails.
782 static int mv643xx_eth_open(struct net_device *dev)
784 struct mv643xx_private *mp = netdev_priv(dev);
785 unsigned int port_num = mp->port_num;
789 /* Clear any pending ethernet port interrupts */
790 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
791 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
792 /* wait for previous write to complete */
793 mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num));
795 err = request_irq(dev->irq, mv643xx_eth_int_handler,
796 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
798 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
805 memset(&mp->timeout, 0, sizeof(struct timer_list));
806 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
807 mp->timeout.data = (unsigned long)dev;
809 /* Allocate RX and TX skb rings */
810 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
813 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
817 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
820 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
822 goto out_free_rx_skb;
825 /* Allocate TX ring */
826 mp->tx_desc_count = 0;
827 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
828 mp->tx_desc_area_size = size;
830 if (mp->tx_sram_size) {
831 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
833 mp->tx_desc_dma = mp->tx_sram_addr;
835 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
839 if (!mp->p_tx_desc_area) {
840 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
843 goto out_free_tx_skb;
845 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
846 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
848 ether_init_tx_desc_ring(mp);
850 /* Allocate RX ring */
851 mp->rx_desc_count = 0;
852 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
853 mp->rx_desc_area_size = size;
855 if (mp->rx_sram_size) {
856 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
858 mp->rx_desc_dma = mp->rx_sram_addr;
860 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
864 if (!mp->p_rx_desc_area) {
865 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
867 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
869 if (mp->rx_sram_size)
870 iounmap(mp->p_tx_desc_area);
872 dma_free_coherent(NULL, mp->tx_desc_area_size,
873 mp->p_tx_desc_area, mp->tx_desc_dma);
875 goto out_free_tx_skb;
877 memset((void *)mp->p_rx_desc_area, 0, size);
879 ether_init_rx_desc_ring(mp);
881 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
884 napi_enable(&mp->napi);
889 /* Interrupt Coalescing */
893 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
897 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
899 /* Unmask phy and link status changes interrupts */
900 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
901 ETH_INT_UNMASK_ALL_EXT);
903 /* Unmask RX buffer and TX end interrupt */
904 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
913 free_irq(dev->irq, dev);
918 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
920 struct mv643xx_private *mp = netdev_priv(dev);
923 mv643xx_eth_port_disable_tx(mp->port_num);
925 /* Free outstanding skb's on TX ring */
926 mv643xx_eth_free_all_tx_descs(dev);
928 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
931 if (mp->tx_sram_size)
932 iounmap(mp->p_tx_desc_area);
934 dma_free_coherent(NULL, mp->tx_desc_area_size,
935 mp->p_tx_desc_area, mp->tx_desc_dma);
938 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
940 struct mv643xx_private *mp = netdev_priv(dev);
941 unsigned int port_num = mp->port_num;
945 mv643xx_eth_port_disable_rx(port_num);
947 /* Free preallocated skb's on RX rings */
948 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
949 if (mp->rx_skb[curr]) {
950 dev_kfree_skb(mp->rx_skb[curr]);
955 if (mp->rx_desc_count)
957 "%s: Error in freeing Rx Ring. %d skb's still"
958 " stuck in RX Ring - ignoring them\n", dev->name,
961 if (mp->rx_sram_size)
962 iounmap(mp->p_rx_desc_area);
964 dma_free_coherent(NULL, mp->rx_desc_area_size,
965 mp->p_rx_desc_area, mp->rx_desc_dma);
971 * This function is used when closing the network device.
972 * It updates the hardware,
973 * release all memory that holds buffers and descriptors and release the IRQ.
974 * Input : a pointer to the device structure
975 * Output : zero if success , nonzero if fails
978 static int mv643xx_eth_stop(struct net_device *dev)
980 struct mv643xx_private *mp = netdev_priv(dev);
981 unsigned int port_num = mp->port_num;
983 /* Mask all interrupts on ethernet port */
984 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
985 /* wait for previous write to complete */
986 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
989 napi_disable(&mp->napi);
991 netif_carrier_off(dev);
992 netif_stop_queue(dev);
994 eth_port_reset(mp->port_num);
996 mv643xx_eth_free_tx_rings(dev);
997 mv643xx_eth_free_rx_rings(dev);
999 free_irq(dev->irq, dev);
1008 * This function is used in case of NAPI
1010 static int mv643xx_poll(struct napi_struct *napi, int budget)
1012 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
1013 struct net_device *dev = mp->dev;
1014 unsigned int port_num = mp->port_num;
1017 #ifdef MV643XX_TX_FAST_REFILL
1018 if (++mp->tx_clean_threshold > 5) {
1019 mv643xx_eth_free_completed_tx_descs(dev);
1020 mp->tx_clean_threshold = 0;
1025 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1026 != (u32) mp->rx_used_desc_q)
1027 work_done = mv643xx_eth_receive_queue(dev, budget);
1029 if (work_done < budget) {
1030 netif_rx_complete(dev, napi);
1031 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1032 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1033 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1034 ETH_INT_UNMASK_ALL);
1042 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1044 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1045 * This helper function detects that case.
1048 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1053 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1054 fragp = &skb_shinfo(skb)->frags[frag];
1055 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1062 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1064 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1068 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1070 tx_desc_curr = mp->tx_curr_desc_q;
1071 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1073 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1075 return tx_desc_curr;
1079 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1081 * Ensure the data for each fragment to be transmitted is mapped properly,
1082 * then fill in descriptors in the tx hw queue.
1084 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1085 struct sk_buff *skb)
1089 struct eth_tx_desc *desc;
1091 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1092 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1094 tx_index = eth_alloc_tx_desc_index(mp);
1095 desc = &mp->p_tx_desc_area[tx_index];
1097 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1098 /* Last Frag enables interrupt and frees the skb */
1099 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1100 desc->cmd_sts |= ETH_ZERO_PADDING |
1102 ETH_TX_ENABLE_INTERRUPT;
1103 mp->tx_skb[tx_index] = skb;
1105 mp->tx_skb[tx_index] = NULL;
1107 desc = &mp->p_tx_desc_area[tx_index];
1109 desc->byte_cnt = this_frag->size;
1110 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1111 this_frag->page_offset,
1118 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1120 * Ensure the data for an skb to be transmitted is mapped properly,
1121 * then fill in descriptors in the tx hw queue and start the hardware.
1123 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1124 struct sk_buff *skb)
1127 struct eth_tx_desc *desc;
1130 int nr_frags = skb_shinfo(skb)->nr_frags;
1132 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1134 tx_index = eth_alloc_tx_desc_index(mp);
1135 desc = &mp->p_tx_desc_area[tx_index];
1138 eth_tx_fill_frag_descs(mp, skb);
1140 length = skb_headlen(skb);
1141 mp->tx_skb[tx_index] = NULL;
1143 cmd_sts |= ETH_ZERO_PADDING |
1145 ETH_TX_ENABLE_INTERRUPT;
1147 mp->tx_skb[tx_index] = skb;
1150 desc->byte_cnt = length;
1151 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1153 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1154 BUG_ON(skb->protocol != ETH_P_IP);
1156 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1157 ETH_GEN_IP_V_4_CHECKSUM |
1158 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
1160 switch (ip_hdr(skb)->protocol) {
1162 cmd_sts |= ETH_UDP_FRAME;
1163 desc->l4i_chk = udp_hdr(skb)->check;
1166 desc->l4i_chk = tcp_hdr(skb)->check;
1172 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1173 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1177 /* ensure all other descriptors are written before first cmd_sts */
1179 desc->cmd_sts = cmd_sts;
1181 /* ensure all descriptors are written before poking hardware */
1183 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1185 mp->tx_desc_count += nr_frags + 1;
1189 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1192 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1194 struct mv643xx_private *mp = netdev_priv(dev);
1195 struct net_device_stats *stats = &mp->stats;
1196 unsigned long flags;
1198 BUG_ON(netif_queue_stopped(dev));
1199 BUG_ON(skb == NULL);
1201 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1202 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1203 netif_stop_queue(dev);
1207 if (has_tiny_unaligned_frags(skb)) {
1208 if (__skb_linearize(skb)) {
1209 stats->tx_dropped++;
1210 printk(KERN_DEBUG "%s: failed to linearize tiny "
1211 "unaligned fragment\n", dev->name);
1216 spin_lock_irqsave(&mp->lock, flags);
1218 eth_tx_submit_descs_for_skb(mp, skb);
1219 stats->tx_bytes += skb->len;
1220 stats->tx_packets++;
1221 dev->trans_start = jiffies;
1223 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1224 netif_stop_queue(dev);
1226 spin_unlock_irqrestore(&mp->lock, flags);
1228 return 0; /* success */
1232 * mv643xx_eth_get_stats
1234 * Returns a pointer to the interface statistics.
1236 * Input : dev - a pointer to the required interface
1238 * Output : a pointer to the interface's statistics
1241 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1243 struct mv643xx_private *mp = netdev_priv(dev);
1248 #ifdef CONFIG_NET_POLL_CONTROLLER
1249 static void mv643xx_netpoll(struct net_device *netdev)
1251 struct mv643xx_private *mp = netdev_priv(netdev);
1252 int port_num = mp->port_num;
1254 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1255 /* wait for previous write to complete */
1256 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1258 mv643xx_eth_int_handler(netdev->irq, netdev);
1260 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1264 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1265 int speed, int duplex,
1266 struct ethtool_cmd *cmd)
1268 struct mv643xx_private *mp = netdev_priv(dev);
1270 memset(cmd, 0, sizeof(*cmd));
1272 cmd->port = PORT_MII;
1273 cmd->transceiver = XCVR_INTERNAL;
1274 cmd->phy_address = phy_address;
1277 cmd->autoneg = AUTONEG_ENABLE;
1278 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1279 cmd->speed = SPEED_100;
1280 cmd->advertising = ADVERTISED_10baseT_Half |
1281 ADVERTISED_10baseT_Full |
1282 ADVERTISED_100baseT_Half |
1283 ADVERTISED_100baseT_Full;
1284 if (mp->mii.supports_gmii)
1285 cmd->advertising |= ADVERTISED_1000baseT_Full;
1287 cmd->autoneg = AUTONEG_DISABLE;
1289 cmd->duplex = duplex;
1296 * First function called after registering the network device.
1297 * It's purpose is to initialize the device as an ethernet device,
1298 * fill the ethernet device structure with pointers * to functions,
1299 * and set the MAC address of the interface
1301 * Input : struct device *
1302 * Output : -ENOMEM if failed , 0 if success
1304 static int mv643xx_eth_probe(struct platform_device *pdev)
1306 struct mv643xx_eth_platform_data *pd;
1308 struct mv643xx_private *mp;
1309 struct net_device *dev;
1311 struct resource *res;
1313 struct ethtool_cmd cmd;
1314 int duplex = DUPLEX_HALF;
1315 int speed = 0; /* default to auto-negotiation */
1317 pd = pdev->dev.platform_data;
1319 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
1323 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1327 platform_set_drvdata(pdev, dev);
1329 mp = netdev_priv(dev);
1332 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
1335 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1337 dev->irq = res->start;
1339 dev->open = mv643xx_eth_open;
1340 dev->stop = mv643xx_eth_stop;
1341 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1342 dev->get_stats = mv643xx_eth_get_stats;
1343 dev->set_mac_address = mv643xx_eth_set_mac_address;
1344 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1346 /* No need to Tx Timeout */
1347 dev->tx_timeout = mv643xx_eth_tx_timeout;
1349 #ifdef CONFIG_NET_POLL_CONTROLLER
1350 dev->poll_controller = mv643xx_netpoll;
1353 dev->watchdog_timeo = 2 * HZ;
1355 dev->change_mtu = mv643xx_eth_change_mtu;
1356 dev->do_ioctl = mv643xx_eth_do_ioctl;
1357 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1359 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1360 #ifdef MAX_SKB_FRAGS
1362 * Zero copy can only work if we use Discovery II memory. Else, we will
1363 * have to map the buffers to ISA memory which is only 16 MB
1365 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1369 /* Configure the timeout task */
1370 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1372 spin_lock_init(&mp->lock);
1374 port_num = mp->port_num = pd->port_number;
1376 /* set default config values */
1377 eth_port_uc_addr_get(port_num, dev->dev_addr);
1378 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1379 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1381 if (is_valid_ether_addr(pd->mac_addr))
1382 memcpy(dev->dev_addr, pd->mac_addr, 6);
1384 if (pd->phy_addr || pd->force_phy_addr)
1385 ethernet_phy_set(port_num, pd->phy_addr);
1387 if (pd->rx_queue_size)
1388 mp->rx_ring_size = pd->rx_queue_size;
1390 if (pd->tx_queue_size)
1391 mp->tx_ring_size = pd->tx_queue_size;
1393 if (pd->tx_sram_size) {
1394 mp->tx_sram_size = pd->tx_sram_size;
1395 mp->tx_sram_addr = pd->tx_sram_addr;
1398 if (pd->rx_sram_size) {
1399 mp->rx_sram_size = pd->rx_sram_size;
1400 mp->rx_sram_addr = pd->rx_sram_addr;
1403 duplex = pd->duplex;
1406 /* Hook up MII support for ethtool */
1408 mp->mii.mdio_read = mv643xx_mdio_read;
1409 mp->mii.mdio_write = mv643xx_mdio_write;
1410 mp->mii.phy_id = ethernet_phy_get(port_num);
1411 mp->mii.phy_id_mask = 0x3f;
1412 mp->mii.reg_num_mask = 0x1f;
1414 err = ethernet_phy_detect(port_num);
1416 pr_debug("MV643xx ethernet port %d: "
1417 "No PHY detected at addr %d\n",
1418 port_num, ethernet_phy_get(port_num));
1422 ethernet_phy_reset(port_num);
1423 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1424 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1425 mv643xx_eth_update_pscr(dev, &cmd);
1426 mv643xx_set_settings(dev, &cmd);
1428 SET_MODULE_OWNER(dev);
1429 SET_NETDEV_DEV(dev, &pdev->dev);
1430 err = register_netdev(dev);
1436 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1437 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1439 if (dev->features & NETIF_F_SG)
1440 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1442 if (dev->features & NETIF_F_IP_CSUM)
1443 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1446 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1447 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1451 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1456 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1459 if (mp->tx_sram_size > 0)
1460 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1470 static int mv643xx_eth_remove(struct platform_device *pdev)
1472 struct net_device *dev = platform_get_drvdata(pdev);
1474 unregister_netdev(dev);
1475 flush_scheduled_work();
1478 platform_set_drvdata(pdev, NULL);
1482 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1484 struct resource *res;
1486 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1492 mv643xx_eth_shared_base = ioremap(res->start,
1493 MV643XX_ETH_SHARED_REGS_SIZE);
1494 if (mv643xx_eth_shared_base == NULL)
1501 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1503 iounmap(mv643xx_eth_shared_base);
1504 mv643xx_eth_shared_base = NULL;
1509 static void mv643xx_eth_shutdown(struct platform_device *pdev)
1511 struct net_device *dev = platform_get_drvdata(pdev);
1512 struct mv643xx_private *mp = netdev_priv(dev);
1513 unsigned int port_num = mp->port_num;
1515 /* Mask all interrupts on ethernet port */
1516 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
1517 mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1519 eth_port_reset(port_num);
1522 static struct platform_driver mv643xx_eth_driver = {
1523 .probe = mv643xx_eth_probe,
1524 .remove = mv643xx_eth_remove,
1525 .shutdown = mv643xx_eth_shutdown,
1527 .name = MV643XX_ETH_NAME,
1531 static struct platform_driver mv643xx_eth_shared_driver = {
1532 .probe = mv643xx_eth_shared_probe,
1533 .remove = mv643xx_eth_shared_remove,
1535 .name = MV643XX_ETH_SHARED_NAME,
1540 * mv643xx_init_module
1542 * Registers the network drivers into the Linux kernel
1548 static int __init mv643xx_init_module(void)
1552 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1554 rc = platform_driver_register(&mv643xx_eth_driver);
1556 platform_driver_unregister(&mv643xx_eth_shared_driver);
1562 * mv643xx_cleanup_module
1564 * Registers the network drivers into the Linux kernel
1570 static void __exit mv643xx_cleanup_module(void)
1572 platform_driver_unregister(&mv643xx_eth_driver);
1573 platform_driver_unregister(&mv643xx_eth_shared_driver);
1576 module_init(mv643xx_init_module);
1577 module_exit(mv643xx_cleanup_module);
1579 MODULE_LICENSE("GPL");
1580 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1581 " and Dale Farnsworth");
1582 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1585 * The second part is the low level driver of the gigE ethernet ports.
1589 * Marvell's Gigabit Ethernet controller low level driver
1592 * This file introduce low level API to Marvell's Gigabit Ethernet
1593 * controller. This Gigabit Ethernet Controller driver API controls
1594 * 1) Operations (i.e. port init, start, reset etc').
1595 * 2) Data flow (i.e. port send, receive etc').
1596 * Each Gigabit Ethernet port is controlled via
1597 * struct mv643xx_private.
1598 * This struct includes user configuration information as well as
1599 * driver internal data needed for its operations.
1601 * Supported Features:
1602 * - This low level driver is OS independent. Allocating memory for
1603 * the descriptor rings and buffers are not within the scope of
1605 * - The user is free from Rx/Tx queue managing.
1606 * - This low level driver introduce functionality API that enable
1607 * the to operate Marvell's Gigabit Ethernet Controller in a
1609 * - Simple Gigabit Ethernet port operation API.
1610 * - Simple Gigabit Ethernet port data flow API.
1611 * - Data flow and operation API support per queue functionality.
1612 * - Support cached descriptors for better performance.
1613 * - Enable access to all four DRAM banks and internal SRAM memory
1615 * - PHY access and control API.
1616 * - Port control register configuration API.
1617 * - Full control over Unicast and Multicast MAC configurations.
1621 * Initialization phase
1622 * This phase complete the initialization of the the
1623 * mv643xx_private struct.
1624 * User information regarding port configuration has to be set
1625 * prior to calling the port initialization routine.
1627 * In this phase any port Tx/Rx activity is halted, MIB counters
1628 * are cleared, PHY address is set according to user parameter and
1629 * access to DRAM and internal SRAM memory spaces.
1631 * Driver ring initialization
1632 * Allocating memory for the descriptor rings and buffers is not
1633 * within the scope of this driver. Thus, the user is required to
1634 * allocate memory for the descriptors ring and buffers. Those
1635 * memory parameters are used by the Rx and Tx ring initialization
1636 * routines in order to curve the descriptor linked list in a form
1638 * Note: Pay special attention to alignment issues when using
1639 * cached descriptors/buffers. In this phase the driver store
1640 * information in the mv643xx_private struct regarding each queue
1644 * This phase prepares the Ethernet port for Rx and Tx activity.
1645 * It uses the information stored in the mv643xx_private struct to
1646 * initialize the various port registers.
1649 * All packet references to/from the driver are done using
1651 * This struct is a unified struct used with Rx and Tx operations.
1652 * This way the user is not required to be familiar with neither
1653 * Tx nor Rx descriptors structures.
1654 * The driver's descriptors rings are management by indexes.
1655 * Those indexes controls the ring resources and used to indicate
1656 * a SW resource error:
1658 * This index points to the current available resource for use. For
1659 * example in Rx process this index will point to the descriptor
1660 * that will be passed to the user upon calling the receive
1661 * routine. In Tx process, this index will point to the descriptor
1662 * that will be assigned with the user packet info and transmitted.
1664 * This index points to the descriptor that need to restore its
1665 * resources. For example in Rx process, using the Rx buffer return
1666 * API will attach the buffer returned in packet info to the
1667 * descriptor pointed by 'used'. In Tx process, using the Tx
1668 * descriptor return will merely return the user packet info with
1669 * the command status of the transmitted buffer pointed by the
1670 * 'used' index. Nevertheless, it is essential to use this routine
1671 * to update the 'used' index.
1673 * This index supports Tx Scatter-Gather. It points to the first
1674 * descriptor of a packet assembled of multiple buffers. For
1675 * example when in middle of Such packet we have a Tx resource
1676 * error the 'curr' index get the value of 'first' to indicate
1677 * that the ring returned to its state before trying to transmit
1680 * Receive operation:
1681 * The eth_port_receive API set the packet information struct,
1682 * passed by the caller, with received information from the
1683 * 'current' SDMA descriptor.
1684 * It is the user responsibility to return this resource back
1685 * to the Rx descriptor ring to enable the reuse of this source.
1686 * Return Rx resource is done using the eth_rx_return_buff API.
1688 * Prior to calling the initialization routine eth_port_init() the user
1689 * must set the following fields under mv643xx_private struct:
1690 * port_num User Ethernet port number.
1691 * port_config User port configuration value.
1692 * port_config_extend User port config extend value.
1693 * port_sdma_config User port SDMA config value.
1694 * port_serial_control User port serial control value.
1696 * This driver data flow is done using the struct pkt_info which
1697 * is a unified struct for Rx and Tx operations:
1699 * byte_cnt Tx/Rx descriptor buffer byte count.
1700 * l4i_chk CPU provided TCP Checksum. For Tx operation
1702 * cmd_sts Tx/Rx descriptor command status.
1703 * buf_ptr Tx/Rx descriptor buffer pointer.
1704 * return_info Tx/Rx user resource return information.
1708 static int ethernet_phy_get(unsigned int eth_port_num);
1709 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1711 /* Ethernet Port routines */
1712 static void eth_port_set_filter_table_entry(int table, unsigned char entry);
1715 * eth_port_init - Initialize the Ethernet port driver
1718 * This function prepares the ethernet port to start its activity:
1719 * 1) Completes the ethernet port driver struct initialization toward port
1721 * 2) Resets the device to a quiescent state in case of warm reboot.
1722 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1723 * 4) Clean MAC tables. The reset status of those tables is unknown.
1724 * 5) Set PHY address.
1725 * Note: Call this routine prior to eth_port_start routine and after
1726 * setting user values in the user fields of Ethernet port control
1730 * struct mv643xx_private *mp Ethernet port control struct
1738 static void eth_port_init(struct mv643xx_private *mp)
1740 mp->rx_resource_err = 0;
1742 eth_port_reset(mp->port_num);
1744 eth_port_init_mac_tables(mp->port_num);
1748 * eth_port_start - Start the Ethernet port activity.
1751 * This routine prepares the Ethernet port for Rx and Tx activity:
1752 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1753 * has been initialized a descriptor's ring (using
1754 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1755 * 2. Initialize and enable the Ethernet configuration port by writing to
1756 * the port's configuration and command registers.
1757 * 3. Initialize and enable the SDMA by writing to the SDMA's
1758 * configuration and command registers. After completing these steps,
1759 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1761 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1762 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1763 * and ether_init_rx_desc_ring for Rx queues).
1766 * dev - a pointer to the required interface
1769 * Ethernet port is ready to receive and transmit.
1774 static void eth_port_start(struct net_device *dev)
1776 struct mv643xx_private *mp = netdev_priv(dev);
1777 unsigned int port_num = mp->port_num;
1778 int tx_curr_desc, rx_curr_desc;
1780 struct ethtool_cmd ethtool_cmd;
1782 /* Assignment of Tx CTRP of given queue */
1783 tx_curr_desc = mp->tx_curr_desc_q;
1784 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1785 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1787 /* Assignment of Rx CRDP of given queue */
1788 rx_curr_desc = mp->rx_curr_desc_q;
1789 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1790 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1792 /* Add the assigned Ethernet address to the port's address table */
1793 eth_port_uc_addr_set(port_num, dev->dev_addr);
1795 /* Assign port configuration and command. */
1796 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num),
1797 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE);
1799 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1800 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE);
1802 pscr = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
1804 pscr &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE | MV643XX_ETH_FORCE_LINK_PASS);
1805 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1807 pscr |= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1808 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII |
1809 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX |
1810 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
1811 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED;
1813 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1815 pscr |= MV643XX_ETH_SERIAL_PORT_ENABLE;
1816 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), pscr);
1818 /* Assign port SDMA configuration */
1819 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1820 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE);
1822 /* Enable port Rx. */
1823 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
1825 /* Disable port bandwidth limits by clearing MTU register */
1826 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1828 /* save phy settings across reset */
1829 mv643xx_get_settings(dev, ðtool_cmd);
1830 ethernet_phy_reset(mp->port_num);
1831 mv643xx_set_settings(dev, ðtool_cmd);
1835 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1837 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
1843 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1844 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1847 mv_write(MV643XX_ETH_MAC_ADDR_LOW(port_num), mac_l);
1848 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(port_num), mac_h);
1850 /* Accept frames with this address */
1851 table = MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port_num);
1852 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
1856 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
1858 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
1863 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(port_num));
1864 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(port_num));
1866 p_addr[0] = (mac_h >> 24) & 0xff;
1867 p_addr[1] = (mac_h >> 16) & 0xff;
1868 p_addr[2] = (mac_h >> 8) & 0xff;
1869 p_addr[3] = mac_h & 0xff;
1870 p_addr[4] = (mac_l >> 8) & 0xff;
1871 p_addr[5] = mac_l & 0xff;
1875 * The entries in each table are indexed by a hash of a packet's MAC
1876 * address. One bit in each entry determines whether the packet is
1877 * accepted. There are 4 entries (each 8 bits wide) in each register
1878 * of the table. The bits in each entry are defined as follows:
1879 * 0 Accept=1, Drop=0
1880 * 3-1 Queue (ETH_Q0=0)
1883 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
1885 unsigned int table_reg;
1886 unsigned int tbl_offset;
1887 unsigned int reg_offset;
1889 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1890 reg_offset = entry % 4; /* Entry offset within the register */
1892 /* Set "accepts frame bit" at specified table entry */
1893 table_reg = mv_read(table + tbl_offset);
1894 table_reg |= 0x01 << (8 * reg_offset);
1895 mv_write(table + tbl_offset, table_reg);
1899 * eth_port_mc_addr - Multicast address settings.
1901 * The MV device supports multicast using two tables:
1902 * 1) Special Multicast Table for MAC addresses of the form
1903 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1904 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1905 * Table entries in the DA-Filter table.
1906 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1907 * is used as an index to the Other Multicast Table entries in the
1908 * DA-Filter table. This function calculates the CRC-8bit value.
1909 * In either case, eth_port_set_filter_table_entry() is then called
1910 * to set to set the actual table entry.
1912 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
1916 unsigned char crc_result = 0;
1922 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
1923 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
1924 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1926 eth_port_set_filter_table_entry(table, p_addr[5]);
1930 /* Calculate CRC-8 out of the given address */
1931 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1932 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1933 (p_addr[4] << 8) | (p_addr[5] << 0);
1935 for (i = 0; i < 32; i++)
1936 mac_array[i] = (mac_l >> i) & 0x1;
1937 for (i = 32; i < 48; i++)
1938 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1940 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1941 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1942 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1943 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1944 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1946 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1947 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1948 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1949 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1950 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1951 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1952 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1954 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1955 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1956 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1957 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1958 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1959 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1961 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1962 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1963 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1964 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1965 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1966 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1968 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1969 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1970 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1971 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1972 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1973 mac_array[3] ^ mac_array[2];
1975 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1976 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1977 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1978 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1979 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1980 mac_array[4] ^ mac_array[3];
1982 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1983 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1984 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1985 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1986 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1989 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1990 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1991 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1992 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1993 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1995 for (i = 0; i < 8; i++)
1996 crc_result = crc_result | (crc[i] << i);
1998 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
1999 eth_port_set_filter_table_entry(table, crc_result);
2003 * Set the entire multicast list based on dev->mc_list.
2005 static void eth_port_set_multicast_list(struct net_device *dev)
2008 struct dev_mc_list *mc_list;
2011 struct mv643xx_private *mp = netdev_priv(dev);
2012 unsigned int eth_port_num = mp->port_num;
2014 /* If the device is in promiscuous mode or in all multicast mode,
2015 * we will fully populate both multicast tables with accept.
2016 * This is guaranteed to yield a match on all multicast addresses...
2018 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2019 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2020 /* Set all entries in DA filter special multicast
2022 * Set for ETH_Q0 for now
2024 * 0 Accept=1, Drop=0
2025 * 3-1 Queue ETH_Q0=0
2028 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2030 /* Set all entries in DA filter other multicast
2032 * Set for ETH_Q0 for now
2034 * 0 Accept=1, Drop=0
2035 * 3-1 Queue ETH_Q0=0
2038 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2043 /* We will clear out multicast tables every time we get the list.
2044 * Then add the entire new list...
2046 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2047 /* Clear DA filter special multicast table (Ex_dFSMT) */
2048 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2049 (eth_port_num) + table_index, 0);
2051 /* Clear DA filter other multicast table (Ex_dFOMT) */
2052 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2053 (eth_port_num) + table_index, 0);
2056 /* Get pointer to net_device multicast list and add each one... */
2057 for (i = 0, mc_list = dev->mc_list;
2058 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2059 i++, mc_list = mc_list->next)
2060 if (mc_list->dmi_addrlen == 6)
2061 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2065 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2068 * Go through all the DA filter tables (Unicast, Special Multicast &
2069 * Other Multicast) and set each entry to 0.
2072 * unsigned int eth_port_num Ethernet Port number.
2075 * Multicast and Unicast packets are rejected.
2080 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2084 /* Clear DA filter unicast table (Ex_dFUT) */
2085 for (table_index = 0; table_index <= 0xC; table_index += 4)
2086 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2087 (eth_port_num) + table_index, 0);
2089 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2090 /* Clear DA filter special multicast table (Ex_dFSMT) */
2091 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2092 (eth_port_num) + table_index, 0);
2093 /* Clear DA filter other multicast table (Ex_dFOMT) */
2094 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2095 (eth_port_num) + table_index, 0);
2100 * eth_clear_mib_counters - Clear all MIB counters
2103 * This function clears all MIB counters of a specific ethernet port.
2104 * A read from the MIB counter will reset the counter.
2107 * unsigned int eth_port_num Ethernet Port number.
2110 * After reading all MIB counters, the counters resets.
2113 * MIB counter value.
2116 static void eth_clear_mib_counters(unsigned int eth_port_num)
2120 /* Perform dummy reads from MIB counters */
2121 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2123 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2126 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2128 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2131 static void eth_update_mib_counters(struct mv643xx_private *mp)
2133 struct mv643xx_mib_counters *p = &mp->mib_counters;
2136 p->good_octets_received +=
2137 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2138 p->good_octets_received +=
2139 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2141 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2142 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2144 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2146 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2147 p->good_octets_sent +=
2148 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2150 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2151 offset <= ETH_MIB_LATE_COLLISION;
2153 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2157 * ethernet_phy_detect - Detect whether a phy is present
2160 * This function tests whether there is a PHY present on
2161 * the specified port.
2164 * unsigned int eth_port_num Ethernet Port number.
2171 * -ENODEV on failure
2174 static int ethernet_phy_detect(unsigned int port_num)
2176 unsigned int phy_reg_data0;
2179 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2180 auto_neg = phy_reg_data0 & 0x1000;
2181 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2182 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2184 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2185 if ((phy_reg_data0 & 0x1000) == auto_neg)
2186 return -ENODEV; /* change didn't take */
2188 phy_reg_data0 ^= 0x1000;
2189 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2194 * ethernet_phy_get - Get the ethernet port PHY address.
2197 * This routine returns the given ethernet port PHY address.
2200 * unsigned int eth_port_num Ethernet Port number.
2209 static int ethernet_phy_get(unsigned int eth_port_num)
2211 unsigned int reg_data;
2213 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2215 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2219 * ethernet_phy_set - Set the ethernet port PHY address.
2222 * This routine sets the given ethernet port PHY address.
2225 * unsigned int eth_port_num Ethernet Port number.
2226 * int phy_addr PHY address.
2235 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2238 int addr_shift = 5 * eth_port_num;
2240 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2241 reg_data &= ~(0x1f << addr_shift);
2242 reg_data |= (phy_addr & 0x1f) << addr_shift;
2243 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2247 * ethernet_phy_reset - Reset Ethernet port PHY.
2250 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2253 * unsigned int eth_port_num Ethernet Port number.
2262 static void ethernet_phy_reset(unsigned int eth_port_num)
2264 unsigned int phy_reg_data;
2267 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2268 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2269 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2271 /* wait for PHY to come out of reset */
2274 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2275 } while (phy_reg_data & 0x8000);
2278 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2279 unsigned int queues)
2281 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
2284 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2285 unsigned int queues)
2287 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
2290 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2294 /* Stop Tx port activity. Check port Tx activity. */
2295 queues = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2298 /* Issue stop command for active queues only */
2299 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2302 /* Wait for all Tx activity to terminate. */
2303 /* Check port cause register that all Tx queues are stopped */
2304 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2306 udelay(PHY_WAIT_MICRO_SECONDS);
2308 /* Wait for Tx FIFO to empty */
2309 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num)) &
2310 ETH_PORT_TX_FIFO_EMPTY)
2311 udelay(PHY_WAIT_MICRO_SECONDS);
2317 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2321 /* Stop Rx port activity. Check port Rx activity. */
2322 queues = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2325 /* Issue stop command for active queues only */
2326 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2329 /* Wait for all Rx activity to terminate. */
2330 /* Check port cause register that all Rx queues are stopped */
2331 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2333 udelay(PHY_WAIT_MICRO_SECONDS);
2340 * eth_port_reset - Reset Ethernet port
2343 * This routine resets the chip by aborting any SDMA engine activity and
2344 * clearing the MIB counters. The Receiver and the Transmit unit are in
2345 * idle state after this command is performed and the port is disabled.
2348 * unsigned int eth_port_num Ethernet Port number.
2351 * Channel activity is halted.
2357 static void eth_port_reset(unsigned int port_num)
2359 unsigned int reg_data;
2361 mv643xx_eth_port_disable_tx(port_num);
2362 mv643xx_eth_port_disable_rx(port_num);
2364 /* Clear all MIB counters */
2365 eth_clear_mib_counters(port_num);
2367 /* Reset the Enable bit in the Configuration Register */
2368 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2369 reg_data &= ~(MV643XX_ETH_SERIAL_PORT_ENABLE |
2370 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL |
2371 MV643XX_ETH_FORCE_LINK_PASS);
2372 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2377 * eth_port_read_smi_reg - Read PHY registers
2380 * This routine utilize the SMI interface to interact with the PHY in
2381 * order to perform PHY register read.
2384 * unsigned int port_num Ethernet Port number.
2385 * unsigned int phy_reg PHY register address offset.
2386 * unsigned int *value Register value buffer.
2389 * Write the value of a specified PHY register into given buffer.
2392 * false if the PHY is busy or read data is not in valid state.
2396 static void eth_port_read_smi_reg(unsigned int port_num,
2397 unsigned int phy_reg, unsigned int *value)
2399 int phy_addr = ethernet_phy_get(port_num);
2400 unsigned long flags;
2403 /* the SMI register is a shared resource */
2404 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2406 /* wait for the SMI register to become available */
2407 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2408 if (i == PHY_WAIT_ITERATIONS) {
2409 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2412 udelay(PHY_WAIT_MICRO_SECONDS);
2415 mv_write(MV643XX_ETH_SMI_REG,
2416 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2418 /* now wait for the data to be valid */
2419 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2420 if (i == PHY_WAIT_ITERATIONS) {
2421 printk("mv643xx PHY read timeout, port %d\n", port_num);
2424 udelay(PHY_WAIT_MICRO_SECONDS);
2427 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2429 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2433 * eth_port_write_smi_reg - Write to PHY registers
2436 * This routine utilize the SMI interface to interact with the PHY in
2437 * order to perform writes to PHY registers.
2440 * unsigned int eth_port_num Ethernet Port number.
2441 * unsigned int phy_reg PHY register address offset.
2442 * unsigned int value Register value.
2445 * Write the given value to the specified PHY register.
2448 * false if the PHY is busy.
2452 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2453 unsigned int phy_reg, unsigned int value)
2457 unsigned long flags;
2459 phy_addr = ethernet_phy_get(eth_port_num);
2461 /* the SMI register is a shared resource */
2462 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2464 /* wait for the SMI register to become available */
2465 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2466 if (i == PHY_WAIT_ITERATIONS) {
2467 printk("mv643xx PHY busy timeout, port %d\n",
2471 udelay(PHY_WAIT_MICRO_SECONDS);
2474 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2475 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2477 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2481 * Wrappers for MII support library.
2483 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
2486 struct mv643xx_private *mp = netdev_priv(dev);
2488 eth_port_read_smi_reg(mp->port_num, location, &val);
2492 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
2494 struct mv643xx_private *mp = netdev_priv(dev);
2495 eth_port_write_smi_reg(mp->port_num, location, val);
2499 * eth_port_receive - Get received information from Rx ring.
2502 * This routine returns the received data to the caller. There is no
2503 * data copying during routine operation. All information is returned
2504 * using pointer to packet information struct passed from the caller.
2505 * If the routine exhausts Rx ring resources then the resource error flag
2509 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2510 * struct pkt_info *p_pkt_info User packet buffer.
2513 * Rx ring current and used indexes are updated.
2516 * ETH_ERROR in case the routine can not access Rx desc ring.
2517 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2518 * ETH_END_OF_JOB if there is no received data.
2521 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2522 struct pkt_info *p_pkt_info)
2524 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2525 volatile struct eth_rx_desc *p_rx_desc;
2526 unsigned int command_status;
2527 unsigned long flags;
2529 /* Do not process Rx ring in case of Rx ring resource error */
2530 if (mp->rx_resource_err)
2531 return ETH_QUEUE_FULL;
2533 spin_lock_irqsave(&mp->lock, flags);
2535 /* Get the Rx Desc ring 'curr and 'used' indexes */
2536 rx_curr_desc = mp->rx_curr_desc_q;
2537 rx_used_desc = mp->rx_used_desc_q;
2539 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2541 /* The following parameters are used to save readings from memory */
2542 command_status = p_rx_desc->cmd_sts;
2545 /* Nothing to receive... */
2546 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2547 spin_unlock_irqrestore(&mp->lock, flags);
2548 return ETH_END_OF_JOB;
2551 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2552 p_pkt_info->cmd_sts = command_status;
2553 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2554 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2555 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2558 * Clean the return info field to indicate that the
2559 * packet has been moved to the upper layers
2561 mp->rx_skb[rx_curr_desc] = NULL;
2563 /* Update current index in data structure */
2564 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2565 mp->rx_curr_desc_q = rx_next_curr_desc;
2567 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2568 if (rx_next_curr_desc == rx_used_desc)
2569 mp->rx_resource_err = 1;
2571 spin_unlock_irqrestore(&mp->lock, flags);
2577 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2580 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2581 * next 'used' descriptor and attached the returned buffer to it.
2582 * In case the Rx ring was in "resource error" condition, where there are
2583 * no available Rx resources, the function resets the resource error flag.
2586 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2587 * struct pkt_info *p_pkt_info Information on returned buffer.
2590 * New available Rx resource in Rx descriptor ring.
2593 * ETH_ERROR in case the routine can not access Rx desc ring.
2596 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2597 struct pkt_info *p_pkt_info)
2599 int used_rx_desc; /* Where to return Rx resource */
2600 volatile struct eth_rx_desc *p_used_rx_desc;
2601 unsigned long flags;
2603 spin_lock_irqsave(&mp->lock, flags);
2605 /* Get 'used' Rx descriptor */
2606 used_rx_desc = mp->rx_used_desc_q;
2607 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2609 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2610 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2611 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2613 /* Flush the write pipe */
2615 /* Return the descriptor to DMA ownership */
2617 p_used_rx_desc->cmd_sts =
2618 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2621 /* Move the used descriptor pointer to the next descriptor */
2622 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2624 /* Any Rx return cancels the Rx resource error status */
2625 mp->rx_resource_err = 0;
2627 spin_unlock_irqrestore(&mp->lock, flags);
2632 /************* Begin ethtool support *************************/
2634 struct mv643xx_stats {
2635 char stat_string[ETH_GSTRING_LEN];
2640 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2641 offsetof(struct mv643xx_private, m)
2643 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2644 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2645 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2646 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2647 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2648 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2649 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2650 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2651 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2652 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2653 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2654 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2655 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2656 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2657 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2658 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2659 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2660 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2661 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2662 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2663 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2664 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2665 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2666 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2667 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2668 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2669 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2670 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2671 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2672 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
2673 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
2674 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
2675 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
2676 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
2677 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
2678 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
2679 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
2680 { "collision", MV643XX_STAT(mib_counters.collision) },
2681 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
2684 #define MV643XX_STATS_LEN \
2685 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2687 static void mv643xx_get_drvinfo(struct net_device *netdev,
2688 struct ethtool_drvinfo *drvinfo)
2690 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
2691 strncpy(drvinfo->version, mv643xx_driver_version, 32);
2692 strncpy(drvinfo->fw_version, "N/A", 32);
2693 strncpy(drvinfo->bus_info, "mv643xx", 32);
2694 drvinfo->n_stats = MV643XX_STATS_LEN;
2697 static int mv643xx_get_stats_count(struct net_device *netdev)
2699 return MV643XX_STATS_LEN;
2702 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
2703 struct ethtool_stats *stats, uint64_t *data)
2705 struct mv643xx_private *mp = netdev->priv;
2708 eth_update_mib_counters(mp);
2710 for (i = 0; i < MV643XX_STATS_LEN; i++) {
2711 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
2712 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
2713 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
2717 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
2724 for (i=0; i < MV643XX_STATS_LEN; i++) {
2725 memcpy(data + i * ETH_GSTRING_LEN,
2726 mv643xx_gstrings_stats[i].stat_string,
2733 static u32 mv643xx_eth_get_link(struct net_device *dev)
2735 struct mv643xx_private *mp = netdev_priv(dev);
2737 return mii_link_ok(&mp->mii);
2740 static int mv643xx_eth_nway_restart(struct net_device *dev)
2742 struct mv643xx_private *mp = netdev_priv(dev);
2744 return mii_nway_restart(&mp->mii);
2747 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2749 struct mv643xx_private *mp = netdev_priv(dev);
2751 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2754 static const struct ethtool_ops mv643xx_ethtool_ops = {
2755 .get_settings = mv643xx_get_settings,
2756 .set_settings = mv643xx_set_settings,
2757 .get_drvinfo = mv643xx_get_drvinfo,
2758 .get_link = mv643xx_eth_get_link,
2759 .get_sg = ethtool_op_get_sg,
2760 .set_sg = ethtool_op_set_sg,
2761 .get_stats_count = mv643xx_get_stats_count,
2762 .get_ethtool_stats = mv643xx_get_ethtool_stats,
2763 .get_strings = mv643xx_get_strings,
2764 .nway_reset = mv643xx_eth_nway_restart,
2767 /************* End ethtool support *************************/