2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
43 #include <linux/mlx4/device.h>
44 #include <linux/mlx4/doorbell.h>
50 MODULE_AUTHOR("Roland Dreier");
51 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
52 MODULE_LICENSE("Dual BSD/GPL");
53 MODULE_VERSION(DRV_VERSION);
55 struct workqueue_struct *mlx4_wq;
57 #ifdef CONFIG_MLX4_DEBUG
59 int mlx4_debug_level = 0;
60 module_param_named(debug_level, mlx4_debug_level, int, 0644);
61 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
63 #endif /* CONFIG_MLX4_DEBUG */
68 module_param(msi_x, int, 0444);
69 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
71 #else /* CONFIG_PCI_MSI */
75 #endif /* CONFIG_PCI_MSI */
77 static char mlx4_version[] __devinitdata =
78 DRV_NAME ": Mellanox ConnectX core driver v"
79 DRV_VERSION " (" DRV_RELDATE ")\n";
81 static struct mlx4_profile default_profile = {
84 .rdmarc_per_qp = 1 << 4,
91 static int log_num_mac = 2;
92 module_param_named(log_num_mac, log_num_mac, int, 0444);
93 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
95 static int log_num_vlan;
96 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
97 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
100 module_param_named(use_prio, use_prio, bool, 0444);
101 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
104 static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
105 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
106 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
108 int mlx4_check_port_params(struct mlx4_dev *dev,
109 enum mlx4_port_type *port_type)
113 for (i = 0; i < dev->caps.num_ports - 1; i++) {
114 if (port_type[i] != port_type[i + 1]) {
115 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
116 mlx4_err(dev, "Only same port types supported "
117 "on this HCA, aborting.\n");
120 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
121 port_type[i + 1] == MLX4_PORT_TYPE_IB)
126 for (i = 0; i < dev->caps.num_ports; i++) {
127 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
128 mlx4_err(dev, "Requested port type for port %d is not "
129 "supported on this HCA\n", i + 1);
136 static void mlx4_set_port_mask(struct mlx4_dev *dev)
140 dev->caps.port_mask = 0;
141 for (i = 1; i <= dev->caps.num_ports; ++i)
142 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
143 dev->caps.port_mask |= 1 << (i - 1);
145 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
150 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
152 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
156 if (dev_cap->min_page_sz > PAGE_SIZE) {
157 mlx4_err(dev, "HCA minimum page size of %d bigger than "
158 "kernel PAGE_SIZE of %ld, aborting.\n",
159 dev_cap->min_page_sz, PAGE_SIZE);
162 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
163 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
165 dev_cap->num_ports, MLX4_MAX_PORTS);
169 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
170 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
171 "PCI resource 2 size of 0x%llx, aborting.\n",
173 (unsigned long long) pci_resource_len(dev->pdev, 2));
177 dev->caps.num_ports = dev_cap->num_ports;
178 for (i = 1; i <= dev->caps.num_ports; ++i) {
179 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
180 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
181 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
182 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
183 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
184 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
185 dev->caps.def_mac[i] = dev_cap->def_mac[i];
186 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
187 dev->caps.trans_type[i] = dev_cap->trans_type[i];
188 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
189 dev->caps.wavelength[i] = dev_cap->wavelength[i];
190 dev->caps.trans_code[i] = dev_cap->trans_code[i];
193 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
194 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
195 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
196 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
197 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
198 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
199 dev->caps.max_wqes = dev_cap->max_qp_sz;
200 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
201 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
202 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
203 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
204 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
205 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
206 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
208 * Subtract 1 from the limit because we need to allocate a
209 * spare CQE so the HCA HW can tell the difference between an
210 * empty CQ and a full CQ.
212 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
213 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
214 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
215 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
216 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
217 dev->caps.mtts_per_seg);
218 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
219 dev->caps.reserved_uars = dev_cap->reserved_uars;
220 dev->caps.reserved_pds = dev_cap->reserved_pds;
221 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
222 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
223 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
224 dev->caps.flags = dev_cap->flags;
225 dev->caps.bmme_flags = dev_cap->bmme_flags;
226 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
227 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
228 dev->caps.udp_rss = dev_cap->udp_rss;
229 dev->caps.loopback_support = dev_cap->loopback_support;
230 dev->caps.vep_uc_steering = dev_cap->vep_uc_steering;
231 dev->caps.vep_mc_steering = dev_cap->vep_mc_steering;
232 dev->caps.wol = dev_cap->wol;
233 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
235 dev->caps.log_num_macs = log_num_mac;
236 dev->caps.log_num_vlans = log_num_vlan;
237 dev->caps.log_num_prios = use_prio ? 3 : 0;
239 for (i = 1; i <= dev->caps.num_ports; ++i) {
240 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
241 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
243 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
244 dev->caps.possible_type[i] = dev->caps.port_type[i];
245 mlx4_priv(dev)->sense.sense_allowed[i] =
246 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
248 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
249 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
250 mlx4_warn(dev, "Requested number of MACs is too much "
251 "for port %d, reducing to %d.\n",
252 i, 1 << dev->caps.log_num_macs);
254 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
255 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
256 mlx4_warn(dev, "Requested number of VLANs is too much "
257 "for port %d, reducing to %d.\n",
258 i, 1 << dev->caps.log_num_vlans);
262 mlx4_set_port_mask(dev);
264 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
265 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
266 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
267 (1 << dev->caps.log_num_macs) *
268 (1 << dev->caps.log_num_vlans) *
269 (1 << dev->caps.log_num_prios) *
271 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
273 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
274 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
275 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
276 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
282 * Change the port configuration of the device.
283 * Every user of this function must hold the port mutex.
285 int mlx4_change_port_types(struct mlx4_dev *dev,
286 enum mlx4_port_type *port_types)
292 for (port = 0; port < dev->caps.num_ports; port++) {
293 /* Change the port type only if the new type is different
294 * from the current, and not set to Auto */
295 if (port_types[port] != dev->caps.port_type[port + 1]) {
297 dev->caps.port_type[port + 1] = port_types[port];
301 mlx4_unregister_device(dev);
302 for (port = 1; port <= dev->caps.num_ports; port++) {
303 mlx4_CLOSE_PORT(dev, port);
304 err = mlx4_SET_PORT(dev, port);
306 mlx4_err(dev, "Failed to set port %d, "
311 mlx4_set_port_mask(dev);
312 err = mlx4_register_device(dev);
319 static ssize_t show_port_type(struct device *dev,
320 struct device_attribute *attr,
323 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
325 struct mlx4_dev *mdev = info->dev;
329 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
331 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
332 sprintf(buf, "auto (%s)\n", type);
334 sprintf(buf, "%s\n", type);
339 static ssize_t set_port_type(struct device *dev,
340 struct device_attribute *attr,
341 const char *buf, size_t count)
343 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
345 struct mlx4_dev *mdev = info->dev;
346 struct mlx4_priv *priv = mlx4_priv(mdev);
347 enum mlx4_port_type types[MLX4_MAX_PORTS];
348 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
352 if (!strcmp(buf, "ib\n"))
353 info->tmp_type = MLX4_PORT_TYPE_IB;
354 else if (!strcmp(buf, "eth\n"))
355 info->tmp_type = MLX4_PORT_TYPE_ETH;
356 else if (!strcmp(buf, "auto\n"))
357 info->tmp_type = MLX4_PORT_TYPE_AUTO;
359 mlx4_err(mdev, "%s is not supported port type\n", buf);
363 mlx4_stop_sense(mdev);
364 mutex_lock(&priv->port_mutex);
365 /* Possible type is always the one that was delivered */
366 mdev->caps.possible_type[info->port] = info->tmp_type;
368 for (i = 0; i < mdev->caps.num_ports; i++) {
369 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
370 mdev->caps.possible_type[i+1];
371 if (types[i] == MLX4_PORT_TYPE_AUTO)
372 types[i] = mdev->caps.port_type[i+1];
375 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
376 for (i = 1; i <= mdev->caps.num_ports; i++) {
377 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
378 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
384 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
385 "Set only 'eth' or 'ib' for both ports "
386 "(should be the same)\n");
390 mlx4_do_sense_ports(mdev, new_types, types);
392 err = mlx4_check_port_params(mdev, new_types);
396 /* We are about to apply the changes after the configuration
397 * was verified, no need to remember the temporary types
399 for (i = 0; i < mdev->caps.num_ports; i++)
400 priv->port[i + 1].tmp_type = 0;
402 err = mlx4_change_port_types(mdev, new_types);
405 mlx4_start_sense(mdev);
406 mutex_unlock(&priv->port_mutex);
407 return err ? err : count;
410 static int mlx4_load_fw(struct mlx4_dev *dev)
412 struct mlx4_priv *priv = mlx4_priv(dev);
415 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
416 GFP_HIGHUSER | __GFP_NOWARN, 0);
417 if (!priv->fw.fw_icm) {
418 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
422 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
424 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
428 err = mlx4_RUN_FW(dev);
430 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
440 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
444 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
447 struct mlx4_priv *priv = mlx4_priv(dev);
450 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
452 ((u64) (MLX4_CMPT_TYPE_QP *
453 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
454 cmpt_entry_sz, dev->caps.num_qps,
455 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
460 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
462 ((u64) (MLX4_CMPT_TYPE_SRQ *
463 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
464 cmpt_entry_sz, dev->caps.num_srqs,
465 dev->caps.reserved_srqs, 0, 0);
469 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
471 ((u64) (MLX4_CMPT_TYPE_CQ *
472 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
473 cmpt_entry_sz, dev->caps.num_cqs,
474 dev->caps.reserved_cqs, 0, 0);
478 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
480 ((u64) (MLX4_CMPT_TYPE_EQ *
481 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
483 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
490 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
493 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
496 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
502 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
503 struct mlx4_init_hca_param *init_hca, u64 icm_size)
505 struct mlx4_priv *priv = mlx4_priv(dev);
509 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
511 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
515 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
516 (unsigned long long) icm_size >> 10,
517 (unsigned long long) aux_pages << 2);
519 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
520 GFP_HIGHUSER | __GFP_NOWARN, 0);
521 if (!priv->fw.aux_icm) {
522 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
526 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
528 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
532 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
534 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
538 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
539 init_hca->eqc_base, dev_cap->eqc_entry_sz,
540 dev->caps.num_eqs, dev->caps.num_eqs,
543 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
548 * Reserved MTT entries must be aligned up to a cacheline
549 * boundary, since the FW will write to them, while the driver
550 * writes to all other MTT entries. (The variable
551 * dev->caps.mtt_entry_sz below is really the MTT segment
552 * size, not the raw entry size)
554 dev->caps.reserved_mtts =
555 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
556 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
558 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
560 dev->caps.mtt_entry_sz,
561 dev->caps.num_mtt_segs,
562 dev->caps.reserved_mtts, 1, 0);
564 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
568 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
570 dev_cap->dmpt_entry_sz,
572 dev->caps.reserved_mrws, 1, 1);
574 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
578 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
580 dev_cap->qpc_entry_sz,
582 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
585 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
589 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
591 dev_cap->aux_entry_sz,
593 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
596 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
600 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
602 dev_cap->altc_entry_sz,
604 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
607 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
611 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
612 init_hca->rdmarc_base,
613 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
615 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
618 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
622 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
624 dev_cap->cqc_entry_sz,
626 dev->caps.reserved_cqs, 0, 0);
628 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
629 goto err_unmap_rdmarc;
632 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
634 dev_cap->srq_entry_sz,
636 dev->caps.reserved_srqs, 0, 0);
638 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
643 * It's not strictly required, but for simplicity just map the
644 * whole multicast group table now. The table isn't very big
645 * and it's a lot easier than trying to track ref counts.
647 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
648 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
649 dev->caps.num_mgms + dev->caps.num_amgms,
650 dev->caps.num_mgms + dev->caps.num_amgms,
653 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
660 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
663 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
666 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
669 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
672 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
675 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
678 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
681 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
684 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
687 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
688 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
689 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
690 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
693 mlx4_UNMAP_ICM_AUX(dev);
696 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
701 static void mlx4_free_icms(struct mlx4_dev *dev)
703 struct mlx4_priv *priv = mlx4_priv(dev);
705 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
706 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
707 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
708 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
709 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
710 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
711 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
712 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
713 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
714 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
715 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
716 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
717 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
718 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
720 mlx4_UNMAP_ICM_AUX(dev);
721 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
724 static void mlx4_close_hca(struct mlx4_dev *dev)
726 mlx4_CLOSE_HCA(dev, 0);
729 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
732 static int mlx4_init_hca(struct mlx4_dev *dev)
734 struct mlx4_priv *priv = mlx4_priv(dev);
735 struct mlx4_adapter adapter;
736 struct mlx4_dev_cap dev_cap;
737 struct mlx4_mod_stat_cfg mlx4_cfg;
738 struct mlx4_profile profile;
739 struct mlx4_init_hca_param init_hca;
743 err = mlx4_QUERY_FW(dev);
746 mlx4_info(dev, "non-primary physical function, skipping.\n");
748 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
752 err = mlx4_load_fw(dev);
754 mlx4_err(dev, "Failed to start FW, aborting.\n");
758 mlx4_cfg.log_pg_sz_m = 1;
759 mlx4_cfg.log_pg_sz = 0;
760 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
762 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
764 err = mlx4_dev_cap(dev, &dev_cap);
766 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
770 profile = default_profile;
772 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
773 if ((long long) icm_size < 0) {
778 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
780 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
784 err = mlx4_INIT_HCA(dev, &init_hca);
786 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
790 err = mlx4_QUERY_ADAPTER(dev, &adapter);
792 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
796 priv->eq_table.inta_pin = adapter.inta_pin;
797 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
802 mlx4_CLOSE_HCA(dev, 0);
809 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
814 static int mlx4_setup_hca(struct mlx4_dev *dev)
816 struct mlx4_priv *priv = mlx4_priv(dev);
819 __be32 ib_port_default_caps;
821 err = mlx4_init_uar_table(dev);
823 mlx4_err(dev, "Failed to initialize "
824 "user access region table, aborting.\n");
828 err = mlx4_uar_alloc(dev, &priv->driver_uar);
830 mlx4_err(dev, "Failed to allocate driver access region, "
832 goto err_uar_table_free;
835 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
837 mlx4_err(dev, "Couldn't map kernel access region, "
843 err = mlx4_init_pd_table(dev);
845 mlx4_err(dev, "Failed to initialize "
846 "protection domain table, aborting.\n");
850 err = mlx4_init_mr_table(dev);
852 mlx4_err(dev, "Failed to initialize "
853 "memory region table, aborting.\n");
854 goto err_pd_table_free;
857 err = mlx4_init_eq_table(dev);
859 mlx4_err(dev, "Failed to initialize "
860 "event queue table, aborting.\n");
861 goto err_mr_table_free;
864 err = mlx4_cmd_use_events(dev);
866 mlx4_err(dev, "Failed to switch to event-driven "
867 "firmware commands, aborting.\n");
868 goto err_eq_table_free;
873 if (dev->flags & MLX4_FLAG_MSI_X) {
874 mlx4_warn(dev, "NOP command failed to generate MSI-X "
875 "interrupt IRQ %d).\n",
876 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
877 mlx4_warn(dev, "Trying again without MSI-X.\n");
879 mlx4_err(dev, "NOP command failed to generate interrupt "
880 "(IRQ %d), aborting.\n",
881 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
882 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
888 mlx4_dbg(dev, "NOP command IRQ test passed\n");
890 err = mlx4_init_cq_table(dev);
892 mlx4_err(dev, "Failed to initialize "
893 "completion queue table, aborting.\n");
897 err = mlx4_init_srq_table(dev);
899 mlx4_err(dev, "Failed to initialize "
900 "shared receive queue table, aborting.\n");
901 goto err_cq_table_free;
904 err = mlx4_init_qp_table(dev);
906 mlx4_err(dev, "Failed to initialize "
907 "queue pair table, aborting.\n");
908 goto err_srq_table_free;
911 err = mlx4_init_mcg_table(dev);
913 mlx4_err(dev, "Failed to initialize "
914 "multicast group table, aborting.\n");
915 goto err_qp_table_free;
918 for (port = 1; port <= dev->caps.num_ports; port++) {
919 ib_port_default_caps = 0;
920 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
922 mlx4_warn(dev, "failed to get port %d default "
923 "ib capabilities (%d). Continuing with "
924 "caps = 0\n", port, err);
925 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
926 err = mlx4_SET_PORT(dev, port);
928 mlx4_err(dev, "Failed to set port %d, aborting\n",
930 goto err_mcg_table_free;
937 mlx4_cleanup_mcg_table(dev);
940 mlx4_cleanup_qp_table(dev);
943 mlx4_cleanup_srq_table(dev);
946 mlx4_cleanup_cq_table(dev);
949 mlx4_cmd_use_polling(dev);
952 mlx4_cleanup_eq_table(dev);
955 mlx4_cleanup_mr_table(dev);
958 mlx4_cleanup_pd_table(dev);
964 mlx4_uar_free(dev, &priv->driver_uar);
967 mlx4_cleanup_uar_table(dev);
971 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
973 struct mlx4_priv *priv = mlx4_priv(dev);
974 struct msix_entry *entries;
975 int nreq = min_t(int, dev->caps.num_ports *
976 min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
977 + MSIX_LEGACY_SZ, MAX_MSIX);
982 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
984 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
988 for (i = 0; i < nreq; ++i)
989 entries[i].entry = i;
992 err = pci_enable_msix(dev->pdev, entries, nreq);
994 /* Try again if at least 2 vectors are available */
996 mlx4_info(dev, "Requested %d vectors, "
997 "but only %d MSI-X vectors available, "
998 "trying again\n", nreq, err);
1007 MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1008 /*Working in legacy mode , all EQ's shared*/
1009 dev->caps.comp_pool = 0;
1010 dev->caps.num_comp_vectors = nreq - 1;
1012 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
1013 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1015 for (i = 0; i < nreq; ++i)
1016 priv->eq_table.eq[i].irq = entries[i].vector;
1018 dev->flags |= MLX4_FLAG_MSI_X;
1025 dev->caps.num_comp_vectors = 1;
1026 dev->caps.comp_pool = 0;
1028 for (i = 0; i < 2; ++i)
1029 priv->eq_table.eq[i].irq = dev->pdev->irq;
1032 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1034 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1039 mlx4_init_mac_table(dev, &info->mac_table);
1040 mlx4_init_vlan_table(dev, &info->vlan_table);
1042 sprintf(info->dev_name, "mlx4_port%d", port);
1043 info->port_attr.attr.name = info->dev_name;
1044 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1045 info->port_attr.show = show_port_type;
1046 info->port_attr.store = set_port_type;
1047 sysfs_attr_init(&info->port_attr.attr);
1049 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1051 mlx4_err(dev, "Failed to create file for port %d\n", port);
1058 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1063 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1066 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1068 struct mlx4_priv *priv;
1069 struct mlx4_dev *dev;
1073 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1075 err = pci_enable_device(pdev);
1077 dev_err(&pdev->dev, "Cannot enable PCI device, "
1083 * Check for BARs. We expect 0: 1MB
1085 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1086 pci_resource_len(pdev, 0) != 1 << 20) {
1087 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1089 goto err_disable_pdev;
1091 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1092 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1094 goto err_disable_pdev;
1097 err = pci_request_regions(pdev, DRV_NAME);
1099 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1100 goto err_disable_pdev;
1103 pci_set_master(pdev);
1105 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1107 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1108 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1110 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1111 goto err_release_regions;
1114 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1116 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1117 "consistent PCI DMA mask.\n");
1118 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1120 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1122 goto err_release_regions;
1126 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1128 dev_err(&pdev->dev, "Device struct alloc failed, "
1131 goto err_release_regions;
1136 INIT_LIST_HEAD(&priv->ctx_list);
1137 spin_lock_init(&priv->ctx_lock);
1139 mutex_init(&priv->port_mutex);
1141 INIT_LIST_HEAD(&priv->pgdir_list);
1142 mutex_init(&priv->pgdir_mutex);
1144 pci_read_config_byte(pdev, PCI_REVISION_ID, &dev->rev_id);
1147 * Now reset the HCA before we touch the PCI capabilities or
1148 * attempt a firmware command, since a boot ROM may have left
1149 * the HCA in an undefined state.
1151 err = mlx4_reset(dev);
1153 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1157 if (mlx4_cmd_init(dev)) {
1158 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1162 err = mlx4_init_hca(dev);
1166 err = mlx4_alloc_eq_table(dev);
1170 priv->msix_ctl.pool_bm = 0;
1171 spin_lock_init(&priv->msix_ctl.pool_lock);
1173 mlx4_enable_msi_x(dev);
1175 err = mlx4_setup_hca(dev);
1176 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1177 dev->flags &= ~MLX4_FLAG_MSI_X;
1178 pci_disable_msix(pdev);
1179 err = mlx4_setup_hca(dev);
1185 for (port = 1; port <= dev->caps.num_ports; port++) {
1186 err = mlx4_init_port_info(dev, port);
1191 err = mlx4_register_device(dev);
1195 mlx4_sense_init(dev);
1196 mlx4_start_sense(dev);
1198 pci_set_drvdata(pdev, dev);
1203 for (--port; port >= 1; --port)
1204 mlx4_cleanup_port_info(&priv->port[port]);
1206 mlx4_cleanup_mcg_table(dev);
1207 mlx4_cleanup_qp_table(dev);
1208 mlx4_cleanup_srq_table(dev);
1209 mlx4_cleanup_cq_table(dev);
1210 mlx4_cmd_use_polling(dev);
1211 mlx4_cleanup_eq_table(dev);
1212 mlx4_cleanup_mr_table(dev);
1213 mlx4_cleanup_pd_table(dev);
1214 mlx4_cleanup_uar_table(dev);
1217 mlx4_free_eq_table(dev);
1220 if (dev->flags & MLX4_FLAG_MSI_X)
1221 pci_disable_msix(pdev);
1223 mlx4_close_hca(dev);
1226 mlx4_cmd_cleanup(dev);
1231 err_release_regions:
1232 pci_release_regions(pdev);
1235 pci_disable_device(pdev);
1236 pci_set_drvdata(pdev, NULL);
1240 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1241 const struct pci_device_id *id)
1243 printk_once(KERN_INFO "%s", mlx4_version);
1245 return __mlx4_init_one(pdev, id);
1248 static void mlx4_remove_one(struct pci_dev *pdev)
1250 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1251 struct mlx4_priv *priv = mlx4_priv(dev);
1255 mlx4_stop_sense(dev);
1256 mlx4_unregister_device(dev);
1258 for (p = 1; p <= dev->caps.num_ports; p++) {
1259 mlx4_cleanup_port_info(&priv->port[p]);
1260 mlx4_CLOSE_PORT(dev, p);
1263 mlx4_cleanup_mcg_table(dev);
1264 mlx4_cleanup_qp_table(dev);
1265 mlx4_cleanup_srq_table(dev);
1266 mlx4_cleanup_cq_table(dev);
1267 mlx4_cmd_use_polling(dev);
1268 mlx4_cleanup_eq_table(dev);
1269 mlx4_cleanup_mr_table(dev);
1270 mlx4_cleanup_pd_table(dev);
1273 mlx4_uar_free(dev, &priv->driver_uar);
1274 mlx4_cleanup_uar_table(dev);
1275 mlx4_free_eq_table(dev);
1276 mlx4_close_hca(dev);
1277 mlx4_cmd_cleanup(dev);
1279 if (dev->flags & MLX4_FLAG_MSI_X)
1280 pci_disable_msix(pdev);
1283 pci_release_regions(pdev);
1284 pci_disable_device(pdev);
1285 pci_set_drvdata(pdev, NULL);
1289 int mlx4_restart_one(struct pci_dev *pdev)
1291 mlx4_remove_one(pdev);
1292 return __mlx4_init_one(pdev, NULL);
1295 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1296 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1297 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1298 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1299 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1300 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1301 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1302 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1303 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1304 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1305 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1306 { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1307 { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1308 { PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
1309 { PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
1310 { PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
1311 { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
1312 { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
1313 { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
1314 { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
1315 { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
1316 { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
1317 { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
1318 { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
1319 { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
1320 { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
1321 { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
1322 { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
1326 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1328 static struct pci_driver mlx4_driver = {
1330 .id_table = mlx4_pci_table,
1331 .probe = mlx4_init_one,
1332 .remove = __devexit_p(mlx4_remove_one)
1335 static int __init mlx4_verify_params(void)
1337 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1338 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1342 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1343 pr_warning("mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1347 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1348 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1355 static int __init mlx4_init(void)
1359 if (mlx4_verify_params())
1364 mlx4_wq = create_singlethread_workqueue("mlx4");
1368 ret = pci_register_driver(&mlx4_driver);
1369 return ret < 0 ? ret : 0;
1372 static void __exit mlx4_cleanup(void)
1374 pci_unregister_driver(&mlx4_driver);
1375 destroy_workqueue(mlx4_wq);
1378 module_init(mlx4_init);
1379 module_exit(mlx4_cleanup);