2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cmd.h>
36 #include <linux/cache.h>
42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
47 extern void __buggy_use_of_MLX4_GET(void);
48 extern void __buggy_use_of_MLX4_PUT(void);
50 static int enable_qos;
51 module_param(enable_qos, bool, 0444);
52 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
54 #define MLX4_GET(dest, source, offset) \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
66 #define MLX4_PUT(dest, source, offset) \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
78 static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
84 [ 3] = "XRC transport",
85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
93 [15] = "Big LSO headers",
96 [18] = "Atomic ops support",
97 [19] = "Raw multicast support",
98 [20] = "Address vector port checking support",
99 [21] = "UD multicast support",
100 [24] = "Demand paging support",
101 [25] = "Router support"
105 mlx4_dbg(dev, "DEV_CAP flags:\n");
106 for (i = 0; i < ARRAY_SIZE(fname); ++i)
107 if (fname[i] && (flags & (1 << i)))
108 mlx4_dbg(dev, " %s\n", fname[i]);
111 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
113 struct mlx4_cmd_mailbox *mailbox;
117 #define MOD_STAT_CFG_IN_SIZE 0x100
119 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
120 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
122 mailbox = mlx4_alloc_cmd_mailbox(dev);
124 return PTR_ERR(mailbox);
125 inbox = mailbox->buf;
127 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
129 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
130 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
132 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
133 MLX4_CMD_TIME_CLASS_A);
135 mlx4_free_cmd_mailbox(dev, mailbox);
139 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
141 struct mlx4_cmd_mailbox *mailbox;
149 #define QUERY_DEV_CAP_OUT_SIZE 0x100
150 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
151 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
152 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
153 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
154 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
155 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
156 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
157 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
158 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
159 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
160 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
161 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
162 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
163 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
164 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
165 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
166 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
167 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
168 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
169 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
170 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
171 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
172 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
173 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
174 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
175 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
176 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
177 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
178 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
179 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
180 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
181 #define QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET 0x43
182 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
183 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
184 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
185 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
186 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
187 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
188 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
189 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
190 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
191 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
192 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
193 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
194 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
195 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
196 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
197 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
198 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
199 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
200 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
201 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
202 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
203 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
204 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
205 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
206 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
207 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
208 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
209 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
210 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
211 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
213 mailbox = mlx4_alloc_cmd_mailbox(dev);
215 return PTR_ERR(mailbox);
216 outbox = mailbox->buf;
218 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
219 MLX4_CMD_TIME_CLASS_A);
223 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
224 dev_cap->reserved_qps = 1 << (field & 0xf);
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
226 dev_cap->max_qps = 1 << (field & 0x1f);
227 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
228 dev_cap->reserved_srqs = 1 << (field >> 4);
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
230 dev_cap->max_srqs = 1 << (field & 0x1f);
231 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
232 dev_cap->max_cq_sz = 1 << field;
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
234 dev_cap->reserved_cqs = 1 << (field & 0xf);
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
236 dev_cap->max_cqs = 1 << (field & 0x1f);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
238 dev_cap->max_mpts = 1 << (field & 0x3f);
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
240 dev_cap->reserved_eqs = field & 0xf;
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
242 dev_cap->max_eqs = 1 << (field & 0xf);
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
244 dev_cap->reserved_mtts = 1 << (field >> 4);
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
246 dev_cap->max_mrw_sz = 1 << field;
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
248 dev_cap->reserved_mrws = 1 << (field & 0xf);
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
250 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
252 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
253 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
254 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
255 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
258 dev_cap->max_gso_sz = 0;
260 dev_cap->max_gso_sz = 1 << field;
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
263 dev_cap->max_rdma_global = 1 << (field & 0x3f);
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
265 dev_cap->local_ca_ack_delay = field & 0x1f;
266 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
267 dev_cap->num_ports = field & 0xf;
268 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
269 dev_cap->max_msg_sz = 1 << (field & 0x1f);
270 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
271 dev_cap->stat_rate_support = stat_rate;
272 MLX4_GET(field, outbox, QUERY_DEV_CAP_ETH_UC_LOOPBACK_OFFSET);
273 dev_cap->loopback_support = field & 0x1;
274 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
275 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
276 dev_cap->reserved_uars = field >> 4;
277 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
278 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
279 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
280 dev_cap->min_page_sz = 1 << field;
282 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
284 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
285 dev_cap->bf_reg_size = 1 << (field & 0x1f);
286 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
287 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
288 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
289 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
291 dev_cap->bf_reg_size = 0;
292 mlx4_dbg(dev, "BlueFlame not available\n");
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
296 dev_cap->max_sq_sg = field;
297 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
298 dev_cap->max_sq_desc_sz = size;
300 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
301 dev_cap->max_qp_per_mcg = 1 << field;
302 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
303 dev_cap->reserved_mgms = field & 0xf;
304 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
305 dev_cap->max_mcgs = 1 << field;
306 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
307 dev_cap->reserved_pds = field >> 4;
308 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
309 dev_cap->max_pds = 1 << (field & 0x3f);
311 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
312 dev_cap->rdmarc_entry_sz = size;
313 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
314 dev_cap->qpc_entry_sz = size;
315 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
316 dev_cap->aux_entry_sz = size;
317 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
318 dev_cap->altc_entry_sz = size;
319 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
320 dev_cap->eqc_entry_sz = size;
321 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
322 dev_cap->cqc_entry_sz = size;
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
324 dev_cap->srq_entry_sz = size;
325 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
326 dev_cap->cmpt_entry_sz = size;
327 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
328 dev_cap->mtt_entry_sz = size;
329 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
330 dev_cap->dmpt_entry_sz = size;
332 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
333 dev_cap->max_srq_sz = 1 << field;
334 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
335 dev_cap->max_qp_sz = 1 << field;
336 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
337 dev_cap->resize_srq = field & 1;
338 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
339 dev_cap->max_rq_sg = field;
340 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
341 dev_cap->max_rq_desc_sz = size;
343 MLX4_GET(dev_cap->bmme_flags, outbox,
344 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
345 MLX4_GET(dev_cap->reserved_lkey, outbox,
346 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
347 MLX4_GET(dev_cap->max_icm_sz, outbox,
348 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
350 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
351 for (i = 1; i <= dev_cap->num_ports; ++i) {
352 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
353 dev_cap->max_vl[i] = field >> 4;
354 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
355 dev_cap->ib_mtu[i] = field >> 4;
356 dev_cap->max_port_width[i] = field & 0xf;
357 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
358 dev_cap->max_gids[i] = 1 << (field & 0xf);
359 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
360 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
363 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
364 #define QUERY_PORT_MTU_OFFSET 0x01
365 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
366 #define QUERY_PORT_WIDTH_OFFSET 0x06
367 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
368 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
369 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
370 #define QUERY_PORT_MAC_OFFSET 0x10
372 for (i = 1; i <= dev_cap->num_ports; ++i) {
373 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
374 MLX4_CMD_TIME_CLASS_B);
378 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
379 dev_cap->supported_port_types[i] = field & 3;
380 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
381 dev_cap->ib_mtu[i] = field & 0xf;
382 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
383 dev_cap->max_port_width[i] = field & 0xf;
384 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
385 dev_cap->max_gids[i] = 1 << (field >> 4);
386 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
387 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
388 dev_cap->max_vl[i] = field & 0xf;
389 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
390 dev_cap->log_max_macs[i] = field & 0xf;
391 dev_cap->log_max_vlans[i] = field >> 4;
392 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
393 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
397 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
398 dev_cap->bmme_flags, dev_cap->reserved_lkey);
401 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
402 * we can't use any EQs whose doorbell falls on that page,
403 * even if the EQ itself isn't reserved.
405 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
406 dev_cap->reserved_eqs);
408 mlx4_dbg(dev, "Max ICM size %lld MB\n",
409 (unsigned long long) dev_cap->max_icm_sz >> 20);
410 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
411 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
412 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
413 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
414 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
415 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
416 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
417 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
418 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
419 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
420 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
421 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
422 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
423 dev_cap->max_pds, dev_cap->reserved_mgms);
424 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
425 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
426 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
427 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
428 dev_cap->max_port_width[1]);
429 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
430 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
431 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
432 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
433 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
435 dump_dev_cap_flags(dev, dev_cap->flags);
438 mlx4_free_cmd_mailbox(dev, mailbox);
442 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
444 struct mlx4_cmd_mailbox *mailbox;
445 struct mlx4_icm_iter iter;
453 mailbox = mlx4_alloc_cmd_mailbox(dev);
455 return PTR_ERR(mailbox);
456 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
457 pages = mailbox->buf;
459 for (mlx4_icm_first(icm, &iter);
460 !mlx4_icm_last(&iter);
461 mlx4_icm_next(&iter)) {
463 * We have to pass pages that are aligned to their
464 * size, so find the least significant 1 in the
465 * address or size and use that as our log2 size.
467 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
468 if (lg < MLX4_ICM_PAGE_SHIFT) {
469 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
471 (unsigned long long) mlx4_icm_addr(&iter),
472 mlx4_icm_size(&iter));
477 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
479 pages[nent * 2] = cpu_to_be64(virt);
483 pages[nent * 2 + 1] =
484 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
485 (lg - MLX4_ICM_PAGE_SHIFT));
486 ts += 1 << (lg - 10);
489 if (++nent == MLX4_MAILBOX_SIZE / 16) {
490 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
491 MLX4_CMD_TIME_CLASS_B);
500 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
505 case MLX4_CMD_MAP_FA:
506 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
508 case MLX4_CMD_MAP_ICM_AUX:
509 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
511 case MLX4_CMD_MAP_ICM:
512 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
513 tc, ts, (unsigned long long) virt - (ts << 10));
518 mlx4_free_cmd_mailbox(dev, mailbox);
522 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
524 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
527 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
529 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
533 int mlx4_RUN_FW(struct mlx4_dev *dev)
535 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
538 int mlx4_QUERY_FW(struct mlx4_dev *dev)
540 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
541 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
542 struct mlx4_cmd_mailbox *mailbox;
549 #define QUERY_FW_OUT_SIZE 0x100
550 #define QUERY_FW_VER_OFFSET 0x00
551 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
552 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
553 #define QUERY_FW_ERR_START_OFFSET 0x30
554 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
555 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
557 #define QUERY_FW_SIZE_OFFSET 0x00
558 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
559 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
561 mailbox = mlx4_alloc_cmd_mailbox(dev);
563 return PTR_ERR(mailbox);
564 outbox = mailbox->buf;
566 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
567 MLX4_CMD_TIME_CLASS_A);
571 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
573 * FW subminor version is at more significant bits than minor
574 * version, so swap here.
576 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
577 ((fw_ver & 0xffff0000ull) >> 16) |
578 ((fw_ver & 0x0000ffffull) << 16);
580 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
581 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
582 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
583 mlx4_err(dev, "Installed FW has unsupported "
584 "command interface revision %d.\n",
586 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
587 (int) (dev->caps.fw_ver >> 32),
588 (int) (dev->caps.fw_ver >> 16) & 0xffff,
589 (int) dev->caps.fw_ver & 0xffff);
590 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
591 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
596 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
597 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
599 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
600 cmd->max_cmds = 1 << lg;
602 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
603 (int) (dev->caps.fw_ver >> 32),
604 (int) (dev->caps.fw_ver >> 16) & 0xffff,
605 (int) dev->caps.fw_ver & 0xffff,
606 cmd_if_rev, cmd->max_cmds);
608 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
609 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
610 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
611 fw->catas_bar = (fw->catas_bar >> 6) * 2;
613 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
614 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
616 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
617 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
618 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
619 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
621 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
624 * Round up number of system pages needed in case
625 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
628 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
629 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
631 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
632 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
635 mlx4_free_cmd_mailbox(dev, mailbox);
639 static void get_board_id(void *vsd, char *board_id)
643 #define VSD_OFFSET_SIG1 0x00
644 #define VSD_OFFSET_SIG2 0xde
645 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
646 #define VSD_OFFSET_TS_BOARD_ID 0x20
648 #define VSD_SIGNATURE_TOPSPIN 0x5ad
650 memset(board_id, 0, MLX4_BOARD_ID_LEN);
652 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
653 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
654 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
657 * The board ID is a string but the firmware byte
658 * swaps each 4-byte word before passing it back to
659 * us. Therefore we need to swab it before printing.
661 for (i = 0; i < 4; ++i)
662 ((u32 *) board_id)[i] =
663 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
667 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
669 struct mlx4_cmd_mailbox *mailbox;
673 #define QUERY_ADAPTER_OUT_SIZE 0x100
674 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
675 #define QUERY_ADAPTER_VSD_OFFSET 0x20
677 mailbox = mlx4_alloc_cmd_mailbox(dev);
679 return PTR_ERR(mailbox);
680 outbox = mailbox->buf;
682 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
683 MLX4_CMD_TIME_CLASS_A);
687 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
689 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
693 mlx4_free_cmd_mailbox(dev, mailbox);
697 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
699 struct mlx4_cmd_mailbox *mailbox;
703 #define INIT_HCA_IN_SIZE 0x200
704 #define INIT_HCA_VERSION_OFFSET 0x000
705 #define INIT_HCA_VERSION 2
706 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
707 #define INIT_HCA_FLAGS_OFFSET 0x014
708 #define INIT_HCA_QPC_OFFSET 0x020
709 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
710 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
711 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
712 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
713 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
714 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
715 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
716 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
717 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
718 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
719 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
720 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
721 #define INIT_HCA_MCAST_OFFSET 0x0c0
722 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
723 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
724 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
725 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
726 #define INIT_HCA_TPT_OFFSET 0x0f0
727 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
728 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
729 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
730 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
731 #define INIT_HCA_UAR_OFFSET 0x120
732 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
733 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
735 mailbox = mlx4_alloc_cmd_mailbox(dev);
737 return PTR_ERR(mailbox);
738 inbox = mailbox->buf;
740 memset(inbox, 0, INIT_HCA_IN_SIZE);
742 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
744 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
745 (ilog2(cache_line_size()) - 4) << 5;
747 #if defined(__LITTLE_ENDIAN)
748 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
749 #elif defined(__BIG_ENDIAN)
750 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
752 #error Host endianness not defined
754 /* Check port for UD address vector: */
755 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
757 /* Enable IPoIB checksumming if we can: */
758 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
759 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
761 /* Enable QoS support if module parameter set */
763 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
765 /* QPC/EEC/CQC/EQC/RDMARC attributes */
767 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
768 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
769 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
770 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
771 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
772 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
773 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
774 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
775 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
776 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
777 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
778 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
780 /* multicast attributes */
782 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
783 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
784 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
785 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
789 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
790 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
791 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
792 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
796 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
797 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
799 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
802 mlx4_err(dev, "INIT_HCA returns %d\n", err);
804 mlx4_free_cmd_mailbox(dev, mailbox);
808 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
810 struct mlx4_cmd_mailbox *mailbox;
816 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
817 #define INIT_PORT_IN_SIZE 256
818 #define INIT_PORT_FLAGS_OFFSET 0x00
819 #define INIT_PORT_FLAG_SIG (1 << 18)
820 #define INIT_PORT_FLAG_NG (1 << 17)
821 #define INIT_PORT_FLAG_G0 (1 << 16)
822 #define INIT_PORT_VL_SHIFT 4
823 #define INIT_PORT_PORT_WIDTH_SHIFT 8
824 #define INIT_PORT_MTU_OFFSET 0x04
825 #define INIT_PORT_MAX_GID_OFFSET 0x06
826 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
827 #define INIT_PORT_GUID0_OFFSET 0x10
828 #define INIT_PORT_NODE_GUID_OFFSET 0x18
829 #define INIT_PORT_SI_GUID_OFFSET 0x20
831 mailbox = mlx4_alloc_cmd_mailbox(dev);
833 return PTR_ERR(mailbox);
834 inbox = mailbox->buf;
836 memset(inbox, 0, INIT_PORT_IN_SIZE);
839 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
840 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
841 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
843 field = 128 << dev->caps.ib_mtu_cap[port];
844 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
845 field = dev->caps.gid_table_len[port];
846 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
847 field = dev->caps.pkey_table_len[port];
848 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
850 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
851 MLX4_CMD_TIME_CLASS_A);
853 mlx4_free_cmd_mailbox(dev, mailbox);
855 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
856 MLX4_CMD_TIME_CLASS_A);
860 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
862 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
864 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
866 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
868 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
870 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
873 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
875 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
876 MLX4_CMD_SET_ICM_SIZE,
877 MLX4_CMD_TIME_CLASS_A);
882 * Round up number of system pages needed in case
883 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
885 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
886 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
891 int mlx4_NOP(struct mlx4_dev *dev)
893 /* Input modifier of 0x1f means "finish as soon as possible." */
894 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);