drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  49
  50 /**
  51  *  ixgbe_identify_phy_generic - Get physical layer module
  52  *  @hw: pointer to hardware structure
  53  *
  54  *  Determines the physical layer module found on the current adapter.
  55  **/
  56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  57 {
  58         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  59         u32 phy_addr;
  60
  61         if (hw->phy.type == ixgbe_phy_unknown) {
  62                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  63                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  64                                 ixgbe_get_phy_id(hw);
  65                                 hw->phy.type =
  66                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  67                                 status = 0;
  68                                 break;
  69                         }
  70                 }
  71         } else {
  72                 status = 0;
  73         }
  74
  75         return status;
  76 }
  77
  78 /**
  79  *  ixgbe_get_phy_id - Get the phy type
  80  *  @hw: pointer to hardware structure
  81  *
  82  **/
  83 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
  84 {
  85         u32 status;
  86         u16 phy_id_high = 0;
  87         u16 phy_id_low = 0;
  88
  89         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
  90                                       &phy_id_high);
  91
  92         if (status == 0) {
  93                 hw->phy.id = (u32)(phy_id_high << 16);
  94                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
  95                                               &phy_id_low);
  96                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
  97                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
  98         }
  99         return status;
 100 }
 101
 102 /**
 103  *  ixgbe_get_phy_type_from_id - Get the phy type
 104  *  @hw: pointer to hardware structure
 105  *
 106  **/
 107 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 108 {
 109         enum ixgbe_phy_type phy_type;
 110
 111         switch (phy_id) {
 112         case TN1010_PHY_ID:
 113                 phy_type = ixgbe_phy_tn;
 114                 break;
 115         case QT2022_PHY_ID:
 116                 phy_type = ixgbe_phy_qt;
 117                 break;
 118         case ATH_PHY_ID:
 119                 phy_type = ixgbe_phy_nl;
 120                 break;
 121         default:
 122                 phy_type = ixgbe_phy_unknown;
 123                 break;
 124         }
 125
 126         return phy_type;
 127 }
 128
 129 /**
 130  *  ixgbe_reset_phy_generic - Performs a PHY reset
 131  *  @hw: pointer to hardware structure
 132  **/
 133 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 134 {
 135         /*
 136          * Perform soft PHY reset to the PHY_XS.
 137          * This will cause a soft reset to the PHY
 138          */
 139         return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 140                                      MDIO_CTRL1_RESET);
 141 }
 142
 143 /**
 144  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 145  *  @hw: pointer to hardware structure
 146  *  @reg_addr: 32 bit address of PHY register to read
 147  *  @phy_data: Pointer to read data from PHY register
 148  **/
 149 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 150                                u32 device_type, u16 *phy_data)
 151 {
 152         u32 command;
 153         u32 i;
 154         u32 data;
 155         s32 status = 0;
 156         u16 gssr;
 157
 158         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 159                 gssr = IXGBE_GSSR_PHY1_SM;
 160         else
 161                 gssr = IXGBE_GSSR_PHY0_SM;
 162
 163         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 164                 status = IXGBE_ERR_SWFW_SYNC;
 165
 166         if (status == 0) {
 167                 /* Setup and write the address cycle command */
 168                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 169                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 170                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 171                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 172
 173                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 174
 175                 /*
 176                  * Check every 10 usec to see if the address cycle completed.
 177                  * The MDI Command bit will clear when the operation is
 178                  * complete
 179                  */
 180                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 181                         udelay(10);
 182
 183                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 184
 185                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 186                                 break;
 187                 }
 188
 189                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 190                         hw_dbg(hw, "PHY address command did not complete.\n");
 191                         status = IXGBE_ERR_PHY;
 192                 }
 193
 194                 if (status == 0) {
 195                         /*
 196                          * Address cycle complete, setup and write the read
 197                          * command
 198                          */
 199                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 200                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 201                                    (hw->phy.mdio.prtad <<
 202                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 203                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 204
 205                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 206
 207                         /*
 208                          * Check every 10 usec to see if the address cycle
 209                          * completed. The MDI Command bit will clear when the
 210                          * operation is complete
 211                          */
 212                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 213                                 udelay(10);
 214
 215                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 216
 217                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 218                                         break;
 219                         }
 220
 221                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 222                                 hw_dbg(hw, "PHY read command didn't complete\n");
 223                                 status = IXGBE_ERR_PHY;
 224                         } else {
 225                                 /*
 226                                  * Read operation is complete.  Get the data
 227                                  * from MSRWD
 228                                  */
 229                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 230                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 231                                 *phy_data = (u16)(data);
 232                         }
 233                 }
 234
 235                 ixgbe_release_swfw_sync(hw, gssr);
 236         }
 237
 238         return status;
 239 }
 240
 241 /**
 242  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 243  *  @hw: pointer to hardware structure
 244  *  @reg_addr: 32 bit PHY register to write
 245  *  @device_type: 5 bit device type
 246  *  @phy_data: Data to write to the PHY register
 247  **/
 248 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 249                                 u32 device_type, u16 phy_data)
 250 {
 251         u32 command;
 252         u32 i;
 253         s32 status = 0;
 254         u16 gssr;
 255
 256         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 257                 gssr = IXGBE_GSSR_PHY1_SM;
 258         else
 259                 gssr = IXGBE_GSSR_PHY0_SM;
 260
 261         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 262                 status = IXGBE_ERR_SWFW_SYNC;
 263
 264         if (status == 0) {
 265                 /* Put the data in the MDI single read and write data register*/
 266                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 267
 268                 /* Setup and write the address cycle command */
 269                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 270                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 271                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 272                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 273
 274                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 275
 276                 /*
 277                  * Check every 10 usec to see if the address cycle completed.
 278                  * The MDI Command bit will clear when the operation is
 279                  * complete
 280                  */
 281                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 282                         udelay(10);
 283
 284                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 285
 286                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 287                                 break;
 288                 }
 289
 290                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 291                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 292                         status = IXGBE_ERR_PHY;
 293                 }
 294
 295                 if (status == 0) {
 296                         /*
 297                          * Address cycle complete, setup and write the write
 298                          * command
 299                          */
 300                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 301                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 302                                    (hw->phy.mdio.prtad <<
 303                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 304                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 305
 306                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 307
 308                         /*
 309                          * Check every 10 usec to see if the address cycle
 310                          * completed. The MDI Command bit will clear when the
 311                          * operation is complete
 312                          */
 313                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 314                                 udelay(10);
 315
 316                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 317
 318                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 319                                         break;
 320                         }
 321
 322                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 323                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 324                                 status = IXGBE_ERR_PHY;
 325                         }
 326                 }
 327
 328                 ixgbe_release_swfw_sync(hw, gssr);
 329         }
 330
 331         return status;
 332 }
 333
 334 /**
 335  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 336  *  @hw: pointer to hardware structure
 337  *
 338  *  Restart autonegotiation and PHY and waits for completion.
 339  **/
 340 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 341 {
 342         s32 status = IXGBE_NOT_IMPLEMENTED;
 343         u32 time_out;
 344         u32 max_time_out = 10;
 345         u16 autoneg_reg;
 346
 347         /*
 348          * Set advertisement settings in PHY based on autoneg_advertised
 349          * settings. If autoneg_advertised = 0, then advertise default values
 350          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 351          * for a 1G.
 352          */
 353         hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
 354
 355         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 356                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 357         else
 358                 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 359
 360         hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
 361
 362         /* Restart PHY autonegotiation and wait for completion */
 363         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
 364
 365         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 366
 367         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
 368
 369         /* Wait for autonegotiation to finish */
 370         for (time_out = 0; time_out < max_time_out; time_out++) {
 371                 udelay(10);
 372                 /* Restart PHY autonegotiation and wait for completion */
 373                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
 374                                               &autoneg_reg);
 375
 376                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 377                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
 378                         status = 0;
 379                         break;
 380                 }
 381         }
 382
 383         if (time_out == max_time_out)
 384                 status = IXGBE_ERR_LINK_SETUP;
 385
 386         return status;
 387 }
 388
 389 /**
 390  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 391  *  @hw: pointer to hardware structure
 392  *  @speed: new link speed
 393  *  @autoneg: true if autonegotiation enabled
 394  **/
 395 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 396                                        ixgbe_link_speed speed,
 397                                        bool autoneg,
 398                                        bool autoneg_wait_to_complete)
 399 {
 400
 401         /*
 402          * Clear autoneg_advertised and set new values based on input link
 403          * speed.
 404          */
 405         hw->phy.autoneg_advertised = 0;
 406
 407         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 408                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 409
 410         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 411                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 412
 413         /* Setup link based on the new speed settings */
 414         hw->phy.ops.setup_link(hw);
 415
 416         return 0;
 417 }
 418
 419 /**
 420  *  ixgbe_reset_phy_nl - Performs a PHY reset
 421  *  @hw: pointer to hardware structure
 422  **/
 423 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 424 {
 425         u16 phy_offset, control, eword, edata, block_crc;
 426         bool end_data = false;
 427         u16 list_offset, data_offset;
 428         u16 phy_data = 0;
 429         s32 ret_val = 0;
 430         u32 i;
 431
 432         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 433
 434         /* reset the PHY and poll for completion */
 435         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 436                               (phy_data | MDIO_CTRL1_RESET));
 437
 438         for (i = 0; i < 100; i++) {
 439                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 440                                      &phy_data);
 441                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 442                         break;
 443                 msleep(10);
 444         }
 445
 446         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 447                 hw_dbg(hw, "PHY reset did not complete.\n");
 448                 ret_val = IXGBE_ERR_PHY;
 449                 goto out;
 450         }
 451
 452         /* Get init offsets */
 453         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 454                                                       &data_offset);
 455         if (ret_val != 0)
 456                 goto out;
 457
 458         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 459         data_offset++;
 460         while (!end_data) {
 461                 /*
 462                  * Read control word from PHY init contents offset
 463                  */
 464                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 465                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 466                            IXGBE_CONTROL_SHIFT_NL;
 467                 edata = eword & IXGBE_DATA_MASK_NL;
 468                 switch (control) {
 469                 case IXGBE_DELAY_NL:
 470                         data_offset++;
 471                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 472                         msleep(edata);
 473                         break;
 474                 case IXGBE_DATA_NL:
 475                         hw_dbg(hw, "DATA:  \n");
 476                         data_offset++;
 477                         hw->eeprom.ops.read(hw, data_offset++,
 478                                             &phy_offset);
 479                         for (i = 0; i < edata; i++) {
 480                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 481                                 hw->phy.ops.write_reg(hw, phy_offset,
 482                                                       MDIO_MMD_PMAPMD, eword);
 483                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 484                                        phy_offset);
 485                                 data_offset++;
 486                                 phy_offset++;
 487                         }
 488                         break;
 489                 case IXGBE_CONTROL_NL:
 490                         data_offset++;
 491                         hw_dbg(hw, "CONTROL: \n");
 492                         if (edata == IXGBE_CONTROL_EOL_NL) {
 493                                 hw_dbg(hw, "EOL\n");
 494                                 end_data = true;
 495                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 496                                 hw_dbg(hw, "SOL\n");
 497                         } else {
 498                                 hw_dbg(hw, "Bad control value\n");
 499                                 ret_val = IXGBE_ERR_PHY;
 500                                 goto out;
 501                         }
 502                         break;
 503                 default:
 504                         hw_dbg(hw, "Bad control type\n");
 505                         ret_val = IXGBE_ERR_PHY;
 506                         goto out;
 507                 }
 508         }
 509
 510 out:
 511         return ret_val;
 512 }
 513
 514 /**
 515  *  ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
 516  *                                      the PHY type.
 517  *  @hw: pointer to hardware structure
 518  *
 519  *  Searches for and indentifies the SFP module.  Assings appropriate PHY type.
 520  **/
 521 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 522 {
 523         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 524         u32 vendor_oui = 0;
 525         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 526         u8 identifier = 0;
 527         u8 comp_codes_1g = 0;
 528         u8 comp_codes_10g = 0;
 529         u8 oui_bytes[3] = {0, 0, 0};
 530         u8 cable_tech = 0;
 531         u16 enforce_sfp = 0;
 532
 533         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
 534                                              &identifier);
 535
 536         if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
 537                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 538                 goto out;
 539         }
 540
 541         if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
 542                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
 543                                             &comp_codes_1g);
 544                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
 545                                             &comp_codes_10g);
 546                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
 547                                             &cable_tech);
 548
 549                 /* ID Module
 550                  * =========
 551                  * 0    SFP_DA_CU
 552                  * 1    SFP_SR
 553                  * 2    SFP_LR
 554                  * 3    SFP_DA_CORE0 - 82599-specific
 555                  * 4    SFP_DA_CORE1 - 82599-specific
 556                  * 5    SFP_SR/LR_CORE0 - 82599-specific
 557                  * 6    SFP_SR/LR_CORE1 - 82599-specific
 558                  */
 559                 if (hw->mac.type == ixgbe_mac_82598EB) {
 560                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 561                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 562                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 563                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 564                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 565                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 566                         else
 567                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 568                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 569                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 570                                 if (hw->bus.lan_id == 0)
 571                                         hw->phy.sfp_type =
 572                                                      ixgbe_sfp_type_da_cu_core0;
 573                                 else
 574                                         hw->phy.sfp_type =
 575                                                      ixgbe_sfp_type_da_cu_core1;
 576                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 577                                 if (hw->bus.lan_id == 0)
 578                                         hw->phy.sfp_type =
 579                                                       ixgbe_sfp_type_srlr_core0;
 580                                 else
 581                                         hw->phy.sfp_type =
 582                                                       ixgbe_sfp_type_srlr_core1;
 583                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 584                                 if (hw->bus.lan_id == 0)
 585                                         hw->phy.sfp_type =
 586                                                       ixgbe_sfp_type_srlr_core0;
 587                                 else
 588                                         hw->phy.sfp_type =
 589                                                       ixgbe_sfp_type_srlr_core1;
 590                         else
 591                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 592                 }
 593
 594                 if (hw->phy.sfp_type != stored_sfp_type)
 595                         hw->phy.sfp_setup_needed = true;
 596
 597                 /* Determine if the SFP+ PHY is dual speed or not. */
 598                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 599                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 600                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
 601                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
 602                         hw->phy.multispeed_fiber = true;
 603
 604                 /* Determine PHY vendor */
 605                 if (hw->phy.type != ixgbe_phy_nl) {
 606                         hw->phy.id = identifier;
 607                         hw->phy.ops.read_i2c_eeprom(hw,
 608                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
 609                                                     &oui_bytes[0]);
 610                         hw->phy.ops.read_i2c_eeprom(hw,
 611                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
 612                                                     &oui_bytes[1]);
 613                         hw->phy.ops.read_i2c_eeprom(hw,
 614                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
 615                                                     &oui_bytes[2]);
 616
 617                         vendor_oui =
 618                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
 619                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
 620                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
 621
 622                         switch (vendor_oui) {
 623                         case IXGBE_SFF_VENDOR_OUI_TYCO:
 624                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 625                                         hw->phy.type = ixgbe_phy_tw_tyco;
 626                                 break;
 627                         case IXGBE_SFF_VENDOR_OUI_FTL:
 628                                 hw->phy.type = ixgbe_phy_sfp_ftl;
 629                                 break;
 630                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
 631                                 hw->phy.type = ixgbe_phy_sfp_avago;
 632                                 break;
 633                         case IXGBE_SFF_VENDOR_OUI_INTEL:
 634                                 hw->phy.type = ixgbe_phy_sfp_intel;
 635                                 break;
 636                         default:
 637                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 638                                         hw->phy.type = ixgbe_phy_tw_unknown;
 639                                 else
 640                                         hw->phy.type = ixgbe_phy_sfp_unknown;
 641                                 break;
 642                         }
 643                 }
 644
 645                 /* All passive DA cables are supported */
 646                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 647                         status = 0;
 648                         goto out;
 649                 }
 650
 651                 /* 1G SFP modules are not supported */
 652                 if (comp_codes_10g == 0) {
 653                         hw->phy.type = ixgbe_phy_sfp_unsupported;
 654                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 655                         goto out;
 656                 }
 657
 658                 /* Anything else 82598-based is supported */
 659                 if (hw->mac.type == ixgbe_mac_82598EB) {
 660                         status = 0;
 661                         goto out;
 662                 }
 663
 664                 /* This is guaranteed to be 82599, no need to check for NULL */
 665                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
 666                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
 667                         /* Make sure we're a supported PHY type */
 668                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
 669                                 status = 0;
 670                         } else {
 671                                 hw_dbg(hw, "SFP+ module not supported\n");
 672                                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 673                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 674                         }
 675                 } else {
 676                         status = 0;
 677                 }
 678         }
 679
 680 out:
 681         return status;
 682 }
 683
 684 /**
 685  *  ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
 686  *  if it supports a given SFP+ module type, if so it returns the offsets to the
 687  *  phy init sequence block.
 688  *  @hw: pointer to hardware structure
 689  *  @list_offset: offset to the SFP ID list
 690  *  @data_offset: offset to the SFP data block
 691  **/
 692 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 693                                         u16 *list_offset,
 694                                         u16 *data_offset)
 695 {
 696         u16 sfp_id;
 697
 698         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
 699                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 700
 701         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 702                 return IXGBE_ERR_SFP_NOT_PRESENT;
 703
 704         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
 705             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
 706                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 707
 708         /* Read offset to PHY init contents */
 709         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
 710
 711         if ((!*list_offset) || (*list_offset == 0xFFFF))
 712                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
 713
 714         /* Shift offset to first ID word */
 715         (*list_offset)++;
 716
 717         /*
 718          * Find the matching SFP ID in the EEPROM
 719          * and program the init sequence
 720          */
 721         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
 722
 723         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
 724                 if (sfp_id == hw->phy.sfp_type) {
 725                         (*list_offset)++;
 726                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
 727                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
 728                                 hw_dbg(hw, "SFP+ module not supported\n");
 729                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 730                         } else {
 731                                 break;
 732                         }
 733                 } else {
 734                         (*list_offset) += 2;
 735                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
 736                                 return IXGBE_ERR_PHY;
 737                 }
 738         }
 739
 740         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
 741                 hw_dbg(hw, "No matching SFP+ module found\n");
 742                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 743         }
 744
 745         return 0;
 746 }
 747
 748 /**
 749  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
 750  *  @hw: pointer to hardware structure
 751  *  @byte_offset: EEPROM byte offset to read
 752  *  @eeprom_data: value read
 753  *
 754  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 755  **/
 756 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 757                                   u8 *eeprom_data)
 758 {
 759         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
 760                                          IXGBE_I2C_EEPROM_DEV_ADDR,
 761                                          eeprom_data);
 762 }
 763
 764 /**
 765  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
 766  *  @hw: pointer to hardware structure
 767  *  @byte_offset: EEPROM byte offset to write
 768  *  @eeprom_data: value to write
 769  *
 770  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
 771  **/
 772 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 773                                    u8 eeprom_data)
 774 {
 775         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
 776                                           IXGBE_I2C_EEPROM_DEV_ADDR,
 777                                           eeprom_data);
 778 }
 779
 780 /**
 781  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
 782  *  @hw: pointer to hardware structure
 783  *  @byte_offset: byte offset to read
 784  *  @data: value read
 785  *
 786  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
 787  *  a specified deivce address.
 788  **/
 789 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 790                                 u8 dev_addr, u8 *data)
 791 {
 792         s32 status = 0;
 793         u32 max_retry = 1;
 794         u32 retry = 0;
 795         bool nack = 1;
 796
 797         do {
 798                 ixgbe_i2c_start(hw);
 799
 800                 /* Device Address and write indication */
 801                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 802                 if (status != 0)
 803                         goto fail;
 804
 805                 status = ixgbe_get_i2c_ack(hw);
 806                 if (status != 0)
 807                         goto fail;
 808
 809                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 810                 if (status != 0)
 811                         goto fail;
 812
 813                 status = ixgbe_get_i2c_ack(hw);
 814                 if (status != 0)
 815                         goto fail;
 816
 817                 ixgbe_i2c_start(hw);
 818
 819                 /* Device Address and read indication */
 820                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
 821                 if (status != 0)
 822                         goto fail;
 823
 824                 status = ixgbe_get_i2c_ack(hw);
 825                 if (status != 0)
 826                         goto fail;
 827
 828                 status = ixgbe_clock_in_i2c_byte(hw, data);
 829                 if (status != 0)
 830                         goto fail;
 831
 832                 status = ixgbe_clock_out_i2c_bit(hw, nack);
 833                 if (status != 0)
 834                         goto fail;
 835
 836                 ixgbe_i2c_stop(hw);
 837                 break;
 838
 839 fail:
 840                 ixgbe_i2c_bus_clear(hw);
 841                 retry++;
 842                 if (retry < max_retry)
 843                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
 844                 else
 845                         hw_dbg(hw, "I2C byte read error.\n");
 846
 847         } while (retry < max_retry);
 848
 849         return status;
 850 }
 851
 852 /**
 853  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
 854  *  @hw: pointer to hardware structure
 855  *  @byte_offset: byte offset to write
 856  *  @data: value to write
 857  *
 858  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
 859  *  a specified device address.
 860  **/
 861 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 862                                  u8 dev_addr, u8 data)
 863 {
 864         s32 status = 0;
 865         u32 max_retry = 1;
 866         u32 retry = 0;
 867
 868         do {
 869                 ixgbe_i2c_start(hw);
 870
 871                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 872                 if (status != 0)
 873                         goto fail;
 874
 875                 status = ixgbe_get_i2c_ack(hw);
 876                 if (status != 0)
 877                         goto fail;
 878
 879                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 880                 if (status != 0)
 881                         goto fail;
 882
 883                 status = ixgbe_get_i2c_ack(hw);
 884                 if (status != 0)
 885                         goto fail;
 886
 887                 status = ixgbe_clock_out_i2c_byte(hw, data);
 888                 if (status != 0)
 889                         goto fail;
 890
 891                 status = ixgbe_get_i2c_ack(hw);
 892                 if (status != 0)
 893                         goto fail;
 894
 895                 ixgbe_i2c_stop(hw);
 896                 break;
 897
 898 fail:
 899                 ixgbe_i2c_bus_clear(hw);
 900                 retry++;
 901                 if (retry < max_retry)
 902                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
 903                 else
 904                         hw_dbg(hw, "I2C byte write error.\n");
 905         } while (retry < max_retry);
 906
 907         return status;
 908 }
 909
 910 /**
 911  *  ixgbe_i2c_start - Sets I2C start condition
 912  *  @hw: pointer to hardware structure
 913  *
 914  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
 915  **/
 916 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
 917 {
 918         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 919
 920         /* Start condition must begin with data and clock high */
 921         ixgbe_set_i2c_data(hw, &i2cctl, 1);
 922         ixgbe_raise_i2c_clk(hw, &i2cctl);
 923
 924         /* Setup time for start condition (4.7us) */
 925         udelay(IXGBE_I2C_T_SU_STA);
 926
 927         ixgbe_set_i2c_data(hw, &i2cctl, 0);
 928
 929         /* Hold time for start condition (4us) */
 930         udelay(IXGBE_I2C_T_HD_STA);
 931
 932         ixgbe_lower_i2c_clk(hw, &i2cctl);
 933
 934         /* Minimum low period of clock is 4.7 us */
 935         udelay(IXGBE_I2C_T_LOW);
 936
 937 }
 938
 939 /**
 940  *  ixgbe_i2c_stop - Sets I2C stop condition
 941  *  @hw: pointer to hardware structure
 942  *
 943  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
 944  **/
 945 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
 946 {
 947         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 948
 949         /* Stop condition must begin with data low and clock high */
 950         ixgbe_set_i2c_data(hw, &i2cctl, 0);
 951         ixgbe_raise_i2c_clk(hw, &i2cctl);
 952
 953         /* Setup time for stop condition (4us) */
 954         udelay(IXGBE_I2C_T_SU_STO);
 955
 956         ixgbe_set_i2c_data(hw, &i2cctl, 1);
 957
 958         /* bus free time between stop and start (4.7us)*/
 959         udelay(IXGBE_I2C_T_BUF);
 960 }
 961
 962 /**
 963  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
 964  *  @hw: pointer to hardware structure
 965  *  @data: data byte to clock in
 966  *
 967  *  Clocks in one byte data via I2C data/clock
 968  **/
 969 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
 970 {
 971         s32 status = 0;
 972         s32 i;
 973         bool bit = 0;
 974
 975         for (i = 7; i >= 0; i--) {
 976                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
 977                 *data |= bit << i;
 978
 979                 if (status != 0)
 980                         break;
 981         }
 982
 983         return status;
 984 }
 985
 986 /**
 987  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
 988  *  @hw: pointer to hardware structure
 989  *  @data: data byte clocked out
 990  *
 991  *  Clocks out one byte data via I2C data/clock
 992  **/
 993 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
 994 {
 995         s32 status = 0;
 996         s32 i;
 997         u32 i2cctl;
 998         bool bit = 0;
 999
1000         for (i = 7; i >= 0; i--) {
1001                 bit = (data >> i) & 0x1;
1002                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1003
1004                 if (status != 0)
1005                         break;
1006         }
1007
1008         /* Release SDA line (set high) */
1009         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1010         i2cctl |= IXGBE_I2C_DATA_OUT;
1011         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1012
1013         return status;
1014 }
1015
1016 /**
1017  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1018  *  @hw: pointer to hardware structure
1019  *
1020  *  Clocks in/out one bit via I2C data/clock
1021  **/
1022 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1023 {
1024         s32 status;
1025         u32 i = 0;
1026         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1027         u32 timeout = 10;
1028         bool ack = 1;
1029
1030         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1031
1032         if (status != 0)
1033                 goto out;
1034
1035         /* Minimum high period of clock is 4us */
1036         udelay(IXGBE_I2C_T_HIGH);
1037
1038         /* Poll for ACK.  Note that ACK in I2C spec is
1039          * transition from 1 to 0 */
1040         for (i = 0; i < timeout; i++) {
1041                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1042                 ack = ixgbe_get_i2c_data(&i2cctl);
1043
1044                 udelay(1);
1045                 if (ack == 0)
1046                         break;
1047         }
1048
1049         if (ack == 1) {
1050                 hw_dbg(hw, "I2C ack was not received.\n");
1051                 status = IXGBE_ERR_I2C;
1052         }
1053
1054         ixgbe_lower_i2c_clk(hw, &i2cctl);
1055
1056         /* Minimum low period of clock is 4.7 us */
1057         udelay(IXGBE_I2C_T_LOW);
1058
1059 out:
1060         return status;
1061 }
1062
1063 /**
1064  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1065  *  @hw: pointer to hardware structure
1066  *  @data: read data value
1067  *
1068  *  Clocks in one bit via I2C data/clock
1069  **/
1070 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1071 {
1072         s32 status;
1073         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1074
1075         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1076
1077         /* Minimum high period of clock is 4us */
1078         udelay(IXGBE_I2C_T_HIGH);
1079
1080         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1081         *data = ixgbe_get_i2c_data(&i2cctl);
1082
1083         ixgbe_lower_i2c_clk(hw, &i2cctl);
1084
1085         /* Minimum low period of clock is 4.7 us */
1086         udelay(IXGBE_I2C_T_LOW);
1087
1088         return status;
1089 }
1090
1091 /**
1092  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1093  *  @hw: pointer to hardware structure
1094  *  @data: data value to write
1095  *
1096  *  Clocks out one bit via I2C data/clock
1097  **/
1098 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1099 {
1100         s32 status;
1101         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1102
1103         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1104         if (status == 0) {
1105                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1106
1107                 /* Minimum high period of clock is 4us */
1108                 udelay(IXGBE_I2C_T_HIGH);
1109
1110                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1111
1112                 /* Minimum low period of clock is 4.7 us.
1113                  * This also takes care of the data hold time.
1114                  */
1115                 udelay(IXGBE_I2C_T_LOW);
1116         } else {
1117                 status = IXGBE_ERR_I2C;
1118                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1119         }
1120
1121         return status;
1122 }
1123 /**
1124  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1125  *  @hw: pointer to hardware structure
1126  *  @i2cctl: Current value of I2CCTL register
1127  *
1128  *  Raises the I2C clock line '0'->'1'
1129  **/
1130 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1131 {
1132         s32 status = 0;
1133
1134         *i2cctl |= IXGBE_I2C_CLK_OUT;
1135
1136         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1137
1138         /* SCL rise time (1000ns) */
1139         udelay(IXGBE_I2C_T_RISE);
1140
1141         return status;
1142 }
1143
1144 /**
1145  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1146  *  @hw: pointer to hardware structure
1147  *  @i2cctl: Current value of I2CCTL register
1148  *
1149  *  Lowers the I2C clock line '1'->'0'
1150  **/
1151 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1152 {
1153
1154         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1155
1156         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1157
1158         /* SCL fall time (300ns) */
1159         udelay(IXGBE_I2C_T_FALL);
1160 }
1161
1162 /**
1163  *  ixgbe_set_i2c_data - Sets the I2C data bit
1164  *  @hw: pointer to hardware structure
1165  *  @i2cctl: Current value of I2CCTL register
1166  *  @data: I2C data value (0 or 1) to set
1167  *
1168  *  Sets the I2C data bit
1169  **/
1170 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1171 {
1172         s32 status = 0;
1173
1174         if (data)
1175                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1176         else
1177                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1178
1179         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1180
1181         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1182         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1183
1184         /* Verify data was set correctly */
1185         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1186         if (data != ixgbe_get_i2c_data(i2cctl)) {
1187                 status = IXGBE_ERR_I2C;
1188                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1189         }
1190
1191         return status;
1192 }
1193
1194 /**
1195  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1196  *  @hw: pointer to hardware structure
1197  *  @i2cctl: Current value of I2CCTL register
1198  *
1199  *  Returns the I2C data bit value
1200  **/
1201 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1202 {
1203         bool data;
1204
1205         if (*i2cctl & IXGBE_I2C_DATA_IN)
1206                 data = 1;
1207         else
1208                 data = 0;
1209
1210         return data;
1211 }
1212
1213 /**
1214  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1215  *  @hw: pointer to hardware structure
1216  *
1217  *  Clears the I2C bus by sending nine clock pulses.
1218  *  Used when data line is stuck low.
1219  **/
1220 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1221 {
1222         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1223         u32 i;
1224
1225         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1226
1227         for (i = 0; i < 9; i++) {
1228                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1229
1230                 /* Min high period of clock is 4us */
1231                 udelay(IXGBE_I2C_T_HIGH);
1232
1233                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1234
1235                 /* Min low period of clock is 4.7us*/
1236                 udelay(IXGBE_I2C_T_LOW);
1237         }
1238
1239         /* Put the i2c bus back to default state */
1240         ixgbe_i2c_stop(hw);
1241 }
1242
1243 /**
1244  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1245  *  @hw: pointer to hardware structure
1246  *
1247  *  Reads the VS1 register to determine if link is up and the current speed for
1248  *  the PHY.
1249  **/
1250 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1251                              bool *link_up)
1252 {
1253         s32 status = 0;
1254         u32 time_out;
1255         u32 max_time_out = 10;
1256         u16 phy_link = 0;
1257         u16 phy_speed = 0;
1258         u16 phy_data = 0;
1259
1260         /* Initialize speed and link to default case */
1261         *link_up = false;
1262         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1263
1264         /*
1265          * Check current speed and link status of the PHY register.
1266          * This is a vendor specific register and may have to
1267          * be changed for other copper PHYs.
1268          */
1269         for (time_out = 0; time_out < max_time_out; time_out++) {
1270                 udelay(10);
1271                 status = hw->phy.ops.read_reg(hw,
1272                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1273                                         MDIO_MMD_VEND1,
1274                                         &phy_data);
1275                 phy_link = phy_data &
1276                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1277                 phy_speed = phy_data &
1278                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1279                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1280                         *link_up = true;
1281                         if (phy_speed ==
1282                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1283                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1284                         break;
1285                 }
1286         }
1287
1288         return status;
1289 }
1290
1291 /**
1292  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1293  *  @hw: pointer to hardware structure
1294  *  @firmware_version: pointer to the PHY Firmware Version
1295  **/
1296 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1297                                        u16 *firmware_version)
1298 {
1299         s32 status = 0;
1300
1301         status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1302                                       firmware_version);
1303
1304         return status;
1305 }
1306