drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/ipv6.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/if_vlan.h>
  42 #include <scsi/fc/fc_fcoe.h>
  43
  44 #include "ixgbe.h"
  45 #include "ixgbe_common.h"
  46
  47 char ixgbe_driver_name[] = "ixgbe";
  48 static const char ixgbe_driver_string[] =
  49                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  50
  51 #define DRV_VERSION "2.0.37-k2"
  52 const char ixgbe_driver_version[] = DRV_VERSION;
  53 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  54
  55 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  56         [board_82598] = &ixgbe_82598_info,
  57         [board_82599] = &ixgbe_82599_info,
  58 };
  59
  60 /* ixgbe_pci_tbl - PCI Device ID Table
  61  *
  62  * Wildcard entries (PCI_ANY_ID) should come last
  63  * Last entry must be all 0s
  64  *
  65  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  66  *   Class, Class Mask, private data (not used) }
  67  */
  68 static struct pci_device_id ixgbe_pci_tbl[] = {
  69         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  70          board_82598 },
  71         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  72          board_82598 },
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  94          board_82599 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  96          board_82599 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  98          board_82599 },
  99
 100         /* required last entry */
 101         {0, }
 102 };
 103 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 104
 105 #ifdef CONFIG_IXGBE_DCA
 106 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 107                             void *p);
 108 static struct notifier_block dca_notifier = {
 109         .notifier_call = ixgbe_notify_dca,
 110         .next          = NULL,
 111         .priority      = 0
 112 };
 113 #endif
 114
 115 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 116 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 117 MODULE_LICENSE("GPL");
 118 MODULE_VERSION(DRV_VERSION);
 119
 120 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 121
 122 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 123 {
 124         u32 ctrl_ext;
 125
 126         /* Let firmware take over control of h/w */
 127         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 128         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 129                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 130 }
 131
 132 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 133 {
 134         u32 ctrl_ext;
 135
 136         /* Let firmware know the driver has taken over */
 137         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 138         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 139                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 140 }
 141
 142 /*
 143  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 144  * @adapter: pointer to adapter struct
 145  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 146  * @queue: queue to map the corresponding interrupt to
 147  * @msix_vector: the vector to map to the corresponding queue
 148  *
 149  */
 150 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 151                            u8 queue, u8 msix_vector)
 152 {
 153         u32 ivar, index;
 154         struct ixgbe_hw *hw = &adapter->hw;
 155         switch (hw->mac.type) {
 156         case ixgbe_mac_82598EB:
 157                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 158                 if (direction == -1)
 159                         direction = 0;
 160                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 161                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 162                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 163                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 164                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 165                 break;
 166         case ixgbe_mac_82599EB:
 167                 if (direction == -1) {
 168                         /* other causes */
 169                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 170                         index = ((queue & 1) * 8);
 171                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 172                         ivar &= ~(0xFF << index);
 173                         ivar |= (msix_vector << index);
 174                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 175                         break;
 176                 } else {
 177                         /* tx or rx causes */
 178                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 179                         index = ((16 * (queue & 1)) + (8 * direction));
 180                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 181                         ivar &= ~(0xFF << index);
 182                         ivar |= (msix_vector << index);
 183                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 184                         break;
 185                 }
 186         default:
 187                 break;
 188         }
 189 }
 190
 191 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 192                                           u64 qmask)
 193 {
 194         u32 mask;
 195
 196         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 197                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 198                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 199         } else {
 200                 mask = (qmask & 0xFFFFFFFF);
 201                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 202                 mask = (qmask >> 32);
 203                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 204         }
 205 }
 206
 207 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 208                                              struct ixgbe_tx_buffer
 209                                              *tx_buffer_info)
 210 {
 211         tx_buffer_info->dma = 0;
 212         if (tx_buffer_info->skb) {
 213                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 214                               DMA_TO_DEVICE);
 215                 dev_kfree_skb_any(tx_buffer_info->skb);
 216                 tx_buffer_info->skb = NULL;
 217         }
 218         tx_buffer_info->time_stamp = 0;
 219         /* tx_buffer_info must be completely set up in the transmit path */
 220 }
 221
 222 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 223                                        struct ixgbe_ring *tx_ring,
 224                                        unsigned int eop)
 225 {
 226         struct ixgbe_hw *hw = &adapter->hw;
 227
 228         /* Detect a transmit hang in hardware, this serializes the
 229          * check with the clearing of time_stamp and movement of eop */
 230         adapter->detect_tx_hung = false;
 231         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 232             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 233             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 234                 /* detected Tx unit hang */
 235                 union ixgbe_adv_tx_desc *tx_desc;
 236                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 237                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 238                         "  Tx Queue             <%d>\n"
 239                         "  TDH, TDT             <%x>, <%x>\n"
 240                         "  next_to_use          <%x>\n"
 241                         "  next_to_clean        <%x>\n"
 242                         "tx_buffer_info[next_to_clean]\n"
 243                         "  time_stamp           <%lx>\n"
 244                         "  jiffies              <%lx>\n",
 245                         tx_ring->queue_index,
 246                         IXGBE_READ_REG(hw, tx_ring->head),
 247                         IXGBE_READ_REG(hw, tx_ring->tail),
 248                         tx_ring->next_to_use, eop,
 249                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 250                 return true;
 251         }
 252
 253         return false;
 254 }
 255
 256 #define IXGBE_MAX_TXD_PWR       14
 257 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 258
 259 /* Tx Descriptors needed, worst case */
 260 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 261                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 262 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 263         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 264
 265 static void ixgbe_tx_timeout(struct net_device *netdev);
 266
 267 /**
 268  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 269  * @q_vector: structure containing interrupt and ring information
 270  * @tx_ring: tx ring to clean
 271  **/
 272 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 273                                struct ixgbe_ring *tx_ring)
 274 {
 275         struct ixgbe_adapter *adapter = q_vector->adapter;
 276         struct net_device *netdev = adapter->netdev;
 277         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 278         struct ixgbe_tx_buffer *tx_buffer_info;
 279         unsigned int i, eop, count = 0;
 280         unsigned int total_bytes = 0, total_packets = 0;
 281
 282         i = tx_ring->next_to_clean;
 283         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 284         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 285
 286         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 287                (count < tx_ring->work_limit)) {
 288                 bool cleaned = false;
 289                 for ( ; !cleaned; count++) {
 290                         struct sk_buff *skb;
 291                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 292                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 293                         cleaned = (i == eop);
 294                         skb = tx_buffer_info->skb;
 295
 296                         if (cleaned && skb) {
 297                                 unsigned int segs, bytecount;
 298                                 unsigned int hlen = skb_headlen(skb);
 299
 300                                 /* gso_segs is currently only valid for tcp */
 301                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 302 #ifdef IXGBE_FCOE
 303                                 /* adjust for FCoE Sequence Offload */
 304                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 305                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 306                                     skb_is_gso(skb)) {
 307                                         hlen = skb_transport_offset(skb) +
 308                                                 sizeof(struct fc_frame_header) +
 309                                                 sizeof(struct fcoe_crc_eof);
 310                                         segs = DIV_ROUND_UP(skb->len - hlen,
 311                                                 skb_shinfo(skb)->gso_size);
 312                                 }
 313 #endif /* IXGBE_FCOE */
 314                                 /* multiply data chunks by size of headers */
 315                                 bytecount = ((segs - 1) * hlen) + skb->len;
 316                                 total_packets += segs;
 317                                 total_bytes += bytecount;
 318                         }
 319
 320                         ixgbe_unmap_and_free_tx_resource(adapter,
 321                                                          tx_buffer_info);
 322
 323                         tx_desc->wb.status = 0;
 324
 325                         i++;
 326                         if (i == tx_ring->count)
 327                                 i = 0;
 328                 }
 329
 330                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 331                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 332         }
 333
 334         tx_ring->next_to_clean = i;
 335
 336 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 337         if (unlikely(count && netif_carrier_ok(netdev) &&
 338                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 339                 /* Make sure that anybody stopping the queue after this
 340                  * sees the new next_to_clean.
 341                  */
 342                 smp_mb();
 343                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 344                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 345                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 346                         ++adapter->restart_queue;
 347                 }
 348         }
 349
 350         if (adapter->detect_tx_hung) {
 351                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 352                         /* schedule immediate reset if we believe we hung */
 353                         DPRINTK(PROBE, INFO,
 354                                 "tx hang %d detected, resetting adapter\n",
 355                                 adapter->tx_timeout_count + 1);
 356                         ixgbe_tx_timeout(adapter->netdev);
 357                 }
 358         }
 359
 360         /* re-arm the interrupt */
 361         if (count >= tx_ring->work_limit)
 362                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 363
 364         tx_ring->total_bytes += total_bytes;
 365         tx_ring->total_packets += total_packets;
 366         tx_ring->stats.packets += total_packets;
 367         tx_ring->stats.bytes += total_bytes;
 368         adapter->net_stats.tx_bytes += total_bytes;
 369         adapter->net_stats.tx_packets += total_packets;
 370         return (count < tx_ring->work_limit);
 371 }
 372
 373 #ifdef CONFIG_IXGBE_DCA
 374 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 375                                 struct ixgbe_ring *rx_ring)
 376 {
 377         u32 rxctrl;
 378         int cpu = get_cpu();
 379         int q = rx_ring - adapter->rx_ring;
 380
 381         if (rx_ring->cpu != cpu) {
 382                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 383                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 384                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 385                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 386                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 387                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 388                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 389                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 390                 }
 391                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 392                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 393                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 394                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 395                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 396                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 397                 rx_ring->cpu = cpu;
 398         }
 399         put_cpu();
 400 }
 401
 402 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 403                                 struct ixgbe_ring *tx_ring)
 404 {
 405         u32 txctrl;
 406         int cpu = get_cpu();
 407         int q = tx_ring - adapter->tx_ring;
 408
 409         if (tx_ring->cpu != cpu) {
 410                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 411                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 412                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 413                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 414                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 415                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 416                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 417                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 418                 }
 419                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 420                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 421                 tx_ring->cpu = cpu;
 422         }
 423         put_cpu();
 424 }
 425
 426 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 427 {
 428         int i;
 429
 430         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 431                 return;
 432
 433         /* always use CB2 mode, difference is masked in the CB driver */
 434         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 435
 436         for (i = 0; i < adapter->num_tx_queues; i++) {
 437                 adapter->tx_ring[i].cpu = -1;
 438                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 439         }
 440         for (i = 0; i < adapter->num_rx_queues; i++) {
 441                 adapter->rx_ring[i].cpu = -1;
 442                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 443         }
 444 }
 445
 446 static int __ixgbe_notify_dca(struct device *dev, void *data)
 447 {
 448         struct net_device *netdev = dev_get_drvdata(dev);
 449         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 450         unsigned long event = *(unsigned long *)data;
 451
 452         switch (event) {
 453         case DCA_PROVIDER_ADD:
 454                 /* if we're already enabled, don't do it again */
 455                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 456                         break;
 457                 if (dca_add_requester(dev) == 0) {
 458                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 459                         ixgbe_setup_dca(adapter);
 460                         break;
 461                 }
 462                 /* Fall Through since DCA is disabled. */
 463         case DCA_PROVIDER_REMOVE:
 464                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 465                         dca_remove_requester(dev);
 466                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 467                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 468                 }
 469                 break;
 470         }
 471
 472         return 0;
 473 }
 474
 475 #endif /* CONFIG_IXGBE_DCA */
 476 /**
 477  * ixgbe_receive_skb - Send a completed packet up the stack
 478  * @adapter: board private structure
 479  * @skb: packet to send up
 480  * @status: hardware indication of status of receive
 481  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 482  * @rx_desc: rx descriptor
 483  **/
 484 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 485                               struct sk_buff *skb, u8 status,
 486                               struct ixgbe_ring *ring,
 487                               union ixgbe_adv_rx_desc *rx_desc)
 488 {
 489         struct ixgbe_adapter *adapter = q_vector->adapter;
 490         struct napi_struct *napi = &q_vector->napi;
 491         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 492         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 493
 494         skb_record_rx_queue(skb, ring->queue_index);
 495         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 496                 if (adapter->vlgrp && is_vlan && (tag != 0))
 497                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 498                 else
 499                         napi_gro_receive(napi, skb);
 500         } else {
 501                 if (adapter->vlgrp && is_vlan && (tag != 0))
 502                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 503                 else
 504                         netif_rx(skb);
 505         }
 506 }
 507
 508 /**
 509  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 510  * @adapter: address of board private structure
 511  * @status_err: hardware indication of status of receive
 512  * @skb: skb currently being received and modified
 513  **/
 514 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 515                                      u32 status_err, struct sk_buff *skb)
 516 {
 517         skb->ip_summed = CHECKSUM_NONE;
 518
 519         /* Rx csum disabled */
 520         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 521                 return;
 522
 523         /* if IP and error */
 524         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 525             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 526                 adapter->hw_csum_rx_error++;
 527                 return;
 528         }
 529
 530         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 531                 return;
 532
 533         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 534                 adapter->hw_csum_rx_error++;
 535                 return;
 536         }
 537
 538         /* It must be a TCP or UDP packet with a valid checksum */
 539         skb->ip_summed = CHECKSUM_UNNECESSARY;
 540         adapter->hw_csum_rx_good++;
 541 }
 542
 543 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 544                                          struct ixgbe_ring *rx_ring, u32 val)
 545 {
 546         /*
 547          * Force memory writes to complete before letting h/w
 548          * know there are new descriptors to fetch.  (Only
 549          * applicable for weak-ordered memory model archs,
 550          * such as IA-64).
 551          */
 552         wmb();
 553         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 554 }
 555
 556 /**
 557  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 558  * @adapter: address of board private structure
 559  **/
 560 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 561                                    struct ixgbe_ring *rx_ring,
 562                                    int cleaned_count)
 563 {
 564         struct pci_dev *pdev = adapter->pdev;
 565         union ixgbe_adv_rx_desc *rx_desc;
 566         struct ixgbe_rx_buffer *bi;
 567         unsigned int i;
 568
 569         i = rx_ring->next_to_use;
 570         bi = &rx_ring->rx_buffer_info[i];
 571
 572         while (cleaned_count--) {
 573                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 574
 575                 if (!bi->page_dma &&
 576                     (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
 577                         if (!bi->page) {
 578                                 bi->page = alloc_page(GFP_ATOMIC);
 579                                 if (!bi->page) {
 580                                         adapter->alloc_rx_page_failed++;
 581                                         goto no_buffers;
 582                                 }
 583                                 bi->page_offset = 0;
 584                         } else {
 585                                 /* use a half page if we're re-using */
 586                                 bi->page_offset ^= (PAGE_SIZE / 2);
 587                         }
 588
 589                         bi->page_dma = pci_map_page(pdev, bi->page,
 590                                                     bi->page_offset,
 591                                                     (PAGE_SIZE / 2),
 592                                                     PCI_DMA_FROMDEVICE);
 593                 }
 594
 595                 if (!bi->skb) {
 596                         struct sk_buff *skb;
 597                         skb = netdev_alloc_skb(adapter->netdev,
 598                                                (rx_ring->rx_buf_len +
 599                                                 NET_IP_ALIGN));
 600
 601                         if (!skb) {
 602                                 adapter->alloc_rx_buff_failed++;
 603                                 goto no_buffers;
 604                         }
 605
 606                         /*
 607                          * Make buffer alignment 2 beyond a 16 byte boundary
 608                          * this will result in a 16 byte aligned IP header after
 609                          * the 14 byte MAC header is removed
 610                          */
 611                         skb_reserve(skb, NET_IP_ALIGN);
 612
 613                         bi->skb = skb;
 614                         bi->dma = pci_map_single(pdev, skb->data,
 615                                                  rx_ring->rx_buf_len,
 616                                                  PCI_DMA_FROMDEVICE);
 617                 }
 618                 /* Refresh the desc even if buffer_addrs didn't change because
 619                  * each write-back erases this info. */
 620                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 621                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 622                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 623                 } else {
 624                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 625                 }
 626
 627                 i++;
 628                 if (i == rx_ring->count)
 629                         i = 0;
 630                 bi = &rx_ring->rx_buffer_info[i];
 631         }
 632
 633 no_buffers:
 634         if (rx_ring->next_to_use != i) {
 635                 rx_ring->next_to_use = i;
 636                 if (i-- == 0)
 637                         i = (rx_ring->count - 1);
 638
 639                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 640         }
 641 }
 642
 643 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 644 {
 645         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 646 }
 647
 648 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 649 {
 650         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 651 }
 652
 653 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 654 {
 655         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 656                 IXGBE_RXDADV_RSCCNT_MASK) >>
 657                 IXGBE_RXDADV_RSCCNT_SHIFT;
 658 }
 659
 660 /**
 661  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 662  * @skb: pointer to the last skb in the rsc queue
 663  *
 664  * This function changes a queue full of hw rsc buffers into a completed
 665  * packet.  It uses the ->prev pointers to find the first packet and then
 666  * turns it into the frag list owner.
 667  **/
 668 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 669 {
 670         unsigned int frag_list_size = 0;
 671
 672         while (skb->prev) {
 673                 struct sk_buff *prev = skb->prev;
 674                 frag_list_size += skb->len;
 675                 skb->prev = NULL;
 676                 skb = prev;
 677         }
 678
 679         skb_shinfo(skb)->frag_list = skb->next;
 680         skb->next = NULL;
 681         skb->len += frag_list_size;
 682         skb->data_len += frag_list_size;
 683         skb->truesize += frag_list_size;
 684         return skb;
 685 }
 686
 687 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 688                                struct ixgbe_ring *rx_ring,
 689                                int *work_done, int work_to_do)
 690 {
 691         struct ixgbe_adapter *adapter = q_vector->adapter;
 692         struct pci_dev *pdev = adapter->pdev;
 693         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 694         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 695         struct sk_buff *skb;
 696         unsigned int i, rsc_count = 0;
 697         u32 len, staterr;
 698         u16 hdr_info;
 699         bool cleaned = false;
 700         int cleaned_count = 0;
 701         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 702 #ifdef IXGBE_FCOE
 703         int ddp_bytes = 0;
 704 #endif /* IXGBE_FCOE */
 705
 706         i = rx_ring->next_to_clean;
 707         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 708         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 709         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 710
 711         while (staterr & IXGBE_RXD_STAT_DD) {
 712                 u32 upper_len = 0;
 713                 if (*work_done >= work_to_do)
 714                         break;
 715                 (*work_done)++;
 716
 717                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 718                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 719                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 720                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 721                         if (hdr_info & IXGBE_RXDADV_SPH)
 722                                 adapter->rx_hdr_split++;
 723                         if (len > IXGBE_RX_HDR_SIZE)
 724                                 len = IXGBE_RX_HDR_SIZE;
 725                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 726                 } else {
 727                         len = le16_to_cpu(rx_desc->wb.upper.length);
 728                 }
 729
 730                 cleaned = true;
 731                 skb = rx_buffer_info->skb;
 732                 prefetch(skb->data - NET_IP_ALIGN);
 733                 rx_buffer_info->skb = NULL;
 734
 735                 if (rx_buffer_info->dma) {
 736                         pci_unmap_single(pdev, rx_buffer_info->dma,
 737                                          rx_ring->rx_buf_len,
 738                                          PCI_DMA_FROMDEVICE);
 739                         rx_buffer_info->dma = 0;
 740                         skb_put(skb, len);
 741                 }
 742
 743                 if (upper_len) {
 744                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 745                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 746                         rx_buffer_info->page_dma = 0;
 747                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 748                                            rx_buffer_info->page,
 749                                            rx_buffer_info->page_offset,
 750                                            upper_len);
 751
 752                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 753                             (page_count(rx_buffer_info->page) != 1))
 754                                 rx_buffer_info->page = NULL;
 755                         else
 756                                 get_page(rx_buffer_info->page);
 757
 758                         skb->len += upper_len;
 759                         skb->data_len += upper_len;
 760                         skb->truesize += upper_len;
 761                 }
 762
 763                 i++;
 764                 if (i == rx_ring->count)
 765                         i = 0;
 766
 767                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 768                 prefetch(next_rxd);
 769                 cleaned_count++;
 770
 771                 if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
 772                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 773
 774                 if (rsc_count) {
 775                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 776                                      IXGBE_RXDADV_NEXTP_SHIFT;
 777                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 778                         rx_ring->rsc_count += (rsc_count - 1);
 779                 } else {
 780                         next_buffer = &rx_ring->rx_buffer_info[i];
 781                 }
 782
 783                 if (staterr & IXGBE_RXD_STAT_EOP) {
 784                         if (skb->prev)
 785                                 skb = ixgbe_transform_rsc_queue(skb);
 786                         rx_ring->stats.packets++;
 787                         rx_ring->stats.bytes += skb->len;
 788                 } else {
 789                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
 790                                 rx_buffer_info->skb = next_buffer->skb;
 791                                 rx_buffer_info->dma = next_buffer->dma;
 792                                 next_buffer->skb = skb;
 793                                 next_buffer->dma = 0;
 794                         } else {
 795                                 skb->next = next_buffer->skb;
 796                                 skb->next->prev = skb;
 797                         }
 798                         adapter->non_eop_descs++;
 799                         goto next_desc;
 800                 }
 801
 802                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 803                         dev_kfree_skb_irq(skb);
 804                         goto next_desc;
 805                 }
 806
 807                 ixgbe_rx_checksum(adapter, staterr, skb);
 808
 809                 /* probably a little skewed due to removing CRC */
 810                 total_rx_bytes += skb->len;
 811                 total_rx_packets++;
 812
 813                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 814 #ifdef IXGBE_FCOE
 815                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 816                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 817                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 818                         if (!ddp_bytes)
 819                                 goto next_desc;
 820                 }
 821 #endif /* IXGBE_FCOE */
 822                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 823
 824 next_desc:
 825                 rx_desc->wb.upper.status_error = 0;
 826
 827                 /* return some buffers to hardware, one at a time is too slow */
 828                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 829                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 830                         cleaned_count = 0;
 831                 }
 832
 833                 /* use prefetched values */
 834                 rx_desc = next_rxd;
 835                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 836
 837                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 838         }
 839
 840         rx_ring->next_to_clean = i;
 841         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 842
 843         if (cleaned_count)
 844                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 845
 846 #ifdef IXGBE_FCOE
 847         /* include DDPed FCoE data */
 848         if (ddp_bytes > 0) {
 849                 unsigned int mss;
 850
 851                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 852                         sizeof(struct fc_frame_header) -
 853                         sizeof(struct fcoe_crc_eof);
 854                 if (mss > 512)
 855                         mss &= ~511;
 856                 total_rx_bytes += ddp_bytes;
 857                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 858         }
 859 #endif /* IXGBE_FCOE */
 860
 861         rx_ring->total_packets += total_rx_packets;
 862         rx_ring->total_bytes += total_rx_bytes;
 863         adapter->net_stats.rx_bytes += total_rx_bytes;
 864         adapter->net_stats.rx_packets += total_rx_packets;
 865
 866         return cleaned;
 867 }
 868
 869 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 870 /**
 871  * ixgbe_configure_msix - Configure MSI-X hardware
 872  * @adapter: board private structure
 873  *
 874  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 875  * interrupts.
 876  **/
 877 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 878 {
 879         struct ixgbe_q_vector *q_vector;
 880         int i, j, q_vectors, v_idx, r_idx;
 881         u32 mask;
 882
 883         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 884
 885         /*
 886          * Populate the IVAR table and set the ITR values to the
 887          * corresponding register.
 888          */
 889         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 890                 q_vector = adapter->q_vector[v_idx];
 891                 /* XXX for_each_bit(...) */
 892                 r_idx = find_first_bit(q_vector->rxr_idx,
 893                                        adapter->num_rx_queues);
 894
 895                 for (i = 0; i < q_vector->rxr_count; i++) {
 896                         j = adapter->rx_ring[r_idx].reg_idx;
 897                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 898                         r_idx = find_next_bit(q_vector->rxr_idx,
 899                                               adapter->num_rx_queues,
 900                                               r_idx + 1);
 901                 }
 902                 r_idx = find_first_bit(q_vector->txr_idx,
 903                                        adapter->num_tx_queues);
 904
 905                 for (i = 0; i < q_vector->txr_count; i++) {
 906                         j = adapter->tx_ring[r_idx].reg_idx;
 907                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 908                         r_idx = find_next_bit(q_vector->txr_idx,
 909                                               adapter->num_tx_queues,
 910                                               r_idx + 1);
 911                 }
 912
 913                 /* if this is a tx only vector halve the interrupt rate */
 914                 if (q_vector->txr_count && !q_vector->rxr_count)
 915                         q_vector->eitr = (adapter->eitr_param >> 1);
 916                 else if (q_vector->rxr_count)
 917                         /* rx only */
 918                         q_vector->eitr = adapter->eitr_param;
 919
 920                 ixgbe_write_eitr(q_vector);
 921         }
 922
 923         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 924                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 925                                v_idx);
 926         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 927                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 928         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 929
 930         /* set up to autoclear timer, and the vectors */
 931         mask = IXGBE_EIMS_ENABLE_MASK;
 932         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 933         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 934 }
 935
 936 enum latency_range {
 937         lowest_latency = 0,
 938         low_latency = 1,
 939         bulk_latency = 2,
 940         latency_invalid = 255
 941 };
 942
 943 /**
 944  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 945  * @adapter: pointer to adapter
 946  * @eitr: eitr setting (ints per sec) to give last timeslice
 947  * @itr_setting: current throttle rate in ints/second
 948  * @packets: the number of packets during this measurement interval
 949  * @bytes: the number of bytes during this measurement interval
 950  *
 951  *      Stores a new ITR value based on packets and byte
 952  *      counts during the last interrupt.  The advantage of per interrupt
 953  *      computation is faster updates and more accurate ITR for the current
 954  *      traffic pattern.  Constants in this function were computed
 955  *      based on theoretical maximum wire speed and thresholds were set based
 956  *      on testing data as well as attempting to minimize response time
 957  *      while increasing bulk throughput.
 958  *      this functionality is controlled by the InterruptThrottleRate module
 959  *      parameter (see ixgbe_param.c)
 960  **/
 961 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 962                            u32 eitr, u8 itr_setting,
 963                            int packets, int bytes)
 964 {
 965         unsigned int retval = itr_setting;
 966         u32 timepassed_us;
 967         u64 bytes_perint;
 968
 969         if (packets == 0)
 970                 goto update_itr_done;
 971
 972
 973         /* simple throttlerate management
 974          *    0-20MB/s lowest (100000 ints/s)
 975          *   20-100MB/s low   (20000 ints/s)
 976          *  100-1249MB/s bulk (8000 ints/s)
 977          */
 978         /* what was last interrupt timeslice? */
 979         timepassed_us = 1000000/eitr;
 980         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 981
 982         switch (itr_setting) {
 983         case lowest_latency:
 984                 if (bytes_perint > adapter->eitr_low)
 985                         retval = low_latency;
 986                 break;
 987         case low_latency:
 988                 if (bytes_perint > adapter->eitr_high)
 989                         retval = bulk_latency;
 990                 else if (bytes_perint <= adapter->eitr_low)
 991                         retval = lowest_latency;
 992                 break;
 993         case bulk_latency:
 994                 if (bytes_perint <= adapter->eitr_high)
 995                         retval = low_latency;
 996                 break;
 997         }
 998
 999 update_itr_done:
1000         return retval;
1001 }
1002
1003 /**
1004  * ixgbe_write_eitr - write EITR register in hardware specific way
1005  * @q_vector: structure containing interrupt and ring information
1006  *
1007  * This function is made to be called by ethtool and by the driver
1008  * when it needs to update EITR registers at runtime.  Hardware
1009  * specific quirks/differences are taken care of here.
1010  */
1011 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1012 {
1013         struct ixgbe_adapter *adapter = q_vector->adapter;
1014         struct ixgbe_hw *hw = &adapter->hw;
1015         int v_idx = q_vector->v_idx;
1016         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1017
1018         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1019                 /* must write high and low 16 bits to reset counter */
1020                 itr_reg |= (itr_reg << 16);
1021         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1022                 /*
1023                  * set the WDIS bit to not clear the timer bits and cause an
1024                  * immediate assertion of the interrupt
1025                  */
1026                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1027         }
1028         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1029 }
1030
1031 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1032 {
1033         struct ixgbe_adapter *adapter = q_vector->adapter;
1034         u32 new_itr;
1035         u8 current_itr, ret_itr;
1036         int i, r_idx;
1037         struct ixgbe_ring *rx_ring, *tx_ring;
1038
1039         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1040         for (i = 0; i < q_vector->txr_count; i++) {
1041                 tx_ring = &(adapter->tx_ring[r_idx]);
1042                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1043                                            q_vector->tx_itr,
1044                                            tx_ring->total_packets,
1045                                            tx_ring->total_bytes);
1046                 /* if the result for this queue would decrease interrupt
1047                  * rate for this vector then use that result */
1048                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1049                                     q_vector->tx_itr - 1 : ret_itr);
1050                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1051                                       r_idx + 1);
1052         }
1053
1054         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1055         for (i = 0; i < q_vector->rxr_count; i++) {
1056                 rx_ring = &(adapter->rx_ring[r_idx]);
1057                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1058                                            q_vector->rx_itr,
1059                                            rx_ring->total_packets,
1060                                            rx_ring->total_bytes);
1061                 /* if the result for this queue would decrease interrupt
1062                  * rate for this vector then use that result */
1063                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1064                                     q_vector->rx_itr - 1 : ret_itr);
1065                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1066                                       r_idx + 1);
1067         }
1068
1069         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1070
1071         switch (current_itr) {
1072         /* counts and packets in update_itr are dependent on these numbers */
1073         case lowest_latency:
1074                 new_itr = 100000;
1075                 break;
1076         case low_latency:
1077                 new_itr = 20000; /* aka hwitr = ~200 */
1078                 break;
1079         case bulk_latency:
1080         default:
1081                 new_itr = 8000;
1082                 break;
1083         }
1084
1085         if (new_itr != q_vector->eitr) {
1086                 /* do an exponential smoothing */
1087                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1088
1089                 /* save the algorithm value here, not the smoothed one */
1090                 q_vector->eitr = new_itr;
1091
1092                 ixgbe_write_eitr(q_vector);
1093         }
1094
1095         return;
1096 }
1097
1098 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1099 {
1100         struct ixgbe_hw *hw = &adapter->hw;
1101
1102         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1103             (eicr & IXGBE_EICR_GPI_SDP1)) {
1104                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1105                 /* write to clear the interrupt */
1106                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1107         }
1108 }
1109
1110 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1111 {
1112         struct ixgbe_hw *hw = &adapter->hw;
1113
1114         if (eicr & IXGBE_EICR_GPI_SDP1) {
1115                 /* Clear the interrupt */
1116                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1117                 schedule_work(&adapter->multispeed_fiber_task);
1118         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1119                 /* Clear the interrupt */
1120                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1121                 schedule_work(&adapter->sfp_config_module_task);
1122         } else {
1123                 /* Interrupt isn't for us... */
1124                 return;
1125         }
1126 }
1127
1128 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1129 {
1130         struct ixgbe_hw *hw = &adapter->hw;
1131
1132         adapter->lsc_int++;
1133         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1134         adapter->link_check_timeout = jiffies;
1135         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1136                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1137                 schedule_work(&adapter->watchdog_task);
1138         }
1139 }
1140
1141 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1142 {
1143         struct net_device *netdev = data;
1144         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1145         struct ixgbe_hw *hw = &adapter->hw;
1146         u32 eicr;
1147
1148         /*
1149          * Workaround for Silicon errata.  Use clear-by-write instead
1150          * of clear-by-read.  Reading with EICS will return the
1151          * interrupt causes without clearing, which later be done
1152          * with the write to EICR.
1153          */
1154         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1155         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1156
1157         if (eicr & IXGBE_EICR_LSC)
1158                 ixgbe_check_lsc(adapter);
1159
1160         if (hw->mac.type == ixgbe_mac_82598EB)
1161                 ixgbe_check_fan_failure(adapter, eicr);
1162
1163         if (hw->mac.type == ixgbe_mac_82599EB) {
1164                 ixgbe_check_sfp_event(adapter, eicr);
1165
1166                 /* Handle Flow Director Full threshold interrupt */
1167                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1168                         int i;
1169                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1170                         /* Disable transmits before FDIR Re-initialization */
1171                         netif_tx_stop_all_queues(netdev);
1172                         for (i = 0; i < adapter->num_tx_queues; i++) {
1173                                 struct ixgbe_ring *tx_ring =
1174                                                            &adapter->tx_ring[i];
1175                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1176                                                        &tx_ring->reinit_state))
1177                                         schedule_work(&adapter->fdir_reinit_task);
1178                         }
1179                 }
1180         }
1181         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1182                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1183
1184         return IRQ_HANDLED;
1185 }
1186
1187 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1188                                            u64 qmask)
1189 {
1190         u32 mask;
1191
1192         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1193                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1194                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1195         } else {
1196                 mask = (qmask & 0xFFFFFFFF);
1197                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1198                 mask = (qmask >> 32);
1199                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1200         }
1201         /* skip the flush */
1202 }
1203
1204 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1205                                             u64 qmask)
1206 {
1207         u32 mask;
1208
1209         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1210                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1212         } else {
1213                 mask = (qmask & 0xFFFFFFFF);
1214                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1215                 mask = (qmask >> 32);
1216                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1217         }
1218         /* skip the flush */
1219 }
1220
1221 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1222 {
1223         struct ixgbe_q_vector *q_vector = data;
1224         struct ixgbe_adapter  *adapter = q_vector->adapter;
1225         struct ixgbe_ring     *tx_ring;
1226         int i, r_idx;
1227
1228         if (!q_vector->txr_count)
1229                 return IRQ_HANDLED;
1230
1231         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1232         for (i = 0; i < q_vector->txr_count; i++) {
1233                 tx_ring = &(adapter->tx_ring[r_idx]);
1234                 tx_ring->total_bytes = 0;
1235                 tx_ring->total_packets = 0;
1236                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1237                                       r_idx + 1);
1238         }
1239
1240         /* disable interrupts on this vector only */
1241         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1242         napi_schedule(&q_vector->napi);
1243
1244         return IRQ_HANDLED;
1245 }
1246
1247 /**
1248  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1249  * @irq: unused
1250  * @data: pointer to our q_vector struct for this interrupt vector
1251  **/
1252 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1253 {
1254         struct ixgbe_q_vector *q_vector = data;
1255         struct ixgbe_adapter  *adapter = q_vector->adapter;
1256         struct ixgbe_ring  *rx_ring;
1257         int r_idx;
1258         int i;
1259
1260         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1261         for (i = 0;  i < q_vector->rxr_count; i++) {
1262                 rx_ring = &(adapter->rx_ring[r_idx]);
1263                 rx_ring->total_bytes = 0;
1264                 rx_ring->total_packets = 0;
1265                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1266                                       r_idx + 1);
1267         }
1268
1269         if (!q_vector->rxr_count)
1270                 return IRQ_HANDLED;
1271
1272         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1273         rx_ring = &(adapter->rx_ring[r_idx]);
1274         /* disable interrupts on this vector only */
1275         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1276         napi_schedule(&q_vector->napi);
1277
1278         return IRQ_HANDLED;
1279 }
1280
1281 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1282 {
1283         struct ixgbe_q_vector *q_vector = data;
1284         struct ixgbe_adapter  *adapter = q_vector->adapter;
1285         struct ixgbe_ring  *ring;
1286         int r_idx;
1287         int i;
1288
1289         if (!q_vector->txr_count && !q_vector->rxr_count)
1290                 return IRQ_HANDLED;
1291
1292         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1293         for (i = 0; i < q_vector->txr_count; i++) {
1294                 ring = &(adapter->tx_ring[r_idx]);
1295                 ring->total_bytes = 0;
1296                 ring->total_packets = 0;
1297                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1298                                       r_idx + 1);
1299         }
1300
1301         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1302         for (i = 0; i < q_vector->rxr_count; i++) {
1303                 ring = &(adapter->rx_ring[r_idx]);
1304                 ring->total_bytes = 0;
1305                 ring->total_packets = 0;
1306                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1307                                       r_idx + 1);
1308         }
1309
1310         /* disable interrupts on this vector only */
1311         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1312         napi_schedule(&q_vector->napi);
1313
1314         return IRQ_HANDLED;
1315 }
1316
1317 /**
1318  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1319  * @napi: napi struct with our devices info in it
1320  * @budget: amount of work driver is allowed to do this pass, in packets
1321  *
1322  * This function is optimized for cleaning one queue only on a single
1323  * q_vector!!!
1324  **/
1325 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1326 {
1327         struct ixgbe_q_vector *q_vector =
1328                                container_of(napi, struct ixgbe_q_vector, napi);
1329         struct ixgbe_adapter *adapter = q_vector->adapter;
1330         struct ixgbe_ring *rx_ring = NULL;
1331         int work_done = 0;
1332         long r_idx;
1333
1334         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1335         rx_ring = &(adapter->rx_ring[r_idx]);
1336 #ifdef CONFIG_IXGBE_DCA
1337         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1338                 ixgbe_update_rx_dca(adapter, rx_ring);
1339 #endif
1340
1341         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1342
1343         /* If all Rx work done, exit the polling mode */
1344         if (work_done < budget) {
1345                 napi_complete(napi);
1346                 if (adapter->itr_setting & 1)
1347                         ixgbe_set_itr_msix(q_vector);
1348                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1349                         ixgbe_irq_enable_queues(adapter,
1350                                                 ((u64)1 << q_vector->v_idx));
1351         }
1352
1353         return work_done;
1354 }
1355
1356 /**
1357  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1358  * @napi: napi struct with our devices info in it
1359  * @budget: amount of work driver is allowed to do this pass, in packets
1360  *
1361  * This function will clean more than one rx queue associated with a
1362  * q_vector.
1363  **/
1364 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1365 {
1366         struct ixgbe_q_vector *q_vector =
1367                                container_of(napi, struct ixgbe_q_vector, napi);
1368         struct ixgbe_adapter *adapter = q_vector->adapter;
1369         struct ixgbe_ring *ring = NULL;
1370         int work_done = 0, i;
1371         long r_idx;
1372         bool tx_clean_complete = true;
1373
1374         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1375         for (i = 0; i < q_vector->txr_count; i++) {
1376                 ring = &(adapter->tx_ring[r_idx]);
1377 #ifdef CONFIG_IXGBE_DCA
1378                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1379                         ixgbe_update_tx_dca(adapter, ring);
1380 #endif
1381                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1382                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1383                                       r_idx + 1);
1384         }
1385
1386         /* attempt to distribute budget to each queue fairly, but don't allow
1387          * the budget to go below 1 because we'll exit polling */
1388         budget /= (q_vector->rxr_count ?: 1);
1389         budget = max(budget, 1);
1390         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1391         for (i = 0; i < q_vector->rxr_count; i++) {
1392                 ring = &(adapter->rx_ring[r_idx]);
1393 #ifdef CONFIG_IXGBE_DCA
1394                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1395                         ixgbe_update_rx_dca(adapter, ring);
1396 #endif
1397                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1398                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1399                                       r_idx + 1);
1400         }
1401
1402         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1403         ring = &(adapter->rx_ring[r_idx]);
1404         /* If all Rx work done, exit the polling mode */
1405         if (work_done < budget) {
1406                 napi_complete(napi);
1407                 if (adapter->itr_setting & 1)
1408                         ixgbe_set_itr_msix(q_vector);
1409                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1410                         ixgbe_irq_enable_queues(adapter,
1411                                                 ((u64)1 << q_vector->v_idx));
1412                 return 0;
1413         }
1414
1415         return work_done;
1416 }
1417
1418 /**
1419  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1420  * @napi: napi struct with our devices info in it
1421  * @budget: amount of work driver is allowed to do this pass, in packets
1422  *
1423  * This function is optimized for cleaning one queue only on a single
1424  * q_vector!!!
1425  **/
1426 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1427 {
1428         struct ixgbe_q_vector *q_vector =
1429                                container_of(napi, struct ixgbe_q_vector, napi);
1430         struct ixgbe_adapter *adapter = q_vector->adapter;
1431         struct ixgbe_ring *tx_ring = NULL;
1432         int work_done = 0;
1433         long r_idx;
1434
1435         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1436         tx_ring = &(adapter->tx_ring[r_idx]);
1437 #ifdef CONFIG_IXGBE_DCA
1438         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1439                 ixgbe_update_tx_dca(adapter, tx_ring);
1440 #endif
1441
1442         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1443                 work_done = budget;
1444
1445         /* If all Rx work done, exit the polling mode */
1446         if (work_done < budget) {
1447                 napi_complete(napi);
1448                 if (adapter->itr_setting & 1)
1449                         ixgbe_set_itr_msix(q_vector);
1450                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1451                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1452         }
1453
1454         return work_done;
1455 }
1456
1457 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1458                                      int r_idx)
1459 {
1460         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1461
1462         set_bit(r_idx, q_vector->rxr_idx);
1463         q_vector->rxr_count++;
1464 }
1465
1466 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1467                                      int t_idx)
1468 {
1469         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1470
1471         set_bit(t_idx, q_vector->txr_idx);
1472         q_vector->txr_count++;
1473 }
1474
1475 /**
1476  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1477  * @adapter: board private structure to initialize
1478  * @vectors: allotted vector count for descriptor rings
1479  *
1480  * This function maps descriptor rings to the queue-specific vectors
1481  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1482  * one vector per ring/queue, but on a constrained vector budget, we
1483  * group the rings as "efficiently" as possible.  You would add new
1484  * mapping configurations in here.
1485  **/
1486 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1487                                       int vectors)
1488 {
1489         int v_start = 0;
1490         int rxr_idx = 0, txr_idx = 0;
1491         int rxr_remaining = adapter->num_rx_queues;
1492         int txr_remaining = adapter->num_tx_queues;
1493         int i, j;
1494         int rqpv, tqpv;
1495         int err = 0;
1496
1497         /* No mapping required if MSI-X is disabled. */
1498         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1499                 goto out;
1500
1501         /*
1502          * The ideal configuration...
1503          * We have enough vectors to map one per queue.
1504          */
1505         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1506                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1507                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1508
1509                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1510                         map_vector_to_txq(adapter, v_start, txr_idx);
1511
1512                 goto out;
1513         }
1514
1515         /*
1516          * If we don't have enough vectors for a 1-to-1
1517          * mapping, we'll have to group them so there are
1518          * multiple queues per vector.
1519          */
1520         /* Re-adjusting *qpv takes care of the remainder. */
1521         for (i = v_start; i < vectors; i++) {
1522                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1523                 for (j = 0; j < rqpv; j++) {
1524                         map_vector_to_rxq(adapter, i, rxr_idx);
1525                         rxr_idx++;
1526                         rxr_remaining--;
1527                 }
1528         }
1529         for (i = v_start; i < vectors; i++) {
1530                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1531                 for (j = 0; j < tqpv; j++) {
1532                         map_vector_to_txq(adapter, i, txr_idx);
1533                         txr_idx++;
1534                         txr_remaining--;
1535                 }
1536         }
1537
1538 out:
1539         return err;
1540 }
1541
1542 /**
1543  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1544  * @adapter: board private structure
1545  *
1546  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1547  * interrupts from the kernel.
1548  **/
1549 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1550 {
1551         struct net_device *netdev = adapter->netdev;
1552         irqreturn_t (*handler)(int, void *);
1553         int i, vector, q_vectors, err;
1554         int ri=0, ti=0;
1555
1556         /* Decrement for Other and TCP Timer vectors */
1557         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1558
1559         /* Map the Tx/Rx rings to the vectors we were allotted. */
1560         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1561         if (err)
1562                 goto out;
1563
1564 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1565                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1566                          &ixgbe_msix_clean_many)
1567         for (vector = 0; vector < q_vectors; vector++) {
1568                 handler = SET_HANDLER(adapter->q_vector[vector]);
1569
1570                 if(handler == &ixgbe_msix_clean_rx) {
1571                         sprintf(adapter->name[vector], "%s-%s-%d",
1572                                 netdev->name, "rx", ri++);
1573                 }
1574                 else if(handler == &ixgbe_msix_clean_tx) {
1575                         sprintf(adapter->name[vector], "%s-%s-%d",
1576                                 netdev->name, "tx", ti++);
1577                 }
1578                 else
1579                         sprintf(adapter->name[vector], "%s-%s-%d",
1580                                 netdev->name, "TxRx", vector);
1581
1582                 err = request_irq(adapter->msix_entries[vector].vector,
1583                                   handler, 0, adapter->name[vector],
1584                                   adapter->q_vector[vector]);
1585                 if (err) {
1586                         DPRINTK(PROBE, ERR,
1587                                 "request_irq failed for MSIX interrupt "
1588                                 "Error: %d\n", err);
1589                         goto free_queue_irqs;
1590                 }
1591         }
1592
1593         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1594         err = request_irq(adapter->msix_entries[vector].vector,
1595                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1596         if (err) {
1597                 DPRINTK(PROBE, ERR,
1598                         "request_irq for msix_lsc failed: %d\n", err);
1599                 goto free_queue_irqs;
1600         }
1601
1602         return 0;
1603
1604 free_queue_irqs:
1605         for (i = vector - 1; i >= 0; i--)
1606                 free_irq(adapter->msix_entries[--vector].vector,
1607                          adapter->q_vector[i]);
1608         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1609         pci_disable_msix(adapter->pdev);
1610         kfree(adapter->msix_entries);
1611         adapter->msix_entries = NULL;
1612 out:
1613         return err;
1614 }
1615
1616 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1617 {
1618         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1619         u8 current_itr;
1620         u32 new_itr = q_vector->eitr;
1621         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1622         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1623
1624         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1625                                             q_vector->tx_itr,
1626                                             tx_ring->total_packets,
1627                                             tx_ring->total_bytes);
1628         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1629                                             q_vector->rx_itr,
1630                                             rx_ring->total_packets,
1631                                             rx_ring->total_bytes);
1632
1633         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1634
1635         switch (current_itr) {
1636         /* counts and packets in update_itr are dependent on these numbers */
1637         case lowest_latency:
1638                 new_itr = 100000;
1639                 break;
1640         case low_latency:
1641                 new_itr = 20000; /* aka hwitr = ~200 */
1642                 break;
1643         case bulk_latency:
1644                 new_itr = 8000;
1645                 break;
1646         default:
1647                 break;
1648         }
1649
1650         if (new_itr != q_vector->eitr) {
1651                 /* do an exponential smoothing */
1652                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1653
1654                 /* save the algorithm value here, not the smoothed one */
1655                 q_vector->eitr = new_itr;
1656
1657                 ixgbe_write_eitr(q_vector);
1658         }
1659
1660         return;
1661 }
1662
1663 /**
1664  * ixgbe_irq_enable - Enable default interrupt generation settings
1665  * @adapter: board private structure
1666  **/
1667 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1668 {
1669         u32 mask;
1670
1671         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1672         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1673                 mask |= IXGBE_EIMS_GPI_SDP1;
1674         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1675                 mask |= IXGBE_EIMS_ECC;
1676                 mask |= IXGBE_EIMS_GPI_SDP1;
1677                 mask |= IXGBE_EIMS_GPI_SDP2;
1678         }
1679         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1680             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1681                 mask |= IXGBE_EIMS_FLOW_DIR;
1682
1683         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1684         ixgbe_irq_enable_queues(adapter, ~0);
1685         IXGBE_WRITE_FLUSH(&adapter->hw);
1686 }
1687
1688 /**
1689  * ixgbe_intr - legacy mode Interrupt Handler
1690  * @irq: interrupt number
1691  * @data: pointer to a network interface device structure
1692  **/
1693 static irqreturn_t ixgbe_intr(int irq, void *data)
1694 {
1695         struct net_device *netdev = data;
1696         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1697         struct ixgbe_hw *hw = &adapter->hw;
1698         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1699         u32 eicr;
1700
1701         /*
1702          * Workaround for silicon errata.  Mask the interrupts
1703          * before the read of EICR.
1704          */
1705         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1706
1707         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1708          * therefore no explict interrupt disable is necessary */
1709         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1710         if (!eicr) {
1711                 /* shared interrupt alert!
1712                  * make sure interrupts are enabled because the read will
1713                  * have disabled interrupts due to EIAM */
1714                 ixgbe_irq_enable(adapter);
1715                 return IRQ_NONE;        /* Not our interrupt */
1716         }
1717
1718         if (eicr & IXGBE_EICR_LSC)
1719                 ixgbe_check_lsc(adapter);
1720
1721         if (hw->mac.type == ixgbe_mac_82599EB)
1722                 ixgbe_check_sfp_event(adapter, eicr);
1723
1724         ixgbe_check_fan_failure(adapter, eicr);
1725
1726         if (napi_schedule_prep(&(q_vector->napi))) {
1727                 adapter->tx_ring[0].total_packets = 0;
1728                 adapter->tx_ring[0].total_bytes = 0;
1729                 adapter->rx_ring[0].total_packets = 0;
1730                 adapter->rx_ring[0].total_bytes = 0;
1731                 /* would disable interrupts here but EIAM disabled it */
1732                 __napi_schedule(&(q_vector->napi));
1733         }
1734
1735         return IRQ_HANDLED;
1736 }
1737
1738 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1739 {
1740         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1741
1742         for (i = 0; i < q_vectors; i++) {
1743                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1744                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1745                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1746                 q_vector->rxr_count = 0;
1747                 q_vector->txr_count = 0;
1748         }
1749 }
1750
1751 /**
1752  * ixgbe_request_irq - initialize interrupts
1753  * @adapter: board private structure
1754  *
1755  * Attempts to configure interrupts using the best available
1756  * capabilities of the hardware and kernel.
1757  **/
1758 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1759 {
1760         struct net_device *netdev = adapter->netdev;
1761         int err;
1762
1763         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1764                 err = ixgbe_request_msix_irqs(adapter);
1765         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1766                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1767                                   netdev->name, netdev);
1768         } else {
1769                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1770                                   netdev->name, netdev);
1771         }
1772
1773         if (err)
1774                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1775
1776         return err;
1777 }
1778
1779 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1780 {
1781         struct net_device *netdev = adapter->netdev;
1782
1783         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1784                 int i, q_vectors;
1785
1786                 q_vectors = adapter->num_msix_vectors;
1787
1788                 i = q_vectors - 1;
1789                 free_irq(adapter->msix_entries[i].vector, netdev);
1790
1791                 i--;
1792                 for (; i >= 0; i--) {
1793                         free_irq(adapter->msix_entries[i].vector,
1794                                  adapter->q_vector[i]);
1795                 }
1796
1797                 ixgbe_reset_q_vectors(adapter);
1798         } else {
1799                 free_irq(adapter->pdev->irq, netdev);
1800         }
1801 }
1802
1803 /**
1804  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1805  * @adapter: board private structure
1806  **/
1807 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1808 {
1809         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1810                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1811         } else {
1812                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1813                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1814                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1815         }
1816         IXGBE_WRITE_FLUSH(&adapter->hw);
1817         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1818                 int i;
1819                 for (i = 0; i < adapter->num_msix_vectors; i++)
1820                         synchronize_irq(adapter->msix_entries[i].vector);
1821         } else {
1822                 synchronize_irq(adapter->pdev->irq);
1823         }
1824 }
1825
1826 /**
1827  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1828  *
1829  **/
1830 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1831 {
1832         struct ixgbe_hw *hw = &adapter->hw;
1833
1834         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1835                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1836
1837         ixgbe_set_ivar(adapter, 0, 0, 0);
1838         ixgbe_set_ivar(adapter, 1, 0, 0);
1839
1840         map_vector_to_rxq(adapter, 0, 0);
1841         map_vector_to_txq(adapter, 0, 0);
1842
1843         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1844 }
1845
1846 /**
1847  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1848  * @adapter: board private structure
1849  *
1850  * Configure the Tx unit of the MAC after a reset.
1851  **/
1852 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1853 {
1854         u64 tdba;
1855         struct ixgbe_hw *hw = &adapter->hw;
1856         u32 i, j, tdlen, txctrl;
1857
1858         /* Setup the HW Tx Head and Tail descriptor pointers */
1859         for (i = 0; i < adapter->num_tx_queues; i++) {
1860                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1861                 j = ring->reg_idx;
1862                 tdba = ring->dma;
1863                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1864                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1865                                 (tdba & DMA_BIT_MASK(32)));
1866                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1867                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1868                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1869                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1870                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1871                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1872                 /* Disable Tx Head Writeback RO bit, since this hoses
1873                  * bookkeeping if things aren't delivered in order.
1874                  */
1875                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1876                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1877                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1878         }
1879         if (hw->mac.type == ixgbe_mac_82599EB) {
1880                 /* We enable 8 traffic classes, DCB only */
1881                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1882                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1883                                         IXGBE_MTQC_8TC_8TQ));
1884         }
1885 }
1886
1887 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1888
1889 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1890 {
1891         struct ixgbe_ring *rx_ring;
1892         u32 srrctl;
1893         int queue0 = 0;
1894         unsigned long mask;
1895         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1896
1897         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1898                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1899                         int dcb_i = feature[RING_F_DCB].indices;
1900                         if (dcb_i == 8)
1901                                 queue0 = index >> 4;
1902                         else if (dcb_i == 4)
1903                                 queue0 = index >> 5;
1904                         else
1905                                 dev_err(&adapter->pdev->dev, "Invalid DCB "
1906                                         "configuration\n");
1907 #ifdef IXGBE_FCOE
1908                         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1909                                 struct ixgbe_ring_feature *f;
1910
1911                                 rx_ring = &adapter->rx_ring[queue0];
1912                                 f = &adapter->ring_feature[RING_F_FCOE];
1913                                 if ((queue0 == 0) && (index > rx_ring->reg_idx))
1914                                         queue0 = f->mask + index -
1915                                                  rx_ring->reg_idx - 1;
1916                         }
1917 #endif /* IXGBE_FCOE */
1918                 } else {
1919                         queue0 = index;
1920                 }
1921         } else {
1922                 mask = (unsigned long) feature[RING_F_RSS].mask;
1923                 queue0 = index & mask;
1924                 index = index & mask;
1925         }
1926
1927         rx_ring = &adapter->rx_ring[queue0];
1928
1929         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1930
1931         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1932         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1933
1934         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1935                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1936
1937         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1938 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1939                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1940 #else
1941                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1942 #endif
1943                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1944         } else {
1945                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1946                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1947                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1948         }
1949
1950         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1951 }
1952
1953 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1954 {
1955         u32 mrqc = 0;
1956         int mask;
1957
1958         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1959                 return mrqc;
1960
1961         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1962 #ifdef CONFIG_IXGBE_DCB
1963                                  | IXGBE_FLAG_DCB_ENABLED
1964 #endif
1965                                 );
1966
1967         switch (mask) {
1968         case (IXGBE_FLAG_RSS_ENABLED):
1969                 mrqc = IXGBE_MRQC_RSSEN;
1970                 break;
1971 #ifdef CONFIG_IXGBE_DCB
1972         case (IXGBE_FLAG_DCB_ENABLED):
1973                 mrqc = IXGBE_MRQC_RT8TCEN;
1974                 break;
1975 #endif /* CONFIG_IXGBE_DCB */
1976         default:
1977                 break;
1978         }
1979
1980         return mrqc;
1981 }
1982
1983 /**
1984  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1985  * @adapter: board private structure
1986  *
1987  * Configure the Rx unit of the MAC after a reset.
1988  **/
1989 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1990 {
1991         u64 rdba;
1992         struct ixgbe_hw *hw = &adapter->hw;
1993         struct net_device *netdev = adapter->netdev;
1994         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1995         int i, j;
1996         u32 rdlen, rxctrl, rxcsum;
1997         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1998                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1999                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2000         u32 fctrl, hlreg0;
2001         u32 reta = 0, mrqc = 0;
2002         u32 rdrxctl;
2003         u32 rscctrl;
2004         int rx_buf_len;
2005
2006         /* Decide whether to use packet split mode or not */
2007         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2008
2009 #ifdef IXGBE_FCOE
2010         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2011                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2012 #endif /* IXGBE_FCOE */
2013
2014         /* Set the RX buffer length according to the mode */
2015         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2016                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2017                 if (hw->mac.type == ixgbe_mac_82599EB) {
2018                         /* PSRTYPE must be initialized in 82599 */
2019                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2020                                       IXGBE_PSRTYPE_UDPHDR |
2021                                       IXGBE_PSRTYPE_IPV4HDR |
2022                                       IXGBE_PSRTYPE_IPV6HDR |
2023                                       IXGBE_PSRTYPE_L2HDR;
2024                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2025                 }
2026         } else {
2027                 if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
2028                     (netdev->mtu <= ETH_DATA_LEN))
2029                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2030                 else
2031                         rx_buf_len = ALIGN(max_frame, 1024);
2032         }
2033
2034         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2035         fctrl |= IXGBE_FCTRL_BAM;
2036         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2037         fctrl |= IXGBE_FCTRL_PMCF;
2038         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2039
2040         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2041         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2042                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2043         else
2044                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2045 #ifdef IXGBE_FCOE
2046         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2047                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2048 #endif
2049         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2050
2051         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2052         /* disable receives while setting up the descriptors */
2053         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2054         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2055
2056         /*
2057          * Setup the HW Rx Head and Tail Descriptor Pointers and
2058          * the Base and Length of the Rx Descriptor Ring
2059          */
2060         for (i = 0; i < adapter->num_rx_queues; i++) {
2061                 rdba = adapter->rx_ring[i].dma;
2062                 j = adapter->rx_ring[i].reg_idx;
2063                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2064                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2065                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2066                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2067                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2068                 adapter->rx_ring[i].head = IXGBE_RDH(j);
2069                 adapter->rx_ring[i].tail = IXGBE_RDT(j);
2070                 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
2071
2072 #ifdef IXGBE_FCOE
2073                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2074                         struct ixgbe_ring_feature *f;
2075                         f = &adapter->ring_feature[RING_F_FCOE];
2076                         if ((rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
2077                             (i >= f->mask) && (i < f->mask + f->indices))
2078                                 adapter->rx_ring[i].rx_buf_len =
2079                                         IXGBE_FCOE_JUMBO_FRAME_SIZE;
2080                 }
2081
2082 #endif /* IXGBE_FCOE */
2083                 ixgbe_configure_srrctl(adapter, j);
2084         }
2085
2086         if (hw->mac.type == ixgbe_mac_82598EB) {
2087                 /*
2088                  * For VMDq support of different descriptor types or
2089                  * buffer sizes through the use of multiple SRRCTL
2090                  * registers, RDRXCTL.MVMEN must be set to 1
2091                  *
2092                  * also, the manual doesn't mention it clearly but DCA hints
2093                  * will only use queue 0's tags unless this bit is set.  Side
2094                  * effects of setting this bit are only that SRRCTL must be
2095                  * fully programmed [0..15]
2096                  */
2097                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2098                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2099                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2100         }
2101
2102         /* Program MRQC for the distribution of queues */
2103         mrqc = ixgbe_setup_mrqc(adapter);
2104
2105         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2106                 /* Fill out redirection table */
2107                 for (i = 0, j = 0; i < 128; i++, j++) {
2108                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2109                                 j = 0;
2110                         /* reta = 4-byte sliding window of
2111                          * 0x00..(indices-1)(indices-1)00..etc. */
2112                         reta = (reta << 8) | (j * 0x11);
2113                         if ((i & 3) == 3)
2114                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2115                 }
2116
2117                 /* Fill out hash function seeds */
2118                 for (i = 0; i < 10; i++)
2119                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2120
2121                 if (hw->mac.type == ixgbe_mac_82598EB)
2122                         mrqc |= IXGBE_MRQC_RSSEN;
2123                     /* Perform hash on these packet types */
2124                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2125                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2126                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2127                       | IXGBE_MRQC_RSS_FIELD_IPV6
2128                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2129                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2130         }
2131         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2132
2133         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2134
2135         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2136             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2137                 /* Disable indicating checksum in descriptor, enables
2138                  * RSS hash */
2139                 rxcsum |= IXGBE_RXCSUM_PCSD;
2140         }
2141         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2142                 /* Enable IPv4 payload checksum for UDP fragments
2143                  * if PCSD is not set */
2144                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2145         }
2146
2147         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2148
2149         if (hw->mac.type == ixgbe_mac_82599EB) {
2150                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2151                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2152                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2153                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2154         }
2155
2156         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
2157                 /* Enable 82599 HW-RSC */
2158                 for (i = 0; i < adapter->num_rx_queues; i++) {
2159                         j = adapter->rx_ring[i].reg_idx;
2160                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2161                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2162                         /*
2163                          * we must limit the number of descriptors so that the
2164                          * total size of max desc * buf_len is not greater
2165                          * than 65535
2166                          */
2167                         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2168 #if (MAX_SKB_FRAGS > 16)
2169                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2170 #elif (MAX_SKB_FRAGS > 8)
2171                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2172 #elif (MAX_SKB_FRAGS > 4)
2173                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2174 #else
2175                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2176 #endif
2177                         } else {
2178                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2179                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2180                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2181                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2182                                 else
2183                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2184                         }
2185                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2186                 }
2187                 /* Disable RSC for ACK packets */
2188                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2189                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2190         }
2191 }
2192
2193 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2194 {
2195         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2196         struct ixgbe_hw *hw = &adapter->hw;
2197
2198         /* add VID to filter table */
2199         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2200 }
2201
2202 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2203 {
2204         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2205         struct ixgbe_hw *hw = &adapter->hw;
2206
2207         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2208                 ixgbe_irq_disable(adapter);
2209
2210         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2211
2212         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2213                 ixgbe_irq_enable(adapter);
2214
2215         /* remove VID from filter table */
2216         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2217 }
2218
2219 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2220                                    struct vlan_group *grp)
2221 {
2222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2223         u32 ctrl;
2224         int i, j;
2225
2226         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2227                 ixgbe_irq_disable(adapter);
2228         adapter->vlgrp = grp;
2229
2230         /*
2231          * For a DCB driver, always enable VLAN tag stripping so we can
2232          * still receive traffic from a DCB-enabled host even if we're
2233          * not in DCB mode.
2234          */
2235         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2236         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2237                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2238                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2239                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2240         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2241                 ctrl |= IXGBE_VLNCTRL_VFE;
2242                 /* enable VLAN tag insert/strip */
2243                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2244                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2245                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2246                 for (i = 0; i < adapter->num_rx_queues; i++) {
2247                         j = adapter->rx_ring[i].reg_idx;
2248                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2249                         ctrl |= IXGBE_RXDCTL_VME;
2250                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2251                 }
2252         }
2253         ixgbe_vlan_rx_add_vid(netdev, 0);
2254
2255         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2256                 ixgbe_irq_enable(adapter);
2257 }
2258
2259 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2260 {
2261         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2262
2263         if (adapter->vlgrp) {
2264                 u16 vid;
2265                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2266                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2267                                 continue;
2268                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2269                 }
2270         }
2271 }
2272
2273 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2274 {
2275         struct dev_mc_list *mc_ptr;
2276         u8 *addr = *mc_addr_ptr;
2277         *vmdq = 0;
2278
2279         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2280         if (mc_ptr->next)
2281                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2282         else
2283                 *mc_addr_ptr = NULL;
2284
2285         return addr;
2286 }
2287
2288 /**
2289  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2290  * @netdev: network interface device structure
2291  *
2292  * The set_rx_method entry point is called whenever the unicast/multicast
2293  * address list or the network interface flags are updated.  This routine is
2294  * responsible for configuring the hardware for proper unicast, multicast and
2295  * promiscuous mode.
2296  **/
2297 static void ixgbe_set_rx_mode(struct net_device *netdev)
2298 {
2299         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2300         struct ixgbe_hw *hw = &adapter->hw;
2301         u32 fctrl, vlnctrl;
2302         u8 *addr_list = NULL;
2303         int addr_count = 0;
2304
2305         /* Check for Promiscuous and All Multicast modes */
2306
2307         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2308         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2309
2310         if (netdev->flags & IFF_PROMISC) {
2311                 hw->addr_ctrl.user_set_promisc = 1;
2312                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2313                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2314         } else {
2315                 if (netdev->flags & IFF_ALLMULTI) {
2316                         fctrl |= IXGBE_FCTRL_MPE;
2317                         fctrl &= ~IXGBE_FCTRL_UPE;
2318                 } else {
2319                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2320                 }
2321                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2322                 hw->addr_ctrl.user_set_promisc = 0;
2323         }
2324
2325         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2326         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2327
2328         /* reprogram secondary unicast list */
2329         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2330
2331         /* reprogram multicast list */
2332         addr_count = netdev->mc_count;
2333         if (addr_count)
2334                 addr_list = netdev->mc_list->dmi_addr;
2335         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2336                                         ixgbe_addr_list_itr);
2337 }
2338
2339 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2340 {
2341         int q_idx;
2342         struct ixgbe_q_vector *q_vector;
2343         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2344
2345         /* legacy and MSI only use one vector */
2346         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2347                 q_vectors = 1;
2348
2349         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2350                 struct napi_struct *napi;
2351                 q_vector = adapter->q_vector[q_idx];
2352                 napi = &q_vector->napi;
2353                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2354                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2355                                 if (q_vector->txr_count == 1)
2356                                         napi->poll = &ixgbe_clean_txonly;
2357                                 else if (q_vector->rxr_count == 1)
2358                                         napi->poll = &ixgbe_clean_rxonly;
2359                         }
2360                 }
2361
2362                 napi_enable(napi);
2363         }
2364 }
2365
2366 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2367 {
2368         int q_idx;
2369         struct ixgbe_q_vector *q_vector;
2370         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2371
2372         /* legacy and MSI only use one vector */
2373         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2374                 q_vectors = 1;
2375
2376         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2377                 q_vector = adapter->q_vector[q_idx];
2378                 napi_disable(&q_vector->napi);
2379         }
2380 }
2381
2382 #ifdef CONFIG_IXGBE_DCB
2383 /*
2384  * ixgbe_configure_dcb - Configure DCB hardware
2385  * @adapter: ixgbe adapter struct
2386  *
2387  * This is called by the driver on open to configure the DCB hardware.
2388  * This is also called by the gennetlink interface when reconfiguring
2389  * the DCB state.
2390  */
2391 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2392 {
2393         struct ixgbe_hw *hw = &adapter->hw;
2394         u32 txdctl, vlnctrl;
2395         int i, j;
2396
2397         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2398         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2399         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2400
2401         /* reconfigure the hardware */
2402         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2403
2404         for (i = 0; i < adapter->num_tx_queues; i++) {
2405                 j = adapter->tx_ring[i].reg_idx;
2406                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2407                 /* PThresh workaround for Tx hang with DFP enabled. */
2408                 txdctl |= 32;
2409                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2410         }
2411         /* Enable VLAN tag insert/strip */
2412         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2413         if (hw->mac.type == ixgbe_mac_82598EB) {
2414                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2415                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2416                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2417         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2418                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2419                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2420                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2421                 for (i = 0; i < adapter->num_rx_queues; i++) {
2422                         j = adapter->rx_ring[i].reg_idx;
2423                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2424                         vlnctrl |= IXGBE_RXDCTL_VME;
2425                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2426                 }
2427         }
2428         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2429 }
2430
2431 #endif
2432 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2433 {
2434         struct net_device *netdev = adapter->netdev;
2435         struct ixgbe_hw *hw = &adapter->hw;
2436         int i;
2437
2438         ixgbe_set_rx_mode(netdev);
2439
2440         ixgbe_restore_vlan(adapter);
2441 #ifdef CONFIG_IXGBE_DCB
2442         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2443                 netif_set_gso_max_size(netdev, 32768);
2444                 ixgbe_configure_dcb(adapter);
2445         } else {
2446                 netif_set_gso_max_size(netdev, 65536);
2447         }
2448 #else
2449         netif_set_gso_max_size(netdev, 65536);
2450 #endif
2451
2452 #ifdef IXGBE_FCOE
2453         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2454                 ixgbe_configure_fcoe(adapter);
2455
2456 #endif /* IXGBE_FCOE */
2457         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2458                 for (i = 0; i < adapter->num_tx_queues; i++)
2459                         adapter->tx_ring[i].atr_sample_rate =
2460                                                        adapter->atr_sample_rate;
2461                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2462         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2463                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2464         }
2465
2466         ixgbe_configure_tx(adapter);
2467         ixgbe_configure_rx(adapter);
2468         for (i = 0; i < adapter->num_rx_queues; i++)
2469                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2470                                        (adapter->rx_ring[i].count - 1));
2471 }
2472
2473 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2474 {
2475         switch (hw->phy.type) {
2476         case ixgbe_phy_sfp_avago:
2477         case ixgbe_phy_sfp_ftl:
2478         case ixgbe_phy_sfp_intel:
2479         case ixgbe_phy_sfp_unknown:
2480         case ixgbe_phy_tw_tyco:
2481         case ixgbe_phy_tw_unknown:
2482                 return true;
2483         default:
2484                 return false;
2485         }
2486 }
2487
2488 /**
2489  * ixgbe_sfp_link_config - set up SFP+ link
2490  * @adapter: pointer to private adapter struct
2491  **/
2492 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2493 {
2494         struct ixgbe_hw *hw = &adapter->hw;
2495
2496                 if (hw->phy.multispeed_fiber) {
2497                         /*
2498                          * In multispeed fiber setups, the device may not have
2499                          * had a physical connection when the driver loaded.
2500                          * If that's the case, the initial link configuration
2501                          * couldn't get the MAC into 10G or 1G mode, so we'll
2502                          * never have a link status change interrupt fire.
2503                          * We need to try and force an autonegotiation
2504                          * session, then bring up link.
2505                          */
2506                         hw->mac.ops.setup_sfp(hw);
2507                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2508                                 schedule_work(&adapter->multispeed_fiber_task);
2509                 } else {
2510                         /*
2511                          * Direct Attach Cu and non-multispeed fiber modules
2512                          * still need to be configured properly prior to
2513                          * attempting link.
2514                          */
2515                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2516                                 schedule_work(&adapter->sfp_config_module_task);
2517                 }
2518 }
2519
2520 /**
2521  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2522  * @hw: pointer to private hardware struct
2523  *
2524  * Returns 0 on success, negative on failure
2525  **/
2526 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2527 {
2528         u32 autoneg;
2529         bool link_up = false;
2530         u32 ret = IXGBE_ERR_LINK_SETUP;
2531
2532         if (hw->mac.ops.check_link)
2533                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2534
2535         if (ret)
2536                 goto link_cfg_out;
2537
2538         if (hw->mac.ops.get_link_capabilities)
2539                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2540                                                         &hw->mac.autoneg);
2541         if (ret)
2542                 goto link_cfg_out;
2543
2544         if (hw->mac.ops.setup_link_speed)
2545                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2546 link_cfg_out:
2547         return ret;
2548 }
2549
2550 #define IXGBE_MAX_RX_DESC_POLL 10
2551 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2552                                               int rxr)
2553 {
2554         int j = adapter->rx_ring[rxr].reg_idx;
2555         int k;
2556
2557         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2558                 if (IXGBE_READ_REG(&adapter->hw,
2559                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2560                         break;
2561                 else
2562                         msleep(1);
2563         }
2564         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2565                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2566                         "not set within the polling period\n", rxr);
2567         }
2568         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2569                               (adapter->rx_ring[rxr].count - 1));
2570 }
2571
2572 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2573 {
2574         struct net_device *netdev = adapter->netdev;
2575         struct ixgbe_hw *hw = &adapter->hw;
2576         int i, j = 0;
2577         int num_rx_rings = adapter->num_rx_queues;
2578         int err;
2579         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2580         u32 txdctl, rxdctl, mhadd;
2581         u32 dmatxctl;
2582         u32 gpie;
2583
2584         ixgbe_get_hw_control(adapter);
2585
2586         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2587             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2588                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2589                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2590                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2591                 } else {
2592                         /* MSI only */
2593                         gpie = 0;
2594                 }
2595                 /* XXX: to interrupt immediately for EICS writes, enable this */
2596                 /* gpie |= IXGBE_GPIE_EIMEN; */
2597                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2598         }
2599
2600         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2601                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2602                  * specifically only auto mask tx and rx interrupts */
2603                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2604         }
2605
2606         /* Enable fan failure interrupt if media type is copper */
2607         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2608                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2609                 gpie |= IXGBE_SDP1_GPIEN;
2610                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2611         }
2612
2613         if (hw->mac.type == ixgbe_mac_82599EB) {
2614                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2615                 gpie |= IXGBE_SDP1_GPIEN;
2616                 gpie |= IXGBE_SDP2_GPIEN;
2617                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2618         }
2619
2620 #ifdef IXGBE_FCOE
2621         /* adjust max frame to be able to do baby jumbo for FCoE */
2622         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2623             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2624                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2625
2626 #endif /* IXGBE_FCOE */
2627         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2628         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2629                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2630                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2631
2632                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2633         }
2634
2635         for (i = 0; i < adapter->num_tx_queues; i++) {
2636                 j = adapter->tx_ring[i].reg_idx;
2637                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2638                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2639                 txdctl |= (8 << 16);
2640                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2641         }
2642
2643         if (hw->mac.type == ixgbe_mac_82599EB) {
2644                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2645                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2646                 dmatxctl |= IXGBE_DMATXCTL_TE;
2647                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2648         }
2649         for (i = 0; i < adapter->num_tx_queues; i++) {
2650                 j = adapter->tx_ring[i].reg_idx;
2651                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2652                 txdctl |= IXGBE_TXDCTL_ENABLE;
2653                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2654         }
2655
2656         for (i = 0; i < num_rx_rings; i++) {
2657                 j = adapter->rx_ring[i].reg_idx;
2658                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2659                 /* enable PTHRESH=32 descriptors (half the internal cache)
2660                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2661                  * this also removes a pesky rx_no_buffer_count increment */
2662                 rxdctl |= 0x0020;
2663                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2664                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2665                 if (hw->mac.type == ixgbe_mac_82599EB)
2666                         ixgbe_rx_desc_queue_enable(adapter, i);
2667         }
2668         /* enable all receives */
2669         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2670         if (hw->mac.type == ixgbe_mac_82598EB)
2671                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2672         else
2673                 rxdctl |= IXGBE_RXCTRL_RXEN;
2674         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2675
2676         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2677                 ixgbe_configure_msix(adapter);
2678         else
2679                 ixgbe_configure_msi_and_legacy(adapter);
2680
2681         clear_bit(__IXGBE_DOWN, &adapter->state);
2682         ixgbe_napi_enable_all(adapter);
2683
2684         /* clear any pending interrupts, may auto mask */
2685         IXGBE_READ_REG(hw, IXGBE_EICR);
2686
2687         ixgbe_irq_enable(adapter);
2688
2689         /*
2690          * If this adapter has a fan, check to see if we had a failure
2691          * before we enabled the interrupt.
2692          */
2693         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2694                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2695                 if (esdp & IXGBE_ESDP_SDP1)
2696                         DPRINTK(DRV, CRIT,
2697                                 "Fan has stopped, replace the adapter\n");
2698         }
2699
2700         /*
2701          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2702          * arrived before interrupts were enabled but after probe.  Such
2703          * devices wouldn't have their type identified yet. We need to
2704          * kick off the SFP+ module setup first, then try to bring up link.
2705          * If we're not hot-pluggable SFP+, we just need to configure link
2706          * and bring it up.
2707          */
2708         if (hw->phy.type == ixgbe_phy_unknown) {
2709                 err = hw->phy.ops.identify(hw);
2710                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2711                         /*
2712                          * Take the device down and schedule the sfp tasklet
2713                          * which will unregister_netdev and log it.
2714                          */
2715                         ixgbe_down(adapter);
2716                         schedule_work(&adapter->sfp_config_module_task);
2717                         return err;
2718                 }
2719         }
2720
2721         if (ixgbe_is_sfp(hw)) {
2722                 ixgbe_sfp_link_config(adapter);
2723         } else {
2724                 err = ixgbe_non_sfp_link_config(hw);
2725                 if (err)
2726                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2727         }
2728
2729         for (i = 0; i < adapter->num_tx_queues; i++)
2730                 set_bit(__IXGBE_FDIR_INIT_DONE,
2731                         &(adapter->tx_ring[i].reinit_state));
2732
2733         /* enable transmits */
2734         netif_tx_start_all_queues(netdev);
2735
2736         /* bring the link up in the watchdog, this could race with our first
2737          * link up interrupt but shouldn't be a problem */
2738         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2739         adapter->link_check_timeout = jiffies;
2740         mod_timer(&adapter->watchdog_timer, jiffies);
2741         return 0;
2742 }
2743
2744 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2745 {
2746         WARN_ON(in_interrupt());
2747         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2748                 msleep(1);
2749         ixgbe_down(adapter);
2750         ixgbe_up(adapter);
2751         clear_bit(__IXGBE_RESETTING, &adapter->state);
2752 }
2753
2754 int ixgbe_up(struct ixgbe_adapter *adapter)
2755 {
2756         /* hardware has been reset, we need to reload some things */
2757         ixgbe_configure(adapter);
2758
2759         return ixgbe_up_complete(adapter);
2760 }
2761
2762 void ixgbe_reset(struct ixgbe_adapter *adapter)
2763 {
2764         struct ixgbe_hw *hw = &adapter->hw;
2765         int err;
2766
2767         err = hw->mac.ops.init_hw(hw);
2768         switch (err) {
2769         case 0:
2770         case IXGBE_ERR_SFP_NOT_PRESENT:
2771                 break;
2772         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2773                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2774                 break;
2775         case IXGBE_ERR_EEPROM_VERSION:
2776                 /* We are running on a pre-production device, log a warning */
2777                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2778                          "adapter/LOM.  Please be aware there may be issues "
2779                          "associated with your hardware.  If you are "
2780                          "experiencing problems please contact your Intel or "
2781                          "hardware representative who provided you with this "
2782                          "hardware.\n");
2783                 break;
2784         default:
2785                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2786         }
2787
2788         /* reprogram the RAR[0] in case user changed it. */
2789         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2790 }
2791
2792 /**
2793  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2794  * @adapter: board private structure
2795  * @rx_ring: ring to free buffers from
2796  **/
2797 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2798                                 struct ixgbe_ring *rx_ring)
2799 {
2800         struct pci_dev *pdev = adapter->pdev;
2801         unsigned long size;
2802         unsigned int i;
2803
2804         /* Free all the Rx ring sk_buffs */
2805
2806         for (i = 0; i < rx_ring->count; i++) {
2807                 struct ixgbe_rx_buffer *rx_buffer_info;
2808
2809                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2810                 if (rx_buffer_info->dma) {
2811                         pci_unmap_single(pdev, rx_buffer_info->dma,
2812                                          rx_ring->rx_buf_len,
2813                                          PCI_DMA_FROMDEVICE);
2814                         rx_buffer_info->dma = 0;
2815                 }
2816                 if (rx_buffer_info->skb) {
2817                         struct sk_buff *skb = rx_buffer_info->skb;
2818                         rx_buffer_info->skb = NULL;
2819                         do {
2820                                 struct sk_buff *this = skb;
2821                                 skb = skb->prev;
2822                                 dev_kfree_skb(this);
2823                         } while (skb);
2824                 }
2825                 if (!rx_buffer_info->page)
2826                         continue;
2827                 if (rx_buffer_info->page_dma) {
2828                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2829                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2830                         rx_buffer_info->page_dma = 0;
2831                 }
2832                 put_page(rx_buffer_info->page);
2833                 rx_buffer_info->page = NULL;
2834                 rx_buffer_info->page_offset = 0;
2835         }
2836
2837         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2838         memset(rx_ring->rx_buffer_info, 0, size);
2839
2840         /* Zero out the descriptor ring */
2841         memset(rx_ring->desc, 0, rx_ring->size);
2842
2843         rx_ring->next_to_clean = 0;
2844         rx_ring->next_to_use = 0;
2845
2846         if (rx_ring->head)
2847                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2848         if (rx_ring->tail)
2849                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2850 }
2851
2852 /**
2853  * ixgbe_clean_tx_ring - Free Tx Buffers
2854  * @adapter: board private structure
2855  * @tx_ring: ring to be cleaned
2856  **/
2857 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2858                                 struct ixgbe_ring *tx_ring)
2859 {
2860         struct ixgbe_tx_buffer *tx_buffer_info;
2861         unsigned long size;
2862         unsigned int i;
2863
2864         /* Free all the Tx ring sk_buffs */
2865
2866         for (i = 0; i < tx_ring->count; i++) {
2867                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2868                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2869         }
2870
2871         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2872         memset(tx_ring->tx_buffer_info, 0, size);
2873
2874         /* Zero out the descriptor ring */
2875         memset(tx_ring->desc, 0, tx_ring->size);
2876
2877         tx_ring->next_to_use = 0;
2878         tx_ring->next_to_clean = 0;
2879
2880         if (tx_ring->head)
2881                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2882         if (tx_ring->tail)
2883                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2884 }
2885
2886 /**
2887  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2888  * @adapter: board private structure
2889  **/
2890 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2891 {
2892         int i;
2893
2894         for (i = 0; i < adapter->num_rx_queues; i++)
2895                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2896 }
2897
2898 /**
2899  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2900  * @adapter: board private structure
2901  **/
2902 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2903 {
2904         int i;
2905
2906         for (i = 0; i < adapter->num_tx_queues; i++)
2907                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2908 }
2909
2910 void ixgbe_down(struct ixgbe_adapter *adapter)
2911 {
2912         struct net_device *netdev = adapter->netdev;
2913         struct ixgbe_hw *hw = &adapter->hw;
2914         u32 rxctrl;
2915         u32 txdctl;
2916         int i, j;
2917
2918         /* signal that we are down to the interrupt handler */
2919         set_bit(__IXGBE_DOWN, &adapter->state);
2920
2921         /* disable receives */
2922         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2923         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2924
2925         netif_tx_disable(netdev);
2926
2927         IXGBE_WRITE_FLUSH(hw);
2928         msleep(10);
2929
2930         netif_tx_stop_all_queues(netdev);
2931
2932         ixgbe_irq_disable(adapter);
2933
2934         ixgbe_napi_disable_all(adapter);
2935
2936         del_timer_sync(&adapter->watchdog_timer);
2937         cancel_work_sync(&adapter->watchdog_task);
2938
2939         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2940             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2941                 cancel_work_sync(&adapter->fdir_reinit_task);
2942
2943         /* disable transmits in the hardware now that interrupts are off */
2944         for (i = 0; i < adapter->num_tx_queues; i++) {
2945                 j = adapter->tx_ring[i].reg_idx;
2946                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2947                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2948                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2949         }
2950         /* Disable the Tx DMA engine on 82599 */
2951         if (hw->mac.type == ixgbe_mac_82599EB)
2952                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2953                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2954                                  ~IXGBE_DMATXCTL_TE));
2955
2956         netif_carrier_off(netdev);
2957
2958         if (!pci_channel_offline(adapter->pdev))
2959                 ixgbe_reset(adapter);
2960         ixgbe_clean_all_tx_rings(adapter);
2961         ixgbe_clean_all_rx_rings(adapter);
2962
2963 #ifdef CONFIG_IXGBE_DCA
2964         /* since we reset the hardware DCA settings were cleared */
2965         ixgbe_setup_dca(adapter);
2966 #endif
2967 }
2968
2969 /**
2970  * ixgbe_poll - NAPI Rx polling callback
2971  * @napi: structure for representing this polling device
2972  * @budget: how many packets driver is allowed to clean
2973  *
2974  * This function is used for legacy and MSI, NAPI mode
2975  **/
2976 static int ixgbe_poll(struct napi_struct *napi, int budget)
2977 {
2978         struct ixgbe_q_vector *q_vector =
2979                                 container_of(napi, struct ixgbe_q_vector, napi);
2980         struct ixgbe_adapter *adapter = q_vector->adapter;
2981         int tx_clean_complete, work_done = 0;
2982
2983 #ifdef CONFIG_IXGBE_DCA
2984         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2985                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2986                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2987         }
2988 #endif
2989
2990         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2991         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2992
2993         if (!tx_clean_complete)
2994                 work_done = budget;
2995
2996         /* If budget not fully consumed, exit the polling mode */
2997         if (work_done < budget) {
2998                 napi_complete(napi);
2999                 if (adapter->itr_setting & 1)
3000                         ixgbe_set_itr(adapter);
3001                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3002                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3003         }
3004         return work_done;
3005 }
3006
3007 /**
3008  * ixgbe_tx_timeout - Respond to a Tx Hang
3009  * @netdev: network interface device structure
3010  **/
3011 static void ixgbe_tx_timeout(struct net_device *netdev)
3012 {
3013         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3014
3015         /* Do the reset outside of interrupt context */
3016         schedule_work(&adapter->reset_task);
3017 }
3018
3019 static void ixgbe_reset_task(struct work_struct *work)
3020 {
3021         struct ixgbe_adapter *adapter;
3022         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3023
3024         /* If we're already down or resetting, just bail */
3025         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3026             test_bit(__IXGBE_RESETTING, &adapter->state))
3027                 return;
3028
3029         adapter->tx_timeout_count++;
3030
3031         ixgbe_reinit_locked(adapter);
3032 }
3033
3034 #ifdef CONFIG_IXGBE_DCB
3035 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3036 {
3037         bool ret = false;
3038         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3039
3040         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3041                 return ret;
3042
3043         f->mask = 0x7 << 3;
3044         adapter->num_rx_queues = f->indices;
3045         adapter->num_tx_queues = f->indices;
3046         ret = true;
3047
3048         return ret;
3049 }
3050 #endif
3051
3052 /**
3053  * ixgbe_set_rss_queues: Allocate queues for RSS
3054  * @adapter: board private structure to initialize
3055  *
3056  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3057  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3058  *
3059  **/
3060 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3061 {
3062         bool ret = false;
3063         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3064
3065         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3066                 f->mask = 0xF;
3067                 adapter->num_rx_queues = f->indices;
3068                 adapter->num_tx_queues = f->indices;
3069                 ret = true;
3070         } else {
3071                 ret = false;
3072         }
3073
3074         return ret;
3075 }
3076
3077 /**
3078  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3079  * @adapter: board private structure to initialize
3080  *
3081  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3082  * to the original CPU that initiated the Tx session.  This runs in addition
3083  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3084  * Rx load across CPUs using RSS.
3085  *
3086  **/
3087 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3088 {
3089         bool ret = false;
3090         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3091
3092         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3093         f_fdir->mask = 0;
3094
3095         /* Flow Director must have RSS enabled */
3096         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3097             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3098              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3099                 adapter->num_tx_queues = f_fdir->indices;
3100                 adapter->num_rx_queues = f_fdir->indices;
3101                 ret = true;
3102         } else {
3103                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3104                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3105         }
3106         return ret;
3107 }
3108
3109 #ifdef IXGBE_FCOE
3110 /**
3111  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3112  * @adapter: board private structure to initialize
3113  *
3114  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3115  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3116  * rx queues out of the max number of rx queues, instead, it is used as the
3117  * index of the first rx queue used by FCoE.
3118  *
3119  **/
3120 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3121 {
3122         bool ret = false;
3123         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3124
3125         f->indices = min((int)num_online_cpus(), f->indices);
3126         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3127 #ifdef CONFIG_IXGBE_DCB
3128                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3129                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3130                         ixgbe_set_dcb_queues(adapter);
3131                 }
3132 #endif
3133                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3134                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3135                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3136                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3137                                 ixgbe_set_fdir_queues(adapter);
3138                         else
3139                                 ixgbe_set_rss_queues(adapter);
3140                 }
3141                 /* adding FCoE rx rings to the end */
3142                 f->mask = adapter->num_rx_queues;
3143                 adapter->num_rx_queues += f->indices;
3144                 if (adapter->num_tx_queues == 0)
3145                         adapter->num_tx_queues = f->indices;
3146
3147                 ret = true;
3148         }
3149
3150         return ret;
3151 }
3152
3153 #endif /* IXGBE_FCOE */
3154 /*
3155  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3156  * @adapter: board private structure to initialize
3157  *
3158  * This is the top level queue allocation routine.  The order here is very
3159  * important, starting with the "most" number of features turned on at once,
3160  * and ending with the smallest set of features.  This way large combinations
3161  * can be allocated if they're turned on, and smaller combinations are the
3162  * fallthrough conditions.
3163  *
3164  **/
3165 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3166 {
3167 #ifdef IXGBE_FCOE
3168         if (ixgbe_set_fcoe_queues(adapter))
3169                 goto done;
3170
3171 #endif /* IXGBE_FCOE */
3172 #ifdef CONFIG_IXGBE_DCB
3173         if (ixgbe_set_dcb_queues(adapter))
3174                 goto done;
3175
3176 #endif
3177         if (ixgbe_set_fdir_queues(adapter))
3178                 goto done;
3179
3180         if (ixgbe_set_rss_queues(adapter))
3181                 goto done;
3182
3183         /* fallback to base case */
3184         adapter->num_rx_queues = 1;
3185         adapter->num_tx_queues = 1;
3186
3187 done:
3188         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3189         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3190 }
3191
3192 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3193                                        int vectors)
3194 {
3195         int err, vector_threshold;
3196
3197         /* We'll want at least 3 (vector_threshold):
3198          * 1) TxQ[0] Cleanup
3199          * 2) RxQ[0] Cleanup
3200          * 3) Other (Link Status Change, etc.)
3201          * 4) TCP Timer (optional)
3202          */
3203         vector_threshold = MIN_MSIX_COUNT;
3204
3205         /* The more we get, the more we will assign to Tx/Rx Cleanup
3206          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3207          * Right now, we simply care about how many we'll get; we'll
3208          * set them up later while requesting irq's.
3209          */
3210         while (vectors >= vector_threshold) {
3211                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3212                                       vectors);
3213                 if (!err) /* Success in acquiring all requested vectors. */
3214                         break;
3215                 else if (err < 0)
3216                         vectors = 0; /* Nasty failure, quit now */
3217                 else /* err == number of vectors we should try again with */
3218                         vectors = err;
3219         }
3220
3221         if (vectors < vector_threshold) {
3222                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3223                  * This just means we'll go with either a single MSI
3224                  * vector or fall back to legacy interrupts.
3225                  */
3226                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3227                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3228                 kfree(adapter->msix_entries);
3229                 adapter->msix_entries = NULL;
3230         } else {
3231                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3232                 /*
3233                  * Adjust for only the vectors we'll use, which is minimum
3234                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3235                  * vectors we were allocated.
3236                  */
3237                 adapter->num_msix_vectors = min(vectors,
3238                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3239         }
3240 }
3241
3242 /**
3243  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3244  * @adapter: board private structure to initialize
3245  *
3246  * Cache the descriptor ring offsets for RSS to the assigned rings.
3247  *
3248  **/
3249 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3250 {
3251         int i;
3252         bool ret = false;
3253
3254         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3255                 for (i = 0; i < adapter->num_rx_queues; i++)
3256                         adapter->rx_ring[i].reg_idx = i;
3257                 for (i = 0; i < adapter->num_tx_queues; i++)
3258                         adapter->tx_ring[i].reg_idx = i;
3259                 ret = true;
3260         } else {
3261                 ret = false;
3262         }
3263
3264         return ret;
3265 }
3266
3267 #ifdef CONFIG_IXGBE_DCB
3268 /**
3269  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3270  * @adapter: board private structure to initialize
3271  *
3272  * Cache the descriptor ring offsets for DCB to the assigned rings.
3273  *
3274  **/
3275 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3276 {
3277         int i;
3278         bool ret = false;
3279         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3280
3281         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3282                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3283                         /* the number of queues is assumed to be symmetric */
3284                         for (i = 0; i < dcb_i; i++) {
3285                                 adapter->rx_ring[i].reg_idx = i << 3;
3286                                 adapter->tx_ring[i].reg_idx = i << 2;
3287                         }
3288                         ret = true;
3289                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3290                         if (dcb_i == 8) {
3291                                 /*
3292                                  * Tx TC0 starts at: descriptor queue 0
3293                                  * Tx TC1 starts at: descriptor queue 32
3294                                  * Tx TC2 starts at: descriptor queue 64
3295                                  * Tx TC3 starts at: descriptor queue 80
3296                                  * Tx TC4 starts at: descriptor queue 96
3297                                  * Tx TC5 starts at: descriptor queue 104
3298                                  * Tx TC6 starts at: descriptor queue 112
3299                                  * Tx TC7 starts at: descriptor queue 120
3300                                  *
3301                                  * Rx TC0-TC7 are offset by 16 queues each
3302                                  */
3303                                 for (i = 0; i < 3; i++) {
3304                                         adapter->tx_ring[i].reg_idx = i << 5;
3305                                         adapter->rx_ring[i].reg_idx = i << 4;
3306                                 }
3307                                 for ( ; i < 5; i++) {
3308                                         adapter->tx_ring[i].reg_idx =
3309                                                                  ((i + 2) << 4);
3310                                         adapter->rx_ring[i].reg_idx = i << 4;
3311                                 }
3312                                 for ( ; i < dcb_i; i++) {
3313                                         adapter->tx_ring[i].reg_idx =
3314                                                                  ((i + 8) << 3);
3315                                         adapter->rx_ring[i].reg_idx = i << 4;
3316                                 }
3317
3318                                 ret = true;
3319                         } else if (dcb_i == 4) {
3320                                 /*
3321                                  * Tx TC0 starts at: descriptor queue 0
3322                                  * Tx TC1 starts at: descriptor queue 64
3323                                  * Tx TC2 starts at: descriptor queue 96
3324                                  * Tx TC3 starts at: descriptor queue 112
3325                                  *
3326                                  * Rx TC0-TC3 are offset by 32 queues each
3327                                  */
3328                                 adapter->tx_ring[0].reg_idx = 0;
3329                                 adapter->tx_ring[1].reg_idx = 64;
3330                                 adapter->tx_ring[2].reg_idx = 96;
3331                                 adapter->tx_ring[3].reg_idx = 112;
3332                                 for (i = 0 ; i < dcb_i; i++)
3333                                         adapter->rx_ring[i].reg_idx = i << 5;
3334
3335                                 ret = true;
3336                         } else {
3337                                 ret = false;
3338                         }
3339                 } else {
3340                         ret = false;
3341                 }
3342         } else {
3343                 ret = false;
3344         }
3345
3346         return ret;
3347 }
3348 #endif
3349
3350 /**
3351  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3352  * @adapter: board private structure to initialize
3353  *
3354  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3355  *
3356  **/
3357 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3358 {
3359         int i;
3360         bool ret = false;
3361
3362         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3363             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3364              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3365                 for (i = 0; i < adapter->num_rx_queues; i++)
3366                         adapter->rx_ring[i].reg_idx = i;
3367                 for (i = 0; i < adapter->num_tx_queues; i++)
3368                         adapter->tx_ring[i].reg_idx = i;
3369                 ret = true;
3370         }
3371
3372         return ret;
3373 }
3374
3375 #ifdef IXGBE_FCOE
3376 /**
3377  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3378  * @adapter: board private structure to initialize
3379  *
3380  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3381  *
3382  */
3383 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3384 {
3385         int i, fcoe_i = 0;
3386         bool ret = false;
3387         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3388
3389         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3390 #ifdef CONFIG_IXGBE_DCB
3391                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3392                         ixgbe_cache_ring_dcb(adapter);
3393                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3394                 }
3395 #endif /* CONFIG_IXGBE_DCB */
3396                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3397                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3398                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3399                                 ixgbe_cache_ring_fdir(adapter);
3400                         else
3401                                 ixgbe_cache_ring_rss(adapter);
3402
3403                         fcoe_i = f->mask;
3404                 }
3405                 for (i = 0; i < f->indices; i++, fcoe_i++)
3406                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3407                 ret = true;
3408         }
3409         return ret;
3410 }
3411
3412 #endif /* IXGBE_FCOE */
3413 /**
3414  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3415  * @adapter: board private structure to initialize
3416  *
3417  * Once we know the feature-set enabled for the device, we'll cache
3418  * the register offset the descriptor ring is assigned to.
3419  *
3420  * Note, the order the various feature calls is important.  It must start with
3421  * the "most" features enabled at the same time, then trickle down to the
3422  * least amount of features turned on at once.
3423  **/
3424 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3425 {
3426         /* start with default case */
3427         adapter->rx_ring[0].reg_idx = 0;
3428         adapter->tx_ring[0].reg_idx = 0;
3429
3430 #ifdef IXGBE_FCOE
3431         if (ixgbe_cache_ring_fcoe(adapter))
3432                 return;
3433
3434 #endif /* IXGBE_FCOE */
3435 #ifdef CONFIG_IXGBE_DCB
3436         if (ixgbe_cache_ring_dcb(adapter))
3437                 return;
3438
3439 #endif
3440         if (ixgbe_cache_ring_fdir(adapter))
3441                 return;
3442
3443         if (ixgbe_cache_ring_rss(adapter))
3444                 return;
3445 }
3446
3447 /**
3448  * ixgbe_alloc_queues - Allocate memory for all rings
3449  * @adapter: board private structure to initialize
3450  *
3451  * We allocate one ring per queue at run-time since we don't know the
3452  * number of queues at compile-time.  The polling_netdev array is
3453  * intended for Multiqueue, but should work fine with a single queue.
3454  **/
3455 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3456 {
3457         int i;
3458
3459         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3460                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3461         if (!adapter->tx_ring)
3462                 goto err_tx_ring_allocation;
3463
3464         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3465                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3466         if (!adapter->rx_ring)
3467                 goto err_rx_ring_allocation;
3468
3469         for (i = 0; i < adapter->num_tx_queues; i++) {
3470                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3471                 adapter->tx_ring[i].queue_index = i;
3472         }
3473
3474         for (i = 0; i < adapter->num_rx_queues; i++) {
3475                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3476                 adapter->rx_ring[i].queue_index = i;
3477         }
3478
3479         ixgbe_cache_ring_register(adapter);
3480
3481         return 0;
3482
3483 err_rx_ring_allocation:
3484         kfree(adapter->tx_ring);
3485 err_tx_ring_allocation:
3486         return -ENOMEM;
3487 }
3488
3489 /**
3490  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3491  * @adapter: board private structure to initialize
3492  *
3493  * Attempt to configure the interrupts using the best available
3494  * capabilities of the hardware and the kernel.
3495  **/
3496 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3497 {
3498         struct ixgbe_hw *hw = &adapter->hw;
3499         int err = 0;
3500         int vector, v_budget;
3501
3502         /*
3503          * It's easy to be greedy for MSI-X vectors, but it really
3504          * doesn't do us much good if we have a lot more vectors
3505          * than CPU's.  So let's be conservative and only ask for
3506          * (roughly) twice the number of vectors as there are CPU's.
3507          */
3508         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3509                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3510
3511         /*
3512          * At the same time, hardware can only support a maximum of
3513          * hw.mac->max_msix_vectors vectors.  With features
3514          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3515          * descriptor queues supported by our device.  Thus, we cap it off in
3516          * those rare cases where the cpu count also exceeds our vector limit.
3517          */
3518         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3519
3520         /* A failure in MSI-X entry allocation isn't fatal, but it does
3521          * mean we disable MSI-X capabilities of the adapter. */
3522         adapter->msix_entries = kcalloc(v_budget,
3523                                         sizeof(struct msix_entry), GFP_KERNEL);
3524         if (adapter->msix_entries) {
3525                 for (vector = 0; vector < v_budget; vector++)
3526                         adapter->msix_entries[vector].entry = vector;
3527
3528                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3529
3530                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3531                         goto out;
3532         }
3533
3534         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3535         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3536         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3537         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3538         adapter->atr_sample_rate = 0;
3539         ixgbe_set_num_queues(adapter);
3540
3541         err = pci_enable_msi(adapter->pdev);
3542         if (!err) {
3543                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3544         } else {
3545                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3546                         "falling back to legacy.  Error: %d\n", err);
3547                 /* reset err */
3548                 err = 0;
3549         }
3550
3551 out:
3552         return err;
3553 }
3554
3555 /**
3556  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3557  * @adapter: board private structure to initialize
3558  *
3559  * We allocate one q_vector per queue interrupt.  If allocation fails we
3560  * return -ENOMEM.
3561  **/
3562 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3563 {
3564         int q_idx, num_q_vectors;
3565         struct ixgbe_q_vector *q_vector;
3566         int napi_vectors;
3567         int (*poll)(struct napi_struct *, int);
3568
3569         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3570                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3571                 napi_vectors = adapter->num_rx_queues;
3572                 poll = &ixgbe_clean_rxtx_many;
3573         } else {
3574                 num_q_vectors = 1;
3575                 napi_vectors = 1;
3576                 poll = &ixgbe_poll;
3577         }
3578
3579         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3580                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3581                 if (!q_vector)
3582                         goto err_out;
3583                 q_vector->adapter = adapter;
3584                 q_vector->eitr = adapter->eitr_param;
3585                 q_vector->v_idx = q_idx;
3586                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3587                 adapter->q_vector[q_idx] = q_vector;
3588         }
3589
3590         return 0;
3591
3592 err_out:
3593         while (q_idx) {
3594                 q_idx--;
3595                 q_vector = adapter->q_vector[q_idx];
3596                 netif_napi_del(&q_vector->napi);
3597                 kfree(q_vector);
3598                 adapter->q_vector[q_idx] = NULL;
3599         }
3600         return -ENOMEM;
3601 }
3602
3603 /**
3604  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3605  * @adapter: board private structure to initialize
3606  *
3607  * This function frees the memory allocated to the q_vectors.  In addition if
3608  * NAPI is enabled it will delete any references to the NAPI struct prior
3609  * to freeing the q_vector.
3610  **/
3611 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3612 {
3613         int q_idx, num_q_vectors;
3614
3615         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3616                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3617         else
3618                 num_q_vectors = 1;
3619
3620         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3621                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3622                 adapter->q_vector[q_idx] = NULL;
3623                 netif_napi_del(&q_vector->napi);
3624                 kfree(q_vector);
3625         }
3626 }
3627
3628 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3629 {
3630         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3631                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3632                 pci_disable_msix(adapter->pdev);
3633                 kfree(adapter->msix_entries);
3634                 adapter->msix_entries = NULL;
3635         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3636                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3637                 pci_disable_msi(adapter->pdev);
3638         }
3639         return;
3640 }
3641
3642 /**
3643  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3644  * @adapter: board private structure to initialize
3645  *
3646  * We determine which interrupt scheme to use based on...
3647  * - Kernel support (MSI, MSI-X)
3648  *   - which can be user-defined (via MODULE_PARAM)
3649  * - Hardware queue count (num_*_queues)
3650  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3651  **/
3652 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3653 {
3654         int err;
3655
3656         /* Number of supported queues */
3657         ixgbe_set_num_queues(adapter);
3658
3659         err = ixgbe_set_interrupt_capability(adapter);
3660         if (err) {
3661                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3662                 goto err_set_interrupt;
3663         }
3664
3665         err = ixgbe_alloc_q_vectors(adapter);
3666         if (err) {
3667                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3668                         "vectors\n");
3669                 goto err_alloc_q_vectors;
3670         }
3671
3672         err = ixgbe_alloc_queues(adapter);
3673         if (err) {
3674                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3675                 goto err_alloc_queues;
3676         }
3677
3678         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3679                 "Tx Queue count = %u\n",
3680                 (adapter->num_rx_queues > 1) ? "Enabled" :
3681                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3682
3683         set_bit(__IXGBE_DOWN, &adapter->state);
3684
3685         return 0;
3686
3687 err_alloc_queues:
3688         ixgbe_free_q_vectors(adapter);
3689 err_alloc_q_vectors:
3690         ixgbe_reset_interrupt_capability(adapter);
3691 err_set_interrupt:
3692         return err;
3693 }
3694
3695 /**
3696  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3697  * @adapter: board private structure to clear interrupt scheme on
3698  *
3699  * We go through and clear interrupt specific resources and reset the structure
3700  * to pre-load conditions
3701  **/
3702 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3703 {
3704         kfree(adapter->tx_ring);
3705         kfree(adapter->rx_ring);
3706         adapter->tx_ring = NULL;
3707         adapter->rx_ring = NULL;
3708
3709         ixgbe_free_q_vectors(adapter);
3710         ixgbe_reset_interrupt_capability(adapter);
3711 }
3712
3713 /**
3714  * ixgbe_sfp_timer - worker thread to find a missing module
3715  * @data: pointer to our adapter struct
3716  **/
3717 static void ixgbe_sfp_timer(unsigned long data)
3718 {
3719         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3720
3721         /*
3722          * Do the sfp_timer outside of interrupt context due to the
3723          * delays that sfp+ detection requires
3724          */
3725         schedule_work(&adapter->sfp_task);
3726 }
3727
3728 /**
3729  * ixgbe_sfp_task - worker thread to find a missing module
3730  * @work: pointer to work_struct containing our data
3731  **/
3732 static void ixgbe_sfp_task(struct work_struct *work)
3733 {
3734         struct ixgbe_adapter *adapter = container_of(work,
3735                                                      struct ixgbe_adapter,
3736                                                      sfp_task);
3737         struct ixgbe_hw *hw = &adapter->hw;
3738
3739         if ((hw->phy.type == ixgbe_phy_nl) &&
3740             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3741                 s32 ret = hw->phy.ops.identify_sfp(hw);
3742                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3743                         goto reschedule;
3744                 ret = hw->phy.ops.reset(hw);
3745                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3746                         dev_err(&adapter->pdev->dev, "failed to initialize "
3747                                 "because an unsupported SFP+ module type "
3748                                 "was detected.\n"
3749                                 "Reload the driver after installing a "
3750                                 "supported module.\n");
3751                         unregister_netdev(adapter->netdev);
3752                 } else {
3753                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3754                                 hw->phy.sfp_type);
3755                 }
3756                 /* don't need this routine any more */
3757                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3758         }
3759         return;
3760 reschedule:
3761         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3762                 mod_timer(&adapter->sfp_timer,
3763                           round_jiffies(jiffies + (2 * HZ)));
3764 }
3765
3766 /**
3767  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3768  * @adapter: board private structure to initialize
3769  *
3770  * ixgbe_sw_init initializes the Adapter private data structure.
3771  * Fields are initialized based on PCI device information and
3772  * OS network device settings (MTU size).
3773  **/
3774 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3775 {
3776         struct ixgbe_hw *hw = &adapter->hw;
3777         struct pci_dev *pdev = adapter->pdev;
3778         unsigned int rss;
3779 #ifdef CONFIG_IXGBE_DCB
3780         int j;
3781         struct tc_configuration *tc;
3782 #endif
3783
3784         /* PCI config space info */
3785
3786         hw->vendor_id = pdev->vendor;
3787         hw->device_id = pdev->device;
3788         hw->revision_id = pdev->revision;
3789         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3790         hw->subsystem_device_id = pdev->subsystem_device;
3791
3792         /* Set capability flags */
3793         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3794         adapter->ring_feature[RING_F_RSS].indices = rss;
3795         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3796         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3797         if (hw->mac.type == ixgbe_mac_82598EB) {
3798                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3799                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3800                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3801         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3802                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3803                 adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
3804                 adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
3805                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3806                 adapter->ring_feature[RING_F_FDIR].indices =
3807                                                          IXGBE_MAX_FDIR_INDICES;
3808                 adapter->atr_sample_rate = 20;
3809                 adapter->fdir_pballoc = 0;
3810 #ifdef IXGBE_FCOE
3811                 adapter->flags |= IXGBE_FLAG_FCOE_ENABLED;
3812                 adapter->ring_feature[RING_F_FCOE].indices = IXGBE_FCRETA_SIZE;
3813 #endif /* IXGBE_FCOE */
3814         }
3815
3816 #ifdef CONFIG_IXGBE_DCB
3817         /* Configure DCB traffic classes */
3818         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3819                 tc = &adapter->dcb_cfg.tc_config[j];
3820                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3821                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3822                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3823                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3824                 tc->dcb_pfc = pfc_disabled;
3825         }
3826         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3827         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3828         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3829         adapter->dcb_cfg.pfc_mode_enable = false;
3830         adapter->dcb_cfg.round_robin_enable = false;
3831         adapter->dcb_set_bitmap = 0x00;
3832         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3833                            adapter->ring_feature[RING_F_DCB].indices);
3834
3835 #endif
3836
3837         /* default flow control settings */
3838         hw->fc.requested_mode = ixgbe_fc_full;
3839         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3840 #ifdef CONFIG_DCB
3841         adapter->last_lfc_mode = hw->fc.current_mode;
3842 #endif
3843         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3844         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3845         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3846         hw->fc.send_xon = true;
3847         hw->fc.disable_fc_autoneg = false;
3848
3849         /* enable itr by default in dynamic mode */
3850         adapter->itr_setting = 1;
3851         adapter->eitr_param = 20000;
3852
3853         /* set defaults for eitr in MegaBytes */
3854         adapter->eitr_low = 10;
3855         adapter->eitr_high = 20;
3856
3857         /* set default ring sizes */
3858         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3859         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3860
3861         /* initialize eeprom parameters */
3862         if (ixgbe_init_eeprom_params_generic(hw)) {
3863                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3864                 return -EIO;
3865         }
3866
3867         /* enable rx csum by default */
3868         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3869
3870         set_bit(__IXGBE_DOWN, &adapter->state);
3871
3872         return 0;
3873 }
3874
3875 /**
3876  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3877  * @adapter: board private structure
3878  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3879  *
3880  * Return 0 on success, negative on failure
3881  **/
3882 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3883                              struct ixgbe_ring *tx_ring)
3884 {
3885         struct pci_dev *pdev = adapter->pdev;
3886         int size;
3887
3888         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3889         tx_ring->tx_buffer_info = vmalloc(size);
3890         if (!tx_ring->tx_buffer_info)
3891                 goto err;
3892         memset(tx_ring->tx_buffer_info, 0, size);
3893
3894         /* round up to nearest 4K */
3895         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3896         tx_ring->size = ALIGN(tx_ring->size, 4096);
3897
3898         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3899                                              &tx_ring->dma);
3900         if (!tx_ring->desc)
3901                 goto err;
3902
3903         tx_ring->next_to_use = 0;
3904         tx_ring->next_to_clean = 0;
3905         tx_ring->work_limit = tx_ring->count;
3906         return 0;
3907
3908 err:
3909         vfree(tx_ring->tx_buffer_info);
3910         tx_ring->tx_buffer_info = NULL;
3911         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3912                             "descriptor ring\n");
3913         return -ENOMEM;
3914 }
3915
3916 /**
3917  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3918  * @adapter: board private structure
3919  *
3920  * If this function returns with an error, then it's possible one or
3921  * more of the rings is populated (while the rest are not).  It is the
3922  * callers duty to clean those orphaned rings.
3923  *
3924  * Return 0 on success, negative on failure
3925  **/
3926 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3927 {
3928         int i, err = 0;
3929
3930         for (i = 0; i < adapter->num_tx_queues; i++) {
3931                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3932                 if (!err)
3933                         continue;
3934                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3935                 break;
3936         }
3937
3938         return err;
3939 }
3940
3941 /**
3942  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3943  * @adapter: board private structure
3944  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3945  *
3946  * Returns 0 on success, negative on failure
3947  **/
3948 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3949                              struct ixgbe_ring *rx_ring)
3950 {
3951         struct pci_dev *pdev = adapter->pdev;
3952         int size;
3953
3954         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3955         rx_ring->rx_buffer_info = vmalloc(size);
3956         if (!rx_ring->rx_buffer_info) {
3957                 DPRINTK(PROBE, ERR,
3958                         "vmalloc allocation failed for the rx desc ring\n");
3959                 goto alloc_failed;
3960         }
3961         memset(rx_ring->rx_buffer_info, 0, size);
3962
3963         /* Round up to nearest 4K */
3964         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3965         rx_ring->size = ALIGN(rx_ring->size, 4096);
3966
3967         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3968
3969         if (!rx_ring->desc) {
3970                 DPRINTK(PROBE, ERR,
3971                         "Memory allocation failed for the rx desc ring\n");
3972                 vfree(rx_ring->rx_buffer_info);
3973                 goto alloc_failed;
3974         }
3975
3976         rx_ring->next_to_clean = 0;
3977         rx_ring->next_to_use = 0;
3978
3979         return 0;
3980
3981 alloc_failed:
3982         return -ENOMEM;
3983 }
3984
3985 /**
3986  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3987  * @adapter: board private structure
3988  *
3989  * If this function returns with an error, then it's possible one or
3990  * more of the rings is populated (while the rest are not).  It is the
3991  * callers duty to clean those orphaned rings.
3992  *
3993  * Return 0 on success, negative on failure
3994  **/
3995
3996 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3997 {
3998         int i, err = 0;
3999
4000         for (i = 0; i < adapter->num_rx_queues; i++) {
4001                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4002                 if (!err)
4003                         continue;
4004                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4005                 break;
4006         }
4007
4008         return err;
4009 }
4010
4011 /**
4012  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4013  * @adapter: board private structure
4014  * @tx_ring: Tx descriptor ring for a specific queue
4015  *
4016  * Free all transmit software resources
4017  **/
4018 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4019                              struct ixgbe_ring *tx_ring)
4020 {
4021         struct pci_dev *pdev = adapter->pdev;
4022
4023         ixgbe_clean_tx_ring(adapter, tx_ring);
4024
4025         vfree(tx_ring->tx_buffer_info);
4026         tx_ring->tx_buffer_info = NULL;
4027
4028         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4029
4030         tx_ring->desc = NULL;
4031 }
4032
4033 /**
4034  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4035  * @adapter: board private structure
4036  *
4037  * Free all transmit software resources
4038  **/
4039 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4040 {
4041         int i;
4042
4043         for (i = 0; i < adapter->num_tx_queues; i++)
4044                 if (adapter->tx_ring[i].desc)
4045                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4046 }
4047
4048 /**
4049  * ixgbe_free_rx_resources - Free Rx Resources
4050  * @adapter: board private structure
4051  * @rx_ring: ring to clean the resources from
4052  *
4053  * Free all receive software resources
4054  **/
4055 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4056                              struct ixgbe_ring *rx_ring)
4057 {
4058         struct pci_dev *pdev = adapter->pdev;
4059
4060         ixgbe_clean_rx_ring(adapter, rx_ring);
4061
4062         vfree(rx_ring->rx_buffer_info);
4063         rx_ring->rx_buffer_info = NULL;
4064
4065         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4066
4067         rx_ring->desc = NULL;
4068 }
4069
4070 /**
4071  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4072  * @adapter: board private structure
4073  *
4074  * Free all receive software resources
4075  **/
4076 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4077 {
4078         int i;
4079
4080         for (i = 0; i < adapter->num_rx_queues; i++)
4081                 if (adapter->rx_ring[i].desc)
4082                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4083 }
4084
4085 /**
4086  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4087  * @netdev: network interface device structure
4088  * @new_mtu: new value for maximum frame size
4089  *
4090  * Returns 0 on success, negative on failure
4091  **/
4092 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4093 {
4094         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4095         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4096
4097         /* MTU < 68 is an error and causes problems on some kernels */
4098         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4099                 return -EINVAL;
4100
4101         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4102                 netdev->mtu, new_mtu);
4103         /* must set new MTU before calling down or up */
4104         netdev->mtu = new_mtu;
4105
4106         if (netif_running(netdev))
4107                 ixgbe_reinit_locked(adapter);
4108
4109         return 0;
4110 }
4111
4112 /**
4113  * ixgbe_open - Called when a network interface is made active
4114  * @netdev: network interface device structure
4115  *
4116  * Returns 0 on success, negative value on failure
4117  *
4118  * The open entry point is called when a network interface is made
4119  * active by the system (IFF_UP).  At this point all resources needed
4120  * for transmit and receive operations are allocated, the interrupt
4121  * handler is registered with the OS, the watchdog timer is started,
4122  * and the stack is notified that the interface is ready.
4123  **/
4124 static int ixgbe_open(struct net_device *netdev)
4125 {
4126         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4127         int err;
4128
4129         /* disallow open during test */
4130         if (test_bit(__IXGBE_TESTING, &adapter->state))
4131                 return -EBUSY;
4132
4133         netif_carrier_off(netdev);
4134
4135         /* allocate transmit descriptors */
4136         err = ixgbe_setup_all_tx_resources(adapter);
4137         if (err)
4138                 goto err_setup_tx;
4139
4140         /* allocate receive descriptors */
4141         err = ixgbe_setup_all_rx_resources(adapter);
4142         if (err)
4143                 goto err_setup_rx;
4144
4145         ixgbe_configure(adapter);
4146
4147         err = ixgbe_request_irq(adapter);
4148         if (err)
4149                 goto err_req_irq;
4150
4151         err = ixgbe_up_complete(adapter);
4152         if (err)
4153                 goto err_up;
4154
4155         netif_tx_start_all_queues(netdev);
4156
4157         return 0;
4158
4159 err_up:
4160         ixgbe_release_hw_control(adapter);
4161         ixgbe_free_irq(adapter);
4162 err_req_irq:
4163 err_setup_rx:
4164         ixgbe_free_all_rx_resources(adapter);
4165 err_setup_tx:
4166         ixgbe_free_all_tx_resources(adapter);
4167         ixgbe_reset(adapter);
4168
4169         return err;
4170 }
4171
4172 /**
4173  * ixgbe_close - Disables a network interface
4174  * @netdev: network interface device structure
4175  *
4176  * Returns 0, this is not allowed to fail
4177  *
4178  * The close entry point is called when an interface is de-activated
4179  * by the OS.  The hardware is still under the drivers control, but
4180  * needs to be disabled.  A global MAC reset is issued to stop the
4181  * hardware, and all transmit and receive resources are freed.
4182  **/
4183 static int ixgbe_close(struct net_device *netdev)
4184 {
4185         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4186
4187         ixgbe_down(adapter);
4188         ixgbe_free_irq(adapter);
4189
4190         ixgbe_free_all_tx_resources(adapter);
4191         ixgbe_free_all_rx_resources(adapter);
4192
4193         ixgbe_release_hw_control(adapter);
4194
4195         return 0;
4196 }
4197
4198 #ifdef CONFIG_PM
4199 static int ixgbe_resume(struct pci_dev *pdev)
4200 {
4201         struct net_device *netdev = pci_get_drvdata(pdev);
4202         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4203         u32 err;
4204
4205         pci_set_power_state(pdev, PCI_D0);
4206         pci_restore_state(pdev);
4207
4208         err = pci_enable_device_mem(pdev);
4209         if (err) {
4210                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4211                                 "suspend\n");
4212                 return err;
4213         }
4214         pci_set_master(pdev);
4215
4216         pci_wake_from_d3(pdev, false);
4217
4218         err = ixgbe_init_interrupt_scheme(adapter);
4219         if (err) {
4220                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4221                                 "device\n");
4222                 return err;
4223         }
4224
4225         ixgbe_reset(adapter);
4226
4227         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4228
4229         if (netif_running(netdev)) {
4230                 err = ixgbe_open(adapter->netdev);
4231                 if (err)
4232                         return err;
4233         }
4234
4235         netif_device_attach(netdev);
4236
4237         return 0;
4238 }
4239 #endif /* CONFIG_PM */
4240
4241 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4242 {
4243         struct net_device *netdev = pci_get_drvdata(pdev);
4244         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4245         struct ixgbe_hw *hw = &adapter->hw;
4246         u32 ctrl, fctrl;
4247         u32 wufc = adapter->wol;
4248 #ifdef CONFIG_PM
4249         int retval = 0;
4250 #endif
4251
4252         netif_device_detach(netdev);
4253
4254         if (netif_running(netdev)) {
4255                 ixgbe_down(adapter);
4256                 ixgbe_free_irq(adapter);
4257                 ixgbe_free_all_tx_resources(adapter);
4258                 ixgbe_free_all_rx_resources(adapter);
4259         }
4260         ixgbe_clear_interrupt_scheme(adapter);
4261
4262 #ifdef CONFIG_PM
4263         retval = pci_save_state(pdev);
4264         if (retval)
4265                 return retval;
4266
4267 #endif
4268         if (wufc) {
4269                 ixgbe_set_rx_mode(netdev);
4270
4271                 /* turn on all-multi mode if wake on multicast is enabled */
4272                 if (wufc & IXGBE_WUFC_MC) {
4273                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4274                         fctrl |= IXGBE_FCTRL_MPE;
4275                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4276                 }
4277
4278                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4279                 ctrl |= IXGBE_CTRL_GIO_DIS;
4280                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4281
4282                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4283         } else {
4284                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4285                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4286         }
4287
4288         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4289                 pci_wake_from_d3(pdev, true);
4290         else
4291                 pci_wake_from_d3(pdev, false);
4292
4293         *enable_wake = !!wufc;
4294
4295         ixgbe_release_hw_control(adapter);
4296
4297         pci_disable_device(pdev);
4298
4299         return 0;
4300 }
4301
4302 #ifdef CONFIG_PM
4303 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4304 {
4305         int retval;
4306         bool wake;
4307
4308         retval = __ixgbe_shutdown(pdev, &wake);
4309         if (retval)
4310                 return retval;
4311
4312         if (wake) {
4313                 pci_prepare_to_sleep(pdev);
4314         } else {
4315                 pci_wake_from_d3(pdev, false);
4316                 pci_set_power_state(pdev, PCI_D3hot);
4317         }
4318
4319         return 0;
4320 }
4321 #endif /* CONFIG_PM */
4322
4323 static void ixgbe_shutdown(struct pci_dev *pdev)
4324 {
4325         bool wake;
4326
4327         __ixgbe_shutdown(pdev, &wake);
4328
4329         if (system_state == SYSTEM_POWER_OFF) {
4330                 pci_wake_from_d3(pdev, wake);
4331                 pci_set_power_state(pdev, PCI_D3hot);
4332         }
4333 }
4334
4335 /**
4336  * ixgbe_update_stats - Update the board statistics counters.
4337  * @adapter: board private structure
4338  **/
4339 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4340 {
4341         struct ixgbe_hw *hw = &adapter->hw;
4342         u64 total_mpc = 0;
4343         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4344
4345         if (hw->mac.type == ixgbe_mac_82599EB) {
4346                 u64 rsc_count = 0;
4347                 for (i = 0; i < 16; i++)
4348                         adapter->hw_rx_no_dma_resources +=
4349                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4350                 for (i = 0; i < adapter->num_rx_queues; i++)
4351                         rsc_count += adapter->rx_ring[i].rsc_count;
4352                 adapter->rsc_count = rsc_count;
4353         }
4354
4355         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4356         for (i = 0; i < 8; i++) {
4357                 /* for packet buffers not used, the register should read 0 */
4358                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4359                 missed_rx += mpc;
4360                 adapter->stats.mpc[i] += mpc;
4361                 total_mpc += adapter->stats.mpc[i];
4362                 if (hw->mac.type == ixgbe_mac_82598EB)
4363                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4364                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4365                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4366                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4367                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4368                 if (hw->mac.type == ixgbe_mac_82599EB) {
4369                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4370                                                             IXGBE_PXONRXCNT(i));
4371                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4372                                                            IXGBE_PXOFFRXCNT(i));
4373                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4374                 } else {
4375                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4376                                                               IXGBE_PXONRXC(i));
4377                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4378                                                              IXGBE_PXOFFRXC(i));
4379                 }
4380                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4381                                                             IXGBE_PXONTXC(i));
4382                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4383                                                              IXGBE_PXOFFTXC(i));
4384         }
4385         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4386         /* work around hardware counting issue */
4387         adapter->stats.gprc -= missed_rx;
4388
4389         /* 82598 hardware only has a 32 bit counter in the high register */
4390         if (hw->mac.type == ixgbe_mac_82599EB) {
4391                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4392                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4393                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4394                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4395                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4396                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4397                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4398                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4399                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4400                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4401 #ifdef IXGBE_FCOE
4402                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4403                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4404                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4405                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4406                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4407                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4408 #endif /* IXGBE_FCOE */
4409         } else {
4410                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4411                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4412                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4413                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4414                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4415         }
4416         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4417         adapter->stats.bprc += bprc;
4418         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4419         if (hw->mac.type == ixgbe_mac_82598EB)
4420                 adapter->stats.mprc -= bprc;
4421         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4422         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4423         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4424         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4425         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4426         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4427         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4428         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4429         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4430         adapter->stats.lxontxc += lxon;
4431         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4432         adapter->stats.lxofftxc += lxoff;
4433         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4434         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4435         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4436         /*
4437          * 82598 errata - tx of flow control packets is included in tx counters
4438          */
4439         xon_off_tot = lxon + lxoff;
4440         adapter->stats.gptc -= xon_off_tot;
4441         adapter->stats.mptc -= xon_off_tot;
4442         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4443         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4444         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4445         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4446         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4447         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4448         adapter->stats.ptc64 -= xon_off_tot;
4449         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4450         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4451         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4452         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4453         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4454         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4455
4456         /* Fill out the OS statistics structure */
4457         adapter->net_stats.multicast = adapter->stats.mprc;
4458
4459         /* Rx Errors */
4460         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4461                                        adapter->stats.rlec;
4462         adapter->net_stats.rx_dropped = 0;
4463         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4464         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4465         adapter->net_stats.rx_missed_errors = total_mpc;
4466 }
4467
4468 /**
4469  * ixgbe_watchdog - Timer Call-back
4470  * @data: pointer to adapter cast into an unsigned long
4471  **/
4472 static void ixgbe_watchdog(unsigned long data)
4473 {
4474         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4475         struct ixgbe_hw *hw = &adapter->hw;
4476         u64 eics = 0;
4477         int i;
4478
4479         /*
4480          *  Do the watchdog outside of interrupt context due to the lovely
4481          * delays that some of the newer hardware requires
4482          */
4483
4484         if (test_bit(__IXGBE_DOWN, &adapter->state))
4485                 goto watchdog_short_circuit;
4486
4487         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4488                 /*
4489                  * for legacy and MSI interrupts don't set any bits
4490                  * that are enabled for EIAM, because this operation
4491                  * would set *both* EIMS and EICS for any bit in EIAM
4492                  */
4493                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4494                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4495                 goto watchdog_reschedule;
4496         }
4497
4498         /* get one bit for every active tx/rx interrupt vector */
4499         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4500                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4501                 if (qv->rxr_count || qv->txr_count)
4502                         eics |= ((u64)1 << i);
4503         }
4504
4505         /* Cause software interrupt to ensure rx rings are cleaned */
4506         ixgbe_irq_rearm_queues(adapter, eics);
4507
4508 watchdog_reschedule:
4509         /* Reset the timer */
4510         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4511
4512 watchdog_short_circuit:
4513         schedule_work(&adapter->watchdog_task);
4514 }
4515
4516 /**
4517  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4518  * @work: pointer to work_struct containing our data
4519  **/
4520 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4521 {
4522         struct ixgbe_adapter *adapter = container_of(work,
4523                                                      struct ixgbe_adapter,
4524                                                      multispeed_fiber_task);
4525         struct ixgbe_hw *hw = &adapter->hw;
4526         u32 autoneg;
4527
4528         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4529         autoneg = hw->phy.autoneg_advertised;
4530         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4531                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4532                                                   &hw->mac.autoneg);
4533         if (hw->mac.ops.setup_link_speed)
4534                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4535         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4536         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4537 }
4538
4539 /**
4540  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4541  * @work: pointer to work_struct containing our data
4542  **/
4543 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4544 {
4545         struct ixgbe_adapter *adapter = container_of(work,
4546                                                      struct ixgbe_adapter,
4547                                                      sfp_config_module_task);
4548         struct ixgbe_hw *hw = &adapter->hw;
4549         u32 err;
4550
4551         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4552
4553         /* Time for electrical oscillations to settle down */
4554         msleep(100);
4555         err = hw->phy.ops.identify_sfp(hw);
4556
4557         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4558                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4559                         "an unsupported SFP+ module type was detected.\n"
4560                         "Reload the driver after installing a supported "
4561                         "module.\n");
4562                 unregister_netdev(adapter->netdev);
4563                 return;
4564         }
4565         hw->mac.ops.setup_sfp(hw);
4566
4567         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4568                 /* This will also work for DA Twinax connections */
4569                 schedule_work(&adapter->multispeed_fiber_task);
4570         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4571 }
4572
4573 /**
4574  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4575  * @work: pointer to work_struct containing our data
4576  **/
4577 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4578 {
4579         struct ixgbe_adapter *adapter = container_of(work,
4580                                                      struct ixgbe_adapter,
4581                                                      fdir_reinit_task);
4582         struct ixgbe_hw *hw = &adapter->hw;
4583         int i;
4584
4585         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4586                 for (i = 0; i < adapter->num_tx_queues; i++)
4587                         set_bit(__IXGBE_FDIR_INIT_DONE,
4588                                 &(adapter->tx_ring[i].reinit_state));
4589         } else {
4590                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4591                         "ignored adding FDIR ATR filters \n");
4592         }
4593         /* Done FDIR Re-initialization, enable transmits */
4594         netif_tx_start_all_queues(adapter->netdev);
4595 }
4596
4597 /**
4598  * ixgbe_watchdog_task - worker thread to bring link up
4599  * @work: pointer to work_struct containing our data
4600  **/
4601 static void ixgbe_watchdog_task(struct work_struct *work)
4602 {
4603         struct ixgbe_adapter *adapter = container_of(work,
4604                                                      struct ixgbe_adapter,
4605                                                      watchdog_task);
4606         struct net_device *netdev = adapter->netdev;
4607         struct ixgbe_hw *hw = &adapter->hw;
4608         u32 link_speed = adapter->link_speed;
4609         bool link_up = adapter->link_up;
4610         int i;
4611         struct ixgbe_ring *tx_ring;
4612         int some_tx_pending = 0;
4613
4614         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4615
4616         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4617                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4618                 if (link_up) {
4619 #ifdef CONFIG_DCB
4620                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4621                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4622                                         hw->mac.ops.fc_enable(hw, i);
4623                         } else {
4624                                 hw->mac.ops.fc_enable(hw, 0);
4625                         }
4626 #else
4627                         hw->mac.ops.fc_enable(hw, 0);
4628 #endif
4629                 }
4630
4631                 if (link_up ||
4632                     time_after(jiffies, (adapter->link_check_timeout +
4633                                          IXGBE_TRY_LINK_TIMEOUT))) {
4634                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4635                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4636                 }
4637                 adapter->link_up = link_up;
4638                 adapter->link_speed = link_speed;
4639         }
4640
4641         if (link_up) {
4642                 if (!netif_carrier_ok(netdev)) {
4643                         bool flow_rx, flow_tx;
4644
4645                         if (hw->mac.type == ixgbe_mac_82599EB) {
4646                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4647                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4648                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4649                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4650                         } else {
4651                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4652                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4653                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4654                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4655                         }
4656
4657                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4658                                "Flow Control: %s\n",
4659                                netdev->name,
4660                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4661                                 "10 Gbps" :
4662                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4663                                  "1 Gbps" : "unknown speed")),
4664                                ((flow_rx && flow_tx) ? "RX/TX" :
4665                                 (flow_rx ? "RX" :
4666                                 (flow_tx ? "TX" : "None"))));
4667
4668                         netif_carrier_on(netdev);
4669                 } else {
4670                         /* Force detection of hung controller */
4671                         adapter->detect_tx_hung = true;
4672                 }
4673         } else {
4674                 adapter->link_up = false;
4675                 adapter->link_speed = 0;
4676                 if (netif_carrier_ok(netdev)) {
4677                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4678                                netdev->name);
4679                         netif_carrier_off(netdev);
4680                 }
4681         }
4682
4683         if (!netif_carrier_ok(netdev)) {
4684                 for (i = 0; i < adapter->num_tx_queues; i++) {
4685                         tx_ring = &adapter->tx_ring[i];
4686                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4687                                 some_tx_pending = 1;
4688                                 break;
4689                         }
4690                 }
4691
4692                 if (some_tx_pending) {
4693                         /* We've lost link, so the controller stops DMA,
4694                          * but we've got queued Tx work that's never going
4695                          * to get done, so reset controller to flush Tx.
4696                          * (Do the reset outside of interrupt context).
4697                          */
4698                          schedule_work(&adapter->reset_task);
4699                 }
4700         }
4701
4702         ixgbe_update_stats(adapter);
4703         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4704 }
4705
4706 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4707                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4708                      u32 tx_flags, u8 *hdr_len)
4709 {
4710         struct ixgbe_adv_tx_context_desc *context_desc;
4711         unsigned int i;
4712         int err;
4713         struct ixgbe_tx_buffer *tx_buffer_info;
4714         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4715         u32 mss_l4len_idx, l4len;
4716
4717         if (skb_is_gso(skb)) {
4718                 if (skb_header_cloned(skb)) {
4719                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4720                         if (err)
4721                                 return err;
4722                 }
4723                 l4len = tcp_hdrlen(skb);
4724                 *hdr_len += l4len;
4725
4726                 if (skb->protocol == htons(ETH_P_IP)) {
4727                         struct iphdr *iph = ip_hdr(skb);
4728                         iph->tot_len = 0;
4729                         iph->check = 0;
4730                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4731                                                                  iph->daddr, 0,
4732                                                                  IPPROTO_TCP,
4733                                                                  0);
4734                         adapter->hw_tso_ctxt++;
4735                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4736                         ipv6_hdr(skb)->payload_len = 0;
4737                         tcp_hdr(skb)->check =
4738                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4739                                              &ipv6_hdr(skb)->daddr,
4740                                              0, IPPROTO_TCP, 0);
4741                         adapter->hw_tso6_ctxt++;
4742                 }
4743
4744                 i = tx_ring->next_to_use;
4745
4746                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4747                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4748
4749                 /* VLAN MACLEN IPLEN */
4750                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4751                         vlan_macip_lens |=
4752                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4753                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4754                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4755                 *hdr_len += skb_network_offset(skb);
4756                 vlan_macip_lens |=
4757                     (skb_transport_header(skb) - skb_network_header(skb));
4758                 *hdr_len +=
4759                     (skb_transport_header(skb) - skb_network_header(skb));
4760                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4761                 context_desc->seqnum_seed = 0;
4762
4763                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4764                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4765                                    IXGBE_ADVTXD_DTYP_CTXT);
4766
4767                 if (skb->protocol == htons(ETH_P_IP))
4768                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4769                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4770                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4771
4772                 /* MSS L4LEN IDX */
4773                 mss_l4len_idx =
4774                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4775                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4776                 /* use index 1 for TSO */
4777                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4778                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4779
4780                 tx_buffer_info->time_stamp = jiffies;
4781                 tx_buffer_info->next_to_watch = i;
4782
4783                 i++;
4784                 if (i == tx_ring->count)
4785                         i = 0;
4786                 tx_ring->next_to_use = i;
4787
4788                 return true;
4789         }
4790         return false;
4791 }
4792
4793 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4794                           struct ixgbe_ring *tx_ring,
4795                           struct sk_buff *skb, u32 tx_flags)
4796 {
4797         struct ixgbe_adv_tx_context_desc *context_desc;
4798         unsigned int i;
4799         struct ixgbe_tx_buffer *tx_buffer_info;
4800         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4801
4802         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4803             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4804                 i = tx_ring->next_to_use;
4805                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4806                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4807
4808                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4809                         vlan_macip_lens |=
4810                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4811                 vlan_macip_lens |= (skb_network_offset(skb) <<
4812                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4813                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4814                         vlan_macip_lens |= (skb_transport_header(skb) -
4815                                             skb_network_header(skb));
4816
4817                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4818                 context_desc->seqnum_seed = 0;
4819
4820                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4821                                     IXGBE_ADVTXD_DTYP_CTXT);
4822
4823                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4824                         switch (skb->protocol) {
4825                         case cpu_to_be16(ETH_P_IP):
4826                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4827                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4828                                         type_tucmd_mlhl |=
4829                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4830                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4831                                         type_tucmd_mlhl |=
4832                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4833                                 break;
4834                         case cpu_to_be16(ETH_P_IPV6):
4835                                 /* XXX what about other V6 headers?? */
4836                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4837                                         type_tucmd_mlhl |=
4838                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4839                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4840                                         type_tucmd_mlhl |=
4841                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4842                                 break;
4843                         default:
4844                                 if (unlikely(net_ratelimit())) {
4845                                         DPRINTK(PROBE, WARNING,
4846                                          "partial checksum but proto=%x!\n",
4847                                          skb->protocol);
4848                                 }
4849                                 break;
4850                         }
4851                 }
4852
4853                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4854                 /* use index zero for tx checksum offload */
4855                 context_desc->mss_l4len_idx = 0;
4856
4857                 tx_buffer_info->time_stamp = jiffies;
4858                 tx_buffer_info->next_to_watch = i;
4859
4860                 adapter->hw_csum_tx_good++;
4861                 i++;
4862                 if (i == tx_ring->count)
4863                         i = 0;
4864                 tx_ring->next_to_use = i;
4865
4866                 return true;
4867         }
4868
4869         return false;
4870 }
4871
4872 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4873                         struct ixgbe_ring *tx_ring,
4874                         struct sk_buff *skb, u32 tx_flags,
4875                         unsigned int first)
4876 {
4877         struct ixgbe_tx_buffer *tx_buffer_info;
4878         unsigned int len;
4879         unsigned int total = skb->len;
4880         unsigned int offset = 0, size, count = 0, i;
4881         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4882         unsigned int f;
4883         dma_addr_t *map;
4884
4885         i = tx_ring->next_to_use;
4886
4887         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4888                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4889                 return 0;
4890         }
4891
4892         map = skb_shinfo(skb)->dma_maps;
4893
4894         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4895                 /* excluding fcoe_crc_eof for FCoE */
4896                 total -= sizeof(struct fcoe_crc_eof);
4897
4898         len = min(skb_headlen(skb), total);
4899         while (len) {
4900                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4901                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4902
4903                 tx_buffer_info->length = size;
4904                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4905                 tx_buffer_info->time_stamp = jiffies;
4906                 tx_buffer_info->next_to_watch = i;
4907
4908                 len -= size;
4909                 total -= size;
4910                 offset += size;
4911                 count++;
4912
4913                 if (len) {
4914                         i++;
4915                         if (i == tx_ring->count)
4916                                 i = 0;
4917                 }
4918         }
4919
4920         for (f = 0; f < nr_frags; f++) {
4921                 struct skb_frag_struct *frag;
4922
4923                 frag = &skb_shinfo(skb)->frags[f];
4924                 len = min((unsigned int)frag->size, total);
4925                 offset = 0;
4926
4927                 while (len) {
4928                         i++;
4929                         if (i == tx_ring->count)
4930                                 i = 0;
4931
4932                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4933                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4934
4935                         tx_buffer_info->length = size;
4936                         tx_buffer_info->dma = map[f] + offset;
4937                         tx_buffer_info->time_stamp = jiffies;
4938                         tx_buffer_info->next_to_watch = i;
4939
4940                         len -= size;
4941                         total -= size;
4942                         offset += size;
4943                         count++;
4944                 }
4945                 if (total == 0)
4946                         break;
4947         }
4948
4949         tx_ring->tx_buffer_info[i].skb = skb;
4950         tx_ring->tx_buffer_info[first].next_to_watch = i;
4951
4952         return count;
4953 }
4954
4955 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4956                            struct ixgbe_ring *tx_ring,
4957                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4958 {
4959         union ixgbe_adv_tx_desc *tx_desc = NULL;
4960         struct ixgbe_tx_buffer *tx_buffer_info;
4961         u32 olinfo_status = 0, cmd_type_len = 0;
4962         unsigned int i;
4963         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4964
4965         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4966
4967         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4968
4969         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4970                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4971
4972         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4973                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4974
4975                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4976                                  IXGBE_ADVTXD_POPTS_SHIFT;
4977
4978                 /* use index 1 context for tso */
4979                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4980                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4981                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4982                                          IXGBE_ADVTXD_POPTS_SHIFT;
4983
4984         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4985                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4986                                  IXGBE_ADVTXD_POPTS_SHIFT;
4987
4988         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4989                 olinfo_status |= IXGBE_ADVTXD_CC;
4990                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4991                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4992                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4993         }
4994
4995         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4996
4997         i = tx_ring->next_to_use;
4998         while (count--) {
4999                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5000                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5001                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5002                 tx_desc->read.cmd_type_len =
5003                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5004                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5005                 i++;
5006                 if (i == tx_ring->count)
5007                         i = 0;
5008         }
5009
5010         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5011
5012         /*
5013          * Force memory writes to complete before letting h/w
5014          * know there are new descriptors to fetch.  (Only
5015          * applicable for weak-ordered memory model archs,
5016          * such as IA-64).
5017          */
5018         wmb();
5019
5020         tx_ring->next_to_use = i;
5021         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5022 }
5023
5024 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5025                       int queue, u32 tx_flags)
5026 {
5027         /* Right now, we support IPv4 only */
5028         struct ixgbe_atr_input atr_input;
5029         struct tcphdr *th;
5030         struct udphdr *uh;
5031         struct iphdr *iph = ip_hdr(skb);
5032         struct ethhdr *eth = (struct ethhdr *)skb->data;
5033         u16 vlan_id, src_port, dst_port, flex_bytes;
5034         u32 src_ipv4_addr, dst_ipv4_addr;
5035         u8 l4type = 0;
5036
5037         /* check if we're UDP or TCP */
5038         if (iph->protocol == IPPROTO_TCP) {
5039                 th = tcp_hdr(skb);
5040                 src_port = th->source;
5041                 dst_port = th->dest;
5042                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5043                 /* l4type IPv4 type is 0, no need to assign */
5044         } else if(iph->protocol == IPPROTO_UDP) {
5045                 uh = udp_hdr(skb);
5046                 src_port = uh->source;
5047                 dst_port = uh->dest;
5048                 l4type |= IXGBE_ATR_L4TYPE_UDP;
5049                 /* l4type IPv4 type is 0, no need to assign */
5050         } else {
5051                 /* Unsupported L4 header, just bail here */
5052                 return;
5053         }
5054
5055         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5056
5057         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5058                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5059         src_ipv4_addr = iph->saddr;
5060         dst_ipv4_addr = iph->daddr;
5061         flex_bytes = eth->h_proto;
5062
5063         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5064         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5065         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5066         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5067         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5068         /* src and dst are inverted, think how the receiver sees them */
5069         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5070         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5071
5072         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5073         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5074 }
5075
5076 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5077                                  struct ixgbe_ring *tx_ring, int size)
5078 {
5079         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5080
5081         netif_stop_subqueue(netdev, tx_ring->queue_index);
5082         /* Herbert's original patch had:
5083          *  smp_mb__after_netif_stop_queue();
5084          * but since that doesn't exist yet, just open code it. */
5085         smp_mb();
5086
5087         /* We need to check again in a case another CPU has just
5088          * made room available. */
5089         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5090                 return -EBUSY;
5091
5092         /* A reprieve! - use start_queue because it doesn't call schedule */
5093         netif_start_subqueue(netdev, tx_ring->queue_index);
5094         ++adapter->restart_queue;
5095         return 0;
5096 }
5097
5098 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5099                               struct ixgbe_ring *tx_ring, int size)
5100 {
5101         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5102                 return 0;
5103         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5104 }
5105
5106 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5107 {
5108         struct ixgbe_adapter *adapter = netdev_priv(dev);
5109
5110         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5111                 return smp_processor_id();
5112
5113         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5114                 return 0;  /* All traffic should default to class 0 */
5115
5116         return skb_tx_hash(dev, skb);
5117 }
5118
5119 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5120 {
5121         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5122         struct ixgbe_ring *tx_ring;
5123         unsigned int first;
5124         unsigned int tx_flags = 0;
5125         u8 hdr_len = 0;
5126         int r_idx = 0, tso;
5127         int count = 0;
5128         unsigned int f;
5129
5130         r_idx = skb->queue_mapping;
5131         tx_ring = &adapter->tx_ring[r_idx];
5132
5133         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5134                 tx_flags |= vlan_tx_tag_get(skb);
5135                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5136                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5137                         tx_flags |= (skb->queue_mapping << 13);
5138                 }
5139                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5140                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5141         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5142                 tx_flags |= (skb->queue_mapping << 13);
5143                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5144                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5145         }
5146
5147         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5148             (skb->protocol == htons(ETH_P_FCOE)))
5149                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5150
5151         /* four things can cause us to need a context descriptor */
5152         if (skb_is_gso(skb) ||
5153             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5154             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5155             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5156                 count++;
5157
5158         count += TXD_USE_COUNT(skb_headlen(skb));
5159         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5160                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5161
5162         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5163                 adapter->tx_busy++;
5164                 return NETDEV_TX_BUSY;
5165         }
5166
5167         first = tx_ring->next_to_use;
5168         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5169 #ifdef IXGBE_FCOE
5170                 /* setup tx offload for FCoE */
5171                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5172                 if (tso < 0) {
5173                         dev_kfree_skb_any(skb);
5174                         return NETDEV_TX_OK;
5175                 }
5176                 if (tso)
5177                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5178 #endif /* IXGBE_FCOE */
5179         } else {
5180                 if (skb->protocol == htons(ETH_P_IP))
5181                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5182                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5183                 if (tso < 0) {
5184                         dev_kfree_skb_any(skb);
5185                         return NETDEV_TX_OK;
5186                 }
5187
5188                 if (tso)
5189                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5190                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5191                          (skb->ip_summed == CHECKSUM_PARTIAL))
5192                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5193         }
5194
5195         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5196         if (count) {
5197                 /* add the ATR filter if ATR is on */
5198                 if (tx_ring->atr_sample_rate) {
5199                         ++tx_ring->atr_count;
5200                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5201                              test_bit(__IXGBE_FDIR_INIT_DONE,
5202                                       &tx_ring->reinit_state)) {
5203                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5204                                           tx_flags);
5205                                 tx_ring->atr_count = 0;
5206                         }
5207                 }
5208                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5209                                hdr_len);
5210                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5211
5212         } else {
5213                 dev_kfree_skb_any(skb);
5214                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5215                 tx_ring->next_to_use = first;
5216         }
5217
5218         return NETDEV_TX_OK;
5219 }
5220
5221 /**
5222  * ixgbe_get_stats - Get System Network Statistics
5223  * @netdev: network interface device structure
5224  *
5225  * Returns the address of the device statistics structure.
5226  * The statistics are actually updated from the timer callback.
5227  **/
5228 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5229 {
5230         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5231
5232         /* only return the current stats */
5233         return &adapter->net_stats;
5234 }
5235
5236 /**
5237  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5238  * @netdev: network interface device structure
5239  * @p: pointer to an address structure
5240  *
5241  * Returns 0 on success, negative on failure
5242  **/
5243 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5244 {
5245         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5246         struct ixgbe_hw *hw = &adapter->hw;
5247         struct sockaddr *addr = p;
5248
5249         if (!is_valid_ether_addr(addr->sa_data))
5250                 return -EADDRNOTAVAIL;
5251
5252         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5253         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5254
5255         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5256
5257         return 0;
5258 }
5259
5260 static int
5261 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5262 {
5263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5264         struct ixgbe_hw *hw = &adapter->hw;
5265         u16 value;
5266         int rc;
5267
5268         if (prtad != hw->phy.mdio.prtad)
5269                 return -EINVAL;
5270         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5271         if (!rc)
5272                 rc = value;
5273         return rc;
5274 }
5275
5276 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5277                             u16 addr, u16 value)
5278 {
5279         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5280         struct ixgbe_hw *hw = &adapter->hw;
5281
5282         if (prtad != hw->phy.mdio.prtad)
5283                 return -EINVAL;
5284         return hw->phy.ops.write_reg(hw, addr, devad, value);
5285 }
5286
5287 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5288 {
5289         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5290
5291         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5292 }
5293
5294 /**
5295  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5296  * netdev->dev_addrs
5297  * @netdev: network interface device structure
5298  *
5299  * Returns non-zero on failure
5300  **/
5301 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5302 {
5303         int err = 0;
5304         struct ixgbe_adapter *adapter = netdev_priv(dev);
5305         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5306
5307         if (is_valid_ether_addr(mac->san_addr)) {
5308                 rtnl_lock();
5309                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5310                 rtnl_unlock();
5311         }
5312         return err;
5313 }
5314
5315 /**
5316  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5317  * netdev->dev_addrs
5318  * @netdev: network interface device structure
5319  *
5320  * Returns non-zero on failure
5321  **/
5322 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5323 {
5324         int err = 0;
5325         struct ixgbe_adapter *adapter = netdev_priv(dev);
5326         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5327
5328         if (is_valid_ether_addr(mac->san_addr)) {
5329                 rtnl_lock();
5330                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5331                 rtnl_unlock();
5332         }
5333         return err;
5334 }
5335
5336 #ifdef CONFIG_NET_POLL_CONTROLLER
5337 /*
5338  * Polling 'interrupt' - used by things like netconsole to send skbs
5339  * without having to re-enable interrupts. It's not called while
5340  * the interrupt routine is executing.
5341  */
5342 static void ixgbe_netpoll(struct net_device *netdev)
5343 {
5344         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5345
5346         disable_irq(adapter->pdev->irq);
5347         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5348         ixgbe_intr(adapter->pdev->irq, netdev);
5349         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5350         enable_irq(adapter->pdev->irq);
5351 }
5352 #endif
5353
5354 static const struct net_device_ops ixgbe_netdev_ops = {
5355         .ndo_open               = ixgbe_open,
5356         .ndo_stop               = ixgbe_close,
5357         .ndo_start_xmit         = ixgbe_xmit_frame,
5358         .ndo_select_queue       = ixgbe_select_queue,
5359         .ndo_get_stats          = ixgbe_get_stats,
5360         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5361         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5362         .ndo_validate_addr      = eth_validate_addr,
5363         .ndo_set_mac_address    = ixgbe_set_mac,
5364         .ndo_change_mtu         = ixgbe_change_mtu,
5365         .ndo_tx_timeout         = ixgbe_tx_timeout,
5366         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5367         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5368         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5369         .ndo_do_ioctl           = ixgbe_ioctl,
5370 #ifdef CONFIG_NET_POLL_CONTROLLER
5371         .ndo_poll_controller    = ixgbe_netpoll,
5372 #endif
5373 #ifdef IXGBE_FCOE
5374         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5375         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5376 #endif /* IXGBE_FCOE */
5377 };
5378
5379 /**
5380  * ixgbe_probe - Device Initialization Routine
5381  * @pdev: PCI device information struct
5382  * @ent: entry in ixgbe_pci_tbl
5383  *
5384  * Returns 0 on success, negative on failure
5385  *
5386  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5387  * The OS initialization, configuring of the adapter private structure,
5388  * and a hardware reset occur.
5389  **/
5390 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5391                                  const struct pci_device_id *ent)
5392 {
5393         struct net_device *netdev;
5394         struct ixgbe_adapter *adapter = NULL;
5395         struct ixgbe_hw *hw;
5396         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5397         static int cards_found;
5398         int i, err, pci_using_dac;
5399 #ifdef IXGBE_FCOE
5400         u16 device_caps;
5401 #endif
5402         u32 part_num, eec;
5403
5404         err = pci_enable_device_mem(pdev);
5405         if (err)
5406                 return err;
5407
5408         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5409             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5410                 pci_using_dac = 1;
5411         } else {
5412                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5413                 if (err) {
5414                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5415                         if (err) {
5416                                 dev_err(&pdev->dev, "No usable DMA "
5417                                         "configuration, aborting\n");
5418                                 goto err_dma;
5419                         }
5420                 }
5421                 pci_using_dac = 0;
5422         }
5423
5424         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5425                                            IORESOURCE_MEM), ixgbe_driver_name);
5426         if (err) {
5427                 dev_err(&pdev->dev,
5428                         "pci_request_selected_regions failed 0x%x\n", err);
5429                 goto err_pci_reg;
5430         }
5431
5432         err = pci_enable_pcie_error_reporting(pdev);
5433         if (err) {
5434                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5435                                     "0x%x\n", err);
5436                 /* non-fatal, continue */
5437         }
5438
5439         pci_set_master(pdev);
5440         pci_save_state(pdev);
5441
5442         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5443         if (!netdev) {
5444                 err = -ENOMEM;
5445                 goto err_alloc_etherdev;
5446         }
5447
5448         SET_NETDEV_DEV(netdev, &pdev->dev);
5449
5450         pci_set_drvdata(pdev, netdev);
5451         adapter = netdev_priv(netdev);
5452
5453         adapter->netdev = netdev;
5454         adapter->pdev = pdev;
5455         hw = &adapter->hw;
5456         hw->back = adapter;
5457         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5458
5459         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5460                               pci_resource_len(pdev, 0));
5461         if (!hw->hw_addr) {
5462                 err = -EIO;
5463                 goto err_ioremap;
5464         }
5465
5466         for (i = 1; i <= 5; i++) {
5467                 if (pci_resource_len(pdev, i) == 0)
5468                         continue;
5469         }
5470
5471         netdev->netdev_ops = &ixgbe_netdev_ops;
5472         ixgbe_set_ethtool_ops(netdev);
5473         netdev->watchdog_timeo = 5 * HZ;
5474         strcpy(netdev->name, pci_name(pdev));
5475
5476         adapter->bd_number = cards_found;
5477
5478         /* Setup hw api */
5479         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5480         hw->mac.type  = ii->mac;
5481
5482         /* EEPROM */
5483         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5484         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5485         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5486         if (!(eec & (1 << 8)))
5487                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5488
5489         /* PHY */
5490         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5491         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5492         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5493         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5494         hw->phy.mdio.mmds = 0;
5495         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5496         hw->phy.mdio.dev = netdev;
5497         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5498         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5499
5500         /* set up this timer and work struct before calling get_invariants
5501          * which might start the timer
5502          */
5503         init_timer(&adapter->sfp_timer);
5504         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5505         adapter->sfp_timer.data = (unsigned long) adapter;
5506
5507         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5508
5509         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5510         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5511
5512         /* a new SFP+ module arrival, called from GPI SDP2 context */
5513         INIT_WORK(&adapter->sfp_config_module_task,
5514                   ixgbe_sfp_config_module_task);
5515
5516         ii->get_invariants(hw);
5517
5518         /* setup the private structure */
5519         err = ixgbe_sw_init(adapter);
5520         if (err)
5521                 goto err_sw_init;
5522
5523         /*
5524          * If there is a fan on this device and it has failed log the
5525          * failure.
5526          */
5527         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5528                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5529                 if (esdp & IXGBE_ESDP_SDP1)
5530                         DPRINTK(PROBE, CRIT,
5531                                 "Fan has stopped, replace the adapter\n");
5532         }
5533
5534         /* reset_hw fills in the perm_addr as well */
5535         err = hw->mac.ops.reset_hw(hw);
5536         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5537             hw->mac.type == ixgbe_mac_82598EB) {
5538                 /*
5539                  * Start a kernel thread to watch for a module to arrive.
5540                  * Only do this for 82598, since 82599 will generate
5541                  * interrupts on module arrival.
5542                  */
5543                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5544                 mod_timer(&adapter->sfp_timer,
5545                           round_jiffies(jiffies + (2 * HZ)));
5546                 err = 0;
5547         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5548                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5549                         "an unsupported SFP+ module type was detected.\n"
5550                         "Reload the driver after installing a supported "
5551                         "module.\n");
5552                 goto err_sw_init;
5553         } else if (err) {
5554                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5555                 goto err_sw_init;
5556         }
5557
5558         netdev->features = NETIF_F_SG |
5559                            NETIF_F_IP_CSUM |
5560                            NETIF_F_HW_VLAN_TX |
5561                            NETIF_F_HW_VLAN_RX |
5562                            NETIF_F_HW_VLAN_FILTER;
5563
5564         netdev->features |= NETIF_F_IPV6_CSUM;
5565         netdev->features |= NETIF_F_TSO;
5566         netdev->features |= NETIF_F_TSO6;
5567         netdev->features |= NETIF_F_GRO;
5568
5569         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5570                 netdev->features |= NETIF_F_SCTP_CSUM;
5571
5572         netdev->vlan_features |= NETIF_F_TSO;
5573         netdev->vlan_features |= NETIF_F_TSO6;
5574         netdev->vlan_features |= NETIF_F_IP_CSUM;
5575         netdev->vlan_features |= NETIF_F_SG;
5576
5577         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5578                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5579
5580 #ifdef CONFIG_IXGBE_DCB
5581         netdev->dcbnl_ops = &dcbnl_ops;
5582 #endif
5583
5584 #ifdef IXGBE_FCOE
5585         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
5586                 if (hw->mac.ops.get_device_caps) {
5587                         hw->mac.ops.get_device_caps(hw, &device_caps);
5588                         if (!(device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)) {
5589                                 netdev->features |= NETIF_F_FCOE_CRC;
5590                                 netdev->features |= NETIF_F_FSO;
5591                                 netdev->fcoe_ddp_xid = IXGBE_FCOE_DDP_MAX - 1;
5592                         } else {
5593                                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5594                         }
5595                 }
5596         }
5597 #endif /* IXGBE_FCOE */
5598         if (pci_using_dac)
5599                 netdev->features |= NETIF_F_HIGHDMA;
5600
5601         if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
5602                 netdev->features |= NETIF_F_LRO;
5603
5604         /* make sure the EEPROM is good */
5605         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5606                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5607                 err = -EIO;
5608                 goto err_eeprom;
5609         }
5610
5611         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5612         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5613
5614         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5615                 dev_err(&pdev->dev, "invalid MAC address\n");
5616                 err = -EIO;
5617                 goto err_eeprom;
5618         }
5619
5620         init_timer(&adapter->watchdog_timer);
5621         adapter->watchdog_timer.function = &ixgbe_watchdog;
5622         adapter->watchdog_timer.data = (unsigned long)adapter;
5623
5624         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5625         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5626
5627         err = ixgbe_init_interrupt_scheme(adapter);
5628         if (err)
5629                 goto err_sw_init;
5630
5631         switch (pdev->device) {
5632         case IXGBE_DEV_ID_82599_KX4:
5633                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5634                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5635                 /* Enable ACPI wakeup in GRC */
5636                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5637                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5638                 break;
5639         default:
5640                 adapter->wol = 0;
5641                 break;
5642         }
5643         device_init_wakeup(&adapter->pdev->dev, true);
5644         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5645
5646         /* pick up the PCI bus settings for reporting later */
5647         hw->mac.ops.get_bus_info(hw);
5648
5649         /* print bus type/speed/width info */
5650         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5651                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5652                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5653                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5654                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5655                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5656                  "Unknown"),
5657                 netdev->dev_addr);
5658         ixgbe_read_pba_num_generic(hw, &part_num);
5659         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5660                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5661                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5662                          (part_num >> 8), (part_num & 0xff));
5663         else
5664                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5665                          hw->mac.type, hw->phy.type,
5666                          (part_num >> 8), (part_num & 0xff));
5667
5668         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5669                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5670                          "this card is not sufficient for optimal "
5671                          "performance.\n");
5672                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5673                          "PCI-Express slot is required.\n");
5674         }
5675
5676         /* save off EEPROM version number */
5677         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5678
5679         /* reset the hardware with the new settings */
5680         err = hw->mac.ops.start_hw(hw);
5681
5682         if (err == IXGBE_ERR_EEPROM_VERSION) {
5683                 /* We are running on a pre-production device, log a warning */
5684                 dev_warn(&pdev->dev, "This device is a pre-production "
5685                          "adapter/LOM.  Please be aware there may be issues "
5686                          "associated with your hardware.  If you are "
5687                          "experiencing problems please contact your Intel or "
5688                          "hardware representative who provided you with this "
5689                          "hardware.\n");
5690         }
5691         strcpy(netdev->name, "eth%d");
5692         err = register_netdev(netdev);
5693         if (err)
5694                 goto err_register;
5695
5696         /* carrier off reporting is important to ethtool even BEFORE open */
5697         netif_carrier_off(netdev);
5698
5699         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5700             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5701                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5702
5703 #ifdef CONFIG_IXGBE_DCA
5704         if (dca_add_requester(&pdev->dev) == 0) {
5705                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5706                 ixgbe_setup_dca(adapter);
5707         }
5708 #endif
5709         /* add san mac addr to netdev */
5710         ixgbe_add_sanmac_netdev(netdev);
5711
5712         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5713         cards_found++;
5714         return 0;
5715
5716 err_register:
5717         ixgbe_release_hw_control(adapter);
5718         ixgbe_clear_interrupt_scheme(adapter);
5719 err_sw_init:
5720 err_eeprom:
5721         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5722         del_timer_sync(&adapter->sfp_timer);
5723         cancel_work_sync(&adapter->sfp_task);
5724         cancel_work_sync(&adapter->multispeed_fiber_task);
5725         cancel_work_sync(&adapter->sfp_config_module_task);
5726         iounmap(hw->hw_addr);
5727 err_ioremap:
5728         free_netdev(netdev);
5729 err_alloc_etherdev:
5730         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5731                                      IORESOURCE_MEM));
5732 err_pci_reg:
5733 err_dma:
5734         pci_disable_device(pdev);
5735         return err;
5736 }
5737
5738 /**
5739  * ixgbe_remove - Device Removal Routine
5740  * @pdev: PCI device information struct
5741  *
5742  * ixgbe_remove is called by the PCI subsystem to alert the driver
5743  * that it should release a PCI device.  The could be caused by a
5744  * Hot-Plug event, or because the driver is going to be removed from
5745  * memory.
5746  **/
5747 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5748 {
5749         struct net_device *netdev = pci_get_drvdata(pdev);
5750         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5751         int err;
5752
5753         set_bit(__IXGBE_DOWN, &adapter->state);
5754         /* clear the module not found bit to make sure the worker won't
5755          * reschedule
5756          */
5757         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5758         del_timer_sync(&adapter->watchdog_timer);
5759
5760         del_timer_sync(&adapter->sfp_timer);
5761         cancel_work_sync(&adapter->watchdog_task);
5762         cancel_work_sync(&adapter->sfp_task);
5763         cancel_work_sync(&adapter->multispeed_fiber_task);
5764         cancel_work_sync(&adapter->sfp_config_module_task);
5765         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5766             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5767                 cancel_work_sync(&adapter->fdir_reinit_task);
5768         flush_scheduled_work();
5769
5770 #ifdef CONFIG_IXGBE_DCA
5771         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5772                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5773                 dca_remove_requester(&pdev->dev);
5774                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5775         }
5776
5777 #endif
5778 #ifdef IXGBE_FCOE
5779         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5780                 ixgbe_cleanup_fcoe(adapter);
5781
5782 #endif /* IXGBE_FCOE */
5783
5784         /* remove the added san mac */
5785         ixgbe_del_sanmac_netdev(netdev);
5786
5787         if (netdev->reg_state == NETREG_REGISTERED)
5788                 unregister_netdev(netdev);
5789
5790         ixgbe_clear_interrupt_scheme(adapter);
5791
5792         ixgbe_release_hw_control(adapter);
5793
5794         iounmap(adapter->hw.hw_addr);
5795         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5796                                      IORESOURCE_MEM));
5797
5798         DPRINTK(PROBE, INFO, "complete\n");
5799
5800         free_netdev(netdev);
5801
5802         err = pci_disable_pcie_error_reporting(pdev);
5803         if (err)
5804                 dev_err(&pdev->dev,
5805                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5806
5807         pci_disable_device(pdev);
5808 }
5809
5810 /**
5811  * ixgbe_io_error_detected - called when PCI error is detected
5812  * @pdev: Pointer to PCI device
5813  * @state: The current pci connection state
5814  *
5815  * This function is called after a PCI bus error affecting
5816  * this device has been detected.
5817  */
5818 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5819                                                 pci_channel_state_t state)
5820 {
5821         struct net_device *netdev = pci_get_drvdata(pdev);
5822         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5823
5824         netif_device_detach(netdev);
5825
5826         if (state == pci_channel_io_perm_failure)
5827                 return PCI_ERS_RESULT_DISCONNECT;
5828
5829         if (netif_running(netdev))
5830                 ixgbe_down(adapter);
5831         pci_disable_device(pdev);
5832
5833         /* Request a slot reset. */
5834         return PCI_ERS_RESULT_NEED_RESET;
5835 }
5836
5837 /**
5838  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5839  * @pdev: Pointer to PCI device
5840  *
5841  * Restart the card from scratch, as if from a cold-boot.
5842  */
5843 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5844 {
5845         struct net_device *netdev = pci_get_drvdata(pdev);
5846         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5847         pci_ers_result_t result;
5848         int err;
5849
5850         if (pci_enable_device_mem(pdev)) {
5851                 DPRINTK(PROBE, ERR,
5852                         "Cannot re-enable PCI device after reset.\n");
5853                 result = PCI_ERS_RESULT_DISCONNECT;
5854         } else {
5855                 pci_set_master(pdev);
5856                 pci_restore_state(pdev);
5857
5858                 pci_wake_from_d3(pdev, false);
5859
5860                 ixgbe_reset(adapter);
5861                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5862                 result = PCI_ERS_RESULT_RECOVERED;
5863         }
5864
5865         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5866         if (err) {
5867                 dev_err(&pdev->dev,
5868                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5869                 /* non-fatal, continue */
5870         }
5871
5872         return result;
5873 }
5874
5875 /**
5876  * ixgbe_io_resume - called when traffic can start flowing again.
5877  * @pdev: Pointer to PCI device
5878  *
5879  * This callback is called when the error recovery driver tells us that
5880  * its OK to resume normal operation.
5881  */
5882 static void ixgbe_io_resume(struct pci_dev *pdev)
5883 {
5884         struct net_device *netdev = pci_get_drvdata(pdev);
5885         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5886
5887         if (netif_running(netdev)) {
5888                 if (ixgbe_up(adapter)) {
5889                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5890                         return;
5891                 }
5892         }
5893
5894         netif_device_attach(netdev);
5895 }
5896
5897 static struct pci_error_handlers ixgbe_err_handler = {
5898         .error_detected = ixgbe_io_error_detected,
5899         .slot_reset = ixgbe_io_slot_reset,
5900         .resume = ixgbe_io_resume,
5901 };
5902
5903 static struct pci_driver ixgbe_driver = {
5904         .name     = ixgbe_driver_name,
5905         .id_table = ixgbe_pci_tbl,
5906         .probe    = ixgbe_probe,
5907         .remove   = __devexit_p(ixgbe_remove),
5908 #ifdef CONFIG_PM
5909         .suspend  = ixgbe_suspend,
5910         .resume   = ixgbe_resume,
5911 #endif
5912         .shutdown = ixgbe_shutdown,
5913         .err_handler = &ixgbe_err_handler
5914 };
5915
5916 /**
5917  * ixgbe_init_module - Driver Registration Routine
5918  *
5919  * ixgbe_init_module is the first routine called when the driver is
5920  * loaded. All it does is register with the PCI subsystem.
5921  **/
5922 static int __init ixgbe_init_module(void)
5923 {
5924         int ret;
5925         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5926                ixgbe_driver_string, ixgbe_driver_version);
5927
5928         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5929
5930 #ifdef CONFIG_IXGBE_DCA
5931         dca_register_notify(&dca_notifier);
5932 #endif
5933
5934         ret = pci_register_driver(&ixgbe_driver);
5935         return ret;
5936 }
5937
5938 module_init(ixgbe_init_module);
5939
5940 /**
5941  * ixgbe_exit_module - Driver Exit Cleanup Routine
5942  *
5943  * ixgbe_exit_module is called just before the driver is removed
5944  * from memory.
5945  **/
5946 static void __exit ixgbe_exit_module(void)
5947 {
5948 #ifdef CONFIG_IXGBE_DCA
5949         dca_unregister_notify(&dca_notifier);
5950 #endif
5951         pci_unregister_driver(&ixgbe_driver);
5952 }
5953
5954 #ifdef CONFIG_IXGBE_DCA
5955 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5956                             void *p)
5957 {
5958         int ret_val;
5959
5960         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5961                                          __ixgbe_notify_dca);
5962
5963         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5964 }
5965
5966 #endif /* CONFIG_IXGBE_DCA */
5967 #ifdef DEBUG
5968 /**
5969  * ixgbe_get_hw_dev_name - return device name string
5970  * used by hardware layer to print debugging information
5971  **/
5972 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5973 {
5974         struct ixgbe_adapter *adapter = hw->back;
5975         return adapter->netdev->name;
5976 }
5977
5978 #endif
5979 module_exit(ixgbe_exit_module);
5980
5981 /* ixgbe_main.c */