drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "3.2.9-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62         [board_X540] = &ixgbe_X540_info,
  63 };
  64
  65 /* ixgbe_pci_tbl - PCI Device ID Table
  66  *
  67  * Wildcard entries (PCI_ANY_ID) should come last
  68  * Last entry must be all 0s
  69  *
  70  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  71  *   Class, Class Mask, private data (not used) }
  72  */
  73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  95          board_82598 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  97          board_82598 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 101          board_82599 },
 102         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 103          board_82599 },
 104         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 105          board_82599 },
 106         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 107          board_82599 },
 108         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 109          board_82599 },
 110         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 111          board_82599 },
 112         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 113          board_82599 },
 114         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 115          board_82599 },
 116         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 117          board_82599 },
 118         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 119          board_82599 },
 120         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 121          board_X540 },
 122
 123         /* required last entry */
 124         {0, }
 125 };
 126 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 127
 128 #ifdef CONFIG_IXGBE_DCA
 129 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 130                             void *p);
 131 static struct notifier_block dca_notifier = {
 132         .notifier_call = ixgbe_notify_dca,
 133         .next          = NULL,
 134         .priority      = 0
 135 };
 136 #endif
 137
 138 #ifdef CONFIG_PCI_IOV
 139 static unsigned int max_vfs;
 140 module_param(max_vfs, uint, 0);
 141 MODULE_PARM_DESC(max_vfs,
 142                  "Maximum number of virtual functions to allocate per physical function");
 143 #endif /* CONFIG_PCI_IOV */
 144
 145 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 146 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 147 MODULE_LICENSE("GPL");
 148 MODULE_VERSION(DRV_VERSION);
 149
 150 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 151
 152 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 153 {
 154         struct ixgbe_hw *hw = &adapter->hw;
 155         u32 gcr;
 156         u32 gpie;
 157         u32 vmdctl;
 158
 159 #ifdef CONFIG_PCI_IOV
 160         /* disable iov and allow time for transactions to clear */
 161         pci_disable_sriov(adapter->pdev);
 162 #endif
 163
 164         /* turn off device IOV mode */
 165         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 166         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 167         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 168         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 169         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 170         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 171
 172         /* set default pool back to 0 */
 173         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 174         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 175         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 176
 177         /* take a breather then clean up driver data */
 178         msleep(100);
 179
 180         kfree(adapter->vfinfo);
 181         adapter->vfinfo = NULL;
 182
 183         adapter->num_vfs = 0;
 184         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 185 }
 186
 187 struct ixgbe_reg_info {
 188         u32 ofs;
 189         char *name;
 190 };
 191
 192 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 193
 194         /* General Registers */
 195         {IXGBE_CTRL, "CTRL"},
 196         {IXGBE_STATUS, "STATUS"},
 197         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 198
 199         /* Interrupt Registers */
 200         {IXGBE_EICR, "EICR"},
 201
 202         /* RX Registers */
 203         {IXGBE_SRRCTL(0), "SRRCTL"},
 204         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 205         {IXGBE_RDLEN(0), "RDLEN"},
 206         {IXGBE_RDH(0), "RDH"},
 207         {IXGBE_RDT(0), "RDT"},
 208         {IXGBE_RXDCTL(0), "RXDCTL"},
 209         {IXGBE_RDBAL(0), "RDBAL"},
 210         {IXGBE_RDBAH(0), "RDBAH"},
 211
 212         /* TX Registers */
 213         {IXGBE_TDBAL(0), "TDBAL"},
 214         {IXGBE_TDBAH(0), "TDBAH"},
 215         {IXGBE_TDLEN(0), "TDLEN"},
 216         {IXGBE_TDH(0), "TDH"},
 217         {IXGBE_TDT(0), "TDT"},
 218         {IXGBE_TXDCTL(0), "TXDCTL"},
 219
 220         /* List Terminator */
 221         {}
 222 };
 223
 224
 225 /*
 226  * ixgbe_regdump - register printout routine
 227  */
 228 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 229 {
 230         int i = 0, j = 0;
 231         char rname[16];
 232         u32 regs[64];
 233
 234         switch (reginfo->ofs) {
 235         case IXGBE_SRRCTL(0):
 236                 for (i = 0; i < 64; i++)
 237                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 238                 break;
 239         case IXGBE_DCA_RXCTRL(0):
 240                 for (i = 0; i < 64; i++)
 241                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 242                 break;
 243         case IXGBE_RDLEN(0):
 244                 for (i = 0; i < 64; i++)
 245                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 246                 break;
 247         case IXGBE_RDH(0):
 248                 for (i = 0; i < 64; i++)
 249                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 250                 break;
 251         case IXGBE_RDT(0):
 252                 for (i = 0; i < 64; i++)
 253                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 254                 break;
 255         case IXGBE_RXDCTL(0):
 256                 for (i = 0; i < 64; i++)
 257                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 258                 break;
 259         case IXGBE_RDBAL(0):
 260                 for (i = 0; i < 64; i++)
 261                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 262                 break;
 263         case IXGBE_RDBAH(0):
 264                 for (i = 0; i < 64; i++)
 265                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 266                 break;
 267         case IXGBE_TDBAL(0):
 268                 for (i = 0; i < 64; i++)
 269                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 270                 break;
 271         case IXGBE_TDBAH(0):
 272                 for (i = 0; i < 64; i++)
 273                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 274                 break;
 275         case IXGBE_TDLEN(0):
 276                 for (i = 0; i < 64; i++)
 277                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 278                 break;
 279         case IXGBE_TDH(0):
 280                 for (i = 0; i < 64; i++)
 281                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 282                 break;
 283         case IXGBE_TDT(0):
 284                 for (i = 0; i < 64; i++)
 285                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 286                 break;
 287         case IXGBE_TXDCTL(0):
 288                 for (i = 0; i < 64; i++)
 289                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 290                 break;
 291         default:
 292                 pr_info("%-15s %08x\n", reginfo->name,
 293                         IXGBE_READ_REG(hw, reginfo->ofs));
 294                 return;
 295         }
 296
 297         for (i = 0; i < 8; i++) {
 298                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 299                 pr_err("%-15s", rname);
 300                 for (j = 0; j < 8; j++)
 301                         pr_cont(" %08x", regs[i*8+j]);
 302                 pr_cont("\n");
 303         }
 304
 305 }
 306
 307 /*
 308  * ixgbe_dump - Print registers, tx-rings and rx-rings
 309  */
 310 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 311 {
 312         struct net_device *netdev = adapter->netdev;
 313         struct ixgbe_hw *hw = &adapter->hw;
 314         struct ixgbe_reg_info *reginfo;
 315         int n = 0;
 316         struct ixgbe_ring *tx_ring;
 317         struct ixgbe_tx_buffer *tx_buffer_info;
 318         union ixgbe_adv_tx_desc *tx_desc;
 319         struct my_u0 { u64 a; u64 b; } *u0;
 320         struct ixgbe_ring *rx_ring;
 321         union ixgbe_adv_rx_desc *rx_desc;
 322         struct ixgbe_rx_buffer *rx_buffer_info;
 323         u32 staterr;
 324         int i = 0;
 325
 326         if (!netif_msg_hw(adapter))
 327                 return;
 328
 329         /* Print netdevice Info */
 330         if (netdev) {
 331                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 332                 pr_info("Device Name     state            "
 333                         "trans_start      last_rx\n");
 334                 pr_info("%-15s %016lX %016lX %016lX\n",
 335                         netdev->name,
 336                         netdev->state,
 337                         netdev->trans_start,
 338                         netdev->last_rx);
 339         }
 340
 341         /* Print Registers */
 342         dev_info(&adapter->pdev->dev, "Register Dump\n");
 343         pr_info(" Register Name   Value\n");
 344         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 345              reginfo->name; reginfo++) {
 346                 ixgbe_regdump(hw, reginfo);
 347         }
 348
 349         /* Print TX Ring Summary */
 350         if (!netdev || !netif_running(netdev))
 351                 goto exit;
 352
 353         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 354         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 355         for (n = 0; n < adapter->num_tx_queues; n++) {
 356                 tx_ring = adapter->tx_ring[n];
 357                 tx_buffer_info =
 358                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 359                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 360                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 361                            (u64)tx_buffer_info->dma,
 362                            tx_buffer_info->length,
 363                            tx_buffer_info->next_to_watch,
 364                            (u64)tx_buffer_info->time_stamp);
 365         }
 366
 367         /* Print TX Rings */
 368         if (!netif_msg_tx_done(adapter))
 369                 goto rx_ring_summary;
 370
 371         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 372
 373         /* Transmit Descriptor Formats
 374          *
 375          * Advanced Transmit Descriptor
 376          *   +--------------------------------------------------------------+
 377          * 0 |         Buffer Address [63:0]                                |
 378          *   +--------------------------------------------------------------+
 379          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 380          *   +--------------------------------------------------------------+
 381          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 382          */
 383
 384         for (n = 0; n < adapter->num_tx_queues; n++) {
 385                 tx_ring = adapter->tx_ring[n];
 386                 pr_info("------------------------------------\n");
 387                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 388                 pr_info("------------------------------------\n");
 389                 pr_info("T [desc]     [address 63:0  ] "
 390                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 391                         "leng  ntw timestamp        bi->skb\n");
 392
 393                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 394                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 395                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 396                         u0 = (struct my_u0 *)tx_desc;
 397                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 398                                 " %04X  %3X %016llX %p", i,
 399                                 le64_to_cpu(u0->a),
 400                                 le64_to_cpu(u0->b),
 401                                 (u64)tx_buffer_info->dma,
 402                                 tx_buffer_info->length,
 403                                 tx_buffer_info->next_to_watch,
 404                                 (u64)tx_buffer_info->time_stamp,
 405                                 tx_buffer_info->skb);
 406                         if (i == tx_ring->next_to_use &&
 407                                 i == tx_ring->next_to_clean)
 408                                 pr_cont(" NTC/U\n");
 409                         else if (i == tx_ring->next_to_use)
 410                                 pr_cont(" NTU\n");
 411                         else if (i == tx_ring->next_to_clean)
 412                                 pr_cont(" NTC\n");
 413                         else
 414                                 pr_cont("\n");
 415
 416                         if (netif_msg_pktdata(adapter) &&
 417                                 tx_buffer_info->dma != 0)
 418                                 print_hex_dump(KERN_INFO, "",
 419                                         DUMP_PREFIX_ADDRESS, 16, 1,
 420                                         phys_to_virt(tx_buffer_info->dma),
 421                                         tx_buffer_info->length, true);
 422                 }
 423         }
 424
 425         /* Print RX Rings Summary */
 426 rx_ring_summary:
 427         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 428         pr_info("Queue [NTU] [NTC]\n");
 429         for (n = 0; n < adapter->num_rx_queues; n++) {
 430                 rx_ring = adapter->rx_ring[n];
 431                 pr_info("%5d %5X %5X\n",
 432                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 433         }
 434
 435         /* Print RX Rings */
 436         if (!netif_msg_rx_status(adapter))
 437                 goto exit;
 438
 439         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 440
 441         /* Advanced Receive Descriptor (Read) Format
 442          *    63                                           1        0
 443          *    +-----------------------------------------------------+
 444          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 445          *    +----------------------------------------------+------+
 446          *  8 |       Header Buffer Address [63:1]           |  DD  |
 447          *    +-----------------------------------------------------+
 448          *
 449          *
 450          * Advanced Receive Descriptor (Write-Back) Format
 451          *
 452          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 453          *   +------------------------------------------------------+
 454          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 455          *   | Checksum   Ident  |   |           |    | Type | Type |
 456          *   +------------------------------------------------------+
 457          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 458          *   +------------------------------------------------------+
 459          *   63       48 47    32 31            20 19               0
 460          */
 461         for (n = 0; n < adapter->num_rx_queues; n++) {
 462                 rx_ring = adapter->rx_ring[n];
 463                 pr_info("------------------------------------\n");
 464                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 465                 pr_info("------------------------------------\n");
 466                 pr_info("R  [desc]      [ PktBuf     A0] "
 467                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 468                         "<-- Adv Rx Read format\n");
 469                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 470                         "[vl er S cks ln] ---------------- [bi->skb] "
 471                         "<-- Adv Rx Write-Back format\n");
 472
 473                 for (i = 0; i < rx_ring->count; i++) {
 474                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 475                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 476                         u0 = (struct my_u0 *)rx_desc;
 477                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 478                         if (staterr & IXGBE_RXD_STAT_DD) {
 479                                 /* Descriptor Done */
 480                                 pr_info("RWB[0x%03X]     %016llX "
 481                                         "%016llX ---------------- %p", i,
 482                                         le64_to_cpu(u0->a),
 483                                         le64_to_cpu(u0->b),
 484                                         rx_buffer_info->skb);
 485                         } else {
 486                                 pr_info("R  [0x%03X]     %016llX "
 487                                         "%016llX %016llX %p", i,
 488                                         le64_to_cpu(u0->a),
 489                                         le64_to_cpu(u0->b),
 490                                         (u64)rx_buffer_info->dma,
 491                                         rx_buffer_info->skb);
 492
 493                                 if (netif_msg_pktdata(adapter)) {
 494                                         print_hex_dump(KERN_INFO, "",
 495                                            DUMP_PREFIX_ADDRESS, 16, 1,
 496                                            phys_to_virt(rx_buffer_info->dma),
 497                                            rx_ring->rx_buf_len, true);
 498
 499                                         if (rx_ring->rx_buf_len
 500                                                 < IXGBE_RXBUFFER_2048)
 501                                                 print_hex_dump(KERN_INFO, "",
 502                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 503                                                   phys_to_virt(
 504                                                     rx_buffer_info->page_dma +
 505                                                     rx_buffer_info->page_offset
 506                                                   ),
 507                                                   PAGE_SIZE/2, true);
 508                                 }
 509                         }
 510
 511                         if (i == rx_ring->next_to_use)
 512                                 pr_cont(" NTU\n");
 513                         else if (i == rx_ring->next_to_clean)
 514                                 pr_cont(" NTC\n");
 515                         else
 516                                 pr_cont("\n");
 517
 518                 }
 519         }
 520
 521 exit:
 522         return;
 523 }
 524
 525 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 526 {
 527         u32 ctrl_ext;
 528
 529         /* Let firmware take over control of h/w */
 530         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 531         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 532                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 533 }
 534
 535 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 536 {
 537         u32 ctrl_ext;
 538
 539         /* Let firmware know the driver has taken over */
 540         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 541         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 542                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 543 }
 544
 545 /*
 546  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 547  * @adapter: pointer to adapter struct
 548  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 549  * @queue: queue to map the corresponding interrupt to
 550  * @msix_vector: the vector to map to the corresponding queue
 551  *
 552  */
 553 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 554                            u8 queue, u8 msix_vector)
 555 {
 556         u32 ivar, index;
 557         struct ixgbe_hw *hw = &adapter->hw;
 558         switch (hw->mac.type) {
 559         case ixgbe_mac_82598EB:
 560                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 561                 if (direction == -1)
 562                         direction = 0;
 563                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 564                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 565                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 566                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 567                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 568                 break;
 569         case ixgbe_mac_82599EB:
 570         case ixgbe_mac_X540:
 571                 if (direction == -1) {
 572                         /* other causes */
 573                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 574                         index = ((queue & 1) * 8);
 575                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 576                         ivar &= ~(0xFF << index);
 577                         ivar |= (msix_vector << index);
 578                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 579                         break;
 580                 } else {
 581                         /* tx or rx causes */
 582                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 583                         index = ((16 * (queue & 1)) + (8 * direction));
 584                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 585                         ivar &= ~(0xFF << index);
 586                         ivar |= (msix_vector << index);
 587                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 588                         break;
 589                 }
 590         default:
 591                 break;
 592         }
 593 }
 594
 595 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 596                                           u64 qmask)
 597 {
 598         u32 mask;
 599
 600         switch (adapter->hw.mac.type) {
 601         case ixgbe_mac_82598EB:
 602                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 603                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 604                 break;
 605         case ixgbe_mac_82599EB:
 606         case ixgbe_mac_X540:
 607                 mask = (qmask & 0xFFFFFFFF);
 608                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 609                 mask = (qmask >> 32);
 610                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 611                 break;
 612         default:
 613                 break;
 614         }
 615 }
 616
 617 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 618                                       struct ixgbe_tx_buffer *tx_buffer_info)
 619 {
 620         if (tx_buffer_info->dma) {
 621                 if (tx_buffer_info->mapped_as_page)
 622                         dma_unmap_page(tx_ring->dev,
 623                                        tx_buffer_info->dma,
 624                                        tx_buffer_info->length,
 625                                        DMA_TO_DEVICE);
 626                 else
 627                         dma_unmap_single(tx_ring->dev,
 628                                          tx_buffer_info->dma,
 629                                          tx_buffer_info->length,
 630                                          DMA_TO_DEVICE);
 631                 tx_buffer_info->dma = 0;
 632         }
 633         if (tx_buffer_info->skb) {
 634                 dev_kfree_skb_any(tx_buffer_info->skb);
 635                 tx_buffer_info->skb = NULL;
 636         }
 637         tx_buffer_info->time_stamp = 0;
 638         /* tx_buffer_info must be completely set up in the transmit path */
 639 }
 640
 641 /**
 642  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 643  * @adapter: driver private struct
 644  * @index: reg idx of queue to query (0-127)
 645  *
 646  * Helper function to determine the traffic index for a paticular
 647  * register index.
 648  *
 649  * Returns : a tc index for use in range 0-7, or 0-3
 650  */
 651 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 652 {
 653         int tc = -1;
 654         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 655
 656         /* if DCB is not enabled the queues have no TC */
 657         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 658                 return tc;
 659
 660         /* check valid range */
 661         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 662                 return tc;
 663
 664         switch (adapter->hw.mac.type) {
 665         case ixgbe_mac_82598EB:
 666                 tc = reg_idx >> 2;
 667                 break;
 668         default:
 669                 if (dcb_i != 4 && dcb_i != 8)
 670                         break;
 671
 672                 /* if VMDq is enabled the lowest order bits determine TC */
 673                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 674                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 675                         tc = reg_idx & (dcb_i - 1);
 676                         break;
 677                 }
 678
 679                 /*
 680                  * Convert the reg_idx into the correct TC. This bitmask
 681                  * targets the last full 32 ring traffic class and assigns
 682                  * it a value of 1. From there the rest of the rings are
 683                  * based on shifting the mask further up to include the
 684                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 685                  * will only ever be 8 or 4 and that reg_idx will never
 686                  * be greater then 128. The code without the power of 2
 687                  * optimizations would be:
 688                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 689                  */
 690                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 691                 tc >>= 9 - (reg_idx >> 5);
 692         }
 693
 694         return tc;
 695 }
 696
 697 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 698 {
 699         struct ixgbe_hw *hw = &adapter->hw;
 700         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 701         u32 data = 0;
 702         u32 xoff[8] = {0};
 703         int i;
 704
 705         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 706             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 707                 switch (hw->mac.type) {
 708                 case ixgbe_mac_82598EB:
 709                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 710                         break;
 711                 default:
 712                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 713                 }
 714                 hwstats->lxoffrxc += data;
 715
 716                 /* refill credits (no tx hang) if we received xoff */
 717                 if (!data)
 718                         return;
 719
 720                 for (i = 0; i < adapter->num_tx_queues; i++)
 721                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 722                                   &adapter->tx_ring[i]->state);
 723                 return;
 724         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 725                 return;
 726
 727         /* update stats for each tc, only valid with PFC enabled */
 728         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 729                 switch (hw->mac.type) {
 730                 case ixgbe_mac_82598EB:
 731                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 732                         break;
 733                 default:
 734                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 735                 }
 736                 hwstats->pxoffrxc[i] += xoff[i];
 737         }
 738
 739         /* disarm tx queues that have received xoff frames */
 740         for (i = 0; i < adapter->num_tx_queues; i++) {
 741                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 742                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 743
 744                 if (xoff[tc])
 745                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 746         }
 747 }
 748
 749 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 750 {
 751         return ring->tx_stats.completed;
 752 }
 753
 754 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 755 {
 756         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 757         struct ixgbe_hw *hw = &adapter->hw;
 758
 759         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 760         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 761
 762         if (head != tail)
 763                 return (head < tail) ?
 764                         tail - head : (tail + ring->count - head);
 765
 766         return 0;
 767 }
 768
 769 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 770 {
 771         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 772         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 773         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 774         bool ret = false;
 775
 776         clear_check_for_tx_hang(tx_ring);
 777
 778         /*
 779          * Check for a hung queue, but be thorough. This verifies
 780          * that a transmit has been completed since the previous
 781          * check AND there is at least one packet pending. The
 782          * ARMED bit is set to indicate a potential hang. The
 783          * bit is cleared if a pause frame is received to remove
 784          * false hang detection due to PFC or 802.3x frames. By
 785          * requiring this to fail twice we avoid races with
 786          * pfc clearing the ARMED bit and conditions where we
 787          * run the check_tx_hang logic with a transmit completion
 788          * pending but without time to complete it yet.
 789          */
 790         if ((tx_done_old == tx_done) && tx_pending) {
 791                 /* make sure it is true for two checks in a row */
 792                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 793                                        &tx_ring->state);
 794         } else {
 795                 /* update completed stats and continue */
 796                 tx_ring->tx_stats.tx_done_old = tx_done;
 797                 /* reset the countdown */
 798                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 799         }
 800
 801         return ret;
 802 }
 803
 804 #define IXGBE_MAX_TXD_PWR       14
 805 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 806
 807 /* Tx Descriptors needed, worst case */
 808 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 809                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 810 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 811         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 812
 813 static void ixgbe_tx_timeout(struct net_device *netdev);
 814
 815 /**
 816  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 817  * @q_vector: structure containing interrupt and ring information
 818  * @tx_ring: tx ring to clean
 819  **/
 820 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 821                                struct ixgbe_ring *tx_ring)
 822 {
 823         struct ixgbe_adapter *adapter = q_vector->adapter;
 824         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 825         struct ixgbe_tx_buffer *tx_buffer_info;
 826         unsigned int total_bytes = 0, total_packets = 0;
 827         u16 i, eop, count = 0;
 828
 829         i = tx_ring->next_to_clean;
 830         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 831         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 832
 833         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 834                (count < tx_ring->work_limit)) {
 835                 bool cleaned = false;
 836                 rmb(); /* read buffer_info after eop_desc */
 837                 for ( ; !cleaned; count++) {
 838                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 839                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 840
 841                         tx_desc->wb.status = 0;
 842                         cleaned = (i == eop);
 843
 844                         i++;
 845                         if (i == tx_ring->count)
 846                                 i = 0;
 847
 848                         if (cleaned && tx_buffer_info->skb) {
 849                                 total_bytes += tx_buffer_info->bytecount;
 850                                 total_packets += tx_buffer_info->gso_segs;
 851                         }
 852
 853                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 854                                                          tx_buffer_info);
 855                 }
 856
 857                 tx_ring->tx_stats.completed++;
 858                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 859                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 860         }
 861
 862         tx_ring->next_to_clean = i;
 863         tx_ring->total_bytes += total_bytes;
 864         tx_ring->total_packets += total_packets;
 865         u64_stats_update_begin(&tx_ring->syncp);
 866         tx_ring->stats.packets += total_packets;
 867         tx_ring->stats.bytes += total_bytes;
 868         u64_stats_update_end(&tx_ring->syncp);
 869
 870         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 871                 /* schedule immediate reset if we believe we hung */
 872                 struct ixgbe_hw *hw = &adapter->hw;
 873                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 874                 e_err(drv, "Detected Tx Unit Hang\n"
 875                         "  Tx Queue             <%d>\n"
 876                         "  TDH, TDT             <%x>, <%x>\n"
 877                         "  next_to_use          <%x>\n"
 878                         "  next_to_clean        <%x>\n"
 879                         "tx_buffer_info[next_to_clean]\n"
 880                         "  time_stamp           <%lx>\n"
 881                         "  jiffies              <%lx>\n",
 882                         tx_ring->queue_index,
 883                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 884                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 885                         tx_ring->next_to_use, eop,
 886                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 887
 888                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 889
 890                 e_info(probe,
 891                        "tx hang %d detected on queue %d, resetting adapter\n",
 892                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 893
 894                 /* schedule immediate reset if we believe we hung */
 895                 ixgbe_tx_timeout(adapter->netdev);
 896
 897                 /* the adapter is about to reset, no point in enabling stuff */
 898                 return true;
 899         }
 900
 901 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 902         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 903                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 904                 /* Make sure that anybody stopping the queue after this
 905                  * sees the new next_to_clean.
 906                  */
 907                 smp_mb();
 908                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 909                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 910                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 911                         ++tx_ring->tx_stats.restart_queue;
 912                 }
 913         }
 914
 915         return count < tx_ring->work_limit;
 916 }
 917
 918 #ifdef CONFIG_IXGBE_DCA
 919 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 920                                 struct ixgbe_ring *rx_ring,
 921                                 int cpu)
 922 {
 923         struct ixgbe_hw *hw = &adapter->hw;
 924         u32 rxctrl;
 925         u8 reg_idx = rx_ring->reg_idx;
 926
 927         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 928         switch (hw->mac.type) {
 929         case ixgbe_mac_82598EB:
 930                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 931                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 932                 break;
 933         case ixgbe_mac_82599EB:
 934         case ixgbe_mac_X540:
 935                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 936                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 937                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 938                 break;
 939         default:
 940                 break;
 941         }
 942         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 943         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 944         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 945         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 946                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 947         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 948 }
 949
 950 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 951                                 struct ixgbe_ring *tx_ring,
 952                                 int cpu)
 953 {
 954         struct ixgbe_hw *hw = &adapter->hw;
 955         u32 txctrl;
 956         u8 reg_idx = tx_ring->reg_idx;
 957
 958         switch (hw->mac.type) {
 959         case ixgbe_mac_82598EB:
 960                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 961                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 962                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 963                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 964                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 965                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 966                 break;
 967         case ixgbe_mac_82599EB:
 968         case ixgbe_mac_X540:
 969                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 970                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 971                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 972                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 973                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 974                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 975                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 976                 break;
 977         default:
 978                 break;
 979         }
 980 }
 981
 982 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 983 {
 984         struct ixgbe_adapter *adapter = q_vector->adapter;
 985         int cpu = get_cpu();
 986         long r_idx;
 987         int i;
 988
 989         if (q_vector->cpu == cpu)
 990                 goto out_no_update;
 991
 992         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 993         for (i = 0; i < q_vector->txr_count; i++) {
 994                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 995                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 996                                       r_idx + 1);
 997         }
 998
 999         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1000         for (i = 0; i < q_vector->rxr_count; i++) {
1001                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1002                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1003                                       r_idx + 1);
1004         }
1005
1006         q_vector->cpu = cpu;
1007 out_no_update:
1008         put_cpu();
1009 }
1010
1011 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1012 {
1013         int num_q_vectors;
1014         int i;
1015
1016         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1017                 return;
1018
1019         /* always use CB2 mode, difference is masked in the CB driver */
1020         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1021
1022         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1023                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1024         else
1025                 num_q_vectors = 1;
1026
1027         for (i = 0; i < num_q_vectors; i++) {
1028                 adapter->q_vector[i]->cpu = -1;
1029                 ixgbe_update_dca(adapter->q_vector[i]);
1030         }
1031 }
1032
1033 static int __ixgbe_notify_dca(struct device *dev, void *data)
1034 {
1035         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1036         unsigned long event = *(unsigned long *)data;
1037
1038         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1039                 return 0;
1040
1041         switch (event) {
1042         case DCA_PROVIDER_ADD:
1043                 /* if we're already enabled, don't do it again */
1044                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1045                         break;
1046                 if (dca_add_requester(dev) == 0) {
1047                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1048                         ixgbe_setup_dca(adapter);
1049                         break;
1050                 }
1051                 /* Fall Through since DCA is disabled. */
1052         case DCA_PROVIDER_REMOVE:
1053                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1054                         dca_remove_requester(dev);
1055                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1056                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1057                 }
1058                 break;
1059         }
1060
1061         return 0;
1062 }
1063
1064 #endif /* CONFIG_IXGBE_DCA */
1065 /**
1066  * ixgbe_receive_skb - Send a completed packet up the stack
1067  * @adapter: board private structure
1068  * @skb: packet to send up
1069  * @status: hardware indication of status of receive
1070  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1071  * @rx_desc: rx descriptor
1072  **/
1073 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1074                               struct sk_buff *skb, u8 status,
1075                               struct ixgbe_ring *ring,
1076                               union ixgbe_adv_rx_desc *rx_desc)
1077 {
1078         struct ixgbe_adapter *adapter = q_vector->adapter;
1079         struct napi_struct *napi = &q_vector->napi;
1080         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1081         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1082
1083         if (is_vlan && (tag & VLAN_VID_MASK))
1084                 __vlan_hwaccel_put_tag(skb, tag);
1085
1086         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1087                 napi_gro_receive(napi, skb);
1088         else
1089                 netif_rx(skb);
1090 }
1091
1092 /**
1093  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1094  * @adapter: address of board private structure
1095  * @status_err: hardware indication of status of receive
1096  * @skb: skb currently being received and modified
1097  **/
1098 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1099                                      union ixgbe_adv_rx_desc *rx_desc,
1100                                      struct sk_buff *skb)
1101 {
1102         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1103
1104         skb_checksum_none_assert(skb);
1105
1106         /* Rx csum disabled */
1107         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1108                 return;
1109
1110         /* if IP and error */
1111         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1112             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1113                 adapter->hw_csum_rx_error++;
1114                 return;
1115         }
1116
1117         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1118                 return;
1119
1120         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1121                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1122
1123                 /*
1124                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1125                  * checksum errors.
1126                  */
1127                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1128                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1129                         return;
1130
1131                 adapter->hw_csum_rx_error++;
1132                 return;
1133         }
1134
1135         /* It must be a TCP or UDP packet with a valid checksum */
1136         skb->ip_summed = CHECKSUM_UNNECESSARY;
1137 }
1138
1139 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1140 {
1141         /*
1142          * Force memory writes to complete before letting h/w
1143          * know there are new descriptors to fetch.  (Only
1144          * applicable for weak-ordered memory model archs,
1145          * such as IA-64).
1146          */
1147         wmb();
1148         writel(val, rx_ring->tail);
1149 }
1150
1151 /**
1152  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1153  * @rx_ring: ring to place buffers on
1154  * @cleaned_count: number of buffers to replace
1155  **/
1156 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1157 {
1158         union ixgbe_adv_rx_desc *rx_desc;
1159         struct ixgbe_rx_buffer *bi;
1160         struct sk_buff *skb;
1161         u16 i = rx_ring->next_to_use;
1162
1163         /* do nothing if no valid netdev defined */
1164         if (!rx_ring->netdev)
1165                 return;
1166
1167         while (cleaned_count--) {
1168                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169                 bi = &rx_ring->rx_buffer_info[i];
1170                 skb = bi->skb;
1171
1172                 if (!skb) {
1173                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1174                                                         rx_ring->rx_buf_len);
1175                         if (!skb) {
1176                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1177                                 goto no_buffers;
1178                         }
1179                         /* initialize queue mapping */
1180                         skb_record_rx_queue(skb, rx_ring->queue_index);
1181                         bi->skb = skb;
1182                 }
1183
1184                 if (!bi->dma) {
1185                         bi->dma = dma_map_single(rx_ring->dev,
1186                                                  skb->data,
1187                                                  rx_ring->rx_buf_len,
1188                                                  DMA_FROM_DEVICE);
1189                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1190                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1191                                 bi->dma = 0;
1192                                 goto no_buffers;
1193                         }
1194                 }
1195
1196                 if (ring_is_ps_enabled(rx_ring)) {
1197                         if (!bi->page) {
1198                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1199                                 if (!bi->page) {
1200                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1201                                         goto no_buffers;
1202                                 }
1203                         }
1204
1205                         if (!bi->page_dma) {
1206                                 /* use a half page if we're re-using */
1207                                 bi->page_offset ^= PAGE_SIZE / 2;
1208                                 bi->page_dma = dma_map_page(rx_ring->dev,
1209                                                             bi->page,
1210                                                             bi->page_offset,
1211                                                             PAGE_SIZE / 2,
1212                                                             DMA_FROM_DEVICE);
1213                                 if (dma_mapping_error(rx_ring->dev,
1214                                                       bi->page_dma)) {
1215                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1216                                         bi->page_dma = 0;
1217                                         goto no_buffers;
1218                                 }
1219                         }
1220
1221                         /* Refresh the desc even if buffer_addrs didn't change
1222                          * because each write-back erases this info. */
1223                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1224                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1225                 } else {
1226                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1227                         rx_desc->read.hdr_addr = 0;
1228                 }
1229
1230                 i++;
1231                 if (i == rx_ring->count)
1232                         i = 0;
1233         }
1234
1235 no_buffers:
1236         if (rx_ring->next_to_use != i) {
1237                 rx_ring->next_to_use = i;
1238                 ixgbe_release_rx_desc(rx_ring, i);
1239         }
1240 }
1241
1242 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1243 {
1244         /* HW will not DMA in data larger than the given buffer, even if it
1245          * parses the (NFS, of course) header to be larger.  In that case, it
1246          * fills the header buffer and spills the rest into the page.
1247          */
1248         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1249         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1250                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1251         if (hlen > IXGBE_RX_HDR_SIZE)
1252                 hlen = IXGBE_RX_HDR_SIZE;
1253         return hlen;
1254 }
1255
1256 /**
1257  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1258  * @skb: pointer to the last skb in the rsc queue
1259  *
1260  * This function changes a queue full of hw rsc buffers into a completed
1261  * packet.  It uses the ->prev pointers to find the first packet and then
1262  * turns it into the frag list owner.
1263  **/
1264 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1265 {
1266         unsigned int frag_list_size = 0;
1267         unsigned int skb_cnt = 1;
1268
1269         while (skb->prev) {
1270                 struct sk_buff *prev = skb->prev;
1271                 frag_list_size += skb->len;
1272                 skb->prev = NULL;
1273                 skb = prev;
1274                 skb_cnt++;
1275         }
1276
1277         skb_shinfo(skb)->frag_list = skb->next;
1278         skb->next = NULL;
1279         skb->len += frag_list_size;
1280         skb->data_len += frag_list_size;
1281         skb->truesize += frag_list_size;
1282         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283
1284         return skb;
1285 }
1286
1287 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1288 {
1289         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1290                 IXGBE_RXDADV_RSCCNT_MASK);
1291 }
1292
1293 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1294                                struct ixgbe_ring *rx_ring,
1295                                int *work_done, int work_to_do)
1296 {
1297         struct ixgbe_adapter *adapter = q_vector->adapter;
1298         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1299         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1300         struct sk_buff *skb;
1301         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1302         const int current_node = numa_node_id();
1303 #ifdef IXGBE_FCOE
1304         int ddp_bytes = 0;
1305 #endif /* IXGBE_FCOE */
1306         u32 staterr;
1307         u16 i;
1308         u16 cleaned_count = 0;
1309         bool pkt_is_rsc = false;
1310
1311         i = rx_ring->next_to_clean;
1312         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1313         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1314
1315         while (staterr & IXGBE_RXD_STAT_DD) {
1316                 u32 upper_len = 0;
1317
1318                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1319
1320                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1321
1322                 skb = rx_buffer_info->skb;
1323                 rx_buffer_info->skb = NULL;
1324                 prefetch(skb->data);
1325
1326                 if (ring_is_rsc_enabled(rx_ring))
1327                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1328
1329                 /* if this is a skb from previous receive DMA will be 0 */
1330                 if (rx_buffer_info->dma) {
1331                         u16 hlen;
1332                         if (pkt_is_rsc &&
1333                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1334                             !skb->prev) {
1335                                 /*
1336                                  * When HWRSC is enabled, delay unmapping
1337                                  * of the first packet. It carries the
1338                                  * header information, HW may still
1339                                  * access the header after the writeback.
1340                                  * Only unmap it when EOP is reached
1341                                  */
1342                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1343                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1344                         } else {
1345                                 dma_unmap_single(rx_ring->dev,
1346                                                  rx_buffer_info->dma,
1347                                                  rx_ring->rx_buf_len,
1348                                                  DMA_FROM_DEVICE);
1349                         }
1350                         rx_buffer_info->dma = 0;
1351
1352                         if (ring_is_ps_enabled(rx_ring)) {
1353                                 hlen = ixgbe_get_hlen(rx_desc);
1354                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1355                         } else {
1356                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357                         }
1358
1359                         skb_put(skb, hlen);
1360                 } else {
1361                         /* assume packet split since header is unmapped */
1362                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1363                 }
1364
1365                 if (upper_len) {
1366                         dma_unmap_page(rx_ring->dev,
1367                                        rx_buffer_info->page_dma,
1368                                        PAGE_SIZE / 2,
1369                                        DMA_FROM_DEVICE);
1370                         rx_buffer_info->page_dma = 0;
1371                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1372                                            rx_buffer_info->page,
1373                                            rx_buffer_info->page_offset,
1374                                            upper_len);
1375
1376                         if ((page_count(rx_buffer_info->page) == 1) &&
1377                             (page_to_nid(rx_buffer_info->page) == current_node))
1378                                 get_page(rx_buffer_info->page);
1379                         else
1380                                 rx_buffer_info->page = NULL;
1381
1382                         skb->len += upper_len;
1383                         skb->data_len += upper_len;
1384                         skb->truesize += upper_len;
1385                 }
1386
1387                 i++;
1388                 if (i == rx_ring->count)
1389                         i = 0;
1390
1391                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1392                 prefetch(next_rxd);
1393                 cleaned_count++;
1394
1395                 if (pkt_is_rsc) {
1396                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1397                                      IXGBE_RXDADV_NEXTP_SHIFT;
1398                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1399                 } else {
1400                         next_buffer = &rx_ring->rx_buffer_info[i];
1401                 }
1402
1403                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1404                         if (ring_is_ps_enabled(rx_ring)) {
1405                                 rx_buffer_info->skb = next_buffer->skb;
1406                                 rx_buffer_info->dma = next_buffer->dma;
1407                                 next_buffer->skb = skb;
1408                                 next_buffer->dma = 0;
1409                         } else {
1410                                 skb->next = next_buffer->skb;
1411                                 skb->next->prev = skb;
1412                         }
1413                         rx_ring->rx_stats.non_eop_descs++;
1414                         goto next_desc;
1415                 }
1416
1417                 if (skb->prev) {
1418                         skb = ixgbe_transform_rsc_queue(skb);
1419                         /* if we got here without RSC the packet is invalid */
1420                         if (!pkt_is_rsc) {
1421                                 __pskb_trim(skb, 0);
1422                                 rx_buffer_info->skb = skb;
1423                                 goto next_desc;
1424                         }
1425                 }
1426
1427                 if (ring_is_rsc_enabled(rx_ring)) {
1428                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1429                                 dma_unmap_single(rx_ring->dev,
1430                                                  IXGBE_RSC_CB(skb)->dma,
1431                                                  rx_ring->rx_buf_len,
1432                                                  DMA_FROM_DEVICE);
1433                                 IXGBE_RSC_CB(skb)->dma = 0;
1434                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1435                         }
1436                 }
1437                 if (pkt_is_rsc) {
1438                         if (ring_is_ps_enabled(rx_ring))
1439                                 rx_ring->rx_stats.rsc_count +=
1440                                         skb_shinfo(skb)->nr_frags;
1441                         else
1442                                 rx_ring->rx_stats.rsc_count +=
1443                                         IXGBE_RSC_CB(skb)->skb_cnt;
1444                         rx_ring->rx_stats.rsc_flush++;
1445                 }
1446
1447                 /* ERR_MASK will only have valid bits if EOP set */
1448                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1449                         /* trim packet back to size 0 and recycle it */
1450                         __pskb_trim(skb, 0);
1451                         rx_buffer_info->skb = skb;
1452                         goto next_desc;
1453                 }
1454
1455                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1456
1457                 /* probably a little skewed due to removing CRC */
1458                 total_rx_bytes += skb->len;
1459                 total_rx_packets++;
1460
1461                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1462 #ifdef IXGBE_FCOE
1463                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1464                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1465                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1466                         if (!ddp_bytes)
1467                                 goto next_desc;
1468                 }
1469 #endif /* IXGBE_FCOE */
1470                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1471
1472 next_desc:
1473                 rx_desc->wb.upper.status_error = 0;
1474
1475                 (*work_done)++;
1476                 if (*work_done >= work_to_do)
1477                         break;
1478
1479                 /* return some buffers to hardware, one at a time is too slow */
1480                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1481                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482                         cleaned_count = 0;
1483                 }
1484
1485                 /* use prefetched values */
1486                 rx_desc = next_rxd;
1487                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1488         }
1489
1490         rx_ring->next_to_clean = i;
1491         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1492
1493         if (cleaned_count)
1494                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1495
1496 #ifdef IXGBE_FCOE
1497         /* include DDPed FCoE data */
1498         if (ddp_bytes > 0) {
1499                 unsigned int mss;
1500
1501                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1502                         sizeof(struct fc_frame_header) -
1503                         sizeof(struct fcoe_crc_eof);
1504                 if (mss > 512)
1505                         mss &= ~511;
1506                 total_rx_bytes += ddp_bytes;
1507                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1508         }
1509 #endif /* IXGBE_FCOE */
1510
1511         rx_ring->total_packets += total_rx_packets;
1512         rx_ring->total_bytes += total_rx_bytes;
1513         u64_stats_update_begin(&rx_ring->syncp);
1514         rx_ring->stats.packets += total_rx_packets;
1515         rx_ring->stats.bytes += total_rx_bytes;
1516         u64_stats_update_end(&rx_ring->syncp);
1517 }
1518
1519 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1520 /**
1521  * ixgbe_configure_msix - Configure MSI-X hardware
1522  * @adapter: board private structure
1523  *
1524  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1525  * interrupts.
1526  **/
1527 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1528 {
1529         struct ixgbe_q_vector *q_vector;
1530         int i, q_vectors, v_idx, r_idx;
1531         u32 mask;
1532
1533         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1534
1535         /*
1536          * Populate the IVAR table and set the ITR values to the
1537          * corresponding register.
1538          */
1539         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1540                 q_vector = adapter->q_vector[v_idx];
1541                 /* XXX for_each_set_bit(...) */
1542                 r_idx = find_first_bit(q_vector->rxr_idx,
1543                                        adapter->num_rx_queues);
1544
1545                 for (i = 0; i < q_vector->rxr_count; i++) {
1546                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1547                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1548                         r_idx = find_next_bit(q_vector->rxr_idx,
1549                                               adapter->num_rx_queues,
1550                                               r_idx + 1);
1551                 }
1552                 r_idx = find_first_bit(q_vector->txr_idx,
1553                                        adapter->num_tx_queues);
1554
1555                 for (i = 0; i < q_vector->txr_count; i++) {
1556                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1557                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1558                         r_idx = find_next_bit(q_vector->txr_idx,
1559                                               adapter->num_tx_queues,
1560                                               r_idx + 1);
1561                 }
1562
1563                 if (q_vector->txr_count && !q_vector->rxr_count)
1564                         /* tx only */
1565                         q_vector->eitr = adapter->tx_eitr_param;
1566                 else if (q_vector->rxr_count)
1567                         /* rx or mixed */
1568                         q_vector->eitr = adapter->rx_eitr_param;
1569
1570                 ixgbe_write_eitr(q_vector);
1571                 /* If Flow Director is enabled, set interrupt affinity */
1572                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1573                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1574                         /*
1575                          * Allocate the affinity_hint cpumask, assign the mask
1576                          * for this vector, and set our affinity_hint for
1577                          * this irq.
1578                          */
1579                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1580                                                GFP_KERNEL))
1581                                 return;
1582                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1583                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1584                                               q_vector->affinity_mask);
1585                 }
1586         }
1587
1588         switch (adapter->hw.mac.type) {
1589         case ixgbe_mac_82598EB:
1590                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1591                                v_idx);
1592                 break;
1593         case ixgbe_mac_82599EB:
1594         case ixgbe_mac_X540:
1595                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1596                 break;
1597
1598         default:
1599                 break;
1600         }
1601         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1602
1603         /* set up to autoclear timer, and the vectors */
1604         mask = IXGBE_EIMS_ENABLE_MASK;
1605         if (adapter->num_vfs)
1606                 mask &= ~(IXGBE_EIMS_OTHER |
1607                           IXGBE_EIMS_MAILBOX |
1608                           IXGBE_EIMS_LSC);
1609         else
1610                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1611         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1612 }
1613
1614 enum latency_range {
1615         lowest_latency = 0,
1616         low_latency = 1,
1617         bulk_latency = 2,
1618         latency_invalid = 255
1619 };
1620
1621 /**
1622  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1623  * @adapter: pointer to adapter
1624  * @eitr: eitr setting (ints per sec) to give last timeslice
1625  * @itr_setting: current throttle rate in ints/second
1626  * @packets: the number of packets during this measurement interval
1627  * @bytes: the number of bytes during this measurement interval
1628  *
1629  *      Stores a new ITR value based on packets and byte
1630  *      counts during the last interrupt.  The advantage of per interrupt
1631  *      computation is faster updates and more accurate ITR for the current
1632  *      traffic pattern.  Constants in this function were computed
1633  *      based on theoretical maximum wire speed and thresholds were set based
1634  *      on testing data as well as attempting to minimize response time
1635  *      while increasing bulk throughput.
1636  *      this functionality is controlled by the InterruptThrottleRate module
1637  *      parameter (see ixgbe_param.c)
1638  **/
1639 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1640                            u32 eitr, u8 itr_setting,
1641                            int packets, int bytes)
1642 {
1643         unsigned int retval = itr_setting;
1644         u32 timepassed_us;
1645         u64 bytes_perint;
1646
1647         if (packets == 0)
1648                 goto update_itr_done;
1649
1650
1651         /* simple throttlerate management
1652          *    0-20MB/s lowest (100000 ints/s)
1653          *   20-100MB/s low   (20000 ints/s)
1654          *  100-1249MB/s bulk (8000 ints/s)
1655          */
1656         /* what was last interrupt timeslice? */
1657         timepassed_us = 1000000/eitr;
1658         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1659
1660         switch (itr_setting) {
1661         case lowest_latency:
1662                 if (bytes_perint > adapter->eitr_low)
1663                         retval = low_latency;
1664                 break;
1665         case low_latency:
1666                 if (bytes_perint > adapter->eitr_high)
1667                         retval = bulk_latency;
1668                 else if (bytes_perint <= adapter->eitr_low)
1669                         retval = lowest_latency;
1670                 break;
1671         case bulk_latency:
1672                 if (bytes_perint <= adapter->eitr_high)
1673                         retval = low_latency;
1674                 break;
1675         }
1676
1677 update_itr_done:
1678         return retval;
1679 }
1680
1681 /**
1682  * ixgbe_write_eitr - write EITR register in hardware specific way
1683  * @q_vector: structure containing interrupt and ring information
1684  *
1685  * This function is made to be called by ethtool and by the driver
1686  * when it needs to update EITR registers at runtime.  Hardware
1687  * specific quirks/differences are taken care of here.
1688  */
1689 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1690 {
1691         struct ixgbe_adapter *adapter = q_vector->adapter;
1692         struct ixgbe_hw *hw = &adapter->hw;
1693         int v_idx = q_vector->v_idx;
1694         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1695
1696         switch (adapter->hw.mac.type) {
1697         case ixgbe_mac_82598EB:
1698                 /* must write high and low 16 bits to reset counter */
1699                 itr_reg |= (itr_reg << 16);
1700                 break;
1701         case ixgbe_mac_82599EB:
1702         case ixgbe_mac_X540:
1703                 /*
1704                  * 82599 and X540 can support a value of zero, so allow it for
1705                  * max interrupt rate, but there is an errata where it can
1706                  * not be zero with RSC
1707                  */
1708                 if (itr_reg == 8 &&
1709                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1710                         itr_reg = 0;
1711
1712                 /*
1713                  * set the WDIS bit to not clear the timer bits and cause an
1714                  * immediate assertion of the interrupt
1715                  */
1716                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1717                 break;
1718         default:
1719                 break;
1720         }
1721         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722 }
1723
1724 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1725 {
1726         struct ixgbe_adapter *adapter = q_vector->adapter;
1727         int i, r_idx;
1728         u32 new_itr;
1729         u8 current_itr, ret_itr;
1730
1731         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1732         for (i = 0; i < q_vector->txr_count; i++) {
1733                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1734                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1735                                            q_vector->tx_itr,
1736                                            tx_ring->total_packets,
1737                                            tx_ring->total_bytes);
1738                 /* if the result for this queue would decrease interrupt
1739                  * rate for this vector then use that result */
1740                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1741                                     q_vector->tx_itr - 1 : ret_itr);
1742                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1743                                       r_idx + 1);
1744         }
1745
1746         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1747         for (i = 0; i < q_vector->rxr_count; i++) {
1748                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1749                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1750                                            q_vector->rx_itr,
1751                                            rx_ring->total_packets,
1752                                            rx_ring->total_bytes);
1753                 /* if the result for this queue would decrease interrupt
1754                  * rate for this vector then use that result */
1755                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1756                                     q_vector->rx_itr - 1 : ret_itr);
1757                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1758                                       r_idx + 1);
1759         }
1760
1761         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1762
1763         switch (current_itr) {
1764         /* counts and packets in update_itr are dependent on these numbers */
1765         case lowest_latency:
1766                 new_itr = 100000;
1767                 break;
1768         case low_latency:
1769                 new_itr = 20000; /* aka hwitr = ~200 */
1770                 break;
1771         case bulk_latency:
1772         default:
1773                 new_itr = 8000;
1774                 break;
1775         }
1776
1777         if (new_itr != q_vector->eitr) {
1778                 /* do an exponential smoothing */
1779                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1780
1781                 /* save the algorithm value here, not the smoothed one */
1782                 q_vector->eitr = new_itr;
1783
1784                 ixgbe_write_eitr(q_vector);
1785         }
1786 }
1787
1788 /**
1789  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1790  * @work: pointer to work_struct containing our data
1791  **/
1792 static void ixgbe_check_overtemp_task(struct work_struct *work)
1793 {
1794         struct ixgbe_adapter *adapter = container_of(work,
1795                                                      struct ixgbe_adapter,
1796                                                      check_overtemp_task);
1797         struct ixgbe_hw *hw = &adapter->hw;
1798         u32 eicr = adapter->interrupt_event;
1799
1800         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1801                 return;
1802
1803         switch (hw->device_id) {
1804         case IXGBE_DEV_ID_82599_T3_LOM: {
1805                 u32 autoneg;
1806                 bool link_up = false;
1807
1808                 if (hw->mac.ops.check_link)
1809                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1812                     (eicr & IXGBE_EICR_LSC))
1813                         /* Check if this is due to overtemp */
1814                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1815                                 break;
1816                 return;
1817         }
1818         default:
1819                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1820                         return;
1821                 break;
1822         }
1823         e_crit(drv,
1824                "Network adapter has been stopped because it has over heated. "
1825                "Restart the computer. If the problem persists, "
1826                "power off the system and replace the adapter\n");
1827         /* write to clear the interrupt */
1828         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1829 }
1830
1831 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1832 {
1833         struct ixgbe_hw *hw = &adapter->hw;
1834
1835         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1836             (eicr & IXGBE_EICR_GPI_SDP1)) {
1837                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1838                 /* write to clear the interrupt */
1839                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1840         }
1841 }
1842
1843 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1844 {
1845         struct ixgbe_hw *hw = &adapter->hw;
1846
1847         if (eicr & IXGBE_EICR_GPI_SDP2) {
1848                 /* Clear the interrupt */
1849                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1850                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1851                         schedule_work(&adapter->sfp_config_module_task);
1852         }
1853
1854         if (eicr & IXGBE_EICR_GPI_SDP1) {
1855                 /* Clear the interrupt */
1856                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1857                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1858                         schedule_work(&adapter->multispeed_fiber_task);
1859         }
1860 }
1861
1862 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1863 {
1864         struct ixgbe_hw *hw = &adapter->hw;
1865
1866         adapter->lsc_int++;
1867         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1868         adapter->link_check_timeout = jiffies;
1869         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1871                 IXGBE_WRITE_FLUSH(hw);
1872                 schedule_work(&adapter->watchdog_task);
1873         }
1874 }
1875
1876 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1877 {
1878         struct net_device *netdev = data;
1879         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880         struct ixgbe_hw *hw = &adapter->hw;
1881         u32 eicr;
1882
1883         /*
1884          * Workaround for Silicon errata.  Use clear-by-write instead
1885          * of clear-by-read.  Reading with EICS will return the
1886          * interrupt causes without clearing, which later be done
1887          * with the write to EICR.
1888          */
1889         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1890         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1891
1892         if (eicr & IXGBE_EICR_LSC)
1893                 ixgbe_check_lsc(adapter);
1894
1895         if (eicr & IXGBE_EICR_MAILBOX)
1896                 ixgbe_msg_task(adapter);
1897
1898         switch (hw->mac.type) {
1899         case ixgbe_mac_82599EB:
1900                 ixgbe_check_sfp_event(adapter, eicr);
1901                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1902                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1903                         adapter->interrupt_event = eicr;
1904                         schedule_work(&adapter->check_overtemp_task);
1905                 }
1906                 /* now fallthrough to handle Flow Director */
1907         case ixgbe_mac_X540:
1908                 /* Handle Flow Director Full threshold interrupt */
1909                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1910                         int i;
1911                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1912                         /* Disable transmits before FDIR Re-initialization */
1913                         netif_tx_stop_all_queues(netdev);
1914                         for (i = 0; i < adapter->num_tx_queues; i++) {
1915                                 struct ixgbe_ring *tx_ring =
1916                                                             adapter->tx_ring[i];
1917                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1918                                                        &tx_ring->state))
1919                                         schedule_work(&adapter->fdir_reinit_task);
1920                         }
1921                 }
1922                 break;
1923         default:
1924                 break;
1925         }
1926
1927         ixgbe_check_fan_failure(adapter, eicr);
1928
1929         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1930                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1931
1932         return IRQ_HANDLED;
1933 }
1934
1935 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1936                                            u64 qmask)
1937 {
1938         u32 mask;
1939         struct ixgbe_hw *hw = &adapter->hw;
1940
1941         switch (hw->mac.type) {
1942         case ixgbe_mac_82598EB:
1943                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1944                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1945                 break;
1946         case ixgbe_mac_82599EB:
1947         case ixgbe_mac_X540:
1948                 mask = (qmask & 0xFFFFFFFF);
1949                 if (mask)
1950                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1951                 mask = (qmask >> 32);
1952                 if (mask)
1953                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1954                 break;
1955         default:
1956                 break;
1957         }
1958         /* skip the flush */
1959 }
1960
1961 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1962                                             u64 qmask)
1963 {
1964         u32 mask;
1965         struct ixgbe_hw *hw = &adapter->hw;
1966
1967         switch (hw->mac.type) {
1968         case ixgbe_mac_82598EB:
1969                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1970                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1971                 break;
1972         case ixgbe_mac_82599EB:
1973         case ixgbe_mac_X540:
1974                 mask = (qmask & 0xFFFFFFFF);
1975                 if (mask)
1976                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1977                 mask = (qmask >> 32);
1978                 if (mask)
1979                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1980                 break;
1981         default:
1982                 break;
1983         }
1984         /* skip the flush */
1985 }
1986
1987 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1988 {
1989         struct ixgbe_q_vector *q_vector = data;
1990         struct ixgbe_adapter  *adapter = q_vector->adapter;
1991         struct ixgbe_ring     *tx_ring;
1992         int i, r_idx;
1993
1994         if (!q_vector->txr_count)
1995                 return IRQ_HANDLED;
1996
1997         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1998         for (i = 0; i < q_vector->txr_count; i++) {
1999                 tx_ring = adapter->tx_ring[r_idx];
2000                 tx_ring->total_bytes = 0;
2001                 tx_ring->total_packets = 0;
2002                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2003                                       r_idx + 1);
2004         }
2005
2006         /* EIAM disabled interrupts (on this vector) for us */
2007         napi_schedule(&q_vector->napi);
2008
2009         return IRQ_HANDLED;
2010 }
2011
2012 /**
2013  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2014  * @irq: unused
2015  * @data: pointer to our q_vector struct for this interrupt vector
2016  **/
2017 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2018 {
2019         struct ixgbe_q_vector *q_vector = data;
2020         struct ixgbe_adapter  *adapter = q_vector->adapter;
2021         struct ixgbe_ring  *rx_ring;
2022         int r_idx;
2023         int i;
2024
2025 #ifdef CONFIG_IXGBE_DCA
2026         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2027                 ixgbe_update_dca(q_vector);
2028 #endif
2029
2030         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2031         for (i = 0; i < q_vector->rxr_count; i++) {
2032                 rx_ring = adapter->rx_ring[r_idx];
2033                 rx_ring->total_bytes = 0;
2034                 rx_ring->total_packets = 0;
2035                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2036                                       r_idx + 1);
2037         }
2038
2039         if (!q_vector->rxr_count)
2040                 return IRQ_HANDLED;
2041
2042         /* EIAM disabled interrupts (on this vector) for us */
2043         napi_schedule(&q_vector->napi);
2044
2045         return IRQ_HANDLED;
2046 }
2047
2048 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2049 {
2050         struct ixgbe_q_vector *q_vector = data;
2051         struct ixgbe_adapter  *adapter = q_vector->adapter;
2052         struct ixgbe_ring  *ring;
2053         int r_idx;
2054         int i;
2055
2056         if (!q_vector->txr_count && !q_vector->rxr_count)
2057                 return IRQ_HANDLED;
2058
2059         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2060         for (i = 0; i < q_vector->txr_count; i++) {
2061                 ring = adapter->tx_ring[r_idx];
2062                 ring->total_bytes = 0;
2063                 ring->total_packets = 0;
2064                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2065                                       r_idx + 1);
2066         }
2067
2068         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2069         for (i = 0; i < q_vector->rxr_count; i++) {
2070                 ring = adapter->rx_ring[r_idx];
2071                 ring->total_bytes = 0;
2072                 ring->total_packets = 0;
2073                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2074                                       r_idx + 1);
2075         }
2076
2077         /* EIAM disabled interrupts (on this vector) for us */
2078         napi_schedule(&q_vector->napi);
2079
2080         return IRQ_HANDLED;
2081 }
2082
2083 /**
2084  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2085  * @napi: napi struct with our devices info in it
2086  * @budget: amount of work driver is allowed to do this pass, in packets
2087  *
2088  * This function is optimized for cleaning one queue only on a single
2089  * q_vector!!!
2090  **/
2091 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2092 {
2093         struct ixgbe_q_vector *q_vector =
2094                                container_of(napi, struct ixgbe_q_vector, napi);
2095         struct ixgbe_adapter *adapter = q_vector->adapter;
2096         struct ixgbe_ring *rx_ring = NULL;
2097         int work_done = 0;
2098         long r_idx;
2099
2100 #ifdef CONFIG_IXGBE_DCA
2101         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2102                 ixgbe_update_dca(q_vector);
2103 #endif
2104
2105         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2106         rx_ring = adapter->rx_ring[r_idx];
2107
2108         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2109
2110         /* If all Rx work done, exit the polling mode */
2111         if (work_done < budget) {
2112                 napi_complete(napi);
2113                 if (adapter->rx_itr_setting & 1)
2114                         ixgbe_set_itr_msix(q_vector);
2115                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2116                         ixgbe_irq_enable_queues(adapter,
2117                                                 ((u64)1 << q_vector->v_idx));
2118         }
2119
2120         return work_done;
2121 }
2122
2123 /**
2124  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2125  * @napi: napi struct with our devices info in it
2126  * @budget: amount of work driver is allowed to do this pass, in packets
2127  *
2128  * This function will clean more than one rx queue associated with a
2129  * q_vector.
2130  **/
2131 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2132 {
2133         struct ixgbe_q_vector *q_vector =
2134                                container_of(napi, struct ixgbe_q_vector, napi);
2135         struct ixgbe_adapter *adapter = q_vector->adapter;
2136         struct ixgbe_ring *ring = NULL;
2137         int work_done = 0, i;
2138         long r_idx;
2139         bool tx_clean_complete = true;
2140
2141 #ifdef CONFIG_IXGBE_DCA
2142         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2143                 ixgbe_update_dca(q_vector);
2144 #endif
2145
2146         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2147         for (i = 0; i < q_vector->txr_count; i++) {
2148                 ring = adapter->tx_ring[r_idx];
2149                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2150                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2151                                       r_idx + 1);
2152         }
2153
2154         /* attempt to distribute budget to each queue fairly, but don't allow
2155          * the budget to go below 1 because we'll exit polling */
2156         budget /= (q_vector->rxr_count ?: 1);
2157         budget = max(budget, 1);
2158         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2159         for (i = 0; i < q_vector->rxr_count; i++) {
2160                 ring = adapter->rx_ring[r_idx];
2161                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2162                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2163                                       r_idx + 1);
2164         }
2165
2166         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2167         ring = adapter->rx_ring[r_idx];
2168         /* If all Rx work done, exit the polling mode */
2169         if (work_done < budget) {
2170                 napi_complete(napi);
2171                 if (adapter->rx_itr_setting & 1)
2172                         ixgbe_set_itr_msix(q_vector);
2173                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2174                         ixgbe_irq_enable_queues(adapter,
2175                                                 ((u64)1 << q_vector->v_idx));
2176                 return 0;
2177         }
2178
2179         return work_done;
2180 }
2181
2182 /**
2183  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2184  * @napi: napi struct with our devices info in it
2185  * @budget: amount of work driver is allowed to do this pass, in packets
2186  *
2187  * This function is optimized for cleaning one queue only on a single
2188  * q_vector!!!
2189  **/
2190 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2191 {
2192         struct ixgbe_q_vector *q_vector =
2193                                container_of(napi, struct ixgbe_q_vector, napi);
2194         struct ixgbe_adapter *adapter = q_vector->adapter;
2195         struct ixgbe_ring *tx_ring = NULL;
2196         int work_done = 0;
2197         long r_idx;
2198
2199 #ifdef CONFIG_IXGBE_DCA
2200         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2201                 ixgbe_update_dca(q_vector);
2202 #endif
2203
2204         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2205         tx_ring = adapter->tx_ring[r_idx];
2206
2207         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2208                 work_done = budget;
2209
2210         /* If all Tx work done, exit the polling mode */
2211         if (work_done < budget) {
2212                 napi_complete(napi);
2213                 if (adapter->tx_itr_setting & 1)
2214                         ixgbe_set_itr_msix(q_vector);
2215                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2216                         ixgbe_irq_enable_queues(adapter,
2217                                                 ((u64)1 << q_vector->v_idx));
2218         }
2219
2220         return work_done;
2221 }
2222
2223 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2224                                      int r_idx)
2225 {
2226         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2228
2229         set_bit(r_idx, q_vector->rxr_idx);
2230         q_vector->rxr_count++;
2231         rx_ring->q_vector = q_vector;
2232 }
2233
2234 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2235                                      int t_idx)
2236 {
2237         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2239
2240         set_bit(t_idx, q_vector->txr_idx);
2241         q_vector->txr_count++;
2242         tx_ring->q_vector = q_vector;
2243 }
2244
2245 /**
2246  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2247  * @adapter: board private structure to initialize
2248  *
2249  * This function maps descriptor rings to the queue-specific vectors
2250  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2251  * one vector per ring/queue, but on a constrained vector budget, we
2252  * group the rings as "efficiently" as possible.  You would add new
2253  * mapping configurations in here.
2254  **/
2255 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2256 {
2257         int q_vectors;
2258         int v_start = 0;
2259         int rxr_idx = 0, txr_idx = 0;
2260         int rxr_remaining = adapter->num_rx_queues;
2261         int txr_remaining = adapter->num_tx_queues;
2262         int i, j;
2263         int rqpv, tqpv;
2264         int err = 0;
2265
2266         /* No mapping required if MSI-X is disabled. */
2267         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2268                 goto out;
2269
2270         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2271
2272         /*
2273          * The ideal configuration...
2274          * We have enough vectors to map one per queue.
2275          */
2276         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2277                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2278                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2279
2280                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2281                         map_vector_to_txq(adapter, v_start, txr_idx);
2282
2283                 goto out;
2284         }
2285
2286         /*
2287          * If we don't have enough vectors for a 1-to-1
2288          * mapping, we'll have to group them so there are
2289          * multiple queues per vector.
2290          */
2291         /* Re-adjusting *qpv takes care of the remainder. */
2292         for (i = v_start; i < q_vectors; i++) {
2293                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2294                 for (j = 0; j < rqpv; j++) {
2295                         map_vector_to_rxq(adapter, i, rxr_idx);
2296                         rxr_idx++;
2297                         rxr_remaining--;
2298                 }
2299                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2300                 for (j = 0; j < tqpv; j++) {
2301                         map_vector_to_txq(adapter, i, txr_idx);
2302                         txr_idx++;
2303                         txr_remaining--;
2304                 }
2305         }
2306 out:
2307         return err;
2308 }
2309
2310 /**
2311  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2312  * @adapter: board private structure
2313  *
2314  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2315  * interrupts from the kernel.
2316  **/
2317 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2318 {
2319         struct net_device *netdev = adapter->netdev;
2320         irqreturn_t (*handler)(int, void *);
2321         int i, vector, q_vectors, err;
2322         int ri = 0, ti = 0;
2323
2324         /* Decrement for Other and TCP Timer vectors */
2325         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2326
2327         err = ixgbe_map_rings_to_vectors(adapter);
2328         if (err)
2329                 return err;
2330
2331 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2332                                           ? &ixgbe_msix_clean_many : \
2333                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2334                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2335                           NULL)
2336         for (vector = 0; vector < q_vectors; vector++) {
2337                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2338                 handler = SET_HANDLER(q_vector);
2339
2340                 if (handler == &ixgbe_msix_clean_rx) {
2341                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2342                                  "%s-%s-%d", netdev->name, "rx", ri++);
2343                 } else if (handler == &ixgbe_msix_clean_tx) {
2344                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2345                                  "%s-%s-%d", netdev->name, "tx", ti++);
2346                 } else if (handler == &ixgbe_msix_clean_many) {
2347                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2348                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2349                         ti++;
2350                 } else {
2351                         /* skip this unused q_vector */
2352                         continue;
2353                 }
2354                 err = request_irq(adapter->msix_entries[vector].vector,
2355                                   handler, 0, q_vector->name,
2356                                   q_vector);
2357                 if (err) {
2358                         e_err(probe, "request_irq failed for MSIX interrupt "
2359                               "Error: %d\n", err);
2360                         goto free_queue_irqs;
2361                 }
2362         }
2363
2364         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2365         err = request_irq(adapter->msix_entries[vector].vector,
2366                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2367         if (err) {
2368                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2369                 goto free_queue_irqs;
2370         }
2371
2372         return 0;
2373
2374 free_queue_irqs:
2375         for (i = vector - 1; i >= 0; i--)
2376                 free_irq(adapter->msix_entries[--vector].vector,
2377                          adapter->q_vector[i]);
2378         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2379         pci_disable_msix(adapter->pdev);
2380         kfree(adapter->msix_entries);
2381         adapter->msix_entries = NULL;
2382         return err;
2383 }
2384
2385 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2386 {
2387         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2388         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2389         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2390         u32 new_itr = q_vector->eitr;
2391         u8 current_itr;
2392
2393         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2394                                             q_vector->tx_itr,
2395                                             tx_ring->total_packets,
2396                                             tx_ring->total_bytes);
2397         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2398                                             q_vector->rx_itr,
2399                                             rx_ring->total_packets,
2400                                             rx_ring->total_bytes);
2401
2402         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2403
2404         switch (current_itr) {
2405         /* counts and packets in update_itr are dependent on these numbers */
2406         case lowest_latency:
2407                 new_itr = 100000;
2408                 break;
2409         case low_latency:
2410                 new_itr = 20000; /* aka hwitr = ~200 */
2411                 break;
2412         case bulk_latency:
2413                 new_itr = 8000;
2414                 break;
2415         default:
2416                 break;
2417         }
2418
2419         if (new_itr != q_vector->eitr) {
2420                 /* do an exponential smoothing */
2421                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2422
2423                 /* save the algorithm value here */
2424                 q_vector->eitr = new_itr;
2425
2426                 ixgbe_write_eitr(q_vector);
2427         }
2428 }
2429
2430 /**
2431  * ixgbe_irq_enable - Enable default interrupt generation settings
2432  * @adapter: board private structure
2433  **/
2434 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2435                                     bool flush)
2436 {
2437         u32 mask;
2438
2439         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2440         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2441                 mask |= IXGBE_EIMS_GPI_SDP0;
2442         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2443                 mask |= IXGBE_EIMS_GPI_SDP1;
2444         switch (adapter->hw.mac.type) {
2445         case ixgbe_mac_82599EB:
2446         case ixgbe_mac_X540:
2447                 mask |= IXGBE_EIMS_ECC;
2448                 mask |= IXGBE_EIMS_GPI_SDP1;
2449                 mask |= IXGBE_EIMS_GPI_SDP2;
2450                 if (adapter->num_vfs)
2451                         mask |= IXGBE_EIMS_MAILBOX;
2452                 break;
2453         default:
2454                 break;
2455         }
2456         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2457             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2458                 mask |= IXGBE_EIMS_FLOW_DIR;
2459
2460         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2461         if (queues)
2462                 ixgbe_irq_enable_queues(adapter, ~0);
2463         if (flush)
2464                 IXGBE_WRITE_FLUSH(&adapter->hw);
2465
2466         if (adapter->num_vfs > 32) {
2467                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2468                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2469         }
2470 }
2471
2472 /**
2473  * ixgbe_intr - legacy mode Interrupt Handler
2474  * @irq: interrupt number
2475  * @data: pointer to a network interface device structure
2476  **/
2477 static irqreturn_t ixgbe_intr(int irq, void *data)
2478 {
2479         struct net_device *netdev = data;
2480         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2481         struct ixgbe_hw *hw = &adapter->hw;
2482         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2483         u32 eicr;
2484
2485         /*
2486          * Workaround for silicon errata on 82598.  Mask the interrupts
2487          * before the read of EICR.
2488          */
2489         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2490
2491         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2492          * therefore no explict interrupt disable is necessary */
2493         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2494         if (!eicr) {
2495                 /*
2496                  * shared interrupt alert!
2497                  * make sure interrupts are enabled because the read will
2498                  * have disabled interrupts due to EIAM
2499                  * finish the workaround of silicon errata on 82598.  Unmask
2500                  * the interrupt that we masked before the EICR read.
2501                  */
2502                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2503                         ixgbe_irq_enable(adapter, true, true);
2504                 return IRQ_NONE;        /* Not our interrupt */
2505         }
2506
2507         if (eicr & IXGBE_EICR_LSC)
2508                 ixgbe_check_lsc(adapter);
2509
2510         switch (hw->mac.type) {
2511         case ixgbe_mac_82599EB:
2512                 ixgbe_check_sfp_event(adapter, eicr);
2513                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2514                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2515                         adapter->interrupt_event = eicr;
2516                         schedule_work(&adapter->check_overtemp_task);
2517                 }
2518                 break;
2519         default:
2520                 break;
2521         }
2522
2523         ixgbe_check_fan_failure(adapter, eicr);
2524
2525         if (napi_schedule_prep(&(q_vector->napi))) {
2526                 adapter->tx_ring[0]->total_packets = 0;
2527                 adapter->tx_ring[0]->total_bytes = 0;
2528                 adapter->rx_ring[0]->total_packets = 0;
2529                 adapter->rx_ring[0]->total_bytes = 0;
2530                 /* would disable interrupts here but EIAM disabled it */
2531                 __napi_schedule(&(q_vector->napi));
2532         }
2533
2534         /*
2535          * re-enable link(maybe) and non-queue interrupts, no flush.
2536          * ixgbe_poll will re-enable the queue interrupts
2537          */
2538
2539         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2540                 ixgbe_irq_enable(adapter, false, false);
2541
2542         return IRQ_HANDLED;
2543 }
2544
2545 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2546 {
2547         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2548
2549         for (i = 0; i < q_vectors; i++) {
2550                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2551                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2552                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2553                 q_vector->rxr_count = 0;
2554                 q_vector->txr_count = 0;
2555         }
2556 }
2557
2558 /**
2559  * ixgbe_request_irq - initialize interrupts
2560  * @adapter: board private structure
2561  *
2562  * Attempts to configure interrupts using the best available
2563  * capabilities of the hardware and kernel.
2564  **/
2565 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2566 {
2567         struct net_device *netdev = adapter->netdev;
2568         int err;
2569
2570         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2571                 err = ixgbe_request_msix_irqs(adapter);
2572         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2573                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2574                                   netdev->name, netdev);
2575         } else {
2576                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2577                                   netdev->name, netdev);
2578         }
2579
2580         if (err)
2581                 e_err(probe, "request_irq failed, Error %d\n", err);
2582
2583         return err;
2584 }
2585
2586 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2587 {
2588         struct net_device *netdev = adapter->netdev;
2589
2590         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2591                 int i, q_vectors;
2592
2593                 q_vectors = adapter->num_msix_vectors;
2594
2595                 i = q_vectors - 1;
2596                 free_irq(adapter->msix_entries[i].vector, netdev);
2597
2598                 i--;
2599                 for (; i >= 0; i--) {
2600                         /* free only the irqs that were actually requested */
2601                         if (!adapter->q_vector[i]->rxr_count &&
2602                             !adapter->q_vector[i]->txr_count)
2603                                 continue;
2604
2605                         free_irq(adapter->msix_entries[i].vector,
2606                                  adapter->q_vector[i]);
2607                 }
2608
2609                 ixgbe_reset_q_vectors(adapter);
2610         } else {
2611                 free_irq(adapter->pdev->irq, netdev);
2612         }
2613 }
2614
2615 /**
2616  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2617  * @adapter: board private structure
2618  **/
2619 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2620 {
2621         switch (adapter->hw.mac.type) {
2622         case ixgbe_mac_82598EB:
2623                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2624                 break;
2625         case ixgbe_mac_82599EB:
2626         case ixgbe_mac_X540:
2627                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2628                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2629                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2630                 if (adapter->num_vfs > 32)
2631                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2632                 break;
2633         default:
2634                 break;
2635         }
2636         IXGBE_WRITE_FLUSH(&adapter->hw);
2637         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2638                 int i;
2639                 for (i = 0; i < adapter->num_msix_vectors; i++)
2640                         synchronize_irq(adapter->msix_entries[i].vector);
2641         } else {
2642                 synchronize_irq(adapter->pdev->irq);
2643         }
2644 }
2645
2646 /**
2647  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2648  *
2649  **/
2650 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2651 {
2652         struct ixgbe_hw *hw = &adapter->hw;
2653
2654         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2655                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2656
2657         ixgbe_set_ivar(adapter, 0, 0, 0);
2658         ixgbe_set_ivar(adapter, 1, 0, 0);
2659
2660         map_vector_to_rxq(adapter, 0, 0);
2661         map_vector_to_txq(adapter, 0, 0);
2662
2663         e_info(hw, "Legacy interrupt IVAR setup done\n");
2664 }
2665
2666 /**
2667  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2668  * @adapter: board private structure
2669  * @ring: structure containing ring specific data
2670  *
2671  * Configure the Tx descriptor ring after a reset.
2672  **/
2673 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2674                              struct ixgbe_ring *ring)
2675 {
2676         struct ixgbe_hw *hw = &adapter->hw;
2677         u64 tdba = ring->dma;
2678         int wait_loop = 10;
2679         u32 txdctl;
2680         u8 reg_idx = ring->reg_idx;
2681
2682         /* disable queue to avoid issues while updating state */
2683         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2684         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2685                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2686         IXGBE_WRITE_FLUSH(hw);
2687
2688         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2689                         (tdba & DMA_BIT_MASK(32)));
2690         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2691         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2692                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2693         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2694         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2695         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2696
2697         /* configure fetching thresholds */
2698         if (adapter->rx_itr_setting == 0) {
2699                 /* cannot set wthresh when itr==0 */
2700                 txdctl &= ~0x007F0000;
2701         } else {
2702                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2703                 txdctl |= (8 << 16);
2704         }
2705         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2706                 /* PThresh workaround for Tx hang with DFP enabled. */
2707                 txdctl |= 32;
2708         }
2709
2710         /* reinitialize flowdirector state */
2711         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2712             adapter->atr_sample_rate) {
2713                 ring->atr_sample_rate = adapter->atr_sample_rate;
2714                 ring->atr_count = 0;
2715                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2716         } else {
2717                 ring->atr_sample_rate = 0;
2718         }
2719
2720         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2721
2722         /* enable queue */
2723         txdctl |= IXGBE_TXDCTL_ENABLE;
2724         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2725
2726         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2727         if (hw->mac.type == ixgbe_mac_82598EB &&
2728             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2729                 return;
2730
2731         /* poll to verify queue is enabled */
2732         do {
2733                 msleep(1);
2734                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2735         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2736         if (!wait_loop)
2737                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2738 }
2739
2740 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2741 {
2742         struct ixgbe_hw *hw = &adapter->hw;
2743         u32 rttdcs;
2744         u32 mask;
2745
2746         if (hw->mac.type == ixgbe_mac_82598EB)
2747                 return;
2748
2749         /* disable the arbiter while setting MTQC */
2750         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2751         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2752         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2753
2754         /* set transmit pool layout */
2755         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2756         switch (adapter->flags & mask) {
2757
2758         case (IXGBE_FLAG_SRIOV_ENABLED):
2759                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2760                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2761                 break;
2762
2763         case (IXGBE_FLAG_DCB_ENABLED):
2764                 /* We enable 8 traffic classes, DCB only */
2765                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2766                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2767                 break;
2768
2769         default:
2770                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2771                 break;
2772         }
2773
2774         /* re-enable the arbiter */
2775         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2776         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2777 }
2778
2779 /**
2780  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2781  * @adapter: board private structure
2782  *
2783  * Configure the Tx unit of the MAC after a reset.
2784  **/
2785 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2786 {
2787         struct ixgbe_hw *hw = &adapter->hw;
2788         u32 dmatxctl;
2789         u32 i;
2790
2791         ixgbe_setup_mtqc(adapter);
2792
2793         if (hw->mac.type != ixgbe_mac_82598EB) {
2794                 /* DMATXCTL.EN must be before Tx queues are enabled */
2795                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2796                 dmatxctl |= IXGBE_DMATXCTL_TE;
2797                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2798         }
2799
2800         /* Setup the HW Tx Head and Tail descriptor pointers */
2801         for (i = 0; i < adapter->num_tx_queues; i++)
2802                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2803 }
2804
2805 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2806
2807 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2808                                    struct ixgbe_ring *rx_ring)
2809 {
2810         u32 srrctl;
2811         u8 reg_idx = rx_ring->reg_idx;
2812
2813         switch (adapter->hw.mac.type) {
2814         case ixgbe_mac_82598EB: {
2815                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2816                 const int mask = feature[RING_F_RSS].mask;
2817                 reg_idx = reg_idx & mask;
2818         }
2819                 break;
2820         case ixgbe_mac_82599EB:
2821         case ixgbe_mac_X540:
2822         default:
2823                 break;
2824         }
2825
2826         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2827
2828         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2829         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2830         if (adapter->num_vfs)
2831                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2832
2833         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2834                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2835
2836         if (ring_is_ps_enabled(rx_ring)) {
2837 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2838                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2839 #else
2840                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2841 #endif
2842                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2843         } else {
2844                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2845                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2846                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2847         }
2848
2849         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2850 }
2851
2852 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2853 {
2854         struct ixgbe_hw *hw = &adapter->hw;
2855         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2856                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2857                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2858         u32 mrqc = 0, reta = 0;
2859         u32 rxcsum;
2860         int i, j;
2861         int mask;
2862
2863         /* Fill out hash function seeds */
2864         for (i = 0; i < 10; i++)
2865                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2866
2867         /* Fill out redirection table */
2868         for (i = 0, j = 0; i < 128; i++, j++) {
2869                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2870                         j = 0;
2871                 /* reta = 4-byte sliding window of
2872                  * 0x00..(indices-1)(indices-1)00..etc. */
2873                 reta = (reta << 8) | (j * 0x11);
2874                 if ((i & 3) == 3)
2875                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2876         }
2877
2878         /* Disable indicating checksum in descriptor, enables RSS hash */
2879         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2880         rxcsum |= IXGBE_RXCSUM_PCSD;
2881         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2882
2883         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2884                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2885         else
2886                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2887 #ifdef CONFIG_IXGBE_DCB
2888                                          | IXGBE_FLAG_DCB_ENABLED
2889 #endif
2890                                          | IXGBE_FLAG_SRIOV_ENABLED
2891                                         );
2892
2893         switch (mask) {
2894         case (IXGBE_FLAG_RSS_ENABLED):
2895                 mrqc = IXGBE_MRQC_RSSEN;
2896                 break;
2897         case (IXGBE_FLAG_SRIOV_ENABLED):
2898                 mrqc = IXGBE_MRQC_VMDQEN;
2899                 break;
2900 #ifdef CONFIG_IXGBE_DCB
2901         case (IXGBE_FLAG_DCB_ENABLED):
2902                 mrqc = IXGBE_MRQC_RT8TCEN;
2903                 break;
2904 #endif /* CONFIG_IXGBE_DCB */
2905         default:
2906                 break;
2907         }
2908
2909         /* Perform hash on these packet types */
2910         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2911               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2912               | IXGBE_MRQC_RSS_FIELD_IPV6
2913               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2914
2915         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2916 }
2917
2918 /**
2919  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2920  * @adapter: address of board private structure
2921  * @ring: structure containing ring specific data
2922  **/
2923 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2924                         struct ixgbe_ring *ring)
2925 {
2926         struct ixgbe_hw *hw = &adapter->hw;
2927         u32 rscctrl;
2928         u8 reg_idx = ring->reg_idx;
2929
2930         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2931         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2932         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2933 }
2934
2935 /**
2936  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2937  * @adapter:    address of board private structure
2938  * @index:      index of ring to set
2939  **/
2940 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2941                                    struct ixgbe_ring *ring)
2942 {
2943         struct ixgbe_hw *hw = &adapter->hw;
2944         u32 rscctrl;
2945         int rx_buf_len;
2946         u8 reg_idx = ring->reg_idx;
2947
2948         if (!ring_is_rsc_enabled(ring))
2949                 return;
2950
2951         rx_buf_len = ring->rx_buf_len;
2952         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2953         rscctrl |= IXGBE_RSCCTL_RSCEN;
2954         /*
2955          * we must limit the number of descriptors so that the
2956          * total size of max desc * buf_len is not greater
2957          * than 65535
2958          */
2959         if (ring_is_ps_enabled(ring)) {
2960 #if (MAX_SKB_FRAGS > 16)
2961                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2962 #elif (MAX_SKB_FRAGS > 8)
2963                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2964 #elif (MAX_SKB_FRAGS > 4)
2965                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2966 #else
2967                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2968 #endif
2969         } else {
2970                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2971                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2972                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2973                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2974                 else
2975                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2976         }
2977         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2978 }
2979
2980 /**
2981  *  ixgbe_set_uta - Set unicast filter table address
2982  *  @adapter: board private structure
2983  *
2984  *  The unicast table address is a register array of 32-bit registers.
2985  *  The table is meant to be used in a way similar to how the MTA is used
2986  *  however due to certain limitations in the hardware it is necessary to
2987  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2988  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2989  **/
2990 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2991 {
2992         struct ixgbe_hw *hw = &adapter->hw;
2993         int i;
2994
2995         /* The UTA table only exists on 82599 hardware and newer */
2996         if (hw->mac.type < ixgbe_mac_82599EB)
2997                 return;
2998
2999         /* we only need to do this if VMDq is enabled */
3000         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3001                 return;
3002
3003         for (i = 0; i < 128; i++)
3004                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3005 }
3006
3007 #define IXGBE_MAX_RX_DESC_POLL 10
3008 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3009                                        struct ixgbe_ring *ring)
3010 {
3011         struct ixgbe_hw *hw = &adapter->hw;
3012         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3013         u32 rxdctl;
3014         u8 reg_idx = ring->reg_idx;
3015
3016         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3017         if (hw->mac.type == ixgbe_mac_82598EB &&
3018             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3019                 return;
3020
3021         do {
3022                 msleep(1);
3023                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3024         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3025
3026         if (!wait_loop) {
3027                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3028                       "the polling period\n", reg_idx);
3029         }
3030 }
3031
3032 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3033                             struct ixgbe_ring *ring)
3034 {
3035         struct ixgbe_hw *hw = &adapter->hw;
3036         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3037         u32 rxdctl;
3038         u8 reg_idx = ring->reg_idx;
3039
3040         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3041         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3042
3043         /* write value back with RXDCTL.ENABLE bit cleared */
3044         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3045
3046         if (hw->mac.type == ixgbe_mac_82598EB &&
3047             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3048                 return;
3049
3050         /* the hardware may take up to 100us to really disable the rx queue */
3051         do {
3052                 udelay(10);
3053                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3054         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3055
3056         if (!wait_loop) {
3057                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3058                       "the polling period\n", reg_idx);
3059         }
3060 }
3061
3062 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3063                              struct ixgbe_ring *ring)
3064 {
3065         struct ixgbe_hw *hw = &adapter->hw;
3066         u64 rdba = ring->dma;
3067         u32 rxdctl;
3068         u8 reg_idx = ring->reg_idx;
3069
3070         /* disable queue to avoid issues while updating state */
3071         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3072         ixgbe_disable_rx_queue(adapter, ring);
3073
3074         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3075         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3076         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3077                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3078         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3079         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3080         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3081
3082         ixgbe_configure_srrctl(adapter, ring);
3083         ixgbe_configure_rscctl(adapter, ring);
3084
3085         /* If operating in IOV mode set RLPML for X540 */
3086         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3087             hw->mac.type == ixgbe_mac_X540) {
3088                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3089                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3090                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3091         }
3092
3093         if (hw->mac.type == ixgbe_mac_82598EB) {
3094                 /*
3095                  * enable cache line friendly hardware writes:
3096                  * PTHRESH=32 descriptors (half the internal cache),
3097                  * this also removes ugly rx_no_buffer_count increment
3098                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3099                  * WTHRESH=8 burst writeback up to two cache lines
3100                  */
3101                 rxdctl &= ~0x3FFFFF;
3102                 rxdctl |=  0x080420;
3103         }
3104
3105         /* enable receive descriptor ring */
3106         rxdctl |= IXGBE_RXDCTL_ENABLE;
3107         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3108
3109         ixgbe_rx_desc_queue_enable(adapter, ring);
3110         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3111 }
3112
3113 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3114 {
3115         struct ixgbe_hw *hw = &adapter->hw;
3116         int p;
3117
3118         /* PSRTYPE must be initialized in non 82598 adapters */
3119         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3120                       IXGBE_PSRTYPE_UDPHDR |
3121                       IXGBE_PSRTYPE_IPV4HDR |
3122                       IXGBE_PSRTYPE_L2HDR |
3123                       IXGBE_PSRTYPE_IPV6HDR;
3124
3125         if (hw->mac.type == ixgbe_mac_82598EB)
3126                 return;
3127
3128         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3129                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3130
3131         for (p = 0; p < adapter->num_rx_pools; p++)
3132                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3133                                 psrtype);
3134 }
3135
3136 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3137 {
3138         struct ixgbe_hw *hw = &adapter->hw;
3139         u32 gcr_ext;
3140         u32 vt_reg_bits;
3141         u32 reg_offset, vf_shift;
3142         u32 vmdctl;
3143
3144         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3145                 return;
3146
3147         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3148         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3149         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3150         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3151
3152         vf_shift = adapter->num_vfs % 32;
3153         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3154
3155         /* Enable only the PF's pool for Tx/Rx */
3156         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3157         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3158         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3159         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3160         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3161
3162         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3163         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3164
3165         /*
3166          * Set up VF register offsets for selected VT Mode,
3167          * i.e. 32 or 64 VFs for SR-IOV
3168          */
3169         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3170         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3171         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3172         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3173
3174         /* enable Tx loopback for VF/PF communication */
3175         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3176         /* Enable MAC Anti-Spoofing */
3177         hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3178                                           adapter->num_vfs);
3179 }
3180
3181 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3182 {
3183         struct ixgbe_hw *hw = &adapter->hw;
3184         struct net_device *netdev = adapter->netdev;
3185         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3186         int rx_buf_len;
3187         struct ixgbe_ring *rx_ring;
3188         int i;
3189         u32 mhadd, hlreg0;
3190
3191         /* Decide whether to use packet split mode or not */
3192         /* On by default */
3193         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3194
3195         /* Do not use packet split if we're in SR-IOV Mode */
3196         if (adapter->num_vfs)
3197                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3198
3199         /* Disable packet split due to 82599 erratum #45 */
3200         if (hw->mac.type == ixgbe_mac_82599EB)
3201                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3202
3203         /* Set the RX buffer length according to the mode */
3204         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3205                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3206         } else {
3207                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3208                     (netdev->mtu <= ETH_DATA_LEN))
3209                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3210                 else
3211                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3212         }
3213
3214 #ifdef IXGBE_FCOE
3215         /* adjust max frame to be able to do baby jumbo for FCoE */
3216         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3217             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3218                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3219
3220 #endif /* IXGBE_FCOE */
3221         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3222         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3223                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3224                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3225
3226                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3227         }
3228
3229         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3230         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3231         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3232         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3233
3234         /*
3235          * Setup the HW Rx Head and Tail Descriptor Pointers and
3236          * the Base and Length of the Rx Descriptor Ring
3237          */
3238         for (i = 0; i < adapter->num_rx_queues; i++) {
3239                 rx_ring = adapter->rx_ring[i];
3240                 rx_ring->rx_buf_len = rx_buf_len;
3241
3242                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3243                         set_ring_ps_enabled(rx_ring);
3244                 else
3245                         clear_ring_ps_enabled(rx_ring);
3246
3247                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3248                         set_ring_rsc_enabled(rx_ring);
3249                 else
3250                         clear_ring_rsc_enabled(rx_ring);
3251
3252 #ifdef IXGBE_FCOE
3253                 if (netdev->features & NETIF_F_FCOE_MTU) {
3254                         struct ixgbe_ring_feature *f;
3255                         f = &adapter->ring_feature[RING_F_FCOE];
3256                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3257                                 clear_ring_ps_enabled(rx_ring);
3258                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3259                                         rx_ring->rx_buf_len =
3260                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3261                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3262                                    !ring_is_ps_enabled(rx_ring)) {
3263                                 rx_ring->rx_buf_len =
3264                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3265                         }
3266                 }
3267 #endif /* IXGBE_FCOE */
3268         }
3269 }
3270
3271 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3272 {
3273         struct ixgbe_hw *hw = &adapter->hw;
3274         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3275
3276         switch (hw->mac.type) {
3277         case ixgbe_mac_82598EB:
3278                 /*
3279                  * For VMDq support of different descriptor types or
3280                  * buffer sizes through the use of multiple SRRCTL
3281                  * registers, RDRXCTL.MVMEN must be set to 1
3282                  *
3283                  * also, the manual doesn't mention it clearly but DCA hints
3284                  * will only use queue 0's tags unless this bit is set.  Side
3285                  * effects of setting this bit are only that SRRCTL must be
3286                  * fully programmed [0..15]
3287                  */
3288                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3289                 break;
3290         case ixgbe_mac_82599EB:
3291         case ixgbe_mac_X540:
3292                 /* Disable RSC for ACK packets */
3293                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3294                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3295                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3296                 /* hardware requires some bits to be set by default */
3297                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3298                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3299                 break;
3300         default:
3301                 /* We should do nothing since we don't know this hardware */
3302                 return;
3303         }
3304
3305         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3306 }
3307
3308 /**
3309  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3310  * @adapter: board private structure
3311  *
3312  * Configure the Rx unit of the MAC after a reset.
3313  **/
3314 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3315 {
3316         struct ixgbe_hw *hw = &adapter->hw;
3317         int i;
3318         u32 rxctrl;
3319
3320         /* disable receives while setting up the descriptors */
3321         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3322         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3323
3324         ixgbe_setup_psrtype(adapter);
3325         ixgbe_setup_rdrxctl(adapter);
3326
3327         /* Program registers for the distribution of queues */
3328         ixgbe_setup_mrqc(adapter);
3329
3330         ixgbe_set_uta(adapter);
3331
3332         /* set_rx_buffer_len must be called before ring initialization */
3333         ixgbe_set_rx_buffer_len(adapter);
3334
3335         /*
3336          * Setup the HW Rx Head and Tail Descriptor Pointers and
3337          * the Base and Length of the Rx Descriptor Ring
3338          */
3339         for (i = 0; i < adapter->num_rx_queues; i++)
3340                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3341
3342         /* disable drop enable for 82598 parts */
3343         if (hw->mac.type == ixgbe_mac_82598EB)
3344                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3345
3346         /* enable all receives */
3347         rxctrl |= IXGBE_RXCTRL_RXEN;
3348         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3349 }
3350
3351 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3352 {
3353         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3354         struct ixgbe_hw *hw = &adapter->hw;
3355         int pool_ndx = adapter->num_vfs;
3356
3357         /* add VID to filter table */
3358         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3359         set_bit(vid, adapter->active_vlans);
3360 }
3361
3362 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3363 {
3364         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3365         struct ixgbe_hw *hw = &adapter->hw;
3366         int pool_ndx = adapter->num_vfs;
3367
3368         /* remove VID from filter table */
3369         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3370         clear_bit(vid, adapter->active_vlans);
3371 }
3372
3373 /**
3374  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3375  * @adapter: driver data
3376  */
3377 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3378 {
3379         struct ixgbe_hw *hw = &adapter->hw;
3380         u32 vlnctrl;
3381
3382         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3383         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3384         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3385 }
3386
3387 /**
3388  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3389  * @adapter: driver data
3390  */
3391 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3392 {
3393         struct ixgbe_hw *hw = &adapter->hw;
3394         u32 vlnctrl;
3395
3396         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3397         vlnctrl |= IXGBE_VLNCTRL_VFE;
3398         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3399         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3400 }
3401
3402 /**
3403  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3404  * @adapter: driver data
3405  */
3406 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3407 {
3408         struct ixgbe_hw *hw = &adapter->hw;
3409         u32 vlnctrl;
3410         int i, j;
3411
3412         switch (hw->mac.type) {
3413         case ixgbe_mac_82598EB:
3414                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3415                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3416                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3417                 break;
3418         case ixgbe_mac_82599EB:
3419         case ixgbe_mac_X540:
3420                 for (i = 0; i < adapter->num_rx_queues; i++) {
3421                         j = adapter->rx_ring[i]->reg_idx;
3422                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3423                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3424                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3425                 }
3426                 break;
3427         default:
3428                 break;
3429         }
3430 }
3431
3432 /**
3433  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3434  * @adapter: driver data
3435  */
3436 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3437 {
3438         struct ixgbe_hw *hw = &adapter->hw;
3439         u32 vlnctrl;
3440         int i, j;
3441
3442         switch (hw->mac.type) {
3443         case ixgbe_mac_82598EB:
3444                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3445                 vlnctrl |= IXGBE_VLNCTRL_VME;
3446                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3447                 break;
3448         case ixgbe_mac_82599EB:
3449         case ixgbe_mac_X540:
3450                 for (i = 0; i < adapter->num_rx_queues; i++) {
3451                         j = adapter->rx_ring[i]->reg_idx;
3452                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3453                         vlnctrl |= IXGBE_RXDCTL_VME;
3454                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3455                 }
3456                 break;
3457         default:
3458                 break;
3459         }
3460 }
3461
3462 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3463 {
3464         u16 vid;
3465
3466         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3467
3468         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3469                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3470 }
3471
3472 /**
3473  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3474  * @netdev: network interface device structure
3475  *
3476  * Writes unicast address list to the RAR table.
3477  * Returns: -ENOMEM on failure/insufficient address space
3478  *                0 on no addresses written
3479  *                X on writing X addresses to the RAR table
3480  **/
3481 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3482 {
3483         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3484         struct ixgbe_hw *hw = &adapter->hw;
3485         unsigned int vfn = adapter->num_vfs;
3486         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3487         int count = 0;
3488
3489         /* return ENOMEM indicating insufficient memory for addresses */
3490         if (netdev_uc_count(netdev) > rar_entries)
3491                 return -ENOMEM;
3492
3493         if (!netdev_uc_empty(netdev) && rar_entries) {
3494                 struct netdev_hw_addr *ha;
3495                 /* return error if we do not support writing to RAR table */
3496                 if (!hw->mac.ops.set_rar)
3497                         return -ENOMEM;
3498
3499                 netdev_for_each_uc_addr(ha, netdev) {
3500                         if (!rar_entries)
3501                                 break;
3502                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3503                                             vfn, IXGBE_RAH_AV);
3504                         count++;
3505                 }
3506         }
3507         /* write the addresses in reverse order to avoid write combining */
3508         for (; rar_entries > 0 ; rar_entries--)
3509                 hw->mac.ops.clear_rar(hw, rar_entries);
3510
3511         return count;
3512 }
3513
3514 /**
3515  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3516  * @netdev: network interface device structure
3517  *
3518  * The set_rx_method entry point is called whenever the unicast/multicast
3519  * address list or the network interface flags are updated.  This routine is
3520  * responsible for configuring the hardware for proper unicast, multicast and
3521  * promiscuous mode.
3522  **/
3523 void ixgbe_set_rx_mode(struct net_device *netdev)
3524 {
3525         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3526         struct ixgbe_hw *hw = &adapter->hw;
3527         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3528         int count;
3529
3530         /* Check for Promiscuous and All Multicast modes */
3531
3532         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3533
3534         /* set all bits that we expect to always be set */
3535         fctrl |= IXGBE_FCTRL_BAM;
3536         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3537         fctrl |= IXGBE_FCTRL_PMCF;
3538
3539         /* clear the bits we are changing the status of */
3540         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3541
3542         if (netdev->flags & IFF_PROMISC) {
3543                 hw->addr_ctrl.user_set_promisc = true;
3544                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3545                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3546                 /* don't hardware filter vlans in promisc mode */
3547                 ixgbe_vlan_filter_disable(adapter);
3548         } else {
3549                 if (netdev->flags & IFF_ALLMULTI) {
3550                         fctrl |= IXGBE_FCTRL_MPE;
3551                         vmolr |= IXGBE_VMOLR_MPE;
3552                 } else {
3553                         /*
3554                          * Write addresses to the MTA, if the attempt fails
3555                          * then we should just turn on promiscous mode so
3556                          * that we can at least receive multicast traffic
3557                          */
3558                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3559                         vmolr |= IXGBE_VMOLR_ROMPE;
3560                 }
3561                 ixgbe_vlan_filter_enable(adapter);
3562                 hw->addr_ctrl.user_set_promisc = false;
3563                 /*
3564                  * Write addresses to available RAR registers, if there is not
3565                  * sufficient space to store all the addresses then enable
3566                  * unicast promiscous mode
3567                  */
3568                 count = ixgbe_write_uc_addr_list(netdev);
3569                 if (count < 0) {
3570                         fctrl |= IXGBE_FCTRL_UPE;
3571                         vmolr |= IXGBE_VMOLR_ROPE;
3572                 }
3573         }
3574
3575         if (adapter->num_vfs) {
3576                 ixgbe_restore_vf_multicasts(adapter);
3577                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3578                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3579                            IXGBE_VMOLR_ROPE);
3580                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3581         }
3582
3583         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3584
3585         if (netdev->features & NETIF_F_HW_VLAN_RX)
3586                 ixgbe_vlan_strip_enable(adapter);
3587         else
3588                 ixgbe_vlan_strip_disable(adapter);
3589 }
3590
3591 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3592 {
3593         int q_idx;
3594         struct ixgbe_q_vector *q_vector;
3595         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3596
3597         /* legacy and MSI only use one vector */
3598         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3599                 q_vectors = 1;
3600
3601         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3602                 struct napi_struct *napi;
3603                 q_vector = adapter->q_vector[q_idx];
3604                 napi = &q_vector->napi;
3605                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3606                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3607                                 if (q_vector->txr_count == 1)
3608                                         napi->poll = &ixgbe_clean_txonly;
3609                                 else if (q_vector->rxr_count == 1)
3610                                         napi->poll = &ixgbe_clean_rxonly;
3611                         }
3612                 }
3613
3614                 napi_enable(napi);
3615         }
3616 }
3617
3618 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3619 {
3620         int q_idx;
3621         struct ixgbe_q_vector *q_vector;
3622         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3623
3624         /* legacy and MSI only use one vector */
3625         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3626                 q_vectors = 1;
3627
3628         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3629                 q_vector = adapter->q_vector[q_idx];
3630                 napi_disable(&q_vector->napi);
3631         }
3632 }
3633
3634 #ifdef CONFIG_IXGBE_DCB
3635 /*
3636  * ixgbe_configure_dcb - Configure DCB hardware
3637  * @adapter: ixgbe adapter struct
3638  *
3639  * This is called by the driver on open to configure the DCB hardware.
3640  * This is also called by the gennetlink interface when reconfiguring
3641  * the DCB state.
3642  */
3643 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3644 {
3645         struct ixgbe_hw *hw = &adapter->hw;
3646         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3647
3648         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3649                 if (hw->mac.type == ixgbe_mac_82598EB)
3650                         netif_set_gso_max_size(adapter->netdev, 65536);
3651                 return;
3652         }
3653
3654         if (hw->mac.type == ixgbe_mac_82598EB)
3655                 netif_set_gso_max_size(adapter->netdev, 32768);
3656
3657 #ifdef CONFIG_FCOE
3658         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3659                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3660 #endif
3661
3662         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3663                                         DCB_TX_CONFIG);
3664         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3665                                         DCB_RX_CONFIG);
3666
3667         /* Enable VLAN tag insert/strip */
3668         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3669
3670         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3671
3672         /* reconfigure the hardware */
3673         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3674 }
3675
3676 #endif
3677 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3678 {
3679         struct net_device *netdev = adapter->netdev;
3680         struct ixgbe_hw *hw = &adapter->hw;
3681         int i;
3682
3683 #ifdef CONFIG_IXGBE_DCB
3684         ixgbe_configure_dcb(adapter);
3685 #endif
3686
3687         ixgbe_set_rx_mode(netdev);
3688         ixgbe_restore_vlan(adapter);
3689
3690 #ifdef IXGBE_FCOE
3691         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3692                 ixgbe_configure_fcoe(adapter);
3693
3694 #endif /* IXGBE_FCOE */
3695         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3696                 for (i = 0; i < adapter->num_tx_queues; i++)
3697                         adapter->tx_ring[i]->atr_sample_rate =
3698                                                        adapter->atr_sample_rate;
3699                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3700         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3701                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3702         }
3703         ixgbe_configure_virtualization(adapter);
3704
3705         ixgbe_configure_tx(adapter);
3706         ixgbe_configure_rx(adapter);
3707 }
3708
3709 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3710 {
3711         switch (hw->phy.type) {
3712         case ixgbe_phy_sfp_avago:
3713         case ixgbe_phy_sfp_ftl:
3714         case ixgbe_phy_sfp_intel:
3715         case ixgbe_phy_sfp_unknown:
3716         case ixgbe_phy_sfp_passive_tyco:
3717         case ixgbe_phy_sfp_passive_unknown:
3718         case ixgbe_phy_sfp_active_unknown:
3719         case ixgbe_phy_sfp_ftl_active:
3720                 return true;
3721         default:
3722                 return false;
3723         }
3724 }
3725
3726 /**
3727  * ixgbe_sfp_link_config - set up SFP+ link
3728  * @adapter: pointer to private adapter struct
3729  **/
3730 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3731 {
3732         struct ixgbe_hw *hw = &adapter->hw;
3733
3734                 if (hw->phy.multispeed_fiber) {
3735                         /*
3736                          * In multispeed fiber setups, the device may not have
3737                          * had a physical connection when the driver loaded.
3738                          * If that's the case, the initial link configuration
3739                          * couldn't get the MAC into 10G or 1G mode, so we'll
3740                          * never have a link status change interrupt fire.
3741                          * We need to try and force an autonegotiation
3742                          * session, then bring up link.
3743                          */
3744                         if (hw->mac.ops.setup_sfp)
3745                                 hw->mac.ops.setup_sfp(hw);
3746                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3747                                 schedule_work(&adapter->multispeed_fiber_task);
3748                 } else {
3749                         /*
3750                          * Direct Attach Cu and non-multispeed fiber modules
3751                          * still need to be configured properly prior to
3752                          * attempting link.
3753                          */
3754                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3755                                 schedule_work(&adapter->sfp_config_module_task);
3756                 }
3757 }
3758
3759 /**
3760  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3761  * @hw: pointer to private hardware struct
3762  *
3763  * Returns 0 on success, negative on failure
3764  **/
3765 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3766 {
3767         u32 autoneg;
3768         bool negotiation, link_up = false;
3769         u32 ret = IXGBE_ERR_LINK_SETUP;
3770
3771         if (hw->mac.ops.check_link)
3772                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3773
3774         if (ret)
3775                 goto link_cfg_out;
3776
3777         if (hw->mac.ops.get_link_capabilities)
3778                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3779                                                         &negotiation);
3780         if (ret)
3781                 goto link_cfg_out;
3782
3783         if (hw->mac.ops.setup_link)
3784                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3785 link_cfg_out:
3786         return ret;
3787 }
3788
3789 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3790 {
3791         struct ixgbe_hw *hw = &adapter->hw;
3792         u32 gpie = 0;
3793
3794         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3795                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3796                        IXGBE_GPIE_OCD;
3797                 gpie |= IXGBE_GPIE_EIAME;
3798                 /*
3799                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3800                  * this saves a register write for every interrupt
3801                  */
3802                 switch (hw->mac.type) {
3803                 case ixgbe_mac_82598EB:
3804                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3805                         break;
3806                 case ixgbe_mac_82599EB:
3807                 case ixgbe_mac_X540:
3808                 default:
3809                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3810                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3811                         break;
3812                 }
3813         } else {
3814                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3815                  * specifically only auto mask tx and rx interrupts */
3816                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3817         }
3818
3819         /* XXX: to interrupt immediately for EICS writes, enable this */
3820         /* gpie |= IXGBE_GPIE_EIMEN; */
3821
3822         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3823                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3824                 gpie |= IXGBE_GPIE_VTMODE_64;
3825         }
3826
3827         /* Enable fan failure interrupt */
3828         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3829                 gpie |= IXGBE_SDP1_GPIEN;
3830
3831         if (hw->mac.type == ixgbe_mac_82599EB)
3832                 gpie |= IXGBE_SDP1_GPIEN;
3833                 gpie |= IXGBE_SDP2_GPIEN;
3834
3835         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3836 }
3837
3838 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3839 {
3840         struct ixgbe_hw *hw = &adapter->hw;
3841         int err;
3842         u32 ctrl_ext;
3843
3844         ixgbe_get_hw_control(adapter);
3845         ixgbe_setup_gpie(adapter);
3846
3847         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3848                 ixgbe_configure_msix(adapter);
3849         else
3850                 ixgbe_configure_msi_and_legacy(adapter);
3851
3852         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3853         if (hw->mac.ops.enable_tx_laser &&
3854             ((hw->phy.multispeed_fiber) ||
3855              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3856               (hw->mac.type == ixgbe_mac_82599EB))))
3857                 hw->mac.ops.enable_tx_laser(hw);
3858
3859         clear_bit(__IXGBE_DOWN, &adapter->state);
3860         ixgbe_napi_enable_all(adapter);
3861
3862         if (ixgbe_is_sfp(hw)) {
3863                 ixgbe_sfp_link_config(adapter);
3864         } else {
3865                 err = ixgbe_non_sfp_link_config(hw);
3866                 if (err)
3867                         e_err(probe, "link_config FAILED %d\n", err);
3868         }
3869
3870         /* clear any pending interrupts, may auto mask */
3871         IXGBE_READ_REG(hw, IXGBE_EICR);
3872         ixgbe_irq_enable(adapter, true, true);
3873
3874         /*
3875          * If this adapter has a fan, check to see if we had a failure
3876          * before we enabled the interrupt.
3877          */
3878         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3879                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3880                 if (esdp & IXGBE_ESDP_SDP1)
3881                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3882         }
3883
3884         /*
3885          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3886          * arrived before interrupts were enabled but after probe.  Such
3887          * devices wouldn't have their type identified yet. We need to
3888          * kick off the SFP+ module setup first, then try to bring up link.
3889          * If we're not hot-pluggable SFP+, we just need to configure link
3890          * and bring it up.
3891          */
3892         if (hw->phy.type == ixgbe_phy_unknown)
3893                 schedule_work(&adapter->sfp_config_module_task);
3894
3895         /* enable transmits */
3896         netif_tx_start_all_queues(adapter->netdev);
3897
3898         /* bring the link up in the watchdog, this could race with our first
3899          * link up interrupt but shouldn't be a problem */
3900         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3901         adapter->link_check_timeout = jiffies;
3902         mod_timer(&adapter->watchdog_timer, jiffies);
3903
3904         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3905         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3906         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3907         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3908
3909         return 0;
3910 }
3911
3912 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3913 {
3914         WARN_ON(in_interrupt());
3915         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3916                 msleep(1);
3917         ixgbe_down(adapter);
3918         /*
3919          * If SR-IOV enabled then wait a bit before bringing the adapter
3920          * back up to give the VFs time to respond to the reset.  The
3921          * two second wait is based upon the watchdog timer cycle in
3922          * the VF driver.
3923          */
3924         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3925                 msleep(2000);
3926         ixgbe_up(adapter);
3927         clear_bit(__IXGBE_RESETTING, &adapter->state);
3928 }
3929
3930 int ixgbe_up(struct ixgbe_adapter *adapter)
3931 {
3932         /* hardware has been reset, we need to reload some things */
3933         ixgbe_configure(adapter);
3934
3935         return ixgbe_up_complete(adapter);
3936 }
3937
3938 void ixgbe_reset(struct ixgbe_adapter *adapter)
3939 {
3940         struct ixgbe_hw *hw = &adapter->hw;
3941         int err;
3942
3943         err = hw->mac.ops.init_hw(hw);
3944         switch (err) {
3945         case 0:
3946         case IXGBE_ERR_SFP_NOT_PRESENT:
3947                 break;
3948         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3949                 e_dev_err("master disable timed out\n");
3950                 break;
3951         case IXGBE_ERR_EEPROM_VERSION:
3952                 /* We are running on a pre-production device, log a warning */
3953                 e_dev_warn("This device is a pre-production adapter/LOM. "
3954                            "Please be aware there may be issuesassociated with "
3955                            "your hardware.  If you are experiencing problems "
3956                            "please contact your Intel or hardware "
3957                            "representative who provided you with this "
3958                            "hardware.\n");
3959                 break;
3960         default:
3961                 e_dev_err("Hardware Error: %d\n", err);
3962         }
3963
3964         /* reprogram the RAR[0] in case user changed it. */
3965         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3966                             IXGBE_RAH_AV);
3967 }
3968
3969 /**
3970  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3971  * @rx_ring: ring to free buffers from
3972  **/
3973 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3974 {
3975         struct device *dev = rx_ring->dev;
3976         unsigned long size;
3977         u16 i;
3978
3979         /* ring already cleared, nothing to do */
3980         if (!rx_ring->rx_buffer_info)
3981                 return;
3982
3983         /* Free all the Rx ring sk_buffs */
3984         for (i = 0; i < rx_ring->count; i++) {
3985                 struct ixgbe_rx_buffer *rx_buffer_info;
3986
3987                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3988                 if (rx_buffer_info->dma) {
3989                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3990                                          rx_ring->rx_buf_len,
3991                                          DMA_FROM_DEVICE);
3992                         rx_buffer_info->dma = 0;
3993                 }
3994                 if (rx_buffer_info->skb) {
3995                         struct sk_buff *skb = rx_buffer_info->skb;
3996                         rx_buffer_info->skb = NULL;
3997                         do {
3998                                 struct sk_buff *this = skb;
3999                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4000                                         dma_unmap_single(dev,
4001                                                          IXGBE_RSC_CB(this)->dma,
4002                                                          rx_ring->rx_buf_len,
4003                                                          DMA_FROM_DEVICE);
4004                                         IXGBE_RSC_CB(this)->dma = 0;
4005                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4006                                 }
4007                                 skb = skb->prev;
4008                                 dev_kfree_skb(this);
4009                         } while (skb);
4010                 }
4011                 if (!rx_buffer_info->page)
4012                         continue;
4013                 if (rx_buffer_info->page_dma) {
4014                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4015                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4016                         rx_buffer_info->page_dma = 0;
4017                 }
4018                 put_page(rx_buffer_info->page);
4019                 rx_buffer_info->page = NULL;
4020                 rx_buffer_info->page_offset = 0;
4021         }
4022
4023         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4024         memset(rx_ring->rx_buffer_info, 0, size);
4025
4026         /* Zero out the descriptor ring */
4027         memset(rx_ring->desc, 0, rx_ring->size);
4028
4029         rx_ring->next_to_clean = 0;
4030         rx_ring->next_to_use = 0;
4031 }
4032
4033 /**
4034  * ixgbe_clean_tx_ring - Free Tx Buffers
4035  * @tx_ring: ring to be cleaned
4036  **/
4037 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4038 {
4039         struct ixgbe_tx_buffer *tx_buffer_info;
4040         unsigned long size;
4041         u16 i;
4042
4043         /* ring already cleared, nothing to do */
4044         if (!tx_ring->tx_buffer_info)
4045                 return;
4046
4047         /* Free all the Tx ring sk_buffs */
4048         for (i = 0; i < tx_ring->count; i++) {
4049                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4050                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4051         }
4052
4053         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4054         memset(tx_ring->tx_buffer_info, 0, size);
4055
4056         /* Zero out the descriptor ring */
4057         memset(tx_ring->desc, 0, tx_ring->size);
4058
4059         tx_ring->next_to_use = 0;
4060         tx_ring->next_to_clean = 0;
4061 }
4062
4063 /**
4064  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4065  * @adapter: board private structure
4066  **/
4067 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4068 {
4069         int i;
4070
4071         for (i = 0; i < adapter->num_rx_queues; i++)
4072                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4073 }
4074
4075 /**
4076  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4077  * @adapter: board private structure
4078  **/
4079 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4080 {
4081         int i;
4082
4083         for (i = 0; i < adapter->num_tx_queues; i++)
4084                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4085 }
4086
4087 void ixgbe_down(struct ixgbe_adapter *adapter)
4088 {
4089         struct net_device *netdev = adapter->netdev;
4090         struct ixgbe_hw *hw = &adapter->hw;
4091         u32 rxctrl;
4092         u32 txdctl;
4093         int i;
4094         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4095
4096         /* signal that we are down to the interrupt handler */
4097         set_bit(__IXGBE_DOWN, &adapter->state);
4098
4099         /* disable receive for all VFs and wait one second */
4100         if (adapter->num_vfs) {
4101                 /* ping all the active vfs to let them know we are going down */
4102                 ixgbe_ping_all_vfs(adapter);
4103
4104                 /* Disable all VFTE/VFRE TX/RX */
4105                 ixgbe_disable_tx_rx(adapter);
4106
4107                 /* Mark all the VFs as inactive */
4108                 for (i = 0 ; i < adapter->num_vfs; i++)
4109                         adapter->vfinfo[i].clear_to_send = 0;
4110         }
4111
4112         /* disable receives */
4113         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4114         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4115
4116         /* disable all enabled rx queues */
4117         for (i = 0; i < adapter->num_rx_queues; i++)
4118                 /* this call also flushes the previous write */
4119                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4120
4121         msleep(10);
4122
4123         netif_tx_stop_all_queues(netdev);
4124
4125         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4126         del_timer_sync(&adapter->sfp_timer);
4127         del_timer_sync(&adapter->watchdog_timer);
4128         cancel_work_sync(&adapter->watchdog_task);
4129
4130         netif_carrier_off(netdev);
4131         netif_tx_disable(netdev);
4132
4133         ixgbe_irq_disable(adapter);
4134
4135         ixgbe_napi_disable_all(adapter);
4136
4137         /* Cleanup the affinity_hint CPU mask memory and callback */
4138         for (i = 0; i < num_q_vectors; i++) {
4139                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4140                 /* clear the affinity_mask in the IRQ descriptor */
4141                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4142                 /* release the CPU mask memory */
4143                 free_cpumask_var(q_vector->affinity_mask);
4144         }
4145
4146         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4147             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4148                 cancel_work_sync(&adapter->fdir_reinit_task);
4149
4150         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4151                 cancel_work_sync(&adapter->check_overtemp_task);
4152
4153         /* disable transmits in the hardware now that interrupts are off */
4154         for (i = 0; i < adapter->num_tx_queues; i++) {
4155                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4156                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4157                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4158                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4159         }
4160         /* Disable the Tx DMA engine on 82599 */
4161         switch (hw->mac.type) {
4162         case ixgbe_mac_82599EB:
4163         case ixgbe_mac_X540:
4164                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4165                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4166                                  ~IXGBE_DMATXCTL_TE));
4167                 break;
4168         default:
4169                 break;
4170         }
4171
4172         /* clear n-tuple filters that are cached */
4173         ethtool_ntuple_flush(netdev);
4174
4175         if (!pci_channel_offline(adapter->pdev))
4176                 ixgbe_reset(adapter);
4177
4178         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4179         if (hw->mac.ops.disable_tx_laser &&
4180             ((hw->phy.multispeed_fiber) ||
4181              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4182               (hw->mac.type == ixgbe_mac_82599EB))))
4183                 hw->mac.ops.disable_tx_laser(hw);
4184
4185         ixgbe_clean_all_tx_rings(adapter);
4186         ixgbe_clean_all_rx_rings(adapter);
4187
4188 #ifdef CONFIG_IXGBE_DCA
4189         /* since we reset the hardware DCA settings were cleared */
4190         ixgbe_setup_dca(adapter);
4191 #endif
4192 }
4193
4194 /**
4195  * ixgbe_poll - NAPI Rx polling callback
4196  * @napi: structure for representing this polling device
4197  * @budget: how many packets driver is allowed to clean
4198  *
4199  * This function is used for legacy and MSI, NAPI mode
4200  **/
4201 static int ixgbe_poll(struct napi_struct *napi, int budget)
4202 {
4203         struct ixgbe_q_vector *q_vector =
4204                                 container_of(napi, struct ixgbe_q_vector, napi);
4205         struct ixgbe_adapter *adapter = q_vector->adapter;
4206         int tx_clean_complete, work_done = 0;
4207
4208 #ifdef CONFIG_IXGBE_DCA
4209         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4210                 ixgbe_update_dca(q_vector);
4211 #endif
4212
4213         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4214         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4215
4216         if (!tx_clean_complete)
4217                 work_done = budget;
4218
4219         /* If budget not fully consumed, exit the polling mode */
4220         if (work_done < budget) {
4221                 napi_complete(napi);
4222                 if (adapter->rx_itr_setting & 1)
4223                         ixgbe_set_itr(adapter);
4224                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4225                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4226         }
4227         return work_done;
4228 }
4229
4230 /**
4231  * ixgbe_tx_timeout - Respond to a Tx Hang
4232  * @netdev: network interface device structure
4233  **/
4234 static void ixgbe_tx_timeout(struct net_device *netdev)
4235 {
4236         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4237
4238         adapter->tx_timeout_count++;
4239
4240         /* Do the reset outside of interrupt context */
4241         schedule_work(&adapter->reset_task);
4242 }
4243
4244 static void ixgbe_reset_task(struct work_struct *work)
4245 {
4246         struct ixgbe_adapter *adapter;
4247         adapter = container_of(work, struct ixgbe_adapter, reset_task);
4248
4249         /* If we're already down or resetting, just bail */
4250         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4251             test_bit(__IXGBE_RESETTING, &adapter->state))
4252                 return;
4253
4254         ixgbe_dump(adapter);
4255         netdev_err(adapter->netdev, "Reset adapter\n");
4256         ixgbe_reinit_locked(adapter);
4257 }
4258
4259 #ifdef CONFIG_IXGBE_DCB
4260 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4261 {
4262         bool ret = false;
4263         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4264
4265         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4266                 return ret;
4267
4268         f->mask = 0x7 << 3;
4269         adapter->num_rx_queues = f->indices;
4270         adapter->num_tx_queues = f->indices;
4271         ret = true;
4272
4273         return ret;
4274 }
4275 #endif
4276
4277 /**
4278  * ixgbe_set_rss_queues: Allocate queues for RSS
4279  * @adapter: board private structure to initialize
4280  *
4281  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4282  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4283  *
4284  **/
4285 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4286 {
4287         bool ret = false;
4288         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4289
4290         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4291                 f->mask = 0xF;
4292                 adapter->num_rx_queues = f->indices;
4293                 adapter->num_tx_queues = f->indices;
4294                 ret = true;
4295         } else {
4296                 ret = false;
4297         }
4298
4299         return ret;
4300 }
4301
4302 /**
4303  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4304  * @adapter: board private structure to initialize
4305  *
4306  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4307  * to the original CPU that initiated the Tx session.  This runs in addition
4308  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4309  * Rx load across CPUs using RSS.
4310  *
4311  **/
4312 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4313 {
4314         bool ret = false;
4315         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4316
4317         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4318         f_fdir->mask = 0;
4319
4320         /* Flow Director must have RSS enabled */
4321         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4322             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4323              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4324                 adapter->num_tx_queues = f_fdir->indices;
4325                 adapter->num_rx_queues = f_fdir->indices;
4326                 ret = true;
4327         } else {
4328                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4329                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4330         }
4331         return ret;
4332 }
4333
4334 #ifdef IXGBE_FCOE
4335 /**
4336  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4337  * @adapter: board private structure to initialize
4338  *
4339  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4340  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4341  * rx queues out of the max number of rx queues, instead, it is used as the
4342  * index of the first rx queue used by FCoE.
4343  *
4344  **/
4345 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4346 {
4347         bool ret = false;
4348         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4349
4350         f->indices = min((int)num_online_cpus(), f->indices);
4351         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4352                 adapter->num_rx_queues = 1;
4353                 adapter->num_tx_queues = 1;
4354 #ifdef CONFIG_IXGBE_DCB
4355                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4356                         e_info(probe, "FCoE enabled with DCB\n");
4357                         ixgbe_set_dcb_queues(adapter);
4358                 }
4359 #endif
4360                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4361                         e_info(probe, "FCoE enabled with RSS\n");
4362                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4363                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4364                                 ixgbe_set_fdir_queues(adapter);
4365                         else
4366                                 ixgbe_set_rss_queues(adapter);
4367                 }
4368                 /* adding FCoE rx rings to the end */
4369                 f->mask = adapter->num_rx_queues;
4370                 adapter->num_rx_queues += f->indices;
4371                 adapter->num_tx_queues += f->indices;
4372
4373                 ret = true;
4374         }
4375
4376         return ret;
4377 }
4378
4379 #endif /* IXGBE_FCOE */
4380 /**
4381  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4382  * @adapter: board private structure to initialize
4383  *
4384  * IOV doesn't actually use anything, so just NAK the
4385  * request for now and let the other queue routines
4386  * figure out what to do.
4387  */
4388 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4389 {
4390         return false;
4391 }
4392
4393 /*
4394  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4395  * @adapter: board private structure to initialize
4396  *
4397  * This is the top level queue allocation routine.  The order here is very
4398  * important, starting with the "most" number of features turned on at once,
4399  * and ending with the smallest set of features.  This way large combinations
4400  * can be allocated if they're turned on, and smaller combinations are the
4401  * fallthrough conditions.
4402  *
4403  **/
4404 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4405 {
4406         /* Start with base case */
4407         adapter->num_rx_queues = 1;
4408         adapter->num_tx_queues = 1;
4409         adapter->num_rx_pools = adapter->num_rx_queues;
4410         adapter->num_rx_queues_per_pool = 1;
4411
4412         if (ixgbe_set_sriov_queues(adapter))
4413                 goto done;
4414
4415 #ifdef IXGBE_FCOE
4416         if (ixgbe_set_fcoe_queues(adapter))
4417                 goto done;
4418
4419 #endif /* IXGBE_FCOE */
4420 #ifdef CONFIG_IXGBE_DCB
4421         if (ixgbe_set_dcb_queues(adapter))
4422                 goto done;
4423
4424 #endif
4425         if (ixgbe_set_fdir_queues(adapter))
4426                 goto done;
4427
4428         if (ixgbe_set_rss_queues(adapter))
4429                 goto done;
4430
4431         /* fallback to base case */
4432         adapter->num_rx_queues = 1;
4433         adapter->num_tx_queues = 1;
4434
4435 done:
4436         /* Notify the stack of the (possibly) reduced queue counts. */
4437         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4438         return netif_set_real_num_rx_queues(adapter->netdev,
4439                                             adapter->num_rx_queues);
4440 }
4441
4442 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4443                                        int vectors)
4444 {
4445         int err, vector_threshold;
4446
4447         /* We'll want at least 3 (vector_threshold):
4448          * 1) TxQ[0] Cleanup
4449          * 2) RxQ[0] Cleanup
4450          * 3) Other (Link Status Change, etc.)
4451          * 4) TCP Timer (optional)
4452          */
4453         vector_threshold = MIN_MSIX_COUNT;
4454
4455         /* The more we get, the more we will assign to Tx/Rx Cleanup
4456          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4457          * Right now, we simply care about how many we'll get; we'll
4458          * set them up later while requesting irq's.
4459          */
4460         while (vectors >= vector_threshold) {
4461                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4462                                       vectors);
4463                 if (!err) /* Success in acquiring all requested vectors. */
4464                         break;
4465                 else if (err < 0)
4466                         vectors = 0; /* Nasty failure, quit now */
4467                 else /* err == number of vectors we should try again with */
4468                         vectors = err;
4469         }
4470
4471         if (vectors < vector_threshold) {
4472                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4473                  * This just means we'll go with either a single MSI
4474                  * vector or fall back to legacy interrupts.
4475                  */
4476                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4477                              "Unable to allocate MSI-X interrupts\n");
4478                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4479                 kfree(adapter->msix_entries);
4480                 adapter->msix_entries = NULL;
4481         } else {
4482                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4483                 /*
4484                  * Adjust for only the vectors we'll use, which is minimum
4485                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4486                  * vectors we were allocated.
4487                  */
4488                 adapter->num_msix_vectors = min(vectors,
4489                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4490         }
4491 }
4492
4493 /**
4494  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4495  * @adapter: board private structure to initialize
4496  *
4497  * Cache the descriptor ring offsets for RSS to the assigned rings.
4498  *
4499  **/
4500 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4501 {
4502         int i;
4503
4504         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4505                 return false;
4506
4507         for (i = 0; i < adapter->num_rx_queues; i++)
4508                 adapter->rx_ring[i]->reg_idx = i;
4509         for (i = 0; i < adapter->num_tx_queues; i++)
4510                 adapter->tx_ring[i]->reg_idx = i;
4511
4512         return true;
4513 }
4514
4515 #ifdef CONFIG_IXGBE_DCB
4516 /**
4517  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4518  * @adapter: board private structure to initialize
4519  *
4520  * Cache the descriptor ring offsets for DCB to the assigned rings.
4521  *
4522  **/
4523 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4524 {
4525         int i;
4526         bool ret = false;
4527         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4528
4529         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4530                 return false;
4531
4532         /* the number of queues is assumed to be symmetric */
4533         switch (adapter->hw.mac.type) {
4534         case ixgbe_mac_82598EB:
4535                 for (i = 0; i < dcb_i; i++) {
4536                         adapter->rx_ring[i]->reg_idx = i << 3;
4537                         adapter->tx_ring[i]->reg_idx = i << 2;
4538                 }
4539                 ret = true;
4540                 break;
4541         case ixgbe_mac_82599EB:
4542         case ixgbe_mac_X540:
4543                 if (dcb_i == 8) {
4544                         /*
4545                          * Tx TC0 starts at: descriptor queue 0
4546                          * Tx TC1 starts at: descriptor queue 32
4547                          * Tx TC2 starts at: descriptor queue 64
4548                          * Tx TC3 starts at: descriptor queue 80
4549                          * Tx TC4 starts at: descriptor queue 96
4550                          * Tx TC5 starts at: descriptor queue 104
4551                          * Tx TC6 starts at: descriptor queue 112
4552                          * Tx TC7 starts at: descriptor queue 120
4553                          *
4554                          * Rx TC0-TC7 are offset by 16 queues each
4555                          */
4556                         for (i = 0; i < 3; i++) {
4557                                 adapter->tx_ring[i]->reg_idx = i << 5;
4558                                 adapter->rx_ring[i]->reg_idx = i << 4;
4559                         }
4560                         for ( ; i < 5; i++) {
4561                                 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4562                                 adapter->rx_ring[i]->reg_idx = i << 4;
4563                         }
4564                         for ( ; i < dcb_i; i++) {
4565                                 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4566                                 adapter->rx_ring[i]->reg_idx = i << 4;
4567                         }
4568                         ret = true;
4569                 } else if (dcb_i == 4) {
4570                         /*
4571                          * Tx TC0 starts at: descriptor queue 0
4572                          * Tx TC1 starts at: descriptor queue 64
4573                          * Tx TC2 starts at: descriptor queue 96
4574                          * Tx TC3 starts at: descriptor queue 112
4575                          *
4576                          * Rx TC0-TC3 are offset by 32 queues each
4577                          */
4578                         adapter->tx_ring[0]->reg_idx = 0;
4579                         adapter->tx_ring[1]->reg_idx = 64;
4580                         adapter->tx_ring[2]->reg_idx = 96;
4581                         adapter->tx_ring[3]->reg_idx = 112;
4582                         for (i = 0 ; i < dcb_i; i++)
4583                                 adapter->rx_ring[i]->reg_idx = i << 5;
4584                         ret = true;
4585                 }
4586                 break;
4587         default:
4588                 break;
4589         }
4590         return ret;
4591 }
4592 #endif
4593
4594 /**
4595  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4596  * @adapter: board private structure to initialize
4597  *
4598  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4599  *
4600  **/
4601 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4602 {
4603         int i;
4604         bool ret = false;
4605
4606         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4607             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4608              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4609                 for (i = 0; i < adapter->num_rx_queues; i++)
4610                         adapter->rx_ring[i]->reg_idx = i;
4611                 for (i = 0; i < adapter->num_tx_queues; i++)
4612                         adapter->tx_ring[i]->reg_idx = i;
4613                 ret = true;
4614         }
4615
4616         return ret;
4617 }
4618
4619 #ifdef IXGBE_FCOE
4620 /**
4621  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4622  * @adapter: board private structure to initialize
4623  *
4624  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4625  *
4626  */
4627 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4628 {
4629         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4630         int i;
4631         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4632
4633         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4634                 return false;
4635
4636 #ifdef CONFIG_IXGBE_DCB
4637         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4638                 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4639
4640                 ixgbe_cache_ring_dcb(adapter);
4641                 /* find out queues in TC for FCoE */
4642                 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4643                 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4644                 /*
4645                  * In 82599, the number of Tx queues for each traffic
4646                  * class for both 8-TC and 4-TC modes are:
4647                  * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4648                  * 8 TCs:  32  32  16  16   8   8   8   8
4649                  * 4 TCs:  64  64  32  32
4650                  * We have max 8 queues for FCoE, where 8 the is
4651                  * FCoE redirection table size. If TC for FCoE is
4652                  * less than or equal to TC3, we have enough queues
4653                  * to add max of 8 queues for FCoE, so we start FCoE
4654                  * Tx queue from the next one, i.e., reg_idx + 1.
4655                  * If TC for FCoE is above TC3, implying 8 TC mode,
4656                  * and we need 8 for FCoE, we have to take all queues
4657                  * in that traffic class for FCoE.
4658                  */
4659                 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4660                         fcoe_tx_i--;
4661         }
4662 #endif /* CONFIG_IXGBE_DCB */
4663         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4664                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4665                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4666                         ixgbe_cache_ring_fdir(adapter);
4667                 else
4668                         ixgbe_cache_ring_rss(adapter);
4669
4670                 fcoe_rx_i = f->mask;
4671                 fcoe_tx_i = f->mask;
4672         }
4673         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4674                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4675                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4676         }
4677         return true;
4678 }
4679
4680 #endif /* IXGBE_FCOE */
4681 /**
4682  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4683  * @adapter: board private structure to initialize
4684  *
4685  * SR-IOV doesn't use any descriptor rings but changes the default if
4686  * no other mapping is used.
4687  *
4688  */
4689 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4690 {
4691         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4692         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4693         if (adapter->num_vfs)
4694                 return true;
4695         else
4696                 return false;
4697 }
4698
4699 /**
4700  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4701  * @adapter: board private structure to initialize
4702  *
4703  * Once we know the feature-set enabled for the device, we'll cache
4704  * the register offset the descriptor ring is assigned to.
4705  *
4706  * Note, the order the various feature calls is important.  It must start with
4707  * the "most" features enabled at the same time, then trickle down to the
4708  * least amount of features turned on at once.
4709  **/
4710 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4711 {
4712         /* start with default case */
4713         adapter->rx_ring[0]->reg_idx = 0;
4714         adapter->tx_ring[0]->reg_idx = 0;
4715
4716         if (ixgbe_cache_ring_sriov(adapter))
4717                 return;
4718
4719 #ifdef IXGBE_FCOE
4720         if (ixgbe_cache_ring_fcoe(adapter))
4721                 return;
4722
4723 #endif /* IXGBE_FCOE */
4724 #ifdef CONFIG_IXGBE_DCB
4725         if (ixgbe_cache_ring_dcb(adapter))
4726                 return;
4727
4728 #endif
4729         if (ixgbe_cache_ring_fdir(adapter))
4730                 return;
4731
4732         if (ixgbe_cache_ring_rss(adapter))
4733                 return;
4734 }
4735
4736 /**
4737  * ixgbe_alloc_queues - Allocate memory for all rings
4738  * @adapter: board private structure to initialize
4739  *
4740  * We allocate one ring per queue at run-time since we don't know the
4741  * number of queues at compile-time.  The polling_netdev array is
4742  * intended for Multiqueue, but should work fine with a single queue.
4743  **/
4744 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4745 {
4746         int rx = 0, tx = 0, nid = adapter->node;
4747
4748         if (nid < 0 || !node_online(nid))
4749                 nid = first_online_node;
4750
4751         for (; tx < adapter->num_tx_queues; tx++) {
4752                 struct ixgbe_ring *ring;
4753
4754                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4755                 if (!ring)
4756                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4757                 if (!ring)
4758                         goto err_allocation;
4759                 ring->count = adapter->tx_ring_count;
4760                 ring->queue_index = tx;
4761                 ring->numa_node = nid;
4762                 ring->dev = &adapter->pdev->dev;
4763                 ring->netdev = adapter->netdev;
4764
4765                 adapter->tx_ring[tx] = ring;
4766         }
4767
4768         for (; rx < adapter->num_rx_queues; rx++) {
4769                 struct ixgbe_ring *ring;
4770
4771                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4772                 if (!ring)
4773                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4774                 if (!ring)
4775                         goto err_allocation;
4776                 ring->count = adapter->rx_ring_count;
4777                 ring->queue_index = rx;
4778                 ring->numa_node = nid;
4779                 ring->dev = &adapter->pdev->dev;
4780                 ring->netdev = adapter->netdev;
4781
4782                 adapter->rx_ring[rx] = ring;
4783         }
4784
4785         ixgbe_cache_ring_register(adapter);
4786
4787         return 0;
4788
4789 err_allocation:
4790         while (tx)
4791                 kfree(adapter->tx_ring[--tx]);
4792
4793         while (rx)
4794                 kfree(adapter->rx_ring[--rx]);
4795         return -ENOMEM;
4796 }
4797
4798 /**
4799  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4800  * @adapter: board private structure to initialize
4801  *
4802  * Attempt to configure the interrupts using the best available
4803  * capabilities of the hardware and the kernel.
4804  **/
4805 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4806 {
4807         struct ixgbe_hw *hw = &adapter->hw;
4808         int err = 0;
4809         int vector, v_budget;
4810
4811         /*
4812          * It's easy to be greedy for MSI-X vectors, but it really
4813          * doesn't do us much good if we have a lot more vectors
4814          * than CPU's.  So let's be conservative and only ask for
4815          * (roughly) the same number of vectors as there are CPU's.
4816          */
4817         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4818                        (int)num_online_cpus()) + NON_Q_VECTORS;
4819
4820         /*
4821          * At the same time, hardware can only support a maximum of
4822          * hw.mac->max_msix_vectors vectors.  With features
4823          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4824          * descriptor queues supported by our device.  Thus, we cap it off in
4825          * those rare cases where the cpu count also exceeds our vector limit.
4826          */
4827         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4828
4829         /* A failure in MSI-X entry allocation isn't fatal, but it does
4830          * mean we disable MSI-X capabilities of the adapter. */
4831         adapter->msix_entries = kcalloc(v_budget,
4832                                         sizeof(struct msix_entry), GFP_KERNEL);
4833         if (adapter->msix_entries) {
4834                 for (vector = 0; vector < v_budget; vector++)
4835                         adapter->msix_entries[vector].entry = vector;
4836
4837                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4838
4839                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4840                         goto out;
4841         }
4842
4843         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4844         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4845         if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4846                               IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4847                 e_err(probe,
4848                       "Flow Director is not supported while multiple "
4849                       "queues are disabled.  Disabling Flow Director\n");
4850         }
4851         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4852         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4853         adapter->atr_sample_rate = 0;
4854         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4855                 ixgbe_disable_sriov(adapter);
4856
4857         err = ixgbe_set_num_queues(adapter);
4858         if (err)
4859                 return err;
4860
4861         err = pci_enable_msi(adapter->pdev);
4862         if (!err) {
4863                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4864         } else {
4865                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4866                              "Unable to allocate MSI interrupt, "
4867                              "falling back to legacy.  Error: %d\n", err);
4868                 /* reset err */
4869                 err = 0;
4870         }
4871
4872 out:
4873         return err;
4874 }
4875
4876 /**
4877  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4878  * @adapter: board private structure to initialize
4879  *
4880  * We allocate one q_vector per queue interrupt.  If allocation fails we
4881  * return -ENOMEM.
4882  **/
4883 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4884 {
4885         int q_idx, num_q_vectors;
4886         struct ixgbe_q_vector *q_vector;
4887         int (*poll)(struct napi_struct *, int);
4888
4889         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4890                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4891                 poll = &ixgbe_clean_rxtx_many;
4892         } else {
4893                 num_q_vectors = 1;
4894                 poll = &ixgbe_poll;
4895         }
4896
4897         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4898                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4899                                         GFP_KERNEL, adapter->node);
4900                 if (!q_vector)
4901                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4902                                            GFP_KERNEL);
4903                 if (!q_vector)
4904                         goto err_out;
4905                 q_vector->adapter = adapter;
4906                 if (q_vector->txr_count && !q_vector->rxr_count)
4907                         q_vector->eitr = adapter->tx_eitr_param;
4908                 else
4909                         q_vector->eitr = adapter->rx_eitr_param;
4910                 q_vector->v_idx = q_idx;
4911                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4912                 adapter->q_vector[q_idx] = q_vector;
4913         }
4914
4915         return 0;
4916
4917 err_out:
4918         while (q_idx) {
4919                 q_idx--;
4920                 q_vector = adapter->q_vector[q_idx];
4921                 netif_napi_del(&q_vector->napi);
4922                 kfree(q_vector);
4923                 adapter->q_vector[q_idx] = NULL;
4924         }
4925         return -ENOMEM;
4926 }
4927
4928 /**
4929  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4930  * @adapter: board private structure to initialize
4931  *
4932  * This function frees the memory allocated to the q_vectors.  In addition if
4933  * NAPI is enabled it will delete any references to the NAPI struct prior
4934  * to freeing the q_vector.
4935  **/
4936 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4937 {
4938         int q_idx, num_q_vectors;
4939
4940         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4941                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4942         else
4943                 num_q_vectors = 1;
4944
4945         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4946                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4947                 adapter->q_vector[q_idx] = NULL;
4948                 netif_napi_del(&q_vector->napi);
4949                 kfree(q_vector);
4950         }
4951 }
4952
4953 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4954 {
4955         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4956                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4957                 pci_disable_msix(adapter->pdev);
4958                 kfree(adapter->msix_entries);
4959                 adapter->msix_entries = NULL;
4960         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4961                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4962                 pci_disable_msi(adapter->pdev);
4963         }
4964 }
4965
4966 /**
4967  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4968  * @adapter: board private structure to initialize
4969  *
4970  * We determine which interrupt scheme to use based on...
4971  * - Kernel support (MSI, MSI-X)
4972  *   - which can be user-defined (via MODULE_PARAM)
4973  * - Hardware queue count (num_*_queues)
4974  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4975  **/
4976 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4977 {
4978         int err;
4979
4980         /* Number of supported queues */
4981         err = ixgbe_set_num_queues(adapter);
4982         if (err)
4983                 return err;
4984
4985         err = ixgbe_set_interrupt_capability(adapter);
4986         if (err) {
4987                 e_dev_err("Unable to setup interrupt capabilities\n");
4988                 goto err_set_interrupt;
4989         }
4990
4991         err = ixgbe_alloc_q_vectors(adapter);
4992         if (err) {
4993                 e_dev_err("Unable to allocate memory for queue vectors\n");
4994                 goto err_alloc_q_vectors;
4995         }
4996
4997         err = ixgbe_alloc_queues(adapter);
4998         if (err) {
4999                 e_dev_err("Unable to allocate memory for queues\n");
5000                 goto err_alloc_queues;
5001         }
5002
5003         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5004                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5005                    adapter->num_rx_queues, adapter->num_tx_queues);
5006
5007         set_bit(__IXGBE_DOWN, &adapter->state);
5008
5009         return 0;
5010
5011 err_alloc_queues:
5012         ixgbe_free_q_vectors(adapter);
5013 err_alloc_q_vectors:
5014         ixgbe_reset_interrupt_capability(adapter);
5015 err_set_interrupt:
5016         return err;
5017 }
5018
5019 static void ring_free_rcu(struct rcu_head *head)
5020 {
5021         kfree(container_of(head, struct ixgbe_ring, rcu));
5022 }
5023
5024 /**
5025  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5026  * @adapter: board private structure to clear interrupt scheme on
5027  *
5028  * We go through and clear interrupt specific resources and reset the structure
5029  * to pre-load conditions
5030  **/
5031 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5032 {
5033         int i;
5034
5035         for (i = 0; i < adapter->num_tx_queues; i++) {
5036                 kfree(adapter->tx_ring[i]);
5037                 adapter->tx_ring[i] = NULL;
5038         }
5039         for (i = 0; i < adapter->num_rx_queues; i++) {
5040                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5041
5042                 /* ixgbe_get_stats64() might access this ring, we must wait
5043                  * a grace period before freeing it.
5044                  */
5045                 call_rcu(&ring->rcu, ring_free_rcu);
5046                 adapter->rx_ring[i] = NULL;
5047         }
5048
5049         adapter->num_tx_queues = 0;
5050         adapter->num_rx_queues = 0;
5051
5052         ixgbe_free_q_vectors(adapter);
5053         ixgbe_reset_interrupt_capability(adapter);
5054 }
5055
5056 /**
5057  * ixgbe_sfp_timer - worker thread to find a missing module
5058  * @data: pointer to our adapter struct
5059  **/
5060 static void ixgbe_sfp_timer(unsigned long data)
5061 {
5062         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5063
5064         /*
5065          * Do the sfp_timer outside of interrupt context due to the
5066          * delays that sfp+ detection requires
5067          */
5068         schedule_work(&adapter->sfp_task);
5069 }
5070
5071 /**
5072  * ixgbe_sfp_task - worker thread to find a missing module
5073  * @work: pointer to work_struct containing our data
5074  **/
5075 static void ixgbe_sfp_task(struct work_struct *work)
5076 {
5077         struct ixgbe_adapter *adapter = container_of(work,
5078                                                      struct ixgbe_adapter,
5079                                                      sfp_task);
5080         struct ixgbe_hw *hw = &adapter->hw;
5081
5082         if ((hw->phy.type == ixgbe_phy_nl) &&
5083             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5084                 s32 ret = hw->phy.ops.identify_sfp(hw);
5085                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5086                         goto reschedule;
5087                 ret = hw->phy.ops.reset(hw);
5088                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5089                         e_dev_err("failed to initialize because an unsupported "
5090                                   "SFP+ module type was detected.\n");
5091                         e_dev_err("Reload the driver after installing a "
5092                                   "supported module.\n");
5093                         unregister_netdev(adapter->netdev);
5094                 } else {
5095                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5096                 }
5097                 /* don't need this routine any more */
5098                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5099         }
5100         return;
5101 reschedule:
5102         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5103                 mod_timer(&adapter->sfp_timer,
5104                           round_jiffies(jiffies + (2 * HZ)));
5105 }
5106
5107 /**
5108  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5109  * @adapter: board private structure to initialize
5110  *
5111  * ixgbe_sw_init initializes the Adapter private data structure.
5112  * Fields are initialized based on PCI device information and
5113  * OS network device settings (MTU size).
5114  **/
5115 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5116 {
5117         struct ixgbe_hw *hw = &adapter->hw;
5118         struct pci_dev *pdev = adapter->pdev;
5119         struct net_device *dev = adapter->netdev;
5120         unsigned int rss;
5121 #ifdef CONFIG_IXGBE_DCB
5122         int j;
5123         struct tc_configuration *tc;
5124 #endif
5125         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5126
5127         /* PCI config space info */
5128
5129         hw->vendor_id = pdev->vendor;
5130         hw->device_id = pdev->device;
5131         hw->revision_id = pdev->revision;
5132         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5133         hw->subsystem_device_id = pdev->subsystem_device;
5134
5135         /* Set capability flags */
5136         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5137         adapter->ring_feature[RING_F_RSS].indices = rss;
5138         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5139         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5140         switch (hw->mac.type) {
5141         case ixgbe_mac_82598EB:
5142                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5143                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5144                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5145                 break;
5146         case ixgbe_mac_82599EB:
5147         case ixgbe_mac_X540:
5148                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5149                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5150                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5151                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5152                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5153                 /* n-tuple support exists, always init our spinlock */
5154                 spin_lock_init(&adapter->fdir_perfect_lock);
5155                 /* Flow Director hash filters enabled */
5156                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5157                 adapter->atr_sample_rate = 20;
5158                 adapter->ring_feature[RING_F_FDIR].indices =
5159                                                          IXGBE_MAX_FDIR_INDICES;
5160                 adapter->fdir_pballoc = 0;
5161 #ifdef IXGBE_FCOE
5162                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5163                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5164                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5165 #ifdef CONFIG_IXGBE_DCB
5166                 /* Default traffic class to use for FCoE */
5167                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5168                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5169 #endif
5170 #endif /* IXGBE_FCOE */
5171                 break;
5172         default:
5173                 break;
5174         }
5175
5176 #ifdef CONFIG_IXGBE_DCB
5177         /* Configure DCB traffic classes */
5178         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5179                 tc = &adapter->dcb_cfg.tc_config[j];
5180                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5181                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5182                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5183                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5184                 tc->dcb_pfc = pfc_disabled;
5185         }
5186         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5187         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5188         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5189         adapter->dcb_cfg.pfc_mode_enable = false;
5190         adapter->dcb_set_bitmap = 0x00;
5191         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5192                            adapter->ring_feature[RING_F_DCB].indices);
5193
5194 #endif
5195
5196         /* default flow control settings */
5197         hw->fc.requested_mode = ixgbe_fc_full;
5198         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5199 #ifdef CONFIG_DCB
5200         adapter->last_lfc_mode = hw->fc.current_mode;
5201 #endif
5202         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5203         hw->fc.low_water = FC_LOW_WATER(max_frame);
5204         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5205         hw->fc.send_xon = true;
5206         hw->fc.disable_fc_autoneg = false;
5207
5208         /* enable itr by default in dynamic mode */
5209         adapter->rx_itr_setting = 1;
5210         adapter->rx_eitr_param = 20000;
5211         adapter->tx_itr_setting = 1;
5212         adapter->tx_eitr_param = 10000;
5213
5214         /* set defaults for eitr in MegaBytes */
5215         adapter->eitr_low = 10;
5216         adapter->eitr_high = 20;
5217
5218         /* set default ring sizes */
5219         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5220         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5221
5222         /* initialize eeprom parameters */
5223         if (ixgbe_init_eeprom_params_generic(hw)) {
5224                 e_dev_err("EEPROM initialization failed\n");
5225                 return -EIO;
5226         }
5227
5228         /* enable rx csum by default */
5229         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5230
5231         /* get assigned NUMA node */
5232         adapter->node = dev_to_node(&pdev->dev);
5233
5234         set_bit(__IXGBE_DOWN, &adapter->state);
5235
5236         return 0;
5237 }
5238
5239 /**
5240  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5241  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5242  *
5243  * Return 0 on success, negative on failure
5244  **/
5245 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5246 {
5247         struct device *dev = tx_ring->dev;
5248         int size;
5249
5250         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5251         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5252         if (!tx_ring->tx_buffer_info)
5253                 tx_ring->tx_buffer_info = vzalloc(size);
5254         if (!tx_ring->tx_buffer_info)
5255                 goto err;
5256
5257         /* round up to nearest 4K */
5258         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5259         tx_ring->size = ALIGN(tx_ring->size, 4096);
5260
5261         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5262                                            &tx_ring->dma, GFP_KERNEL);
5263         if (!tx_ring->desc)
5264                 goto err;
5265
5266         tx_ring->next_to_use = 0;
5267         tx_ring->next_to_clean = 0;
5268         tx_ring->work_limit = tx_ring->count;
5269         return 0;
5270
5271 err:
5272         vfree(tx_ring->tx_buffer_info);
5273         tx_ring->tx_buffer_info = NULL;
5274         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5275         return -ENOMEM;
5276 }
5277
5278 /**
5279  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5280  * @adapter: board private structure
5281  *
5282  * If this function returns with an error, then it's possible one or
5283  * more of the rings is populated (while the rest are not).  It is the
5284  * callers duty to clean those orphaned rings.
5285  *
5286  * Return 0 on success, negative on failure
5287  **/
5288 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5289 {
5290         int i, err = 0;
5291
5292         for (i = 0; i < adapter->num_tx_queues; i++) {
5293                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5294                 if (!err)
5295                         continue;
5296                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5297                 break;
5298         }
5299
5300         return err;
5301 }
5302
5303 /**
5304  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5305  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5306  *
5307  * Returns 0 on success, negative on failure
5308  **/
5309 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5310 {
5311         struct device *dev = rx_ring->dev;
5312         int size;
5313
5314         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5315         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5316         if (!rx_ring->rx_buffer_info)
5317                 rx_ring->rx_buffer_info = vzalloc(size);
5318         if (!rx_ring->rx_buffer_info)
5319                 goto err;
5320
5321         /* Round up to nearest 4K */
5322         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5323         rx_ring->size = ALIGN(rx_ring->size, 4096);
5324
5325         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5326                                            &rx_ring->dma, GFP_KERNEL);
5327
5328         if (!rx_ring->desc)
5329                 goto err;
5330
5331         rx_ring->next_to_clean = 0;
5332         rx_ring->next_to_use = 0;
5333
5334         return 0;
5335 err:
5336         vfree(rx_ring->rx_buffer_info);
5337         rx_ring->rx_buffer_info = NULL;
5338         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5339         return -ENOMEM;
5340 }
5341
5342 /**
5343  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5344  * @adapter: board private structure
5345  *
5346  * If this function returns with an error, then it's possible one or
5347  * more of the rings is populated (while the rest are not).  It is the
5348  * callers duty to clean those orphaned rings.
5349  *
5350  * Return 0 on success, negative on failure
5351  **/
5352 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5353 {
5354         int i, err = 0;
5355
5356         for (i = 0; i < adapter->num_rx_queues; i++) {
5357                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5358                 if (!err)
5359                         continue;
5360                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5361                 break;
5362         }
5363
5364         return err;
5365 }
5366
5367 /**
5368  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5369  * @tx_ring: Tx descriptor ring for a specific queue
5370  *
5371  * Free all transmit software resources
5372  **/
5373 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5374 {
5375         ixgbe_clean_tx_ring(tx_ring);
5376
5377         vfree(tx_ring->tx_buffer_info);
5378         tx_ring->tx_buffer_info = NULL;
5379
5380         /* if not set, then don't free */
5381         if (!tx_ring->desc)
5382                 return;
5383
5384         dma_free_coherent(tx_ring->dev, tx_ring->size,
5385                           tx_ring->desc, tx_ring->dma);
5386
5387         tx_ring->desc = NULL;
5388 }
5389
5390 /**
5391  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5392  * @adapter: board private structure
5393  *
5394  * Free all transmit software resources
5395  **/
5396 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5397 {
5398         int i;
5399
5400         for (i = 0; i < adapter->num_tx_queues; i++)
5401                 if (adapter->tx_ring[i]->desc)
5402                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5403 }
5404
5405 /**
5406  * ixgbe_free_rx_resources - Free Rx Resources
5407  * @rx_ring: ring to clean the resources from
5408  *
5409  * Free all receive software resources
5410  **/
5411 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5412 {
5413         ixgbe_clean_rx_ring(rx_ring);
5414
5415         vfree(rx_ring->rx_buffer_info);
5416         rx_ring->rx_buffer_info = NULL;
5417
5418         /* if not set, then don't free */
5419         if (!rx_ring->desc)
5420                 return;
5421
5422         dma_free_coherent(rx_ring->dev, rx_ring->size,
5423                           rx_ring->desc, rx_ring->dma);
5424
5425         rx_ring->desc = NULL;
5426 }
5427
5428 /**
5429  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5430  * @adapter: board private structure
5431  *
5432  * Free all receive software resources
5433  **/
5434 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5435 {
5436         int i;
5437
5438         for (i = 0; i < adapter->num_rx_queues; i++)
5439                 if (adapter->rx_ring[i]->desc)
5440                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5441 }
5442
5443 /**
5444  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5445  * @netdev: network interface device structure
5446  * @new_mtu: new value for maximum frame size
5447  *
5448  * Returns 0 on success, negative on failure
5449  **/
5450 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5451 {
5452         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5453         struct ixgbe_hw *hw = &adapter->hw;
5454         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5455
5456         /* MTU < 68 is an error and causes problems on some kernels */
5457         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5458             hw->mac.type != ixgbe_mac_X540) {
5459                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5460                         return -EINVAL;
5461         } else {
5462                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5463                         return -EINVAL;
5464         }
5465
5466         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5467         /* must set new MTU before calling down or up */
5468         netdev->mtu = new_mtu;
5469
5470         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5471         hw->fc.low_water = FC_LOW_WATER(max_frame);
5472
5473         if (netif_running(netdev))
5474                 ixgbe_reinit_locked(adapter);
5475
5476         return 0;
5477 }
5478
5479 /**
5480  * ixgbe_open - Called when a network interface is made active
5481  * @netdev: network interface device structure
5482  *
5483  * Returns 0 on success, negative value on failure
5484  *
5485  * The open entry point is called when a network interface is made
5486  * active by the system (IFF_UP).  At this point all resources needed
5487  * for transmit and receive operations are allocated, the interrupt
5488  * handler is registered with the OS, the watchdog timer is started,
5489  * and the stack is notified that the interface is ready.
5490  **/
5491 static int ixgbe_open(struct net_device *netdev)
5492 {
5493         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5494         int err;
5495
5496         /* disallow open during test */
5497         if (test_bit(__IXGBE_TESTING, &adapter->state))
5498                 return -EBUSY;
5499
5500         netif_carrier_off(netdev);
5501
5502         /* allocate transmit descriptors */
5503         err = ixgbe_setup_all_tx_resources(adapter);
5504         if (err)
5505                 goto err_setup_tx;
5506
5507         /* allocate receive descriptors */
5508         err = ixgbe_setup_all_rx_resources(adapter);
5509         if (err)
5510                 goto err_setup_rx;
5511
5512         ixgbe_configure(adapter);
5513
5514         err = ixgbe_request_irq(adapter);
5515         if (err)
5516                 goto err_req_irq;
5517
5518         err = ixgbe_up_complete(adapter);
5519         if (err)
5520                 goto err_up;
5521
5522         netif_tx_start_all_queues(netdev);
5523
5524         return 0;
5525
5526 err_up:
5527         ixgbe_release_hw_control(adapter);
5528         ixgbe_free_irq(adapter);
5529 err_req_irq:
5530 err_setup_rx:
5531         ixgbe_free_all_rx_resources(adapter);
5532 err_setup_tx:
5533         ixgbe_free_all_tx_resources(adapter);
5534         ixgbe_reset(adapter);
5535
5536         return err;
5537 }
5538
5539 /**
5540  * ixgbe_close - Disables a network interface
5541  * @netdev: network interface device structure
5542  *
5543  * Returns 0, this is not allowed to fail
5544  *
5545  * The close entry point is called when an interface is de-activated
5546  * by the OS.  The hardware is still under the drivers control, but
5547  * needs to be disabled.  A global MAC reset is issued to stop the
5548  * hardware, and all transmit and receive resources are freed.
5549  **/
5550 static int ixgbe_close(struct net_device *netdev)
5551 {
5552         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5553
5554         ixgbe_down(adapter);
5555         ixgbe_free_irq(adapter);
5556
5557         ixgbe_free_all_tx_resources(adapter);
5558         ixgbe_free_all_rx_resources(adapter);
5559
5560         ixgbe_release_hw_control(adapter);
5561
5562         return 0;
5563 }
5564
5565 #ifdef CONFIG_PM
5566 static int ixgbe_resume(struct pci_dev *pdev)
5567 {
5568         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5569         struct net_device *netdev = adapter->netdev;
5570         u32 err;
5571
5572         pci_set_power_state(pdev, PCI_D0);
5573         pci_restore_state(pdev);
5574         /*
5575          * pci_restore_state clears dev->state_saved so call
5576          * pci_save_state to restore it.
5577          */
5578         pci_save_state(pdev);
5579
5580         err = pci_enable_device_mem(pdev);
5581         if (err) {
5582                 e_dev_err("Cannot enable PCI device from suspend\n");
5583                 return err;
5584         }
5585         pci_set_master(pdev);
5586
5587         pci_wake_from_d3(pdev, false);
5588
5589         err = ixgbe_init_interrupt_scheme(adapter);
5590         if (err) {
5591                 e_dev_err("Cannot initialize interrupts for device\n");
5592                 return err;
5593         }
5594
5595         ixgbe_reset(adapter);
5596
5597         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5598
5599         if (netif_running(netdev)) {
5600                 err = ixgbe_open(netdev);
5601                 if (err)
5602                         return err;
5603         }
5604
5605         netif_device_attach(netdev);
5606
5607         return 0;
5608 }
5609 #endif /* CONFIG_PM */
5610
5611 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5612 {
5613         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5614         struct net_device *netdev = adapter->netdev;
5615         struct ixgbe_hw *hw = &adapter->hw;
5616         u32 ctrl, fctrl;
5617         u32 wufc = adapter->wol;
5618 #ifdef CONFIG_PM
5619         int retval = 0;
5620 #endif
5621
5622         netif_device_detach(netdev);
5623
5624         if (netif_running(netdev)) {
5625                 ixgbe_down(adapter);
5626                 ixgbe_free_irq(adapter);
5627                 ixgbe_free_all_tx_resources(adapter);
5628                 ixgbe_free_all_rx_resources(adapter);
5629         }
5630
5631         ixgbe_clear_interrupt_scheme(adapter);
5632 #ifdef CONFIG_DCB
5633         kfree(adapter->ixgbe_ieee_pfc);
5634         kfree(adapter->ixgbe_ieee_ets);
5635 #endif
5636
5637 #ifdef CONFIG_PM
5638         retval = pci_save_state(pdev);
5639         if (retval)
5640                 return retval;
5641
5642 #endif
5643         if (wufc) {
5644                 ixgbe_set_rx_mode(netdev);
5645
5646                 /* turn on all-multi mode if wake on multicast is enabled */
5647                 if (wufc & IXGBE_WUFC_MC) {
5648                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5649                         fctrl |= IXGBE_FCTRL_MPE;
5650                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5651                 }
5652
5653                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5654                 ctrl |= IXGBE_CTRL_GIO_DIS;
5655                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5656
5657                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5658         } else {
5659                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5660                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5661         }
5662
5663         switch (hw->mac.type) {
5664         case ixgbe_mac_82598EB:
5665                 pci_wake_from_d3(pdev, false);
5666                 break;
5667         case ixgbe_mac_82599EB:
5668         case ixgbe_mac_X540:
5669                 pci_wake_from_d3(pdev, !!wufc);
5670                 break;
5671         default:
5672                 break;
5673         }
5674
5675         *enable_wake = !!wufc;
5676
5677         ixgbe_release_hw_control(adapter);
5678
5679         pci_disable_device(pdev);
5680
5681         return 0;
5682 }
5683
5684 #ifdef CONFIG_PM
5685 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5686 {
5687         int retval;
5688         bool wake;
5689
5690         retval = __ixgbe_shutdown(pdev, &wake);
5691         if (retval)
5692                 return retval;
5693
5694         if (wake) {
5695                 pci_prepare_to_sleep(pdev);
5696         } else {
5697                 pci_wake_from_d3(pdev, false);
5698                 pci_set_power_state(pdev, PCI_D3hot);
5699         }
5700
5701         return 0;
5702 }
5703 #endif /* CONFIG_PM */
5704
5705 static void ixgbe_shutdown(struct pci_dev *pdev)
5706 {
5707         bool wake;
5708
5709         __ixgbe_shutdown(pdev, &wake);
5710
5711         if (system_state == SYSTEM_POWER_OFF) {
5712                 pci_wake_from_d3(pdev, wake);
5713                 pci_set_power_state(pdev, PCI_D3hot);
5714         }
5715 }
5716
5717 /**
5718  * ixgbe_update_stats - Update the board statistics counters.
5719  * @adapter: board private structure
5720  **/
5721 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5722 {
5723         struct net_device *netdev = adapter->netdev;
5724         struct ixgbe_hw *hw = &adapter->hw;
5725         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5726         u64 total_mpc = 0;
5727         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5728         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5729         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5730         u64 bytes = 0, packets = 0;
5731
5732         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5733             test_bit(__IXGBE_RESETTING, &adapter->state))
5734                 return;
5735
5736         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5737                 u64 rsc_count = 0;
5738                 u64 rsc_flush = 0;
5739                 for (i = 0; i < 16; i++)
5740                         adapter->hw_rx_no_dma_resources +=
5741                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5742                 for (i = 0; i < adapter->num_rx_queues; i++) {
5743                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5744                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5745                 }
5746                 adapter->rsc_total_count = rsc_count;
5747                 adapter->rsc_total_flush = rsc_flush;
5748         }
5749
5750         for (i = 0; i < adapter->num_rx_queues; i++) {
5751                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5752                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5753                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5754                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5755                 bytes += rx_ring->stats.bytes;
5756                 packets += rx_ring->stats.packets;
5757         }
5758         adapter->non_eop_descs = non_eop_descs;
5759         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5760         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5761         netdev->stats.rx_bytes = bytes;
5762         netdev->stats.rx_packets = packets;
5763
5764         bytes = 0;
5765         packets = 0;
5766         /* gather some stats to the adapter struct that are per queue */
5767         for (i = 0; i < adapter->num_tx_queues; i++) {
5768                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5769                 restart_queue += tx_ring->tx_stats.restart_queue;
5770                 tx_busy += tx_ring->tx_stats.tx_busy;
5771                 bytes += tx_ring->stats.bytes;
5772                 packets += tx_ring->stats.packets;
5773         }
5774         adapter->restart_queue = restart_queue;
5775         adapter->tx_busy = tx_busy;
5776         netdev->stats.tx_bytes = bytes;
5777         netdev->stats.tx_packets = packets;
5778
5779         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5780         for (i = 0; i < 8; i++) {
5781                 /* for packet buffers not used, the register should read 0 */
5782                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5783                 missed_rx += mpc;
5784                 hwstats->mpc[i] += mpc;
5785                 total_mpc += hwstats->mpc[i];
5786                 if (hw->mac.type == ixgbe_mac_82598EB)
5787                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5788                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5789                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5790                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5791                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5792                 switch (hw->mac.type) {
5793                 case ixgbe_mac_82598EB:
5794                         hwstats->pxonrxc[i] +=
5795                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5796                         break;
5797                 case ixgbe_mac_82599EB:
5798                 case ixgbe_mac_X540:
5799                         hwstats->pxonrxc[i] +=
5800                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5801                         break;
5802                 default:
5803                         break;
5804                 }
5805                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5806                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5807         }
5808         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5809         /* work around hardware counting issue */
5810         hwstats->gprc -= missed_rx;
5811
5812         ixgbe_update_xoff_received(adapter);
5813
5814         /* 82598 hardware only has a 32 bit counter in the high register */
5815         switch (hw->mac.type) {
5816         case ixgbe_mac_82598EB:
5817                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5818                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5819                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5820                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5821                 break;
5822         case ixgbe_mac_82599EB:
5823         case ixgbe_mac_X540:
5824                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5825                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5826                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5827                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5828                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5829                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5830                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5831                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5832                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5833 #ifdef IXGBE_FCOE
5834                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5835                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5836                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5837                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5838                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5839                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5840 #endif /* IXGBE_FCOE */
5841                 break;
5842         default:
5843                 break;
5844         }
5845         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5846         hwstats->bprc += bprc;
5847         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5848         if (hw->mac.type == ixgbe_mac_82598EB)
5849                 hwstats->mprc -= bprc;
5850         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5851         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5852         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5853         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5854         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5855         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5856         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5857         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5858         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5859         hwstats->lxontxc += lxon;
5860         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5861         hwstats->lxofftxc += lxoff;
5862         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5863         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5864         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5865         /*
5866          * 82598 errata - tx of flow control packets is included in tx counters
5867          */
5868         xon_off_tot = lxon + lxoff;
5869         hwstats->gptc -= xon_off_tot;
5870         hwstats->mptc -= xon_off_tot;
5871         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5872         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5873         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5874         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5875         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5876         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5877         hwstats->ptc64 -= xon_off_tot;
5878         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5879         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5880         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5881         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5882         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5883         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5884
5885         /* Fill out the OS statistics structure */
5886         netdev->stats.multicast = hwstats->mprc;
5887
5888         /* Rx Errors */
5889         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5890         netdev->stats.rx_dropped = 0;
5891         netdev->stats.rx_length_errors = hwstats->rlec;
5892         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5893         netdev->stats.rx_missed_errors = total_mpc;
5894 }
5895
5896 /**
5897  * ixgbe_watchdog - Timer Call-back
5898  * @data: pointer to adapter cast into an unsigned long
5899  **/
5900 static void ixgbe_watchdog(unsigned long data)
5901 {
5902         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5903         struct ixgbe_hw *hw = &adapter->hw;
5904         u64 eics = 0;
5905         int i;
5906
5907         /*
5908          *  Do the watchdog outside of interrupt context due to the lovely
5909          * delays that some of the newer hardware requires
5910          */
5911
5912         if (test_bit(__IXGBE_DOWN, &adapter->state))
5913                 goto watchdog_short_circuit;
5914
5915         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5916                 /*
5917                  * for legacy and MSI interrupts don't set any bits
5918                  * that are enabled for EIAM, because this operation
5919                  * would set *both* EIMS and EICS for any bit in EIAM
5920                  */
5921                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5922                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5923                 goto watchdog_reschedule;
5924         }
5925
5926         /* get one bit for every active tx/rx interrupt vector */
5927         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5928                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5929                 if (qv->rxr_count || qv->txr_count)
5930                         eics |= ((u64)1 << i);
5931         }
5932
5933         /* Cause software interrupt to ensure rx rings are cleaned */
5934         ixgbe_irq_rearm_queues(adapter, eics);
5935
5936 watchdog_reschedule:
5937         /* Reset the timer */
5938         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5939
5940 watchdog_short_circuit:
5941         schedule_work(&adapter->watchdog_task);
5942 }
5943
5944 /**
5945  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5946  * @work: pointer to work_struct containing our data
5947  **/
5948 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5949 {
5950         struct ixgbe_adapter *adapter = container_of(work,
5951                                                      struct ixgbe_adapter,
5952                                                      multispeed_fiber_task);
5953         struct ixgbe_hw *hw = &adapter->hw;
5954         u32 autoneg;
5955         bool negotiation;
5956
5957         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5958         autoneg = hw->phy.autoneg_advertised;
5959         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5960                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5961         hw->mac.autotry_restart = false;
5962         if (hw->mac.ops.setup_link)
5963                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5964         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5965         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5966 }
5967
5968 /**
5969  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5970  * @work: pointer to work_struct containing our data
5971  **/
5972 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5973 {
5974         struct ixgbe_adapter *adapter = container_of(work,
5975                                                      struct ixgbe_adapter,
5976                                                      sfp_config_module_task);
5977         struct ixgbe_hw *hw = &adapter->hw;
5978         u32 err;
5979
5980         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5981
5982         /* Time for electrical oscillations to settle down */
5983         msleep(100);
5984         err = hw->phy.ops.identify_sfp(hw);
5985
5986         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5987                 e_dev_err("failed to initialize because an unsupported SFP+ "
5988                           "module type was detected.\n");
5989                 e_dev_err("Reload the driver after installing a supported "
5990                           "module.\n");
5991                 unregister_netdev(adapter->netdev);
5992                 return;
5993         }
5994         if (hw->mac.ops.setup_sfp)
5995                 hw->mac.ops.setup_sfp(hw);
5996
5997         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5998                 /* This will also work for DA Twinax connections */
5999                 schedule_work(&adapter->multispeed_fiber_task);
6000         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6001 }
6002
6003 /**
6004  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6005  * @work: pointer to work_struct containing our data
6006  **/
6007 static void ixgbe_fdir_reinit_task(struct work_struct *work)
6008 {
6009         struct ixgbe_adapter *adapter = container_of(work,
6010                                                      struct ixgbe_adapter,
6011                                                      fdir_reinit_task);
6012         struct ixgbe_hw *hw = &adapter->hw;
6013         int i;
6014
6015         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6016                 for (i = 0; i < adapter->num_tx_queues; i++)
6017                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6018                                 &(adapter->tx_ring[i]->state));
6019         } else {
6020                 e_err(probe, "failed to finish FDIR re-initialization, "
6021                       "ignored adding FDIR ATR filters\n");
6022         }
6023         /* Done FDIR Re-initialization, enable transmits */
6024         netif_tx_start_all_queues(adapter->netdev);
6025 }
6026
6027 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6028 {
6029         u32 ssvpc;
6030
6031         /* Do not perform spoof check for 82598 */
6032         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6033                 return;
6034
6035         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6036
6037         /*
6038          * ssvpc register is cleared on read, if zero then no
6039          * spoofed packets in the last interval.
6040          */
6041         if (!ssvpc)
6042                 return;
6043
6044         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6045 }
6046
6047 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6048
6049 /**
6050  * ixgbe_watchdog_task - worker thread to bring link up
6051  * @work: pointer to work_struct containing our data
6052  **/
6053 static void ixgbe_watchdog_task(struct work_struct *work)
6054 {
6055         struct ixgbe_adapter *adapter = container_of(work,
6056                                                      struct ixgbe_adapter,
6057                                                      watchdog_task);
6058         struct net_device *netdev = adapter->netdev;
6059         struct ixgbe_hw *hw = &adapter->hw;
6060         u32 link_speed;
6061         bool link_up;
6062         int i;
6063         struct ixgbe_ring *tx_ring;
6064         int some_tx_pending = 0;
6065
6066         mutex_lock(&ixgbe_watchdog_lock);
6067
6068         link_up = adapter->link_up;
6069         link_speed = adapter->link_speed;
6070
6071         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6072                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6073                 if (link_up) {
6074 #ifdef CONFIG_DCB
6075                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6076                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6077                                         hw->mac.ops.fc_enable(hw, i);
6078                         } else {
6079                                 hw->mac.ops.fc_enable(hw, 0);
6080                         }
6081 #else
6082                         hw->mac.ops.fc_enable(hw, 0);
6083 #endif
6084                 }
6085
6086                 if (link_up ||
6087                     time_after(jiffies, (adapter->link_check_timeout +
6088                                          IXGBE_TRY_LINK_TIMEOUT))) {
6089                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6090                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6091                 }
6092                 adapter->link_up = link_up;
6093                 adapter->link_speed = link_speed;
6094         }
6095
6096         if (link_up) {
6097                 if (!netif_carrier_ok(netdev)) {
6098                         bool flow_rx, flow_tx;
6099
6100                         switch (hw->mac.type) {
6101                         case ixgbe_mac_82598EB: {
6102                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6103                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6104                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6105                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6106                         }
6107                                 break;
6108                         case ixgbe_mac_82599EB:
6109                         case ixgbe_mac_X540: {
6110                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6111                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6112                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6113                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6114                         }
6115                                 break;
6116                         default:
6117                                 flow_tx = false;
6118                                 flow_rx = false;
6119                                 break;
6120                         }
6121
6122                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6123                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6124                                "10 Gbps" :
6125                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6126                                "1 Gbps" :
6127                                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6128                                "100 Mbps" :
6129                                "unknown speed"))),
6130                                ((flow_rx && flow_tx) ? "RX/TX" :
6131                                (flow_rx ? "RX" :
6132                                (flow_tx ? "TX" : "None"))));
6133
6134                         netif_carrier_on(netdev);
6135                 } else {
6136                         /* Force detection of hung controller */
6137                         for (i = 0; i < adapter->num_tx_queues; i++) {
6138                                 tx_ring = adapter->tx_ring[i];
6139                                 set_check_for_tx_hang(tx_ring);
6140                         }
6141                 }
6142         } else {
6143                 adapter->link_up = false;
6144                 adapter->link_speed = 0;
6145                 if (netif_carrier_ok(netdev)) {
6146                         e_info(drv, "NIC Link is Down\n");
6147                         netif_carrier_off(netdev);
6148                 }
6149         }
6150
6151         if (!netif_carrier_ok(netdev)) {
6152                 for (i = 0; i < adapter->num_tx_queues; i++) {
6153                         tx_ring = adapter->tx_ring[i];
6154                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6155                                 some_tx_pending = 1;
6156                                 break;
6157                         }
6158                 }
6159
6160                 if (some_tx_pending) {
6161                         /* We've lost link, so the controller stops DMA,
6162                          * but we've got queued Tx work that's never going
6163                          * to get done, so reset controller to flush Tx.
6164                          * (Do the reset outside of interrupt context).
6165                          */
6166                          schedule_work(&adapter->reset_task);
6167                 }
6168         }
6169
6170         ixgbe_spoof_check(adapter);
6171         ixgbe_update_stats(adapter);
6172         mutex_unlock(&ixgbe_watchdog_lock);
6173 }
6174
6175 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6176                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6177                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6178 {
6179         struct ixgbe_adv_tx_context_desc *context_desc;
6180         unsigned int i;
6181         int err;
6182         struct ixgbe_tx_buffer *tx_buffer_info;
6183         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6184         u32 mss_l4len_idx, l4len;
6185
6186         if (skb_is_gso(skb)) {
6187                 if (skb_header_cloned(skb)) {
6188                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6189                         if (err)
6190                                 return err;
6191                 }
6192                 l4len = tcp_hdrlen(skb);
6193                 *hdr_len += l4len;
6194
6195                 if (protocol == htons(ETH_P_IP)) {
6196                         struct iphdr *iph = ip_hdr(skb);
6197                         iph->tot_len = 0;
6198                         iph->check = 0;
6199                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6200                                                                  iph->daddr, 0,
6201                                                                  IPPROTO_TCP,
6202                                                                  0);
6203                 } else if (skb_is_gso_v6(skb)) {
6204                         ipv6_hdr(skb)->payload_len = 0;
6205                         tcp_hdr(skb)->check =
6206                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6207                                              &ipv6_hdr(skb)->daddr,
6208                                              0, IPPROTO_TCP, 0);
6209                 }
6210
6211                 i = tx_ring->next_to_use;
6212
6213                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6214                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6215
6216                 /* VLAN MACLEN IPLEN */
6217                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6218                         vlan_macip_lens |=
6219                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6220                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6221                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6222                 *hdr_len += skb_network_offset(skb);
6223                 vlan_macip_lens |=
6224                     (skb_transport_header(skb) - skb_network_header(skb));
6225                 *hdr_len +=
6226                     (skb_transport_header(skb) - skb_network_header(skb));
6227                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6228                 context_desc->seqnum_seed = 0;
6229
6230                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6231                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6232                                    IXGBE_ADVTXD_DTYP_CTXT);
6233
6234                 if (protocol == htons(ETH_P_IP))
6235                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6236                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6237                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6238
6239                 /* MSS L4LEN IDX */
6240                 mss_l4len_idx =
6241                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6242                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6243                 /* use index 1 for TSO */
6244                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6245                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6246
6247                 tx_buffer_info->time_stamp = jiffies;
6248                 tx_buffer_info->next_to_watch = i;
6249
6250                 i++;
6251                 if (i == tx_ring->count)
6252                         i = 0;
6253                 tx_ring->next_to_use = i;
6254
6255                 return true;
6256         }
6257         return false;
6258 }
6259
6260 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6261                       __be16 protocol)
6262 {
6263         u32 rtn = 0;
6264
6265         switch (protocol) {
6266         case cpu_to_be16(ETH_P_IP):
6267                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6268                 switch (ip_hdr(skb)->protocol) {
6269                 case IPPROTO_TCP:
6270                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6271                         break;
6272                 case IPPROTO_SCTP:
6273                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6274                         break;
6275                 }
6276                 break;
6277         case cpu_to_be16(ETH_P_IPV6):
6278                 /* XXX what about other V6 headers?? */
6279                 switch (ipv6_hdr(skb)->nexthdr) {
6280                 case IPPROTO_TCP:
6281                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6282                         break;
6283                 case IPPROTO_SCTP:
6284                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6285                         break;
6286                 }
6287                 break;
6288         default:
6289                 if (unlikely(net_ratelimit()))
6290                         e_warn(probe, "partial checksum but proto=%x!\n",
6291                                protocol);
6292                 break;
6293         }
6294
6295         return rtn;
6296 }
6297
6298 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6299                           struct ixgbe_ring *tx_ring,
6300                           struct sk_buff *skb, u32 tx_flags,
6301                           __be16 protocol)
6302 {
6303         struct ixgbe_adv_tx_context_desc *context_desc;
6304         unsigned int i;
6305         struct ixgbe_tx_buffer *tx_buffer_info;
6306         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6307
6308         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6309             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6310                 i = tx_ring->next_to_use;
6311                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6312                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6313
6314                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6315                         vlan_macip_lens |=
6316                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6317                 vlan_macip_lens |= (skb_network_offset(skb) <<
6318                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6319                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6320                         vlan_macip_lens |= (skb_transport_header(skb) -
6321                                             skb_network_header(skb));
6322
6323                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6324                 context_desc->seqnum_seed = 0;
6325
6326                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6327                                     IXGBE_ADVTXD_DTYP_CTXT);
6328
6329                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6330                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6331
6332                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6333                 /* use index zero for tx checksum offload */
6334                 context_desc->mss_l4len_idx = 0;
6335
6336                 tx_buffer_info->time_stamp = jiffies;
6337                 tx_buffer_info->next_to_watch = i;
6338
6339                 i++;
6340                 if (i == tx_ring->count)
6341                         i = 0;
6342                 tx_ring->next_to_use = i;
6343
6344                 return true;
6345         }
6346
6347         return false;
6348 }
6349
6350 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6351                         struct ixgbe_ring *tx_ring,
6352                         struct sk_buff *skb, u32 tx_flags,
6353                         unsigned int first, const u8 hdr_len)
6354 {
6355         struct device *dev = tx_ring->dev;
6356         struct ixgbe_tx_buffer *tx_buffer_info;
6357         unsigned int len;
6358         unsigned int total = skb->len;
6359         unsigned int offset = 0, size, count = 0, i;
6360         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6361         unsigned int f;
6362         unsigned int bytecount = skb->len;
6363         u16 gso_segs = 1;
6364
6365         i = tx_ring->next_to_use;
6366
6367         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6368                 /* excluding fcoe_crc_eof for FCoE */
6369                 total -= sizeof(struct fcoe_crc_eof);
6370
6371         len = min(skb_headlen(skb), total);
6372         while (len) {
6373                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6374                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6375
6376                 tx_buffer_info->length = size;
6377                 tx_buffer_info->mapped_as_page = false;
6378                 tx_buffer_info->dma = dma_map_single(dev,
6379                                                      skb->data + offset,
6380                                                      size, DMA_TO_DEVICE);
6381                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6382                         goto dma_error;
6383                 tx_buffer_info->time_stamp = jiffies;
6384                 tx_buffer_info->next_to_watch = i;
6385
6386                 len -= size;
6387                 total -= size;
6388                 offset += size;
6389                 count++;
6390
6391                 if (len) {
6392                         i++;
6393                         if (i == tx_ring->count)
6394                                 i = 0;
6395                 }
6396         }
6397
6398         for (f = 0; f < nr_frags; f++) {
6399                 struct skb_frag_struct *frag;
6400
6401                 frag = &skb_shinfo(skb)->frags[f];
6402                 len = min((unsigned int)frag->size, total);
6403                 offset = frag->page_offset;
6404
6405                 while (len) {
6406                         i++;
6407                         if (i == tx_ring->count)
6408                                 i = 0;
6409
6410                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6411                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6412
6413                         tx_buffer_info->length = size;
6414                         tx_buffer_info->dma = dma_map_page(dev,
6415                                                            frag->page,
6416                                                            offset, size,
6417                                                            DMA_TO_DEVICE);
6418                         tx_buffer_info->mapped_as_page = true;
6419                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6420                                 goto dma_error;
6421                         tx_buffer_info->time_stamp = jiffies;
6422                         tx_buffer_info->next_to_watch = i;
6423
6424                         len -= size;
6425                         total -= size;
6426                         offset += size;
6427                         count++;
6428                 }
6429                 if (total == 0)
6430                         break;
6431         }
6432
6433         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6434                 gso_segs = skb_shinfo(skb)->gso_segs;
6435 #ifdef IXGBE_FCOE
6436         /* adjust for FCoE Sequence Offload */
6437         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6438                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6439                                         skb_shinfo(skb)->gso_size);
6440 #endif /* IXGBE_FCOE */
6441         bytecount += (gso_segs - 1) * hdr_len;
6442
6443         /* multiply data chunks by size of headers */
6444         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6445         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6446         tx_ring->tx_buffer_info[i].skb = skb;
6447         tx_ring->tx_buffer_info[first].next_to_watch = i;
6448
6449         return count;
6450
6451 dma_error:
6452         e_dev_err("TX DMA map failed\n");
6453
6454         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6455         tx_buffer_info->dma = 0;
6456         tx_buffer_info->time_stamp = 0;
6457         tx_buffer_info->next_to_watch = 0;
6458         if (count)
6459                 count--;
6460
6461         /* clear timestamp and dma mappings for remaining portion of packet */
6462         while (count--) {
6463                 if (i == 0)
6464                         i += tx_ring->count;
6465                 i--;
6466                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6467                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6468         }
6469
6470         return 0;
6471 }
6472
6473 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6474                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6475 {
6476         union ixgbe_adv_tx_desc *tx_desc = NULL;
6477         struct ixgbe_tx_buffer *tx_buffer_info;
6478         u32 olinfo_status = 0, cmd_type_len = 0;
6479         unsigned int i;
6480         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6481
6482         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6483
6484         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6485
6486         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6487                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6488
6489         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6490                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6491
6492                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6493                                  IXGBE_ADVTXD_POPTS_SHIFT;
6494
6495                 /* use index 1 context for tso */
6496                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6497                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6498                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6499                                          IXGBE_ADVTXD_POPTS_SHIFT;
6500
6501         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6502                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6503                                  IXGBE_ADVTXD_POPTS_SHIFT;
6504
6505         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6506                 olinfo_status |= IXGBE_ADVTXD_CC;
6507                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6508                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6509                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6510         }
6511
6512         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6513
6514         i = tx_ring->next_to_use;
6515         while (count--) {
6516                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6517                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6518                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6519                 tx_desc->read.cmd_type_len =
6520                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6521                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6522                 i++;
6523                 if (i == tx_ring->count)
6524                         i = 0;
6525         }
6526
6527         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6528
6529         /*
6530          * Force memory writes to complete before letting h/w
6531          * know there are new descriptors to fetch.  (Only
6532          * applicable for weak-ordered memory model archs,
6533          * such as IA-64).
6534          */
6535         wmb();
6536
6537         tx_ring->next_to_use = i;
6538         writel(i, tx_ring->tail);
6539 }
6540
6541 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6542                       u32 tx_flags, __be16 protocol)
6543 {
6544         struct ixgbe_q_vector *q_vector = ring->q_vector;
6545         union ixgbe_atr_hash_dword input = { .dword = 0 };
6546         union ixgbe_atr_hash_dword common = { .dword = 0 };
6547         union {
6548                 unsigned char *network;
6549                 struct iphdr *ipv4;
6550                 struct ipv6hdr *ipv6;
6551         } hdr;
6552         struct tcphdr *th;
6553         __be16 vlan_id;
6554
6555         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6556         if (!q_vector)
6557                 return;
6558
6559         /* do nothing if sampling is disabled */
6560         if (!ring->atr_sample_rate)
6561                 return;
6562
6563         ring->atr_count++;
6564
6565         /* snag network header to get L4 type and address */
6566         hdr.network = skb_network_header(skb);
6567
6568         /* Currently only IPv4/IPv6 with TCP is supported */
6569         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6570              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6571             (protocol != __constant_htons(ETH_P_IP) ||
6572              hdr.ipv4->protocol != IPPROTO_TCP))
6573                 return;
6574
6575         th = tcp_hdr(skb);
6576
6577         /* skip this packet since the socket is closing */
6578         if (th->fin)
6579                 return;
6580
6581         /* sample on all syn packets or once every atr sample count */
6582         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6583                 return;
6584
6585         /* reset sample count */
6586         ring->atr_count = 0;
6587
6588         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6589
6590         /*
6591          * src and dst are inverted, think how the receiver sees them
6592          *
6593          * The input is broken into two sections, a non-compressed section
6594          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6595          * is XORed together and stored in the compressed dword.
6596          */
6597         input.formatted.vlan_id = vlan_id;
6598
6599         /*
6600          * since src port and flex bytes occupy the same word XOR them together
6601          * and write the value to source port portion of compressed dword
6602          */
6603         if (vlan_id)
6604                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6605         else
6606                 common.port.src ^= th->dest ^ protocol;
6607         common.port.dst ^= th->source;
6608
6609         if (protocol == __constant_htons(ETH_P_IP)) {
6610                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6611                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6612         } else {
6613                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6614                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6615                              hdr.ipv6->saddr.s6_addr32[1] ^
6616                              hdr.ipv6->saddr.s6_addr32[2] ^
6617                              hdr.ipv6->saddr.s6_addr32[3] ^
6618                              hdr.ipv6->daddr.s6_addr32[0] ^
6619                              hdr.ipv6->daddr.s6_addr32[1] ^
6620                              hdr.ipv6->daddr.s6_addr32[2] ^
6621                              hdr.ipv6->daddr.s6_addr32[3];
6622         }
6623
6624         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6625         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6626                                               input, common, ring->queue_index);
6627 }
6628
6629 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6630 {
6631         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6632         /* Herbert's original patch had:
6633          *  smp_mb__after_netif_stop_queue();
6634          * but since that doesn't exist yet, just open code it. */
6635         smp_mb();
6636
6637         /* We need to check again in a case another CPU has just
6638          * made room available. */
6639         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6640                 return -EBUSY;
6641
6642         /* A reprieve! - use start_queue because it doesn't call schedule */
6643         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6644         ++tx_ring->tx_stats.restart_queue;
6645         return 0;
6646 }
6647
6648 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6649 {
6650         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6651                 return 0;
6652         return __ixgbe_maybe_stop_tx(tx_ring, size);
6653 }
6654
6655 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6656 {
6657         struct ixgbe_adapter *adapter = netdev_priv(dev);
6658         int txq = smp_processor_id();
6659 #ifdef IXGBE_FCOE
6660         __be16 protocol;
6661
6662         protocol = vlan_get_protocol(skb);
6663
6664         if ((protocol == htons(ETH_P_FCOE)) ||
6665             (protocol == htons(ETH_P_FIP))) {
6666                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6667                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6668                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6669                         return txq;
6670 #ifdef CONFIG_IXGBE_DCB
6671                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6672                         txq = adapter->fcoe.up;
6673                         return txq;
6674 #endif
6675                 }
6676         }
6677 #endif
6678
6679         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6680                 while (unlikely(txq >= dev->real_num_tx_queues))
6681                         txq -= dev->real_num_tx_queues;
6682                 return txq;
6683         }
6684
6685         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6686                 if (skb->priority == TC_PRIO_CONTROL)
6687                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6688                 else
6689                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6690                                >> 13;
6691                 return txq;
6692         }
6693
6694         return skb_tx_hash(dev, skb);
6695 }
6696
6697 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6698                           struct ixgbe_adapter *adapter,
6699                           struct ixgbe_ring *tx_ring)
6700 {
6701         unsigned int first;
6702         unsigned int tx_flags = 0;
6703         u8 hdr_len = 0;
6704         int tso;
6705         int count = 0;
6706         unsigned int f;
6707         __be16 protocol;
6708
6709         protocol = vlan_get_protocol(skb);
6710
6711         if (vlan_tx_tag_present(skb)) {
6712                 tx_flags |= vlan_tx_tag_get(skb);
6713                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6714                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6715                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6716                 }
6717                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6718                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6719         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6720                    skb->priority != TC_PRIO_CONTROL) {
6721                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6722                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6723                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6724         }
6725
6726 #ifdef IXGBE_FCOE
6727         /* for FCoE with DCB, we force the priority to what
6728          * was specified by the switch */
6729         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6730             (protocol == htons(ETH_P_FCOE) ||
6731              protocol == htons(ETH_P_FIP))) {
6732 #ifdef CONFIG_IXGBE_DCB
6733                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6734                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6735                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6736                         tx_flags |= ((adapter->fcoe.up << 13)
6737                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6738                 }
6739 #endif
6740                 /* flag for FCoE offloads */
6741                 if (protocol == htons(ETH_P_FCOE))
6742                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6743         }
6744 #endif
6745
6746         /* four things can cause us to need a context descriptor */
6747         if (skb_is_gso(skb) ||
6748             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6749             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6750             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6751                 count++;
6752
6753         count += TXD_USE_COUNT(skb_headlen(skb));
6754         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6755                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6756
6757         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6758                 tx_ring->tx_stats.tx_busy++;
6759                 return NETDEV_TX_BUSY;
6760         }
6761
6762         first = tx_ring->next_to_use;
6763         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6764 #ifdef IXGBE_FCOE
6765                 /* setup tx offload for FCoE */
6766                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6767                 if (tso < 0) {
6768                         dev_kfree_skb_any(skb);
6769                         return NETDEV_TX_OK;
6770                 }
6771                 if (tso)
6772                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6773 #endif /* IXGBE_FCOE */
6774         } else {
6775                 if (protocol == htons(ETH_P_IP))
6776                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6777                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6778                                 protocol);
6779                 if (tso < 0) {
6780                         dev_kfree_skb_any(skb);
6781                         return NETDEV_TX_OK;
6782                 }
6783
6784                 if (tso)
6785                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6786                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6787                                        protocol) &&
6788                          (skb->ip_summed == CHECKSUM_PARTIAL))
6789                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6790         }
6791
6792         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6793         if (count) {
6794                 /* add the ATR filter if ATR is on */
6795                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6796                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6797                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6798                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6799
6800         } else {
6801                 dev_kfree_skb_any(skb);
6802                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6803                 tx_ring->next_to_use = first;
6804         }
6805
6806         return NETDEV_TX_OK;
6807 }
6808
6809 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6810 {
6811         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6812         struct ixgbe_ring *tx_ring;
6813
6814         tx_ring = adapter->tx_ring[skb->queue_mapping];
6815         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6816 }
6817
6818 /**
6819  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6820  * @netdev: network interface device structure
6821  * @p: pointer to an address structure
6822  *
6823  * Returns 0 on success, negative on failure
6824  **/
6825 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6826 {
6827         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6828         struct ixgbe_hw *hw = &adapter->hw;
6829         struct sockaddr *addr = p;
6830
6831         if (!is_valid_ether_addr(addr->sa_data))
6832                 return -EADDRNOTAVAIL;
6833
6834         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6835         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6836
6837         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6838                             IXGBE_RAH_AV);
6839
6840         return 0;
6841 }
6842
6843 static int
6844 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6845 {
6846         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6847         struct ixgbe_hw *hw = &adapter->hw;
6848         u16 value;
6849         int rc;
6850
6851         if (prtad != hw->phy.mdio.prtad)
6852                 return -EINVAL;
6853         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6854         if (!rc)
6855                 rc = value;
6856         return rc;
6857 }
6858
6859 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6860                             u16 addr, u16 value)
6861 {
6862         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6863         struct ixgbe_hw *hw = &adapter->hw;
6864
6865         if (prtad != hw->phy.mdio.prtad)
6866                 return -EINVAL;
6867         return hw->phy.ops.write_reg(hw, addr, devad, value);
6868 }
6869
6870 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6871 {
6872         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6873
6874         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6875 }
6876
6877 /**
6878  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6879  * netdev->dev_addrs
6880  * @netdev: network interface device structure
6881  *
6882  * Returns non-zero on failure
6883  **/
6884 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6885 {
6886         int err = 0;
6887         struct ixgbe_adapter *adapter = netdev_priv(dev);
6888         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6889
6890         if (is_valid_ether_addr(mac->san_addr)) {
6891                 rtnl_lock();
6892                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6893                 rtnl_unlock();
6894         }
6895         return err;
6896 }
6897
6898 /**
6899  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6900  * netdev->dev_addrs
6901  * @netdev: network interface device structure
6902  *
6903  * Returns non-zero on failure
6904  **/
6905 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6906 {
6907         int err = 0;
6908         struct ixgbe_adapter *adapter = netdev_priv(dev);
6909         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6910
6911         if (is_valid_ether_addr(mac->san_addr)) {
6912                 rtnl_lock();
6913                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6914                 rtnl_unlock();
6915         }
6916         return err;
6917 }
6918
6919 #ifdef CONFIG_NET_POLL_CONTROLLER
6920 /*
6921  * Polling 'interrupt' - used by things like netconsole to send skbs
6922  * without having to re-enable interrupts. It's not called while
6923  * the interrupt routine is executing.
6924  */
6925 static void ixgbe_netpoll(struct net_device *netdev)
6926 {
6927         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6928         int i;
6929
6930         /* if interface is down do nothing */
6931         if (test_bit(__IXGBE_DOWN, &adapter->state))
6932                 return;
6933
6934         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6935         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6936                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6937                 for (i = 0; i < num_q_vectors; i++) {
6938                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6939                         ixgbe_msix_clean_many(0, q_vector);
6940                 }
6941         } else {
6942                 ixgbe_intr(adapter->pdev->irq, netdev);
6943         }
6944         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6945 }
6946 #endif
6947
6948 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6949                                                    struct rtnl_link_stats64 *stats)
6950 {
6951         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6952         int i;
6953
6954         rcu_read_lock();
6955         for (i = 0; i < adapter->num_rx_queues; i++) {
6956                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6957                 u64 bytes, packets;
6958                 unsigned int start;
6959
6960                 if (ring) {
6961                         do {
6962                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6963                                 packets = ring->stats.packets;
6964                                 bytes   = ring->stats.bytes;
6965                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6966                         stats->rx_packets += packets;
6967                         stats->rx_bytes   += bytes;
6968                 }
6969         }
6970
6971         for (i = 0; i < adapter->num_tx_queues; i++) {
6972                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6973                 u64 bytes, packets;
6974                 unsigned int start;
6975
6976                 if (ring) {
6977                         do {
6978                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6979                                 packets = ring->stats.packets;
6980                                 bytes   = ring->stats.bytes;
6981                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6982                         stats->tx_packets += packets;
6983                         stats->tx_bytes   += bytes;
6984                 }
6985         }
6986         rcu_read_unlock();
6987         /* following stats updated by ixgbe_watchdog_task() */
6988         stats->multicast        = netdev->stats.multicast;
6989         stats->rx_errors        = netdev->stats.rx_errors;
6990         stats->rx_length_errors = netdev->stats.rx_length_errors;
6991         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6992         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6993         return stats;
6994 }
6995
6996
6997 static const struct net_device_ops ixgbe_netdev_ops = {
6998         .ndo_open               = ixgbe_open,
6999         .ndo_stop               = ixgbe_close,
7000         .ndo_start_xmit         = ixgbe_xmit_frame,
7001         .ndo_select_queue       = ixgbe_select_queue,
7002         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7003         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7004         .ndo_validate_addr      = eth_validate_addr,
7005         .ndo_set_mac_address    = ixgbe_set_mac,
7006         .ndo_change_mtu         = ixgbe_change_mtu,
7007         .ndo_tx_timeout         = ixgbe_tx_timeout,
7008         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7009         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7010         .ndo_do_ioctl           = ixgbe_ioctl,
7011         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7012         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7013         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7014         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7015         .ndo_get_stats64        = ixgbe_get_stats64,
7016 #ifdef CONFIG_NET_POLL_CONTROLLER
7017         .ndo_poll_controller    = ixgbe_netpoll,
7018 #endif
7019 #ifdef IXGBE_FCOE
7020         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7021         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7022         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7023         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7024         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7025 #endif /* IXGBE_FCOE */
7026 };
7027
7028 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7029                            const struct ixgbe_info *ii)
7030 {
7031 #ifdef CONFIG_PCI_IOV
7032         struct ixgbe_hw *hw = &adapter->hw;
7033         int err;
7034
7035         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7036                 return;
7037
7038         /* The 82599 supports up to 64 VFs per physical function
7039          * but this implementation limits allocation to 63 so that
7040          * basic networking resources are still available to the
7041          * physical function
7042          */
7043         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7044         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7045         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7046         if (err) {
7047                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7048                 goto err_novfs;
7049         }
7050         /* If call to enable VFs succeeded then allocate memory
7051          * for per VF control structures.
7052          */
7053         adapter->vfinfo =
7054                 kcalloc(adapter->num_vfs,
7055                         sizeof(struct vf_data_storage), GFP_KERNEL);
7056         if (adapter->vfinfo) {
7057                 /* Now that we're sure SR-IOV is enabled
7058                  * and memory allocated set up the mailbox parameters
7059                  */
7060                 ixgbe_init_mbx_params_pf(hw);
7061                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7062                        sizeof(hw->mbx.ops));
7063
7064                 /* Disable RSC when in SR-IOV mode */
7065                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7066                                      IXGBE_FLAG2_RSC_ENABLED);
7067                 return;
7068         }
7069
7070         /* Oh oh */
7071         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7072               "SRIOV disabled\n");
7073         pci_disable_sriov(adapter->pdev);
7074
7075 err_novfs:
7076         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7077         adapter->num_vfs = 0;
7078 #endif /* CONFIG_PCI_IOV */
7079 }
7080
7081 /**
7082  * ixgbe_probe - Device Initialization Routine
7083  * @pdev: PCI device information struct
7084  * @ent: entry in ixgbe_pci_tbl
7085  *
7086  * Returns 0 on success, negative on failure
7087  *
7088  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7089  * The OS initialization, configuring of the adapter private structure,
7090  * and a hardware reset occur.
7091  **/
7092 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7093                                  const struct pci_device_id *ent)
7094 {
7095         struct net_device *netdev;
7096         struct ixgbe_adapter *adapter = NULL;
7097         struct ixgbe_hw *hw;
7098         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7099         static int cards_found;
7100         int i, err, pci_using_dac;
7101         u8 part_str[IXGBE_PBANUM_LENGTH];
7102         unsigned int indices = num_possible_cpus();
7103 #ifdef IXGBE_FCOE
7104         u16 device_caps;
7105 #endif
7106         u32 eec;
7107
7108         /* Catch broken hardware that put the wrong VF device ID in
7109          * the PCIe SR-IOV capability.
7110          */
7111         if (pdev->is_virtfn) {
7112                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7113                      pci_name(pdev), pdev->vendor, pdev->device);
7114                 return -EINVAL;
7115         }
7116
7117         err = pci_enable_device_mem(pdev);
7118         if (err)
7119                 return err;
7120
7121         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7122             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7123                 pci_using_dac = 1;
7124         } else {
7125                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7126                 if (err) {
7127                         err = dma_set_coherent_mask(&pdev->dev,
7128                                                     DMA_BIT_MASK(32));
7129                         if (err) {
7130                                 dev_err(&pdev->dev,
7131                                         "No usable DMA configuration, aborting\n");
7132                                 goto err_dma;
7133                         }
7134                 }
7135                 pci_using_dac = 0;
7136         }
7137
7138         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7139                                            IORESOURCE_MEM), ixgbe_driver_name);
7140         if (err) {
7141                 dev_err(&pdev->dev,
7142                         "pci_request_selected_regions failed 0x%x\n", err);
7143                 goto err_pci_reg;
7144         }
7145
7146         pci_enable_pcie_error_reporting(pdev);
7147
7148         pci_set_master(pdev);
7149         pci_save_state(pdev);
7150
7151         if (ii->mac == ixgbe_mac_82598EB)
7152                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7153         else
7154                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7155
7156         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7157 #ifdef IXGBE_FCOE
7158         indices += min_t(unsigned int, num_possible_cpus(),
7159                          IXGBE_MAX_FCOE_INDICES);
7160 #endif
7161         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7162         if (!netdev) {
7163                 err = -ENOMEM;
7164                 goto err_alloc_etherdev;
7165         }
7166
7167         SET_NETDEV_DEV(netdev, &pdev->dev);
7168
7169         adapter = netdev_priv(netdev);
7170         pci_set_drvdata(pdev, adapter);
7171
7172         adapter->netdev = netdev;
7173         adapter->pdev = pdev;
7174         hw = &adapter->hw;
7175         hw->back = adapter;
7176         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7177
7178         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7179                               pci_resource_len(pdev, 0));
7180         if (!hw->hw_addr) {
7181                 err = -EIO;
7182                 goto err_ioremap;
7183         }
7184
7185         for (i = 1; i <= 5; i++) {
7186                 if (pci_resource_len(pdev, i) == 0)
7187                         continue;
7188         }
7189
7190         netdev->netdev_ops = &ixgbe_netdev_ops;
7191         ixgbe_set_ethtool_ops(netdev);
7192         netdev->watchdog_timeo = 5 * HZ;
7193         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7194
7195         adapter->bd_number = cards_found;
7196
7197         /* Setup hw api */
7198         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7199         hw->mac.type  = ii->mac;
7200
7201         /* EEPROM */
7202         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7203         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7204         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7205         if (!(eec & (1 << 8)))
7206                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7207
7208         /* PHY */
7209         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7210         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7211         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7212         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7213         hw->phy.mdio.mmds = 0;
7214         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7215         hw->phy.mdio.dev = netdev;
7216         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7217         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7218
7219         /* set up this timer and work struct before calling get_invariants
7220          * which might start the timer
7221          */
7222         init_timer(&adapter->sfp_timer);
7223         adapter->sfp_timer.function = ixgbe_sfp_timer;
7224         adapter->sfp_timer.data = (unsigned long) adapter;
7225
7226         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7227
7228         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7229         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7230
7231         /* a new SFP+ module arrival, called from GPI SDP2 context */
7232         INIT_WORK(&adapter->sfp_config_module_task,
7233                   ixgbe_sfp_config_module_task);
7234
7235         ii->get_invariants(hw);
7236
7237         /* setup the private structure */
7238         err = ixgbe_sw_init(adapter);
7239         if (err)
7240                 goto err_sw_init;
7241
7242         /* Make it possible the adapter to be woken up via WOL */
7243         switch (adapter->hw.mac.type) {
7244         case ixgbe_mac_82599EB:
7245         case ixgbe_mac_X540:
7246                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7247                 break;
7248         default:
7249                 break;
7250         }
7251
7252         /*
7253          * If there is a fan on this device and it has failed log the
7254          * failure.
7255          */
7256         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7257                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7258                 if (esdp & IXGBE_ESDP_SDP1)
7259                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7260         }
7261
7262         /* reset_hw fills in the perm_addr as well */
7263         hw->phy.reset_if_overtemp = true;
7264         err = hw->mac.ops.reset_hw(hw);
7265         hw->phy.reset_if_overtemp = false;
7266         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7267             hw->mac.type == ixgbe_mac_82598EB) {
7268                 /*
7269                  * Start a kernel thread to watch for a module to arrive.
7270                  * Only do this for 82598, since 82599 will generate
7271                  * interrupts on module arrival.
7272                  */
7273                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7274                 mod_timer(&adapter->sfp_timer,
7275                           round_jiffies(jiffies + (2 * HZ)));
7276                 err = 0;
7277         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7278                 e_dev_err("failed to initialize because an unsupported SFP+ "
7279                           "module type was detected.\n");
7280                 e_dev_err("Reload the driver after installing a supported "
7281                           "module.\n");
7282                 goto err_sw_init;
7283         } else if (err) {
7284                 e_dev_err("HW Init failed: %d\n", err);
7285                 goto err_sw_init;
7286         }
7287
7288         ixgbe_probe_vf(adapter, ii);
7289
7290         netdev->features = NETIF_F_SG |
7291                            NETIF_F_IP_CSUM |
7292                            NETIF_F_HW_VLAN_TX |
7293                            NETIF_F_HW_VLAN_RX |
7294                            NETIF_F_HW_VLAN_FILTER;
7295
7296         netdev->features |= NETIF_F_IPV6_CSUM;
7297         netdev->features |= NETIF_F_TSO;
7298         netdev->features |= NETIF_F_TSO6;
7299         netdev->features |= NETIF_F_GRO;
7300
7301         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7302                 netdev->features |= NETIF_F_SCTP_CSUM;
7303
7304         netdev->vlan_features |= NETIF_F_TSO;
7305         netdev->vlan_features |= NETIF_F_TSO6;
7306         netdev->vlan_features |= NETIF_F_IP_CSUM;
7307         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7308         netdev->vlan_features |= NETIF_F_SG;
7309
7310         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7311                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7312                                     IXGBE_FLAG_DCB_ENABLED);
7313         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7314                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7315
7316 #ifdef CONFIG_IXGBE_DCB
7317         netdev->dcbnl_ops = &dcbnl_ops;
7318 #endif
7319
7320 #ifdef IXGBE_FCOE
7321         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7322                 if (hw->mac.ops.get_device_caps) {
7323                         hw->mac.ops.get_device_caps(hw, &device_caps);
7324                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7325                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7326                 }
7327         }
7328         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7329                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7330                 netdev->vlan_features |= NETIF_F_FSO;
7331                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7332         }
7333 #endif /* IXGBE_FCOE */
7334         if (pci_using_dac) {
7335                 netdev->features |= NETIF_F_HIGHDMA;
7336                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7337         }
7338
7339         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7340                 netdev->features |= NETIF_F_LRO;
7341
7342         /* make sure the EEPROM is good */
7343         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7344                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7345                 err = -EIO;
7346                 goto err_eeprom;
7347         }
7348
7349         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7350         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7351
7352         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7353                 e_dev_err("invalid MAC address\n");
7354                 err = -EIO;
7355                 goto err_eeprom;
7356         }
7357
7358         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7359         if (hw->mac.ops.disable_tx_laser &&
7360             ((hw->phy.multispeed_fiber) ||
7361              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7362               (hw->mac.type == ixgbe_mac_82599EB))))
7363                 hw->mac.ops.disable_tx_laser(hw);
7364
7365         init_timer(&adapter->watchdog_timer);
7366         adapter->watchdog_timer.function = ixgbe_watchdog;
7367         adapter->watchdog_timer.data = (unsigned long)adapter;
7368
7369         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7370         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7371
7372         err = ixgbe_init_interrupt_scheme(adapter);
7373         if (err)
7374                 goto err_sw_init;
7375
7376         switch (pdev->device) {
7377         case IXGBE_DEV_ID_82599_SFP:
7378                 /* Only this subdevice supports WOL */
7379                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7380                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7381                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7382                 break;
7383         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7384                 /* All except this subdevice support WOL */
7385                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7386                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7387                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7388                 break;
7389         case IXGBE_DEV_ID_82599_KX4:
7390                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7391                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7392                 break;
7393         default:
7394                 adapter->wol = 0;
7395                 break;
7396         }
7397         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7398
7399         /* pick up the PCI bus settings for reporting later */
7400         hw->mac.ops.get_bus_info(hw);
7401
7402         /* print bus type/speed/width info */
7403         e_dev_info("(PCI Express:%s:%s) %pM\n",
7404                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7405                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7406                     "Unknown"),
7407                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7408                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7409                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7410                     "Unknown"),
7411                    netdev->dev_addr);
7412
7413         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7414         if (err)
7415                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7416         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7417                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7418                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7419                            part_str);
7420         else
7421                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7422                            hw->mac.type, hw->phy.type, part_str);
7423
7424         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7425                 e_dev_warn("PCI-Express bandwidth available for this card is "
7426                            "not sufficient for optimal performance.\n");
7427                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7428                            "is required.\n");
7429         }
7430
7431         /* save off EEPROM version number */
7432         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7433
7434         /* reset the hardware with the new settings */
7435         err = hw->mac.ops.start_hw(hw);
7436
7437         if (err == IXGBE_ERR_EEPROM_VERSION) {
7438                 /* We are running on a pre-production device, log a warning */
7439                 e_dev_warn("This device is a pre-production adapter/LOM. "
7440                            "Please be aware there may be issues associated "
7441                            "with your hardware.  If you are experiencing "
7442                            "problems please contact your Intel or hardware "
7443                            "representative who provided you with this "
7444                            "hardware.\n");
7445         }
7446         strcpy(netdev->name, "eth%d");
7447         err = register_netdev(netdev);
7448         if (err)
7449                 goto err_register;
7450
7451         /* carrier off reporting is important to ethtool even BEFORE open */
7452         netif_carrier_off(netdev);
7453
7454         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7455             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7456                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7457
7458         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7459                 INIT_WORK(&adapter->check_overtemp_task,
7460                           ixgbe_check_overtemp_task);
7461 #ifdef CONFIG_IXGBE_DCA
7462         if (dca_add_requester(&pdev->dev) == 0) {
7463                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7464                 ixgbe_setup_dca(adapter);
7465         }
7466 #endif
7467         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7468                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7469                 for (i = 0; i < adapter->num_vfs; i++)
7470                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7471         }
7472
7473         /* add san mac addr to netdev */
7474         ixgbe_add_sanmac_netdev(netdev);
7475
7476         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7477         cards_found++;
7478         return 0;
7479
7480 err_register:
7481         ixgbe_release_hw_control(adapter);
7482         ixgbe_clear_interrupt_scheme(adapter);
7483 err_sw_init:
7484 err_eeprom:
7485         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7486                 ixgbe_disable_sriov(adapter);
7487         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7488         del_timer_sync(&adapter->sfp_timer);
7489         cancel_work_sync(&adapter->sfp_task);
7490         cancel_work_sync(&adapter->multispeed_fiber_task);
7491         cancel_work_sync(&adapter->sfp_config_module_task);
7492         iounmap(hw->hw_addr);
7493 err_ioremap:
7494         free_netdev(netdev);
7495 err_alloc_etherdev:
7496         pci_release_selected_regions(pdev,
7497                                      pci_select_bars(pdev, IORESOURCE_MEM));
7498 err_pci_reg:
7499 err_dma:
7500         pci_disable_device(pdev);
7501         return err;
7502 }
7503
7504 /**
7505  * ixgbe_remove - Device Removal Routine
7506  * @pdev: PCI device information struct
7507  *
7508  * ixgbe_remove is called by the PCI subsystem to alert the driver
7509  * that it should release a PCI device.  The could be caused by a
7510  * Hot-Plug event, or because the driver is going to be removed from
7511  * memory.
7512  **/
7513 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7514 {
7515         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7516         struct net_device *netdev = adapter->netdev;
7517
7518         set_bit(__IXGBE_DOWN, &adapter->state);
7519
7520         /*
7521          * The timers may be rescheduled, so explicitly disable them
7522          * from being rescheduled.
7523          */
7524         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7525         del_timer_sync(&adapter->watchdog_timer);
7526         del_timer_sync(&adapter->sfp_timer);
7527
7528         cancel_work_sync(&adapter->watchdog_task);
7529         cancel_work_sync(&adapter->sfp_task);
7530         cancel_work_sync(&adapter->multispeed_fiber_task);
7531         cancel_work_sync(&adapter->sfp_config_module_task);
7532         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7533             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7534                 cancel_work_sync(&adapter->fdir_reinit_task);
7535         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7536                 cancel_work_sync(&adapter->check_overtemp_task);
7537
7538 #ifdef CONFIG_IXGBE_DCA
7539         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7540                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7541                 dca_remove_requester(&pdev->dev);
7542                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7543         }
7544
7545 #endif
7546 #ifdef IXGBE_FCOE
7547         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7548                 ixgbe_cleanup_fcoe(adapter);
7549
7550 #endif /* IXGBE_FCOE */
7551
7552         /* remove the added san mac */
7553         ixgbe_del_sanmac_netdev(netdev);
7554
7555         if (netdev->reg_state == NETREG_REGISTERED)
7556                 unregister_netdev(netdev);
7557
7558         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7559                 ixgbe_disable_sriov(adapter);
7560
7561         ixgbe_clear_interrupt_scheme(adapter);
7562
7563         ixgbe_release_hw_control(adapter);
7564
7565         iounmap(adapter->hw.hw_addr);
7566         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7567                                      IORESOURCE_MEM));
7568
7569         e_dev_info("complete\n");
7570
7571         free_netdev(netdev);
7572
7573         pci_disable_pcie_error_reporting(pdev);
7574
7575         pci_disable_device(pdev);
7576 }
7577
7578 /**
7579  * ixgbe_io_error_detected - called when PCI error is detected
7580  * @pdev: Pointer to PCI device
7581  * @state: The current pci connection state
7582  *
7583  * This function is called after a PCI bus error affecting
7584  * this device has been detected.
7585  */
7586 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7587                                                 pci_channel_state_t state)
7588 {
7589         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7590         struct net_device *netdev = adapter->netdev;
7591
7592         netif_device_detach(netdev);
7593
7594         if (state == pci_channel_io_perm_failure)
7595                 return PCI_ERS_RESULT_DISCONNECT;
7596
7597         if (netif_running(netdev))
7598                 ixgbe_down(adapter);
7599         pci_disable_device(pdev);
7600
7601         /* Request a slot reset. */
7602         return PCI_ERS_RESULT_NEED_RESET;
7603 }
7604
7605 /**
7606  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7607  * @pdev: Pointer to PCI device
7608  *
7609  * Restart the card from scratch, as if from a cold-boot.
7610  */
7611 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7612 {
7613         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7614         pci_ers_result_t result;
7615         int err;
7616
7617         if (pci_enable_device_mem(pdev)) {
7618                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7619                 result = PCI_ERS_RESULT_DISCONNECT;
7620         } else {
7621                 pci_set_master(pdev);
7622                 pci_restore_state(pdev);
7623                 pci_save_state(pdev);
7624
7625                 pci_wake_from_d3(pdev, false);
7626
7627                 ixgbe_reset(adapter);
7628                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7629                 result = PCI_ERS_RESULT_RECOVERED;
7630         }
7631
7632         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7633         if (err) {
7634                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7635                           "failed 0x%0x\n", err);
7636                 /* non-fatal, continue */
7637         }
7638
7639         return result;
7640 }
7641
7642 /**
7643  * ixgbe_io_resume - called when traffic can start flowing again.
7644  * @pdev: Pointer to PCI device
7645  *
7646  * This callback is called when the error recovery driver tells us that
7647  * its OK to resume normal operation.
7648  */
7649 static void ixgbe_io_resume(struct pci_dev *pdev)
7650 {
7651         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7652         struct net_device *netdev = adapter->netdev;
7653
7654         if (netif_running(netdev)) {
7655                 if (ixgbe_up(adapter)) {
7656                         e_info(probe, "ixgbe_up failed after reset\n");
7657                         return;
7658                 }
7659         }
7660
7661         netif_device_attach(netdev);
7662 }
7663
7664 static struct pci_error_handlers ixgbe_err_handler = {
7665         .error_detected = ixgbe_io_error_detected,
7666         .slot_reset = ixgbe_io_slot_reset,
7667         .resume = ixgbe_io_resume,
7668 };
7669
7670 static struct pci_driver ixgbe_driver = {
7671         .name     = ixgbe_driver_name,
7672         .id_table = ixgbe_pci_tbl,
7673         .probe    = ixgbe_probe,
7674         .remove   = __devexit_p(ixgbe_remove),
7675 #ifdef CONFIG_PM
7676         .suspend  = ixgbe_suspend,
7677         .resume   = ixgbe_resume,
7678 #endif
7679         .shutdown = ixgbe_shutdown,
7680         .err_handler = &ixgbe_err_handler
7681 };
7682
7683 /**
7684  * ixgbe_init_module - Driver Registration Routine
7685  *
7686  * ixgbe_init_module is the first routine called when the driver is
7687  * loaded. All it does is register with the PCI subsystem.
7688  **/
7689 static int __init ixgbe_init_module(void)
7690 {
7691         int ret;
7692         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7693         pr_info("%s\n", ixgbe_copyright);
7694
7695 #ifdef CONFIG_IXGBE_DCA
7696         dca_register_notify(&dca_notifier);
7697 #endif
7698
7699         ret = pci_register_driver(&ixgbe_driver);
7700         return ret;
7701 }
7702
7703 module_init(ixgbe_init_module);
7704
7705 /**
7706  * ixgbe_exit_module - Driver Exit Cleanup Routine
7707  *
7708  * ixgbe_exit_module is called just before the driver is removed
7709  * from memory.
7710  **/
7711 static void __exit ixgbe_exit_module(void)
7712 {
7713 #ifdef CONFIG_IXGBE_DCA
7714         dca_unregister_notify(&dca_notifier);
7715 #endif
7716         pci_unregister_driver(&ixgbe_driver);
7717         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7718 }
7719
7720 #ifdef CONFIG_IXGBE_DCA
7721 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7722                             void *p)
7723 {
7724         int ret_val;
7725
7726         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7727                                          __ixgbe_notify_dca);
7728
7729         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7730 }
7731
7732 #endif /* CONFIG_IXGBE_DCA */
7733
7734 module_exit(ixgbe_exit_module);
7735
7736 /* ixgbe_main.c */