drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 604                                       struct ixgbe_tx_buffer
 605                                       *tx_buffer_info)
 606 {
 607         if (tx_buffer_info->dma) {
 608                 if (tx_buffer_info->mapped_as_page)
 609                         dma_unmap_page(&adapter->pdev->dev,
 610                                        tx_buffer_info->dma,
 611                                        tx_buffer_info->length,
 612                                        DMA_TO_DEVICE);
 613                 else
 614                         dma_unmap_single(&adapter->pdev->dev,
 615                                          tx_buffer_info->dma,
 616                                          tx_buffer_info->length,
 617                                          DMA_TO_DEVICE);
 618                 tx_buffer_info->dma = 0;
 619         }
 620         if (tx_buffer_info->skb) {
 621                 dev_kfree_skb_any(tx_buffer_info->skb);
 622                 tx_buffer_info->skb = NULL;
 623         }
 624         tx_buffer_info->time_stamp = 0;
 625         /* tx_buffer_info must be completely set up in the transmit path */
 626 }
 627
 628 /**
 629  * ixgbe_tx_xon_state - check the tx ring xon state
 630  * @adapter: the ixgbe adapter
 631  * @tx_ring: the corresponding tx_ring
 632  *
 633  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 634  * corresponding TC of this tx_ring when checking TFCS.
 635  *
 636  * Returns : true if in xon state (currently not paused)
 637  */
 638 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 639                                       struct ixgbe_ring *tx_ring)
 640 {
 641         u32 txoff = IXGBE_TFCS_TXOFF;
 642
 643 #ifdef CONFIG_IXGBE_DCB
 644         if (adapter->dcb_cfg.pfc_mode_enable) {
 645                 int tc;
 646                 int reg_idx = tx_ring->reg_idx;
 647                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 648
 649                 switch (adapter->hw.mac.type) {
 650                 case ixgbe_mac_82598EB:
 651                         tc = reg_idx >> 2;
 652                         txoff = IXGBE_TFCS_TXOFF0;
 653                         break;
 654                 case ixgbe_mac_82599EB:
 655                         tc = 0;
 656                         txoff = IXGBE_TFCS_TXOFF;
 657                         if (dcb_i == 8) {
 658                                 /* TC0, TC1 */
 659                                 tc = reg_idx >> 5;
 660                                 if (tc == 2) /* TC2, TC3 */
 661                                         tc += (reg_idx - 64) >> 4;
 662                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 663                                         tc += 1 + ((reg_idx - 96) >> 3);
 664                         } else if (dcb_i == 4) {
 665                                 /* TC0, TC1 */
 666                                 tc = reg_idx >> 6;
 667                                 if (tc == 1) {
 668                                         tc += (reg_idx - 64) >> 5;
 669                                         if (tc == 2) /* TC2, TC3 */
 670                                                 tc += (reg_idx - 96) >> 4;
 671                                 }
 672                         }
 673                         break;
 674                 default:
 675                         tc = 0;
 676                 }
 677                 txoff <<= tc;
 678         }
 679 #endif
 680         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 681 }
 682
 683 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 684                                        struct ixgbe_ring *tx_ring,
 685                                        unsigned int eop)
 686 {
 687         struct ixgbe_hw *hw = &adapter->hw;
 688
 689         /* Detect a transmit hang in hardware, this serializes the
 690          * check with the clearing of time_stamp and movement of eop */
 691         adapter->detect_tx_hung = false;
 692         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 693             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 694             ixgbe_tx_xon_state(adapter, tx_ring)) {
 695                 /* detected Tx unit hang */
 696                 union ixgbe_adv_tx_desc *tx_desc;
 697                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 698                 e_err(drv, "Detected Tx Unit Hang\n"
 699                       "  Tx Queue             <%d>\n"
 700                       "  TDH, TDT             <%x>, <%x>\n"
 701                       "  next_to_use          <%x>\n"
 702                       "  next_to_clean        <%x>\n"
 703                       "tx_buffer_info[next_to_clean]\n"
 704                       "  time_stamp           <%lx>\n"
 705                       "  jiffies              <%lx>\n",
 706                       tx_ring->queue_index,
 707                       IXGBE_READ_REG(hw, tx_ring->head),
 708                       IXGBE_READ_REG(hw, tx_ring->tail),
 709                       tx_ring->next_to_use, eop,
 710                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 711                 return true;
 712         }
 713
 714         return false;
 715 }
 716
 717 #define IXGBE_MAX_TXD_PWR       14
 718 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 719
 720 /* Tx Descriptors needed, worst case */
 721 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 722                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 723 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 724         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 725
 726 static void ixgbe_tx_timeout(struct net_device *netdev);
 727
 728 /**
 729  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 730  * @q_vector: structure containing interrupt and ring information
 731  * @tx_ring: tx ring to clean
 732  **/
 733 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 734                                struct ixgbe_ring *tx_ring)
 735 {
 736         struct ixgbe_adapter *adapter = q_vector->adapter;
 737         struct net_device *netdev = adapter->netdev;
 738         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 739         struct ixgbe_tx_buffer *tx_buffer_info;
 740         unsigned int i, eop, count = 0;
 741         unsigned int total_bytes = 0, total_packets = 0;
 742
 743         i = tx_ring->next_to_clean;
 744         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 745         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 746
 747         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 748                (count < tx_ring->work_limit)) {
 749                 bool cleaned = false;
 750                 rmb(); /* read buffer_info after eop_desc */
 751                 for ( ; !cleaned; count++) {
 752                         struct sk_buff *skb;
 753                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 754                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 755                         cleaned = (i == eop);
 756                         skb = tx_buffer_info->skb;
 757
 758                         if (cleaned && skb) {
 759                                 unsigned int segs, bytecount;
 760                                 unsigned int hlen = skb_headlen(skb);
 761
 762                                 /* gso_segs is currently only valid for tcp */
 763                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 764 #ifdef IXGBE_FCOE
 765                                 /* adjust for FCoE Sequence Offload */
 766                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 767                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 768                                     skb_is_gso(skb)) {
 769                                         hlen = skb_transport_offset(skb) +
 770                                                 sizeof(struct fc_frame_header) +
 771                                                 sizeof(struct fcoe_crc_eof);
 772                                         segs = DIV_ROUND_UP(skb->len - hlen,
 773                                                 skb_shinfo(skb)->gso_size);
 774                                 }
 775 #endif /* IXGBE_FCOE */
 776                                 /* multiply data chunks by size of headers */
 777                                 bytecount = ((segs - 1) * hlen) + skb->len;
 778                                 total_packets += segs;
 779                                 total_bytes += bytecount;
 780                         }
 781
 782                         ixgbe_unmap_and_free_tx_resource(adapter,
 783                                                          tx_buffer_info);
 784
 785                         tx_desc->wb.status = 0;
 786
 787                         i++;
 788                         if (i == tx_ring->count)
 789                                 i = 0;
 790                 }
 791
 792                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 793                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 794         }
 795
 796         tx_ring->next_to_clean = i;
 797
 798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 799         if (unlikely(count && netif_carrier_ok(netdev) &&
 800                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 801                 /* Make sure that anybody stopping the queue after this
 802                  * sees the new next_to_clean.
 803                  */
 804                 smp_mb();
 805                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 806                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 807                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 808                         ++tx_ring->restart_queue;
 809                 }
 810         }
 811
 812         if (adapter->detect_tx_hung) {
 813                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 814                         /* schedule immediate reset if we believe we hung */
 815                         e_info(probe, "tx hang %d detected, resetting "
 816                                "adapter\n", adapter->tx_timeout_count + 1);
 817                         ixgbe_tx_timeout(adapter->netdev);
 818                 }
 819         }
 820
 821         /* re-arm the interrupt */
 822         if (count >= tx_ring->work_limit)
 823                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 824
 825         tx_ring->total_bytes += total_bytes;
 826         tx_ring->total_packets += total_packets;
 827         tx_ring->stats.packets += total_packets;
 828         tx_ring->stats.bytes += total_bytes;
 829         return count < tx_ring->work_limit;
 830 }
 831
 832 #ifdef CONFIG_IXGBE_DCA
 833 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 834                                 struct ixgbe_ring *rx_ring)
 835 {
 836         u32 rxctrl;
 837         int cpu = get_cpu();
 838         int q = rx_ring->reg_idx;
 839
 840         if (rx_ring->cpu != cpu) {
 841                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 842                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 843                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 844                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 845                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 846                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 847                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 848                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 849                 }
 850                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 851                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 852                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 853                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 854                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 855                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 856                 rx_ring->cpu = cpu;
 857         }
 858         put_cpu();
 859 }
 860
 861 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 862                                 struct ixgbe_ring *tx_ring)
 863 {
 864         u32 txctrl;
 865         int cpu = get_cpu();
 866         int q = tx_ring->reg_idx;
 867         struct ixgbe_hw *hw = &adapter->hw;
 868
 869         if (tx_ring->cpu != cpu) {
 870                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 871                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 872                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 873                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 874                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 875                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 876                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 877                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 878                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 879                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 880                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 881                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 882                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 883                 }
 884                 tx_ring->cpu = cpu;
 885         }
 886         put_cpu();
 887 }
 888
 889 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 890 {
 891         int i;
 892
 893         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 894                 return;
 895
 896         /* always use CB2 mode, difference is masked in the CB driver */
 897         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 898
 899         for (i = 0; i < adapter->num_tx_queues; i++) {
 900                 adapter->tx_ring[i]->cpu = -1;
 901                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 902         }
 903         for (i = 0; i < adapter->num_rx_queues; i++) {
 904                 adapter->rx_ring[i]->cpu = -1;
 905                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 906         }
 907 }
 908
 909 static int __ixgbe_notify_dca(struct device *dev, void *data)
 910 {
 911         struct net_device *netdev = dev_get_drvdata(dev);
 912         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 913         unsigned long event = *(unsigned long *)data;
 914
 915         switch (event) {
 916         case DCA_PROVIDER_ADD:
 917                 /* if we're already enabled, don't do it again */
 918                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 919                         break;
 920                 if (dca_add_requester(dev) == 0) {
 921                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 922                         ixgbe_setup_dca(adapter);
 923                         break;
 924                 }
 925                 /* Fall Through since DCA is disabled. */
 926         case DCA_PROVIDER_REMOVE:
 927                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 928                         dca_remove_requester(dev);
 929                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 930                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 931                 }
 932                 break;
 933         }
 934
 935         return 0;
 936 }
 937
 938 #endif /* CONFIG_IXGBE_DCA */
 939 /**
 940  * ixgbe_receive_skb - Send a completed packet up the stack
 941  * @adapter: board private structure
 942  * @skb: packet to send up
 943  * @status: hardware indication of status of receive
 944  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 945  * @rx_desc: rx descriptor
 946  **/
 947 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 948                               struct sk_buff *skb, u8 status,
 949                               struct ixgbe_ring *ring,
 950                               union ixgbe_adv_rx_desc *rx_desc)
 951 {
 952         struct ixgbe_adapter *adapter = q_vector->adapter;
 953         struct napi_struct *napi = &q_vector->napi;
 954         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 955         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 956
 957         if (is_vlan && (tag & VLAN_VID_MASK))
 958                 __vlan_hwaccel_put_tag(skb, tag);
 959
 960         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 961                 napi_gro_receive(napi, skb);
 962         else
 963                 netif_rx(skb);
 964 }
 965
 966 /**
 967  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 968  * @adapter: address of board private structure
 969  * @status_err: hardware indication of status of receive
 970  * @skb: skb currently being received and modified
 971  **/
 972 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 973                                      union ixgbe_adv_rx_desc *rx_desc,
 974                                      struct sk_buff *skb)
 975 {
 976         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 977
 978         skb_checksum_none_assert(skb);
 979
 980         /* Rx csum disabled */
 981         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 982                 return;
 983
 984         /* if IP and error */
 985         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 986             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 987                 adapter->hw_csum_rx_error++;
 988                 return;
 989         }
 990
 991         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 992                 return;
 993
 994         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 995                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 996
 997                 /*
 998                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 999                  * checksum errors.
1000                  */
1001                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1002                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1003                         return;
1004
1005                 adapter->hw_csum_rx_error++;
1006                 return;
1007         }
1008
1009         /* It must be a TCP or UDP packet with a valid checksum */
1010         skb->ip_summed = CHECKSUM_UNNECESSARY;
1011 }
1012
1013 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1014                                          struct ixgbe_ring *rx_ring, u32 val)
1015 {
1016         /*
1017          * Force memory writes to complete before letting h/w
1018          * know there are new descriptors to fetch.  (Only
1019          * applicable for weak-ordered memory model archs,
1020          * such as IA-64).
1021          */
1022         wmb();
1023         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1024 }
1025
1026 /**
1027  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1028  * @adapter: address of board private structure
1029  **/
1030 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1031                             struct ixgbe_ring *rx_ring,
1032                             int cleaned_count)
1033 {
1034         struct net_device *netdev = adapter->netdev;
1035         struct pci_dev *pdev = adapter->pdev;
1036         union ixgbe_adv_rx_desc *rx_desc;
1037         struct ixgbe_rx_buffer *bi;
1038         unsigned int i;
1039         unsigned int bufsz = rx_ring->rx_buf_len;
1040
1041         i = rx_ring->next_to_use;
1042         bi = &rx_ring->rx_buffer_info[i];
1043
1044         while (cleaned_count--) {
1045                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1046
1047                 if (!bi->page_dma &&
1048                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1049                         if (!bi->page) {
1050                                 bi->page = netdev_alloc_page(netdev);
1051                                 if (!bi->page) {
1052                                         adapter->alloc_rx_page_failed++;
1053                                         goto no_buffers;
1054                                 }
1055                                 bi->page_offset = 0;
1056                         } else {
1057                                 /* use a half page if we're re-using */
1058                                 bi->page_offset ^= (PAGE_SIZE / 2);
1059                         }
1060
1061                         bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1062                                                     bi->page_offset,
1063                                                     (PAGE_SIZE / 2),
1064                                                     DMA_FROM_DEVICE);
1065                 }
1066
1067                 if (!bi->skb) {
1068                         struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1069                                                                         bufsz);
1070                         bi->skb = skb;
1071
1072                         if (!skb) {
1073                                 adapter->alloc_rx_buff_failed++;
1074                                 goto no_buffers;
1075                         }
1076                         /* initialize queue mapping */
1077                         skb_record_rx_queue(skb, rx_ring->queue_index);
1078                 }
1079
1080                 if (!bi->dma) {
1081                         bi->dma = dma_map_single(&pdev->dev,
1082                                                  bi->skb->data,
1083                                                  rx_ring->rx_buf_len,
1084                                                  DMA_FROM_DEVICE);
1085                 }
1086                 /* Refresh the desc even if buffer_addrs didn't change because
1087                  * each write-back erases this info. */
1088                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1089                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1090                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1091                 } else {
1092                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1093                         rx_desc->read.hdr_addr = 0;
1094                 }
1095
1096                 i++;
1097                 if (i == rx_ring->count)
1098                         i = 0;
1099                 bi = &rx_ring->rx_buffer_info[i];
1100         }
1101
1102 no_buffers:
1103         if (rx_ring->next_to_use != i) {
1104                 rx_ring->next_to_use = i;
1105                 if (i-- == 0)
1106                         i = (rx_ring->count - 1);
1107
1108                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1109         }
1110 }
1111
1112 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1113 {
1114         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1115 }
1116
1117 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1118 {
1119         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1120 }
1121
1122 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1123 {
1124         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1125                 IXGBE_RXDADV_RSCCNT_MASK) >>
1126                 IXGBE_RXDADV_RSCCNT_SHIFT;
1127 }
1128
1129 /**
1130  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1131  * @skb: pointer to the last skb in the rsc queue
1132  * @count: pointer to number of packets coalesced in this context
1133  *
1134  * This function changes a queue full of hw rsc buffers into a completed
1135  * packet.  It uses the ->prev pointers to find the first packet and then
1136  * turns it into the frag list owner.
1137  **/
1138 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1139                                                         u64 *count)
1140 {
1141         unsigned int frag_list_size = 0;
1142
1143         while (skb->prev) {
1144                 struct sk_buff *prev = skb->prev;
1145                 frag_list_size += skb->len;
1146                 skb->prev = NULL;
1147                 skb = prev;
1148                 *count += 1;
1149         }
1150
1151         skb_shinfo(skb)->frag_list = skb->next;
1152         skb->next = NULL;
1153         skb->len += frag_list_size;
1154         skb->data_len += frag_list_size;
1155         skb->truesize += frag_list_size;
1156         return skb;
1157 }
1158
1159 struct ixgbe_rsc_cb {
1160         dma_addr_t dma;
1161         bool delay_unmap;
1162 };
1163
1164 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1165
1166 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1167                                struct ixgbe_ring *rx_ring,
1168                                int *work_done, int work_to_do)
1169 {
1170         struct ixgbe_adapter *adapter = q_vector->adapter;
1171         struct net_device *netdev = adapter->netdev;
1172         struct pci_dev *pdev = adapter->pdev;
1173         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1174         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1175         struct sk_buff *skb;
1176         unsigned int i, rsc_count = 0;
1177         u32 len, staterr;
1178         u16 hdr_info;
1179         bool cleaned = false;
1180         int cleaned_count = 0;
1181         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1182 #ifdef IXGBE_FCOE
1183         int ddp_bytes = 0;
1184 #endif /* IXGBE_FCOE */
1185
1186         i = rx_ring->next_to_clean;
1187         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1188         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1189         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1190
1191         while (staterr & IXGBE_RXD_STAT_DD) {
1192                 u32 upper_len = 0;
1193                 if (*work_done >= work_to_do)
1194                         break;
1195                 (*work_done)++;
1196
1197                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1198                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1199                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1200                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1201                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1202                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1203                         if ((len > IXGBE_RX_HDR_SIZE) ||
1204                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1205                                 len = IXGBE_RX_HDR_SIZE;
1206                 } else {
1207                         len = le16_to_cpu(rx_desc->wb.upper.length);
1208                 }
1209
1210                 cleaned = true;
1211                 skb = rx_buffer_info->skb;
1212                 prefetch(skb->data);
1213                 rx_buffer_info->skb = NULL;
1214
1215                 if (rx_buffer_info->dma) {
1216                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1217                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1218                                  (!(skb->prev))) {
1219                                 /*
1220                                  * When HWRSC is enabled, delay unmapping
1221                                  * of the first packet. It carries the
1222                                  * header information, HW may still
1223                                  * access the header after the writeback.
1224                                  * Only unmap it when EOP is reached
1225                                  */
1226                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1227                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1228                         } else {
1229                                 dma_unmap_single(&pdev->dev,
1230                                                  rx_buffer_info->dma,
1231                                                  rx_ring->rx_buf_len,
1232                                                  DMA_FROM_DEVICE);
1233                         }
1234                         rx_buffer_info->dma = 0;
1235                         skb_put(skb, len);
1236                 }
1237
1238                 if (upper_len) {
1239                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1240                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1241                         rx_buffer_info->page_dma = 0;
1242                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1243                                            rx_buffer_info->page,
1244                                            rx_buffer_info->page_offset,
1245                                            upper_len);
1246
1247                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1248                             (page_count(rx_buffer_info->page) != 1))
1249                                 rx_buffer_info->page = NULL;
1250                         else
1251                                 get_page(rx_buffer_info->page);
1252
1253                         skb->len += upper_len;
1254                         skb->data_len += upper_len;
1255                         skb->truesize += upper_len;
1256                 }
1257
1258                 i++;
1259                 if (i == rx_ring->count)
1260                         i = 0;
1261
1262                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1263                 prefetch(next_rxd);
1264                 cleaned_count++;
1265
1266                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1267                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1268
1269                 if (rsc_count) {
1270                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1271                                      IXGBE_RXDADV_NEXTP_SHIFT;
1272                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1273                 } else {
1274                         next_buffer = &rx_ring->rx_buffer_info[i];
1275                 }
1276
1277                 if (staterr & IXGBE_RXD_STAT_EOP) {
1278                         if (skb->prev)
1279                                 skb = ixgbe_transform_rsc_queue(skb,
1280                                                                 &(rx_ring->rsc_count));
1281                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1282                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1283                                         dma_unmap_single(&pdev->dev,
1284                                                          IXGBE_RSC_CB(skb)->dma,
1285                                                          rx_ring->rx_buf_len,
1286                                                          DMA_FROM_DEVICE);
1287                                         IXGBE_RSC_CB(skb)->dma = 0;
1288                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1289                                 }
1290                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1291                                         rx_ring->rsc_count +=
1292                                                 skb_shinfo(skb)->nr_frags;
1293                                 else
1294                                         rx_ring->rsc_count++;
1295                                 rx_ring->rsc_flush++;
1296                         }
1297                         rx_ring->stats.packets++;
1298                         rx_ring->stats.bytes += skb->len;
1299                 } else {
1300                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1301                                 rx_buffer_info->skb = next_buffer->skb;
1302                                 rx_buffer_info->dma = next_buffer->dma;
1303                                 next_buffer->skb = skb;
1304                                 next_buffer->dma = 0;
1305                         } else {
1306                                 skb->next = next_buffer->skb;
1307                                 skb->next->prev = skb;
1308                         }
1309                         rx_ring->non_eop_descs++;
1310                         goto next_desc;
1311                 }
1312
1313                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1314                         dev_kfree_skb_irq(skb);
1315                         goto next_desc;
1316                 }
1317
1318                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1319
1320                 /* probably a little skewed due to removing CRC */
1321                 total_rx_bytes += skb->len;
1322                 total_rx_packets++;
1323
1324                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1325 #ifdef IXGBE_FCOE
1326                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1327                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1328                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1329                         if (!ddp_bytes)
1330                                 goto next_desc;
1331                 }
1332 #endif /* IXGBE_FCOE */
1333                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1334
1335 next_desc:
1336                 rx_desc->wb.upper.status_error = 0;
1337
1338                 /* return some buffers to hardware, one at a time is too slow */
1339                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1340                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1341                         cleaned_count = 0;
1342                 }
1343
1344                 /* use prefetched values */
1345                 rx_desc = next_rxd;
1346                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1347
1348                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1349         }
1350
1351         rx_ring->next_to_clean = i;
1352         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1353
1354         if (cleaned_count)
1355                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1356
1357 #ifdef IXGBE_FCOE
1358         /* include DDPed FCoE data */
1359         if (ddp_bytes > 0) {
1360                 unsigned int mss;
1361
1362                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1363                         sizeof(struct fc_frame_header) -
1364                         sizeof(struct fcoe_crc_eof);
1365                 if (mss > 512)
1366                         mss &= ~511;
1367                 total_rx_bytes += ddp_bytes;
1368                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1369         }
1370 #endif /* IXGBE_FCOE */
1371
1372         rx_ring->total_packets += total_rx_packets;
1373         rx_ring->total_bytes += total_rx_bytes;
1374         netdev->stats.rx_bytes += total_rx_bytes;
1375         netdev->stats.rx_packets += total_rx_packets;
1376
1377         return cleaned;
1378 }
1379
1380 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1381 /**
1382  * ixgbe_configure_msix - Configure MSI-X hardware
1383  * @adapter: board private structure
1384  *
1385  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1386  * interrupts.
1387  **/
1388 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1389 {
1390         struct ixgbe_q_vector *q_vector;
1391         int i, j, q_vectors, v_idx, r_idx;
1392         u32 mask;
1393
1394         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1395
1396         /*
1397          * Populate the IVAR table and set the ITR values to the
1398          * corresponding register.
1399          */
1400         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1401                 q_vector = adapter->q_vector[v_idx];
1402                 /* XXX for_each_set_bit(...) */
1403                 r_idx = find_first_bit(q_vector->rxr_idx,
1404                                        adapter->num_rx_queues);
1405
1406                 for (i = 0; i < q_vector->rxr_count; i++) {
1407                         j = adapter->rx_ring[r_idx]->reg_idx;
1408                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1409                         r_idx = find_next_bit(q_vector->rxr_idx,
1410                                               adapter->num_rx_queues,
1411                                               r_idx + 1);
1412                 }
1413                 r_idx = find_first_bit(q_vector->txr_idx,
1414                                        adapter->num_tx_queues);
1415
1416                 for (i = 0; i < q_vector->txr_count; i++) {
1417                         j = adapter->tx_ring[r_idx]->reg_idx;
1418                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1419                         r_idx = find_next_bit(q_vector->txr_idx,
1420                                               adapter->num_tx_queues,
1421                                               r_idx + 1);
1422                 }
1423
1424                 if (q_vector->txr_count && !q_vector->rxr_count)
1425                         /* tx only */
1426                         q_vector->eitr = adapter->tx_eitr_param;
1427                 else if (q_vector->rxr_count)
1428                         /* rx or mixed */
1429                         q_vector->eitr = adapter->rx_eitr_param;
1430
1431                 ixgbe_write_eitr(q_vector);
1432                 /* If Flow Director is enabled, set interrupt affinity */
1433                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1434                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1435                         /*
1436                          * Allocate the affinity_hint cpumask, assign the mask
1437                          * for this vector, and set our affinity_hint for
1438                          * this irq.
1439                          */
1440                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1441                                                GFP_KERNEL))
1442                                 return;
1443                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1444                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1445                                               q_vector->affinity_mask);
1446                 }
1447         }
1448
1449         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1450                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1451                                v_idx);
1452         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1453                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1454         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1455
1456         /* set up to autoclear timer, and the vectors */
1457         mask = IXGBE_EIMS_ENABLE_MASK;
1458         if (adapter->num_vfs)
1459                 mask &= ~(IXGBE_EIMS_OTHER |
1460                           IXGBE_EIMS_MAILBOX |
1461                           IXGBE_EIMS_LSC);
1462         else
1463                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1464         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1465 }
1466
1467 enum latency_range {
1468         lowest_latency = 0,
1469         low_latency = 1,
1470         bulk_latency = 2,
1471         latency_invalid = 255
1472 };
1473
1474 /**
1475  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1476  * @adapter: pointer to adapter
1477  * @eitr: eitr setting (ints per sec) to give last timeslice
1478  * @itr_setting: current throttle rate in ints/second
1479  * @packets: the number of packets during this measurement interval
1480  * @bytes: the number of bytes during this measurement interval
1481  *
1482  *      Stores a new ITR value based on packets and byte
1483  *      counts during the last interrupt.  The advantage of per interrupt
1484  *      computation is faster updates and more accurate ITR for the current
1485  *      traffic pattern.  Constants in this function were computed
1486  *      based on theoretical maximum wire speed and thresholds were set based
1487  *      on testing data as well as attempting to minimize response time
1488  *      while increasing bulk throughput.
1489  *      this functionality is controlled by the InterruptThrottleRate module
1490  *      parameter (see ixgbe_param.c)
1491  **/
1492 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1493                            u32 eitr, u8 itr_setting,
1494                            int packets, int bytes)
1495 {
1496         unsigned int retval = itr_setting;
1497         u32 timepassed_us;
1498         u64 bytes_perint;
1499
1500         if (packets == 0)
1501                 goto update_itr_done;
1502
1503
1504         /* simple throttlerate management
1505          *    0-20MB/s lowest (100000 ints/s)
1506          *   20-100MB/s low   (20000 ints/s)
1507          *  100-1249MB/s bulk (8000 ints/s)
1508          */
1509         /* what was last interrupt timeslice? */
1510         timepassed_us = 1000000/eitr;
1511         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1512
1513         switch (itr_setting) {
1514         case lowest_latency:
1515                 if (bytes_perint > adapter->eitr_low)
1516                         retval = low_latency;
1517                 break;
1518         case low_latency:
1519                 if (bytes_perint > adapter->eitr_high)
1520                         retval = bulk_latency;
1521                 else if (bytes_perint <= adapter->eitr_low)
1522                         retval = lowest_latency;
1523                 break;
1524         case bulk_latency:
1525                 if (bytes_perint <= adapter->eitr_high)
1526                         retval = low_latency;
1527                 break;
1528         }
1529
1530 update_itr_done:
1531         return retval;
1532 }
1533
1534 /**
1535  * ixgbe_write_eitr - write EITR register in hardware specific way
1536  * @q_vector: structure containing interrupt and ring information
1537  *
1538  * This function is made to be called by ethtool and by the driver
1539  * when it needs to update EITR registers at runtime.  Hardware
1540  * specific quirks/differences are taken care of here.
1541  */
1542 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1543 {
1544         struct ixgbe_adapter *adapter = q_vector->adapter;
1545         struct ixgbe_hw *hw = &adapter->hw;
1546         int v_idx = q_vector->v_idx;
1547         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1548
1549         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1550                 /* must write high and low 16 bits to reset counter */
1551                 itr_reg |= (itr_reg << 16);
1552         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1553                 /*
1554                  * 82599 can support a value of zero, so allow it for
1555                  * max interrupt rate, but there is an errata where it can
1556                  * not be zero with RSC
1557                  */
1558                 if (itr_reg == 8 &&
1559                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1560                         itr_reg = 0;
1561
1562                 /*
1563                  * set the WDIS bit to not clear the timer bits and cause an
1564                  * immediate assertion of the interrupt
1565                  */
1566                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1567         }
1568         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1569 }
1570
1571 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1572 {
1573         struct ixgbe_adapter *adapter = q_vector->adapter;
1574         u32 new_itr;
1575         u8 current_itr, ret_itr;
1576         int i, r_idx;
1577         struct ixgbe_ring *rx_ring, *tx_ring;
1578
1579         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1580         for (i = 0; i < q_vector->txr_count; i++) {
1581                 tx_ring = adapter->tx_ring[r_idx];
1582                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1583                                            q_vector->tx_itr,
1584                                            tx_ring->total_packets,
1585                                            tx_ring->total_bytes);
1586                 /* if the result for this queue would decrease interrupt
1587                  * rate for this vector then use that result */
1588                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1589                                     q_vector->tx_itr - 1 : ret_itr);
1590                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1591                                       r_idx + 1);
1592         }
1593
1594         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1595         for (i = 0; i < q_vector->rxr_count; i++) {
1596                 rx_ring = adapter->rx_ring[r_idx];
1597                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1598                                            q_vector->rx_itr,
1599                                            rx_ring->total_packets,
1600                                            rx_ring->total_bytes);
1601                 /* if the result for this queue would decrease interrupt
1602                  * rate for this vector then use that result */
1603                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1604                                     q_vector->rx_itr - 1 : ret_itr);
1605                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1606                                       r_idx + 1);
1607         }
1608
1609         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1610
1611         switch (current_itr) {
1612         /* counts and packets in update_itr are dependent on these numbers */
1613         case lowest_latency:
1614                 new_itr = 100000;
1615                 break;
1616         case low_latency:
1617                 new_itr = 20000; /* aka hwitr = ~200 */
1618                 break;
1619         case bulk_latency:
1620         default:
1621                 new_itr = 8000;
1622                 break;
1623         }
1624
1625         if (new_itr != q_vector->eitr) {
1626                 /* do an exponential smoothing */
1627                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1628
1629                 /* save the algorithm value here, not the smoothed one */
1630                 q_vector->eitr = new_itr;
1631
1632                 ixgbe_write_eitr(q_vector);
1633         }
1634 }
1635
1636 /**
1637  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1638  * @work: pointer to work_struct containing our data
1639  **/
1640 static void ixgbe_check_overtemp_task(struct work_struct *work)
1641 {
1642         struct ixgbe_adapter *adapter = container_of(work,
1643                                                      struct ixgbe_adapter,
1644                                                      check_overtemp_task);
1645         struct ixgbe_hw *hw = &adapter->hw;
1646         u32 eicr = adapter->interrupt_event;
1647
1648         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1649                 return;
1650
1651         switch (hw->device_id) {
1652         case IXGBE_DEV_ID_82599_T3_LOM: {
1653                 u32 autoneg;
1654                 bool link_up = false;
1655
1656                 if (hw->mac.ops.check_link)
1657                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1658
1659                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1660                     (eicr & IXGBE_EICR_LSC))
1661                         /* Check if this is due to overtemp */
1662                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1663                                 break;
1664                 return;
1665         }
1666         default:
1667                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1668                         return;
1669                 break;
1670         }
1671         e_crit(drv,
1672                "Network adapter has been stopped because it has over heated. "
1673                "Restart the computer. If the problem persists, "
1674                "power off the system and replace the adapter\n");
1675         /* write to clear the interrupt */
1676         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1677 }
1678
1679 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1680 {
1681         struct ixgbe_hw *hw = &adapter->hw;
1682
1683         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1684             (eicr & IXGBE_EICR_GPI_SDP1)) {
1685                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1686                 /* write to clear the interrupt */
1687                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1688         }
1689 }
1690
1691 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1692 {
1693         struct ixgbe_hw *hw = &adapter->hw;
1694
1695         if (eicr & IXGBE_EICR_GPI_SDP1) {
1696                 /* Clear the interrupt */
1697                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1698                 schedule_work(&adapter->multispeed_fiber_task);
1699         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1700                 /* Clear the interrupt */
1701                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1702                 schedule_work(&adapter->sfp_config_module_task);
1703         } else {
1704                 /* Interrupt isn't for us... */
1705                 return;
1706         }
1707 }
1708
1709 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1710 {
1711         struct ixgbe_hw *hw = &adapter->hw;
1712
1713         adapter->lsc_int++;
1714         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1715         adapter->link_check_timeout = jiffies;
1716         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1717                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1718                 IXGBE_WRITE_FLUSH(hw);
1719                 schedule_work(&adapter->watchdog_task);
1720         }
1721 }
1722
1723 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1724 {
1725         struct net_device *netdev = data;
1726         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1727         struct ixgbe_hw *hw = &adapter->hw;
1728         u32 eicr;
1729
1730         /*
1731          * Workaround for Silicon errata.  Use clear-by-write instead
1732          * of clear-by-read.  Reading with EICS will return the
1733          * interrupt causes without clearing, which later be done
1734          * with the write to EICR.
1735          */
1736         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1737         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1738
1739         if (eicr & IXGBE_EICR_LSC)
1740                 ixgbe_check_lsc(adapter);
1741
1742         if (eicr & IXGBE_EICR_MAILBOX)
1743                 ixgbe_msg_task(adapter);
1744
1745         if (hw->mac.type == ixgbe_mac_82598EB)
1746                 ixgbe_check_fan_failure(adapter, eicr);
1747
1748         if (hw->mac.type == ixgbe_mac_82599EB) {
1749                 ixgbe_check_sfp_event(adapter, eicr);
1750                 adapter->interrupt_event = eicr;
1751                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1752                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1753                         schedule_work(&adapter->check_overtemp_task);
1754
1755                 /* Handle Flow Director Full threshold interrupt */
1756                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1757                         int i;
1758                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1759                         /* Disable transmits before FDIR Re-initialization */
1760                         netif_tx_stop_all_queues(netdev);
1761                         for (i = 0; i < adapter->num_tx_queues; i++) {
1762                                 struct ixgbe_ring *tx_ring =
1763                                                             adapter->tx_ring[i];
1764                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1765                                                        &tx_ring->reinit_state))
1766                                         schedule_work(&adapter->fdir_reinit_task);
1767                         }
1768                 }
1769         }
1770         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1771                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1772
1773         return IRQ_HANDLED;
1774 }
1775
1776 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1777                                            u64 qmask)
1778 {
1779         u32 mask;
1780
1781         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1782                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1783                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1784         } else {
1785                 mask = (qmask & 0xFFFFFFFF);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1787                 mask = (qmask >> 32);
1788                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1789         }
1790         /* skip the flush */
1791 }
1792
1793 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1794                                             u64 qmask)
1795 {
1796         u32 mask;
1797
1798         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1799                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1800                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1801         } else {
1802                 mask = (qmask & 0xFFFFFFFF);
1803                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1804                 mask = (qmask >> 32);
1805                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1806         }
1807         /* skip the flush */
1808 }
1809
1810 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1811 {
1812         struct ixgbe_q_vector *q_vector = data;
1813         struct ixgbe_adapter  *adapter = q_vector->adapter;
1814         struct ixgbe_ring     *tx_ring;
1815         int i, r_idx;
1816
1817         if (!q_vector->txr_count)
1818                 return IRQ_HANDLED;
1819
1820         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1821         for (i = 0; i < q_vector->txr_count; i++) {
1822                 tx_ring = adapter->tx_ring[r_idx];
1823                 tx_ring->total_bytes = 0;
1824                 tx_ring->total_packets = 0;
1825                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1826                                       r_idx + 1);
1827         }
1828
1829         /* EIAM disabled interrupts (on this vector) for us */
1830         napi_schedule(&q_vector->napi);
1831
1832         return IRQ_HANDLED;
1833 }
1834
1835 /**
1836  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1837  * @irq: unused
1838  * @data: pointer to our q_vector struct for this interrupt vector
1839  **/
1840 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1841 {
1842         struct ixgbe_q_vector *q_vector = data;
1843         struct ixgbe_adapter  *adapter = q_vector->adapter;
1844         struct ixgbe_ring  *rx_ring;
1845         int r_idx;
1846         int i;
1847
1848         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1849         for (i = 0;  i < q_vector->rxr_count; i++) {
1850                 rx_ring = adapter->rx_ring[r_idx];
1851                 rx_ring->total_bytes = 0;
1852                 rx_ring->total_packets = 0;
1853                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1854                                       r_idx + 1);
1855         }
1856
1857         if (!q_vector->rxr_count)
1858                 return IRQ_HANDLED;
1859
1860         /* disable interrupts on this vector only */
1861         /* EIAM disabled interrupts (on this vector) for us */
1862         napi_schedule(&q_vector->napi);
1863
1864         return IRQ_HANDLED;
1865 }
1866
1867 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1868 {
1869         struct ixgbe_q_vector *q_vector = data;
1870         struct ixgbe_adapter  *adapter = q_vector->adapter;
1871         struct ixgbe_ring  *ring;
1872         int r_idx;
1873         int i;
1874
1875         if (!q_vector->txr_count && !q_vector->rxr_count)
1876                 return IRQ_HANDLED;
1877
1878         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1879         for (i = 0; i < q_vector->txr_count; i++) {
1880                 ring = adapter->tx_ring[r_idx];
1881                 ring->total_bytes = 0;
1882                 ring->total_packets = 0;
1883                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1884                                       r_idx + 1);
1885         }
1886
1887         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1888         for (i = 0; i < q_vector->rxr_count; i++) {
1889                 ring = adapter->rx_ring[r_idx];
1890                 ring->total_bytes = 0;
1891                 ring->total_packets = 0;
1892                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1893                                       r_idx + 1);
1894         }
1895
1896         /* EIAM disabled interrupts (on this vector) for us */
1897         napi_schedule(&q_vector->napi);
1898
1899         return IRQ_HANDLED;
1900 }
1901
1902 /**
1903  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1904  * @napi: napi struct with our devices info in it
1905  * @budget: amount of work driver is allowed to do this pass, in packets
1906  *
1907  * This function is optimized for cleaning one queue only on a single
1908  * q_vector!!!
1909  **/
1910 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1911 {
1912         struct ixgbe_q_vector *q_vector =
1913                                container_of(napi, struct ixgbe_q_vector, napi);
1914         struct ixgbe_adapter *adapter = q_vector->adapter;
1915         struct ixgbe_ring *rx_ring = NULL;
1916         int work_done = 0;
1917         long r_idx;
1918
1919         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1920         rx_ring = adapter->rx_ring[r_idx];
1921 #ifdef CONFIG_IXGBE_DCA
1922         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1923                 ixgbe_update_rx_dca(adapter, rx_ring);
1924 #endif
1925
1926         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1927
1928         /* If all Rx work done, exit the polling mode */
1929         if (work_done < budget) {
1930                 napi_complete(napi);
1931                 if (adapter->rx_itr_setting & 1)
1932                         ixgbe_set_itr_msix(q_vector);
1933                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1934                         ixgbe_irq_enable_queues(adapter,
1935                                                 ((u64)1 << q_vector->v_idx));
1936         }
1937
1938         return work_done;
1939 }
1940
1941 /**
1942  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1943  * @napi: napi struct with our devices info in it
1944  * @budget: amount of work driver is allowed to do this pass, in packets
1945  *
1946  * This function will clean more than one rx queue associated with a
1947  * q_vector.
1948  **/
1949 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1950 {
1951         struct ixgbe_q_vector *q_vector =
1952                                container_of(napi, struct ixgbe_q_vector, napi);
1953         struct ixgbe_adapter *adapter = q_vector->adapter;
1954         struct ixgbe_ring *ring = NULL;
1955         int work_done = 0, i;
1956         long r_idx;
1957         bool tx_clean_complete = true;
1958
1959         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1960         for (i = 0; i < q_vector->txr_count; i++) {
1961                 ring = adapter->tx_ring[r_idx];
1962 #ifdef CONFIG_IXGBE_DCA
1963                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1964                         ixgbe_update_tx_dca(adapter, ring);
1965 #endif
1966                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1967                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1968                                       r_idx + 1);
1969         }
1970
1971         /* attempt to distribute budget to each queue fairly, but don't allow
1972          * the budget to go below 1 because we'll exit polling */
1973         budget /= (q_vector->rxr_count ?: 1);
1974         budget = max(budget, 1);
1975         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1976         for (i = 0; i < q_vector->rxr_count; i++) {
1977                 ring = adapter->rx_ring[r_idx];
1978 #ifdef CONFIG_IXGBE_DCA
1979                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1980                         ixgbe_update_rx_dca(adapter, ring);
1981 #endif
1982                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1983                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1984                                       r_idx + 1);
1985         }
1986
1987         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1988         ring = adapter->rx_ring[r_idx];
1989         /* If all Rx work done, exit the polling mode */
1990         if (work_done < budget) {
1991                 napi_complete(napi);
1992                 if (adapter->rx_itr_setting & 1)
1993                         ixgbe_set_itr_msix(q_vector);
1994                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1995                         ixgbe_irq_enable_queues(adapter,
1996                                                 ((u64)1 << q_vector->v_idx));
1997                 return 0;
1998         }
1999
2000         return work_done;
2001 }
2002
2003 /**
2004  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2005  * @napi: napi struct with our devices info in it
2006  * @budget: amount of work driver is allowed to do this pass, in packets
2007  *
2008  * This function is optimized for cleaning one queue only on a single
2009  * q_vector!!!
2010  **/
2011 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2012 {
2013         struct ixgbe_q_vector *q_vector =
2014                                container_of(napi, struct ixgbe_q_vector, napi);
2015         struct ixgbe_adapter *adapter = q_vector->adapter;
2016         struct ixgbe_ring *tx_ring = NULL;
2017         int work_done = 0;
2018         long r_idx;
2019
2020         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2021         tx_ring = adapter->tx_ring[r_idx];
2022 #ifdef CONFIG_IXGBE_DCA
2023         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2024                 ixgbe_update_tx_dca(adapter, tx_ring);
2025 #endif
2026
2027         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2028                 work_done = budget;
2029
2030         /* If all Tx work done, exit the polling mode */
2031         if (work_done < budget) {
2032                 napi_complete(napi);
2033                 if (adapter->tx_itr_setting & 1)
2034                         ixgbe_set_itr_msix(q_vector);
2035                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2036                         ixgbe_irq_enable_queues(adapter,
2037                                                 ((u64)1 << q_vector->v_idx));
2038         }
2039
2040         return work_done;
2041 }
2042
2043 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2044                                      int r_idx)
2045 {
2046         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2047
2048         set_bit(r_idx, q_vector->rxr_idx);
2049         q_vector->rxr_count++;
2050 }
2051
2052 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2053                                      int t_idx)
2054 {
2055         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2056
2057         set_bit(t_idx, q_vector->txr_idx);
2058         q_vector->txr_count++;
2059 }
2060
2061 /**
2062  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2063  * @adapter: board private structure to initialize
2064  * @vectors: allotted vector count for descriptor rings
2065  *
2066  * This function maps descriptor rings to the queue-specific vectors
2067  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2068  * one vector per ring/queue, but on a constrained vector budget, we
2069  * group the rings as "efficiently" as possible.  You would add new
2070  * mapping configurations in here.
2071  **/
2072 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2073                                       int vectors)
2074 {
2075         int v_start = 0;
2076         int rxr_idx = 0, txr_idx = 0;
2077         int rxr_remaining = adapter->num_rx_queues;
2078         int txr_remaining = adapter->num_tx_queues;
2079         int i, j;
2080         int rqpv, tqpv;
2081         int err = 0;
2082
2083         /* No mapping required if MSI-X is disabled. */
2084         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2085                 goto out;
2086
2087         /*
2088          * The ideal configuration...
2089          * We have enough vectors to map one per queue.
2090          */
2091         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2092                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2093                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2094
2095                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2096                         map_vector_to_txq(adapter, v_start, txr_idx);
2097
2098                 goto out;
2099         }
2100
2101         /*
2102          * If we don't have enough vectors for a 1-to-1
2103          * mapping, we'll have to group them so there are
2104          * multiple queues per vector.
2105          */
2106         /* Re-adjusting *qpv takes care of the remainder. */
2107         for (i = v_start; i < vectors; i++) {
2108                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2109                 for (j = 0; j < rqpv; j++) {
2110                         map_vector_to_rxq(adapter, i, rxr_idx);
2111                         rxr_idx++;
2112                         rxr_remaining--;
2113                 }
2114         }
2115         for (i = v_start; i < vectors; i++) {
2116                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2117                 for (j = 0; j < tqpv; j++) {
2118                         map_vector_to_txq(adapter, i, txr_idx);
2119                         txr_idx++;
2120                         txr_remaining--;
2121                 }
2122         }
2123
2124 out:
2125         return err;
2126 }
2127
2128 /**
2129  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2130  * @adapter: board private structure
2131  *
2132  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2133  * interrupts from the kernel.
2134  **/
2135 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2136 {
2137         struct net_device *netdev = adapter->netdev;
2138         irqreturn_t (*handler)(int, void *);
2139         int i, vector, q_vectors, err;
2140         int ri = 0, ti = 0;
2141
2142         /* Decrement for Other and TCP Timer vectors */
2143         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2144
2145         /* Map the Tx/Rx rings to the vectors we were allotted. */
2146         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2147         if (err)
2148                 goto out;
2149
2150 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2151                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2152                          &ixgbe_msix_clean_many)
2153         for (vector = 0; vector < q_vectors; vector++) {
2154                 handler = SET_HANDLER(adapter->q_vector[vector]);
2155
2156                 if (handler == &ixgbe_msix_clean_rx) {
2157                         sprintf(adapter->name[vector], "%s-%s-%d",
2158                                 netdev->name, "rx", ri++);
2159                 } else if (handler == &ixgbe_msix_clean_tx) {
2160                         sprintf(adapter->name[vector], "%s-%s-%d",
2161                                 netdev->name, "tx", ti++);
2162                 } else
2163                         sprintf(adapter->name[vector], "%s-%s-%d",
2164                                 netdev->name, "TxRx", vector);
2165
2166                 err = request_irq(adapter->msix_entries[vector].vector,
2167                                   handler, 0, adapter->name[vector],
2168                                   adapter->q_vector[vector]);
2169                 if (err) {
2170                         e_err(probe, "request_irq failed for MSIX interrupt "
2171                               "Error: %d\n", err);
2172                         goto free_queue_irqs;
2173                 }
2174         }
2175
2176         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2177         err = request_irq(adapter->msix_entries[vector].vector,
2178                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2179         if (err) {
2180                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2181                 goto free_queue_irqs;
2182         }
2183
2184         return 0;
2185
2186 free_queue_irqs:
2187         for (i = vector - 1; i >= 0; i--)
2188                 free_irq(adapter->msix_entries[--vector].vector,
2189                          adapter->q_vector[i]);
2190         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2191         pci_disable_msix(adapter->pdev);
2192         kfree(adapter->msix_entries);
2193         adapter->msix_entries = NULL;
2194 out:
2195         return err;
2196 }
2197
2198 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2199 {
2200         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2201         u8 current_itr;
2202         u32 new_itr = q_vector->eitr;
2203         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2204         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2205
2206         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2207                                             q_vector->tx_itr,
2208                                             tx_ring->total_packets,
2209                                             tx_ring->total_bytes);
2210         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2211                                             q_vector->rx_itr,
2212                                             rx_ring->total_packets,
2213                                             rx_ring->total_bytes);
2214
2215         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2216
2217         switch (current_itr) {
2218         /* counts and packets in update_itr are dependent on these numbers */
2219         case lowest_latency:
2220                 new_itr = 100000;
2221                 break;
2222         case low_latency:
2223                 new_itr = 20000; /* aka hwitr = ~200 */
2224                 break;
2225         case bulk_latency:
2226                 new_itr = 8000;
2227                 break;
2228         default:
2229                 break;
2230         }
2231
2232         if (new_itr != q_vector->eitr) {
2233                 /* do an exponential smoothing */
2234                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2235
2236                 /* save the algorithm value here, not the smoothed one */
2237                 q_vector->eitr = new_itr;
2238
2239                 ixgbe_write_eitr(q_vector);
2240         }
2241 }
2242
2243 /**
2244  * ixgbe_irq_enable - Enable default interrupt generation settings
2245  * @adapter: board private structure
2246  **/
2247 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2248                                     bool flush)
2249 {
2250         u32 mask;
2251
2252         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2253         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2254                 mask |= IXGBE_EIMS_GPI_SDP0;
2255         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2256                 mask |= IXGBE_EIMS_GPI_SDP1;
2257         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2258                 mask |= IXGBE_EIMS_ECC;
2259                 mask |= IXGBE_EIMS_GPI_SDP1;
2260                 mask |= IXGBE_EIMS_GPI_SDP2;
2261                 if (adapter->num_vfs)
2262                         mask |= IXGBE_EIMS_MAILBOX;
2263         }
2264         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2265             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2266                 mask |= IXGBE_EIMS_FLOW_DIR;
2267
2268         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2269         if (queues)
2270                 ixgbe_irq_enable_queues(adapter, ~0);
2271         if (flush)
2272                 IXGBE_WRITE_FLUSH(&adapter->hw);
2273
2274         if (adapter->num_vfs > 32) {
2275                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2276                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2277         }
2278 }
2279
2280 /**
2281  * ixgbe_intr - legacy mode Interrupt Handler
2282  * @irq: interrupt number
2283  * @data: pointer to a network interface device structure
2284  **/
2285 static irqreturn_t ixgbe_intr(int irq, void *data)
2286 {
2287         struct net_device *netdev = data;
2288         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2289         struct ixgbe_hw *hw = &adapter->hw;
2290         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2291         u32 eicr;
2292
2293         /*
2294          * Workaround for silicon errata on 82598.  Mask the interrupts
2295          * before the read of EICR.
2296          */
2297         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2298
2299         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2300          * therefore no explict interrupt disable is necessary */
2301         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2302         if (!eicr) {
2303                 /*
2304                  * shared interrupt alert!
2305                  * make sure interrupts are enabled because the read will
2306                  * have disabled interrupts due to EIAM
2307                  * finish the workaround of silicon errata on 82598.  Unmask
2308                  * the interrupt that we masked before the EICR read.
2309                  */
2310                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2311                         ixgbe_irq_enable(adapter, true, true);
2312                 return IRQ_NONE;        /* Not our interrupt */
2313         }
2314
2315         if (eicr & IXGBE_EICR_LSC)
2316                 ixgbe_check_lsc(adapter);
2317
2318         if (hw->mac.type == ixgbe_mac_82599EB)
2319                 ixgbe_check_sfp_event(adapter, eicr);
2320
2321         ixgbe_check_fan_failure(adapter, eicr);
2322         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2323             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2324                 schedule_work(&adapter->check_overtemp_task);
2325
2326         if (napi_schedule_prep(&(q_vector->napi))) {
2327                 adapter->tx_ring[0]->total_packets = 0;
2328                 adapter->tx_ring[0]->total_bytes = 0;
2329                 adapter->rx_ring[0]->total_packets = 0;
2330                 adapter->rx_ring[0]->total_bytes = 0;
2331                 /* would disable interrupts here but EIAM disabled it */
2332                 __napi_schedule(&(q_vector->napi));
2333         }
2334
2335         /*
2336          * re-enable link(maybe) and non-queue interrupts, no flush.
2337          * ixgbe_poll will re-enable the queue interrupts
2338          */
2339
2340         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2341                 ixgbe_irq_enable(adapter, false, false);
2342
2343         return IRQ_HANDLED;
2344 }
2345
2346 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2347 {
2348         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2349
2350         for (i = 0; i < q_vectors; i++) {
2351                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2352                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2353                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2354                 q_vector->rxr_count = 0;
2355                 q_vector->txr_count = 0;
2356         }
2357 }
2358
2359 /**
2360  * ixgbe_request_irq - initialize interrupts
2361  * @adapter: board private structure
2362  *
2363  * Attempts to configure interrupts using the best available
2364  * capabilities of the hardware and kernel.
2365  **/
2366 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2367 {
2368         struct net_device *netdev = adapter->netdev;
2369         int err;
2370
2371         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2372                 err = ixgbe_request_msix_irqs(adapter);
2373         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2374                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2375                                   netdev->name, netdev);
2376         } else {
2377                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2378                                   netdev->name, netdev);
2379         }
2380
2381         if (err)
2382                 e_err(probe, "request_irq failed, Error %d\n", err);
2383
2384         return err;
2385 }
2386
2387 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2388 {
2389         struct net_device *netdev = adapter->netdev;
2390
2391         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2392                 int i, q_vectors;
2393
2394                 q_vectors = adapter->num_msix_vectors;
2395
2396                 i = q_vectors - 1;
2397                 free_irq(adapter->msix_entries[i].vector, netdev);
2398
2399                 i--;
2400                 for (; i >= 0; i--) {
2401                         free_irq(adapter->msix_entries[i].vector,
2402                                  adapter->q_vector[i]);
2403                 }
2404
2405                 ixgbe_reset_q_vectors(adapter);
2406         } else {
2407                 free_irq(adapter->pdev->irq, netdev);
2408         }
2409 }
2410
2411 /**
2412  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2413  * @adapter: board private structure
2414  **/
2415 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2416 {
2417         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2418                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2419         } else {
2420                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2421                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2422                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2423                 if (adapter->num_vfs > 32)
2424                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2425         }
2426         IXGBE_WRITE_FLUSH(&adapter->hw);
2427         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2428                 int i;
2429                 for (i = 0; i < adapter->num_msix_vectors; i++)
2430                         synchronize_irq(adapter->msix_entries[i].vector);
2431         } else {
2432                 synchronize_irq(adapter->pdev->irq);
2433         }
2434 }
2435
2436 /**
2437  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2438  *
2439  **/
2440 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2441 {
2442         struct ixgbe_hw *hw = &adapter->hw;
2443
2444         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2445                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2446
2447         ixgbe_set_ivar(adapter, 0, 0, 0);
2448         ixgbe_set_ivar(adapter, 1, 0, 0);
2449
2450         map_vector_to_rxq(adapter, 0, 0);
2451         map_vector_to_txq(adapter, 0, 0);
2452
2453         e_info(hw, "Legacy interrupt IVAR setup done\n");
2454 }
2455
2456 /**
2457  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2458  * @adapter: board private structure
2459  * @ring: structure containing ring specific data
2460  *
2461  * Configure the Tx descriptor ring after a reset.
2462  **/
2463 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2464                              struct ixgbe_ring *ring)
2465 {
2466         struct ixgbe_hw *hw = &adapter->hw;
2467         u64 tdba = ring->dma;
2468         int wait_loop = 10;
2469         u32 txdctl;
2470         u16 reg_idx = ring->reg_idx;
2471
2472         /* disable queue to avoid issues while updating state */
2473         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2474         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2475                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2476         IXGBE_WRITE_FLUSH(hw);
2477
2478         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2479                         (tdba & DMA_BIT_MASK(32)));
2480         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2481         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2482                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2483         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2484         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2485         ring->head = IXGBE_TDH(reg_idx);
2486         ring->tail = IXGBE_TDT(reg_idx);
2487
2488         /* configure fetching thresholds */
2489         if (adapter->rx_itr_setting == 0) {
2490                 /* cannot set wthresh when itr==0 */
2491                 txdctl &= ~0x007F0000;
2492         } else {
2493                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2494                 txdctl |= (8 << 16);
2495         }
2496         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2497                 /* PThresh workaround for Tx hang with DFP enabled. */
2498                 txdctl |= 32;
2499         }
2500
2501         /* reinitialize flowdirector state */
2502         set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2503
2504         /* enable queue */
2505         txdctl |= IXGBE_TXDCTL_ENABLE;
2506         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2507
2508         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2509         if (hw->mac.type == ixgbe_mac_82598EB &&
2510             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2511                 return;
2512
2513         /* poll to verify queue is enabled */
2514         do {
2515                 msleep(1);
2516                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2517         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2518         if (!wait_loop)
2519                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2520 }
2521
2522 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2523 {
2524         struct ixgbe_hw *hw = &adapter->hw;
2525         u32 rttdcs;
2526         u32 mask;
2527
2528         if (hw->mac.type == ixgbe_mac_82598EB)
2529                 return;
2530
2531         /* disable the arbiter while setting MTQC */
2532         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2533         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2534         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2535
2536         /* set transmit pool layout */
2537         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2538         switch (adapter->flags & mask) {
2539
2540         case (IXGBE_FLAG_SRIOV_ENABLED):
2541                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2542                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2543                 break;
2544
2545         case (IXGBE_FLAG_DCB_ENABLED):
2546                 /* We enable 8 traffic classes, DCB only */
2547                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2548                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2549                 break;
2550
2551         default:
2552                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2553                 break;
2554         }
2555
2556         /* re-enable the arbiter */
2557         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2558         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2559 }
2560
2561 /**
2562  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2563  * @adapter: board private structure
2564  *
2565  * Configure the Tx unit of the MAC after a reset.
2566  **/
2567 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2568 {
2569         struct ixgbe_hw *hw = &adapter->hw;
2570         u32 dmatxctl;
2571         u32 i;
2572
2573         ixgbe_setup_mtqc(adapter);
2574
2575         if (hw->mac.type != ixgbe_mac_82598EB) {
2576                 /* DMATXCTL.EN must be before Tx queues are enabled */
2577                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2578                 dmatxctl |= IXGBE_DMATXCTL_TE;
2579                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2580         }
2581
2582         /* Setup the HW Tx Head and Tail descriptor pointers */
2583         for (i = 0; i < adapter->num_tx_queues; i++)
2584                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2585 }
2586
2587 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2588
2589 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2590                                    struct ixgbe_ring *rx_ring)
2591 {
2592         u32 srrctl;
2593         int index;
2594         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2595
2596         index = rx_ring->reg_idx;
2597         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2598                 unsigned long mask;
2599                 mask = (unsigned long) feature[RING_F_RSS].mask;
2600                 index = index & mask;
2601         }
2602         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2603
2604         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2605         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2606         if (adapter->num_vfs)
2607                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2608
2609         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2610                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2611
2612         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2613 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2614                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2615 #else
2616                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2617 #endif
2618                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2619         } else {
2620                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2621                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2622                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2623         }
2624
2625         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2626 }
2627
2628 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2629 {
2630         struct ixgbe_hw *hw = &adapter->hw;
2631         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2632                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2633                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2634         u32 mrqc = 0, reta = 0;
2635         u32 rxcsum;
2636         int i, j;
2637         int mask;
2638
2639         /* Fill out hash function seeds */
2640         for (i = 0; i < 10; i++)
2641                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2642
2643         /* Fill out redirection table */
2644         for (i = 0, j = 0; i < 128; i++, j++) {
2645                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2646                         j = 0;
2647                 /* reta = 4-byte sliding window of
2648                  * 0x00..(indices-1)(indices-1)00..etc. */
2649                 reta = (reta << 8) | (j * 0x11);
2650                 if ((i & 3) == 3)
2651                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2652         }
2653
2654         /* Disable indicating checksum in descriptor, enables RSS hash */
2655         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2656         rxcsum |= IXGBE_RXCSUM_PCSD;
2657         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2658
2659         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2660                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2661         else
2662                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2663 #ifdef CONFIG_IXGBE_DCB
2664                                          | IXGBE_FLAG_DCB_ENABLED
2665 #endif
2666                                          | IXGBE_FLAG_SRIOV_ENABLED
2667                                         );
2668
2669         switch (mask) {
2670         case (IXGBE_FLAG_RSS_ENABLED):
2671                 mrqc = IXGBE_MRQC_RSSEN;
2672                 break;
2673         case (IXGBE_FLAG_SRIOV_ENABLED):
2674                 mrqc = IXGBE_MRQC_VMDQEN;
2675                 break;
2676 #ifdef CONFIG_IXGBE_DCB
2677         case (IXGBE_FLAG_DCB_ENABLED):
2678                 mrqc = IXGBE_MRQC_RT8TCEN;
2679                 break;
2680 #endif /* CONFIG_IXGBE_DCB */
2681         default:
2682                 break;
2683         }
2684
2685         /* Perform hash on these packet types */
2686         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2687               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2688               | IXGBE_MRQC_RSS_FIELD_IPV6
2689               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2690
2691         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2692 }
2693
2694 /**
2695  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2696  * @adapter:    address of board private structure
2697  * @index:      index of ring to set
2698  **/
2699 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2700                                    struct ixgbe_ring *ring)
2701 {
2702         struct ixgbe_hw *hw = &adapter->hw;
2703         u32 rscctrl;
2704         int rx_buf_len;
2705         u16 reg_idx = ring->reg_idx;
2706
2707         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2708                 return;
2709
2710         rx_buf_len = ring->rx_buf_len;
2711         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2712         rscctrl |= IXGBE_RSCCTL_RSCEN;
2713         /*
2714          * we must limit the number of descriptors so that the
2715          * total size of max desc * buf_len is not greater
2716          * than 65535
2717          */
2718         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2719 #if (MAX_SKB_FRAGS > 16)
2720                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2721 #elif (MAX_SKB_FRAGS > 8)
2722                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2723 #elif (MAX_SKB_FRAGS > 4)
2724                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2725 #else
2726                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2727 #endif
2728         } else {
2729                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2730                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2731                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2732                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2733                 else
2734                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2735         }
2736         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2737 }
2738
2739 /**
2740  *  ixgbe_set_uta - Set unicast filter table address
2741  *  @adapter: board private structure
2742  *
2743  *  The unicast table address is a register array of 32-bit registers.
2744  *  The table is meant to be used in a way similar to how the MTA is used
2745  *  however due to certain limitations in the hardware it is necessary to
2746  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2747  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2748  **/
2749 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2750 {
2751         struct ixgbe_hw *hw = &adapter->hw;
2752         int i;
2753
2754         /* The UTA table only exists on 82599 hardware and newer */
2755         if (hw->mac.type < ixgbe_mac_82599EB)
2756                 return;
2757
2758         /* we only need to do this if VMDq is enabled */
2759         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2760                 return;
2761
2762         for (i = 0; i < 128; i++)
2763                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2764 }
2765
2766 #define IXGBE_MAX_RX_DESC_POLL 10
2767 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2768                                        struct ixgbe_ring *ring)
2769 {
2770         struct ixgbe_hw *hw = &adapter->hw;
2771         int reg_idx = ring->reg_idx;
2772         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2773         u32 rxdctl;
2774
2775         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2776         if (hw->mac.type == ixgbe_mac_82598EB &&
2777             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2778                 return;
2779
2780         do {
2781                 msleep(1);
2782                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2783         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2784
2785         if (!wait_loop) {
2786                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2787                       "the polling period\n", reg_idx);
2788         }
2789 }
2790
2791 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2792                              struct ixgbe_ring *ring)
2793 {
2794         struct ixgbe_hw *hw = &adapter->hw;
2795         u64 rdba = ring->dma;
2796         u32 rxdctl;
2797         u16 reg_idx = ring->reg_idx;
2798
2799         /* disable queue to avoid issues while updating state */
2800         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2801         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2802                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2803         IXGBE_WRITE_FLUSH(hw);
2804
2805         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2806         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2807         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2808                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2809         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2810         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2811         ring->head = IXGBE_RDH(reg_idx);
2812         ring->tail = IXGBE_RDT(reg_idx);
2813
2814         ixgbe_configure_srrctl(adapter, ring);
2815         ixgbe_configure_rscctl(adapter, ring);
2816
2817         if (hw->mac.type == ixgbe_mac_82598EB) {
2818                 /*
2819                  * enable cache line friendly hardware writes:
2820                  * PTHRESH=32 descriptors (half the internal cache),
2821                  * this also removes ugly rx_no_buffer_count increment
2822                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2823                  * WTHRESH=8 burst writeback up to two cache lines
2824                  */
2825                 rxdctl &= ~0x3FFFFF;
2826                 rxdctl |=  0x080420;
2827         }
2828
2829         /* enable receive descriptor ring */
2830         rxdctl |= IXGBE_RXDCTL_ENABLE;
2831         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2832
2833         ixgbe_rx_desc_queue_enable(adapter, ring);
2834         ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2835 }
2836
2837 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2838 {
2839         struct ixgbe_hw *hw = &adapter->hw;
2840         int p;
2841
2842         /* PSRTYPE must be initialized in non 82598 adapters */
2843         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2844                       IXGBE_PSRTYPE_UDPHDR |
2845                       IXGBE_PSRTYPE_IPV4HDR |
2846                       IXGBE_PSRTYPE_L2HDR |
2847                       IXGBE_PSRTYPE_IPV6HDR;
2848
2849         if (hw->mac.type == ixgbe_mac_82598EB)
2850                 return;
2851
2852         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2853                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2854
2855         for (p = 0; p < adapter->num_rx_pools; p++)
2856                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2857                                 psrtype);
2858 }
2859
2860 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2861 {
2862         struct ixgbe_hw *hw = &adapter->hw;
2863         u32 gcr_ext;
2864         u32 vt_reg_bits;
2865         u32 reg_offset, vf_shift;
2866         u32 vmdctl;
2867
2868         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2869                 return;
2870
2871         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2872         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2873         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2874         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2875
2876         vf_shift = adapter->num_vfs % 32;
2877         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2878
2879         /* Enable only the PF's pool for Tx/Rx */
2880         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2881         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2882         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2883         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2884         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2885
2886         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2887         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2888
2889         /*
2890          * Set up VF register offsets for selected VT Mode,
2891          * i.e. 32 or 64 VFs for SR-IOV
2892          */
2893         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2894         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2895         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2896         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2897
2898         /* enable Tx loopback for VF/PF communication */
2899         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2900 }
2901
2902 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2903 {
2904         struct ixgbe_hw *hw = &adapter->hw;
2905         struct net_device *netdev = adapter->netdev;
2906         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2907         int rx_buf_len;
2908         struct ixgbe_ring *rx_ring;
2909         int i;
2910         u32 mhadd, hlreg0;
2911
2912         /* Decide whether to use packet split mode or not */
2913         /* Do not use packet split if we're in SR-IOV Mode */
2914         if (!adapter->num_vfs)
2915                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2916
2917         /* Set the RX buffer length according to the mode */
2918         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2919                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2920         } else {
2921                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2922                     (netdev->mtu <= ETH_DATA_LEN))
2923                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2924                 else
2925                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2926         }
2927
2928 #ifdef IXGBE_FCOE
2929         /* adjust max frame to be able to do baby jumbo for FCoE */
2930         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2931             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2932                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2933
2934 #endif /* IXGBE_FCOE */
2935         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2936         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2937                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2938                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2939
2940                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2941         }
2942
2943         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2944         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2945         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2946         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2947
2948         /*
2949          * Setup the HW Rx Head and Tail Descriptor Pointers and
2950          * the Base and Length of the Rx Descriptor Ring
2951          */
2952         for (i = 0; i < adapter->num_rx_queues; i++) {
2953                 rx_ring = adapter->rx_ring[i];
2954                 rx_ring->rx_buf_len = rx_buf_len;
2955
2956                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2957                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2958                 else
2959                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2960
2961 #ifdef IXGBE_FCOE
2962                 if (netdev->features & NETIF_F_FCOE_MTU) {
2963                         struct ixgbe_ring_feature *f;
2964                         f = &adapter->ring_feature[RING_F_FCOE];
2965                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2966                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2967                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2968                                         rx_ring->rx_buf_len =
2969                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2970                         }
2971                 }
2972 #endif /* IXGBE_FCOE */
2973         }
2974
2975 }
2976
2977 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2978 {
2979         struct ixgbe_hw *hw = &adapter->hw;
2980         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2981
2982         switch (hw->mac.type) {
2983         case ixgbe_mac_82598EB:
2984                 /*
2985                  * For VMDq support of different descriptor types or
2986                  * buffer sizes through the use of multiple SRRCTL
2987                  * registers, RDRXCTL.MVMEN must be set to 1
2988                  *
2989                  * also, the manual doesn't mention it clearly but DCA hints
2990                  * will only use queue 0's tags unless this bit is set.  Side
2991                  * effects of setting this bit are only that SRRCTL must be
2992                  * fully programmed [0..15]
2993                  */
2994                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2995                 break;
2996         case ixgbe_mac_82599EB:
2997                 /* Disable RSC for ACK packets */
2998                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2999                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3000                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3001                 /* hardware requires some bits to be set by default */
3002                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3003                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3004                 break;
3005         default:
3006                 /* We should do nothing since we don't know this hardware */
3007                 return;
3008         }
3009
3010         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3011 }
3012
3013 /**
3014  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3015  * @adapter: board private structure
3016  *
3017  * Configure the Rx unit of the MAC after a reset.
3018  **/
3019 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3020 {
3021         struct ixgbe_hw *hw = &adapter->hw;
3022         int i;
3023         u32 rxctrl;
3024
3025         /* disable receives while setting up the descriptors */
3026         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3027         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3028
3029         ixgbe_setup_psrtype(adapter);
3030         ixgbe_setup_rdrxctl(adapter);
3031
3032         /* Program registers for the distribution of queues */
3033         ixgbe_setup_mrqc(adapter);
3034
3035         ixgbe_set_uta(adapter);
3036
3037         /* set_rx_buffer_len must be called before ring initialization */
3038         ixgbe_set_rx_buffer_len(adapter);
3039
3040         /*
3041          * Setup the HW Rx Head and Tail Descriptor Pointers and
3042          * the Base and Length of the Rx Descriptor Ring
3043          */
3044         for (i = 0; i < adapter->num_rx_queues; i++)
3045                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3046
3047         /* disable drop enable for 82598 parts */
3048         if (hw->mac.type == ixgbe_mac_82598EB)
3049                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3050
3051         /* enable all receives */
3052         rxctrl |= IXGBE_RXCTRL_RXEN;
3053         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3054 }
3055
3056 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3057 {
3058         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3059         struct ixgbe_hw *hw = &adapter->hw;
3060         int pool_ndx = adapter->num_vfs;
3061
3062         /* add VID to filter table */
3063         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3064         set_bit(vid, adapter->active_vlans);
3065 }
3066
3067 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3068 {
3069         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3070         struct ixgbe_hw *hw = &adapter->hw;
3071         int pool_ndx = adapter->num_vfs;
3072
3073         /* remove VID from filter table */
3074         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3075         clear_bit(vid, adapter->active_vlans);
3076 }
3077
3078 /**
3079  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3080  * @adapter: driver data
3081  */
3082 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3083 {
3084         struct ixgbe_hw *hw = &adapter->hw;
3085         u32 vlnctrl;
3086
3087         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3088         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3089         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3090 }
3091
3092 /**
3093  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3094  * @adapter: driver data
3095  */
3096 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3097 {
3098         struct ixgbe_hw *hw = &adapter->hw;
3099         u32 vlnctrl;
3100
3101         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3102         vlnctrl |= IXGBE_VLNCTRL_VFE;
3103         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3104         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3105 }
3106
3107 /**
3108  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3109  * @adapter: driver data
3110  */
3111 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3112 {
3113         struct ixgbe_hw *hw = &adapter->hw;
3114         u32 vlnctrl;
3115         int i, j;
3116
3117         switch (hw->mac.type) {
3118         case ixgbe_mac_82598EB:
3119                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3120                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3121                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3122                 break;
3123         case ixgbe_mac_82599EB:
3124                 for (i = 0; i < adapter->num_rx_queues; i++) {
3125                         j = adapter->rx_ring[i]->reg_idx;
3126                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3127                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3128                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3129                 }
3130                 break;
3131         default:
3132                 break;
3133         }
3134 }
3135
3136 /**
3137  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3138  * @adapter: driver data
3139  */
3140 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3141 {
3142         struct ixgbe_hw *hw = &adapter->hw;
3143         u32 vlnctrl;
3144         int i, j;
3145
3146         switch (hw->mac.type) {
3147         case ixgbe_mac_82598EB:
3148                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3149                 vlnctrl |= IXGBE_VLNCTRL_VME;
3150                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3151                 break;
3152         case ixgbe_mac_82599EB:
3153                 for (i = 0; i < adapter->num_rx_queues; i++) {
3154                         j = adapter->rx_ring[i]->reg_idx;
3155                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3156                         vlnctrl |= IXGBE_RXDCTL_VME;
3157                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3158                 }
3159                 break;
3160         default:
3161                 break;
3162         }
3163 }
3164
3165 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3166 {
3167         u16 vid;
3168
3169         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3170
3171         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3172                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3173 }
3174
3175 /**
3176  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3177  * @netdev: network interface device structure
3178  *
3179  * Writes unicast address list to the RAR table.
3180  * Returns: -ENOMEM on failure/insufficient address space
3181  *                0 on no addresses written
3182  *                X on writing X addresses to the RAR table
3183  **/
3184 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3185 {
3186         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3187         struct ixgbe_hw *hw = &adapter->hw;
3188         unsigned int vfn = adapter->num_vfs;
3189         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3190         int count = 0;
3191
3192         /* return ENOMEM indicating insufficient memory for addresses */
3193         if (netdev_uc_count(netdev) > rar_entries)
3194                 return -ENOMEM;
3195
3196         if (!netdev_uc_empty(netdev) && rar_entries) {
3197                 struct netdev_hw_addr *ha;
3198                 /* return error if we do not support writing to RAR table */
3199                 if (!hw->mac.ops.set_rar)
3200                         return -ENOMEM;
3201
3202                 netdev_for_each_uc_addr(ha, netdev) {
3203                         if (!rar_entries)
3204                                 break;
3205                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3206                                             vfn, IXGBE_RAH_AV);
3207                         count++;
3208                 }
3209         }
3210         /* write the addresses in reverse order to avoid write combining */
3211         for (; rar_entries > 0 ; rar_entries--)
3212                 hw->mac.ops.clear_rar(hw, rar_entries);
3213
3214         return count;
3215 }
3216
3217 /**
3218  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3219  * @netdev: network interface device structure
3220  *
3221  * The set_rx_method entry point is called whenever the unicast/multicast
3222  * address list or the network interface flags are updated.  This routine is
3223  * responsible for configuring the hardware for proper unicast, multicast and
3224  * promiscuous mode.
3225  **/
3226 void ixgbe_set_rx_mode(struct net_device *netdev)
3227 {
3228         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3229         struct ixgbe_hw *hw = &adapter->hw;
3230         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3231         int count;
3232
3233         /* Check for Promiscuous and All Multicast modes */
3234
3235         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3236
3237         /* set all bits that we expect to always be set */
3238         fctrl |= IXGBE_FCTRL_BAM;
3239         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3240         fctrl |= IXGBE_FCTRL_PMCF;
3241
3242         /* clear the bits we are changing the status of */
3243         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3244
3245         if (netdev->flags & IFF_PROMISC) {
3246                 hw->addr_ctrl.user_set_promisc = true;
3247                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3248                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3249                 /* don't hardware filter vlans in promisc mode */
3250                 ixgbe_vlan_filter_disable(adapter);
3251         } else {
3252                 if (netdev->flags & IFF_ALLMULTI) {
3253                         fctrl |= IXGBE_FCTRL_MPE;
3254                         vmolr |= IXGBE_VMOLR_MPE;
3255                 } else {
3256                         /*
3257                          * Write addresses to the MTA, if the attempt fails
3258                          * then we should just turn on promiscous mode so
3259                          * that we can at least receive multicast traffic
3260                          */
3261                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3262                         vmolr |= IXGBE_VMOLR_ROMPE;
3263                 }
3264                 ixgbe_vlan_filter_enable(adapter);
3265                 hw->addr_ctrl.user_set_promisc = false;
3266                 /*
3267                  * Write addresses to available RAR registers, if there is not
3268                  * sufficient space to store all the addresses then enable
3269                  * unicast promiscous mode
3270                  */
3271                 count = ixgbe_write_uc_addr_list(netdev);
3272                 if (count < 0) {
3273                         fctrl |= IXGBE_FCTRL_UPE;
3274                         vmolr |= IXGBE_VMOLR_ROPE;
3275                 }
3276         }
3277
3278         if (adapter->num_vfs) {
3279                 ixgbe_restore_vf_multicasts(adapter);
3280                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3281                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3282                            IXGBE_VMOLR_ROPE);
3283                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3284         }
3285
3286         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3287
3288         if (netdev->features & NETIF_F_HW_VLAN_RX)
3289                 ixgbe_vlan_strip_enable(adapter);
3290         else
3291                 ixgbe_vlan_strip_disable(adapter);
3292 }
3293
3294 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3295 {
3296         int q_idx;
3297         struct ixgbe_q_vector *q_vector;
3298         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3299
3300         /* legacy and MSI only use one vector */
3301         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3302                 q_vectors = 1;
3303
3304         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3305                 struct napi_struct *napi;
3306                 q_vector = adapter->q_vector[q_idx];
3307                 napi = &q_vector->napi;
3308                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3309                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3310                                 if (q_vector->txr_count == 1)
3311                                         napi->poll = &ixgbe_clean_txonly;
3312                                 else if (q_vector->rxr_count == 1)
3313                                         napi->poll = &ixgbe_clean_rxonly;
3314                         }
3315                 }
3316
3317                 napi_enable(napi);
3318         }
3319 }
3320
3321 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3322 {
3323         int q_idx;
3324         struct ixgbe_q_vector *q_vector;
3325         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3326
3327         /* legacy and MSI only use one vector */
3328         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3329                 q_vectors = 1;
3330
3331         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3332                 q_vector = adapter->q_vector[q_idx];
3333                 napi_disable(&q_vector->napi);
3334         }
3335 }
3336
3337 #ifdef CONFIG_IXGBE_DCB
3338 /*
3339  * ixgbe_configure_dcb - Configure DCB hardware
3340  * @adapter: ixgbe adapter struct
3341  *
3342  * This is called by the driver on open to configure the DCB hardware.
3343  * This is also called by the gennetlink interface when reconfiguring
3344  * the DCB state.
3345  */
3346 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3347 {
3348         struct ixgbe_hw *hw = &adapter->hw;
3349         u32 txdctl;
3350         int i, j;
3351
3352         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3353                 if (hw->mac.type == ixgbe_mac_82598EB)
3354                         netif_set_gso_max_size(adapter->netdev, 65536);
3355                 return;
3356         }
3357
3358         if (hw->mac.type == ixgbe_mac_82598EB)
3359                 netif_set_gso_max_size(adapter->netdev, 32768);
3360
3361         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
3362         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
3363
3364         /* reconfigure the hardware */
3365         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3366
3367         for (i = 0; i < adapter->num_tx_queues; i++) {
3368                 j = adapter->tx_ring[i]->reg_idx;
3369                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3370                 /* PThresh workaround for Tx hang with DFP enabled. */
3371                 txdctl |= 32;
3372                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3373         }
3374         /* Enable VLAN tag insert/strip */
3375         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3376
3377         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3378 }
3379
3380 #endif
3381 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3382 {
3383         struct net_device *netdev = adapter->netdev;
3384         struct ixgbe_hw *hw = &adapter->hw;
3385         int i;
3386
3387 #ifdef CONFIG_IXGBE_DCB
3388         ixgbe_configure_dcb(adapter);
3389 #endif
3390
3391         ixgbe_set_rx_mode(netdev);
3392         ixgbe_restore_vlan(adapter);
3393
3394 #ifdef IXGBE_FCOE
3395         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3396                 ixgbe_configure_fcoe(adapter);
3397
3398 #endif /* IXGBE_FCOE */
3399         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3400                 for (i = 0; i < adapter->num_tx_queues; i++)
3401                         adapter->tx_ring[i]->atr_sample_rate =
3402                                                        adapter->atr_sample_rate;
3403                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3404         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3405                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3406         }
3407         ixgbe_configure_virtualization(adapter);
3408
3409         ixgbe_configure_tx(adapter);
3410         ixgbe_configure_rx(adapter);
3411 }
3412
3413 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3414 {
3415         switch (hw->phy.type) {
3416         case ixgbe_phy_sfp_avago:
3417         case ixgbe_phy_sfp_ftl:
3418         case ixgbe_phy_sfp_intel:
3419         case ixgbe_phy_sfp_unknown:
3420         case ixgbe_phy_sfp_passive_tyco:
3421         case ixgbe_phy_sfp_passive_unknown:
3422         case ixgbe_phy_sfp_active_unknown:
3423         case ixgbe_phy_sfp_ftl_active:
3424                 return true;
3425         default:
3426                 return false;
3427         }
3428 }
3429
3430 /**
3431  * ixgbe_sfp_link_config - set up SFP+ link
3432  * @adapter: pointer to private adapter struct
3433  **/
3434 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3435 {
3436         struct ixgbe_hw *hw = &adapter->hw;
3437
3438                 if (hw->phy.multispeed_fiber) {
3439                         /*
3440                          * In multispeed fiber setups, the device may not have
3441                          * had a physical connection when the driver loaded.
3442                          * If that's the case, the initial link configuration
3443                          * couldn't get the MAC into 10G or 1G mode, so we'll
3444                          * never have a link status change interrupt fire.
3445                          * We need to try and force an autonegotiation
3446                          * session, then bring up link.
3447                          */
3448                         hw->mac.ops.setup_sfp(hw);
3449                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3450                                 schedule_work(&adapter->multispeed_fiber_task);
3451                 } else {
3452                         /*
3453                          * Direct Attach Cu and non-multispeed fiber modules
3454                          * still need to be configured properly prior to
3455                          * attempting link.
3456                          */
3457                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3458                                 schedule_work(&adapter->sfp_config_module_task);
3459                 }
3460 }
3461
3462 /**
3463  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3464  * @hw: pointer to private hardware struct
3465  *
3466  * Returns 0 on success, negative on failure
3467  **/
3468 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3469 {
3470         u32 autoneg;
3471         bool negotiation, link_up = false;
3472         u32 ret = IXGBE_ERR_LINK_SETUP;
3473
3474         if (hw->mac.ops.check_link)
3475                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3476
3477         if (ret)
3478                 goto link_cfg_out;
3479
3480         if (hw->mac.ops.get_link_capabilities)
3481                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3482                                                         &negotiation);
3483         if (ret)
3484                 goto link_cfg_out;
3485
3486         if (hw->mac.ops.setup_link)
3487                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3488 link_cfg_out:
3489         return ret;
3490 }
3491
3492 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3493 {
3494         struct ixgbe_hw *hw = &adapter->hw;
3495         u32 gpie = 0;
3496
3497         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3498                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3499                        IXGBE_GPIE_OCD;
3500                 gpie |= IXGBE_GPIE_EIAME;
3501                 /*
3502                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3503                  * this saves a register write for every interrupt
3504                  */
3505                 switch (hw->mac.type) {
3506                 case ixgbe_mac_82598EB:
3507                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3508                         break;
3509                 default:
3510                 case ixgbe_mac_82599EB:
3511                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3512                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3513                         break;
3514                 }
3515         } else {
3516                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3517                  * specifically only auto mask tx and rx interrupts */
3518                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3519         }
3520
3521         /* XXX: to interrupt immediately for EICS writes, enable this */
3522         /* gpie |= IXGBE_GPIE_EIMEN; */
3523
3524         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3525                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3526                 gpie |= IXGBE_GPIE_VTMODE_64;
3527         }
3528
3529         /* Enable fan failure interrupt */
3530         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3531                 gpie |= IXGBE_SDP1_GPIEN;
3532
3533         if (hw->mac.type == ixgbe_mac_82599EB)
3534                 gpie |= IXGBE_SDP1_GPIEN;
3535                 gpie |= IXGBE_SDP2_GPIEN;
3536
3537         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3538 }
3539
3540 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3541 {
3542         struct ixgbe_hw *hw = &adapter->hw;
3543         int err;
3544         u32 ctrl_ext;
3545
3546         ixgbe_get_hw_control(adapter);
3547         ixgbe_setup_gpie(adapter);
3548
3549         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3550                 ixgbe_configure_msix(adapter);
3551         else
3552                 ixgbe_configure_msi_and_legacy(adapter);
3553
3554         /* enable the optics */
3555         if (hw->phy.multispeed_fiber)
3556                 hw->mac.ops.enable_tx_laser(hw);
3557
3558         clear_bit(__IXGBE_DOWN, &adapter->state);
3559         ixgbe_napi_enable_all(adapter);
3560
3561         /* clear any pending interrupts, may auto mask */
3562         IXGBE_READ_REG(hw, IXGBE_EICR);
3563         ixgbe_irq_enable(adapter, true, true);
3564
3565         /*
3566          * If this adapter has a fan, check to see if we had a failure
3567          * before we enabled the interrupt.
3568          */
3569         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3570                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3571                 if (esdp & IXGBE_ESDP_SDP1)
3572                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3573         }
3574
3575         /*
3576          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3577          * arrived before interrupts were enabled but after probe.  Such
3578          * devices wouldn't have their type identified yet. We need to
3579          * kick off the SFP+ module setup first, then try to bring up link.
3580          * If we're not hot-pluggable SFP+, we just need to configure link
3581          * and bring it up.
3582          */
3583         if (hw->phy.type == ixgbe_phy_unknown) {
3584                 err = hw->phy.ops.identify(hw);
3585                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3586                         /*
3587                          * Take the device down and schedule the sfp tasklet
3588                          * which will unregister_netdev and log it.
3589                          */
3590                         ixgbe_down(adapter);
3591                         schedule_work(&adapter->sfp_config_module_task);
3592                         return err;
3593                 }
3594         }
3595
3596         if (ixgbe_is_sfp(hw)) {
3597                 ixgbe_sfp_link_config(adapter);
3598         } else {
3599                 err = ixgbe_non_sfp_link_config(hw);
3600                 if (err)
3601                         e_err(probe, "link_config FAILED %d\n", err);
3602         }
3603
3604         /* enable transmits */
3605         netif_tx_start_all_queues(adapter->netdev);
3606
3607         /* bring the link up in the watchdog, this could race with our first
3608          * link up interrupt but shouldn't be a problem */
3609         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3610         adapter->link_check_timeout = jiffies;
3611         mod_timer(&adapter->watchdog_timer, jiffies);
3612
3613         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3614         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3615         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3616         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3617
3618         return 0;
3619 }
3620
3621 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3622 {
3623         WARN_ON(in_interrupt());
3624         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3625                 msleep(1);
3626         ixgbe_down(adapter);
3627         /*
3628          * If SR-IOV enabled then wait a bit before bringing the adapter
3629          * back up to give the VFs time to respond to the reset.  The
3630          * two second wait is based upon the watchdog timer cycle in
3631          * the VF driver.
3632          */
3633         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3634                 msleep(2000);
3635         ixgbe_up(adapter);
3636         clear_bit(__IXGBE_RESETTING, &adapter->state);
3637 }
3638
3639 int ixgbe_up(struct ixgbe_adapter *adapter)
3640 {
3641         /* hardware has been reset, we need to reload some things */
3642         ixgbe_configure(adapter);
3643
3644         return ixgbe_up_complete(adapter);
3645 }
3646
3647 void ixgbe_reset(struct ixgbe_adapter *adapter)
3648 {
3649         struct ixgbe_hw *hw = &adapter->hw;
3650         int err;
3651
3652         err = hw->mac.ops.init_hw(hw);
3653         switch (err) {
3654         case 0:
3655         case IXGBE_ERR_SFP_NOT_PRESENT:
3656                 break;
3657         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3658                 e_dev_err("master disable timed out\n");
3659                 break;
3660         case IXGBE_ERR_EEPROM_VERSION:
3661                 /* We are running on a pre-production device, log a warning */
3662                 e_dev_warn("This device is a pre-production adapter/LOM. "
3663                            "Please be aware there may be issuesassociated with "
3664                            "your hardware.  If you are experiencing problems "
3665                            "please contact your Intel or hardware "
3666                            "representative who provided you with this "
3667                            "hardware.\n");
3668                 break;
3669         default:
3670                 e_dev_err("Hardware Error: %d\n", err);
3671         }
3672
3673         /* reprogram the RAR[0] in case user changed it. */
3674         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3675                             IXGBE_RAH_AV);
3676 }
3677
3678 /**
3679  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3680  * @adapter: board private structure
3681  * @rx_ring: ring to free buffers from
3682  **/
3683 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3684                                 struct ixgbe_ring *rx_ring)
3685 {
3686         struct pci_dev *pdev = adapter->pdev;
3687         unsigned long size;
3688         unsigned int i;
3689
3690         /* ring already cleared, nothing to do */
3691         if (!rx_ring->rx_buffer_info)
3692                 return;
3693
3694         /* Free all the Rx ring sk_buffs */
3695         for (i = 0; i < rx_ring->count; i++) {
3696                 struct ixgbe_rx_buffer *rx_buffer_info;
3697
3698                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3699                 if (rx_buffer_info->dma) {
3700                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3701                                          rx_ring->rx_buf_len,
3702                                          DMA_FROM_DEVICE);
3703                         rx_buffer_info->dma = 0;
3704                 }
3705                 if (rx_buffer_info->skb) {
3706                         struct sk_buff *skb = rx_buffer_info->skb;
3707                         rx_buffer_info->skb = NULL;
3708                         do {
3709                                 struct sk_buff *this = skb;
3710                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3711                                         dma_unmap_single(&pdev->dev,
3712                                                          IXGBE_RSC_CB(this)->dma,
3713                                                          rx_ring->rx_buf_len,
3714                                                          DMA_FROM_DEVICE);
3715                                         IXGBE_RSC_CB(this)->dma = 0;
3716                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3717                                 }
3718                                 skb = skb->prev;
3719                                 dev_kfree_skb(this);
3720                         } while (skb);
3721                 }
3722                 if (!rx_buffer_info->page)
3723                         continue;
3724                 if (rx_buffer_info->page_dma) {
3725                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3726                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3727                         rx_buffer_info->page_dma = 0;
3728                 }
3729                 put_page(rx_buffer_info->page);
3730                 rx_buffer_info->page = NULL;
3731                 rx_buffer_info->page_offset = 0;
3732         }
3733
3734         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3735         memset(rx_ring->rx_buffer_info, 0, size);
3736
3737         /* Zero out the descriptor ring */
3738         memset(rx_ring->desc, 0, rx_ring->size);
3739
3740         rx_ring->next_to_clean = 0;
3741         rx_ring->next_to_use = 0;
3742
3743         if (rx_ring->head)
3744                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3745         if (rx_ring->tail)
3746                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3747 }
3748
3749 /**
3750  * ixgbe_clean_tx_ring - Free Tx Buffers
3751  * @adapter: board private structure
3752  * @tx_ring: ring to be cleaned
3753  **/
3754 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3755                                 struct ixgbe_ring *tx_ring)
3756 {
3757         struct ixgbe_tx_buffer *tx_buffer_info;
3758         unsigned long size;
3759         unsigned int i;
3760
3761         /* ring already cleared, nothing to do */
3762         if (!tx_ring->tx_buffer_info)
3763                 return;
3764
3765         /* Free all the Tx ring sk_buffs */
3766         for (i = 0; i < tx_ring->count; i++) {
3767                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3768                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3769         }
3770
3771         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3772         memset(tx_ring->tx_buffer_info, 0, size);
3773
3774         /* Zero out the descriptor ring */
3775         memset(tx_ring->desc, 0, tx_ring->size);
3776
3777         tx_ring->next_to_use = 0;
3778         tx_ring->next_to_clean = 0;
3779
3780         if (tx_ring->head)
3781                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3782         if (tx_ring->tail)
3783                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3784 }
3785
3786 /**
3787  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3788  * @adapter: board private structure
3789  **/
3790 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3791 {
3792         int i;
3793
3794         for (i = 0; i < adapter->num_rx_queues; i++)
3795                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3796 }
3797
3798 /**
3799  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3800  * @adapter: board private structure
3801  **/
3802 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3803 {
3804         int i;
3805
3806         for (i = 0; i < adapter->num_tx_queues; i++)
3807                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3808 }
3809
3810 void ixgbe_down(struct ixgbe_adapter *adapter)
3811 {
3812         struct net_device *netdev = adapter->netdev;
3813         struct ixgbe_hw *hw = &adapter->hw;
3814         u32 rxctrl;
3815         u32 txdctl;
3816         int i, j;
3817         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3818
3819         /* signal that we are down to the interrupt handler */
3820         set_bit(__IXGBE_DOWN, &adapter->state);
3821
3822         /* disable receive for all VFs and wait one second */
3823         if (adapter->num_vfs) {
3824                 /* ping all the active vfs to let them know we are going down */
3825                 ixgbe_ping_all_vfs(adapter);
3826
3827                 /* Disable all VFTE/VFRE TX/RX */
3828                 ixgbe_disable_tx_rx(adapter);
3829
3830                 /* Mark all the VFs as inactive */
3831                 for (i = 0 ; i < adapter->num_vfs; i++)
3832                         adapter->vfinfo[i].clear_to_send = 0;
3833         }
3834
3835         /* disable receives */
3836         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3837         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3838
3839         IXGBE_WRITE_FLUSH(hw);
3840         msleep(10);
3841
3842         netif_tx_stop_all_queues(netdev);
3843
3844         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3845         del_timer_sync(&adapter->sfp_timer);
3846         del_timer_sync(&adapter->watchdog_timer);
3847         cancel_work_sync(&adapter->watchdog_task);
3848
3849         netif_carrier_off(netdev);
3850         netif_tx_disable(netdev);
3851
3852         ixgbe_irq_disable(adapter);
3853
3854         ixgbe_napi_disable_all(adapter);
3855
3856         /* Cleanup the affinity_hint CPU mask memory and callback */
3857         for (i = 0; i < num_q_vectors; i++) {
3858                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3859                 /* clear the affinity_mask in the IRQ descriptor */
3860                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3861                 /* release the CPU mask memory */
3862                 free_cpumask_var(q_vector->affinity_mask);
3863         }
3864
3865         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3866             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3867                 cancel_work_sync(&adapter->fdir_reinit_task);
3868
3869         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3870                 cancel_work_sync(&adapter->check_overtemp_task);
3871
3872         /* disable transmits in the hardware now that interrupts are off */
3873         for (i = 0; i < adapter->num_tx_queues; i++) {
3874                 j = adapter->tx_ring[i]->reg_idx;
3875                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3876                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3877                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3878         }
3879         /* Disable the Tx DMA engine on 82599 */
3880         if (hw->mac.type == ixgbe_mac_82599EB)
3881                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3882                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3883                                  ~IXGBE_DMATXCTL_TE));
3884
3885         /* power down the optics */
3886         if (hw->phy.multispeed_fiber)
3887                 hw->mac.ops.disable_tx_laser(hw);
3888
3889         /* clear n-tuple filters that are cached */
3890         ethtool_ntuple_flush(netdev);
3891
3892         if (!pci_channel_offline(adapter->pdev))
3893                 ixgbe_reset(adapter);
3894         ixgbe_clean_all_tx_rings(adapter);
3895         ixgbe_clean_all_rx_rings(adapter);
3896
3897 #ifdef CONFIG_IXGBE_DCA
3898         /* since we reset the hardware DCA settings were cleared */
3899         ixgbe_setup_dca(adapter);
3900 #endif
3901 }
3902
3903 /**
3904  * ixgbe_poll - NAPI Rx polling callback
3905  * @napi: structure for representing this polling device
3906  * @budget: how many packets driver is allowed to clean
3907  *
3908  * This function is used for legacy and MSI, NAPI mode
3909  **/
3910 static int ixgbe_poll(struct napi_struct *napi, int budget)
3911 {
3912         struct ixgbe_q_vector *q_vector =
3913                                 container_of(napi, struct ixgbe_q_vector, napi);
3914         struct ixgbe_adapter *adapter = q_vector->adapter;
3915         int tx_clean_complete, work_done = 0;
3916
3917 #ifdef CONFIG_IXGBE_DCA
3918         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3919                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3920                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3921         }
3922 #endif
3923
3924         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3925         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3926
3927         if (!tx_clean_complete)
3928                 work_done = budget;
3929
3930         /* If budget not fully consumed, exit the polling mode */
3931         if (work_done < budget) {
3932                 napi_complete(napi);
3933                 if (adapter->rx_itr_setting & 1)
3934                         ixgbe_set_itr(adapter);
3935                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3936                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3937         }
3938         return work_done;
3939 }
3940
3941 /**
3942  * ixgbe_tx_timeout - Respond to a Tx Hang
3943  * @netdev: network interface device structure
3944  **/
3945 static void ixgbe_tx_timeout(struct net_device *netdev)
3946 {
3947         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3948
3949         /* Do the reset outside of interrupt context */
3950         schedule_work(&adapter->reset_task);
3951 }
3952
3953 static void ixgbe_reset_task(struct work_struct *work)
3954 {
3955         struct ixgbe_adapter *adapter;
3956         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3957
3958         /* If we're already down or resetting, just bail */
3959         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3960             test_bit(__IXGBE_RESETTING, &adapter->state))
3961                 return;
3962
3963         adapter->tx_timeout_count++;
3964
3965         ixgbe_dump(adapter);
3966         netdev_err(adapter->netdev, "Reset adapter\n");
3967         ixgbe_reinit_locked(adapter);
3968 }
3969
3970 #ifdef CONFIG_IXGBE_DCB
3971 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3972 {
3973         bool ret = false;
3974         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3975
3976         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3977                 return ret;
3978
3979         f->mask = 0x7 << 3;
3980         adapter->num_rx_queues = f->indices;
3981         adapter->num_tx_queues = f->indices;
3982         ret = true;
3983
3984         return ret;
3985 }
3986 #endif
3987
3988 /**
3989  * ixgbe_set_rss_queues: Allocate queues for RSS
3990  * @adapter: board private structure to initialize
3991  *
3992  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3993  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3994  *
3995  **/
3996 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3997 {
3998         bool ret = false;
3999         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4000
4001         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4002                 f->mask = 0xF;
4003                 adapter->num_rx_queues = f->indices;
4004                 adapter->num_tx_queues = f->indices;
4005                 ret = true;
4006         } else {
4007                 ret = false;
4008         }
4009
4010         return ret;
4011 }
4012
4013 /**
4014  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4015  * @adapter: board private structure to initialize
4016  *
4017  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4018  * to the original CPU that initiated the Tx session.  This runs in addition
4019  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4020  * Rx load across CPUs using RSS.
4021  *
4022  **/
4023 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4024 {
4025         bool ret = false;
4026         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4027
4028         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4029         f_fdir->mask = 0;
4030
4031         /* Flow Director must have RSS enabled */
4032         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4033             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4034              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4035                 adapter->num_tx_queues = f_fdir->indices;
4036                 adapter->num_rx_queues = f_fdir->indices;
4037                 ret = true;
4038         } else {
4039                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4040                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4041         }
4042         return ret;
4043 }
4044
4045 #ifdef IXGBE_FCOE
4046 /**
4047  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4048  * @adapter: board private structure to initialize
4049  *
4050  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4051  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4052  * rx queues out of the max number of rx queues, instead, it is used as the
4053  * index of the first rx queue used by FCoE.
4054  *
4055  **/
4056 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4057 {
4058         bool ret = false;
4059         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4060
4061         f->indices = min((int)num_online_cpus(), f->indices);
4062         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4063                 adapter->num_rx_queues = 1;
4064                 adapter->num_tx_queues = 1;
4065 #ifdef CONFIG_IXGBE_DCB
4066                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4067                         e_info(probe, "FCoE enabled with DCB\n");
4068                         ixgbe_set_dcb_queues(adapter);
4069                 }
4070 #endif
4071                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4072                         e_info(probe, "FCoE enabled with RSS\n");
4073                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4074                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4075                                 ixgbe_set_fdir_queues(adapter);
4076                         else
4077                                 ixgbe_set_rss_queues(adapter);
4078                 }
4079                 /* adding FCoE rx rings to the end */
4080                 f->mask = adapter->num_rx_queues;
4081                 adapter->num_rx_queues += f->indices;
4082                 adapter->num_tx_queues += f->indices;
4083
4084                 ret = true;
4085         }
4086
4087         return ret;
4088 }
4089
4090 #endif /* IXGBE_FCOE */
4091 /**
4092  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4093  * @adapter: board private structure to initialize
4094  *
4095  * IOV doesn't actually use anything, so just NAK the
4096  * request for now and let the other queue routines
4097  * figure out what to do.
4098  */
4099 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4100 {
4101         return false;
4102 }
4103
4104 /*
4105  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4106  * @adapter: board private structure to initialize
4107  *
4108  * This is the top level queue allocation routine.  The order here is very
4109  * important, starting with the "most" number of features turned on at once,
4110  * and ending with the smallest set of features.  This way large combinations
4111  * can be allocated if they're turned on, and smaller combinations are the
4112  * fallthrough conditions.
4113  *
4114  **/
4115 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4116 {
4117         /* Start with base case */
4118         adapter->num_rx_queues = 1;
4119         adapter->num_tx_queues = 1;
4120         adapter->num_rx_pools = adapter->num_rx_queues;
4121         adapter->num_rx_queues_per_pool = 1;
4122
4123         if (ixgbe_set_sriov_queues(adapter))
4124                 goto done;
4125
4126 #ifdef IXGBE_FCOE
4127         if (ixgbe_set_fcoe_queues(adapter))
4128                 goto done;
4129
4130 #endif /* IXGBE_FCOE */
4131 #ifdef CONFIG_IXGBE_DCB
4132         if (ixgbe_set_dcb_queues(adapter))
4133                 goto done;
4134
4135 #endif
4136         if (ixgbe_set_fdir_queues(adapter))
4137                 goto done;
4138
4139         if (ixgbe_set_rss_queues(adapter))
4140                 goto done;
4141
4142         /* fallback to base case */
4143         adapter->num_rx_queues = 1;
4144         adapter->num_tx_queues = 1;
4145
4146 done:
4147         /* Notify the stack of the (possibly) reduced queue counts. */
4148         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4149         return netif_set_real_num_rx_queues(adapter->netdev,
4150                                             adapter->num_rx_queues);
4151 }
4152
4153 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4154                                        int vectors)
4155 {
4156         int err, vector_threshold;
4157
4158         /* We'll want at least 3 (vector_threshold):
4159          * 1) TxQ[0] Cleanup
4160          * 2) RxQ[0] Cleanup
4161          * 3) Other (Link Status Change, etc.)
4162          * 4) TCP Timer (optional)
4163          */
4164         vector_threshold = MIN_MSIX_COUNT;
4165
4166         /* The more we get, the more we will assign to Tx/Rx Cleanup
4167          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4168          * Right now, we simply care about how many we'll get; we'll
4169          * set them up later while requesting irq's.
4170          */
4171         while (vectors >= vector_threshold) {
4172                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4173                                       vectors);
4174                 if (!err) /* Success in acquiring all requested vectors. */
4175                         break;
4176                 else if (err < 0)
4177                         vectors = 0; /* Nasty failure, quit now */
4178                 else /* err == number of vectors we should try again with */
4179                         vectors = err;
4180         }
4181
4182         if (vectors < vector_threshold) {
4183                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4184                  * This just means we'll go with either a single MSI
4185                  * vector or fall back to legacy interrupts.
4186                  */
4187                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4188                              "Unable to allocate MSI-X interrupts\n");
4189                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4190                 kfree(adapter->msix_entries);
4191                 adapter->msix_entries = NULL;
4192         } else {
4193                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4194                 /*
4195                  * Adjust for only the vectors we'll use, which is minimum
4196                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4197                  * vectors we were allocated.
4198                  */
4199                 adapter->num_msix_vectors = min(vectors,
4200                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4201         }
4202 }
4203
4204 /**
4205  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4206  * @adapter: board private structure to initialize
4207  *
4208  * Cache the descriptor ring offsets for RSS to the assigned rings.
4209  *
4210  **/
4211 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4212 {
4213         int i;
4214         bool ret = false;
4215
4216         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4217                 for (i = 0; i < adapter->num_rx_queues; i++)
4218                         adapter->rx_ring[i]->reg_idx = i;
4219                 for (i = 0; i < adapter->num_tx_queues; i++)
4220                         adapter->tx_ring[i]->reg_idx = i;
4221                 ret = true;
4222         } else {
4223                 ret = false;
4224         }
4225
4226         return ret;
4227 }
4228
4229 #ifdef CONFIG_IXGBE_DCB
4230 /**
4231  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4232  * @adapter: board private structure to initialize
4233  *
4234  * Cache the descriptor ring offsets for DCB to the assigned rings.
4235  *
4236  **/
4237 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4238 {
4239         int i;
4240         bool ret = false;
4241         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4242
4243         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4244                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4245                         /* the number of queues is assumed to be symmetric */
4246                         for (i = 0; i < dcb_i; i++) {
4247                                 adapter->rx_ring[i]->reg_idx = i << 3;
4248                                 adapter->tx_ring[i]->reg_idx = i << 2;
4249                         }
4250                         ret = true;
4251                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4252                         if (dcb_i == 8) {
4253                                 /*
4254                                  * Tx TC0 starts at: descriptor queue 0
4255                                  * Tx TC1 starts at: descriptor queue 32
4256                                  * Tx TC2 starts at: descriptor queue 64
4257                                  * Tx TC3 starts at: descriptor queue 80
4258                                  * Tx TC4 starts at: descriptor queue 96
4259                                  * Tx TC5 starts at: descriptor queue 104
4260                                  * Tx TC6 starts at: descriptor queue 112
4261                                  * Tx TC7 starts at: descriptor queue 120
4262                                  *
4263                                  * Rx TC0-TC7 are offset by 16 queues each
4264                                  */
4265                                 for (i = 0; i < 3; i++) {
4266                                         adapter->tx_ring[i]->reg_idx = i << 5;
4267                                         adapter->rx_ring[i]->reg_idx = i << 4;
4268                                 }
4269                                 for ( ; i < 5; i++) {
4270                                         adapter->tx_ring[i]->reg_idx =
4271                                                                  ((i + 2) << 4);
4272                                         adapter->rx_ring[i]->reg_idx = i << 4;
4273                                 }
4274                                 for ( ; i < dcb_i; i++) {
4275                                         adapter->tx_ring[i]->reg_idx =
4276                                                                  ((i + 8) << 3);
4277                                         adapter->rx_ring[i]->reg_idx = i << 4;
4278                                 }
4279
4280                                 ret = true;
4281                         } else if (dcb_i == 4) {
4282                                 /*
4283                                  * Tx TC0 starts at: descriptor queue 0
4284                                  * Tx TC1 starts at: descriptor queue 64
4285                                  * Tx TC2 starts at: descriptor queue 96
4286                                  * Tx TC3 starts at: descriptor queue 112
4287                                  *
4288                                  * Rx TC0-TC3 are offset by 32 queues each
4289                                  */
4290                                 adapter->tx_ring[0]->reg_idx = 0;
4291                                 adapter->tx_ring[1]->reg_idx = 64;
4292                                 adapter->tx_ring[2]->reg_idx = 96;
4293                                 adapter->tx_ring[3]->reg_idx = 112;
4294                                 for (i = 0 ; i < dcb_i; i++)
4295                                         adapter->rx_ring[i]->reg_idx = i << 5;
4296
4297                                 ret = true;
4298                         } else {
4299                                 ret = false;
4300                         }
4301                 } else {
4302                         ret = false;
4303                 }
4304         } else {
4305                 ret = false;
4306         }
4307
4308         return ret;
4309 }
4310 #endif
4311
4312 /**
4313  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4314  * @adapter: board private structure to initialize
4315  *
4316  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4317  *
4318  **/
4319 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4320 {
4321         int i;
4322         bool ret = false;
4323
4324         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4325             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4326              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4327                 for (i = 0; i < adapter->num_rx_queues; i++)
4328                         adapter->rx_ring[i]->reg_idx = i;
4329                 for (i = 0; i < adapter->num_tx_queues; i++)
4330                         adapter->tx_ring[i]->reg_idx = i;
4331                 ret = true;
4332         }
4333
4334         return ret;
4335 }
4336
4337 #ifdef IXGBE_FCOE
4338 /**
4339  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4340  * @adapter: board private structure to initialize
4341  *
4342  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4343  *
4344  */
4345 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4346 {
4347         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4348         bool ret = false;
4349         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4350
4351         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4352 #ifdef CONFIG_IXGBE_DCB
4353                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4354                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4355
4356                         ixgbe_cache_ring_dcb(adapter);
4357                         /* find out queues in TC for FCoE */
4358                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4359                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4360                         /*
4361                          * In 82599, the number of Tx queues for each traffic
4362                          * class for both 8-TC and 4-TC modes are:
4363                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4364                          * 8 TCs:  32  32  16  16   8   8   8   8
4365                          * 4 TCs:  64  64  32  32
4366                          * We have max 8 queues for FCoE, where 8 the is
4367                          * FCoE redirection table size. If TC for FCoE is
4368                          * less than or equal to TC3, we have enough queues
4369                          * to add max of 8 queues for FCoE, so we start FCoE
4370                          * tx descriptor from the next one, i.e., reg_idx + 1.
4371                          * If TC for FCoE is above TC3, implying 8 TC mode,
4372                          * and we need 8 for FCoE, we have to take all queues
4373                          * in that traffic class for FCoE.
4374                          */
4375                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4376                                 fcoe_tx_i--;
4377                 }
4378 #endif /* CONFIG_IXGBE_DCB */
4379                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4380                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4381                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4382                                 ixgbe_cache_ring_fdir(adapter);
4383                         else
4384                                 ixgbe_cache_ring_rss(adapter);
4385
4386                         fcoe_rx_i = f->mask;
4387                         fcoe_tx_i = f->mask;
4388                 }
4389                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4390                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4391                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4392                 }
4393                 ret = true;
4394         }
4395         return ret;
4396 }
4397
4398 #endif /* IXGBE_FCOE */
4399 /**
4400  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4401  * @adapter: board private structure to initialize
4402  *
4403  * SR-IOV doesn't use any descriptor rings but changes the default if
4404  * no other mapping is used.
4405  *
4406  */
4407 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4408 {
4409         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4410         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4411         if (adapter->num_vfs)
4412                 return true;
4413         else
4414                 return false;
4415 }
4416
4417 /**
4418  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4419  * @adapter: board private structure to initialize
4420  *
4421  * Once we know the feature-set enabled for the device, we'll cache
4422  * the register offset the descriptor ring is assigned to.
4423  *
4424  * Note, the order the various feature calls is important.  It must start with
4425  * the "most" features enabled at the same time, then trickle down to the
4426  * least amount of features turned on at once.
4427  **/
4428 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4429 {
4430         /* start with default case */
4431         adapter->rx_ring[0]->reg_idx = 0;
4432         adapter->tx_ring[0]->reg_idx = 0;
4433
4434         if (ixgbe_cache_ring_sriov(adapter))
4435                 return;
4436
4437 #ifdef IXGBE_FCOE
4438         if (ixgbe_cache_ring_fcoe(adapter))
4439                 return;
4440
4441 #endif /* IXGBE_FCOE */
4442 #ifdef CONFIG_IXGBE_DCB
4443         if (ixgbe_cache_ring_dcb(adapter))
4444                 return;
4445
4446 #endif
4447         if (ixgbe_cache_ring_fdir(adapter))
4448                 return;
4449
4450         if (ixgbe_cache_ring_rss(adapter))
4451                 return;
4452 }
4453
4454 /**
4455  * ixgbe_alloc_queues - Allocate memory for all rings
4456  * @adapter: board private structure to initialize
4457  *
4458  * We allocate one ring per queue at run-time since we don't know the
4459  * number of queues at compile-time.  The polling_netdev array is
4460  * intended for Multiqueue, but should work fine with a single queue.
4461  **/
4462 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4463 {
4464         int i;
4465         int orig_node = adapter->node;
4466
4467         for (i = 0; i < adapter->num_tx_queues; i++) {
4468                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4469                 if (orig_node == -1) {
4470                         int cur_node = next_online_node(adapter->node);
4471                         if (cur_node == MAX_NUMNODES)
4472                                 cur_node = first_online_node;
4473                         adapter->node = cur_node;
4474                 }
4475                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4476                                     adapter->node);
4477                 if (!ring)
4478                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4479                 if (!ring)
4480                         goto err_tx_ring_allocation;
4481                 ring->count = adapter->tx_ring_count;
4482                 ring->queue_index = i;
4483                 ring->numa_node = adapter->node;
4484
4485                 adapter->tx_ring[i] = ring;
4486         }
4487
4488         /* Restore the adapter's original node */
4489         adapter->node = orig_node;
4490
4491         for (i = 0; i < adapter->num_rx_queues; i++) {
4492                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4493                 if (orig_node == -1) {
4494                         int cur_node = next_online_node(adapter->node);
4495                         if (cur_node == MAX_NUMNODES)
4496                                 cur_node = first_online_node;
4497                         adapter->node = cur_node;
4498                 }
4499                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4500                                     adapter->node);
4501                 if (!ring)
4502                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4503                 if (!ring)
4504                         goto err_rx_ring_allocation;
4505                 ring->count = adapter->rx_ring_count;
4506                 ring->queue_index = i;
4507                 ring->numa_node = adapter->node;
4508
4509                 adapter->rx_ring[i] = ring;
4510         }
4511
4512         /* Restore the adapter's original node */
4513         adapter->node = orig_node;
4514
4515         ixgbe_cache_ring_register(adapter);
4516
4517         return 0;
4518
4519 err_rx_ring_allocation:
4520         for (i = 0; i < adapter->num_tx_queues; i++)
4521                 kfree(adapter->tx_ring[i]);
4522 err_tx_ring_allocation:
4523         return -ENOMEM;
4524 }
4525
4526 /**
4527  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4528  * @adapter: board private structure to initialize
4529  *
4530  * Attempt to configure the interrupts using the best available
4531  * capabilities of the hardware and the kernel.
4532  **/
4533 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4534 {
4535         struct ixgbe_hw *hw = &adapter->hw;
4536         int err = 0;
4537         int vector, v_budget;
4538
4539         /*
4540          * It's easy to be greedy for MSI-X vectors, but it really
4541          * doesn't do us much good if we have a lot more vectors
4542          * than CPU's.  So let's be conservative and only ask for
4543          * (roughly) the same number of vectors as there are CPU's.
4544          */
4545         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4546                        (int)num_online_cpus()) + NON_Q_VECTORS;
4547
4548         /*
4549          * At the same time, hardware can only support a maximum of
4550          * hw.mac->max_msix_vectors vectors.  With features
4551          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4552          * descriptor queues supported by our device.  Thus, we cap it off in
4553          * those rare cases where the cpu count also exceeds our vector limit.
4554          */
4555         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4556
4557         /* A failure in MSI-X entry allocation isn't fatal, but it does
4558          * mean we disable MSI-X capabilities of the adapter. */
4559         adapter->msix_entries = kcalloc(v_budget,
4560                                         sizeof(struct msix_entry), GFP_KERNEL);
4561         if (adapter->msix_entries) {
4562                 for (vector = 0; vector < v_budget; vector++)
4563                         adapter->msix_entries[vector].entry = vector;
4564
4565                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4566
4567                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4568                         goto out;
4569         }
4570
4571         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4572         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4573         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4574         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4575         adapter->atr_sample_rate = 0;
4576         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4577                 ixgbe_disable_sriov(adapter);
4578
4579         err = ixgbe_set_num_queues(adapter);
4580         if (err)
4581                 return err;
4582
4583         err = pci_enable_msi(adapter->pdev);
4584         if (!err) {
4585                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4586         } else {
4587                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4588                              "Unable to allocate MSI interrupt, "
4589                              "falling back to legacy.  Error: %d\n", err);
4590                 /* reset err */
4591                 err = 0;
4592         }
4593
4594 out:
4595         return err;
4596 }
4597
4598 /**
4599  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4600  * @adapter: board private structure to initialize
4601  *
4602  * We allocate one q_vector per queue interrupt.  If allocation fails we
4603  * return -ENOMEM.
4604  **/
4605 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4606 {
4607         int q_idx, num_q_vectors;
4608         struct ixgbe_q_vector *q_vector;
4609         int napi_vectors;
4610         int (*poll)(struct napi_struct *, int);
4611
4612         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4613                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4614                 napi_vectors = adapter->num_rx_queues;
4615                 poll = &ixgbe_clean_rxtx_many;
4616         } else {
4617                 num_q_vectors = 1;
4618                 napi_vectors = 1;
4619                 poll = &ixgbe_poll;
4620         }
4621
4622         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4623                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4624                                         GFP_KERNEL, adapter->node);
4625                 if (!q_vector)
4626                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4627                                            GFP_KERNEL);
4628                 if (!q_vector)
4629                         goto err_out;
4630                 q_vector->adapter = adapter;
4631                 if (q_vector->txr_count && !q_vector->rxr_count)
4632                         q_vector->eitr = adapter->tx_eitr_param;
4633                 else
4634                         q_vector->eitr = adapter->rx_eitr_param;
4635                 q_vector->v_idx = q_idx;
4636                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4637                 adapter->q_vector[q_idx] = q_vector;
4638         }
4639
4640         return 0;
4641
4642 err_out:
4643         while (q_idx) {
4644                 q_idx--;
4645                 q_vector = adapter->q_vector[q_idx];
4646                 netif_napi_del(&q_vector->napi);
4647                 kfree(q_vector);
4648                 adapter->q_vector[q_idx] = NULL;
4649         }
4650         return -ENOMEM;
4651 }
4652
4653 /**
4654  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4655  * @adapter: board private structure to initialize
4656  *
4657  * This function frees the memory allocated to the q_vectors.  In addition if
4658  * NAPI is enabled it will delete any references to the NAPI struct prior
4659  * to freeing the q_vector.
4660  **/
4661 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4662 {
4663         int q_idx, num_q_vectors;
4664
4665         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4666                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4667         else
4668                 num_q_vectors = 1;
4669
4670         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4671                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4672                 adapter->q_vector[q_idx] = NULL;
4673                 netif_napi_del(&q_vector->napi);
4674                 kfree(q_vector);
4675         }
4676 }
4677
4678 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4679 {
4680         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4681                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4682                 pci_disable_msix(adapter->pdev);
4683                 kfree(adapter->msix_entries);
4684                 adapter->msix_entries = NULL;
4685         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4686                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4687                 pci_disable_msi(adapter->pdev);
4688         }
4689 }
4690
4691 /**
4692  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4693  * @adapter: board private structure to initialize
4694  *
4695  * We determine which interrupt scheme to use based on...
4696  * - Kernel support (MSI, MSI-X)
4697  *   - which can be user-defined (via MODULE_PARAM)
4698  * - Hardware queue count (num_*_queues)
4699  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4700  **/
4701 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4702 {
4703         int err;
4704
4705         /* Number of supported queues */
4706         err = ixgbe_set_num_queues(adapter);
4707         if (err)
4708                 return err;
4709
4710         err = ixgbe_set_interrupt_capability(adapter);
4711         if (err) {
4712                 e_dev_err("Unable to setup interrupt capabilities\n");
4713                 goto err_set_interrupt;
4714         }
4715
4716         err = ixgbe_alloc_q_vectors(adapter);
4717         if (err) {
4718                 e_dev_err("Unable to allocate memory for queue vectors\n");
4719                 goto err_alloc_q_vectors;
4720         }
4721
4722         err = ixgbe_alloc_queues(adapter);
4723         if (err) {
4724                 e_dev_err("Unable to allocate memory for queues\n");
4725                 goto err_alloc_queues;
4726         }
4727
4728         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4729                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4730                    adapter->num_rx_queues, adapter->num_tx_queues);
4731
4732         set_bit(__IXGBE_DOWN, &adapter->state);
4733
4734         return 0;
4735
4736 err_alloc_queues:
4737         ixgbe_free_q_vectors(adapter);
4738 err_alloc_q_vectors:
4739         ixgbe_reset_interrupt_capability(adapter);
4740 err_set_interrupt:
4741         return err;
4742 }
4743
4744 /**
4745  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4746  * @adapter: board private structure to clear interrupt scheme on
4747  *
4748  * We go through and clear interrupt specific resources and reset the structure
4749  * to pre-load conditions
4750  **/
4751 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4752 {
4753         int i;
4754
4755         for (i = 0; i < adapter->num_tx_queues; i++) {
4756                 kfree(adapter->tx_ring[i]);
4757                 adapter->tx_ring[i] = NULL;
4758         }
4759         for (i = 0; i < adapter->num_rx_queues; i++) {
4760                 kfree(adapter->rx_ring[i]);
4761                 adapter->rx_ring[i] = NULL;
4762         }
4763
4764         ixgbe_free_q_vectors(adapter);
4765         ixgbe_reset_interrupt_capability(adapter);
4766 }
4767
4768 /**
4769  * ixgbe_sfp_timer - worker thread to find a missing module
4770  * @data: pointer to our adapter struct
4771  **/
4772 static void ixgbe_sfp_timer(unsigned long data)
4773 {
4774         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4775
4776         /*
4777          * Do the sfp_timer outside of interrupt context due to the
4778          * delays that sfp+ detection requires
4779          */
4780         schedule_work(&adapter->sfp_task);
4781 }
4782
4783 /**
4784  * ixgbe_sfp_task - worker thread to find a missing module
4785  * @work: pointer to work_struct containing our data
4786  **/
4787 static void ixgbe_sfp_task(struct work_struct *work)
4788 {
4789         struct ixgbe_adapter *adapter = container_of(work,
4790                                                      struct ixgbe_adapter,
4791                                                      sfp_task);
4792         struct ixgbe_hw *hw = &adapter->hw;
4793
4794         if ((hw->phy.type == ixgbe_phy_nl) &&
4795             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4796                 s32 ret = hw->phy.ops.identify_sfp(hw);
4797                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4798                         goto reschedule;
4799                 ret = hw->phy.ops.reset(hw);
4800                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4801                         e_dev_err("failed to initialize because an unsupported "
4802                                   "SFP+ module type was detected.\n");
4803                         e_dev_err("Reload the driver after installing a "
4804                                   "supported module.\n");
4805                         unregister_netdev(adapter->netdev);
4806                 } else {
4807                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4808                 }
4809                 /* don't need this routine any more */
4810                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4811         }
4812         return;
4813 reschedule:
4814         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4815                 mod_timer(&adapter->sfp_timer,
4816                           round_jiffies(jiffies + (2 * HZ)));
4817 }
4818
4819 /**
4820  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4821  * @adapter: board private structure to initialize
4822  *
4823  * ixgbe_sw_init initializes the Adapter private data structure.
4824  * Fields are initialized based on PCI device information and
4825  * OS network device settings (MTU size).
4826  **/
4827 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4828 {
4829         struct ixgbe_hw *hw = &adapter->hw;
4830         struct pci_dev *pdev = adapter->pdev;
4831         struct net_device *dev = adapter->netdev;
4832         unsigned int rss;
4833 #ifdef CONFIG_IXGBE_DCB
4834         int j;
4835         struct tc_configuration *tc;
4836 #endif
4837
4838         /* PCI config space info */
4839
4840         hw->vendor_id = pdev->vendor;
4841         hw->device_id = pdev->device;
4842         hw->revision_id = pdev->revision;
4843         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4844         hw->subsystem_device_id = pdev->subsystem_device;
4845
4846         /* Set capability flags */
4847         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4848         adapter->ring_feature[RING_F_RSS].indices = rss;
4849         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4850         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4851         if (hw->mac.type == ixgbe_mac_82598EB) {
4852                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4853                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4854                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4855         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4856                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4857                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4858                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4859                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4860                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4861                 if (dev->features & NETIF_F_NTUPLE) {
4862                         /* Flow Director perfect filter enabled */
4863                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4864                         adapter->atr_sample_rate = 0;
4865                         spin_lock_init(&adapter->fdir_perfect_lock);
4866                 } else {
4867                         /* Flow Director hash filters enabled */
4868                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4869                         adapter->atr_sample_rate = 20;
4870                 }
4871                 adapter->ring_feature[RING_F_FDIR].indices =
4872                                                          IXGBE_MAX_FDIR_INDICES;
4873                 adapter->fdir_pballoc = 0;
4874 #ifdef IXGBE_FCOE
4875                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4876                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4877                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4878 #ifdef CONFIG_IXGBE_DCB
4879                 /* Default traffic class to use for FCoE */
4880                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4881                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4882 #endif
4883 #endif /* IXGBE_FCOE */
4884         }
4885
4886 #ifdef CONFIG_IXGBE_DCB
4887         /* Configure DCB traffic classes */
4888         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4889                 tc = &adapter->dcb_cfg.tc_config[j];
4890                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4891                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4892                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4893                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4894                 tc->dcb_pfc = pfc_disabled;
4895         }
4896         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4897         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4898         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4899         adapter->dcb_cfg.pfc_mode_enable = false;
4900         adapter->dcb_cfg.round_robin_enable = false;
4901         adapter->dcb_set_bitmap = 0x00;
4902         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4903                            adapter->ring_feature[RING_F_DCB].indices);
4904
4905 #endif
4906
4907         /* default flow control settings */
4908         hw->fc.requested_mode = ixgbe_fc_full;
4909         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4910 #ifdef CONFIG_DCB
4911         adapter->last_lfc_mode = hw->fc.current_mode;
4912 #endif
4913         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4914         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4915         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4916         hw->fc.send_xon = true;
4917         hw->fc.disable_fc_autoneg = false;
4918
4919         /* enable itr by default in dynamic mode */
4920         adapter->rx_itr_setting = 1;
4921         adapter->rx_eitr_param = 20000;
4922         adapter->tx_itr_setting = 1;
4923         adapter->tx_eitr_param = 10000;
4924
4925         /* set defaults for eitr in MegaBytes */
4926         adapter->eitr_low = 10;
4927         adapter->eitr_high = 20;
4928
4929         /* set default ring sizes */
4930         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4931         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4932
4933         /* initialize eeprom parameters */
4934         if (ixgbe_init_eeprom_params_generic(hw)) {
4935                 e_dev_err("EEPROM initialization failed\n");
4936                 return -EIO;
4937         }
4938
4939         /* enable rx csum by default */
4940         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4941
4942         /* get assigned NUMA node */
4943         adapter->node = dev_to_node(&pdev->dev);
4944
4945         set_bit(__IXGBE_DOWN, &adapter->state);
4946
4947         return 0;
4948 }
4949
4950 /**
4951  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4952  * @adapter: board private structure
4953  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4954  *
4955  * Return 0 on success, negative on failure
4956  **/
4957 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4958                              struct ixgbe_ring *tx_ring)
4959 {
4960         struct pci_dev *pdev = adapter->pdev;
4961         int size;
4962
4963         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4964         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4965         if (!tx_ring->tx_buffer_info)
4966                 tx_ring->tx_buffer_info = vmalloc(size);
4967         if (!tx_ring->tx_buffer_info)
4968                 goto err;
4969         memset(tx_ring->tx_buffer_info, 0, size);
4970
4971         /* round up to nearest 4K */
4972         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4973         tx_ring->size = ALIGN(tx_ring->size, 4096);
4974
4975         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4976                                            &tx_ring->dma, GFP_KERNEL);
4977         if (!tx_ring->desc)
4978                 goto err;
4979
4980         tx_ring->next_to_use = 0;
4981         tx_ring->next_to_clean = 0;
4982         tx_ring->work_limit = tx_ring->count;
4983         return 0;
4984
4985 err:
4986         vfree(tx_ring->tx_buffer_info);
4987         tx_ring->tx_buffer_info = NULL;
4988         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4989         return -ENOMEM;
4990 }
4991
4992 /**
4993  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4994  * @adapter: board private structure
4995  *
4996  * If this function returns with an error, then it's possible one or
4997  * more of the rings is populated (while the rest are not).  It is the
4998  * callers duty to clean those orphaned rings.
4999  *
5000  * Return 0 on success, negative on failure
5001  **/
5002 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5003 {
5004         int i, err = 0;
5005
5006         for (i = 0; i < adapter->num_tx_queues; i++) {
5007                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
5008                 if (!err)
5009                         continue;
5010                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5011                 break;
5012         }
5013
5014         return err;
5015 }
5016
5017 /**
5018  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5019  * @adapter: board private structure
5020  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5021  *
5022  * Returns 0 on success, negative on failure
5023  **/
5024 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
5025                              struct ixgbe_ring *rx_ring)
5026 {
5027         struct pci_dev *pdev = adapter->pdev;
5028         int size;
5029
5030         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5031         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5032         if (!rx_ring->rx_buffer_info)
5033                 rx_ring->rx_buffer_info = vmalloc(size);
5034         if (!rx_ring->rx_buffer_info) {
5035                 e_err(probe, "vmalloc allocation failed for the Rx "
5036                       "descriptor ring\n");
5037                 goto alloc_failed;
5038         }
5039         memset(rx_ring->rx_buffer_info, 0, size);
5040
5041         /* Round up to nearest 4K */
5042         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5043         rx_ring->size = ALIGN(rx_ring->size, 4096);
5044
5045         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5046                                            &rx_ring->dma, GFP_KERNEL);
5047
5048         if (!rx_ring->desc) {
5049                 e_err(probe, "Memory allocation failed for the Rx "
5050                       "descriptor ring\n");
5051                 vfree(rx_ring->rx_buffer_info);
5052                 goto alloc_failed;
5053         }
5054
5055         rx_ring->next_to_clean = 0;
5056         rx_ring->next_to_use = 0;
5057
5058         return 0;
5059
5060 alloc_failed:
5061         return -ENOMEM;
5062 }
5063
5064 /**
5065  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5066  * @adapter: board private structure
5067  *
5068  * If this function returns with an error, then it's possible one or
5069  * more of the rings is populated (while the rest are not).  It is the
5070  * callers duty to clean those orphaned rings.
5071  *
5072  * Return 0 on success, negative on failure
5073  **/
5074
5075 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5076 {
5077         int i, err = 0;
5078
5079         for (i = 0; i < adapter->num_rx_queues; i++) {
5080                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
5081                 if (!err)
5082                         continue;
5083                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5084                 break;
5085         }
5086
5087         return err;
5088 }
5089
5090 /**
5091  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5092  * @adapter: board private structure
5093  * @tx_ring: Tx descriptor ring for a specific queue
5094  *
5095  * Free all transmit software resources
5096  **/
5097 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5098                              struct ixgbe_ring *tx_ring)
5099 {
5100         struct pci_dev *pdev = adapter->pdev;
5101
5102         ixgbe_clean_tx_ring(adapter, tx_ring);
5103
5104         vfree(tx_ring->tx_buffer_info);
5105         tx_ring->tx_buffer_info = NULL;
5106
5107         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5108                           tx_ring->dma);
5109
5110         tx_ring->desc = NULL;
5111 }
5112
5113 /**
5114  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5115  * @adapter: board private structure
5116  *
5117  * Free all transmit software resources
5118  **/
5119 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5120 {
5121         int i;
5122
5123         for (i = 0; i < adapter->num_tx_queues; i++)
5124                 if (adapter->tx_ring[i]->desc)
5125                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5126 }
5127
5128 /**
5129  * ixgbe_free_rx_resources - Free Rx Resources
5130  * @adapter: board private structure
5131  * @rx_ring: ring to clean the resources from
5132  *
5133  * Free all receive software resources
5134  **/
5135 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5136                              struct ixgbe_ring *rx_ring)
5137 {
5138         struct pci_dev *pdev = adapter->pdev;
5139
5140         ixgbe_clean_rx_ring(adapter, rx_ring);
5141
5142         vfree(rx_ring->rx_buffer_info);
5143         rx_ring->rx_buffer_info = NULL;
5144
5145         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5146                           rx_ring->dma);
5147
5148         rx_ring->desc = NULL;
5149 }
5150
5151 /**
5152  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5153  * @adapter: board private structure
5154  *
5155  * Free all receive software resources
5156  **/
5157 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5158 {
5159         int i;
5160
5161         for (i = 0; i < adapter->num_rx_queues; i++)
5162                 if (adapter->rx_ring[i]->desc)
5163                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5164 }
5165
5166 /**
5167  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5168  * @netdev: network interface device structure
5169  * @new_mtu: new value for maximum frame size
5170  *
5171  * Returns 0 on success, negative on failure
5172  **/
5173 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5174 {
5175         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5176         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5177
5178         /* MTU < 68 is an error and causes problems on some kernels */
5179         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5180                 return -EINVAL;
5181
5182         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5183         /* must set new MTU before calling down or up */
5184         netdev->mtu = new_mtu;
5185
5186         if (netif_running(netdev))
5187                 ixgbe_reinit_locked(adapter);
5188
5189         return 0;
5190 }
5191
5192 /**
5193  * ixgbe_open - Called when a network interface is made active
5194  * @netdev: network interface device structure
5195  *
5196  * Returns 0 on success, negative value on failure
5197  *
5198  * The open entry point is called when a network interface is made
5199  * active by the system (IFF_UP).  At this point all resources needed
5200  * for transmit and receive operations are allocated, the interrupt
5201  * handler is registered with the OS, the watchdog timer is started,
5202  * and the stack is notified that the interface is ready.
5203  **/
5204 static int ixgbe_open(struct net_device *netdev)
5205 {
5206         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5207         int err;
5208
5209         /* disallow open during test */
5210         if (test_bit(__IXGBE_TESTING, &adapter->state))
5211                 return -EBUSY;
5212
5213         netif_carrier_off(netdev);
5214
5215         /* allocate transmit descriptors */
5216         err = ixgbe_setup_all_tx_resources(adapter);
5217         if (err)
5218                 goto err_setup_tx;
5219
5220         /* allocate receive descriptors */
5221         err = ixgbe_setup_all_rx_resources(adapter);
5222         if (err)
5223                 goto err_setup_rx;
5224
5225         ixgbe_configure(adapter);
5226
5227         err = ixgbe_request_irq(adapter);
5228         if (err)
5229                 goto err_req_irq;
5230
5231         err = ixgbe_up_complete(adapter);
5232         if (err)
5233                 goto err_up;
5234
5235         netif_tx_start_all_queues(netdev);
5236
5237         return 0;
5238
5239 err_up:
5240         ixgbe_release_hw_control(adapter);
5241         ixgbe_free_irq(adapter);
5242 err_req_irq:
5243 err_setup_rx:
5244         ixgbe_free_all_rx_resources(adapter);
5245 err_setup_tx:
5246         ixgbe_free_all_tx_resources(adapter);
5247         ixgbe_reset(adapter);
5248
5249         return err;
5250 }
5251
5252 /**
5253  * ixgbe_close - Disables a network interface
5254  * @netdev: network interface device structure
5255  *
5256  * Returns 0, this is not allowed to fail
5257  *
5258  * The close entry point is called when an interface is de-activated
5259  * by the OS.  The hardware is still under the drivers control, but
5260  * needs to be disabled.  A global MAC reset is issued to stop the
5261  * hardware, and all transmit and receive resources are freed.
5262  **/
5263 static int ixgbe_close(struct net_device *netdev)
5264 {
5265         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5266
5267         ixgbe_down(adapter);
5268         ixgbe_free_irq(adapter);
5269
5270         ixgbe_free_all_tx_resources(adapter);
5271         ixgbe_free_all_rx_resources(adapter);
5272
5273         ixgbe_release_hw_control(adapter);
5274
5275         return 0;
5276 }
5277
5278 #ifdef CONFIG_PM
5279 static int ixgbe_resume(struct pci_dev *pdev)
5280 {
5281         struct net_device *netdev = pci_get_drvdata(pdev);
5282         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5283         u32 err;
5284
5285         pci_set_power_state(pdev, PCI_D0);
5286         pci_restore_state(pdev);
5287         /*
5288          * pci_restore_state clears dev->state_saved so call
5289          * pci_save_state to restore it.
5290          */
5291         pci_save_state(pdev);
5292
5293         err = pci_enable_device_mem(pdev);
5294         if (err) {
5295                 e_dev_err("Cannot enable PCI device from suspend\n");
5296                 return err;
5297         }
5298         pci_set_master(pdev);
5299
5300         pci_wake_from_d3(pdev, false);
5301
5302         err = ixgbe_init_interrupt_scheme(adapter);
5303         if (err) {
5304                 e_dev_err("Cannot initialize interrupts for device\n");
5305                 return err;
5306         }
5307
5308         ixgbe_reset(adapter);
5309
5310         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5311
5312         if (netif_running(netdev)) {
5313                 err = ixgbe_open(adapter->netdev);
5314                 if (err)
5315                         return err;
5316         }
5317
5318         netif_device_attach(netdev);
5319
5320         return 0;
5321 }
5322 #endif /* CONFIG_PM */
5323
5324 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5325 {
5326         struct net_device *netdev = pci_get_drvdata(pdev);
5327         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5328         struct ixgbe_hw *hw = &adapter->hw;
5329         u32 ctrl, fctrl;
5330         u32 wufc = adapter->wol;
5331 #ifdef CONFIG_PM
5332         int retval = 0;
5333 #endif
5334
5335         netif_device_detach(netdev);
5336
5337         if (netif_running(netdev)) {
5338                 ixgbe_down(adapter);
5339                 ixgbe_free_irq(adapter);
5340                 ixgbe_free_all_tx_resources(adapter);
5341                 ixgbe_free_all_rx_resources(adapter);
5342         }
5343
5344 #ifdef CONFIG_PM
5345         retval = pci_save_state(pdev);
5346         if (retval)
5347                 return retval;
5348
5349 #endif
5350         if (wufc) {
5351                 ixgbe_set_rx_mode(netdev);
5352
5353                 /* turn on all-multi mode if wake on multicast is enabled */
5354                 if (wufc & IXGBE_WUFC_MC) {
5355                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5356                         fctrl |= IXGBE_FCTRL_MPE;
5357                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5358                 }
5359
5360                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5361                 ctrl |= IXGBE_CTRL_GIO_DIS;
5362                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5363
5364                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5365         } else {
5366                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5367                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5368         }
5369
5370         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5371                 pci_wake_from_d3(pdev, true);
5372         else
5373                 pci_wake_from_d3(pdev, false);
5374
5375         *enable_wake = !!wufc;
5376
5377         ixgbe_clear_interrupt_scheme(adapter);
5378
5379         ixgbe_release_hw_control(adapter);
5380
5381         pci_disable_device(pdev);
5382
5383         return 0;
5384 }
5385
5386 #ifdef CONFIG_PM
5387 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5388 {
5389         int retval;
5390         bool wake;
5391
5392         retval = __ixgbe_shutdown(pdev, &wake);
5393         if (retval)
5394                 return retval;
5395
5396         if (wake) {
5397                 pci_prepare_to_sleep(pdev);
5398         } else {
5399                 pci_wake_from_d3(pdev, false);
5400                 pci_set_power_state(pdev, PCI_D3hot);
5401         }
5402
5403         return 0;
5404 }
5405 #endif /* CONFIG_PM */
5406
5407 static void ixgbe_shutdown(struct pci_dev *pdev)
5408 {
5409         bool wake;
5410
5411         __ixgbe_shutdown(pdev, &wake);
5412
5413         if (system_state == SYSTEM_POWER_OFF) {
5414                 pci_wake_from_d3(pdev, wake);
5415                 pci_set_power_state(pdev, PCI_D3hot);
5416         }
5417 }
5418
5419 /**
5420  * ixgbe_update_stats - Update the board statistics counters.
5421  * @adapter: board private structure
5422  **/
5423 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5424 {
5425         struct net_device *netdev = adapter->netdev;
5426         struct ixgbe_hw *hw = &adapter->hw;
5427         u64 total_mpc = 0;
5428         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5429         u64 non_eop_descs = 0, restart_queue = 0;
5430         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5431
5432         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5433             test_bit(__IXGBE_RESETTING, &adapter->state))
5434                 return;
5435
5436         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5437                 u64 rsc_count = 0;
5438                 u64 rsc_flush = 0;
5439                 for (i = 0; i < 16; i++)
5440                         adapter->hw_rx_no_dma_resources +=
5441                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5442                 for (i = 0; i < adapter->num_rx_queues; i++) {
5443                         rsc_count += adapter->rx_ring[i]->rsc_count;
5444                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5445                 }
5446                 adapter->rsc_total_count = rsc_count;
5447                 adapter->rsc_total_flush = rsc_flush;
5448         }
5449
5450         /* gather some stats to the adapter struct that are per queue */
5451         for (i = 0; i < adapter->num_tx_queues; i++)
5452                 restart_queue += adapter->tx_ring[i]->restart_queue;
5453         adapter->restart_queue = restart_queue;
5454
5455         for (i = 0; i < adapter->num_rx_queues; i++)
5456                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5457         adapter->non_eop_descs = non_eop_descs;
5458
5459         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5460         for (i = 0; i < 8; i++) {
5461                 /* for packet buffers not used, the register should read 0 */
5462                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5463                 missed_rx += mpc;
5464                 hwstats->mpc[i] += mpc;
5465                 total_mpc += hwstats->mpc[i];
5466                 if (hw->mac.type == ixgbe_mac_82598EB)
5467                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5468                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5469                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5470                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5471                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5472                 if (hw->mac.type == ixgbe_mac_82599EB) {
5473                         hwstats->pxonrxc[i] +=
5474                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5475                         hwstats->pxoffrxc[i] +=
5476                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5477                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5478                 } else {
5479                         hwstats->pxonrxc[i] +=
5480                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5481                         hwstats->pxoffrxc[i] +=
5482                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5483                 }
5484                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5485                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5486         }
5487         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5488         /* work around hardware counting issue */
5489         hwstats->gprc -= missed_rx;
5490
5491         /* 82598 hardware only has a 32 bit counter in the high register */
5492         if (hw->mac.type == ixgbe_mac_82599EB) {
5493                 u64 tmp;
5494                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5495                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5496                                                 /* 4 high bits of GORC */
5497                 hwstats->gorc += (tmp << 32);
5498                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5499                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5500                                                 /* 4 high bits of GOTC */
5501                 hwstats->gotc += (tmp << 32);
5502                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5503                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5504                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5505                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5506                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5507                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5508 #ifdef IXGBE_FCOE
5509                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5510                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5511                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5512                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5513                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5514                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5515 #endif /* IXGBE_FCOE */
5516         } else {
5517                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5518                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5519                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5520                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5521                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5522         }
5523         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5524         hwstats->bprc += bprc;
5525         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5526         if (hw->mac.type == ixgbe_mac_82598EB)
5527                 hwstats->mprc -= bprc;
5528         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5529         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5530         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5531         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5532         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5533         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5534         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5535         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5536         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5537         hwstats->lxontxc += lxon;
5538         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5539         hwstats->lxofftxc += lxoff;
5540         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5541         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5542         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5543         /*
5544          * 82598 errata - tx of flow control packets is included in tx counters
5545          */
5546         xon_off_tot = lxon + lxoff;
5547         hwstats->gptc -= xon_off_tot;
5548         hwstats->mptc -= xon_off_tot;
5549         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5550         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5551         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5552         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5553         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5554         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5555         hwstats->ptc64 -= xon_off_tot;
5556         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5557         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5558         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5559         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5560         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5561         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5562
5563         /* Fill out the OS statistics structure */
5564         netdev->stats.multicast = hwstats->mprc;
5565
5566         /* Rx Errors */
5567         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5568         netdev->stats.rx_dropped = 0;
5569         netdev->stats.rx_length_errors = hwstats->rlec;
5570         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5571         netdev->stats.rx_missed_errors = total_mpc;
5572 }
5573
5574 /**
5575  * ixgbe_watchdog - Timer Call-back
5576  * @data: pointer to adapter cast into an unsigned long
5577  **/
5578 static void ixgbe_watchdog(unsigned long data)
5579 {
5580         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5581         struct ixgbe_hw *hw = &adapter->hw;
5582         u64 eics = 0;
5583         int i;
5584
5585         /*
5586          *  Do the watchdog outside of interrupt context due to the lovely
5587          * delays that some of the newer hardware requires
5588          */
5589
5590         if (test_bit(__IXGBE_DOWN, &adapter->state))
5591                 goto watchdog_short_circuit;
5592
5593         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5594                 /*
5595                  * for legacy and MSI interrupts don't set any bits
5596                  * that are enabled for EIAM, because this operation
5597                  * would set *both* EIMS and EICS for any bit in EIAM
5598                  */
5599                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5600                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5601                 goto watchdog_reschedule;
5602         }
5603
5604         /* get one bit for every active tx/rx interrupt vector */
5605         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5606                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5607                 if (qv->rxr_count || qv->txr_count)
5608                         eics |= ((u64)1 << i);
5609         }
5610
5611         /* Cause software interrupt to ensure rx rings are cleaned */
5612         ixgbe_irq_rearm_queues(adapter, eics);
5613
5614 watchdog_reschedule:
5615         /* Reset the timer */
5616         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5617
5618 watchdog_short_circuit:
5619         schedule_work(&adapter->watchdog_task);
5620 }
5621
5622 /**
5623  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5624  * @work: pointer to work_struct containing our data
5625  **/
5626 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5627 {
5628         struct ixgbe_adapter *adapter = container_of(work,
5629                                                      struct ixgbe_adapter,
5630                                                      multispeed_fiber_task);
5631         struct ixgbe_hw *hw = &adapter->hw;
5632         u32 autoneg;
5633         bool negotiation;
5634
5635         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5636         autoneg = hw->phy.autoneg_advertised;
5637         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5638                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5639         hw->mac.autotry_restart = false;
5640         if (hw->mac.ops.setup_link)
5641                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5642         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5643         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5644 }
5645
5646 /**
5647  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5648  * @work: pointer to work_struct containing our data
5649  **/
5650 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5651 {
5652         struct ixgbe_adapter *adapter = container_of(work,
5653                                                      struct ixgbe_adapter,
5654                                                      sfp_config_module_task);
5655         struct ixgbe_hw *hw = &adapter->hw;
5656         u32 err;
5657
5658         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5659
5660         /* Time for electrical oscillations to settle down */
5661         msleep(100);
5662         err = hw->phy.ops.identify_sfp(hw);
5663
5664         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5665                 e_dev_err("failed to initialize because an unsupported SFP+ "
5666                           "module type was detected.\n");
5667                 e_dev_err("Reload the driver after installing a supported "
5668                           "module.\n");
5669                 unregister_netdev(adapter->netdev);
5670                 return;
5671         }
5672         hw->mac.ops.setup_sfp(hw);
5673
5674         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5675                 /* This will also work for DA Twinax connections */
5676                 schedule_work(&adapter->multispeed_fiber_task);
5677         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5678 }
5679
5680 /**
5681  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5682  * @work: pointer to work_struct containing our data
5683  **/
5684 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5685 {
5686         struct ixgbe_adapter *adapter = container_of(work,
5687                                                      struct ixgbe_adapter,
5688                                                      fdir_reinit_task);
5689         struct ixgbe_hw *hw = &adapter->hw;
5690         int i;
5691
5692         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5693                 for (i = 0; i < adapter->num_tx_queues; i++)
5694                         set_bit(__IXGBE_FDIR_INIT_DONE,
5695                                 &(adapter->tx_ring[i]->reinit_state));
5696         } else {
5697                 e_err(probe, "failed to finish FDIR re-initialization, "
5698                       "ignored adding FDIR ATR filters\n");
5699         }
5700         /* Done FDIR Re-initialization, enable transmits */
5701         netif_tx_start_all_queues(adapter->netdev);
5702 }
5703
5704 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5705
5706 /**
5707  * ixgbe_watchdog_task - worker thread to bring link up
5708  * @work: pointer to work_struct containing our data
5709  **/
5710 static void ixgbe_watchdog_task(struct work_struct *work)
5711 {
5712         struct ixgbe_adapter *adapter = container_of(work,
5713                                                      struct ixgbe_adapter,
5714                                                      watchdog_task);
5715         struct net_device *netdev = adapter->netdev;
5716         struct ixgbe_hw *hw = &adapter->hw;
5717         u32 link_speed;
5718         bool link_up;
5719         int i;
5720         struct ixgbe_ring *tx_ring;
5721         int some_tx_pending = 0;
5722
5723         mutex_lock(&ixgbe_watchdog_lock);
5724
5725         link_up = adapter->link_up;
5726         link_speed = adapter->link_speed;
5727
5728         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5729                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5730                 if (link_up) {
5731 #ifdef CONFIG_DCB
5732                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5733                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5734                                         hw->mac.ops.fc_enable(hw, i);
5735                         } else {
5736                                 hw->mac.ops.fc_enable(hw, 0);
5737                         }
5738 #else
5739                         hw->mac.ops.fc_enable(hw, 0);
5740 #endif
5741                 }
5742
5743                 if (link_up ||
5744                     time_after(jiffies, (adapter->link_check_timeout +
5745                                          IXGBE_TRY_LINK_TIMEOUT))) {
5746                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5747                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5748                 }
5749                 adapter->link_up = link_up;
5750                 adapter->link_speed = link_speed;
5751         }
5752
5753         if (link_up) {
5754                 if (!netif_carrier_ok(netdev)) {
5755                         bool flow_rx, flow_tx;
5756
5757                         if (hw->mac.type == ixgbe_mac_82599EB) {
5758                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5759                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5760                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5761                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5762                         } else {
5763                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5764                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5765                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5766                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5767                         }
5768
5769                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5770                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5771                                "10 Gbps" :
5772                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5773                                "1 Gbps" : "unknown speed")),
5774                                ((flow_rx && flow_tx) ? "RX/TX" :
5775                                (flow_rx ? "RX" :
5776                                (flow_tx ? "TX" : "None"))));
5777
5778                         netif_carrier_on(netdev);
5779                 } else {
5780                         /* Force detection of hung controller */
5781                         adapter->detect_tx_hung = true;
5782                 }
5783         } else {
5784                 adapter->link_up = false;
5785                 adapter->link_speed = 0;
5786                 if (netif_carrier_ok(netdev)) {
5787                         e_info(drv, "NIC Link is Down\n");
5788                         netif_carrier_off(netdev);
5789                 }
5790         }
5791
5792         if (!netif_carrier_ok(netdev)) {
5793                 for (i = 0; i < adapter->num_tx_queues; i++) {
5794                         tx_ring = adapter->tx_ring[i];
5795                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5796                                 some_tx_pending = 1;
5797                                 break;
5798                         }
5799                 }
5800
5801                 if (some_tx_pending) {
5802                         /* We've lost link, so the controller stops DMA,
5803                          * but we've got queued Tx work that's never going
5804                          * to get done, so reset controller to flush Tx.
5805                          * (Do the reset outside of interrupt context).
5806                          */
5807                          schedule_work(&adapter->reset_task);
5808                 }
5809         }
5810
5811         ixgbe_update_stats(adapter);
5812         mutex_unlock(&ixgbe_watchdog_lock);
5813 }
5814
5815 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5816                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5817                      u32 tx_flags, u8 *hdr_len)
5818 {
5819         struct ixgbe_adv_tx_context_desc *context_desc;
5820         unsigned int i;
5821         int err;
5822         struct ixgbe_tx_buffer *tx_buffer_info;
5823         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5824         u32 mss_l4len_idx, l4len;
5825
5826         if (skb_is_gso(skb)) {
5827                 if (skb_header_cloned(skb)) {
5828                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5829                         if (err)
5830                                 return err;
5831                 }
5832                 l4len = tcp_hdrlen(skb);
5833                 *hdr_len += l4len;
5834
5835                 if (skb->protocol == htons(ETH_P_IP)) {
5836                         struct iphdr *iph = ip_hdr(skb);
5837                         iph->tot_len = 0;
5838                         iph->check = 0;
5839                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5840                                                                  iph->daddr, 0,
5841                                                                  IPPROTO_TCP,
5842                                                                  0);
5843                 } else if (skb_is_gso_v6(skb)) {
5844                         ipv6_hdr(skb)->payload_len = 0;
5845                         tcp_hdr(skb)->check =
5846                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5847                                              &ipv6_hdr(skb)->daddr,
5848                                              0, IPPROTO_TCP, 0);
5849                 }
5850
5851                 i = tx_ring->next_to_use;
5852
5853                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5854                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5855
5856                 /* VLAN MACLEN IPLEN */
5857                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5858                         vlan_macip_lens |=
5859                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5860                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5861                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5862                 *hdr_len += skb_network_offset(skb);
5863                 vlan_macip_lens |=
5864                     (skb_transport_header(skb) - skb_network_header(skb));
5865                 *hdr_len +=
5866                     (skb_transport_header(skb) - skb_network_header(skb));
5867                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5868                 context_desc->seqnum_seed = 0;
5869
5870                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5871                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5872                                    IXGBE_ADVTXD_DTYP_CTXT);
5873
5874                 if (skb->protocol == htons(ETH_P_IP))
5875                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5876                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5877                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5878
5879                 /* MSS L4LEN IDX */
5880                 mss_l4len_idx =
5881                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5882                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5883                 /* use index 1 for TSO */
5884                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5885                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5886
5887                 tx_buffer_info->time_stamp = jiffies;
5888                 tx_buffer_info->next_to_watch = i;
5889
5890                 i++;
5891                 if (i == tx_ring->count)
5892                         i = 0;
5893                 tx_ring->next_to_use = i;
5894
5895                 return true;
5896         }
5897         return false;
5898 }
5899
5900 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb)
5901 {
5902         u32 rtn = 0;
5903         __be16 protocol;
5904
5905         if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5906                 protocol = ((const struct vlan_ethhdr *)skb->data)->
5907                                         h_vlan_encapsulated_proto;
5908         else
5909                 protocol = skb->protocol;
5910
5911         switch (protocol) {
5912         case cpu_to_be16(ETH_P_IP):
5913                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5914                 switch (ip_hdr(skb)->protocol) {
5915                 case IPPROTO_TCP:
5916                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5917                         break;
5918                 case IPPROTO_SCTP:
5919                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5920                         break;
5921                 }
5922                 break;
5923         case cpu_to_be16(ETH_P_IPV6):
5924                 /* XXX what about other V6 headers?? */
5925                 switch (ipv6_hdr(skb)->nexthdr) {
5926                 case IPPROTO_TCP:
5927                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5928                         break;
5929                 case IPPROTO_SCTP:
5930                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5931                         break;
5932                 }
5933                 break;
5934         default:
5935                 if (unlikely(net_ratelimit()))
5936                         e_warn(probe, "partial checksum but proto=%x!\n",
5937                                skb->protocol);
5938                 break;
5939         }
5940
5941         return rtn;
5942 }
5943
5944 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5945                           struct ixgbe_ring *tx_ring,
5946                           struct sk_buff *skb, u32 tx_flags)
5947 {
5948         struct ixgbe_adv_tx_context_desc *context_desc;
5949         unsigned int i;
5950         struct ixgbe_tx_buffer *tx_buffer_info;
5951         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5952
5953         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5954             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5955                 i = tx_ring->next_to_use;
5956                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5957                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5958
5959                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5960                         vlan_macip_lens |=
5961                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5962                 vlan_macip_lens |= (skb_network_offset(skb) <<
5963                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5964                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5965                         vlan_macip_lens |= (skb_transport_header(skb) -
5966                                             skb_network_header(skb));
5967
5968                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5969                 context_desc->seqnum_seed = 0;
5970
5971                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5972                                     IXGBE_ADVTXD_DTYP_CTXT);
5973
5974                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5975                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb);
5976
5977                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5978                 /* use index zero for tx checksum offload */
5979                 context_desc->mss_l4len_idx = 0;
5980
5981                 tx_buffer_info->time_stamp = jiffies;
5982                 tx_buffer_info->next_to_watch = i;
5983
5984                 i++;
5985                 if (i == tx_ring->count)
5986                         i = 0;
5987                 tx_ring->next_to_use = i;
5988
5989                 return true;
5990         }
5991
5992         return false;
5993 }
5994
5995 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5996                         struct ixgbe_ring *tx_ring,
5997                         struct sk_buff *skb, u32 tx_flags,
5998                         unsigned int first)
5999 {
6000         struct pci_dev *pdev = adapter->pdev;
6001         struct ixgbe_tx_buffer *tx_buffer_info;
6002         unsigned int len;
6003         unsigned int total = skb->len;
6004         unsigned int offset = 0, size, count = 0, i;
6005         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6006         unsigned int f;
6007
6008         i = tx_ring->next_to_use;
6009
6010         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6011                 /* excluding fcoe_crc_eof for FCoE */
6012                 total -= sizeof(struct fcoe_crc_eof);
6013
6014         len = min(skb_headlen(skb), total);
6015         while (len) {
6016                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6017                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6018
6019                 tx_buffer_info->length = size;
6020                 tx_buffer_info->mapped_as_page = false;
6021                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
6022                                                      skb->data + offset,
6023                                                      size, DMA_TO_DEVICE);
6024                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6025                         goto dma_error;
6026                 tx_buffer_info->time_stamp = jiffies;
6027                 tx_buffer_info->next_to_watch = i;
6028
6029                 len -= size;
6030                 total -= size;
6031                 offset += size;
6032                 count++;
6033
6034                 if (len) {
6035                         i++;
6036                         if (i == tx_ring->count)
6037                                 i = 0;
6038                 }
6039         }
6040
6041         for (f = 0; f < nr_frags; f++) {
6042                 struct skb_frag_struct *frag;
6043
6044                 frag = &skb_shinfo(skb)->frags[f];
6045                 len = min((unsigned int)frag->size, total);
6046                 offset = frag->page_offset;
6047
6048                 while (len) {
6049                         i++;
6050                         if (i == tx_ring->count)
6051                                 i = 0;
6052
6053                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6054                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6055
6056                         tx_buffer_info->length = size;
6057                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
6058                                                            frag->page,
6059                                                            offset, size,
6060                                                            DMA_TO_DEVICE);
6061                         tx_buffer_info->mapped_as_page = true;
6062                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6063                                 goto dma_error;
6064                         tx_buffer_info->time_stamp = jiffies;
6065                         tx_buffer_info->next_to_watch = i;
6066
6067                         len -= size;
6068                         total -= size;
6069                         offset += size;
6070                         count++;
6071                 }
6072                 if (total == 0)
6073                         break;
6074         }
6075
6076         tx_ring->tx_buffer_info[i].skb = skb;
6077         tx_ring->tx_buffer_info[first].next_to_watch = i;
6078
6079         return count;
6080
6081 dma_error:
6082         e_dev_err("TX DMA map failed\n");
6083
6084         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6085         tx_buffer_info->dma = 0;
6086         tx_buffer_info->time_stamp = 0;
6087         tx_buffer_info->next_to_watch = 0;
6088         if (count)
6089                 count--;
6090
6091         /* clear timestamp and dma mappings for remaining portion of packet */
6092         while (count--) {
6093                 if (i == 0)
6094                         i += tx_ring->count;
6095                 i--;
6096                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6097                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6098         }
6099
6100         return 0;
6101 }
6102
6103 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6104                            struct ixgbe_ring *tx_ring,
6105                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6106 {
6107         union ixgbe_adv_tx_desc *tx_desc = NULL;
6108         struct ixgbe_tx_buffer *tx_buffer_info;
6109         u32 olinfo_status = 0, cmd_type_len = 0;
6110         unsigned int i;
6111         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6112
6113         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6114
6115         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6116
6117         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6118                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6119
6120         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6121                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6122
6123                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6124                                  IXGBE_ADVTXD_POPTS_SHIFT;
6125
6126                 /* use index 1 context for tso */
6127                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6128                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6129                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6130                                          IXGBE_ADVTXD_POPTS_SHIFT;
6131
6132         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6133                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6134                                  IXGBE_ADVTXD_POPTS_SHIFT;
6135
6136         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6137                 olinfo_status |= IXGBE_ADVTXD_CC;
6138                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6139                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6140                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6141         }
6142
6143         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6144
6145         i = tx_ring->next_to_use;
6146         while (count--) {
6147                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6148                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6149                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6150                 tx_desc->read.cmd_type_len =
6151                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6152                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6153                 i++;
6154                 if (i == tx_ring->count)
6155                         i = 0;
6156         }
6157
6158         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6159
6160         /*
6161          * Force memory writes to complete before letting h/w
6162          * know there are new descriptors to fetch.  (Only
6163          * applicable for weak-ordered memory model archs,
6164          * such as IA-64).
6165          */
6166         wmb();
6167
6168         tx_ring->next_to_use = i;
6169         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6170 }
6171
6172 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6173                       int queue, u32 tx_flags)
6174 {
6175         struct ixgbe_atr_input atr_input;
6176         struct tcphdr *th;
6177         struct iphdr *iph = ip_hdr(skb);
6178         struct ethhdr *eth = (struct ethhdr *)skb->data;
6179         u16 vlan_id, src_port, dst_port, flex_bytes;
6180         u32 src_ipv4_addr, dst_ipv4_addr;
6181         u8 l4type = 0;
6182
6183         /* Right now, we support IPv4 only */
6184         if (skb->protocol != htons(ETH_P_IP))
6185                 return;
6186         /* check if we're UDP or TCP */
6187         if (iph->protocol == IPPROTO_TCP) {
6188                 th = tcp_hdr(skb);
6189                 src_port = th->source;
6190                 dst_port = th->dest;
6191                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6192                 /* l4type IPv4 type is 0, no need to assign */
6193         } else {
6194                 /* Unsupported L4 header, just bail here */
6195                 return;
6196         }
6197
6198         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6199
6200         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6201                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6202         src_ipv4_addr = iph->saddr;
6203         dst_ipv4_addr = iph->daddr;
6204         flex_bytes = eth->h_proto;
6205
6206         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6207         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6208         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6209         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6210         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6211         /* src and dst are inverted, think how the receiver sees them */
6212         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6213         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6214
6215         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6216         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6217 }
6218
6219 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6220                                  struct ixgbe_ring *tx_ring, int size)
6221 {
6222         netif_stop_subqueue(netdev, tx_ring->queue_index);
6223         /* Herbert's original patch had:
6224          *  smp_mb__after_netif_stop_queue();
6225          * but since that doesn't exist yet, just open code it. */
6226         smp_mb();
6227
6228         /* We need to check again in a case another CPU has just
6229          * made room available. */
6230         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6231                 return -EBUSY;
6232
6233         /* A reprieve! - use start_queue because it doesn't call schedule */
6234         netif_start_subqueue(netdev, tx_ring->queue_index);
6235         ++tx_ring->restart_queue;
6236         return 0;
6237 }
6238
6239 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6240                               struct ixgbe_ring *tx_ring, int size)
6241 {
6242         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6243                 return 0;
6244         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6245 }
6246
6247 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6248 {
6249         struct ixgbe_adapter *adapter = netdev_priv(dev);
6250         int txq = smp_processor_id();
6251
6252 #ifdef IXGBE_FCOE
6253         if ((skb->protocol == htons(ETH_P_FCOE)) ||
6254             (skb->protocol == htons(ETH_P_FIP))) {
6255                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6256                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6257                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6258                         return txq;
6259 #ifdef CONFIG_IXGBE_DCB
6260                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6261                         txq = adapter->fcoe.up;
6262                         return txq;
6263 #endif
6264                 }
6265         }
6266 #endif
6267
6268         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6269                 while (unlikely(txq >= dev->real_num_tx_queues))
6270                         txq -= dev->real_num_tx_queues;
6271                 return txq;
6272         }
6273
6274         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6275                 if (skb->priority == TC_PRIO_CONTROL)
6276                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6277                 else
6278                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6279                                >> 13;
6280                 return txq;
6281         }
6282
6283         return skb_tx_hash(dev, skb);
6284 }
6285
6286 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6287                           struct ixgbe_adapter *adapter,
6288                           struct ixgbe_ring *tx_ring)
6289 {
6290         struct netdev_queue *txq;
6291         unsigned int first;
6292         unsigned int tx_flags = 0;
6293         u8 hdr_len = 0;
6294         int tso;
6295         int count = 0;
6296         unsigned int f;
6297
6298         if (vlan_tx_tag_present(skb)) {
6299                 tx_flags |= vlan_tx_tag_get(skb);
6300                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6301                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6302                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6303                 }
6304                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6305                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6306         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6307                    skb->priority != TC_PRIO_CONTROL) {
6308                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6309                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6310                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6311         }
6312
6313 #ifdef IXGBE_FCOE
6314         /* for FCoE with DCB, we force the priority to what
6315          * was specified by the switch */
6316         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6317             (skb->protocol == htons(ETH_P_FCOE) ||
6318              skb->protocol == htons(ETH_P_FIP))) {
6319 #ifdef CONFIG_IXGBE_DCB
6320                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6321                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6322                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6323                         tx_flags |= ((adapter->fcoe.up << 13)
6324                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6325                 }
6326 #endif
6327                 /* flag for FCoE offloads */
6328                 if (skb->protocol == htons(ETH_P_FCOE))
6329                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6330         }
6331 #endif
6332
6333         /* four things can cause us to need a context descriptor */
6334         if (skb_is_gso(skb) ||
6335             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6336             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6337             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6338                 count++;
6339
6340         count += TXD_USE_COUNT(skb_headlen(skb));
6341         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6342                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6343
6344         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6345                 adapter->tx_busy++;
6346                 return NETDEV_TX_BUSY;
6347         }
6348
6349         first = tx_ring->next_to_use;
6350         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6351 #ifdef IXGBE_FCOE
6352                 /* setup tx offload for FCoE */
6353                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6354                 if (tso < 0) {
6355                         dev_kfree_skb_any(skb);
6356                         return NETDEV_TX_OK;
6357                 }
6358                 if (tso)
6359                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6360 #endif /* IXGBE_FCOE */
6361         } else {
6362                 if (skb->protocol == htons(ETH_P_IP))
6363                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6364                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6365                 if (tso < 0) {
6366                         dev_kfree_skb_any(skb);
6367                         return NETDEV_TX_OK;
6368                 }
6369
6370                 if (tso)
6371                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6372                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
6373                          (skb->ip_summed == CHECKSUM_PARTIAL))
6374                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6375         }
6376
6377         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6378         if (count) {
6379                 /* add the ATR filter if ATR is on */
6380                 if (tx_ring->atr_sample_rate) {
6381                         ++tx_ring->atr_count;
6382                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6383                              test_bit(__IXGBE_FDIR_INIT_DONE,
6384                                       &tx_ring->reinit_state)) {
6385                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6386                                           tx_flags);
6387                                 tx_ring->atr_count = 0;
6388                         }
6389                 }
6390                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6391                 txq->tx_bytes += skb->len;
6392                 txq->tx_packets++;
6393                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6394                                hdr_len);
6395                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6396
6397         } else {
6398                 dev_kfree_skb_any(skb);
6399                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6400                 tx_ring->next_to_use = first;
6401         }
6402
6403         return NETDEV_TX_OK;
6404 }
6405
6406 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6407 {
6408         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6409         struct ixgbe_ring *tx_ring;
6410
6411         tx_ring = adapter->tx_ring[skb->queue_mapping];
6412         return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6413 }
6414
6415 /**
6416  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6417  * @netdev: network interface device structure
6418  * @p: pointer to an address structure
6419  *
6420  * Returns 0 on success, negative on failure
6421  **/
6422 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6423 {
6424         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6425         struct ixgbe_hw *hw = &adapter->hw;
6426         struct sockaddr *addr = p;
6427
6428         if (!is_valid_ether_addr(addr->sa_data))
6429                 return -EADDRNOTAVAIL;
6430
6431         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6432         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6433
6434         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6435                             IXGBE_RAH_AV);
6436
6437         return 0;
6438 }
6439
6440 static int
6441 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6442 {
6443         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6444         struct ixgbe_hw *hw = &adapter->hw;
6445         u16 value;
6446         int rc;
6447
6448         if (prtad != hw->phy.mdio.prtad)
6449                 return -EINVAL;
6450         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6451         if (!rc)
6452                 rc = value;
6453         return rc;
6454 }
6455
6456 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6457                             u16 addr, u16 value)
6458 {
6459         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6460         struct ixgbe_hw *hw = &adapter->hw;
6461
6462         if (prtad != hw->phy.mdio.prtad)
6463                 return -EINVAL;
6464         return hw->phy.ops.write_reg(hw, addr, devad, value);
6465 }
6466
6467 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6468 {
6469         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6470
6471         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6472 }
6473
6474 /**
6475  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6476  * netdev->dev_addrs
6477  * @netdev: network interface device structure
6478  *
6479  * Returns non-zero on failure
6480  **/
6481 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6482 {
6483         int err = 0;
6484         struct ixgbe_adapter *adapter = netdev_priv(dev);
6485         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6486
6487         if (is_valid_ether_addr(mac->san_addr)) {
6488                 rtnl_lock();
6489                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6490                 rtnl_unlock();
6491         }
6492         return err;
6493 }
6494
6495 /**
6496  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6497  * netdev->dev_addrs
6498  * @netdev: network interface device structure
6499  *
6500  * Returns non-zero on failure
6501  **/
6502 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6503 {
6504         int err = 0;
6505         struct ixgbe_adapter *adapter = netdev_priv(dev);
6506         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6507
6508         if (is_valid_ether_addr(mac->san_addr)) {
6509                 rtnl_lock();
6510                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6511                 rtnl_unlock();
6512         }
6513         return err;
6514 }
6515
6516 #ifdef CONFIG_NET_POLL_CONTROLLER
6517 /*
6518  * Polling 'interrupt' - used by things like netconsole to send skbs
6519  * without having to re-enable interrupts. It's not called while
6520  * the interrupt routine is executing.
6521  */
6522 static void ixgbe_netpoll(struct net_device *netdev)
6523 {
6524         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6525         int i;
6526
6527         /* if interface is down do nothing */
6528         if (test_bit(__IXGBE_DOWN, &adapter->state))
6529                 return;
6530
6531         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6532         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6533                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6534                 for (i = 0; i < num_q_vectors; i++) {
6535                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6536                         ixgbe_msix_clean_many(0, q_vector);
6537                 }
6538         } else {
6539                 ixgbe_intr(adapter->pdev->irq, netdev);
6540         }
6541         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6542 }
6543 #endif
6544
6545 static const struct net_device_ops ixgbe_netdev_ops = {
6546         .ndo_open               = ixgbe_open,
6547         .ndo_stop               = ixgbe_close,
6548         .ndo_start_xmit         = ixgbe_xmit_frame,
6549         .ndo_select_queue       = ixgbe_select_queue,
6550         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6551         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6552         .ndo_validate_addr      = eth_validate_addr,
6553         .ndo_set_mac_address    = ixgbe_set_mac,
6554         .ndo_change_mtu         = ixgbe_change_mtu,
6555         .ndo_tx_timeout         = ixgbe_tx_timeout,
6556         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6557         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6558         .ndo_do_ioctl           = ixgbe_ioctl,
6559         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6560         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6561         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6562         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6563 #ifdef CONFIG_NET_POLL_CONTROLLER
6564         .ndo_poll_controller    = ixgbe_netpoll,
6565 #endif
6566 #ifdef IXGBE_FCOE
6567         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6568         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6569         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6570         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6571         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6572 #endif /* IXGBE_FCOE */
6573 };
6574
6575 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6576                            const struct ixgbe_info *ii)
6577 {
6578 #ifdef CONFIG_PCI_IOV
6579         struct ixgbe_hw *hw = &adapter->hw;
6580         int err;
6581
6582         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6583                 return;
6584
6585         /* The 82599 supports up to 64 VFs per physical function
6586          * but this implementation limits allocation to 63 so that
6587          * basic networking resources are still available to the
6588          * physical function
6589          */
6590         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6591         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6592         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6593         if (err) {
6594                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6595                 goto err_novfs;
6596         }
6597         /* If call to enable VFs succeeded then allocate memory
6598          * for per VF control structures.
6599          */
6600         adapter->vfinfo =
6601                 kcalloc(adapter->num_vfs,
6602                         sizeof(struct vf_data_storage), GFP_KERNEL);
6603         if (adapter->vfinfo) {
6604                 /* Now that we're sure SR-IOV is enabled
6605                  * and memory allocated set up the mailbox parameters
6606                  */
6607                 ixgbe_init_mbx_params_pf(hw);
6608                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6609                        sizeof(hw->mbx.ops));
6610
6611                 /* Disable RSC when in SR-IOV mode */
6612                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6613                                      IXGBE_FLAG2_RSC_ENABLED);
6614                 return;
6615         }
6616
6617         /* Oh oh */
6618         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6619               "SRIOV disabled\n");
6620         pci_disable_sriov(adapter->pdev);
6621
6622 err_novfs:
6623         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6624         adapter->num_vfs = 0;
6625 #endif /* CONFIG_PCI_IOV */
6626 }
6627
6628 /**
6629  * ixgbe_probe - Device Initialization Routine
6630  * @pdev: PCI device information struct
6631  * @ent: entry in ixgbe_pci_tbl
6632  *
6633  * Returns 0 on success, negative on failure
6634  *
6635  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6636  * The OS initialization, configuring of the adapter private structure,
6637  * and a hardware reset occur.
6638  **/
6639 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6640                                  const struct pci_device_id *ent)
6641 {
6642         struct net_device *netdev;
6643         struct ixgbe_adapter *adapter = NULL;
6644         struct ixgbe_hw *hw;
6645         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6646         static int cards_found;
6647         int i, err, pci_using_dac;
6648         unsigned int indices = num_possible_cpus();
6649 #ifdef IXGBE_FCOE
6650         u16 device_caps;
6651 #endif
6652         u32 part_num, eec;
6653
6654         /* Catch broken hardware that put the wrong VF device ID in
6655          * the PCIe SR-IOV capability.
6656          */
6657         if (pdev->is_virtfn) {
6658                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6659                      pci_name(pdev), pdev->vendor, pdev->device);
6660                 return -EINVAL;
6661         }
6662
6663         err = pci_enable_device_mem(pdev);
6664         if (err)
6665                 return err;
6666
6667         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6668             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6669                 pci_using_dac = 1;
6670         } else {
6671                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6672                 if (err) {
6673                         err = dma_set_coherent_mask(&pdev->dev,
6674                                                     DMA_BIT_MASK(32));
6675                         if (err) {
6676                                 dev_err(&pdev->dev,
6677                                         "No usable DMA configuration, aborting\n");
6678                                 goto err_dma;
6679                         }
6680                 }
6681                 pci_using_dac = 0;
6682         }
6683
6684         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6685                                            IORESOURCE_MEM), ixgbe_driver_name);
6686         if (err) {
6687                 dev_err(&pdev->dev,
6688                         "pci_request_selected_regions failed 0x%x\n", err);
6689                 goto err_pci_reg;
6690         }
6691
6692         pci_enable_pcie_error_reporting(pdev);
6693
6694         pci_set_master(pdev);
6695         pci_save_state(pdev);
6696
6697         if (ii->mac == ixgbe_mac_82598EB)
6698                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6699         else
6700                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6701
6702         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6703 #ifdef IXGBE_FCOE
6704         indices += min_t(unsigned int, num_possible_cpus(),
6705                          IXGBE_MAX_FCOE_INDICES);
6706 #endif
6707         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6708         if (!netdev) {
6709                 err = -ENOMEM;
6710                 goto err_alloc_etherdev;
6711         }
6712
6713         SET_NETDEV_DEV(netdev, &pdev->dev);
6714
6715         pci_set_drvdata(pdev, netdev);
6716         adapter = netdev_priv(netdev);
6717
6718         adapter->netdev = netdev;
6719         adapter->pdev = pdev;
6720         hw = &adapter->hw;
6721         hw->back = adapter;
6722         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6723
6724         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6725                               pci_resource_len(pdev, 0));
6726         if (!hw->hw_addr) {
6727                 err = -EIO;
6728                 goto err_ioremap;
6729         }
6730
6731         for (i = 1; i <= 5; i++) {
6732                 if (pci_resource_len(pdev, i) == 0)
6733                         continue;
6734         }
6735
6736         netdev->netdev_ops = &ixgbe_netdev_ops;
6737         ixgbe_set_ethtool_ops(netdev);
6738         netdev->watchdog_timeo = 5 * HZ;
6739         strcpy(netdev->name, pci_name(pdev));
6740
6741         adapter->bd_number = cards_found;
6742
6743         /* Setup hw api */
6744         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6745         hw->mac.type  = ii->mac;
6746
6747         /* EEPROM */
6748         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6749         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6750         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6751         if (!(eec & (1 << 8)))
6752                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6753
6754         /* PHY */
6755         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6756         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6757         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6758         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6759         hw->phy.mdio.mmds = 0;
6760         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6761         hw->phy.mdio.dev = netdev;
6762         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6763         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6764
6765         /* set up this timer and work struct before calling get_invariants
6766          * which might start the timer
6767          */
6768         init_timer(&adapter->sfp_timer);
6769         adapter->sfp_timer.function = ixgbe_sfp_timer;
6770         adapter->sfp_timer.data = (unsigned long) adapter;
6771
6772         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6773
6774         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6775         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6776
6777         /* a new SFP+ module arrival, called from GPI SDP2 context */
6778         INIT_WORK(&adapter->sfp_config_module_task,
6779                   ixgbe_sfp_config_module_task);
6780
6781         ii->get_invariants(hw);
6782
6783         /* setup the private structure */
6784         err = ixgbe_sw_init(adapter);
6785         if (err)
6786                 goto err_sw_init;
6787
6788         /* Make it possible the adapter to be woken up via WOL */
6789         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6790                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6791
6792         /*
6793          * If there is a fan on this device and it has failed log the
6794          * failure.
6795          */
6796         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6797                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6798                 if (esdp & IXGBE_ESDP_SDP1)
6799                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6800         }
6801
6802         /* reset_hw fills in the perm_addr as well */
6803         hw->phy.reset_if_overtemp = true;
6804         err = hw->mac.ops.reset_hw(hw);
6805         hw->phy.reset_if_overtemp = false;
6806         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6807             hw->mac.type == ixgbe_mac_82598EB) {
6808                 /*
6809                  * Start a kernel thread to watch for a module to arrive.
6810                  * Only do this for 82598, since 82599 will generate
6811                  * interrupts on module arrival.
6812                  */
6813                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6814                 mod_timer(&adapter->sfp_timer,
6815                           round_jiffies(jiffies + (2 * HZ)));
6816                 err = 0;
6817         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6818                 e_dev_err("failed to initialize because an unsupported SFP+ "
6819                           "module type was detected.\n");
6820                 e_dev_err("Reload the driver after installing a supported "
6821                           "module.\n");
6822                 goto err_sw_init;
6823         } else if (err) {
6824                 e_dev_err("HW Init failed: %d\n", err);
6825                 goto err_sw_init;
6826         }
6827
6828         ixgbe_probe_vf(adapter, ii);
6829
6830         netdev->features = NETIF_F_SG |
6831                            NETIF_F_IP_CSUM |
6832                            NETIF_F_HW_VLAN_TX |
6833                            NETIF_F_HW_VLAN_RX |
6834                            NETIF_F_HW_VLAN_FILTER;
6835
6836         netdev->features |= NETIF_F_IPV6_CSUM;
6837         netdev->features |= NETIF_F_TSO;
6838         netdev->features |= NETIF_F_TSO6;
6839         netdev->features |= NETIF_F_GRO;
6840
6841         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6842                 netdev->features |= NETIF_F_SCTP_CSUM;
6843
6844         netdev->vlan_features |= NETIF_F_TSO;
6845         netdev->vlan_features |= NETIF_F_TSO6;
6846         netdev->vlan_features |= NETIF_F_IP_CSUM;
6847         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6848         netdev->vlan_features |= NETIF_F_SG;
6849
6850         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6851                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6852                                     IXGBE_FLAG_DCB_ENABLED);
6853         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6854                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6855
6856 #ifdef CONFIG_IXGBE_DCB
6857         netdev->dcbnl_ops = &dcbnl_ops;
6858 #endif
6859
6860 #ifdef IXGBE_FCOE
6861         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6862                 if (hw->mac.ops.get_device_caps) {
6863                         hw->mac.ops.get_device_caps(hw, &device_caps);
6864                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6865                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6866                 }
6867         }
6868         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6869                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6870                 netdev->vlan_features |= NETIF_F_FSO;
6871                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6872         }
6873 #endif /* IXGBE_FCOE */
6874         if (pci_using_dac) {
6875                 netdev->features |= NETIF_F_HIGHDMA;
6876                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6877         }
6878
6879         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6880                 netdev->features |= NETIF_F_LRO;
6881
6882         /* make sure the EEPROM is good */
6883         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6884                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6885                 err = -EIO;
6886                 goto err_eeprom;
6887         }
6888
6889         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6890         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6891
6892         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6893                 e_dev_err("invalid MAC address\n");
6894                 err = -EIO;
6895                 goto err_eeprom;
6896         }
6897
6898         /* power down the optics */
6899         if (hw->phy.multispeed_fiber)
6900                 hw->mac.ops.disable_tx_laser(hw);
6901
6902         init_timer(&adapter->watchdog_timer);
6903         adapter->watchdog_timer.function = ixgbe_watchdog;
6904         adapter->watchdog_timer.data = (unsigned long)adapter;
6905
6906         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6907         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6908
6909         err = ixgbe_init_interrupt_scheme(adapter);
6910         if (err)
6911                 goto err_sw_init;
6912
6913         switch (pdev->device) {
6914         case IXGBE_DEV_ID_82599_KX4:
6915                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6916                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6917                 break;
6918         default:
6919                 adapter->wol = 0;
6920                 break;
6921         }
6922         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6923
6924         /* pick up the PCI bus settings for reporting later */
6925         hw->mac.ops.get_bus_info(hw);
6926
6927         /* print bus type/speed/width info */
6928         e_dev_info("(PCI Express:%s:%s) %pM\n",
6929                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6930                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6931                     "Unknown"),
6932                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6933                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6934                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6935                     "Unknown"),
6936                    netdev->dev_addr);
6937         ixgbe_read_pba_num_generic(hw, &part_num);
6938         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6939                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6940                            "PBA No: %06x-%03x\n",
6941                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6942                            (part_num >> 8), (part_num & 0xff));
6943         else
6944                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6945                            hw->mac.type, hw->phy.type,
6946                            (part_num >> 8), (part_num & 0xff));
6947
6948         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6949                 e_dev_warn("PCI-Express bandwidth available for this card is "
6950                            "not sufficient for optimal performance.\n");
6951                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6952                            "is required.\n");
6953         }
6954
6955         /* save off EEPROM version number */
6956         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
6957
6958         /* reset the hardware with the new settings */
6959         err = hw->mac.ops.start_hw(hw);
6960
6961         if (err == IXGBE_ERR_EEPROM_VERSION) {
6962                 /* We are running on a pre-production device, log a warning */
6963                 e_dev_warn("This device is a pre-production adapter/LOM. "
6964                            "Please be aware there may be issues associated "
6965                            "with your hardware.  If you are experiencing "
6966                            "problems please contact your Intel or hardware "
6967                            "representative who provided you with this "
6968                            "hardware.\n");
6969         }
6970         strcpy(netdev->name, "eth%d");
6971         err = register_netdev(netdev);
6972         if (err)
6973                 goto err_register;
6974
6975         /* carrier off reporting is important to ethtool even BEFORE open */
6976         netif_carrier_off(netdev);
6977
6978         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
6979             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6980                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
6981
6982         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
6983                 INIT_WORK(&adapter->check_overtemp_task,
6984                           ixgbe_check_overtemp_task);
6985 #ifdef CONFIG_IXGBE_DCA
6986         if (dca_add_requester(&pdev->dev) == 0) {
6987                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
6988                 ixgbe_setup_dca(adapter);
6989         }
6990 #endif
6991         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6992                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
6993                 for (i = 0; i < adapter->num_vfs; i++)
6994                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
6995         }
6996
6997         /* add san mac addr to netdev */
6998         ixgbe_add_sanmac_netdev(netdev);
6999
7000         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7001         cards_found++;
7002         return 0;
7003
7004 err_register:
7005         ixgbe_release_hw_control(adapter);
7006         ixgbe_clear_interrupt_scheme(adapter);
7007 err_sw_init:
7008 err_eeprom:
7009         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7010                 ixgbe_disable_sriov(adapter);
7011         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7012         del_timer_sync(&adapter->sfp_timer);
7013         cancel_work_sync(&adapter->sfp_task);
7014         cancel_work_sync(&adapter->multispeed_fiber_task);
7015         cancel_work_sync(&adapter->sfp_config_module_task);
7016         iounmap(hw->hw_addr);
7017 err_ioremap:
7018         free_netdev(netdev);
7019 err_alloc_etherdev:
7020         pci_release_selected_regions(pdev,
7021                                      pci_select_bars(pdev, IORESOURCE_MEM));
7022 err_pci_reg:
7023 err_dma:
7024         pci_disable_device(pdev);
7025         return err;
7026 }
7027
7028 /**
7029  * ixgbe_remove - Device Removal Routine
7030  * @pdev: PCI device information struct
7031  *
7032  * ixgbe_remove is called by the PCI subsystem to alert the driver
7033  * that it should release a PCI device.  The could be caused by a
7034  * Hot-Plug event, or because the driver is going to be removed from
7035  * memory.
7036  **/
7037 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7038 {
7039         struct net_device *netdev = pci_get_drvdata(pdev);
7040         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7041
7042         set_bit(__IXGBE_DOWN, &adapter->state);
7043         /* clear the module not found bit to make sure the worker won't
7044          * reschedule
7045          */
7046         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7047         del_timer_sync(&adapter->watchdog_timer);
7048
7049         del_timer_sync(&adapter->sfp_timer);
7050         cancel_work_sync(&adapter->watchdog_task);
7051         cancel_work_sync(&adapter->sfp_task);
7052         cancel_work_sync(&adapter->multispeed_fiber_task);
7053         cancel_work_sync(&adapter->sfp_config_module_task);
7054         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7055             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7056                 cancel_work_sync(&adapter->fdir_reinit_task);
7057         flush_scheduled_work();
7058
7059 #ifdef CONFIG_IXGBE_DCA
7060         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7061                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7062                 dca_remove_requester(&pdev->dev);
7063                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7064         }
7065
7066 #endif
7067 #ifdef IXGBE_FCOE
7068         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7069                 ixgbe_cleanup_fcoe(adapter);
7070
7071 #endif /* IXGBE_FCOE */
7072
7073         /* remove the added san mac */
7074         ixgbe_del_sanmac_netdev(netdev);
7075
7076         if (netdev->reg_state == NETREG_REGISTERED)
7077                 unregister_netdev(netdev);
7078
7079         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7080                 ixgbe_disable_sriov(adapter);
7081
7082         ixgbe_clear_interrupt_scheme(adapter);
7083
7084         ixgbe_release_hw_control(adapter);
7085
7086         iounmap(adapter->hw.hw_addr);
7087         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7088                                      IORESOURCE_MEM));
7089
7090         e_dev_info("complete\n");
7091
7092         free_netdev(netdev);
7093
7094         pci_disable_pcie_error_reporting(pdev);
7095
7096         pci_disable_device(pdev);
7097 }
7098
7099 /**
7100  * ixgbe_io_error_detected - called when PCI error is detected
7101  * @pdev: Pointer to PCI device
7102  * @state: The current pci connection state
7103  *
7104  * This function is called after a PCI bus error affecting
7105  * this device has been detected.
7106  */
7107 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7108                                                 pci_channel_state_t state)
7109 {
7110         struct net_device *netdev = pci_get_drvdata(pdev);
7111         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7112
7113         netif_device_detach(netdev);
7114
7115         if (state == pci_channel_io_perm_failure)
7116                 return PCI_ERS_RESULT_DISCONNECT;
7117
7118         if (netif_running(netdev))
7119                 ixgbe_down(adapter);
7120         pci_disable_device(pdev);
7121
7122         /* Request a slot reset. */
7123         return PCI_ERS_RESULT_NEED_RESET;
7124 }
7125
7126 /**
7127  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7128  * @pdev: Pointer to PCI device
7129  *
7130  * Restart the card from scratch, as if from a cold-boot.
7131  */
7132 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7133 {
7134         struct net_device *netdev = pci_get_drvdata(pdev);
7135         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7136         pci_ers_result_t result;
7137         int err;
7138
7139         if (pci_enable_device_mem(pdev)) {
7140                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7141                 result = PCI_ERS_RESULT_DISCONNECT;
7142         } else {
7143                 pci_set_master(pdev);
7144                 pci_restore_state(pdev);
7145                 pci_save_state(pdev);
7146
7147                 pci_wake_from_d3(pdev, false);
7148
7149                 ixgbe_reset(adapter);
7150                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7151                 result = PCI_ERS_RESULT_RECOVERED;
7152         }
7153
7154         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7155         if (err) {
7156                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7157                           "failed 0x%0x\n", err);
7158                 /* non-fatal, continue */
7159         }
7160
7161         return result;
7162 }
7163
7164 /**
7165  * ixgbe_io_resume - called when traffic can start flowing again.
7166  * @pdev: Pointer to PCI device
7167  *
7168  * This callback is called when the error recovery driver tells us that
7169  * its OK to resume normal operation.
7170  */
7171 static void ixgbe_io_resume(struct pci_dev *pdev)
7172 {
7173         struct net_device *netdev = pci_get_drvdata(pdev);
7174         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7175
7176         if (netif_running(netdev)) {
7177                 if (ixgbe_up(adapter)) {
7178                         e_info(probe, "ixgbe_up failed after reset\n");
7179                         return;
7180                 }
7181         }
7182
7183         netif_device_attach(netdev);
7184 }
7185
7186 static struct pci_error_handlers ixgbe_err_handler = {
7187         .error_detected = ixgbe_io_error_detected,
7188         .slot_reset = ixgbe_io_slot_reset,
7189         .resume = ixgbe_io_resume,
7190 };
7191
7192 static struct pci_driver ixgbe_driver = {
7193         .name     = ixgbe_driver_name,
7194         .id_table = ixgbe_pci_tbl,
7195         .probe    = ixgbe_probe,
7196         .remove   = __devexit_p(ixgbe_remove),
7197 #ifdef CONFIG_PM
7198         .suspend  = ixgbe_suspend,
7199         .resume   = ixgbe_resume,
7200 #endif
7201         .shutdown = ixgbe_shutdown,
7202         .err_handler = &ixgbe_err_handler
7203 };
7204
7205 /**
7206  * ixgbe_init_module - Driver Registration Routine
7207  *
7208  * ixgbe_init_module is the first routine called when the driver is
7209  * loaded. All it does is register with the PCI subsystem.
7210  **/
7211 static int __init ixgbe_init_module(void)
7212 {
7213         int ret;
7214         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7215         pr_info("%s\n", ixgbe_copyright);
7216
7217 #ifdef CONFIG_IXGBE_DCA
7218         dca_register_notify(&dca_notifier);
7219 #endif
7220
7221         ret = pci_register_driver(&ixgbe_driver);
7222         return ret;
7223 }
7224
7225 module_init(ixgbe_init_module);
7226
7227 /**
7228  * ixgbe_exit_module - Driver Exit Cleanup Routine
7229  *
7230  * ixgbe_exit_module is called just before the driver is removed
7231  * from memory.
7232  **/
7233 static void __exit ixgbe_exit_module(void)
7234 {
7235 #ifdef CONFIG_IXGBE_DCA
7236         dca_unregister_notify(&dca_notifier);
7237 #endif
7238         pci_unregister_driver(&ixgbe_driver);
7239 }
7240
7241 #ifdef CONFIG_IXGBE_DCA
7242 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7243                             void *p)
7244 {
7245         int ret_val;
7246
7247         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7248                                          __ixgbe_notify_dca);
7249
7250         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7251 }
7252
7253 #endif /* CONFIG_IXGBE_DCA */
7254
7255 /**
7256  * ixgbe_get_hw_dev return device
7257  * used by hardware layer to print debugging information
7258  **/
7259 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7260 {
7261         struct ixgbe_adapter *adapter = hw->back;
7262         return adapter->netdev;
7263 }
7264
7265 module_exit(ixgbe_exit_module);
7266
7267 /* ixgbe_main.c */