drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54 #define MAJ 3
  55 #define MIN 2
  56 #define BUILD 9
  57 #define KFIX 2
  58 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  59         __stringify(BUILD) "-k" __stringify(KFIX)
  60 const char ixgbe_driver_version[] = DRV_VERSION;
  61 static const char ixgbe_copyright[] =
  62                                 "Copyright (c) 1999-2011 Intel Corporation.";
  63
  64 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  65         [board_82598] = &ixgbe_82598_info,
  66         [board_82599] = &ixgbe_82599_info,
  67         [board_X540] = &ixgbe_X540_info,
  68 };
  69
  70 /* ixgbe_pci_tbl - PCI Device ID Table
  71  *
  72  * Wildcard entries (PCI_ANY_ID) should come last
  73  * Last entry must be all 0s
  74  *
  75  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  76  *   Class, Class Mask, private data (not used) }
  77  */
  78 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  98          board_82598 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 100          board_82598 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 102          board_82598 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 114          board_82599 },
 115         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 116          board_82599 },
 117         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 118          board_82599 },
 119         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 120          board_82599 },
 121         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 122          board_82599 },
 123         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 124          board_82599 },
 125         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 126          board_X540 },
 127
 128         /* required last entry */
 129         {0, }
 130 };
 131 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 132
 133 #ifdef CONFIG_IXGBE_DCA
 134 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 135                             void *p);
 136 static struct notifier_block dca_notifier = {
 137         .notifier_call = ixgbe_notify_dca,
 138         .next          = NULL,
 139         .priority      = 0
 140 };
 141 #endif
 142
 143 #ifdef CONFIG_PCI_IOV
 144 static unsigned int max_vfs;
 145 module_param(max_vfs, uint, 0);
 146 MODULE_PARM_DESC(max_vfs,
 147                  "Maximum number of virtual functions to allocate per physical function");
 148 #endif /* CONFIG_PCI_IOV */
 149
 150 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 151 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 152 MODULE_LICENSE("GPL");
 153 MODULE_VERSION(DRV_VERSION);
 154
 155 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 156
 157 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 158 {
 159         struct ixgbe_hw *hw = &adapter->hw;
 160         u32 gcr;
 161         u32 gpie;
 162         u32 vmdctl;
 163
 164 #ifdef CONFIG_PCI_IOV
 165         /* disable iov and allow time for transactions to clear */
 166         pci_disable_sriov(adapter->pdev);
 167 #endif
 168
 169         /* turn off device IOV mode */
 170         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 171         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 172         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 173         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 174         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 175         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 176
 177         /* set default pool back to 0 */
 178         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 179         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 180         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 181
 182         /* take a breather then clean up driver data */
 183         msleep(100);
 184
 185         kfree(adapter->vfinfo);
 186         adapter->vfinfo = NULL;
 187
 188         adapter->num_vfs = 0;
 189         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 190 }
 191
 192 struct ixgbe_reg_info {
 193         u32 ofs;
 194         char *name;
 195 };
 196
 197 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 198
 199         /* General Registers */
 200         {IXGBE_CTRL, "CTRL"},
 201         {IXGBE_STATUS, "STATUS"},
 202         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 203
 204         /* Interrupt Registers */
 205         {IXGBE_EICR, "EICR"},
 206
 207         /* RX Registers */
 208         {IXGBE_SRRCTL(0), "SRRCTL"},
 209         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 210         {IXGBE_RDLEN(0), "RDLEN"},
 211         {IXGBE_RDH(0), "RDH"},
 212         {IXGBE_RDT(0), "RDT"},
 213         {IXGBE_RXDCTL(0), "RXDCTL"},
 214         {IXGBE_RDBAL(0), "RDBAL"},
 215         {IXGBE_RDBAH(0), "RDBAH"},
 216
 217         /* TX Registers */
 218         {IXGBE_TDBAL(0), "TDBAL"},
 219         {IXGBE_TDBAH(0), "TDBAH"},
 220         {IXGBE_TDLEN(0), "TDLEN"},
 221         {IXGBE_TDH(0), "TDH"},
 222         {IXGBE_TDT(0), "TDT"},
 223         {IXGBE_TXDCTL(0), "TXDCTL"},
 224
 225         /* List Terminator */
 226         {}
 227 };
 228
 229
 230 /*
 231  * ixgbe_regdump - register printout routine
 232  */
 233 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 234 {
 235         int i = 0, j = 0;
 236         char rname[16];
 237         u32 regs[64];
 238
 239         switch (reginfo->ofs) {
 240         case IXGBE_SRRCTL(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 243                 break;
 244         case IXGBE_DCA_RXCTRL(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 247                 break;
 248         case IXGBE_RDLEN(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 251                 break;
 252         case IXGBE_RDH(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 255                 break;
 256         case IXGBE_RDT(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 259                 break;
 260         case IXGBE_RXDCTL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 263                 break;
 264         case IXGBE_RDBAL(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 267                 break;
 268         case IXGBE_RDBAH(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 271                 break;
 272         case IXGBE_TDBAL(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 275                 break;
 276         case IXGBE_TDBAH(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 279                 break;
 280         case IXGBE_TDLEN(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 283                 break;
 284         case IXGBE_TDH(0):
 285                 for (i = 0; i < 64; i++)
 286                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 287                 break;
 288         case IXGBE_TDT(0):
 289                 for (i = 0; i < 64; i++)
 290                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 291                 break;
 292         case IXGBE_TXDCTL(0):
 293                 for (i = 0; i < 64; i++)
 294                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 295                 break;
 296         default:
 297                 pr_info("%-15s %08x\n", reginfo->name,
 298                         IXGBE_READ_REG(hw, reginfo->ofs));
 299                 return;
 300         }
 301
 302         for (i = 0; i < 8; i++) {
 303                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 304                 pr_err("%-15s", rname);
 305                 for (j = 0; j < 8; j++)
 306                         pr_cont(" %08x", regs[i*8+j]);
 307                 pr_cont("\n");
 308         }
 309
 310 }
 311
 312 /*
 313  * ixgbe_dump - Print registers, tx-rings and rx-rings
 314  */
 315 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 316 {
 317         struct net_device *netdev = adapter->netdev;
 318         struct ixgbe_hw *hw = &adapter->hw;
 319         struct ixgbe_reg_info *reginfo;
 320         int n = 0;
 321         struct ixgbe_ring *tx_ring;
 322         struct ixgbe_tx_buffer *tx_buffer_info;
 323         union ixgbe_adv_tx_desc *tx_desc;
 324         struct my_u0 { u64 a; u64 b; } *u0;
 325         struct ixgbe_ring *rx_ring;
 326         union ixgbe_adv_rx_desc *rx_desc;
 327         struct ixgbe_rx_buffer *rx_buffer_info;
 328         u32 staterr;
 329         int i = 0;
 330
 331         if (!netif_msg_hw(adapter))
 332                 return;
 333
 334         /* Print netdevice Info */
 335         if (netdev) {
 336                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 337                 pr_info("Device Name     state            "
 338                         "trans_start      last_rx\n");
 339                 pr_info("%-15s %016lX %016lX %016lX\n",
 340                         netdev->name,
 341                         netdev->state,
 342                         netdev->trans_start,
 343                         netdev->last_rx);
 344         }
 345
 346         /* Print Registers */
 347         dev_info(&adapter->pdev->dev, "Register Dump\n");
 348         pr_info(" Register Name   Value\n");
 349         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 350              reginfo->name; reginfo++) {
 351                 ixgbe_regdump(hw, reginfo);
 352         }
 353
 354         /* Print TX Ring Summary */
 355         if (!netdev || !netif_running(netdev))
 356                 goto exit;
 357
 358         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 359         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 360         for (n = 0; n < adapter->num_tx_queues; n++) {
 361                 tx_ring = adapter->tx_ring[n];
 362                 tx_buffer_info =
 363                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 364                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 365                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 366                            (u64)tx_buffer_info->dma,
 367                            tx_buffer_info->length,
 368                            tx_buffer_info->next_to_watch,
 369                            (u64)tx_buffer_info->time_stamp);
 370         }
 371
 372         /* Print TX Rings */
 373         if (!netif_msg_tx_done(adapter))
 374                 goto rx_ring_summary;
 375
 376         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 377
 378         /* Transmit Descriptor Formats
 379          *
 380          * Advanced Transmit Descriptor
 381          *   +--------------------------------------------------------------+
 382          * 0 |         Buffer Address [63:0]                                |
 383          *   +--------------------------------------------------------------+
 384          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 385          *   +--------------------------------------------------------------+
 386          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 387          */
 388
 389         for (n = 0; n < adapter->num_tx_queues; n++) {
 390                 tx_ring = adapter->tx_ring[n];
 391                 pr_info("------------------------------------\n");
 392                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 393                 pr_info("------------------------------------\n");
 394                 pr_info("T [desc]     [address 63:0  ] "
 395                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 396                         "leng  ntw timestamp        bi->skb\n");
 397
 398                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 399                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 400                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 401                         u0 = (struct my_u0 *)tx_desc;
 402                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 403                                 " %04X  %3X %016llX %p", i,
 404                                 le64_to_cpu(u0->a),
 405                                 le64_to_cpu(u0->b),
 406                                 (u64)tx_buffer_info->dma,
 407                                 tx_buffer_info->length,
 408                                 tx_buffer_info->next_to_watch,
 409                                 (u64)tx_buffer_info->time_stamp,
 410                                 tx_buffer_info->skb);
 411                         if (i == tx_ring->next_to_use &&
 412                                 i == tx_ring->next_to_clean)
 413                                 pr_cont(" NTC/U\n");
 414                         else if (i == tx_ring->next_to_use)
 415                                 pr_cont(" NTU\n");
 416                         else if (i == tx_ring->next_to_clean)
 417                                 pr_cont(" NTC\n");
 418                         else
 419                                 pr_cont("\n");
 420
 421                         if (netif_msg_pktdata(adapter) &&
 422                                 tx_buffer_info->dma != 0)
 423                                 print_hex_dump(KERN_INFO, "",
 424                                         DUMP_PREFIX_ADDRESS, 16, 1,
 425                                         phys_to_virt(tx_buffer_info->dma),
 426                                         tx_buffer_info->length, true);
 427                 }
 428         }
 429
 430         /* Print RX Rings Summary */
 431 rx_ring_summary:
 432         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 433         pr_info("Queue [NTU] [NTC]\n");
 434         for (n = 0; n < adapter->num_rx_queues; n++) {
 435                 rx_ring = adapter->rx_ring[n];
 436                 pr_info("%5d %5X %5X\n",
 437                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 438         }
 439
 440         /* Print RX Rings */
 441         if (!netif_msg_rx_status(adapter))
 442                 goto exit;
 443
 444         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 445
 446         /* Advanced Receive Descriptor (Read) Format
 447          *    63                                           1        0
 448          *    +-----------------------------------------------------+
 449          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 450          *    +----------------------------------------------+------+
 451          *  8 |       Header Buffer Address [63:1]           |  DD  |
 452          *    +-----------------------------------------------------+
 453          *
 454          *
 455          * Advanced Receive Descriptor (Write-Back) Format
 456          *
 457          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 458          *   +------------------------------------------------------+
 459          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 460          *   | Checksum   Ident  |   |           |    | Type | Type |
 461          *   +------------------------------------------------------+
 462          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 463          *   +------------------------------------------------------+
 464          *   63       48 47    32 31            20 19               0
 465          */
 466         for (n = 0; n < adapter->num_rx_queues; n++) {
 467                 rx_ring = adapter->rx_ring[n];
 468                 pr_info("------------------------------------\n");
 469                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 470                 pr_info("------------------------------------\n");
 471                 pr_info("R  [desc]      [ PktBuf     A0] "
 472                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 473                         "<-- Adv Rx Read format\n");
 474                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 475                         "[vl er S cks ln] ---------------- [bi->skb] "
 476                         "<-- Adv Rx Write-Back format\n");
 477
 478                 for (i = 0; i < rx_ring->count; i++) {
 479                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 480                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 481                         u0 = (struct my_u0 *)rx_desc;
 482                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 483                         if (staterr & IXGBE_RXD_STAT_DD) {
 484                                 /* Descriptor Done */
 485                                 pr_info("RWB[0x%03X]     %016llX "
 486                                         "%016llX ---------------- %p", i,
 487                                         le64_to_cpu(u0->a),
 488                                         le64_to_cpu(u0->b),
 489                                         rx_buffer_info->skb);
 490                         } else {
 491                                 pr_info("R  [0x%03X]     %016llX "
 492                                         "%016llX %016llX %p", i,
 493                                         le64_to_cpu(u0->a),
 494                                         le64_to_cpu(u0->b),
 495                                         (u64)rx_buffer_info->dma,
 496                                         rx_buffer_info->skb);
 497
 498                                 if (netif_msg_pktdata(adapter)) {
 499                                         print_hex_dump(KERN_INFO, "",
 500                                            DUMP_PREFIX_ADDRESS, 16, 1,
 501                                            phys_to_virt(rx_buffer_info->dma),
 502                                            rx_ring->rx_buf_len, true);
 503
 504                                         if (rx_ring->rx_buf_len
 505                                                 < IXGBE_RXBUFFER_2048)
 506                                                 print_hex_dump(KERN_INFO, "",
 507                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 508                                                   phys_to_virt(
 509                                                     rx_buffer_info->page_dma +
 510                                                     rx_buffer_info->page_offset
 511                                                   ),
 512                                                   PAGE_SIZE/2, true);
 513                                 }
 514                         }
 515
 516                         if (i == rx_ring->next_to_use)
 517                                 pr_cont(" NTU\n");
 518                         else if (i == rx_ring->next_to_clean)
 519                                 pr_cont(" NTC\n");
 520                         else
 521                                 pr_cont("\n");
 522
 523                 }
 524         }
 525
 526 exit:
 527         return;
 528 }
 529
 530 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 531 {
 532         u32 ctrl_ext;
 533
 534         /* Let firmware take over control of h/w */
 535         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 536         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 537                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 538 }
 539
 540 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 541 {
 542         u32 ctrl_ext;
 543
 544         /* Let firmware know the driver has taken over */
 545         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 546         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 547                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 548 }
 549
 550 /*
 551  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 552  * @adapter: pointer to adapter struct
 553  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 554  * @queue: queue to map the corresponding interrupt to
 555  * @msix_vector: the vector to map to the corresponding queue
 556  *
 557  */
 558 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 559                            u8 queue, u8 msix_vector)
 560 {
 561         u32 ivar, index;
 562         struct ixgbe_hw *hw = &adapter->hw;
 563         switch (hw->mac.type) {
 564         case ixgbe_mac_82598EB:
 565                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                 if (direction == -1)
 567                         direction = 0;
 568                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 569                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 570                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 571                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 572                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 573                 break;
 574         case ixgbe_mac_82599EB:
 575         case ixgbe_mac_X540:
 576                 if (direction == -1) {
 577                         /* other causes */
 578                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 579                         index = ((queue & 1) * 8);
 580                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 581                         ivar &= ~(0xFF << index);
 582                         ivar |= (msix_vector << index);
 583                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 584                         break;
 585                 } else {
 586                         /* tx or rx causes */
 587                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 588                         index = ((16 * (queue & 1)) + (8 * direction));
 589                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 590                         ivar &= ~(0xFF << index);
 591                         ivar |= (msix_vector << index);
 592                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 593                         break;
 594                 }
 595         default:
 596                 break;
 597         }
 598 }
 599
 600 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 601                                           u64 qmask)
 602 {
 603         u32 mask;
 604
 605         switch (adapter->hw.mac.type) {
 606         case ixgbe_mac_82598EB:
 607                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 608                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 609                 break;
 610         case ixgbe_mac_82599EB:
 611         case ixgbe_mac_X540:
 612                 mask = (qmask & 0xFFFFFFFF);
 613                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 614                 mask = (qmask >> 32);
 615                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 616                 break;
 617         default:
 618                 break;
 619         }
 620 }
 621
 622 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 623                                       struct ixgbe_tx_buffer *tx_buffer_info)
 624 {
 625         if (tx_buffer_info->dma) {
 626                 if (tx_buffer_info->mapped_as_page)
 627                         dma_unmap_page(tx_ring->dev,
 628                                        tx_buffer_info->dma,
 629                                        tx_buffer_info->length,
 630                                        DMA_TO_DEVICE);
 631                 else
 632                         dma_unmap_single(tx_ring->dev,
 633                                          tx_buffer_info->dma,
 634                                          tx_buffer_info->length,
 635                                          DMA_TO_DEVICE);
 636                 tx_buffer_info->dma = 0;
 637         }
 638         if (tx_buffer_info->skb) {
 639                 dev_kfree_skb_any(tx_buffer_info->skb);
 640                 tx_buffer_info->skb = NULL;
 641         }
 642         tx_buffer_info->time_stamp = 0;
 643         /* tx_buffer_info must be completely set up in the transmit path */
 644 }
 645
 646 /**
 647  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 648  * @adapter: driver private struct
 649  * @index: reg idx of queue to query (0-127)
 650  *
 651  * Helper function to determine the traffic index for a particular
 652  * register index.
 653  *
 654  * Returns : a tc index for use in range 0-7, or 0-3
 655  */
 656 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 657 {
 658         int tc = -1;
 659         int dcb_i = netdev_get_num_tc(adapter->netdev);
 660
 661         /* if DCB is not enabled the queues have no TC */
 662         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 663                 return tc;
 664
 665         /* check valid range */
 666         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 667                 return tc;
 668
 669         switch (adapter->hw.mac.type) {
 670         case ixgbe_mac_82598EB:
 671                 tc = reg_idx >> 2;
 672                 break;
 673         default:
 674                 if (dcb_i != 4 && dcb_i != 8)
 675                         break;
 676
 677                 /* if VMDq is enabled the lowest order bits determine TC */
 678                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 679                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 680                         tc = reg_idx & (dcb_i - 1);
 681                         break;
 682                 }
 683
 684                 /*
 685                  * Convert the reg_idx into the correct TC. This bitmask
 686                  * targets the last full 32 ring traffic class and assigns
 687                  * it a value of 1. From there the rest of the rings are
 688                  * based on shifting the mask further up to include the
 689                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 690                  * will only ever be 8 or 4 and that reg_idx will never
 691                  * be greater then 128. The code without the power of 2
 692                  * optimizations would be:
 693                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 694                  */
 695                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 696                 tc >>= 9 - (reg_idx >> 5);
 697         }
 698
 699         return tc;
 700 }
 701
 702 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 703 {
 704         struct ixgbe_hw *hw = &adapter->hw;
 705         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 706         u32 data = 0;
 707         u32 xoff[8] = {0};
 708         int i;
 709
 710         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 711             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 712                 switch (hw->mac.type) {
 713                 case ixgbe_mac_82598EB:
 714                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 715                         break;
 716                 default:
 717                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 718                 }
 719                 hwstats->lxoffrxc += data;
 720
 721                 /* refill credits (no tx hang) if we received xoff */
 722                 if (!data)
 723                         return;
 724
 725                 for (i = 0; i < adapter->num_tx_queues; i++)
 726                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 727                                   &adapter->tx_ring[i]->state);
 728                 return;
 729         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 730                 return;
 731
 732         /* update stats for each tc, only valid with PFC enabled */
 733         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 734                 switch (hw->mac.type) {
 735                 case ixgbe_mac_82598EB:
 736                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 737                         break;
 738                 default:
 739                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 740                 }
 741                 hwstats->pxoffrxc[i] += xoff[i];
 742         }
 743
 744         /* disarm tx queues that have received xoff frames */
 745         for (i = 0; i < adapter->num_tx_queues; i++) {
 746                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 747                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 748
 749                 if (xoff[tc])
 750                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 751         }
 752 }
 753
 754 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 755 {
 756         return ring->tx_stats.completed;
 757 }
 758
 759 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 760 {
 761         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 762         struct ixgbe_hw *hw = &adapter->hw;
 763
 764         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 765         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 766
 767         if (head != tail)
 768                 return (head < tail) ?
 769                         tail - head : (tail + ring->count - head);
 770
 771         return 0;
 772 }
 773
 774 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 775 {
 776         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 777         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 778         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 779         bool ret = false;
 780
 781         clear_check_for_tx_hang(tx_ring);
 782
 783         /*
 784          * Check for a hung queue, but be thorough. This verifies
 785          * that a transmit has been completed since the previous
 786          * check AND there is at least one packet pending. The
 787          * ARMED bit is set to indicate a potential hang. The
 788          * bit is cleared if a pause frame is received to remove
 789          * false hang detection due to PFC or 802.3x frames. By
 790          * requiring this to fail twice we avoid races with
 791          * pfc clearing the ARMED bit and conditions where we
 792          * run the check_tx_hang logic with a transmit completion
 793          * pending but without time to complete it yet.
 794          */
 795         if ((tx_done_old == tx_done) && tx_pending) {
 796                 /* make sure it is true for two checks in a row */
 797                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 798                                        &tx_ring->state);
 799         } else {
 800                 /* update completed stats and continue */
 801                 tx_ring->tx_stats.tx_done_old = tx_done;
 802                 /* reset the countdown */
 803                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 804         }
 805
 806         return ret;
 807 }
 808
 809 #define IXGBE_MAX_TXD_PWR       14
 810 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 811
 812 /* Tx Descriptors needed, worst case */
 813 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 814                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 815 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 816         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 817
 818 static void ixgbe_tx_timeout(struct net_device *netdev);
 819
 820 /**
 821  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 822  * @q_vector: structure containing interrupt and ring information
 823  * @tx_ring: tx ring to clean
 824  **/
 825 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 826                                struct ixgbe_ring *tx_ring)
 827 {
 828         struct ixgbe_adapter *adapter = q_vector->adapter;
 829         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 830         struct ixgbe_tx_buffer *tx_buffer_info;
 831         unsigned int total_bytes = 0, total_packets = 0;
 832         u16 i, eop, count = 0;
 833
 834         i = tx_ring->next_to_clean;
 835         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 836         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 837
 838         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 839                (count < tx_ring->work_limit)) {
 840                 bool cleaned = false;
 841                 rmb(); /* read buffer_info after eop_desc */
 842                 for ( ; !cleaned; count++) {
 843                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 844                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 845
 846                         tx_desc->wb.status = 0;
 847                         cleaned = (i == eop);
 848
 849                         i++;
 850                         if (i == tx_ring->count)
 851                                 i = 0;
 852
 853                         if (cleaned && tx_buffer_info->skb) {
 854                                 total_bytes += tx_buffer_info->bytecount;
 855                                 total_packets += tx_buffer_info->gso_segs;
 856                         }
 857
 858                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 859                                                          tx_buffer_info);
 860                 }
 861
 862                 tx_ring->tx_stats.completed++;
 863                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 864                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 865         }
 866
 867         tx_ring->next_to_clean = i;
 868         tx_ring->total_bytes += total_bytes;
 869         tx_ring->total_packets += total_packets;
 870         u64_stats_update_begin(&tx_ring->syncp);
 871         tx_ring->stats.packets += total_packets;
 872         tx_ring->stats.bytes += total_bytes;
 873         u64_stats_update_end(&tx_ring->syncp);
 874
 875         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 876                 /* schedule immediate reset if we believe we hung */
 877                 struct ixgbe_hw *hw = &adapter->hw;
 878                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 879                 e_err(drv, "Detected Tx Unit Hang\n"
 880                         "  Tx Queue             <%d>\n"
 881                         "  TDH, TDT             <%x>, <%x>\n"
 882                         "  next_to_use          <%x>\n"
 883                         "  next_to_clean        <%x>\n"
 884                         "tx_buffer_info[next_to_clean]\n"
 885                         "  time_stamp           <%lx>\n"
 886                         "  jiffies              <%lx>\n",
 887                         tx_ring->queue_index,
 888                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 889                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 890                         tx_ring->next_to_use, eop,
 891                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 892
 893                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 894
 895                 e_info(probe,
 896                        "tx hang %d detected on queue %d, resetting adapter\n",
 897                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 898
 899                 /* schedule immediate reset if we believe we hung */
 900                 ixgbe_tx_timeout(adapter->netdev);
 901
 902                 /* the adapter is about to reset, no point in enabling stuff */
 903                 return true;
 904         }
 905
 906 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 907         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 908                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 909                 /* Make sure that anybody stopping the queue after this
 910                  * sees the new next_to_clean.
 911                  */
 912                 smp_mb();
 913                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 914                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 915                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 916                         ++tx_ring->tx_stats.restart_queue;
 917                 }
 918         }
 919
 920         return count < tx_ring->work_limit;
 921 }
 922
 923 #ifdef CONFIG_IXGBE_DCA
 924 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 925                                 struct ixgbe_ring *rx_ring,
 926                                 int cpu)
 927 {
 928         struct ixgbe_hw *hw = &adapter->hw;
 929         u32 rxctrl;
 930         u8 reg_idx = rx_ring->reg_idx;
 931
 932         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 933         switch (hw->mac.type) {
 934         case ixgbe_mac_82598EB:
 935                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 936                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 937                 break;
 938         case ixgbe_mac_82599EB:
 939         case ixgbe_mac_X540:
 940                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 941                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 942                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 943                 break;
 944         default:
 945                 break;
 946         }
 947         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 948         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 949         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 950         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 951                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 952         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 953 }
 954
 955 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 956                                 struct ixgbe_ring *tx_ring,
 957                                 int cpu)
 958 {
 959         struct ixgbe_hw *hw = &adapter->hw;
 960         u32 txctrl;
 961         u8 reg_idx = tx_ring->reg_idx;
 962
 963         switch (hw->mac.type) {
 964         case ixgbe_mac_82598EB:
 965                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 966                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 967                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 968                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 969                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 970                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 971                 break;
 972         case ixgbe_mac_82599EB:
 973         case ixgbe_mac_X540:
 974                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 975                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 976                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 977                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 978                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 979                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 980                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 981                 break;
 982         default:
 983                 break;
 984         }
 985 }
 986
 987 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 988 {
 989         struct ixgbe_adapter *adapter = q_vector->adapter;
 990         int cpu = get_cpu();
 991         long r_idx;
 992         int i;
 993
 994         if (q_vector->cpu == cpu)
 995                 goto out_no_update;
 996
 997         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 998         for (i = 0; i < q_vector->txr_count; i++) {
 999                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1000                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1001                                       r_idx + 1);
1002         }
1003
1004         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1005         for (i = 0; i < q_vector->rxr_count; i++) {
1006                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1007                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1008                                       r_idx + 1);
1009         }
1010
1011         q_vector->cpu = cpu;
1012 out_no_update:
1013         put_cpu();
1014 }
1015
1016 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1017 {
1018         int num_q_vectors;
1019         int i;
1020
1021         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1022                 return;
1023
1024         /* always use CB2 mode, difference is masked in the CB driver */
1025         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1026
1027         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1028                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1029         else
1030                 num_q_vectors = 1;
1031
1032         for (i = 0; i < num_q_vectors; i++) {
1033                 adapter->q_vector[i]->cpu = -1;
1034                 ixgbe_update_dca(adapter->q_vector[i]);
1035         }
1036 }
1037
1038 static int __ixgbe_notify_dca(struct device *dev, void *data)
1039 {
1040         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1041         unsigned long event = *(unsigned long *)data;
1042
1043         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1044                 return 0;
1045
1046         switch (event) {
1047         case DCA_PROVIDER_ADD:
1048                 /* if we're already enabled, don't do it again */
1049                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1050                         break;
1051                 if (dca_add_requester(dev) == 0) {
1052                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1053                         ixgbe_setup_dca(adapter);
1054                         break;
1055                 }
1056                 /* Fall Through since DCA is disabled. */
1057         case DCA_PROVIDER_REMOVE:
1058                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1059                         dca_remove_requester(dev);
1060                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1061                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1062                 }
1063                 break;
1064         }
1065
1066         return 0;
1067 }
1068
1069 #endif /* CONFIG_IXGBE_DCA */
1070 /**
1071  * ixgbe_receive_skb - Send a completed packet up the stack
1072  * @adapter: board private structure
1073  * @skb: packet to send up
1074  * @status: hardware indication of status of receive
1075  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1076  * @rx_desc: rx descriptor
1077  **/
1078 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1079                               struct sk_buff *skb, u8 status,
1080                               struct ixgbe_ring *ring,
1081                               union ixgbe_adv_rx_desc *rx_desc)
1082 {
1083         struct ixgbe_adapter *adapter = q_vector->adapter;
1084         struct napi_struct *napi = &q_vector->napi;
1085         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1086         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1087
1088         if (is_vlan && (tag & VLAN_VID_MASK))
1089                 __vlan_hwaccel_put_tag(skb, tag);
1090
1091         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1092                 napi_gro_receive(napi, skb);
1093         else
1094                 netif_rx(skb);
1095 }
1096
1097 /**
1098  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1099  * @adapter: address of board private structure
1100  * @status_err: hardware indication of status of receive
1101  * @skb: skb currently being received and modified
1102  **/
1103 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1104                                      union ixgbe_adv_rx_desc *rx_desc,
1105                                      struct sk_buff *skb)
1106 {
1107         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1108
1109         skb_checksum_none_assert(skb);
1110
1111         /* Rx csum disabled */
1112         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1113                 return;
1114
1115         /* if IP and error */
1116         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1117             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1118                 adapter->hw_csum_rx_error++;
1119                 return;
1120         }
1121
1122         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1123                 return;
1124
1125         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1126                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1127
1128                 /*
1129                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1130                  * checksum errors.
1131                  */
1132                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1133                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1134                         return;
1135
1136                 adapter->hw_csum_rx_error++;
1137                 return;
1138         }
1139
1140         /* It must be a TCP or UDP packet with a valid checksum */
1141         skb->ip_summed = CHECKSUM_UNNECESSARY;
1142 }
1143
1144 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1145 {
1146         /*
1147          * Force memory writes to complete before letting h/w
1148          * know there are new descriptors to fetch.  (Only
1149          * applicable for weak-ordered memory model archs,
1150          * such as IA-64).
1151          */
1152         wmb();
1153         writel(val, rx_ring->tail);
1154 }
1155
1156 /**
1157  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1158  * @rx_ring: ring to place buffers on
1159  * @cleaned_count: number of buffers to replace
1160  **/
1161 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1162 {
1163         union ixgbe_adv_rx_desc *rx_desc;
1164         struct ixgbe_rx_buffer *bi;
1165         struct sk_buff *skb;
1166         u16 i = rx_ring->next_to_use;
1167
1168         /* do nothing if no valid netdev defined */
1169         if (!rx_ring->netdev)
1170                 return;
1171
1172         while (cleaned_count--) {
1173                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1174                 bi = &rx_ring->rx_buffer_info[i];
1175                 skb = bi->skb;
1176
1177                 if (!skb) {
1178                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1179                                                         rx_ring->rx_buf_len);
1180                         if (!skb) {
1181                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1182                                 goto no_buffers;
1183                         }
1184                         /* initialize queue mapping */
1185                         skb_record_rx_queue(skb, rx_ring->queue_index);
1186                         bi->skb = skb;
1187                 }
1188
1189                 if (!bi->dma) {
1190                         bi->dma = dma_map_single(rx_ring->dev,
1191                                                  skb->data,
1192                                                  rx_ring->rx_buf_len,
1193                                                  DMA_FROM_DEVICE);
1194                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1195                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1196                                 bi->dma = 0;
1197                                 goto no_buffers;
1198                         }
1199                 }
1200
1201                 if (ring_is_ps_enabled(rx_ring)) {
1202                         if (!bi->page) {
1203                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1204                                 if (!bi->page) {
1205                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1206                                         goto no_buffers;
1207                                 }
1208                         }
1209
1210                         if (!bi->page_dma) {
1211                                 /* use a half page if we're re-using */
1212                                 bi->page_offset ^= PAGE_SIZE / 2;
1213                                 bi->page_dma = dma_map_page(rx_ring->dev,
1214                                                             bi->page,
1215                                                             bi->page_offset,
1216                                                             PAGE_SIZE / 2,
1217                                                             DMA_FROM_DEVICE);
1218                                 if (dma_mapping_error(rx_ring->dev,
1219                                                       bi->page_dma)) {
1220                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1221                                         bi->page_dma = 0;
1222                                         goto no_buffers;
1223                                 }
1224                         }
1225
1226                         /* Refresh the desc even if buffer_addrs didn't change
1227                          * because each write-back erases this info. */
1228                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1229                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1230                 } else {
1231                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1232                         rx_desc->read.hdr_addr = 0;
1233                 }
1234
1235                 i++;
1236                 if (i == rx_ring->count)
1237                         i = 0;
1238         }
1239
1240 no_buffers:
1241         if (rx_ring->next_to_use != i) {
1242                 rx_ring->next_to_use = i;
1243                 ixgbe_release_rx_desc(rx_ring, i);
1244         }
1245 }
1246
1247 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1248 {
1249         /* HW will not DMA in data larger than the given buffer, even if it
1250          * parses the (NFS, of course) header to be larger.  In that case, it
1251          * fills the header buffer and spills the rest into the page.
1252          */
1253         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1254         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1255                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1256         if (hlen > IXGBE_RX_HDR_SIZE)
1257                 hlen = IXGBE_RX_HDR_SIZE;
1258         return hlen;
1259 }
1260
1261 /**
1262  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1263  * @skb: pointer to the last skb in the rsc queue
1264  *
1265  * This function changes a queue full of hw rsc buffers into a completed
1266  * packet.  It uses the ->prev pointers to find the first packet and then
1267  * turns it into the frag list owner.
1268  **/
1269 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1270 {
1271         unsigned int frag_list_size = 0;
1272         unsigned int skb_cnt = 1;
1273
1274         while (skb->prev) {
1275                 struct sk_buff *prev = skb->prev;
1276                 frag_list_size += skb->len;
1277                 skb->prev = NULL;
1278                 skb = prev;
1279                 skb_cnt++;
1280         }
1281
1282         skb_shinfo(skb)->frag_list = skb->next;
1283         skb->next = NULL;
1284         skb->len += frag_list_size;
1285         skb->data_len += frag_list_size;
1286         skb->truesize += frag_list_size;
1287         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1288
1289         return skb;
1290 }
1291
1292 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1293 {
1294         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1295                 IXGBE_RXDADV_RSCCNT_MASK);
1296 }
1297
1298 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1299                                struct ixgbe_ring *rx_ring,
1300                                int *work_done, int work_to_do)
1301 {
1302         struct ixgbe_adapter *adapter = q_vector->adapter;
1303         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1304         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1305         struct sk_buff *skb;
1306         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1307         const int current_node = numa_node_id();
1308 #ifdef IXGBE_FCOE
1309         int ddp_bytes = 0;
1310 #endif /* IXGBE_FCOE */
1311         u32 staterr;
1312         u16 i;
1313         u16 cleaned_count = 0;
1314         bool pkt_is_rsc = false;
1315
1316         i = rx_ring->next_to_clean;
1317         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1318         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1319
1320         while (staterr & IXGBE_RXD_STAT_DD) {
1321                 u32 upper_len = 0;
1322
1323                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1324
1325                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1326
1327                 skb = rx_buffer_info->skb;
1328                 rx_buffer_info->skb = NULL;
1329                 prefetch(skb->data);
1330
1331                 if (ring_is_rsc_enabled(rx_ring))
1332                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1333
1334                 /* if this is a skb from previous receive DMA will be 0 */
1335                 if (rx_buffer_info->dma) {
1336                         u16 hlen;
1337                         if (pkt_is_rsc &&
1338                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1339                             !skb->prev) {
1340                                 /*
1341                                  * When HWRSC is enabled, delay unmapping
1342                                  * of the first packet. It carries the
1343                                  * header information, HW may still
1344                                  * access the header after the writeback.
1345                                  * Only unmap it when EOP is reached
1346                                  */
1347                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1348                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1349                         } else {
1350                                 dma_unmap_single(rx_ring->dev,
1351                                                  rx_buffer_info->dma,
1352                                                  rx_ring->rx_buf_len,
1353                                                  DMA_FROM_DEVICE);
1354                         }
1355                         rx_buffer_info->dma = 0;
1356
1357                         if (ring_is_ps_enabled(rx_ring)) {
1358                                 hlen = ixgbe_get_hlen(rx_desc);
1359                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1360                         } else {
1361                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1362                         }
1363
1364                         skb_put(skb, hlen);
1365                 } else {
1366                         /* assume packet split since header is unmapped */
1367                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1368                 }
1369
1370                 if (upper_len) {
1371                         dma_unmap_page(rx_ring->dev,
1372                                        rx_buffer_info->page_dma,
1373                                        PAGE_SIZE / 2,
1374                                        DMA_FROM_DEVICE);
1375                         rx_buffer_info->page_dma = 0;
1376                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1377                                            rx_buffer_info->page,
1378                                            rx_buffer_info->page_offset,
1379                                            upper_len);
1380
1381                         if ((page_count(rx_buffer_info->page) == 1) &&
1382                             (page_to_nid(rx_buffer_info->page) == current_node))
1383                                 get_page(rx_buffer_info->page);
1384                         else
1385                                 rx_buffer_info->page = NULL;
1386
1387                         skb->len += upper_len;
1388                         skb->data_len += upper_len;
1389                         skb->truesize += upper_len;
1390                 }
1391
1392                 i++;
1393                 if (i == rx_ring->count)
1394                         i = 0;
1395
1396                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1397                 prefetch(next_rxd);
1398                 cleaned_count++;
1399
1400                 if (pkt_is_rsc) {
1401                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1402                                      IXGBE_RXDADV_NEXTP_SHIFT;
1403                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1404                 } else {
1405                         next_buffer = &rx_ring->rx_buffer_info[i];
1406                 }
1407
1408                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1409                         if (ring_is_ps_enabled(rx_ring)) {
1410                                 rx_buffer_info->skb = next_buffer->skb;
1411                                 rx_buffer_info->dma = next_buffer->dma;
1412                                 next_buffer->skb = skb;
1413                                 next_buffer->dma = 0;
1414                         } else {
1415                                 skb->next = next_buffer->skb;
1416                                 skb->next->prev = skb;
1417                         }
1418                         rx_ring->rx_stats.non_eop_descs++;
1419                         goto next_desc;
1420                 }
1421
1422                 if (skb->prev) {
1423                         skb = ixgbe_transform_rsc_queue(skb);
1424                         /* if we got here without RSC the packet is invalid */
1425                         if (!pkt_is_rsc) {
1426                                 __pskb_trim(skb, 0);
1427                                 rx_buffer_info->skb = skb;
1428                                 goto next_desc;
1429                         }
1430                 }
1431
1432                 if (ring_is_rsc_enabled(rx_ring)) {
1433                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1434                                 dma_unmap_single(rx_ring->dev,
1435                                                  IXGBE_RSC_CB(skb)->dma,
1436                                                  rx_ring->rx_buf_len,
1437                                                  DMA_FROM_DEVICE);
1438                                 IXGBE_RSC_CB(skb)->dma = 0;
1439                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1440                         }
1441                 }
1442                 if (pkt_is_rsc) {
1443                         if (ring_is_ps_enabled(rx_ring))
1444                                 rx_ring->rx_stats.rsc_count +=
1445                                         skb_shinfo(skb)->nr_frags;
1446                         else
1447                                 rx_ring->rx_stats.rsc_count +=
1448                                         IXGBE_RSC_CB(skb)->skb_cnt;
1449                         rx_ring->rx_stats.rsc_flush++;
1450                 }
1451
1452                 /* ERR_MASK will only have valid bits if EOP set */
1453                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1454                         /* trim packet back to size 0 and recycle it */
1455                         __pskb_trim(skb, 0);
1456                         rx_buffer_info->skb = skb;
1457                         goto next_desc;
1458                 }
1459
1460                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1461
1462                 /* probably a little skewed due to removing CRC */
1463                 total_rx_bytes += skb->len;
1464                 total_rx_packets++;
1465
1466                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1467 #ifdef IXGBE_FCOE
1468                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1469                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1470                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1471                         if (!ddp_bytes)
1472                                 goto next_desc;
1473                 }
1474 #endif /* IXGBE_FCOE */
1475                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1476
1477 next_desc:
1478                 rx_desc->wb.upper.status_error = 0;
1479
1480                 (*work_done)++;
1481                 if (*work_done >= work_to_do)
1482                         break;
1483
1484                 /* return some buffers to hardware, one at a time is too slow */
1485                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1486                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1487                         cleaned_count = 0;
1488                 }
1489
1490                 /* use prefetched values */
1491                 rx_desc = next_rxd;
1492                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1493         }
1494
1495         rx_ring->next_to_clean = i;
1496         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1497
1498         if (cleaned_count)
1499                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1500
1501 #ifdef IXGBE_FCOE
1502         /* include DDPed FCoE data */
1503         if (ddp_bytes > 0) {
1504                 unsigned int mss;
1505
1506                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1507                         sizeof(struct fc_frame_header) -
1508                         sizeof(struct fcoe_crc_eof);
1509                 if (mss > 512)
1510                         mss &= ~511;
1511                 total_rx_bytes += ddp_bytes;
1512                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1513         }
1514 #endif /* IXGBE_FCOE */
1515
1516         rx_ring->total_packets += total_rx_packets;
1517         rx_ring->total_bytes += total_rx_bytes;
1518         u64_stats_update_begin(&rx_ring->syncp);
1519         rx_ring->stats.packets += total_rx_packets;
1520         rx_ring->stats.bytes += total_rx_bytes;
1521         u64_stats_update_end(&rx_ring->syncp);
1522 }
1523
1524 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1525 /**
1526  * ixgbe_configure_msix - Configure MSI-X hardware
1527  * @adapter: board private structure
1528  *
1529  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1530  * interrupts.
1531  **/
1532 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1533 {
1534         struct ixgbe_q_vector *q_vector;
1535         int i, q_vectors, v_idx, r_idx;
1536         u32 mask;
1537
1538         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1539
1540         /*
1541          * Populate the IVAR table and set the ITR values to the
1542          * corresponding register.
1543          */
1544         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1545                 q_vector = adapter->q_vector[v_idx];
1546                 /* XXX for_each_set_bit(...) */
1547                 r_idx = find_first_bit(q_vector->rxr_idx,
1548                                        adapter->num_rx_queues);
1549
1550                 for (i = 0; i < q_vector->rxr_count; i++) {
1551                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1552                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1553                         r_idx = find_next_bit(q_vector->rxr_idx,
1554                                               adapter->num_rx_queues,
1555                                               r_idx + 1);
1556                 }
1557                 r_idx = find_first_bit(q_vector->txr_idx,
1558                                        adapter->num_tx_queues);
1559
1560                 for (i = 0; i < q_vector->txr_count; i++) {
1561                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1562                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1563                         r_idx = find_next_bit(q_vector->txr_idx,
1564                                               adapter->num_tx_queues,
1565                                               r_idx + 1);
1566                 }
1567
1568                 if (q_vector->txr_count && !q_vector->rxr_count)
1569                         /* tx only */
1570                         q_vector->eitr = adapter->tx_eitr_param;
1571                 else if (q_vector->rxr_count)
1572                         /* rx or mixed */
1573                         q_vector->eitr = adapter->rx_eitr_param;
1574
1575                 ixgbe_write_eitr(q_vector);
1576                 /* If Flow Director is enabled, set interrupt affinity */
1577                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1578                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1579                         /*
1580                          * Allocate the affinity_hint cpumask, assign the mask
1581                          * for this vector, and set our affinity_hint for
1582                          * this irq.
1583                          */
1584                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1585                                                GFP_KERNEL))
1586                                 return;
1587                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1588                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1589                                               q_vector->affinity_mask);
1590                 }
1591         }
1592
1593         switch (adapter->hw.mac.type) {
1594         case ixgbe_mac_82598EB:
1595                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1596                                v_idx);
1597                 break;
1598         case ixgbe_mac_82599EB:
1599         case ixgbe_mac_X540:
1600                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1601                 break;
1602
1603         default:
1604                 break;
1605         }
1606         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1607
1608         /* set up to autoclear timer, and the vectors */
1609         mask = IXGBE_EIMS_ENABLE_MASK;
1610         if (adapter->num_vfs)
1611                 mask &= ~(IXGBE_EIMS_OTHER |
1612                           IXGBE_EIMS_MAILBOX |
1613                           IXGBE_EIMS_LSC);
1614         else
1615                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1616         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1617 }
1618
1619 enum latency_range {
1620         lowest_latency = 0,
1621         low_latency = 1,
1622         bulk_latency = 2,
1623         latency_invalid = 255
1624 };
1625
1626 /**
1627  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1628  * @adapter: pointer to adapter
1629  * @eitr: eitr setting (ints per sec) to give last timeslice
1630  * @itr_setting: current throttle rate in ints/second
1631  * @packets: the number of packets during this measurement interval
1632  * @bytes: the number of bytes during this measurement interval
1633  *
1634  *      Stores a new ITR value based on packets and byte
1635  *      counts during the last interrupt.  The advantage of per interrupt
1636  *      computation is faster updates and more accurate ITR for the current
1637  *      traffic pattern.  Constants in this function were computed
1638  *      based on theoretical maximum wire speed and thresholds were set based
1639  *      on testing data as well as attempting to minimize response time
1640  *      while increasing bulk throughput.
1641  *      this functionality is controlled by the InterruptThrottleRate module
1642  *      parameter (see ixgbe_param.c)
1643  **/
1644 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1645                            u32 eitr, u8 itr_setting,
1646                            int packets, int bytes)
1647 {
1648         unsigned int retval = itr_setting;
1649         u32 timepassed_us;
1650         u64 bytes_perint;
1651
1652         if (packets == 0)
1653                 goto update_itr_done;
1654
1655
1656         /* simple throttlerate management
1657          *    0-20MB/s lowest (100000 ints/s)
1658          *   20-100MB/s low   (20000 ints/s)
1659          *  100-1249MB/s bulk (8000 ints/s)
1660          */
1661         /* what was last interrupt timeslice? */
1662         timepassed_us = 1000000/eitr;
1663         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1664
1665         switch (itr_setting) {
1666         case lowest_latency:
1667                 if (bytes_perint > adapter->eitr_low)
1668                         retval = low_latency;
1669                 break;
1670         case low_latency:
1671                 if (bytes_perint > adapter->eitr_high)
1672                         retval = bulk_latency;
1673                 else if (bytes_perint <= adapter->eitr_low)
1674                         retval = lowest_latency;
1675                 break;
1676         case bulk_latency:
1677                 if (bytes_perint <= adapter->eitr_high)
1678                         retval = low_latency;
1679                 break;
1680         }
1681
1682 update_itr_done:
1683         return retval;
1684 }
1685
1686 /**
1687  * ixgbe_write_eitr - write EITR register in hardware specific way
1688  * @q_vector: structure containing interrupt and ring information
1689  *
1690  * This function is made to be called by ethtool and by the driver
1691  * when it needs to update EITR registers at runtime.  Hardware
1692  * specific quirks/differences are taken care of here.
1693  */
1694 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1695 {
1696         struct ixgbe_adapter *adapter = q_vector->adapter;
1697         struct ixgbe_hw *hw = &adapter->hw;
1698         int v_idx = q_vector->v_idx;
1699         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1700
1701         switch (adapter->hw.mac.type) {
1702         case ixgbe_mac_82598EB:
1703                 /* must write high and low 16 bits to reset counter */
1704                 itr_reg |= (itr_reg << 16);
1705                 break;
1706         case ixgbe_mac_82599EB:
1707         case ixgbe_mac_X540:
1708                 /*
1709                  * 82599 and X540 can support a value of zero, so allow it for
1710                  * max interrupt rate, but there is an errata where it can
1711                  * not be zero with RSC
1712                  */
1713                 if (itr_reg == 8 &&
1714                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1715                         itr_reg = 0;
1716
1717                 /*
1718                  * set the WDIS bit to not clear the timer bits and cause an
1719                  * immediate assertion of the interrupt
1720                  */
1721                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1722                 break;
1723         default:
1724                 break;
1725         }
1726         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1727 }
1728
1729 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1730 {
1731         struct ixgbe_adapter *adapter = q_vector->adapter;
1732         int i, r_idx;
1733         u32 new_itr;
1734         u8 current_itr, ret_itr;
1735
1736         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1737         for (i = 0; i < q_vector->txr_count; i++) {
1738                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1739                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1740                                            q_vector->tx_itr,
1741                                            tx_ring->total_packets,
1742                                            tx_ring->total_bytes);
1743                 /* if the result for this queue would decrease interrupt
1744                  * rate for this vector then use that result */
1745                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1746                                     q_vector->tx_itr - 1 : ret_itr);
1747                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1748                                       r_idx + 1);
1749         }
1750
1751         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1752         for (i = 0; i < q_vector->rxr_count; i++) {
1753                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1754                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1755                                            q_vector->rx_itr,
1756                                            rx_ring->total_packets,
1757                                            rx_ring->total_bytes);
1758                 /* if the result for this queue would decrease interrupt
1759                  * rate for this vector then use that result */
1760                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1761                                     q_vector->rx_itr - 1 : ret_itr);
1762                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1763                                       r_idx + 1);
1764         }
1765
1766         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1767
1768         switch (current_itr) {
1769         /* counts and packets in update_itr are dependent on these numbers */
1770         case lowest_latency:
1771                 new_itr = 100000;
1772                 break;
1773         case low_latency:
1774                 new_itr = 20000; /* aka hwitr = ~200 */
1775                 break;
1776         case bulk_latency:
1777         default:
1778                 new_itr = 8000;
1779                 break;
1780         }
1781
1782         if (new_itr != q_vector->eitr) {
1783                 /* do an exponential smoothing */
1784                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1785
1786                 /* save the algorithm value here, not the smoothed one */
1787                 q_vector->eitr = new_itr;
1788
1789                 ixgbe_write_eitr(q_vector);
1790         }
1791 }
1792
1793 /**
1794  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1795  * @work: pointer to work_struct containing our data
1796  **/
1797 static void ixgbe_check_overtemp_task(struct work_struct *work)
1798 {
1799         struct ixgbe_adapter *adapter = container_of(work,
1800                                                      struct ixgbe_adapter,
1801                                                      check_overtemp_task);
1802         struct ixgbe_hw *hw = &adapter->hw;
1803         u32 eicr = adapter->interrupt_event;
1804
1805         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1806                 return;
1807
1808         switch (hw->device_id) {
1809         case IXGBE_DEV_ID_82599_T3_LOM: {
1810                 u32 autoneg;
1811                 bool link_up = false;
1812
1813                 if (hw->mac.ops.check_link)
1814                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1815
1816                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1817                     (eicr & IXGBE_EICR_LSC))
1818                         /* Check if this is due to overtemp */
1819                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1820                                 break;
1821                 return;
1822         }
1823         default:
1824                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1825                         return;
1826                 break;
1827         }
1828         e_crit(drv,
1829                "Network adapter has been stopped because it has over heated. "
1830                "Restart the computer. If the problem persists, "
1831                "power off the system and replace the adapter\n");
1832         /* write to clear the interrupt */
1833         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1834 }
1835
1836 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1837 {
1838         struct ixgbe_hw *hw = &adapter->hw;
1839
1840         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1841             (eicr & IXGBE_EICR_GPI_SDP1)) {
1842                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1843                 /* write to clear the interrupt */
1844                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1845         }
1846 }
1847
1848 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1849 {
1850         struct ixgbe_hw *hw = &adapter->hw;
1851
1852         if (eicr & IXGBE_EICR_GPI_SDP2) {
1853                 /* Clear the interrupt */
1854                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1855                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1856                         schedule_work(&adapter->sfp_config_module_task);
1857         }
1858
1859         if (eicr & IXGBE_EICR_GPI_SDP1) {
1860                 /* Clear the interrupt */
1861                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1862                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1863                         schedule_work(&adapter->multispeed_fiber_task);
1864         }
1865 }
1866
1867 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1868 {
1869         struct ixgbe_hw *hw = &adapter->hw;
1870
1871         adapter->lsc_int++;
1872         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1873         adapter->link_check_timeout = jiffies;
1874         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1875                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1876                 IXGBE_WRITE_FLUSH(hw);
1877                 schedule_work(&adapter->watchdog_task);
1878         }
1879 }
1880
1881 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1882 {
1883         struct net_device *netdev = data;
1884         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1885         struct ixgbe_hw *hw = &adapter->hw;
1886         u32 eicr;
1887
1888         /*
1889          * Workaround for Silicon errata.  Use clear-by-write instead
1890          * of clear-by-read.  Reading with EICS will return the
1891          * interrupt causes without clearing, which later be done
1892          * with the write to EICR.
1893          */
1894         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1895         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1896
1897         if (eicr & IXGBE_EICR_LSC)
1898                 ixgbe_check_lsc(adapter);
1899
1900         if (eicr & IXGBE_EICR_MAILBOX)
1901                 ixgbe_msg_task(adapter);
1902
1903         switch (hw->mac.type) {
1904         case ixgbe_mac_82599EB:
1905                 ixgbe_check_sfp_event(adapter, eicr);
1906                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1907                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1908                         adapter->interrupt_event = eicr;
1909                         schedule_work(&adapter->check_overtemp_task);
1910                 }
1911                 /* now fallthrough to handle Flow Director */
1912         case ixgbe_mac_X540:
1913                 /* Handle Flow Director Full threshold interrupt */
1914                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1915                         int i;
1916                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1917                         /* Disable transmits before FDIR Re-initialization */
1918                         netif_tx_stop_all_queues(netdev);
1919                         for (i = 0; i < adapter->num_tx_queues; i++) {
1920                                 struct ixgbe_ring *tx_ring =
1921                                                             adapter->tx_ring[i];
1922                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1923                                                        &tx_ring->state))
1924                                         schedule_work(&adapter->fdir_reinit_task);
1925                         }
1926                 }
1927                 break;
1928         default:
1929                 break;
1930         }
1931
1932         ixgbe_check_fan_failure(adapter, eicr);
1933
1934         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1935                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1936
1937         return IRQ_HANDLED;
1938 }
1939
1940 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1941                                            u64 qmask)
1942 {
1943         u32 mask;
1944         struct ixgbe_hw *hw = &adapter->hw;
1945
1946         switch (hw->mac.type) {
1947         case ixgbe_mac_82598EB:
1948                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1949                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1950                 break;
1951         case ixgbe_mac_82599EB:
1952         case ixgbe_mac_X540:
1953                 mask = (qmask & 0xFFFFFFFF);
1954                 if (mask)
1955                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1956                 mask = (qmask >> 32);
1957                 if (mask)
1958                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1959                 break;
1960         default:
1961                 break;
1962         }
1963         /* skip the flush */
1964 }
1965
1966 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1967                                             u64 qmask)
1968 {
1969         u32 mask;
1970         struct ixgbe_hw *hw = &adapter->hw;
1971
1972         switch (hw->mac.type) {
1973         case ixgbe_mac_82598EB:
1974                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1975                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1976                 break;
1977         case ixgbe_mac_82599EB:
1978         case ixgbe_mac_X540:
1979                 mask = (qmask & 0xFFFFFFFF);
1980                 if (mask)
1981                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1982                 mask = (qmask >> 32);
1983                 if (mask)
1984                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1985                 break;
1986         default:
1987                 break;
1988         }
1989         /* skip the flush */
1990 }
1991
1992 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1993 {
1994         struct ixgbe_q_vector *q_vector = data;
1995         struct ixgbe_adapter  *adapter = q_vector->adapter;
1996         struct ixgbe_ring     *tx_ring;
1997         int i, r_idx;
1998
1999         if (!q_vector->txr_count)
2000                 return IRQ_HANDLED;
2001
2002         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2003         for (i = 0; i < q_vector->txr_count; i++) {
2004                 tx_ring = adapter->tx_ring[r_idx];
2005                 tx_ring->total_bytes = 0;
2006                 tx_ring->total_packets = 0;
2007                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2008                                       r_idx + 1);
2009         }
2010
2011         /* EIAM disabled interrupts (on this vector) for us */
2012         napi_schedule(&q_vector->napi);
2013
2014         return IRQ_HANDLED;
2015 }
2016
2017 /**
2018  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2019  * @irq: unused
2020  * @data: pointer to our q_vector struct for this interrupt vector
2021  **/
2022 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2023 {
2024         struct ixgbe_q_vector *q_vector = data;
2025         struct ixgbe_adapter  *adapter = q_vector->adapter;
2026         struct ixgbe_ring  *rx_ring;
2027         int r_idx;
2028         int i;
2029
2030 #ifdef CONFIG_IXGBE_DCA
2031         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2032                 ixgbe_update_dca(q_vector);
2033 #endif
2034
2035         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2036         for (i = 0; i < q_vector->rxr_count; i++) {
2037                 rx_ring = adapter->rx_ring[r_idx];
2038                 rx_ring->total_bytes = 0;
2039                 rx_ring->total_packets = 0;
2040                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2041                                       r_idx + 1);
2042         }
2043
2044         if (!q_vector->rxr_count)
2045                 return IRQ_HANDLED;
2046
2047         /* EIAM disabled interrupts (on this vector) for us */
2048         napi_schedule(&q_vector->napi);
2049
2050         return IRQ_HANDLED;
2051 }
2052
2053 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2054 {
2055         struct ixgbe_q_vector *q_vector = data;
2056         struct ixgbe_adapter  *adapter = q_vector->adapter;
2057         struct ixgbe_ring  *ring;
2058         int r_idx;
2059         int i;
2060
2061         if (!q_vector->txr_count && !q_vector->rxr_count)
2062                 return IRQ_HANDLED;
2063
2064         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2065         for (i = 0; i < q_vector->txr_count; i++) {
2066                 ring = adapter->tx_ring[r_idx];
2067                 ring->total_bytes = 0;
2068                 ring->total_packets = 0;
2069                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2070                                       r_idx + 1);
2071         }
2072
2073         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2074         for (i = 0; i < q_vector->rxr_count; i++) {
2075                 ring = adapter->rx_ring[r_idx];
2076                 ring->total_bytes = 0;
2077                 ring->total_packets = 0;
2078                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2079                                       r_idx + 1);
2080         }
2081
2082         /* EIAM disabled interrupts (on this vector) for us */
2083         napi_schedule(&q_vector->napi);
2084
2085         return IRQ_HANDLED;
2086 }
2087
2088 /**
2089  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2090  * @napi: napi struct with our devices info in it
2091  * @budget: amount of work driver is allowed to do this pass, in packets
2092  *
2093  * This function is optimized for cleaning one queue only on a single
2094  * q_vector!!!
2095  **/
2096 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2097 {
2098         struct ixgbe_q_vector *q_vector =
2099                                container_of(napi, struct ixgbe_q_vector, napi);
2100         struct ixgbe_adapter *adapter = q_vector->adapter;
2101         struct ixgbe_ring *rx_ring = NULL;
2102         int work_done = 0;
2103         long r_idx;
2104
2105 #ifdef CONFIG_IXGBE_DCA
2106         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2107                 ixgbe_update_dca(q_vector);
2108 #endif
2109
2110         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2111         rx_ring = adapter->rx_ring[r_idx];
2112
2113         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2114
2115         /* If all Rx work done, exit the polling mode */
2116         if (work_done < budget) {
2117                 napi_complete(napi);
2118                 if (adapter->rx_itr_setting & 1)
2119                         ixgbe_set_itr_msix(q_vector);
2120                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2121                         ixgbe_irq_enable_queues(adapter,
2122                                                 ((u64)1 << q_vector->v_idx));
2123         }
2124
2125         return work_done;
2126 }
2127
2128 /**
2129  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2130  * @napi: napi struct with our devices info in it
2131  * @budget: amount of work driver is allowed to do this pass, in packets
2132  *
2133  * This function will clean more than one rx queue associated with a
2134  * q_vector.
2135  **/
2136 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2137 {
2138         struct ixgbe_q_vector *q_vector =
2139                                container_of(napi, struct ixgbe_q_vector, napi);
2140         struct ixgbe_adapter *adapter = q_vector->adapter;
2141         struct ixgbe_ring *ring = NULL;
2142         int work_done = 0, i;
2143         long r_idx;
2144         bool tx_clean_complete = true;
2145
2146 #ifdef CONFIG_IXGBE_DCA
2147         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2148                 ixgbe_update_dca(q_vector);
2149 #endif
2150
2151         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2152         for (i = 0; i < q_vector->txr_count; i++) {
2153                 ring = adapter->tx_ring[r_idx];
2154                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2155                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2156                                       r_idx + 1);
2157         }
2158
2159         /* attempt to distribute budget to each queue fairly, but don't allow
2160          * the budget to go below 1 because we'll exit polling */
2161         budget /= (q_vector->rxr_count ?: 1);
2162         budget = max(budget, 1);
2163         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2164         for (i = 0; i < q_vector->rxr_count; i++) {
2165                 ring = adapter->rx_ring[r_idx];
2166                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2167                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2168                                       r_idx + 1);
2169         }
2170
2171         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2172         ring = adapter->rx_ring[r_idx];
2173         /* If all Rx work done, exit the polling mode */
2174         if (work_done < budget) {
2175                 napi_complete(napi);
2176                 if (adapter->rx_itr_setting & 1)
2177                         ixgbe_set_itr_msix(q_vector);
2178                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2179                         ixgbe_irq_enable_queues(adapter,
2180                                                 ((u64)1 << q_vector->v_idx));
2181                 return 0;
2182         }
2183
2184         return work_done;
2185 }
2186
2187 /**
2188  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2189  * @napi: napi struct with our devices info in it
2190  * @budget: amount of work driver is allowed to do this pass, in packets
2191  *
2192  * This function is optimized for cleaning one queue only on a single
2193  * q_vector!!!
2194  **/
2195 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2196 {
2197         struct ixgbe_q_vector *q_vector =
2198                                container_of(napi, struct ixgbe_q_vector, napi);
2199         struct ixgbe_adapter *adapter = q_vector->adapter;
2200         struct ixgbe_ring *tx_ring = NULL;
2201         int work_done = 0;
2202         long r_idx;
2203
2204 #ifdef CONFIG_IXGBE_DCA
2205         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2206                 ixgbe_update_dca(q_vector);
2207 #endif
2208
2209         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2210         tx_ring = adapter->tx_ring[r_idx];
2211
2212         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2213                 work_done = budget;
2214
2215         /* If all Tx work done, exit the polling mode */
2216         if (work_done < budget) {
2217                 napi_complete(napi);
2218                 if (adapter->tx_itr_setting & 1)
2219                         ixgbe_set_itr_msix(q_vector);
2220                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2221                         ixgbe_irq_enable_queues(adapter,
2222                                                 ((u64)1 << q_vector->v_idx));
2223         }
2224
2225         return work_done;
2226 }
2227
2228 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2229                                      int r_idx)
2230 {
2231         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2232         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2233
2234         set_bit(r_idx, q_vector->rxr_idx);
2235         q_vector->rxr_count++;
2236         rx_ring->q_vector = q_vector;
2237 }
2238
2239 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2240                                      int t_idx)
2241 {
2242         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2243         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2244
2245         set_bit(t_idx, q_vector->txr_idx);
2246         q_vector->txr_count++;
2247         tx_ring->q_vector = q_vector;
2248 }
2249
2250 /**
2251  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2252  * @adapter: board private structure to initialize
2253  *
2254  * This function maps descriptor rings to the queue-specific vectors
2255  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2256  * one vector per ring/queue, but on a constrained vector budget, we
2257  * group the rings as "efficiently" as possible.  You would add new
2258  * mapping configurations in here.
2259  **/
2260 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2261 {
2262         int q_vectors;
2263         int v_start = 0;
2264         int rxr_idx = 0, txr_idx = 0;
2265         int rxr_remaining = adapter->num_rx_queues;
2266         int txr_remaining = adapter->num_tx_queues;
2267         int i, j;
2268         int rqpv, tqpv;
2269         int err = 0;
2270
2271         /* No mapping required if MSI-X is disabled. */
2272         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2273                 goto out;
2274
2275         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2276
2277         /*
2278          * The ideal configuration...
2279          * We have enough vectors to map one per queue.
2280          */
2281         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2282                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2283                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2284
2285                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2286                         map_vector_to_txq(adapter, v_start, txr_idx);
2287
2288                 goto out;
2289         }
2290
2291         /*
2292          * If we don't have enough vectors for a 1-to-1
2293          * mapping, we'll have to group them so there are
2294          * multiple queues per vector.
2295          */
2296         /* Re-adjusting *qpv takes care of the remainder. */
2297         for (i = v_start; i < q_vectors; i++) {
2298                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2299                 for (j = 0; j < rqpv; j++) {
2300                         map_vector_to_rxq(adapter, i, rxr_idx);
2301                         rxr_idx++;
2302                         rxr_remaining--;
2303                 }
2304                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2305                 for (j = 0; j < tqpv; j++) {
2306                         map_vector_to_txq(adapter, i, txr_idx);
2307                         txr_idx++;
2308                         txr_remaining--;
2309                 }
2310         }
2311 out:
2312         return err;
2313 }
2314
2315 /**
2316  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2317  * @adapter: board private structure
2318  *
2319  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2320  * interrupts from the kernel.
2321  **/
2322 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2323 {
2324         struct net_device *netdev = adapter->netdev;
2325         irqreturn_t (*handler)(int, void *);
2326         int i, vector, q_vectors, err;
2327         int ri = 0, ti = 0;
2328
2329         /* Decrement for Other and TCP Timer vectors */
2330         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2331
2332         err = ixgbe_map_rings_to_vectors(adapter);
2333         if (err)
2334                 return err;
2335
2336 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2337                                           ? &ixgbe_msix_clean_many : \
2338                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2339                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2340                           NULL)
2341         for (vector = 0; vector < q_vectors; vector++) {
2342                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2343                 handler = SET_HANDLER(q_vector);
2344
2345                 if (handler == &ixgbe_msix_clean_rx) {
2346                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2347                                  "%s-%s-%d", netdev->name, "rx", ri++);
2348                 } else if (handler == &ixgbe_msix_clean_tx) {
2349                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2350                                  "%s-%s-%d", netdev->name, "tx", ti++);
2351                 } else if (handler == &ixgbe_msix_clean_many) {
2352                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2353                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2354                         ti++;
2355                 } else {
2356                         /* skip this unused q_vector */
2357                         continue;
2358                 }
2359                 err = request_irq(adapter->msix_entries[vector].vector,
2360                                   handler, 0, q_vector->name,
2361                                   q_vector);
2362                 if (err) {
2363                         e_err(probe, "request_irq failed for MSIX interrupt "
2364                               "Error: %d\n", err);
2365                         goto free_queue_irqs;
2366                 }
2367         }
2368
2369         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2370         err = request_irq(adapter->msix_entries[vector].vector,
2371                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2372         if (err) {
2373                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2374                 goto free_queue_irqs;
2375         }
2376
2377         return 0;
2378
2379 free_queue_irqs:
2380         for (i = vector - 1; i >= 0; i--)
2381                 free_irq(adapter->msix_entries[--vector].vector,
2382                          adapter->q_vector[i]);
2383         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2384         pci_disable_msix(adapter->pdev);
2385         kfree(adapter->msix_entries);
2386         adapter->msix_entries = NULL;
2387         return err;
2388 }
2389
2390 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2391 {
2392         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2393         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2394         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2395         u32 new_itr = q_vector->eitr;
2396         u8 current_itr;
2397
2398         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2399                                             q_vector->tx_itr,
2400                                             tx_ring->total_packets,
2401                                             tx_ring->total_bytes);
2402         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2403                                             q_vector->rx_itr,
2404                                             rx_ring->total_packets,
2405                                             rx_ring->total_bytes);
2406
2407         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2408
2409         switch (current_itr) {
2410         /* counts and packets in update_itr are dependent on these numbers */
2411         case lowest_latency:
2412                 new_itr = 100000;
2413                 break;
2414         case low_latency:
2415                 new_itr = 20000; /* aka hwitr = ~200 */
2416                 break;
2417         case bulk_latency:
2418                 new_itr = 8000;
2419                 break;
2420         default:
2421                 break;
2422         }
2423
2424         if (new_itr != q_vector->eitr) {
2425                 /* do an exponential smoothing */
2426                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2427
2428                 /* save the algorithm value here */
2429                 q_vector->eitr = new_itr;
2430
2431                 ixgbe_write_eitr(q_vector);
2432         }
2433 }
2434
2435 /**
2436  * ixgbe_irq_enable - Enable default interrupt generation settings
2437  * @adapter: board private structure
2438  **/
2439 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2440                                     bool flush)
2441 {
2442         u32 mask;
2443
2444         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2445         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2446                 mask |= IXGBE_EIMS_GPI_SDP0;
2447         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2448                 mask |= IXGBE_EIMS_GPI_SDP1;
2449         switch (adapter->hw.mac.type) {
2450         case ixgbe_mac_82599EB:
2451         case ixgbe_mac_X540:
2452                 mask |= IXGBE_EIMS_ECC;
2453                 mask |= IXGBE_EIMS_GPI_SDP1;
2454                 mask |= IXGBE_EIMS_GPI_SDP2;
2455                 if (adapter->num_vfs)
2456                         mask |= IXGBE_EIMS_MAILBOX;
2457                 break;
2458         default:
2459                 break;
2460         }
2461         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2462             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2463                 mask |= IXGBE_EIMS_FLOW_DIR;
2464
2465         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2466         if (queues)
2467                 ixgbe_irq_enable_queues(adapter, ~0);
2468         if (flush)
2469                 IXGBE_WRITE_FLUSH(&adapter->hw);
2470
2471         if (adapter->num_vfs > 32) {
2472                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2473                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2474         }
2475 }
2476
2477 /**
2478  * ixgbe_intr - legacy mode Interrupt Handler
2479  * @irq: interrupt number
2480  * @data: pointer to a network interface device structure
2481  **/
2482 static irqreturn_t ixgbe_intr(int irq, void *data)
2483 {
2484         struct net_device *netdev = data;
2485         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2486         struct ixgbe_hw *hw = &adapter->hw;
2487         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2488         u32 eicr;
2489
2490         /*
2491          * Workaround for silicon errata on 82598.  Mask the interrupts
2492          * before the read of EICR.
2493          */
2494         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2495
2496         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2497          * therefore no explict interrupt disable is necessary */
2498         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2499         if (!eicr) {
2500                 /*
2501                  * shared interrupt alert!
2502                  * make sure interrupts are enabled because the read will
2503                  * have disabled interrupts due to EIAM
2504                  * finish the workaround of silicon errata on 82598.  Unmask
2505                  * the interrupt that we masked before the EICR read.
2506                  */
2507                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2508                         ixgbe_irq_enable(adapter, true, true);
2509                 return IRQ_NONE;        /* Not our interrupt */
2510         }
2511
2512         if (eicr & IXGBE_EICR_LSC)
2513                 ixgbe_check_lsc(adapter);
2514
2515         switch (hw->mac.type) {
2516         case ixgbe_mac_82599EB:
2517                 ixgbe_check_sfp_event(adapter, eicr);
2518                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2519                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2520                         adapter->interrupt_event = eicr;
2521                         schedule_work(&adapter->check_overtemp_task);
2522                 }
2523                 break;
2524         default:
2525                 break;
2526         }
2527
2528         ixgbe_check_fan_failure(adapter, eicr);
2529
2530         if (napi_schedule_prep(&(q_vector->napi))) {
2531                 adapter->tx_ring[0]->total_packets = 0;
2532                 adapter->tx_ring[0]->total_bytes = 0;
2533                 adapter->rx_ring[0]->total_packets = 0;
2534                 adapter->rx_ring[0]->total_bytes = 0;
2535                 /* would disable interrupts here but EIAM disabled it */
2536                 __napi_schedule(&(q_vector->napi));
2537         }
2538
2539         /*
2540          * re-enable link(maybe) and non-queue interrupts, no flush.
2541          * ixgbe_poll will re-enable the queue interrupts
2542          */
2543
2544         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2545                 ixgbe_irq_enable(adapter, false, false);
2546
2547         return IRQ_HANDLED;
2548 }
2549
2550 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2551 {
2552         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2553
2554         for (i = 0; i < q_vectors; i++) {
2555                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2556                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2557                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2558                 q_vector->rxr_count = 0;
2559                 q_vector->txr_count = 0;
2560         }
2561 }
2562
2563 /**
2564  * ixgbe_request_irq - initialize interrupts
2565  * @adapter: board private structure
2566  *
2567  * Attempts to configure interrupts using the best available
2568  * capabilities of the hardware and kernel.
2569  **/
2570 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2571 {
2572         struct net_device *netdev = adapter->netdev;
2573         int err;
2574
2575         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576                 err = ixgbe_request_msix_irqs(adapter);
2577         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2578                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2579                                   netdev->name, netdev);
2580         } else {
2581                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2582                                   netdev->name, netdev);
2583         }
2584
2585         if (err)
2586                 e_err(probe, "request_irq failed, Error %d\n", err);
2587
2588         return err;
2589 }
2590
2591 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2592 {
2593         struct net_device *netdev = adapter->netdev;
2594
2595         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2596                 int i, q_vectors;
2597
2598                 q_vectors = adapter->num_msix_vectors;
2599
2600                 i = q_vectors - 1;
2601                 free_irq(adapter->msix_entries[i].vector, netdev);
2602
2603                 i--;
2604                 for (; i >= 0; i--) {
2605                         /* free only the irqs that were actually requested */
2606                         if (!adapter->q_vector[i]->rxr_count &&
2607                             !adapter->q_vector[i]->txr_count)
2608                                 continue;
2609
2610                         free_irq(adapter->msix_entries[i].vector,
2611                                  adapter->q_vector[i]);
2612                 }
2613
2614                 ixgbe_reset_q_vectors(adapter);
2615         } else {
2616                 free_irq(adapter->pdev->irq, netdev);
2617         }
2618 }
2619
2620 /**
2621  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2622  * @adapter: board private structure
2623  **/
2624 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2625 {
2626         switch (adapter->hw.mac.type) {
2627         case ixgbe_mac_82598EB:
2628                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2629                 break;
2630         case ixgbe_mac_82599EB:
2631         case ixgbe_mac_X540:
2632                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2633                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2634                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2635                 if (adapter->num_vfs > 32)
2636                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2637                 break;
2638         default:
2639                 break;
2640         }
2641         IXGBE_WRITE_FLUSH(&adapter->hw);
2642         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2643                 int i;
2644                 for (i = 0; i < adapter->num_msix_vectors; i++)
2645                         synchronize_irq(adapter->msix_entries[i].vector);
2646         } else {
2647                 synchronize_irq(adapter->pdev->irq);
2648         }
2649 }
2650
2651 /**
2652  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2653  *
2654  **/
2655 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2656 {
2657         struct ixgbe_hw *hw = &adapter->hw;
2658
2659         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2660                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2661
2662         ixgbe_set_ivar(adapter, 0, 0, 0);
2663         ixgbe_set_ivar(adapter, 1, 0, 0);
2664
2665         map_vector_to_rxq(adapter, 0, 0);
2666         map_vector_to_txq(adapter, 0, 0);
2667
2668         e_info(hw, "Legacy interrupt IVAR setup done\n");
2669 }
2670
2671 /**
2672  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2673  * @adapter: board private structure
2674  * @ring: structure containing ring specific data
2675  *
2676  * Configure the Tx descriptor ring after a reset.
2677  **/
2678 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2679                              struct ixgbe_ring *ring)
2680 {
2681         struct ixgbe_hw *hw = &adapter->hw;
2682         u64 tdba = ring->dma;
2683         int wait_loop = 10;
2684         u32 txdctl;
2685         u8 reg_idx = ring->reg_idx;
2686
2687         /* disable queue to avoid issues while updating state */
2688         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2689         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2690                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2691         IXGBE_WRITE_FLUSH(hw);
2692
2693         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2694                         (tdba & DMA_BIT_MASK(32)));
2695         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2696         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2697                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2698         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2699         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2700         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2701
2702         /* configure fetching thresholds */
2703         if (adapter->rx_itr_setting == 0) {
2704                 /* cannot set wthresh when itr==0 */
2705                 txdctl &= ~0x007F0000;
2706         } else {
2707                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2708                 txdctl |= (8 << 16);
2709         }
2710         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2711                 /* PThresh workaround for Tx hang with DFP enabled. */
2712                 txdctl |= 32;
2713         }
2714
2715         /* reinitialize flowdirector state */
2716         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2717             adapter->atr_sample_rate) {
2718                 ring->atr_sample_rate = adapter->atr_sample_rate;
2719                 ring->atr_count = 0;
2720                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2721         } else {
2722                 ring->atr_sample_rate = 0;
2723         }
2724
2725         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2726
2727         /* enable queue */
2728         txdctl |= IXGBE_TXDCTL_ENABLE;
2729         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2730
2731         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2732         if (hw->mac.type == ixgbe_mac_82598EB &&
2733             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2734                 return;
2735
2736         /* poll to verify queue is enabled */
2737         do {
2738                 msleep(1);
2739                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2740         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2741         if (!wait_loop)
2742                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2743 }
2744
2745 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2746 {
2747         struct ixgbe_hw *hw = &adapter->hw;
2748         u32 rttdcs;
2749         u32 mask;
2750
2751         if (hw->mac.type == ixgbe_mac_82598EB)
2752                 return;
2753
2754         /* disable the arbiter while setting MTQC */
2755         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2756         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2757         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2758
2759         /* set transmit pool layout */
2760         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2761         switch (adapter->flags & mask) {
2762
2763         case (IXGBE_FLAG_SRIOV_ENABLED):
2764                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2765                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2766                 break;
2767
2768         case (IXGBE_FLAG_DCB_ENABLED):
2769                 /* We enable 8 traffic classes, DCB only */
2770                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2771                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2772                 break;
2773
2774         default:
2775                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2776                 break;
2777         }
2778
2779         /* re-enable the arbiter */
2780         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2781         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2782 }
2783
2784 /**
2785  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2786  * @adapter: board private structure
2787  *
2788  * Configure the Tx unit of the MAC after a reset.
2789  **/
2790 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2791 {
2792         struct ixgbe_hw *hw = &adapter->hw;
2793         u32 dmatxctl;
2794         u32 i;
2795
2796         ixgbe_setup_mtqc(adapter);
2797
2798         if (hw->mac.type != ixgbe_mac_82598EB) {
2799                 /* DMATXCTL.EN must be before Tx queues are enabled */
2800                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2801                 dmatxctl |= IXGBE_DMATXCTL_TE;
2802                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2803         }
2804
2805         /* Setup the HW Tx Head and Tail descriptor pointers */
2806         for (i = 0; i < adapter->num_tx_queues; i++)
2807                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2808 }
2809
2810 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2811
2812 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2813                                    struct ixgbe_ring *rx_ring)
2814 {
2815         u32 srrctl;
2816         u8 reg_idx = rx_ring->reg_idx;
2817
2818         switch (adapter->hw.mac.type) {
2819         case ixgbe_mac_82598EB: {
2820                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2821                 const int mask = feature[RING_F_RSS].mask;
2822                 reg_idx = reg_idx & mask;
2823         }
2824                 break;
2825         case ixgbe_mac_82599EB:
2826         case ixgbe_mac_X540:
2827         default:
2828                 break;
2829         }
2830
2831         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2832
2833         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2834         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2835         if (adapter->num_vfs)
2836                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2837
2838         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2839                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2840
2841         if (ring_is_ps_enabled(rx_ring)) {
2842 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2843                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2844 #else
2845                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2846 #endif
2847                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2848         } else {
2849                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2850                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2851                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2852         }
2853
2854         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2855 }
2856
2857 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2858 {
2859         struct ixgbe_hw *hw = &adapter->hw;
2860         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2861                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2862                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2863         u32 mrqc = 0, reta = 0;
2864         u32 rxcsum;
2865         int i, j;
2866         int mask;
2867
2868         /* Fill out hash function seeds */
2869         for (i = 0; i < 10; i++)
2870                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2871
2872         /* Fill out redirection table */
2873         for (i = 0, j = 0; i < 128; i++, j++) {
2874                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2875                         j = 0;
2876                 /* reta = 4-byte sliding window of
2877                  * 0x00..(indices-1)(indices-1)00..etc. */
2878                 reta = (reta << 8) | (j * 0x11);
2879                 if ((i & 3) == 3)
2880                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2881         }
2882
2883         /* Disable indicating checksum in descriptor, enables RSS hash */
2884         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2885         rxcsum |= IXGBE_RXCSUM_PCSD;
2886         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2887
2888         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2889                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2890         else
2891                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2892 #ifdef CONFIG_IXGBE_DCB
2893                                          | IXGBE_FLAG_DCB_ENABLED
2894 #endif
2895                                          | IXGBE_FLAG_SRIOV_ENABLED
2896                                         );
2897
2898         switch (mask) {
2899 #ifdef CONFIG_IXGBE_DCB
2900         case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2901                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2902                 break;
2903         case (IXGBE_FLAG_DCB_ENABLED):
2904                 mrqc = IXGBE_MRQC_RT8TCEN;
2905                 break;
2906 #endif /* CONFIG_IXGBE_DCB */
2907         case (IXGBE_FLAG_RSS_ENABLED):
2908                 mrqc = IXGBE_MRQC_RSSEN;
2909                 break;
2910         case (IXGBE_FLAG_SRIOV_ENABLED):
2911                 mrqc = IXGBE_MRQC_VMDQEN;
2912                 break;
2913         default:
2914                 break;
2915         }
2916
2917         /* Perform hash on these packet types */
2918         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2919               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2920               | IXGBE_MRQC_RSS_FIELD_IPV6
2921               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2922
2923         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2924 }
2925
2926 /**
2927  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2928  * @adapter: address of board private structure
2929  * @ring: structure containing ring specific data
2930  **/
2931 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2932                         struct ixgbe_ring *ring)
2933 {
2934         struct ixgbe_hw *hw = &adapter->hw;
2935         u32 rscctrl;
2936         u8 reg_idx = ring->reg_idx;
2937
2938         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2939         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2940         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2941 }
2942
2943 /**
2944  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2945  * @adapter:    address of board private structure
2946  * @index:      index of ring to set
2947  **/
2948 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2949                                    struct ixgbe_ring *ring)
2950 {
2951         struct ixgbe_hw *hw = &adapter->hw;
2952         u32 rscctrl;
2953         int rx_buf_len;
2954         u8 reg_idx = ring->reg_idx;
2955
2956         if (!ring_is_rsc_enabled(ring))
2957                 return;
2958
2959         rx_buf_len = ring->rx_buf_len;
2960         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2961         rscctrl |= IXGBE_RSCCTL_RSCEN;
2962         /*
2963          * we must limit the number of descriptors so that the
2964          * total size of max desc * buf_len is not greater
2965          * than 65535
2966          */
2967         if (ring_is_ps_enabled(ring)) {
2968 #if (MAX_SKB_FRAGS > 16)
2969                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2970 #elif (MAX_SKB_FRAGS > 8)
2971                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2972 #elif (MAX_SKB_FRAGS > 4)
2973                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2974 #else
2975                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2976 #endif
2977         } else {
2978                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2979                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2980                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2981                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2982                 else
2983                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2984         }
2985         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2986 }
2987
2988 /**
2989  *  ixgbe_set_uta - Set unicast filter table address
2990  *  @adapter: board private structure
2991  *
2992  *  The unicast table address is a register array of 32-bit registers.
2993  *  The table is meant to be used in a way similar to how the MTA is used
2994  *  however due to certain limitations in the hardware it is necessary to
2995  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2996  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2997  **/
2998 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2999 {
3000         struct ixgbe_hw *hw = &adapter->hw;
3001         int i;
3002
3003         /* The UTA table only exists on 82599 hardware and newer */
3004         if (hw->mac.type < ixgbe_mac_82599EB)
3005                 return;
3006
3007         /* we only need to do this if VMDq is enabled */
3008         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3009                 return;
3010
3011         for (i = 0; i < 128; i++)
3012                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3013 }
3014
3015 #define IXGBE_MAX_RX_DESC_POLL 10
3016 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3017                                        struct ixgbe_ring *ring)
3018 {
3019         struct ixgbe_hw *hw = &adapter->hw;
3020         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3021         u32 rxdctl;
3022         u8 reg_idx = ring->reg_idx;
3023
3024         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3025         if (hw->mac.type == ixgbe_mac_82598EB &&
3026             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3027                 return;
3028
3029         do {
3030                 msleep(1);
3031                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3032         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3033
3034         if (!wait_loop) {
3035                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3036                       "the polling period\n", reg_idx);
3037         }
3038 }
3039
3040 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3041                             struct ixgbe_ring *ring)
3042 {
3043         struct ixgbe_hw *hw = &adapter->hw;
3044         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3045         u32 rxdctl;
3046         u8 reg_idx = ring->reg_idx;
3047
3048         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3049         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3050
3051         /* write value back with RXDCTL.ENABLE bit cleared */
3052         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3053
3054         if (hw->mac.type == ixgbe_mac_82598EB &&
3055             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3056                 return;
3057
3058         /* the hardware may take up to 100us to really disable the rx queue */
3059         do {
3060                 udelay(10);
3061                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3062         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3063
3064         if (!wait_loop) {
3065                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3066                       "the polling period\n", reg_idx);
3067         }
3068 }
3069
3070 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3071                              struct ixgbe_ring *ring)
3072 {
3073         struct ixgbe_hw *hw = &adapter->hw;
3074         u64 rdba = ring->dma;
3075         u32 rxdctl;
3076         u8 reg_idx = ring->reg_idx;
3077
3078         /* disable queue to avoid issues while updating state */
3079         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3080         ixgbe_disable_rx_queue(adapter, ring);
3081
3082         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3083         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3084         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3085                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3086         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3087         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3088         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3089
3090         ixgbe_configure_srrctl(adapter, ring);
3091         ixgbe_configure_rscctl(adapter, ring);
3092
3093         /* If operating in IOV mode set RLPML for X540 */
3094         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3095             hw->mac.type == ixgbe_mac_X540) {
3096                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3097                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3098                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3099         }
3100
3101         if (hw->mac.type == ixgbe_mac_82598EB) {
3102                 /*
3103                  * enable cache line friendly hardware writes:
3104                  * PTHRESH=32 descriptors (half the internal cache),
3105                  * this also removes ugly rx_no_buffer_count increment
3106                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3107                  * WTHRESH=8 burst writeback up to two cache lines
3108                  */
3109                 rxdctl &= ~0x3FFFFF;
3110                 rxdctl |=  0x080420;
3111         }
3112
3113         /* enable receive descriptor ring */
3114         rxdctl |= IXGBE_RXDCTL_ENABLE;
3115         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3116
3117         ixgbe_rx_desc_queue_enable(adapter, ring);
3118         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3119 }
3120
3121 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3122 {
3123         struct ixgbe_hw *hw = &adapter->hw;
3124         int p;
3125
3126         /* PSRTYPE must be initialized in non 82598 adapters */
3127         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3128                       IXGBE_PSRTYPE_UDPHDR |
3129                       IXGBE_PSRTYPE_IPV4HDR |
3130                       IXGBE_PSRTYPE_L2HDR |
3131                       IXGBE_PSRTYPE_IPV6HDR;
3132
3133         if (hw->mac.type == ixgbe_mac_82598EB)
3134                 return;
3135
3136         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3137                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3138
3139         for (p = 0; p < adapter->num_rx_pools; p++)
3140                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3141                                 psrtype);
3142 }
3143
3144 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3145 {
3146         struct ixgbe_hw *hw = &adapter->hw;
3147         u32 gcr_ext;
3148         u32 vt_reg_bits;
3149         u32 reg_offset, vf_shift;
3150         u32 vmdctl;
3151
3152         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3153                 return;
3154
3155         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3156         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3157         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3158         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3159
3160         vf_shift = adapter->num_vfs % 32;
3161         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3162
3163         /* Enable only the PF's pool for Tx/Rx */
3164         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3165         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3166         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3167         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3168         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3169
3170         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3171         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3172
3173         /*
3174          * Set up VF register offsets for selected VT Mode,
3175          * i.e. 32 or 64 VFs for SR-IOV
3176          */
3177         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3178         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3179         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3180         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3181
3182         /* enable Tx loopback for VF/PF communication */
3183         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3184         /* Enable MAC Anti-Spoofing */
3185         hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
3186                                           adapter->num_vfs);
3187 }
3188
3189 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3190 {
3191         struct ixgbe_hw *hw = &adapter->hw;
3192         struct net_device *netdev = adapter->netdev;
3193         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3194         int rx_buf_len;
3195         struct ixgbe_ring *rx_ring;
3196         int i;
3197         u32 mhadd, hlreg0;
3198
3199         /* Decide whether to use packet split mode or not */
3200         /* On by default */
3201         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3202
3203         /* Do not use packet split if we're in SR-IOV Mode */
3204         if (adapter->num_vfs)
3205                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3206
3207         /* Disable packet split due to 82599 erratum #45 */
3208         if (hw->mac.type == ixgbe_mac_82599EB)
3209                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3210
3211         /* Set the RX buffer length according to the mode */
3212         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3213                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3214         } else {
3215                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3216                     (netdev->mtu <= ETH_DATA_LEN))
3217                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3218                 else
3219                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3220         }
3221
3222 #ifdef IXGBE_FCOE
3223         /* adjust max frame to be able to do baby jumbo for FCoE */
3224         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3225             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3226                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3227
3228 #endif /* IXGBE_FCOE */
3229         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3230         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3231                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3232                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3233
3234                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3235         }
3236
3237         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3238         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3239         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3240         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3241
3242         /*
3243          * Setup the HW Rx Head and Tail Descriptor Pointers and
3244          * the Base and Length of the Rx Descriptor Ring
3245          */
3246         for (i = 0; i < adapter->num_rx_queues; i++) {
3247                 rx_ring = adapter->rx_ring[i];
3248                 rx_ring->rx_buf_len = rx_buf_len;
3249
3250                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3251                         set_ring_ps_enabled(rx_ring);
3252                 else
3253                         clear_ring_ps_enabled(rx_ring);
3254
3255                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3256                         set_ring_rsc_enabled(rx_ring);
3257                 else
3258                         clear_ring_rsc_enabled(rx_ring);
3259
3260 #ifdef IXGBE_FCOE
3261                 if (netdev->features & NETIF_F_FCOE_MTU) {
3262                         struct ixgbe_ring_feature *f;
3263                         f = &adapter->ring_feature[RING_F_FCOE];
3264                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3265                                 clear_ring_ps_enabled(rx_ring);
3266                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3267                                         rx_ring->rx_buf_len =
3268                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3269                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3270                                    !ring_is_ps_enabled(rx_ring)) {
3271                                 rx_ring->rx_buf_len =
3272                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3273                         }
3274                 }
3275 #endif /* IXGBE_FCOE */
3276         }
3277 }
3278
3279 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3280 {
3281         struct ixgbe_hw *hw = &adapter->hw;
3282         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3283
3284         switch (hw->mac.type) {
3285         case ixgbe_mac_82598EB:
3286                 /*
3287                  * For VMDq support of different descriptor types or
3288                  * buffer sizes through the use of multiple SRRCTL
3289                  * registers, RDRXCTL.MVMEN must be set to 1
3290                  *
3291                  * also, the manual doesn't mention it clearly but DCA hints
3292                  * will only use queue 0's tags unless this bit is set.  Side
3293                  * effects of setting this bit are only that SRRCTL must be
3294                  * fully programmed [0..15]
3295                  */
3296                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3297                 break;
3298         case ixgbe_mac_82599EB:
3299         case ixgbe_mac_X540:
3300                 /* Disable RSC for ACK packets */
3301                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3302                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3303                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3304                 /* hardware requires some bits to be set by default */
3305                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3306                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3307                 break;
3308         default:
3309                 /* We should do nothing since we don't know this hardware */
3310                 return;
3311         }
3312
3313         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3314 }
3315
3316 /**
3317  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3318  * @adapter: board private structure
3319  *
3320  * Configure the Rx unit of the MAC after a reset.
3321  **/
3322 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3323 {
3324         struct ixgbe_hw *hw = &adapter->hw;
3325         int i;
3326         u32 rxctrl;
3327
3328         /* disable receives while setting up the descriptors */
3329         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3330         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3331
3332         ixgbe_setup_psrtype(adapter);
3333         ixgbe_setup_rdrxctl(adapter);
3334
3335         /* Program registers for the distribution of queues */
3336         ixgbe_setup_mrqc(adapter);
3337
3338         ixgbe_set_uta(adapter);
3339
3340         /* set_rx_buffer_len must be called before ring initialization */
3341         ixgbe_set_rx_buffer_len(adapter);
3342
3343         /*
3344          * Setup the HW Rx Head and Tail Descriptor Pointers and
3345          * the Base and Length of the Rx Descriptor Ring
3346          */
3347         for (i = 0; i < adapter->num_rx_queues; i++)
3348                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3349
3350         /* disable drop enable for 82598 parts */
3351         if (hw->mac.type == ixgbe_mac_82598EB)
3352                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3353
3354         /* enable all receives */
3355         rxctrl |= IXGBE_RXCTRL_RXEN;
3356         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3357 }
3358
3359 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3360 {
3361         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3362         struct ixgbe_hw *hw = &adapter->hw;
3363         int pool_ndx = adapter->num_vfs;
3364
3365         /* add VID to filter table */
3366         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3367         set_bit(vid, adapter->active_vlans);
3368 }
3369
3370 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3371 {
3372         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3373         struct ixgbe_hw *hw = &adapter->hw;
3374         int pool_ndx = adapter->num_vfs;
3375
3376         /* remove VID from filter table */
3377         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3378         clear_bit(vid, adapter->active_vlans);
3379 }
3380
3381 /**
3382  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3383  * @adapter: driver data
3384  */
3385 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3386 {
3387         struct ixgbe_hw *hw = &adapter->hw;
3388         u32 vlnctrl;
3389
3390         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3391         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3392         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3393 }
3394
3395 /**
3396  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3397  * @adapter: driver data
3398  */
3399 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3400 {
3401         struct ixgbe_hw *hw = &adapter->hw;
3402         u32 vlnctrl;
3403
3404         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3405         vlnctrl |= IXGBE_VLNCTRL_VFE;
3406         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3407         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3408 }
3409
3410 /**
3411  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3412  * @adapter: driver data
3413  */
3414 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3415 {
3416         struct ixgbe_hw *hw = &adapter->hw;
3417         u32 vlnctrl;
3418         int i, j;
3419
3420         switch (hw->mac.type) {
3421         case ixgbe_mac_82598EB:
3422                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3423                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3424                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3425                 break;
3426         case ixgbe_mac_82599EB:
3427         case ixgbe_mac_X540:
3428                 for (i = 0; i < adapter->num_rx_queues; i++) {
3429                         j = adapter->rx_ring[i]->reg_idx;
3430                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3431                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3432                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3433                 }
3434                 break;
3435         default:
3436                 break;
3437         }
3438 }
3439
3440 /**
3441  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3442  * @adapter: driver data
3443  */
3444 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3445 {
3446         struct ixgbe_hw *hw = &adapter->hw;
3447         u32 vlnctrl;
3448         int i, j;
3449
3450         switch (hw->mac.type) {
3451         case ixgbe_mac_82598EB:
3452                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3453                 vlnctrl |= IXGBE_VLNCTRL_VME;
3454                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3455                 break;
3456         case ixgbe_mac_82599EB:
3457         case ixgbe_mac_X540:
3458                 for (i = 0; i < adapter->num_rx_queues; i++) {
3459                         j = adapter->rx_ring[i]->reg_idx;
3460                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3461                         vlnctrl |= IXGBE_RXDCTL_VME;
3462                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3463                 }
3464                 break;
3465         default:
3466                 break;
3467         }
3468 }
3469
3470 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3471 {
3472         u16 vid;
3473
3474         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3475
3476         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3477                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3478 }
3479
3480 /**
3481  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3482  * @netdev: network interface device structure
3483  *
3484  * Writes unicast address list to the RAR table.
3485  * Returns: -ENOMEM on failure/insufficient address space
3486  *                0 on no addresses written
3487  *                X on writing X addresses to the RAR table
3488  **/
3489 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3490 {
3491         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3492         struct ixgbe_hw *hw = &adapter->hw;
3493         unsigned int vfn = adapter->num_vfs;
3494         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3495         int count = 0;
3496
3497         /* return ENOMEM indicating insufficient memory for addresses */
3498         if (netdev_uc_count(netdev) > rar_entries)
3499                 return -ENOMEM;
3500
3501         if (!netdev_uc_empty(netdev) && rar_entries) {
3502                 struct netdev_hw_addr *ha;
3503                 /* return error if we do not support writing to RAR table */
3504                 if (!hw->mac.ops.set_rar)
3505                         return -ENOMEM;
3506
3507                 netdev_for_each_uc_addr(ha, netdev) {
3508                         if (!rar_entries)
3509                                 break;
3510                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3511                                             vfn, IXGBE_RAH_AV);
3512                         count++;
3513                 }
3514         }
3515         /* write the addresses in reverse order to avoid write combining */
3516         for (; rar_entries > 0 ; rar_entries--)
3517                 hw->mac.ops.clear_rar(hw, rar_entries);
3518
3519         return count;
3520 }
3521
3522 /**
3523  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3524  * @netdev: network interface device structure
3525  *
3526  * The set_rx_method entry point is called whenever the unicast/multicast
3527  * address list or the network interface flags are updated.  This routine is
3528  * responsible for configuring the hardware for proper unicast, multicast and
3529  * promiscuous mode.
3530  **/
3531 void ixgbe_set_rx_mode(struct net_device *netdev)
3532 {
3533         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3534         struct ixgbe_hw *hw = &adapter->hw;
3535         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3536         int count;
3537
3538         /* Check for Promiscuous and All Multicast modes */
3539
3540         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3541
3542         /* set all bits that we expect to always be set */
3543         fctrl |= IXGBE_FCTRL_BAM;
3544         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3545         fctrl |= IXGBE_FCTRL_PMCF;
3546
3547         /* clear the bits we are changing the status of */
3548         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3549
3550         if (netdev->flags & IFF_PROMISC) {
3551                 hw->addr_ctrl.user_set_promisc = true;
3552                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3553                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3554                 /* don't hardware filter vlans in promisc mode */
3555                 ixgbe_vlan_filter_disable(adapter);
3556         } else {
3557                 if (netdev->flags & IFF_ALLMULTI) {
3558                         fctrl |= IXGBE_FCTRL_MPE;
3559                         vmolr |= IXGBE_VMOLR_MPE;
3560                 } else {
3561                         /*
3562                          * Write addresses to the MTA, if the attempt fails
3563                          * then we should just turn on promiscuous mode so
3564                          * that we can at least receive multicast traffic
3565                          */
3566                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3567                         vmolr |= IXGBE_VMOLR_ROMPE;
3568                 }
3569                 ixgbe_vlan_filter_enable(adapter);
3570                 hw->addr_ctrl.user_set_promisc = false;
3571                 /*
3572                  * Write addresses to available RAR registers, if there is not
3573                  * sufficient space to store all the addresses then enable
3574                  * unicast promiscuous mode
3575                  */
3576                 count = ixgbe_write_uc_addr_list(netdev);
3577                 if (count < 0) {
3578                         fctrl |= IXGBE_FCTRL_UPE;
3579                         vmolr |= IXGBE_VMOLR_ROPE;
3580                 }
3581         }
3582
3583         if (adapter->num_vfs) {
3584                 ixgbe_restore_vf_multicasts(adapter);
3585                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3586                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3587                            IXGBE_VMOLR_ROPE);
3588                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3589         }
3590
3591         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3592
3593         if (netdev->features & NETIF_F_HW_VLAN_RX)
3594                 ixgbe_vlan_strip_enable(adapter);
3595         else
3596                 ixgbe_vlan_strip_disable(adapter);
3597 }
3598
3599 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3600 {
3601         int q_idx;
3602         struct ixgbe_q_vector *q_vector;
3603         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3604
3605         /* legacy and MSI only use one vector */
3606         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3607                 q_vectors = 1;
3608
3609         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3610                 struct napi_struct *napi;
3611                 q_vector = adapter->q_vector[q_idx];
3612                 napi = &q_vector->napi;
3613                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3614                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3615                                 if (q_vector->txr_count == 1)
3616                                         napi->poll = &ixgbe_clean_txonly;
3617                                 else if (q_vector->rxr_count == 1)
3618                                         napi->poll = &ixgbe_clean_rxonly;
3619                         }
3620                 }
3621
3622                 napi_enable(napi);
3623         }
3624 }
3625
3626 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3627 {
3628         int q_idx;
3629         struct ixgbe_q_vector *q_vector;
3630         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3631
3632         /* legacy and MSI only use one vector */
3633         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3634                 q_vectors = 1;
3635
3636         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3637                 q_vector = adapter->q_vector[q_idx];
3638                 napi_disable(&q_vector->napi);
3639         }
3640 }
3641
3642 #ifdef CONFIG_IXGBE_DCB
3643 /*
3644  * ixgbe_configure_dcb - Configure DCB hardware
3645  * @adapter: ixgbe adapter struct
3646  *
3647  * This is called by the driver on open to configure the DCB hardware.
3648  * This is also called by the gennetlink interface when reconfiguring
3649  * the DCB state.
3650  */
3651 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3652 {
3653         struct ixgbe_hw *hw = &adapter->hw;
3654         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3655
3656         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3657                 if (hw->mac.type == ixgbe_mac_82598EB)
3658                         netif_set_gso_max_size(adapter->netdev, 65536);
3659                 return;
3660         }
3661
3662         if (hw->mac.type == ixgbe_mac_82598EB)
3663                 netif_set_gso_max_size(adapter->netdev, 32768);
3664
3665
3666         /* Enable VLAN tag insert/strip */
3667         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3668
3669         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3670
3671         /* reconfigure the hardware */
3672         if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3673 #ifdef CONFIG_FCOE
3674                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3675                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3676 #endif
3677                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3678                                                 DCB_TX_CONFIG);
3679                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3680                                                 DCB_RX_CONFIG);
3681                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3682         } else {
3683                 struct net_device *dev = adapter->netdev;
3684
3685                 if (adapter->ixgbe_ieee_ets)
3686                         dev->dcbnl_ops->ieee_setets(dev,
3687                                                     adapter->ixgbe_ieee_ets);
3688                 if (adapter->ixgbe_ieee_pfc)
3689                         dev->dcbnl_ops->ieee_setpfc(dev,
3690                                                     adapter->ixgbe_ieee_pfc);
3691         }
3692
3693         /* Enable RSS Hash per TC */
3694         if (hw->mac.type != ixgbe_mac_82598EB) {
3695                 int i;
3696                 u32 reg = 0;
3697
3698                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3699                         u8 msb = 0;
3700                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3701
3702                         while (cnt >>= 1)
3703                                 msb++;
3704
3705                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3706                 }
3707                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3708         }
3709 }
3710
3711 #endif
3712 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3713 {
3714         struct net_device *netdev = adapter->netdev;
3715         struct ixgbe_hw *hw = &adapter->hw;
3716         int i;
3717
3718 #ifdef CONFIG_IXGBE_DCB
3719         ixgbe_configure_dcb(adapter);
3720 #endif
3721
3722         ixgbe_set_rx_mode(netdev);
3723         ixgbe_restore_vlan(adapter);
3724
3725 #ifdef IXGBE_FCOE
3726         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3727                 ixgbe_configure_fcoe(adapter);
3728
3729 #endif /* IXGBE_FCOE */
3730         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3731                 for (i = 0; i < adapter->num_tx_queues; i++)
3732                         adapter->tx_ring[i]->atr_sample_rate =
3733                                                        adapter->atr_sample_rate;
3734                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3735         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3736                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3737         }
3738         ixgbe_configure_virtualization(adapter);
3739
3740         ixgbe_configure_tx(adapter);
3741         ixgbe_configure_rx(adapter);
3742 }
3743
3744 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3745 {
3746         switch (hw->phy.type) {
3747         case ixgbe_phy_sfp_avago:
3748         case ixgbe_phy_sfp_ftl:
3749         case ixgbe_phy_sfp_intel:
3750         case ixgbe_phy_sfp_unknown:
3751         case ixgbe_phy_sfp_passive_tyco:
3752         case ixgbe_phy_sfp_passive_unknown:
3753         case ixgbe_phy_sfp_active_unknown:
3754         case ixgbe_phy_sfp_ftl_active:
3755                 return true;
3756         default:
3757                 return false;
3758         }
3759 }
3760
3761 /**
3762  * ixgbe_sfp_link_config - set up SFP+ link
3763  * @adapter: pointer to private adapter struct
3764  **/
3765 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3766 {
3767         struct ixgbe_hw *hw = &adapter->hw;
3768
3769                 if (hw->phy.multispeed_fiber) {
3770                         /*
3771                          * In multispeed fiber setups, the device may not have
3772                          * had a physical connection when the driver loaded.
3773                          * If that's the case, the initial link configuration
3774                          * couldn't get the MAC into 10G or 1G mode, so we'll
3775                          * never have a link status change interrupt fire.
3776                          * We need to try and force an autonegotiation
3777                          * session, then bring up link.
3778                          */
3779                         if (hw->mac.ops.setup_sfp)
3780                                 hw->mac.ops.setup_sfp(hw);
3781                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3782                                 schedule_work(&adapter->multispeed_fiber_task);
3783                 } else {
3784                         /*
3785                          * Direct Attach Cu and non-multispeed fiber modules
3786                          * still need to be configured properly prior to
3787                          * attempting link.
3788                          */
3789                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3790                                 schedule_work(&adapter->sfp_config_module_task);
3791                 }
3792 }
3793
3794 /**
3795  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3796  * @hw: pointer to private hardware struct
3797  *
3798  * Returns 0 on success, negative on failure
3799  **/
3800 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3801 {
3802         u32 autoneg;
3803         bool negotiation, link_up = false;
3804         u32 ret = IXGBE_ERR_LINK_SETUP;
3805
3806         if (hw->mac.ops.check_link)
3807                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3808
3809         if (ret)
3810                 goto link_cfg_out;
3811
3812         autoneg = hw->phy.autoneg_advertised;
3813         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3814                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3815                                                         &negotiation);
3816         if (ret)
3817                 goto link_cfg_out;
3818
3819         if (hw->mac.ops.setup_link)
3820                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3821 link_cfg_out:
3822         return ret;
3823 }
3824
3825 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3826 {
3827         struct ixgbe_hw *hw = &adapter->hw;
3828         u32 gpie = 0;
3829
3830         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3831                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3832                        IXGBE_GPIE_OCD;
3833                 gpie |= IXGBE_GPIE_EIAME;
3834                 /*
3835                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3836                  * this saves a register write for every interrupt
3837                  */
3838                 switch (hw->mac.type) {
3839                 case ixgbe_mac_82598EB:
3840                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3841                         break;
3842                 case ixgbe_mac_82599EB:
3843                 case ixgbe_mac_X540:
3844                 default:
3845                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3846                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3847                         break;
3848                 }
3849         } else {
3850                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3851                  * specifically only auto mask tx and rx interrupts */
3852                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3853         }
3854
3855         /* XXX: to interrupt immediately for EICS writes, enable this */
3856         /* gpie |= IXGBE_GPIE_EIMEN; */
3857
3858         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3859                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3860                 gpie |= IXGBE_GPIE_VTMODE_64;
3861         }
3862
3863         /* Enable fan failure interrupt */
3864         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3865                 gpie |= IXGBE_SDP1_GPIEN;
3866
3867         if (hw->mac.type == ixgbe_mac_82599EB)
3868                 gpie |= IXGBE_SDP1_GPIEN;
3869                 gpie |= IXGBE_SDP2_GPIEN;
3870
3871         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3872 }
3873
3874 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3875 {
3876         struct ixgbe_hw *hw = &adapter->hw;
3877         int err;
3878         u32 ctrl_ext;
3879
3880         ixgbe_get_hw_control(adapter);
3881         ixgbe_setup_gpie(adapter);
3882
3883         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3884                 ixgbe_configure_msix(adapter);
3885         else
3886                 ixgbe_configure_msi_and_legacy(adapter);
3887
3888         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3889         if (hw->mac.ops.enable_tx_laser &&
3890             ((hw->phy.multispeed_fiber) ||
3891              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3892               (hw->mac.type == ixgbe_mac_82599EB))))
3893                 hw->mac.ops.enable_tx_laser(hw);
3894
3895         clear_bit(__IXGBE_DOWN, &adapter->state);
3896         ixgbe_napi_enable_all(adapter);
3897
3898         if (ixgbe_is_sfp(hw)) {
3899                 ixgbe_sfp_link_config(adapter);
3900         } else {
3901                 err = ixgbe_non_sfp_link_config(hw);
3902                 if (err)
3903                         e_err(probe, "link_config FAILED %d\n", err);
3904         }
3905
3906         /* clear any pending interrupts, may auto mask */
3907         IXGBE_READ_REG(hw, IXGBE_EICR);
3908         ixgbe_irq_enable(adapter, true, true);
3909
3910         /*
3911          * If this adapter has a fan, check to see if we had a failure
3912          * before we enabled the interrupt.
3913          */
3914         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3915                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3916                 if (esdp & IXGBE_ESDP_SDP1)
3917                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3918         }
3919
3920         /*
3921          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3922          * arrived before interrupts were enabled but after probe.  Such
3923          * devices wouldn't have their type identified yet. We need to
3924          * kick off the SFP+ module setup first, then try to bring up link.
3925          * If we're not hot-pluggable SFP+, we just need to configure link
3926          * and bring it up.
3927          */
3928         if (hw->phy.type == ixgbe_phy_none)
3929                 schedule_work(&adapter->sfp_config_module_task);
3930
3931         /* enable transmits */
3932         netif_tx_start_all_queues(adapter->netdev);
3933
3934         /* bring the link up in the watchdog, this could race with our first
3935          * link up interrupt but shouldn't be a problem */
3936         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3937         adapter->link_check_timeout = jiffies;
3938         mod_timer(&adapter->watchdog_timer, jiffies);
3939
3940         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3941         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3942         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3943         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3944
3945         return 0;
3946 }
3947
3948 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3949 {
3950         WARN_ON(in_interrupt());
3951         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3952                 msleep(1);
3953         ixgbe_down(adapter);
3954         /*
3955          * If SR-IOV enabled then wait a bit before bringing the adapter
3956          * back up to give the VFs time to respond to the reset.  The
3957          * two second wait is based upon the watchdog timer cycle in
3958          * the VF driver.
3959          */
3960         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3961                 msleep(2000);
3962         ixgbe_up(adapter);
3963         clear_bit(__IXGBE_RESETTING, &adapter->state);
3964 }
3965
3966 int ixgbe_up(struct ixgbe_adapter *adapter)
3967 {
3968         /* hardware has been reset, we need to reload some things */
3969         ixgbe_configure(adapter);
3970
3971         return ixgbe_up_complete(adapter);
3972 }
3973
3974 void ixgbe_reset(struct ixgbe_adapter *adapter)
3975 {
3976         struct ixgbe_hw *hw = &adapter->hw;
3977         int err;
3978
3979         err = hw->mac.ops.init_hw(hw);
3980         switch (err) {
3981         case 0:
3982         case IXGBE_ERR_SFP_NOT_PRESENT:
3983                 break;
3984         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3985                 e_dev_err("master disable timed out\n");
3986                 break;
3987         case IXGBE_ERR_EEPROM_VERSION:
3988                 /* We are running on a pre-production device, log a warning */
3989                 e_dev_warn("This device is a pre-production adapter/LOM. "
3990                            "Please be aware there may be issuesassociated with "
3991                            "your hardware.  If you are experiencing problems "
3992                            "please contact your Intel or hardware "
3993                            "representative who provided you with this "
3994                            "hardware.\n");
3995                 break;
3996         default:
3997                 e_dev_err("Hardware Error: %d\n", err);
3998         }
3999
4000         /* reprogram the RAR[0] in case user changed it. */
4001         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4002                             IXGBE_RAH_AV);
4003 }
4004
4005 /**
4006  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4007  * @rx_ring: ring to free buffers from
4008  **/
4009 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4010 {
4011         struct device *dev = rx_ring->dev;
4012         unsigned long size;
4013         u16 i;
4014
4015         /* ring already cleared, nothing to do */
4016         if (!rx_ring->rx_buffer_info)
4017                 return;
4018
4019         /* Free all the Rx ring sk_buffs */
4020         for (i = 0; i < rx_ring->count; i++) {
4021                 struct ixgbe_rx_buffer *rx_buffer_info;
4022
4023                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4024                 if (rx_buffer_info->dma) {
4025                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4026                                          rx_ring->rx_buf_len,
4027                                          DMA_FROM_DEVICE);
4028                         rx_buffer_info->dma = 0;
4029                 }
4030                 if (rx_buffer_info->skb) {
4031                         struct sk_buff *skb = rx_buffer_info->skb;
4032                         rx_buffer_info->skb = NULL;
4033                         do {
4034                                 struct sk_buff *this = skb;
4035                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4036                                         dma_unmap_single(dev,
4037                                                          IXGBE_RSC_CB(this)->dma,
4038                                                          rx_ring->rx_buf_len,
4039                                                          DMA_FROM_DEVICE);
4040                                         IXGBE_RSC_CB(this)->dma = 0;
4041                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4042                                 }
4043                                 skb = skb->prev;
4044                                 dev_kfree_skb(this);
4045                         } while (skb);
4046                 }
4047                 if (!rx_buffer_info->page)
4048                         continue;
4049                 if (rx_buffer_info->page_dma) {
4050                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4051                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4052                         rx_buffer_info->page_dma = 0;
4053                 }
4054                 put_page(rx_buffer_info->page);
4055                 rx_buffer_info->page = NULL;
4056                 rx_buffer_info->page_offset = 0;
4057         }
4058
4059         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4060         memset(rx_ring->rx_buffer_info, 0, size);
4061
4062         /* Zero out the descriptor ring */
4063         memset(rx_ring->desc, 0, rx_ring->size);
4064
4065         rx_ring->next_to_clean = 0;
4066         rx_ring->next_to_use = 0;
4067 }
4068
4069 /**
4070  * ixgbe_clean_tx_ring - Free Tx Buffers
4071  * @tx_ring: ring to be cleaned
4072  **/
4073 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4074 {
4075         struct ixgbe_tx_buffer *tx_buffer_info;
4076         unsigned long size;
4077         u16 i;
4078
4079         /* ring already cleared, nothing to do */
4080         if (!tx_ring->tx_buffer_info)
4081                 return;
4082
4083         /* Free all the Tx ring sk_buffs */
4084         for (i = 0; i < tx_ring->count; i++) {
4085                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4086                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4087         }
4088
4089         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4090         memset(tx_ring->tx_buffer_info, 0, size);
4091
4092         /* Zero out the descriptor ring */
4093         memset(tx_ring->desc, 0, tx_ring->size);
4094
4095         tx_ring->next_to_use = 0;
4096         tx_ring->next_to_clean = 0;
4097 }
4098
4099 /**
4100  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4101  * @adapter: board private structure
4102  **/
4103 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4104 {
4105         int i;
4106
4107         for (i = 0; i < adapter->num_rx_queues; i++)
4108                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4109 }
4110
4111 /**
4112  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4113  * @adapter: board private structure
4114  **/
4115 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4116 {
4117         int i;
4118
4119         for (i = 0; i < adapter->num_tx_queues; i++)
4120                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4121 }
4122
4123 void ixgbe_down(struct ixgbe_adapter *adapter)
4124 {
4125         struct net_device *netdev = adapter->netdev;
4126         struct ixgbe_hw *hw = &adapter->hw;
4127         u32 rxctrl;
4128         u32 txdctl;
4129         int i;
4130         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4131
4132         /* signal that we are down to the interrupt handler */
4133         set_bit(__IXGBE_DOWN, &adapter->state);
4134
4135         /* disable receive for all VFs and wait one second */
4136         if (adapter->num_vfs) {
4137                 /* ping all the active vfs to let them know we are going down */
4138                 ixgbe_ping_all_vfs(adapter);
4139
4140                 /* Disable all VFTE/VFRE TX/RX */
4141                 ixgbe_disable_tx_rx(adapter);
4142
4143                 /* Mark all the VFs as inactive */
4144                 for (i = 0 ; i < adapter->num_vfs; i++)
4145                         adapter->vfinfo[i].clear_to_send = 0;
4146         }
4147
4148         /* disable receives */
4149         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4150         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4151
4152         /* disable all enabled rx queues */
4153         for (i = 0; i < adapter->num_rx_queues; i++)
4154                 /* this call also flushes the previous write */
4155                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4156
4157         msleep(10);
4158
4159         netif_tx_stop_all_queues(netdev);
4160
4161         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4162         del_timer_sync(&adapter->sfp_timer);
4163         del_timer_sync(&adapter->watchdog_timer);
4164         cancel_work_sync(&adapter->watchdog_task);
4165
4166         netif_carrier_off(netdev);
4167         netif_tx_disable(netdev);
4168
4169         ixgbe_irq_disable(adapter);
4170
4171         ixgbe_napi_disable_all(adapter);
4172
4173         /* Cleanup the affinity_hint CPU mask memory and callback */
4174         for (i = 0; i < num_q_vectors; i++) {
4175                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4176                 /* clear the affinity_mask in the IRQ descriptor */
4177                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4178                 /* release the CPU mask memory */
4179                 free_cpumask_var(q_vector->affinity_mask);
4180         }
4181
4182         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4183             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4184                 cancel_work_sync(&adapter->fdir_reinit_task);
4185
4186         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4187                 cancel_work_sync(&adapter->check_overtemp_task);
4188
4189         /* disable transmits in the hardware now that interrupts are off */
4190         for (i = 0; i < adapter->num_tx_queues; i++) {
4191                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4192                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4193                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4194                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4195         }
4196         /* Disable the Tx DMA engine on 82599 */
4197         switch (hw->mac.type) {
4198         case ixgbe_mac_82599EB:
4199         case ixgbe_mac_X540:
4200                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4201                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4202                                  ~IXGBE_DMATXCTL_TE));
4203                 break;
4204         default:
4205                 break;
4206         }
4207
4208         /* clear n-tuple filters that are cached */
4209         ethtool_ntuple_flush(netdev);
4210
4211         if (!pci_channel_offline(adapter->pdev))
4212                 ixgbe_reset(adapter);
4213
4214         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4215         if (hw->mac.ops.disable_tx_laser &&
4216             ((hw->phy.multispeed_fiber) ||
4217              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4218               (hw->mac.type == ixgbe_mac_82599EB))))
4219                 hw->mac.ops.disable_tx_laser(hw);
4220
4221         ixgbe_clean_all_tx_rings(adapter);
4222         ixgbe_clean_all_rx_rings(adapter);
4223
4224 #ifdef CONFIG_IXGBE_DCA
4225         /* since we reset the hardware DCA settings were cleared */
4226         ixgbe_setup_dca(adapter);
4227 #endif
4228 }
4229
4230 /**
4231  * ixgbe_poll - NAPI Rx polling callback
4232  * @napi: structure for representing this polling device
4233  * @budget: how many packets driver is allowed to clean
4234  *
4235  * This function is used for legacy and MSI, NAPI mode
4236  **/
4237 static int ixgbe_poll(struct napi_struct *napi, int budget)
4238 {
4239         struct ixgbe_q_vector *q_vector =
4240                                 container_of(napi, struct ixgbe_q_vector, napi);
4241         struct ixgbe_adapter *adapter = q_vector->adapter;
4242         int tx_clean_complete, work_done = 0;
4243
4244 #ifdef CONFIG_IXGBE_DCA
4245         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4246                 ixgbe_update_dca(q_vector);
4247 #endif
4248
4249         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4250         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4251
4252         if (!tx_clean_complete)
4253                 work_done = budget;
4254
4255         /* If budget not fully consumed, exit the polling mode */
4256         if (work_done < budget) {
4257                 napi_complete(napi);
4258                 if (adapter->rx_itr_setting & 1)
4259                         ixgbe_set_itr(adapter);
4260                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4261                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4262         }
4263         return work_done;
4264 }
4265
4266 /**
4267  * ixgbe_tx_timeout - Respond to a Tx Hang
4268  * @netdev: network interface device structure
4269  **/
4270 static void ixgbe_tx_timeout(struct net_device *netdev)
4271 {
4272         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4273
4274         adapter->tx_timeout_count++;
4275
4276         /* Do the reset outside of interrupt context */
4277         schedule_work(&adapter->reset_task);
4278 }
4279
4280 static void ixgbe_reset_task(struct work_struct *work)
4281 {
4282         struct ixgbe_adapter *adapter;
4283         adapter = container_of(work, struct ixgbe_adapter, reset_task);
4284
4285         /* If we're already down or resetting, just bail */
4286         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4287             test_bit(__IXGBE_RESETTING, &adapter->state))
4288                 return;
4289
4290         ixgbe_dump(adapter);
4291         netdev_err(adapter->netdev, "Reset adapter\n");
4292         ixgbe_reinit_locked(adapter);
4293 }
4294
4295 /**
4296  * ixgbe_set_rss_queues: Allocate queues for RSS
4297  * @adapter: board private structure to initialize
4298  *
4299  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4300  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4301  *
4302  **/
4303 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4304 {
4305         bool ret = false;
4306         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4307
4308         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4309                 f->mask = 0xF;
4310                 adapter->num_rx_queues = f->indices;
4311                 adapter->num_tx_queues = f->indices;
4312                 ret = true;
4313         } else {
4314                 ret = false;
4315         }
4316
4317         return ret;
4318 }
4319
4320 /**
4321  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4322  * @adapter: board private structure to initialize
4323  *
4324  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4325  * to the original CPU that initiated the Tx session.  This runs in addition
4326  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4327  * Rx load across CPUs using RSS.
4328  *
4329  **/
4330 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4331 {
4332         bool ret = false;
4333         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4334
4335         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4336         f_fdir->mask = 0;
4337
4338         /* Flow Director must have RSS enabled */
4339         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4340             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4341              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4342                 adapter->num_tx_queues = f_fdir->indices;
4343                 adapter->num_rx_queues = f_fdir->indices;
4344                 ret = true;
4345         } else {
4346                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4347                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4348         }
4349         return ret;
4350 }
4351
4352 #ifdef IXGBE_FCOE
4353 /**
4354  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4355  * @adapter: board private structure to initialize
4356  *
4357  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4358  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4359  * rx queues out of the max number of rx queues, instead, it is used as the
4360  * index of the first rx queue used by FCoE.
4361  *
4362  **/
4363 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4364 {
4365         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4366
4367         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4368                 return false;
4369
4370         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4371 #ifdef CONFIG_IXGBE_DCB
4372                 int tc;
4373                 struct net_device *dev = adapter->netdev;
4374
4375                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4376                 f->indices = dev->tc_to_txq[tc].count;
4377                 f->mask = dev->tc_to_txq[tc].offset;
4378 #endif
4379         } else {
4380                 f->indices = min((int)num_online_cpus(), f->indices);
4381
4382                 adapter->num_rx_queues = 1;
4383                 adapter->num_tx_queues = 1;
4384
4385                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4386                         e_info(probe, "FCoE enabled with RSS\n");
4387                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4388                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4389                                 ixgbe_set_fdir_queues(adapter);
4390                         else
4391                                 ixgbe_set_rss_queues(adapter);
4392                 }
4393                 /* adding FCoE rx rings to the end */
4394                 f->mask = adapter->num_rx_queues;
4395                 adapter->num_rx_queues += f->indices;
4396                 adapter->num_tx_queues += f->indices;
4397         }
4398
4399         return true;
4400 }
4401 #endif /* IXGBE_FCOE */
4402
4403 #ifdef CONFIG_IXGBE_DCB
4404 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4405 {
4406         bool ret = false;
4407         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4408         int i, q;
4409
4410         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4411                 return ret;
4412
4413         f->indices = 0;
4414         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4415                 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4416                 f->indices += q;
4417         }
4418
4419         f->mask = 0x7 << 3;
4420         adapter->num_rx_queues = f->indices;
4421         adapter->num_tx_queues = f->indices;
4422         ret = true;
4423
4424 #ifdef IXGBE_FCOE
4425         /* FCoE enabled queues require special configuration done through
4426          * configure_fcoe() and others. Here we map FCoE indices onto the
4427          * DCB queue pairs allowing FCoE to own configuration later.
4428          */
4429         ixgbe_set_fcoe_queues(adapter);
4430 #endif
4431
4432         return ret;
4433 }
4434 #endif
4435
4436 /**
4437  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4438  * @adapter: board private structure to initialize
4439  *
4440  * IOV doesn't actually use anything, so just NAK the
4441  * request for now and let the other queue routines
4442  * figure out what to do.
4443  */
4444 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4445 {
4446         return false;
4447 }
4448
4449 /*
4450  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4451  * @adapter: board private structure to initialize
4452  *
4453  * This is the top level queue allocation routine.  The order here is very
4454  * important, starting with the "most" number of features turned on at once,
4455  * and ending with the smallest set of features.  This way large combinations
4456  * can be allocated if they're turned on, and smaller combinations are the
4457  * fallthrough conditions.
4458  *
4459  **/
4460 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4461 {
4462         /* Start with base case */
4463         adapter->num_rx_queues = 1;
4464         adapter->num_tx_queues = 1;
4465         adapter->num_rx_pools = adapter->num_rx_queues;
4466         adapter->num_rx_queues_per_pool = 1;
4467
4468         if (ixgbe_set_sriov_queues(adapter))
4469                 goto done;
4470
4471 #ifdef CONFIG_IXGBE_DCB
4472         if (ixgbe_set_dcb_queues(adapter))
4473                 goto done;
4474
4475 #endif
4476 #ifdef IXGBE_FCOE
4477         if (ixgbe_set_fcoe_queues(adapter))
4478                 goto done;
4479
4480 #endif /* IXGBE_FCOE */
4481         if (ixgbe_set_fdir_queues(adapter))
4482                 goto done;
4483
4484         if (ixgbe_set_rss_queues(adapter))
4485                 goto done;
4486
4487         /* fallback to base case */
4488         adapter->num_rx_queues = 1;
4489         adapter->num_tx_queues = 1;
4490
4491 done:
4492         /* Notify the stack of the (possibly) reduced queue counts. */
4493         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4494         return netif_set_real_num_rx_queues(adapter->netdev,
4495                                             adapter->num_rx_queues);
4496 }
4497
4498 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4499                                        int vectors)
4500 {
4501         int err, vector_threshold;
4502
4503         /* We'll want at least 3 (vector_threshold):
4504          * 1) TxQ[0] Cleanup
4505          * 2) RxQ[0] Cleanup
4506          * 3) Other (Link Status Change, etc.)
4507          * 4) TCP Timer (optional)
4508          */
4509         vector_threshold = MIN_MSIX_COUNT;
4510
4511         /* The more we get, the more we will assign to Tx/Rx Cleanup
4512          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4513          * Right now, we simply care about how many we'll get; we'll
4514          * set them up later while requesting irq's.
4515          */
4516         while (vectors >= vector_threshold) {
4517                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4518                                       vectors);
4519                 if (!err) /* Success in acquiring all requested vectors. */
4520                         break;
4521                 else if (err < 0)
4522                         vectors = 0; /* Nasty failure, quit now */
4523                 else /* err == number of vectors we should try again with */
4524                         vectors = err;
4525         }
4526
4527         if (vectors < vector_threshold) {
4528                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4529                  * This just means we'll go with either a single MSI
4530                  * vector or fall back to legacy interrupts.
4531                  */
4532                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4533                              "Unable to allocate MSI-X interrupts\n");
4534                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4535                 kfree(adapter->msix_entries);
4536                 adapter->msix_entries = NULL;
4537         } else {
4538                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4539                 /*
4540                  * Adjust for only the vectors we'll use, which is minimum
4541                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4542                  * vectors we were allocated.
4543                  */
4544                 adapter->num_msix_vectors = min(vectors,
4545                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4546         }
4547 }
4548
4549 /**
4550  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4551  * @adapter: board private structure to initialize
4552  *
4553  * Cache the descriptor ring offsets for RSS to the assigned rings.
4554  *
4555  **/
4556 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4557 {
4558         int i;
4559
4560         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4561                 return false;
4562
4563         for (i = 0; i < adapter->num_rx_queues; i++)
4564                 adapter->rx_ring[i]->reg_idx = i;
4565         for (i = 0; i < adapter->num_tx_queues; i++)
4566                 adapter->tx_ring[i]->reg_idx = i;
4567
4568         return true;
4569 }
4570
4571 #ifdef CONFIG_IXGBE_DCB
4572
4573 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4574 void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4575                              unsigned int *tx, unsigned int *rx)
4576 {
4577         struct net_device *dev = adapter->netdev;
4578         struct ixgbe_hw *hw = &adapter->hw;
4579         u8 num_tcs = netdev_get_num_tc(dev);
4580
4581         *tx = 0;
4582         *rx = 0;
4583
4584         switch (hw->mac.type) {
4585         case ixgbe_mac_82598EB:
4586                 *tx = tc << 3;
4587                 *rx = tc << 2;
4588                 break;
4589         case ixgbe_mac_82599EB:
4590         case ixgbe_mac_X540:
4591                 if (num_tcs == 8) {
4592                         if (tc < 3) {
4593                                 *tx = tc << 5;
4594                                 *rx = tc << 4;
4595                         } else if (tc <  5) {
4596                                 *tx = ((tc + 2) << 4);
4597                                 *rx = tc << 4;
4598                         } else if (tc < num_tcs) {
4599                                 *tx = ((tc + 8) << 3);
4600                                 *rx = tc << 4;
4601                         }
4602                 } else if (num_tcs == 4) {
4603                         *rx =  tc << 5;
4604                         switch (tc) {
4605                         case 0:
4606                                 *tx =  0;
4607                                 break;
4608                         case 1:
4609                                 *tx = 64;
4610                                 break;
4611                         case 2:
4612                                 *tx = 96;
4613                                 break;
4614                         case 3:
4615                                 *tx = 112;
4616                                 break;
4617                         default:
4618                                 break;
4619                         }
4620                 }
4621                 break;
4622         default:
4623                 break;
4624         }
4625 }
4626
4627 #define IXGBE_MAX_Q_PER_TC      (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4628
4629 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4630  * classes.
4631  *
4632  * @netdev: net device to configure
4633  * @tc: number of traffic classes to enable
4634  */
4635 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4636 {
4637         int i;
4638         unsigned int q, offset = 0;
4639
4640         if (!tc) {
4641                 netdev_reset_tc(dev);
4642         } else {
4643                 struct ixgbe_adapter *adapter = netdev_priv(dev);
4644
4645                 /* Hardware supports up to 8 traffic classes */
4646                 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4647                         return -EINVAL;
4648
4649                 /* Partition Tx queues evenly amongst traffic classes */
4650                 for (i = 0; i < tc; i++) {
4651                         q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4652                         netdev_set_prio_tc_map(dev, i, i);
4653                         netdev_set_tc_queue(dev, i, q, offset);
4654                         offset += q;
4655                 }
4656
4657                 /* This enables multiple traffic class support in the hardware
4658                  * which defaults to strict priority transmission by default.
4659                  * If traffic classes are already enabled perhaps through DCB
4660                  * code path then existing configuration will be used.
4661                  */
4662                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4663                     dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4664                         struct ieee_ets ets = {
4665                                         .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4666                                               };
4667                         u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4668
4669                         dev->dcbnl_ops->setdcbx(dev, mode);
4670                         dev->dcbnl_ops->ieee_setets(dev, &ets);
4671                 }
4672         }
4673         return 0;
4674 }
4675
4676 /**
4677  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4678  * @adapter: board private structure to initialize
4679  *
4680  * Cache the descriptor ring offsets for DCB to the assigned rings.
4681  *
4682  **/
4683 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4684 {
4685         struct net_device *dev = adapter->netdev;
4686         int i, j, k;
4687         u8 num_tcs = netdev_get_num_tc(dev);
4688
4689         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4690                 return false;
4691
4692         for (i = 0, k = 0; i < num_tcs; i++) {
4693                 unsigned int tx_s, rx_s;
4694                 u16 count = dev->tc_to_txq[i].count;
4695
4696                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4697                 for (j = 0; j < count; j++, k++) {
4698                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4699                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4700                         adapter->tx_ring[k]->dcb_tc = i;
4701                         adapter->rx_ring[k]->dcb_tc = i;
4702                 }
4703         }
4704
4705         return true;
4706 }
4707 #endif
4708
4709 /**
4710  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4711  * @adapter: board private structure to initialize
4712  *
4713  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4714  *
4715  **/
4716 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4717 {
4718         int i;
4719         bool ret = false;
4720
4721         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4722             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4723              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4724                 for (i = 0; i < adapter->num_rx_queues; i++)
4725                         adapter->rx_ring[i]->reg_idx = i;
4726                 for (i = 0; i < adapter->num_tx_queues; i++)
4727                         adapter->tx_ring[i]->reg_idx = i;
4728                 ret = true;
4729         }
4730
4731         return ret;
4732 }
4733
4734 #ifdef IXGBE_FCOE
4735 /**
4736  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4737  * @adapter: board private structure to initialize
4738  *
4739  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4740  *
4741  */
4742 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4743 {
4744         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4745         int i;
4746         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4747
4748         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4749                 return false;
4750
4751         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4752                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4753                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4754                         ixgbe_cache_ring_fdir(adapter);
4755                 else
4756                         ixgbe_cache_ring_rss(adapter);
4757
4758                 fcoe_rx_i = f->mask;
4759                 fcoe_tx_i = f->mask;
4760         }
4761         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4762                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4763                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4764         }
4765         return true;
4766 }
4767
4768 #endif /* IXGBE_FCOE */
4769 /**
4770  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4771  * @adapter: board private structure to initialize
4772  *
4773  * SR-IOV doesn't use any descriptor rings but changes the default if
4774  * no other mapping is used.
4775  *
4776  */
4777 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4778 {
4779         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4780         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4781         if (adapter->num_vfs)
4782                 return true;
4783         else
4784                 return false;
4785 }
4786
4787 /**
4788  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4789  * @adapter: board private structure to initialize
4790  *
4791  * Once we know the feature-set enabled for the device, we'll cache
4792  * the register offset the descriptor ring is assigned to.
4793  *
4794  * Note, the order the various feature calls is important.  It must start with
4795  * the "most" features enabled at the same time, then trickle down to the
4796  * least amount of features turned on at once.
4797  **/
4798 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4799 {
4800         /* start with default case */
4801         adapter->rx_ring[0]->reg_idx = 0;
4802         adapter->tx_ring[0]->reg_idx = 0;
4803
4804         if (ixgbe_cache_ring_sriov(adapter))
4805                 return;
4806
4807 #ifdef CONFIG_IXGBE_DCB
4808         if (ixgbe_cache_ring_dcb(adapter))
4809                 return;
4810 #endif
4811
4812 #ifdef IXGBE_FCOE
4813         if (ixgbe_cache_ring_fcoe(adapter))
4814                 return;
4815 #endif /* IXGBE_FCOE */
4816
4817         if (ixgbe_cache_ring_fdir(adapter))
4818                 return;
4819
4820         if (ixgbe_cache_ring_rss(adapter))
4821                 return;
4822 }
4823
4824 /**
4825  * ixgbe_alloc_queues - Allocate memory for all rings
4826  * @adapter: board private structure to initialize
4827  *
4828  * We allocate one ring per queue at run-time since we don't know the
4829  * number of queues at compile-time.  The polling_netdev array is
4830  * intended for Multiqueue, but should work fine with a single queue.
4831  **/
4832 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4833 {
4834         int rx = 0, tx = 0, nid = adapter->node;
4835
4836         if (nid < 0 || !node_online(nid))
4837                 nid = first_online_node;
4838
4839         for (; tx < adapter->num_tx_queues; tx++) {
4840                 struct ixgbe_ring *ring;
4841
4842                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4843                 if (!ring)
4844                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4845                 if (!ring)
4846                         goto err_allocation;
4847                 ring->count = adapter->tx_ring_count;
4848                 ring->queue_index = tx;
4849                 ring->numa_node = nid;
4850                 ring->dev = &adapter->pdev->dev;
4851                 ring->netdev = adapter->netdev;
4852
4853                 adapter->tx_ring[tx] = ring;
4854         }
4855
4856         for (; rx < adapter->num_rx_queues; rx++) {
4857                 struct ixgbe_ring *ring;
4858
4859                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4860                 if (!ring)
4861                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4862                 if (!ring)
4863                         goto err_allocation;
4864                 ring->count = adapter->rx_ring_count;
4865                 ring->queue_index = rx;
4866                 ring->numa_node = nid;
4867                 ring->dev = &adapter->pdev->dev;
4868                 ring->netdev = adapter->netdev;
4869
4870                 adapter->rx_ring[rx] = ring;
4871         }
4872
4873         ixgbe_cache_ring_register(adapter);
4874
4875         return 0;
4876
4877 err_allocation:
4878         while (tx)
4879                 kfree(adapter->tx_ring[--tx]);
4880
4881         while (rx)
4882                 kfree(adapter->rx_ring[--rx]);
4883         return -ENOMEM;
4884 }
4885
4886 /**
4887  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4888  * @adapter: board private structure to initialize
4889  *
4890  * Attempt to configure the interrupts using the best available
4891  * capabilities of the hardware and the kernel.
4892  **/
4893 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4894 {
4895         struct ixgbe_hw *hw = &adapter->hw;
4896         int err = 0;
4897         int vector, v_budget;
4898
4899         /*
4900          * It's easy to be greedy for MSI-X vectors, but it really
4901          * doesn't do us much good if we have a lot more vectors
4902          * than CPU's.  So let's be conservative and only ask for
4903          * (roughly) the same number of vectors as there are CPU's.
4904          */
4905         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4906                        (int)num_online_cpus()) + NON_Q_VECTORS;
4907
4908         /*
4909          * At the same time, hardware can only support a maximum of
4910          * hw.mac->max_msix_vectors vectors.  With features
4911          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4912          * descriptor queues supported by our device.  Thus, we cap it off in
4913          * those rare cases where the cpu count also exceeds our vector limit.
4914          */
4915         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4916
4917         /* A failure in MSI-X entry allocation isn't fatal, but it does
4918          * mean we disable MSI-X capabilities of the adapter. */
4919         adapter->msix_entries = kcalloc(v_budget,
4920                                         sizeof(struct msix_entry), GFP_KERNEL);
4921         if (adapter->msix_entries) {
4922                 for (vector = 0; vector < v_budget; vector++)
4923                         adapter->msix_entries[vector].entry = vector;
4924
4925                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4926
4927                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4928                         goto out;
4929         }
4930
4931         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4932         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4933         if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4934                               IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4935                 e_err(probe,
4936                       "Flow Director is not supported while multiple "
4937                       "queues are disabled.  Disabling Flow Director\n");
4938         }
4939         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4940         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4941         adapter->atr_sample_rate = 0;
4942         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4943                 ixgbe_disable_sriov(adapter);
4944
4945         err = ixgbe_set_num_queues(adapter);
4946         if (err)
4947                 return err;
4948
4949         err = pci_enable_msi(adapter->pdev);
4950         if (!err) {
4951                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4952         } else {
4953                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4954                              "Unable to allocate MSI interrupt, "
4955                              "falling back to legacy.  Error: %d\n", err);
4956                 /* reset err */
4957                 err = 0;
4958         }
4959
4960 out:
4961         return err;
4962 }
4963
4964 /**
4965  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4966  * @adapter: board private structure to initialize
4967  *
4968  * We allocate one q_vector per queue interrupt.  If allocation fails we
4969  * return -ENOMEM.
4970  **/
4971 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4972 {
4973         int q_idx, num_q_vectors;
4974         struct ixgbe_q_vector *q_vector;
4975         int (*poll)(struct napi_struct *, int);
4976
4977         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4978                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4979                 poll = &ixgbe_clean_rxtx_many;
4980         } else {
4981                 num_q_vectors = 1;
4982                 poll = &ixgbe_poll;
4983         }
4984
4985         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4986                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4987                                         GFP_KERNEL, adapter->node);
4988                 if (!q_vector)
4989                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4990                                            GFP_KERNEL);
4991                 if (!q_vector)
4992                         goto err_out;
4993                 q_vector->adapter = adapter;
4994                 if (q_vector->txr_count && !q_vector->rxr_count)
4995                         q_vector->eitr = adapter->tx_eitr_param;
4996                 else
4997                         q_vector->eitr = adapter->rx_eitr_param;
4998                 q_vector->v_idx = q_idx;
4999                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
5000                 adapter->q_vector[q_idx] = q_vector;
5001         }
5002
5003         return 0;
5004
5005 err_out:
5006         while (q_idx) {
5007                 q_idx--;
5008                 q_vector = adapter->q_vector[q_idx];
5009                 netif_napi_del(&q_vector->napi);
5010                 kfree(q_vector);
5011                 adapter->q_vector[q_idx] = NULL;
5012         }
5013         return -ENOMEM;
5014 }
5015
5016 /**
5017  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5018  * @adapter: board private structure to initialize
5019  *
5020  * This function frees the memory allocated to the q_vectors.  In addition if
5021  * NAPI is enabled it will delete any references to the NAPI struct prior
5022  * to freeing the q_vector.
5023  **/
5024 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5025 {
5026         int q_idx, num_q_vectors;
5027
5028         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5029                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5030         else
5031                 num_q_vectors = 1;
5032
5033         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5034                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5035                 adapter->q_vector[q_idx] = NULL;
5036                 netif_napi_del(&q_vector->napi);
5037                 kfree(q_vector);
5038         }
5039 }
5040
5041 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5042 {
5043         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5044                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5045                 pci_disable_msix(adapter->pdev);
5046                 kfree(adapter->msix_entries);
5047                 adapter->msix_entries = NULL;
5048         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5049                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5050                 pci_disable_msi(adapter->pdev);
5051         }
5052 }
5053
5054 /**
5055  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5056  * @adapter: board private structure to initialize
5057  *
5058  * We determine which interrupt scheme to use based on...
5059  * - Kernel support (MSI, MSI-X)
5060  *   - which can be user-defined (via MODULE_PARAM)
5061  * - Hardware queue count (num_*_queues)
5062  *   - defined by miscellaneous hardware support/features (RSS, etc.)
5063  **/
5064 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5065 {
5066         int err;
5067
5068         /* Number of supported queues */
5069         err = ixgbe_set_num_queues(adapter);
5070         if (err)
5071                 return err;
5072
5073         err = ixgbe_set_interrupt_capability(adapter);
5074         if (err) {
5075                 e_dev_err("Unable to setup interrupt capabilities\n");
5076                 goto err_set_interrupt;
5077         }
5078
5079         err = ixgbe_alloc_q_vectors(adapter);
5080         if (err) {
5081                 e_dev_err("Unable to allocate memory for queue vectors\n");
5082                 goto err_alloc_q_vectors;
5083         }
5084
5085         err = ixgbe_alloc_queues(adapter);
5086         if (err) {
5087                 e_dev_err("Unable to allocate memory for queues\n");
5088                 goto err_alloc_queues;
5089         }
5090
5091         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5092                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5093                    adapter->num_rx_queues, adapter->num_tx_queues);
5094
5095         set_bit(__IXGBE_DOWN, &adapter->state);
5096
5097         return 0;
5098
5099 err_alloc_queues:
5100         ixgbe_free_q_vectors(adapter);
5101 err_alloc_q_vectors:
5102         ixgbe_reset_interrupt_capability(adapter);
5103 err_set_interrupt:
5104         return err;
5105 }
5106
5107 static void ring_free_rcu(struct rcu_head *head)
5108 {
5109         kfree(container_of(head, struct ixgbe_ring, rcu));
5110 }
5111
5112 /**
5113  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5114  * @adapter: board private structure to clear interrupt scheme on
5115  *
5116  * We go through and clear interrupt specific resources and reset the structure
5117  * to pre-load conditions
5118  **/
5119 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5120 {
5121         int i;
5122
5123         for (i = 0; i < adapter->num_tx_queues; i++) {
5124                 kfree(adapter->tx_ring[i]);
5125                 adapter->tx_ring[i] = NULL;
5126         }
5127         for (i = 0; i < adapter->num_rx_queues; i++) {
5128                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5129
5130                 /* ixgbe_get_stats64() might access this ring, we must wait
5131                  * a grace period before freeing it.
5132                  */
5133                 call_rcu(&ring->rcu, ring_free_rcu);
5134                 adapter->rx_ring[i] = NULL;
5135         }
5136
5137         adapter->num_tx_queues = 0;
5138         adapter->num_rx_queues = 0;
5139
5140         ixgbe_free_q_vectors(adapter);
5141         ixgbe_reset_interrupt_capability(adapter);
5142 }
5143
5144 /**
5145  * ixgbe_sfp_timer - worker thread to find a missing module
5146  * @data: pointer to our adapter struct
5147  **/
5148 static void ixgbe_sfp_timer(unsigned long data)
5149 {
5150         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5151
5152         /*
5153          * Do the sfp_timer outside of interrupt context due to the
5154          * delays that sfp+ detection requires
5155          */
5156         schedule_work(&adapter->sfp_task);
5157 }
5158
5159 /**
5160  * ixgbe_sfp_task - worker thread to find a missing module
5161  * @work: pointer to work_struct containing our data
5162  **/
5163 static void ixgbe_sfp_task(struct work_struct *work)
5164 {
5165         struct ixgbe_adapter *adapter = container_of(work,
5166                                                      struct ixgbe_adapter,
5167                                                      sfp_task);
5168         struct ixgbe_hw *hw = &adapter->hw;
5169
5170         if ((hw->phy.type == ixgbe_phy_nl) &&
5171             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
5172                 s32 ret = hw->phy.ops.identify_sfp(hw);
5173                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
5174                         goto reschedule;
5175                 ret = hw->phy.ops.reset(hw);
5176                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5177                         e_dev_err("failed to initialize because an unsupported "
5178                                   "SFP+ module type was detected.\n");
5179                         e_dev_err("Reload the driver after installing a "
5180                                   "supported module.\n");
5181                         unregister_netdev(adapter->netdev);
5182                 } else {
5183                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5184                 }
5185                 /* don't need this routine any more */
5186                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5187         }
5188         return;
5189 reschedule:
5190         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5191                 mod_timer(&adapter->sfp_timer,
5192                           round_jiffies(jiffies + (2 * HZ)));
5193 }
5194
5195 /**
5196  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5197  * @adapter: board private structure to initialize
5198  *
5199  * ixgbe_sw_init initializes the Adapter private data structure.
5200  * Fields are initialized based on PCI device information and
5201  * OS network device settings (MTU size).
5202  **/
5203 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5204 {
5205         struct ixgbe_hw *hw = &adapter->hw;
5206         struct pci_dev *pdev = adapter->pdev;
5207         struct net_device *dev = adapter->netdev;
5208         unsigned int rss;
5209 #ifdef CONFIG_IXGBE_DCB
5210         int j;
5211         struct tc_configuration *tc;
5212 #endif
5213         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5214
5215         /* PCI config space info */
5216
5217         hw->vendor_id = pdev->vendor;
5218         hw->device_id = pdev->device;
5219         hw->revision_id = pdev->revision;
5220         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5221         hw->subsystem_device_id = pdev->subsystem_device;
5222
5223         /* Set capability flags */
5224         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5225         adapter->ring_feature[RING_F_RSS].indices = rss;
5226         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5227         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5228         switch (hw->mac.type) {
5229         case ixgbe_mac_82598EB:
5230                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5231                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5232                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5233                 break;
5234         case ixgbe_mac_82599EB:
5235         case ixgbe_mac_X540:
5236                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5237                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5238                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5239                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5240                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5241                 /* n-tuple support exists, always init our spinlock */
5242                 spin_lock_init(&adapter->fdir_perfect_lock);
5243                 /* Flow Director hash filters enabled */
5244                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5245                 adapter->atr_sample_rate = 20;
5246                 adapter->ring_feature[RING_F_FDIR].indices =
5247                                                          IXGBE_MAX_FDIR_INDICES;
5248                 adapter->fdir_pballoc = 0;
5249 #ifdef IXGBE_FCOE
5250                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5251                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5252                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5253 #ifdef CONFIG_IXGBE_DCB
5254                 /* Default traffic class to use for FCoE */
5255                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5256                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5257 #endif
5258 #endif /* IXGBE_FCOE */
5259                 break;
5260         default:
5261                 break;
5262         }
5263
5264 #ifdef CONFIG_IXGBE_DCB
5265         /* Configure DCB traffic classes */
5266         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5267                 tc = &adapter->dcb_cfg.tc_config[j];
5268                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5269                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5270                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5271                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5272                 tc->dcb_pfc = pfc_disabled;
5273         }
5274         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5275         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5276         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5277         adapter->dcb_cfg.pfc_mode_enable = false;
5278         adapter->dcb_set_bitmap = 0x00;
5279         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5280         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5281                            MAX_TRAFFIC_CLASS);
5282
5283 #endif
5284
5285         /* default flow control settings */
5286         hw->fc.requested_mode = ixgbe_fc_full;
5287         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5288 #ifdef CONFIG_DCB
5289         adapter->last_lfc_mode = hw->fc.current_mode;
5290 #endif
5291         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5292         hw->fc.low_water = FC_LOW_WATER(max_frame);
5293         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5294         hw->fc.send_xon = true;
5295         hw->fc.disable_fc_autoneg = false;
5296
5297         /* enable itr by default in dynamic mode */
5298         adapter->rx_itr_setting = 1;
5299         adapter->rx_eitr_param = 20000;
5300         adapter->tx_itr_setting = 1;
5301         adapter->tx_eitr_param = 10000;
5302
5303         /* set defaults for eitr in MegaBytes */
5304         adapter->eitr_low = 10;
5305         adapter->eitr_high = 20;
5306
5307         /* set default ring sizes */
5308         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5309         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5310
5311         /* initialize eeprom parameters */
5312         if (ixgbe_init_eeprom_params_generic(hw)) {
5313                 e_dev_err("EEPROM initialization failed\n");
5314                 return -EIO;
5315         }
5316
5317         /* enable rx csum by default */
5318         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5319
5320         /* get assigned NUMA node */
5321         adapter->node = dev_to_node(&pdev->dev);
5322
5323         set_bit(__IXGBE_DOWN, &adapter->state);
5324
5325         return 0;
5326 }
5327
5328 /**
5329  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5330  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5331  *
5332  * Return 0 on success, negative on failure
5333  **/
5334 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5335 {
5336         struct device *dev = tx_ring->dev;
5337         int size;
5338
5339         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5340         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5341         if (!tx_ring->tx_buffer_info)
5342                 tx_ring->tx_buffer_info = vzalloc(size);
5343         if (!tx_ring->tx_buffer_info)
5344                 goto err;
5345
5346         /* round up to nearest 4K */
5347         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5348         tx_ring->size = ALIGN(tx_ring->size, 4096);
5349
5350         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5351                                            &tx_ring->dma, GFP_KERNEL);
5352         if (!tx_ring->desc)
5353                 goto err;
5354
5355         tx_ring->next_to_use = 0;
5356         tx_ring->next_to_clean = 0;
5357         tx_ring->work_limit = tx_ring->count;
5358         return 0;
5359
5360 err:
5361         vfree(tx_ring->tx_buffer_info);
5362         tx_ring->tx_buffer_info = NULL;
5363         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5364         return -ENOMEM;
5365 }
5366
5367 /**
5368  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5369  * @adapter: board private structure
5370  *
5371  * If this function returns with an error, then it's possible one or
5372  * more of the rings is populated (while the rest are not).  It is the
5373  * callers duty to clean those orphaned rings.
5374  *
5375  * Return 0 on success, negative on failure
5376  **/
5377 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5378 {
5379         int i, err = 0;
5380
5381         for (i = 0; i < adapter->num_tx_queues; i++) {
5382                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5383                 if (!err)
5384                         continue;
5385                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5386                 break;
5387         }
5388
5389         return err;
5390 }
5391
5392 /**
5393  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5394  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5395  *
5396  * Returns 0 on success, negative on failure
5397  **/
5398 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5399 {
5400         struct device *dev = rx_ring->dev;
5401         int size;
5402
5403         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5404         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5405         if (!rx_ring->rx_buffer_info)
5406                 rx_ring->rx_buffer_info = vzalloc(size);
5407         if (!rx_ring->rx_buffer_info)
5408                 goto err;
5409
5410         /* Round up to nearest 4K */
5411         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5412         rx_ring->size = ALIGN(rx_ring->size, 4096);
5413
5414         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5415                                            &rx_ring->dma, GFP_KERNEL);
5416
5417         if (!rx_ring->desc)
5418                 goto err;
5419
5420         rx_ring->next_to_clean = 0;
5421         rx_ring->next_to_use = 0;
5422
5423         return 0;
5424 err:
5425         vfree(rx_ring->rx_buffer_info);
5426         rx_ring->rx_buffer_info = NULL;
5427         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5428         return -ENOMEM;
5429 }
5430
5431 /**
5432  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5433  * @adapter: board private structure
5434  *
5435  * If this function returns with an error, then it's possible one or
5436  * more of the rings is populated (while the rest are not).  It is the
5437  * callers duty to clean those orphaned rings.
5438  *
5439  * Return 0 on success, negative on failure
5440  **/
5441 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5442 {
5443         int i, err = 0;
5444
5445         for (i = 0; i < adapter->num_rx_queues; i++) {
5446                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5447                 if (!err)
5448                         continue;
5449                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5450                 break;
5451         }
5452
5453         return err;
5454 }
5455
5456 /**
5457  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5458  * @tx_ring: Tx descriptor ring for a specific queue
5459  *
5460  * Free all transmit software resources
5461  **/
5462 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5463 {
5464         ixgbe_clean_tx_ring(tx_ring);
5465
5466         vfree(tx_ring->tx_buffer_info);
5467         tx_ring->tx_buffer_info = NULL;
5468
5469         /* if not set, then don't free */
5470         if (!tx_ring->desc)
5471                 return;
5472
5473         dma_free_coherent(tx_ring->dev, tx_ring->size,
5474                           tx_ring->desc, tx_ring->dma);
5475
5476         tx_ring->desc = NULL;
5477 }
5478
5479 /**
5480  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5481  * @adapter: board private structure
5482  *
5483  * Free all transmit software resources
5484  **/
5485 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5486 {
5487         int i;
5488
5489         for (i = 0; i < adapter->num_tx_queues; i++)
5490                 if (adapter->tx_ring[i]->desc)
5491                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5492 }
5493
5494 /**
5495  * ixgbe_free_rx_resources - Free Rx Resources
5496  * @rx_ring: ring to clean the resources from
5497  *
5498  * Free all receive software resources
5499  **/
5500 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5501 {
5502         ixgbe_clean_rx_ring(rx_ring);
5503
5504         vfree(rx_ring->rx_buffer_info);
5505         rx_ring->rx_buffer_info = NULL;
5506
5507         /* if not set, then don't free */
5508         if (!rx_ring->desc)
5509                 return;
5510
5511         dma_free_coherent(rx_ring->dev, rx_ring->size,
5512                           rx_ring->desc, rx_ring->dma);
5513
5514         rx_ring->desc = NULL;
5515 }
5516
5517 /**
5518  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5519  * @adapter: board private structure
5520  *
5521  * Free all receive software resources
5522  **/
5523 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5524 {
5525         int i;
5526
5527         for (i = 0; i < adapter->num_rx_queues; i++)
5528                 if (adapter->rx_ring[i]->desc)
5529                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5530 }
5531
5532 /**
5533  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5534  * @netdev: network interface device structure
5535  * @new_mtu: new value for maximum frame size
5536  *
5537  * Returns 0 on success, negative on failure
5538  **/
5539 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5540 {
5541         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5542         struct ixgbe_hw *hw = &adapter->hw;
5543         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5544
5545         /* MTU < 68 is an error and causes problems on some kernels */
5546         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5547             hw->mac.type != ixgbe_mac_X540) {
5548                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5549                         return -EINVAL;
5550         } else {
5551                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5552                         return -EINVAL;
5553         }
5554
5555         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5556         /* must set new MTU before calling down or up */
5557         netdev->mtu = new_mtu;
5558
5559         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5560         hw->fc.low_water = FC_LOW_WATER(max_frame);
5561
5562         if (netif_running(netdev))
5563                 ixgbe_reinit_locked(adapter);
5564
5565         return 0;
5566 }
5567
5568 /**
5569  * ixgbe_open - Called when a network interface is made active
5570  * @netdev: network interface device structure
5571  *
5572  * Returns 0 on success, negative value on failure
5573  *
5574  * The open entry point is called when a network interface is made
5575  * active by the system (IFF_UP).  At this point all resources needed
5576  * for transmit and receive operations are allocated, the interrupt
5577  * handler is registered with the OS, the watchdog timer is started,
5578  * and the stack is notified that the interface is ready.
5579  **/
5580 static int ixgbe_open(struct net_device *netdev)
5581 {
5582         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5583         int err;
5584
5585         /* disallow open during test */
5586         if (test_bit(__IXGBE_TESTING, &adapter->state))
5587                 return -EBUSY;
5588
5589         netif_carrier_off(netdev);
5590
5591         /* allocate transmit descriptors */
5592         err = ixgbe_setup_all_tx_resources(adapter);
5593         if (err)
5594                 goto err_setup_tx;
5595
5596         /* allocate receive descriptors */
5597         err = ixgbe_setup_all_rx_resources(adapter);
5598         if (err)
5599                 goto err_setup_rx;
5600
5601         ixgbe_configure(adapter);
5602
5603         err = ixgbe_request_irq(adapter);
5604         if (err)
5605                 goto err_req_irq;
5606
5607         err = ixgbe_up_complete(adapter);
5608         if (err)
5609                 goto err_up;
5610
5611         netif_tx_start_all_queues(netdev);
5612
5613         return 0;
5614
5615 err_up:
5616         ixgbe_release_hw_control(adapter);
5617         ixgbe_free_irq(adapter);
5618 err_req_irq:
5619 err_setup_rx:
5620         ixgbe_free_all_rx_resources(adapter);
5621 err_setup_tx:
5622         ixgbe_free_all_tx_resources(adapter);
5623         ixgbe_reset(adapter);
5624
5625         return err;
5626 }
5627
5628 /**
5629  * ixgbe_close - Disables a network interface
5630  * @netdev: network interface device structure
5631  *
5632  * Returns 0, this is not allowed to fail
5633  *
5634  * The close entry point is called when an interface is de-activated
5635  * by the OS.  The hardware is still under the drivers control, but
5636  * needs to be disabled.  A global MAC reset is issued to stop the
5637  * hardware, and all transmit and receive resources are freed.
5638  **/
5639 static int ixgbe_close(struct net_device *netdev)
5640 {
5641         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5642
5643         ixgbe_down(adapter);
5644         ixgbe_free_irq(adapter);
5645
5646         ixgbe_free_all_tx_resources(adapter);
5647         ixgbe_free_all_rx_resources(adapter);
5648
5649         ixgbe_release_hw_control(adapter);
5650
5651         return 0;
5652 }
5653
5654 #ifdef CONFIG_PM
5655 static int ixgbe_resume(struct pci_dev *pdev)
5656 {
5657         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5658         struct net_device *netdev = adapter->netdev;
5659         u32 err;
5660
5661         pci_set_power_state(pdev, PCI_D0);
5662         pci_restore_state(pdev);
5663         /*
5664          * pci_restore_state clears dev->state_saved so call
5665          * pci_save_state to restore it.
5666          */
5667         pci_save_state(pdev);
5668
5669         err = pci_enable_device_mem(pdev);
5670         if (err) {
5671                 e_dev_err("Cannot enable PCI device from suspend\n");
5672                 return err;
5673         }
5674         pci_set_master(pdev);
5675
5676         pci_wake_from_d3(pdev, false);
5677
5678         err = ixgbe_init_interrupt_scheme(adapter);
5679         if (err) {
5680                 e_dev_err("Cannot initialize interrupts for device\n");
5681                 return err;
5682         }
5683
5684         ixgbe_reset(adapter);
5685
5686         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5687
5688         if (netif_running(netdev)) {
5689                 err = ixgbe_open(netdev);
5690                 if (err)
5691                         return err;
5692         }
5693
5694         netif_device_attach(netdev);
5695
5696         return 0;
5697 }
5698 #endif /* CONFIG_PM */
5699
5700 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5701 {
5702         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5703         struct net_device *netdev = adapter->netdev;
5704         struct ixgbe_hw *hw = &adapter->hw;
5705         u32 ctrl, fctrl;
5706         u32 wufc = adapter->wol;
5707 #ifdef CONFIG_PM
5708         int retval = 0;
5709 #endif
5710
5711         netif_device_detach(netdev);
5712
5713         if (netif_running(netdev)) {
5714                 ixgbe_down(adapter);
5715                 ixgbe_free_irq(adapter);
5716                 ixgbe_free_all_tx_resources(adapter);
5717                 ixgbe_free_all_rx_resources(adapter);
5718         }
5719
5720         ixgbe_clear_interrupt_scheme(adapter);
5721 #ifdef CONFIG_DCB
5722         kfree(adapter->ixgbe_ieee_pfc);
5723         kfree(adapter->ixgbe_ieee_ets);
5724 #endif
5725
5726 #ifdef CONFIG_PM
5727         retval = pci_save_state(pdev);
5728         if (retval)
5729                 return retval;
5730
5731 #endif
5732         if (wufc) {
5733                 ixgbe_set_rx_mode(netdev);
5734
5735                 /* turn on all-multi mode if wake on multicast is enabled */
5736                 if (wufc & IXGBE_WUFC_MC) {
5737                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5738                         fctrl |= IXGBE_FCTRL_MPE;
5739                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5740                 }
5741
5742                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5743                 ctrl |= IXGBE_CTRL_GIO_DIS;
5744                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5745
5746                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5747         } else {
5748                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5749                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5750         }
5751
5752         switch (hw->mac.type) {
5753         case ixgbe_mac_82598EB:
5754                 pci_wake_from_d3(pdev, false);
5755                 break;
5756         case ixgbe_mac_82599EB:
5757         case ixgbe_mac_X540:
5758                 pci_wake_from_d3(pdev, !!wufc);
5759                 break;
5760         default:
5761                 break;
5762         }
5763
5764         *enable_wake = !!wufc;
5765
5766         ixgbe_release_hw_control(adapter);
5767
5768         pci_disable_device(pdev);
5769
5770         return 0;
5771 }
5772
5773 #ifdef CONFIG_PM
5774 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5775 {
5776         int retval;
5777         bool wake;
5778
5779         retval = __ixgbe_shutdown(pdev, &wake);
5780         if (retval)
5781                 return retval;
5782
5783         if (wake) {
5784                 pci_prepare_to_sleep(pdev);
5785         } else {
5786                 pci_wake_from_d3(pdev, false);
5787                 pci_set_power_state(pdev, PCI_D3hot);
5788         }
5789
5790         return 0;
5791 }
5792 #endif /* CONFIG_PM */
5793
5794 static void ixgbe_shutdown(struct pci_dev *pdev)
5795 {
5796         bool wake;
5797
5798         __ixgbe_shutdown(pdev, &wake);
5799
5800         if (system_state == SYSTEM_POWER_OFF) {
5801                 pci_wake_from_d3(pdev, wake);
5802                 pci_set_power_state(pdev, PCI_D3hot);
5803         }
5804 }
5805
5806 /**
5807  * ixgbe_update_stats - Update the board statistics counters.
5808  * @adapter: board private structure
5809  **/
5810 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5811 {
5812         struct net_device *netdev = adapter->netdev;
5813         struct ixgbe_hw *hw = &adapter->hw;
5814         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5815         u64 total_mpc = 0;
5816         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5817         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5818         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5819         u64 bytes = 0, packets = 0;
5820
5821         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5822             test_bit(__IXGBE_RESETTING, &adapter->state))
5823                 return;
5824
5825         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5826                 u64 rsc_count = 0;
5827                 u64 rsc_flush = 0;
5828                 for (i = 0; i < 16; i++)
5829                         adapter->hw_rx_no_dma_resources +=
5830                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5831                 for (i = 0; i < adapter->num_rx_queues; i++) {
5832                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5833                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5834                 }
5835                 adapter->rsc_total_count = rsc_count;
5836                 adapter->rsc_total_flush = rsc_flush;
5837         }
5838
5839         for (i = 0; i < adapter->num_rx_queues; i++) {
5840                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5841                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5842                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5843                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5844                 bytes += rx_ring->stats.bytes;
5845                 packets += rx_ring->stats.packets;
5846         }
5847         adapter->non_eop_descs = non_eop_descs;
5848         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5849         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5850         netdev->stats.rx_bytes = bytes;
5851         netdev->stats.rx_packets = packets;
5852
5853         bytes = 0;
5854         packets = 0;
5855         /* gather some stats to the adapter struct that are per queue */
5856         for (i = 0; i < adapter->num_tx_queues; i++) {
5857                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5858                 restart_queue += tx_ring->tx_stats.restart_queue;
5859                 tx_busy += tx_ring->tx_stats.tx_busy;
5860                 bytes += tx_ring->stats.bytes;
5861                 packets += tx_ring->stats.packets;
5862         }
5863         adapter->restart_queue = restart_queue;
5864         adapter->tx_busy = tx_busy;
5865         netdev->stats.tx_bytes = bytes;
5866         netdev->stats.tx_packets = packets;
5867
5868         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5869         for (i = 0; i < 8; i++) {
5870                 /* for packet buffers not used, the register should read 0 */
5871                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5872                 missed_rx += mpc;
5873                 hwstats->mpc[i] += mpc;
5874                 total_mpc += hwstats->mpc[i];
5875                 if (hw->mac.type == ixgbe_mac_82598EB)
5876                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5877                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5878                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5879                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5880                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5881                 switch (hw->mac.type) {
5882                 case ixgbe_mac_82598EB:
5883                         hwstats->pxonrxc[i] +=
5884                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5885                         break;
5886                 case ixgbe_mac_82599EB:
5887                 case ixgbe_mac_X540:
5888                         hwstats->pxonrxc[i] +=
5889                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5890                         break;
5891                 default:
5892                         break;
5893                 }
5894                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5895                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5896         }
5897         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5898         /* work around hardware counting issue */
5899         hwstats->gprc -= missed_rx;
5900
5901         ixgbe_update_xoff_received(adapter);
5902
5903         /* 82598 hardware only has a 32 bit counter in the high register */
5904         switch (hw->mac.type) {
5905         case ixgbe_mac_82598EB:
5906                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5907                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5908                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5909                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5910                 break;
5911         case ixgbe_mac_82599EB:
5912         case ixgbe_mac_X540:
5913                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5914                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5915                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5916                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5917                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5918                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5919                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5920                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5921                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5922 #ifdef IXGBE_FCOE
5923                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5924                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5925                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5926                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5927                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5928                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5929 #endif /* IXGBE_FCOE */
5930                 break;
5931         default:
5932                 break;
5933         }
5934         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5935         hwstats->bprc += bprc;
5936         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5937         if (hw->mac.type == ixgbe_mac_82598EB)
5938                 hwstats->mprc -= bprc;
5939         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5940         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5941         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5942         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5943         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5944         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5945         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5946         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5947         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5948         hwstats->lxontxc += lxon;
5949         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5950         hwstats->lxofftxc += lxoff;
5951         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5952         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5953         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5954         /*
5955          * 82598 errata - tx of flow control packets is included in tx counters
5956          */
5957         xon_off_tot = lxon + lxoff;
5958         hwstats->gptc -= xon_off_tot;
5959         hwstats->mptc -= xon_off_tot;
5960         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5961         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5962         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5963         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5964         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5965         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5966         hwstats->ptc64 -= xon_off_tot;
5967         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5968         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5969         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5970         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5971         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5972         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5973
5974         /* Fill out the OS statistics structure */
5975         netdev->stats.multicast = hwstats->mprc;
5976
5977         /* Rx Errors */
5978         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5979         netdev->stats.rx_dropped = 0;
5980         netdev->stats.rx_length_errors = hwstats->rlec;
5981         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5982         netdev->stats.rx_missed_errors = total_mpc;
5983 }
5984
5985 /**
5986  * ixgbe_watchdog - Timer Call-back
5987  * @data: pointer to adapter cast into an unsigned long
5988  **/
5989 static void ixgbe_watchdog(unsigned long data)
5990 {
5991         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5992         struct ixgbe_hw *hw = &adapter->hw;
5993         u64 eics = 0;
5994         int i;
5995
5996         /*
5997          *  Do the watchdog outside of interrupt context due to the lovely
5998          * delays that some of the newer hardware requires
5999          */
6000
6001         if (test_bit(__IXGBE_DOWN, &adapter->state))
6002                 goto watchdog_short_circuit;
6003
6004         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6005                 /*
6006                  * for legacy and MSI interrupts don't set any bits
6007                  * that are enabled for EIAM, because this operation
6008                  * would set *both* EIMS and EICS for any bit in EIAM
6009                  */
6010                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6011                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6012                 goto watchdog_reschedule;
6013         }
6014
6015         /* get one bit for every active tx/rx interrupt vector */
6016         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6017                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
6018                 if (qv->rxr_count || qv->txr_count)
6019                         eics |= ((u64)1 << i);
6020         }
6021
6022         /* Cause software interrupt to ensure rx rings are cleaned */
6023         ixgbe_irq_rearm_queues(adapter, eics);
6024
6025 watchdog_reschedule:
6026         /* Reset the timer */
6027         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
6028
6029 watchdog_short_circuit:
6030         schedule_work(&adapter->watchdog_task);
6031 }
6032
6033 /**
6034  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
6035  * @work: pointer to work_struct containing our data
6036  **/
6037 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
6038 {
6039         struct ixgbe_adapter *adapter = container_of(work,
6040                                                      struct ixgbe_adapter,
6041                                                      multispeed_fiber_task);
6042         struct ixgbe_hw *hw = &adapter->hw;
6043         u32 autoneg;
6044         bool negotiation;
6045
6046         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
6047         autoneg = hw->phy.autoneg_advertised;
6048         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6049                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6050         hw->mac.autotry_restart = false;
6051         if (hw->mac.ops.setup_link)
6052                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6053         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6054         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
6055 }
6056
6057 /**
6058  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
6059  * @work: pointer to work_struct containing our data
6060  **/
6061 static void ixgbe_sfp_config_module_task(struct work_struct *work)
6062 {
6063         struct ixgbe_adapter *adapter = container_of(work,
6064                                                      struct ixgbe_adapter,
6065                                                      sfp_config_module_task);
6066         struct ixgbe_hw *hw = &adapter->hw;
6067         u32 err;
6068
6069         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
6070
6071         /* Time for electrical oscillations to settle down */
6072         msleep(100);
6073         err = hw->phy.ops.identify_sfp(hw);
6074
6075         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6076                 e_dev_err("failed to initialize because an unsupported SFP+ "
6077                           "module type was detected.\n");
6078                 e_dev_err("Reload the driver after installing a supported "
6079                           "module.\n");
6080                 unregister_netdev(adapter->netdev);
6081                 return;
6082         }
6083         if (hw->mac.ops.setup_sfp)
6084                 hw->mac.ops.setup_sfp(hw);
6085
6086         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
6087                 /* This will also work for DA Twinax connections */
6088                 schedule_work(&adapter->multispeed_fiber_task);
6089         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
6090 }
6091
6092 /**
6093  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
6094  * @work: pointer to work_struct containing our data
6095  **/
6096 static void ixgbe_fdir_reinit_task(struct work_struct *work)
6097 {
6098         struct ixgbe_adapter *adapter = container_of(work,
6099                                                      struct ixgbe_adapter,
6100                                                      fdir_reinit_task);
6101         struct ixgbe_hw *hw = &adapter->hw;
6102         int i;
6103
6104         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6105                 for (i = 0; i < adapter->num_tx_queues; i++)
6106                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
6107                                 &(adapter->tx_ring[i]->state));
6108         } else {
6109                 e_err(probe, "failed to finish FDIR re-initialization, "
6110                       "ignored adding FDIR ATR filters\n");
6111         }
6112         /* Done FDIR Re-initialization, enable transmits */
6113         netif_tx_start_all_queues(adapter->netdev);
6114 }
6115
6116 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6117 {
6118         u32 ssvpc;
6119
6120         /* Do not perform spoof check for 82598 */
6121         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6122                 return;
6123
6124         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6125
6126         /*
6127          * ssvpc register is cleared on read, if zero then no
6128          * spoofed packets in the last interval.
6129          */
6130         if (!ssvpc)
6131                 return;
6132
6133         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6134 }
6135
6136 static DEFINE_MUTEX(ixgbe_watchdog_lock);
6137
6138 /**
6139  * ixgbe_watchdog_task - worker thread to bring link up
6140  * @work: pointer to work_struct containing our data
6141  **/
6142 static void ixgbe_watchdog_task(struct work_struct *work)
6143 {
6144         struct ixgbe_adapter *adapter = container_of(work,
6145                                                      struct ixgbe_adapter,
6146                                                      watchdog_task);
6147         struct net_device *netdev = adapter->netdev;
6148         struct ixgbe_hw *hw = &adapter->hw;
6149         u32 link_speed;
6150         bool link_up;
6151         int i;
6152         struct ixgbe_ring *tx_ring;
6153         int some_tx_pending = 0;
6154
6155         mutex_lock(&ixgbe_watchdog_lock);
6156
6157         link_up = adapter->link_up;
6158         link_speed = adapter->link_speed;
6159
6160         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
6161                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6162                 if (link_up) {
6163 #ifdef CONFIG_DCB
6164                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6165                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6166                                         hw->mac.ops.fc_enable(hw, i);
6167                         } else {
6168                                 hw->mac.ops.fc_enable(hw, 0);
6169                         }
6170 #else
6171                         hw->mac.ops.fc_enable(hw, 0);
6172 #endif
6173                 }
6174
6175                 if (link_up ||
6176                     time_after(jiffies, (adapter->link_check_timeout +
6177                                          IXGBE_TRY_LINK_TIMEOUT))) {
6178                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6179                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6180                 }
6181                 adapter->link_up = link_up;
6182                 adapter->link_speed = link_speed;
6183         }
6184
6185         if (link_up) {
6186                 if (!netif_carrier_ok(netdev)) {
6187                         bool flow_rx, flow_tx;
6188
6189                         switch (hw->mac.type) {
6190                         case ixgbe_mac_82598EB: {
6191                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6192                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6193                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6194                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6195                         }
6196                                 break;
6197                         case ixgbe_mac_82599EB:
6198                         case ixgbe_mac_X540: {
6199                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6200                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6201                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6202                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6203                         }
6204                                 break;
6205                         default:
6206                                 flow_tx = false;
6207                                 flow_rx = false;
6208                                 break;
6209                         }
6210
6211                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6212                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6213                                "10 Gbps" :
6214                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6215                                "1 Gbps" :
6216                                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6217                                "100 Mbps" :
6218                                "unknown speed"))),
6219                                ((flow_rx && flow_tx) ? "RX/TX" :
6220                                (flow_rx ? "RX" :
6221                                (flow_tx ? "TX" : "None"))));
6222
6223                         netif_carrier_on(netdev);
6224                         ixgbe_check_vf_rate_limit(adapter);
6225                 } else {
6226                         /* Force detection of hung controller */
6227                         for (i = 0; i < adapter->num_tx_queues; i++) {
6228                                 tx_ring = adapter->tx_ring[i];
6229                                 set_check_for_tx_hang(tx_ring);
6230                         }
6231                 }
6232         } else {
6233                 adapter->link_up = false;
6234                 adapter->link_speed = 0;
6235                 if (netif_carrier_ok(netdev)) {
6236                         e_info(drv, "NIC Link is Down\n");
6237                         netif_carrier_off(netdev);
6238                 }
6239         }
6240
6241         if (!netif_carrier_ok(netdev)) {
6242                 for (i = 0; i < adapter->num_tx_queues; i++) {
6243                         tx_ring = adapter->tx_ring[i];
6244                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6245                                 some_tx_pending = 1;
6246                                 break;
6247                         }
6248                 }
6249
6250                 if (some_tx_pending) {
6251                         /* We've lost link, so the controller stops DMA,
6252                          * but we've got queued Tx work that's never going
6253                          * to get done, so reset controller to flush Tx.
6254                          * (Do the reset outside of interrupt context).
6255                          */
6256                          schedule_work(&adapter->reset_task);
6257                 }
6258         }
6259
6260         ixgbe_spoof_check(adapter);
6261         ixgbe_update_stats(adapter);
6262         mutex_unlock(&ixgbe_watchdog_lock);
6263 }
6264
6265 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6266                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6267                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6268 {
6269         struct ixgbe_adv_tx_context_desc *context_desc;
6270         unsigned int i;
6271         int err;
6272         struct ixgbe_tx_buffer *tx_buffer_info;
6273         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6274         u32 mss_l4len_idx, l4len;
6275
6276         if (skb_is_gso(skb)) {
6277                 if (skb_header_cloned(skb)) {
6278                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6279                         if (err)
6280                                 return err;
6281                 }
6282                 l4len = tcp_hdrlen(skb);
6283                 *hdr_len += l4len;
6284
6285                 if (protocol == htons(ETH_P_IP)) {
6286                         struct iphdr *iph = ip_hdr(skb);
6287                         iph->tot_len = 0;
6288                         iph->check = 0;
6289                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6290                                                                  iph->daddr, 0,
6291                                                                  IPPROTO_TCP,
6292                                                                  0);
6293                 } else if (skb_is_gso_v6(skb)) {
6294                         ipv6_hdr(skb)->payload_len = 0;
6295                         tcp_hdr(skb)->check =
6296                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6297                                              &ipv6_hdr(skb)->daddr,
6298                                              0, IPPROTO_TCP, 0);
6299                 }
6300
6301                 i = tx_ring->next_to_use;
6302
6303                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6304                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6305
6306                 /* VLAN MACLEN IPLEN */
6307                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6308                         vlan_macip_lens |=
6309                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6310                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6311                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6312                 *hdr_len += skb_network_offset(skb);
6313                 vlan_macip_lens |=
6314                     (skb_transport_header(skb) - skb_network_header(skb));
6315                 *hdr_len +=
6316                     (skb_transport_header(skb) - skb_network_header(skb));
6317                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6318                 context_desc->seqnum_seed = 0;
6319
6320                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6321                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6322                                    IXGBE_ADVTXD_DTYP_CTXT);
6323
6324                 if (protocol == htons(ETH_P_IP))
6325                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6326                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6327                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6328
6329                 /* MSS L4LEN IDX */
6330                 mss_l4len_idx =
6331                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6332                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6333                 /* use index 1 for TSO */
6334                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6335                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6336
6337                 tx_buffer_info->time_stamp = jiffies;
6338                 tx_buffer_info->next_to_watch = i;
6339
6340                 i++;
6341                 if (i == tx_ring->count)
6342                         i = 0;
6343                 tx_ring->next_to_use = i;
6344
6345                 return true;
6346         }
6347         return false;
6348 }
6349
6350 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6351                       __be16 protocol)
6352 {
6353         u32 rtn = 0;
6354
6355         switch (protocol) {
6356         case cpu_to_be16(ETH_P_IP):
6357                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6358                 switch (ip_hdr(skb)->protocol) {
6359                 case IPPROTO_TCP:
6360                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6361                         break;
6362                 case IPPROTO_SCTP:
6363                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6364                         break;
6365                 }
6366                 break;
6367         case cpu_to_be16(ETH_P_IPV6):
6368                 /* XXX what about other V6 headers?? */
6369                 switch (ipv6_hdr(skb)->nexthdr) {
6370                 case IPPROTO_TCP:
6371                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6372                         break;
6373                 case IPPROTO_SCTP:
6374                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6375                         break;
6376                 }
6377                 break;
6378         default:
6379                 if (unlikely(net_ratelimit()))
6380                         e_warn(probe, "partial checksum but proto=%x!\n",
6381                                protocol);
6382                 break;
6383         }
6384
6385         return rtn;
6386 }
6387
6388 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6389                           struct ixgbe_ring *tx_ring,
6390                           struct sk_buff *skb, u32 tx_flags,
6391                           __be16 protocol)
6392 {
6393         struct ixgbe_adv_tx_context_desc *context_desc;
6394         unsigned int i;
6395         struct ixgbe_tx_buffer *tx_buffer_info;
6396         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6397
6398         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6399             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6400                 i = tx_ring->next_to_use;
6401                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6402                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6403
6404                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6405                         vlan_macip_lens |=
6406                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6407                 vlan_macip_lens |= (skb_network_offset(skb) <<
6408                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6409                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6410                         vlan_macip_lens |= (skb_transport_header(skb) -
6411                                             skb_network_header(skb));
6412
6413                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6414                 context_desc->seqnum_seed = 0;
6415
6416                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6417                                     IXGBE_ADVTXD_DTYP_CTXT);
6418
6419                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6420                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6421
6422                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6423                 /* use index zero for tx checksum offload */
6424                 context_desc->mss_l4len_idx = 0;
6425
6426                 tx_buffer_info->time_stamp = jiffies;
6427                 tx_buffer_info->next_to_watch = i;
6428
6429                 i++;
6430                 if (i == tx_ring->count)
6431                         i = 0;
6432                 tx_ring->next_to_use = i;
6433
6434                 return true;
6435         }
6436
6437         return false;
6438 }
6439
6440 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6441                         struct ixgbe_ring *tx_ring,
6442                         struct sk_buff *skb, u32 tx_flags,
6443                         unsigned int first, const u8 hdr_len)
6444 {
6445         struct device *dev = tx_ring->dev;
6446         struct ixgbe_tx_buffer *tx_buffer_info;
6447         unsigned int len;
6448         unsigned int total = skb->len;
6449         unsigned int offset = 0, size, count = 0, i;
6450         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6451         unsigned int f;
6452         unsigned int bytecount = skb->len;
6453         u16 gso_segs = 1;
6454
6455         i = tx_ring->next_to_use;
6456
6457         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6458                 /* excluding fcoe_crc_eof for FCoE */
6459                 total -= sizeof(struct fcoe_crc_eof);
6460
6461         len = min(skb_headlen(skb), total);
6462         while (len) {
6463                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6464                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6465
6466                 tx_buffer_info->length = size;
6467                 tx_buffer_info->mapped_as_page = false;
6468                 tx_buffer_info->dma = dma_map_single(dev,
6469                                                      skb->data + offset,
6470                                                      size, DMA_TO_DEVICE);
6471                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6472                         goto dma_error;
6473                 tx_buffer_info->time_stamp = jiffies;
6474                 tx_buffer_info->next_to_watch = i;
6475
6476                 len -= size;
6477                 total -= size;
6478                 offset += size;
6479                 count++;
6480
6481                 if (len) {
6482                         i++;
6483                         if (i == tx_ring->count)
6484                                 i = 0;
6485                 }
6486         }
6487
6488         for (f = 0; f < nr_frags; f++) {
6489                 struct skb_frag_struct *frag;
6490
6491                 frag = &skb_shinfo(skb)->frags[f];
6492                 len = min((unsigned int)frag->size, total);
6493                 offset = frag->page_offset;
6494
6495                 while (len) {
6496                         i++;
6497                         if (i == tx_ring->count)
6498                                 i = 0;
6499
6500                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6501                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6502
6503                         tx_buffer_info->length = size;
6504                         tx_buffer_info->dma = dma_map_page(dev,
6505                                                            frag->page,
6506                                                            offset, size,
6507                                                            DMA_TO_DEVICE);
6508                         tx_buffer_info->mapped_as_page = true;
6509                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6510                                 goto dma_error;
6511                         tx_buffer_info->time_stamp = jiffies;
6512                         tx_buffer_info->next_to_watch = i;
6513
6514                         len -= size;
6515                         total -= size;
6516                         offset += size;
6517                         count++;
6518                 }
6519                 if (total == 0)
6520                         break;
6521         }
6522
6523         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6524                 gso_segs = skb_shinfo(skb)->gso_segs;
6525 #ifdef IXGBE_FCOE
6526         /* adjust for FCoE Sequence Offload */
6527         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6528                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6529                                         skb_shinfo(skb)->gso_size);
6530 #endif /* IXGBE_FCOE */
6531         bytecount += (gso_segs - 1) * hdr_len;
6532
6533         /* multiply data chunks by size of headers */
6534         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6535         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6536         tx_ring->tx_buffer_info[i].skb = skb;
6537         tx_ring->tx_buffer_info[first].next_to_watch = i;
6538
6539         return count;
6540
6541 dma_error:
6542         e_dev_err("TX DMA map failed\n");
6543
6544         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6545         tx_buffer_info->dma = 0;
6546         tx_buffer_info->time_stamp = 0;
6547         tx_buffer_info->next_to_watch = 0;
6548         if (count)
6549                 count--;
6550
6551         /* clear timestamp and dma mappings for remaining portion of packet */
6552         while (count--) {
6553                 if (i == 0)
6554                         i += tx_ring->count;
6555                 i--;
6556                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6557                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6558         }
6559
6560         return 0;
6561 }
6562
6563 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6564                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6565 {
6566         union ixgbe_adv_tx_desc *tx_desc = NULL;
6567         struct ixgbe_tx_buffer *tx_buffer_info;
6568         u32 olinfo_status = 0, cmd_type_len = 0;
6569         unsigned int i;
6570         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6571
6572         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6573
6574         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6575
6576         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6577                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6578
6579         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6580                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6581
6582                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6583                                  IXGBE_ADVTXD_POPTS_SHIFT;
6584
6585                 /* use index 1 context for tso */
6586                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6587                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6588                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6589                                          IXGBE_ADVTXD_POPTS_SHIFT;
6590
6591         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6592                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6593                                  IXGBE_ADVTXD_POPTS_SHIFT;
6594
6595         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6596                 olinfo_status |= IXGBE_ADVTXD_CC;
6597                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6598                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6599                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6600         }
6601
6602         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6603
6604         i = tx_ring->next_to_use;
6605         while (count--) {
6606                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6607                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6608                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6609                 tx_desc->read.cmd_type_len =
6610                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6611                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6612                 i++;
6613                 if (i == tx_ring->count)
6614                         i = 0;
6615         }
6616
6617         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6618
6619         /*
6620          * Force memory writes to complete before letting h/w
6621          * know there are new descriptors to fetch.  (Only
6622          * applicable for weak-ordered memory model archs,
6623          * such as IA-64).
6624          */
6625         wmb();
6626
6627         tx_ring->next_to_use = i;
6628         writel(i, tx_ring->tail);
6629 }
6630
6631 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6632                       u32 tx_flags, __be16 protocol)
6633 {
6634         struct ixgbe_q_vector *q_vector = ring->q_vector;
6635         union ixgbe_atr_hash_dword input = { .dword = 0 };
6636         union ixgbe_atr_hash_dword common = { .dword = 0 };
6637         union {
6638                 unsigned char *network;
6639                 struct iphdr *ipv4;
6640                 struct ipv6hdr *ipv6;
6641         } hdr;
6642         struct tcphdr *th;
6643         __be16 vlan_id;
6644
6645         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6646         if (!q_vector)
6647                 return;
6648
6649         /* do nothing if sampling is disabled */
6650         if (!ring->atr_sample_rate)
6651                 return;
6652
6653         ring->atr_count++;
6654
6655         /* snag network header to get L4 type and address */
6656         hdr.network = skb_network_header(skb);
6657
6658         /* Currently only IPv4/IPv6 with TCP is supported */
6659         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6660              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6661             (protocol != __constant_htons(ETH_P_IP) ||
6662              hdr.ipv4->protocol != IPPROTO_TCP))
6663                 return;
6664
6665         th = tcp_hdr(skb);
6666
6667         /* skip this packet since the socket is closing */
6668         if (th->fin)
6669                 return;
6670
6671         /* sample on all syn packets or once every atr sample count */
6672         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6673                 return;
6674
6675         /* reset sample count */
6676         ring->atr_count = 0;
6677
6678         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6679
6680         /*
6681          * src and dst are inverted, think how the receiver sees them
6682          *
6683          * The input is broken into two sections, a non-compressed section
6684          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6685          * is XORed together and stored in the compressed dword.
6686          */
6687         input.formatted.vlan_id = vlan_id;
6688
6689         /*
6690          * since src port and flex bytes occupy the same word XOR them together
6691          * and write the value to source port portion of compressed dword
6692          */
6693         if (vlan_id)
6694                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6695         else
6696                 common.port.src ^= th->dest ^ protocol;
6697         common.port.dst ^= th->source;
6698
6699         if (protocol == __constant_htons(ETH_P_IP)) {
6700                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6701                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6702         } else {
6703                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6704                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6705                              hdr.ipv6->saddr.s6_addr32[1] ^
6706                              hdr.ipv6->saddr.s6_addr32[2] ^
6707                              hdr.ipv6->saddr.s6_addr32[3] ^
6708                              hdr.ipv6->daddr.s6_addr32[0] ^
6709                              hdr.ipv6->daddr.s6_addr32[1] ^
6710                              hdr.ipv6->daddr.s6_addr32[2] ^
6711                              hdr.ipv6->daddr.s6_addr32[3];
6712         }
6713
6714         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6715         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6716                                               input, common, ring->queue_index);
6717 }
6718
6719 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6720 {
6721         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6722         /* Herbert's original patch had:
6723          *  smp_mb__after_netif_stop_queue();
6724          * but since that doesn't exist yet, just open code it. */
6725         smp_mb();
6726
6727         /* We need to check again in a case another CPU has just
6728          * made room available. */
6729         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6730                 return -EBUSY;
6731
6732         /* A reprieve! - use start_queue because it doesn't call schedule */
6733         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6734         ++tx_ring->tx_stats.restart_queue;
6735         return 0;
6736 }
6737
6738 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6739 {
6740         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6741                 return 0;
6742         return __ixgbe_maybe_stop_tx(tx_ring, size);
6743 }
6744
6745 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6746 {
6747         struct ixgbe_adapter *adapter = netdev_priv(dev);
6748         int txq = smp_processor_id();
6749 #ifdef IXGBE_FCOE
6750         __be16 protocol;
6751
6752         protocol = vlan_get_protocol(skb);
6753
6754         if (((protocol == htons(ETH_P_FCOE)) ||
6755             (protocol == htons(ETH_P_FIP))) &&
6756             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6757                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6758                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6759                 return txq;
6760         }
6761 #endif
6762
6763         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6764                 while (unlikely(txq >= dev->real_num_tx_queues))
6765                         txq -= dev->real_num_tx_queues;
6766                 return txq;
6767         }
6768
6769         return skb_tx_hash(dev, skb);
6770 }
6771
6772 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6773                           struct ixgbe_adapter *adapter,
6774                           struct ixgbe_ring *tx_ring)
6775 {
6776         unsigned int first;
6777         unsigned int tx_flags = 0;
6778         u8 hdr_len = 0;
6779         int tso;
6780         int count = 0;
6781         unsigned int f;
6782         __be16 protocol;
6783
6784         protocol = vlan_get_protocol(skb);
6785
6786         if (vlan_tx_tag_present(skb)) {
6787                 tx_flags |= vlan_tx_tag_get(skb);
6788                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6789                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6790                         tx_flags |= tx_ring->dcb_tc << 13;
6791                 }
6792                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6793                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6794         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6795                    skb->priority != TC_PRIO_CONTROL) {
6796                 tx_flags |= tx_ring->dcb_tc << 13;
6797                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6798                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6799         }
6800
6801 #ifdef IXGBE_FCOE
6802         /* for FCoE with DCB, we force the priority to what
6803          * was specified by the switch */
6804         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6805             (protocol == htons(ETH_P_FCOE)))
6806                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6807 #endif
6808
6809         /* four things can cause us to need a context descriptor */
6810         if (skb_is_gso(skb) ||
6811             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6812             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6813             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6814                 count++;
6815
6816         count += TXD_USE_COUNT(skb_headlen(skb));
6817         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6818                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6819
6820         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6821                 tx_ring->tx_stats.tx_busy++;
6822                 return NETDEV_TX_BUSY;
6823         }
6824
6825         first = tx_ring->next_to_use;
6826         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6827 #ifdef IXGBE_FCOE
6828                 /* setup tx offload for FCoE */
6829                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6830                 if (tso < 0) {
6831                         dev_kfree_skb_any(skb);
6832                         return NETDEV_TX_OK;
6833                 }
6834                 if (tso)
6835                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6836 #endif /* IXGBE_FCOE */
6837         } else {
6838                 if (protocol == htons(ETH_P_IP))
6839                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6840                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6841                                 protocol);
6842                 if (tso < 0) {
6843                         dev_kfree_skb_any(skb);
6844                         return NETDEV_TX_OK;
6845                 }
6846
6847                 if (tso)
6848                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6849                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6850                                        protocol) &&
6851                          (skb->ip_summed == CHECKSUM_PARTIAL))
6852                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6853         }
6854
6855         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6856         if (count) {
6857                 /* add the ATR filter if ATR is on */
6858                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6859                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6860                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6861                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6862
6863         } else {
6864                 dev_kfree_skb_any(skb);
6865                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6866                 tx_ring->next_to_use = first;
6867         }
6868
6869         return NETDEV_TX_OK;
6870 }
6871
6872 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6873 {
6874         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6875         struct ixgbe_ring *tx_ring;
6876
6877         tx_ring = adapter->tx_ring[skb->queue_mapping];
6878         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6879 }
6880
6881 /**
6882  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6883  * @netdev: network interface device structure
6884  * @p: pointer to an address structure
6885  *
6886  * Returns 0 on success, negative on failure
6887  **/
6888 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6889 {
6890         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6891         struct ixgbe_hw *hw = &adapter->hw;
6892         struct sockaddr *addr = p;
6893
6894         if (!is_valid_ether_addr(addr->sa_data))
6895                 return -EADDRNOTAVAIL;
6896
6897         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6898         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6899
6900         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6901                             IXGBE_RAH_AV);
6902
6903         return 0;
6904 }
6905
6906 static int
6907 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6908 {
6909         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6910         struct ixgbe_hw *hw = &adapter->hw;
6911         u16 value;
6912         int rc;
6913
6914         if (prtad != hw->phy.mdio.prtad)
6915                 return -EINVAL;
6916         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6917         if (!rc)
6918                 rc = value;
6919         return rc;
6920 }
6921
6922 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6923                             u16 addr, u16 value)
6924 {
6925         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926         struct ixgbe_hw *hw = &adapter->hw;
6927
6928         if (prtad != hw->phy.mdio.prtad)
6929                 return -EINVAL;
6930         return hw->phy.ops.write_reg(hw, addr, devad, value);
6931 }
6932
6933 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6934 {
6935         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6936
6937         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6938 }
6939
6940 /**
6941  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6942  * netdev->dev_addrs
6943  * @netdev: network interface device structure
6944  *
6945  * Returns non-zero on failure
6946  **/
6947 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6948 {
6949         int err = 0;
6950         struct ixgbe_adapter *adapter = netdev_priv(dev);
6951         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6952
6953         if (is_valid_ether_addr(mac->san_addr)) {
6954                 rtnl_lock();
6955                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6956                 rtnl_unlock();
6957         }
6958         return err;
6959 }
6960
6961 /**
6962  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6963  * netdev->dev_addrs
6964  * @netdev: network interface device structure
6965  *
6966  * Returns non-zero on failure
6967  **/
6968 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6969 {
6970         int err = 0;
6971         struct ixgbe_adapter *adapter = netdev_priv(dev);
6972         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6973
6974         if (is_valid_ether_addr(mac->san_addr)) {
6975                 rtnl_lock();
6976                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6977                 rtnl_unlock();
6978         }
6979         return err;
6980 }
6981
6982 #ifdef CONFIG_NET_POLL_CONTROLLER
6983 /*
6984  * Polling 'interrupt' - used by things like netconsole to send skbs
6985  * without having to re-enable interrupts. It's not called while
6986  * the interrupt routine is executing.
6987  */
6988 static void ixgbe_netpoll(struct net_device *netdev)
6989 {
6990         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6991         int i;
6992
6993         /* if interface is down do nothing */
6994         if (test_bit(__IXGBE_DOWN, &adapter->state))
6995                 return;
6996
6997         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6998         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6999                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7000                 for (i = 0; i < num_q_vectors; i++) {
7001                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7002                         ixgbe_msix_clean_many(0, q_vector);
7003                 }
7004         } else {
7005                 ixgbe_intr(adapter->pdev->irq, netdev);
7006         }
7007         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7008 }
7009 #endif
7010
7011 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7012                                                    struct rtnl_link_stats64 *stats)
7013 {
7014         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7015         int i;
7016
7017         rcu_read_lock();
7018         for (i = 0; i < adapter->num_rx_queues; i++) {
7019                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7020                 u64 bytes, packets;
7021                 unsigned int start;
7022
7023                 if (ring) {
7024                         do {
7025                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7026                                 packets = ring->stats.packets;
7027                                 bytes   = ring->stats.bytes;
7028                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7029                         stats->rx_packets += packets;
7030                         stats->rx_bytes   += bytes;
7031                 }
7032         }
7033
7034         for (i = 0; i < adapter->num_tx_queues; i++) {
7035                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7036                 u64 bytes, packets;
7037                 unsigned int start;
7038
7039                 if (ring) {
7040                         do {
7041                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7042                                 packets = ring->stats.packets;
7043                                 bytes   = ring->stats.bytes;
7044                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7045                         stats->tx_packets += packets;
7046                         stats->tx_bytes   += bytes;
7047                 }
7048         }
7049         rcu_read_unlock();
7050         /* following stats updated by ixgbe_watchdog_task() */
7051         stats->multicast        = netdev->stats.multicast;
7052         stats->rx_errors        = netdev->stats.rx_errors;
7053         stats->rx_length_errors = netdev->stats.rx_length_errors;
7054         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7055         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7056         return stats;
7057 }
7058
7059
7060 static const struct net_device_ops ixgbe_netdev_ops = {
7061         .ndo_open               = ixgbe_open,
7062         .ndo_stop               = ixgbe_close,
7063         .ndo_start_xmit         = ixgbe_xmit_frame,
7064         .ndo_select_queue       = ixgbe_select_queue,
7065         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7066         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7067         .ndo_validate_addr      = eth_validate_addr,
7068         .ndo_set_mac_address    = ixgbe_set_mac,
7069         .ndo_change_mtu         = ixgbe_change_mtu,
7070         .ndo_tx_timeout         = ixgbe_tx_timeout,
7071         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7072         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7073         .ndo_do_ioctl           = ixgbe_ioctl,
7074         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7075         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7076         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7077         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7078         .ndo_get_stats64        = ixgbe_get_stats64,
7079 #ifdef CONFIG_IXGBE_DCB
7080         .ndo_setup_tc           = ixgbe_setup_tc,
7081 #endif
7082 #ifdef CONFIG_NET_POLL_CONTROLLER
7083         .ndo_poll_controller    = ixgbe_netpoll,
7084 #endif
7085 #ifdef IXGBE_FCOE
7086         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7087         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7088         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7089         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7090         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7091         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7092 #endif /* IXGBE_FCOE */
7093 };
7094
7095 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7096                            const struct ixgbe_info *ii)
7097 {
7098 #ifdef CONFIG_PCI_IOV
7099         struct ixgbe_hw *hw = &adapter->hw;
7100         int err;
7101
7102         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7103                 return;
7104
7105         /* The 82599 supports up to 64 VFs per physical function
7106          * but this implementation limits allocation to 63 so that
7107          * basic networking resources are still available to the
7108          * physical function
7109          */
7110         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7111         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7112         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7113         if (err) {
7114                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7115                 goto err_novfs;
7116         }
7117         /* If call to enable VFs succeeded then allocate memory
7118          * for per VF control structures.
7119          */
7120         adapter->vfinfo =
7121                 kcalloc(adapter->num_vfs,
7122                         sizeof(struct vf_data_storage), GFP_KERNEL);
7123         if (adapter->vfinfo) {
7124                 /* Now that we're sure SR-IOV is enabled
7125                  * and memory allocated set up the mailbox parameters
7126                  */
7127                 ixgbe_init_mbx_params_pf(hw);
7128                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7129                        sizeof(hw->mbx.ops));
7130
7131                 /* Disable RSC when in SR-IOV mode */
7132                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7133                                      IXGBE_FLAG2_RSC_ENABLED);
7134                 return;
7135         }
7136
7137         /* Oh oh */
7138         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7139               "SRIOV disabled\n");
7140         pci_disable_sriov(adapter->pdev);
7141
7142 err_novfs:
7143         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7144         adapter->num_vfs = 0;
7145 #endif /* CONFIG_PCI_IOV */
7146 }
7147
7148 /**
7149  * ixgbe_probe - Device Initialization Routine
7150  * @pdev: PCI device information struct
7151  * @ent: entry in ixgbe_pci_tbl
7152  *
7153  * Returns 0 on success, negative on failure
7154  *
7155  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7156  * The OS initialization, configuring of the adapter private structure,
7157  * and a hardware reset occur.
7158  **/
7159 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7160                                  const struct pci_device_id *ent)
7161 {
7162         struct net_device *netdev;
7163         struct ixgbe_adapter *adapter = NULL;
7164         struct ixgbe_hw *hw;
7165         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7166         static int cards_found;
7167         int i, err, pci_using_dac;
7168         u8 part_str[IXGBE_PBANUM_LENGTH];
7169         unsigned int indices = num_possible_cpus();
7170 #ifdef IXGBE_FCOE
7171         u16 device_caps;
7172 #endif
7173         u32 eec;
7174
7175         /* Catch broken hardware that put the wrong VF device ID in
7176          * the PCIe SR-IOV capability.
7177          */
7178         if (pdev->is_virtfn) {
7179                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7180                      pci_name(pdev), pdev->vendor, pdev->device);
7181                 return -EINVAL;
7182         }
7183
7184         err = pci_enable_device_mem(pdev);
7185         if (err)
7186                 return err;
7187
7188         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7189             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7190                 pci_using_dac = 1;
7191         } else {
7192                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7193                 if (err) {
7194                         err = dma_set_coherent_mask(&pdev->dev,
7195                                                     DMA_BIT_MASK(32));
7196                         if (err) {
7197                                 dev_err(&pdev->dev,
7198                                         "No usable DMA configuration, aborting\n");
7199                                 goto err_dma;
7200                         }
7201                 }
7202                 pci_using_dac = 0;
7203         }
7204
7205         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7206                                            IORESOURCE_MEM), ixgbe_driver_name);
7207         if (err) {
7208                 dev_err(&pdev->dev,
7209                         "pci_request_selected_regions failed 0x%x\n", err);
7210                 goto err_pci_reg;
7211         }
7212
7213         pci_enable_pcie_error_reporting(pdev);
7214
7215         pci_set_master(pdev);
7216         pci_save_state(pdev);
7217
7218         if (ii->mac == ixgbe_mac_82598EB)
7219                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7220         else
7221                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7222
7223 #if defined(CONFIG_DCB)
7224         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7225 #elif defined(IXGBE_FCOE)
7226         indices += min_t(unsigned int, num_possible_cpus(),
7227                          IXGBE_MAX_FCOE_INDICES);
7228 #endif
7229         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7230         if (!netdev) {
7231                 err = -ENOMEM;
7232                 goto err_alloc_etherdev;
7233         }
7234
7235         SET_NETDEV_DEV(netdev, &pdev->dev);
7236
7237         adapter = netdev_priv(netdev);
7238         pci_set_drvdata(pdev, adapter);
7239
7240         adapter->netdev = netdev;
7241         adapter->pdev = pdev;
7242         hw = &adapter->hw;
7243         hw->back = adapter;
7244         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7245
7246         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7247                               pci_resource_len(pdev, 0));
7248         if (!hw->hw_addr) {
7249                 err = -EIO;
7250                 goto err_ioremap;
7251         }
7252
7253         for (i = 1; i <= 5; i++) {
7254                 if (pci_resource_len(pdev, i) == 0)
7255                         continue;
7256         }
7257
7258         netdev->netdev_ops = &ixgbe_netdev_ops;
7259         ixgbe_set_ethtool_ops(netdev);
7260         netdev->watchdog_timeo = 5 * HZ;
7261         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7262
7263         adapter->bd_number = cards_found;
7264
7265         /* Setup hw api */
7266         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7267         hw->mac.type  = ii->mac;
7268
7269         /* EEPROM */
7270         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7271         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7272         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7273         if (!(eec & (1 << 8)))
7274                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7275
7276         /* PHY */
7277         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7278         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7279         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7280         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7281         hw->phy.mdio.mmds = 0;
7282         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7283         hw->phy.mdio.dev = netdev;
7284         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7285         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7286
7287         /* set up this timer and work struct before calling get_invariants
7288          * which might start the timer
7289          */
7290         init_timer(&adapter->sfp_timer);
7291         adapter->sfp_timer.function = ixgbe_sfp_timer;
7292         adapter->sfp_timer.data = (unsigned long) adapter;
7293
7294         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7295
7296         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7297         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7298
7299         /* a new SFP+ module arrival, called from GPI SDP2 context */
7300         INIT_WORK(&adapter->sfp_config_module_task,
7301                   ixgbe_sfp_config_module_task);
7302
7303         ii->get_invariants(hw);
7304
7305         /* setup the private structure */
7306         err = ixgbe_sw_init(adapter);
7307         if (err)
7308                 goto err_sw_init;
7309
7310         /* Make it possible the adapter to be woken up via WOL */
7311         switch (adapter->hw.mac.type) {
7312         case ixgbe_mac_82599EB:
7313         case ixgbe_mac_X540:
7314                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7315                 break;
7316         default:
7317                 break;
7318         }
7319
7320         /*
7321          * If there is a fan on this device and it has failed log the
7322          * failure.
7323          */
7324         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7325                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7326                 if (esdp & IXGBE_ESDP_SDP1)
7327                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7328         }
7329
7330         /* reset_hw fills in the perm_addr as well */
7331         hw->phy.reset_if_overtemp = true;
7332         err = hw->mac.ops.reset_hw(hw);
7333         hw->phy.reset_if_overtemp = false;
7334         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7335             hw->mac.type == ixgbe_mac_82598EB) {
7336                 /*
7337                  * Start a kernel thread to watch for a module to arrive.
7338                  * Only do this for 82598, since 82599 will generate
7339                  * interrupts on module arrival.
7340                  */
7341                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7342                 mod_timer(&adapter->sfp_timer,
7343                           round_jiffies(jiffies + (2 * HZ)));
7344                 err = 0;
7345         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7346                 e_dev_err("failed to initialize because an unsupported SFP+ "
7347                           "module type was detected.\n");
7348                 e_dev_err("Reload the driver after installing a supported "
7349                           "module.\n");
7350                 goto err_sw_init;
7351         } else if (err) {
7352                 e_dev_err("HW Init failed: %d\n", err);
7353                 goto err_sw_init;
7354         }
7355
7356         ixgbe_probe_vf(adapter, ii);
7357
7358         netdev->features = NETIF_F_SG |
7359                            NETIF_F_IP_CSUM |
7360                            NETIF_F_HW_VLAN_TX |
7361                            NETIF_F_HW_VLAN_RX |
7362                            NETIF_F_HW_VLAN_FILTER;
7363
7364         netdev->features |= NETIF_F_IPV6_CSUM;
7365         netdev->features |= NETIF_F_TSO;
7366         netdev->features |= NETIF_F_TSO6;
7367         netdev->features |= NETIF_F_GRO;
7368
7369         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7370                 netdev->features |= NETIF_F_SCTP_CSUM;
7371
7372         netdev->vlan_features |= NETIF_F_TSO;
7373         netdev->vlan_features |= NETIF_F_TSO6;
7374         netdev->vlan_features |= NETIF_F_IP_CSUM;
7375         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7376         netdev->vlan_features |= NETIF_F_SG;
7377
7378         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7379                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7380                                     IXGBE_FLAG_DCB_ENABLED);
7381
7382 #ifdef CONFIG_IXGBE_DCB
7383         netdev->dcbnl_ops = &dcbnl_ops;
7384 #endif
7385
7386 #ifdef IXGBE_FCOE
7387         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7388                 if (hw->mac.ops.get_device_caps) {
7389                         hw->mac.ops.get_device_caps(hw, &device_caps);
7390                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7391                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7392                 }
7393         }
7394         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7395                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7396                 netdev->vlan_features |= NETIF_F_FSO;
7397                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7398         }
7399 #endif /* IXGBE_FCOE */
7400         if (pci_using_dac) {
7401                 netdev->features |= NETIF_F_HIGHDMA;
7402                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7403         }
7404
7405         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7406                 netdev->features |= NETIF_F_LRO;
7407
7408         /* make sure the EEPROM is good */
7409         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7410                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7411                 err = -EIO;
7412                 goto err_eeprom;
7413         }
7414
7415         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7416         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7417
7418         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7419                 e_dev_err("invalid MAC address\n");
7420                 err = -EIO;
7421                 goto err_eeprom;
7422         }
7423
7424         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7425         if (hw->mac.ops.disable_tx_laser &&
7426             ((hw->phy.multispeed_fiber) ||
7427              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7428               (hw->mac.type == ixgbe_mac_82599EB))))
7429                 hw->mac.ops.disable_tx_laser(hw);
7430
7431         init_timer(&adapter->watchdog_timer);
7432         adapter->watchdog_timer.function = ixgbe_watchdog;
7433         adapter->watchdog_timer.data = (unsigned long)adapter;
7434
7435         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7436         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7437
7438         err = ixgbe_init_interrupt_scheme(adapter);
7439         if (err)
7440                 goto err_sw_init;
7441
7442         switch (pdev->device) {
7443         case IXGBE_DEV_ID_82599_SFP:
7444                 /* Only this subdevice supports WOL */
7445                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7446                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7447                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7448                 break;
7449         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7450                 /* All except this subdevice support WOL */
7451                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7452                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7453                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7454                 break;
7455         case IXGBE_DEV_ID_82599_KX4:
7456                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7457                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7458                 break;
7459         default:
7460                 adapter->wol = 0;
7461                 break;
7462         }
7463         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7464
7465         /* pick up the PCI bus settings for reporting later */
7466         hw->mac.ops.get_bus_info(hw);
7467
7468         /* print bus type/speed/width info */
7469         e_dev_info("(PCI Express:%s:%s) %pM\n",
7470                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7471                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7472                     "Unknown"),
7473                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7474                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7475                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7476                     "Unknown"),
7477                    netdev->dev_addr);
7478
7479         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7480         if (err)
7481                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7482         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7483                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7484                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7485                            part_str);
7486         else
7487                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7488                            hw->mac.type, hw->phy.type, part_str);
7489
7490         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7491                 e_dev_warn("PCI-Express bandwidth available for this card is "
7492                            "not sufficient for optimal performance.\n");
7493                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7494                            "is required.\n");
7495         }
7496
7497         /* save off EEPROM version number */
7498         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7499
7500         /* reset the hardware with the new settings */
7501         err = hw->mac.ops.start_hw(hw);
7502
7503         if (err == IXGBE_ERR_EEPROM_VERSION) {
7504                 /* We are running on a pre-production device, log a warning */
7505                 e_dev_warn("This device is a pre-production adapter/LOM. "
7506                            "Please be aware there may be issues associated "
7507                            "with your hardware.  If you are experiencing "
7508                            "problems please contact your Intel or hardware "
7509                            "representative who provided you with this "
7510                            "hardware.\n");
7511         }
7512         strcpy(netdev->name, "eth%d");
7513         err = register_netdev(netdev);
7514         if (err)
7515                 goto err_register;
7516
7517         /* carrier off reporting is important to ethtool even BEFORE open */
7518         netif_carrier_off(netdev);
7519
7520         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7521             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7522                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7523
7524         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7525                 INIT_WORK(&adapter->check_overtemp_task,
7526                           ixgbe_check_overtemp_task);
7527 #ifdef CONFIG_IXGBE_DCA
7528         if (dca_add_requester(&pdev->dev) == 0) {
7529                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7530                 ixgbe_setup_dca(adapter);
7531         }
7532 #endif
7533         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7534                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7535                 for (i = 0; i < adapter->num_vfs; i++)
7536                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7537         }
7538
7539         /* add san mac addr to netdev */
7540         ixgbe_add_sanmac_netdev(netdev);
7541
7542         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7543         cards_found++;
7544         return 0;
7545
7546 err_register:
7547         ixgbe_release_hw_control(adapter);
7548         ixgbe_clear_interrupt_scheme(adapter);
7549 err_sw_init:
7550 err_eeprom:
7551         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7552                 ixgbe_disable_sriov(adapter);
7553         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7554         del_timer_sync(&adapter->sfp_timer);
7555         cancel_work_sync(&adapter->sfp_task);
7556         cancel_work_sync(&adapter->multispeed_fiber_task);
7557         cancel_work_sync(&adapter->sfp_config_module_task);
7558         iounmap(hw->hw_addr);
7559 err_ioremap:
7560         free_netdev(netdev);
7561 err_alloc_etherdev:
7562         pci_release_selected_regions(pdev,
7563                                      pci_select_bars(pdev, IORESOURCE_MEM));
7564 err_pci_reg:
7565 err_dma:
7566         pci_disable_device(pdev);
7567         return err;
7568 }
7569
7570 /**
7571  * ixgbe_remove - Device Removal Routine
7572  * @pdev: PCI device information struct
7573  *
7574  * ixgbe_remove is called by the PCI subsystem to alert the driver
7575  * that it should release a PCI device.  The could be caused by a
7576  * Hot-Plug event, or because the driver is going to be removed from
7577  * memory.
7578  **/
7579 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7580 {
7581         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7582         struct net_device *netdev = adapter->netdev;
7583
7584         set_bit(__IXGBE_DOWN, &adapter->state);
7585
7586         /*
7587          * The timers may be rescheduled, so explicitly disable them
7588          * from being rescheduled.
7589          */
7590         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7591         del_timer_sync(&adapter->watchdog_timer);
7592         del_timer_sync(&adapter->sfp_timer);
7593
7594         cancel_work_sync(&adapter->watchdog_task);
7595         cancel_work_sync(&adapter->sfp_task);
7596         cancel_work_sync(&adapter->multispeed_fiber_task);
7597         cancel_work_sync(&adapter->sfp_config_module_task);
7598         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7599             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7600                 cancel_work_sync(&adapter->fdir_reinit_task);
7601         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7602                 cancel_work_sync(&adapter->check_overtemp_task);
7603
7604 #ifdef CONFIG_IXGBE_DCA
7605         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7606                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7607                 dca_remove_requester(&pdev->dev);
7608                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7609         }
7610
7611 #endif
7612 #ifdef IXGBE_FCOE
7613         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7614                 ixgbe_cleanup_fcoe(adapter);
7615
7616 #endif /* IXGBE_FCOE */
7617
7618         /* remove the added san mac */
7619         ixgbe_del_sanmac_netdev(netdev);
7620
7621         if (netdev->reg_state == NETREG_REGISTERED)
7622                 unregister_netdev(netdev);
7623
7624         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7625                 ixgbe_disable_sriov(adapter);
7626
7627         ixgbe_clear_interrupt_scheme(adapter);
7628
7629         ixgbe_release_hw_control(adapter);
7630
7631         iounmap(adapter->hw.hw_addr);
7632         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7633                                      IORESOURCE_MEM));
7634
7635         e_dev_info("complete\n");
7636
7637         free_netdev(netdev);
7638
7639         pci_disable_pcie_error_reporting(pdev);
7640
7641         pci_disable_device(pdev);
7642 }
7643
7644 /**
7645  * ixgbe_io_error_detected - called when PCI error is detected
7646  * @pdev: Pointer to PCI device
7647  * @state: The current pci connection state
7648  *
7649  * This function is called after a PCI bus error affecting
7650  * this device has been detected.
7651  */
7652 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7653                                                 pci_channel_state_t state)
7654 {
7655         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7656         struct net_device *netdev = adapter->netdev;
7657
7658         netif_device_detach(netdev);
7659
7660         if (state == pci_channel_io_perm_failure)
7661                 return PCI_ERS_RESULT_DISCONNECT;
7662
7663         if (netif_running(netdev))
7664                 ixgbe_down(adapter);
7665         pci_disable_device(pdev);
7666
7667         /* Request a slot reset. */
7668         return PCI_ERS_RESULT_NEED_RESET;
7669 }
7670
7671 /**
7672  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7673  * @pdev: Pointer to PCI device
7674  *
7675  * Restart the card from scratch, as if from a cold-boot.
7676  */
7677 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7678 {
7679         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7680         pci_ers_result_t result;
7681         int err;
7682
7683         if (pci_enable_device_mem(pdev)) {
7684                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7685                 result = PCI_ERS_RESULT_DISCONNECT;
7686         } else {
7687                 pci_set_master(pdev);
7688                 pci_restore_state(pdev);
7689                 pci_save_state(pdev);
7690
7691                 pci_wake_from_d3(pdev, false);
7692
7693                 ixgbe_reset(adapter);
7694                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7695                 result = PCI_ERS_RESULT_RECOVERED;
7696         }
7697
7698         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7699         if (err) {
7700                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7701                           "failed 0x%0x\n", err);
7702                 /* non-fatal, continue */
7703         }
7704
7705         return result;
7706 }
7707
7708 /**
7709  * ixgbe_io_resume - called when traffic can start flowing again.
7710  * @pdev: Pointer to PCI device
7711  *
7712  * This callback is called when the error recovery driver tells us that
7713  * its OK to resume normal operation.
7714  */
7715 static void ixgbe_io_resume(struct pci_dev *pdev)
7716 {
7717         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7718         struct net_device *netdev = adapter->netdev;
7719
7720         if (netif_running(netdev)) {
7721                 if (ixgbe_up(adapter)) {
7722                         e_info(probe, "ixgbe_up failed after reset\n");
7723                         return;
7724                 }
7725         }
7726
7727         netif_device_attach(netdev);
7728 }
7729
7730 static struct pci_error_handlers ixgbe_err_handler = {
7731         .error_detected = ixgbe_io_error_detected,
7732         .slot_reset = ixgbe_io_slot_reset,
7733         .resume = ixgbe_io_resume,
7734 };
7735
7736 static struct pci_driver ixgbe_driver = {
7737         .name     = ixgbe_driver_name,
7738         .id_table = ixgbe_pci_tbl,
7739         .probe    = ixgbe_probe,
7740         .remove   = __devexit_p(ixgbe_remove),
7741 #ifdef CONFIG_PM
7742         .suspend  = ixgbe_suspend,
7743         .resume   = ixgbe_resume,
7744 #endif
7745         .shutdown = ixgbe_shutdown,
7746         .err_handler = &ixgbe_err_handler
7747 };
7748
7749 /**
7750  * ixgbe_init_module - Driver Registration Routine
7751  *
7752  * ixgbe_init_module is the first routine called when the driver is
7753  * loaded. All it does is register with the PCI subsystem.
7754  **/
7755 static int __init ixgbe_init_module(void)
7756 {
7757         int ret;
7758         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7759         pr_info("%s\n", ixgbe_copyright);
7760
7761 #ifdef CONFIG_IXGBE_DCA
7762         dca_register_notify(&dca_notifier);
7763 #endif
7764
7765         ret = pci_register_driver(&ixgbe_driver);
7766         return ret;
7767 }
7768
7769 module_init(ixgbe_init_module);
7770
7771 /**
7772  * ixgbe_exit_module - Driver Exit Cleanup Routine
7773  *
7774  * ixgbe_exit_module is called just before the driver is removed
7775  * from memory.
7776  **/
7777 static void __exit ixgbe_exit_module(void)
7778 {
7779 #ifdef CONFIG_IXGBE_DCA
7780         dca_unregister_notify(&dca_notifier);
7781 #endif
7782         pci_unregister_driver(&ixgbe_driver);
7783         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7784 }
7785
7786 #ifdef CONFIG_IXGBE_DCA
7787 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7788                             void *p)
7789 {
7790         int ret_val;
7791
7792         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7793                                          __ixgbe_notify_dca);
7794
7795         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7796 }
7797
7798 #endif /* CONFIG_IXGBE_DCA */
7799
7800 module_exit(ixgbe_exit_module);
7801
7802 /* ixgbe_main.c */