2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through of_device. Configuration information
29 * is therefore conveyed through an OF-style device tree.
31 * The Gianfar Ethernet Controller uses a ring of buffer
32 * descriptors. The beginning is indicated by a register
33 * pointing to the physical address of the start of the ring.
34 * The end is determined by a "wrap" bit being set in the
35 * last descriptor of the ring.
37 * When a packet is received, the RXF bit in the
38 * IEVENT register is set, triggering an interrupt when the
39 * corresponding bit in the IMASK register is also set (if
40 * interrupt coalescing is active, then the interrupt may not
41 * happen immediately, but will wait until either a set number
42 * of frames or amount of time have passed). In NAPI, the
43 * interrupt handler will signal there is work to be done, and
44 * exit. This method will start at the last known empty
45 * descriptor, and process every subsequent descriptor until there
46 * are none left with data (NAPI will stop after a set number of
47 * packets to give time to other tasks, but will eventually
48 * process all the packets). The data arrives inside a
49 * pre-allocated skb, and so after the skb is passed up to the
50 * stack, a new skb must be allocated, and the address field in
51 * the buffer descriptor must be updated to indicate this new
54 * When the kernel requests that a packet be transmitted, the
55 * driver starts where it left off last time, and points the
56 * descriptor at the buffer which was passed in. The driver
57 * then informs the DMA engine that there are packets ready to
58 * be transmitted. Once the controller is finished transmitting
59 * the packet, an interrupt may be triggered (under the same
60 * conditions as for reception, but depending on the TXF bit).
61 * The driver then cleans up the buffer.
64 #include <linux/kernel.h>
65 #include <linux/string.h>
66 #include <linux/errno.h>
67 #include <linux/unistd.h>
68 #include <linux/slab.h>
69 #include <linux/interrupt.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/netdevice.h>
73 #include <linux/etherdevice.h>
74 #include <linux/skbuff.h>
75 #include <linux/if_vlan.h>
76 #include <linux/spinlock.h>
78 #include <linux/of_mdio.h>
79 #include <linux/of_platform.h>
81 #include <linux/tcp.h>
82 #include <linux/udp.h>
87 #include <asm/uaccess.h>
88 #include <linux/module.h>
89 #include <linux/dma-mapping.h>
90 #include <linux/crc32.h>
91 #include <linux/mii.h>
92 #include <linux/phy.h>
93 #include <linux/phy_fixed.h>
97 #include "fsl_pq_mdio.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct of_device *ofdev,
123 const struct of_device_id *match);
124 static int gfar_remove(struct of_device *ofdev);
125 static void free_skb_resources(struct gfar_private *priv);
126 static void gfar_set_multi(struct net_device *dev);
127 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
128 static void gfar_configure_serdes(struct net_device *dev);
129 static int gfar_poll(struct napi_struct *napi, int budget);
130 #ifdef CONFIG_NET_POLL_CONTROLLER
131 static void gfar_netpoll(struct net_device *dev);
133 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
134 static int gfar_clean_tx_ring(struct net_device *dev);
135 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
137 static void gfar_vlan_rx_register(struct net_device *netdev,
138 struct vlan_group *grp);
139 void gfar_halt(struct net_device *dev);
140 static void gfar_halt_nodisable(struct net_device *dev);
141 void gfar_start(struct net_device *dev);
142 static void gfar_clear_exact_match(struct net_device *dev);
143 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
144 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
146 MODULE_AUTHOR("Freescale Semiconductor, Inc");
147 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
148 MODULE_LICENSE("GPL");
150 static const struct net_device_ops gfar_netdev_ops = {
151 .ndo_open = gfar_enet_open,
152 .ndo_start_xmit = gfar_start_xmit,
153 .ndo_stop = gfar_close,
154 .ndo_change_mtu = gfar_change_mtu,
155 .ndo_set_multicast_list = gfar_set_multi,
156 .ndo_tx_timeout = gfar_timeout,
157 .ndo_do_ioctl = gfar_ioctl,
158 .ndo_vlan_rx_register = gfar_vlan_rx_register,
159 #ifdef CONFIG_NET_POLL_CONTROLLER
160 .ndo_poll_controller = gfar_netpoll,
164 /* Returns 1 if incoming frames use an FCB */
165 static inline int gfar_uses_fcb(struct gfar_private *priv)
167 return priv->vlgrp || priv->rx_csum_enable;
170 static int gfar_of_init(struct net_device *dev)
174 const void *mac_addr;
177 struct gfar_private *priv = netdev_priv(dev);
178 struct device_node *np = priv->node;
180 const u32 *stash_len;
181 const u32 *stash_idx;
183 if (!np || !of_device_is_available(np))
186 /* get a pointer to the register memory */
187 addr = of_translate_address(np, of_get_address(np, 0, &size, NULL));
188 priv->regs = ioremap(addr, size);
190 if (priv->regs == NULL)
193 priv->interruptTransmit = irq_of_parse_and_map(np, 0);
195 model = of_get_property(np, "model", NULL);
197 /* If we aren't the FEC we have multiple interrupts */
198 if (model && strcasecmp(model, "FEC")) {
199 priv->interruptReceive = irq_of_parse_and_map(np, 1);
201 priv->interruptError = irq_of_parse_and_map(np, 2);
203 if (priv->interruptTransmit < 0 ||
204 priv->interruptReceive < 0 ||
205 priv->interruptError < 0) {
211 stash = of_get_property(np, "bd-stash", NULL);
214 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
215 priv->bd_stash_en = 1;
218 stash_len = of_get_property(np, "rx-stash-len", NULL);
221 priv->rx_stash_size = *stash_len;
223 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
226 priv->rx_stash_index = *stash_idx;
228 if (stash_len || stash_idx)
229 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
231 mac_addr = of_get_mac_address(np);
233 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
235 if (model && !strcasecmp(model, "TSEC"))
237 FSL_GIANFAR_DEV_HAS_GIGABIT |
238 FSL_GIANFAR_DEV_HAS_COALESCE |
239 FSL_GIANFAR_DEV_HAS_RMON |
240 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
241 if (model && !strcasecmp(model, "eTSEC"))
243 FSL_GIANFAR_DEV_HAS_GIGABIT |
244 FSL_GIANFAR_DEV_HAS_COALESCE |
245 FSL_GIANFAR_DEV_HAS_RMON |
246 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
247 FSL_GIANFAR_DEV_HAS_PADDING |
248 FSL_GIANFAR_DEV_HAS_CSUM |
249 FSL_GIANFAR_DEV_HAS_VLAN |
250 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
251 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
253 ctype = of_get_property(np, "phy-connection-type", NULL);
255 /* We only care about rgmii-id. The rest are autodetected */
256 if (ctype && !strcmp(ctype, "rgmii-id"))
257 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
259 priv->interface = PHY_INTERFACE_MODE_MII;
261 if (of_get_property(np, "fsl,magic-packet", NULL))
262 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
264 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
265 if (!priv->phy_node) {
268 fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
275 /* Find the TBI PHY. If it's not there, we don't support SGMII */
276 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
285 /* Ioctl MII Interface */
286 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
288 struct gfar_private *priv = netdev_priv(dev);
290 if (!netif_running(dev))
296 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
299 /* Set up the ethernet device structure, private data,
300 * and anything else we need before we start */
301 static int gfar_probe(struct of_device *ofdev,
302 const struct of_device_id *match)
305 struct net_device *dev = NULL;
306 struct gfar_private *priv = NULL;
307 DECLARE_MAC_BUF(mac);
311 /* Create an ethernet device instance */
312 dev = alloc_etherdev(sizeof (*priv));
317 priv = netdev_priv(dev);
320 priv->node = ofdev->node;
321 SET_NETDEV_DEV(dev, &ofdev->dev);
323 err = gfar_of_init(dev);
328 spin_lock_init(&priv->txlock);
329 spin_lock_init(&priv->rxlock);
330 spin_lock_init(&priv->bflock);
331 INIT_WORK(&priv->reset_task, gfar_reset_task);
333 dev_set_drvdata(&ofdev->dev, priv);
335 /* Stop the DMA engine now, in case it was running before */
336 /* (The firmware could have used it, and left it running). */
339 /* Reset MAC layer */
340 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
342 /* We need to delay at least 3 TX clocks */
345 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
346 gfar_write(&priv->regs->maccfg1, tempval);
348 /* Initialize MACCFG2. */
349 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
351 /* Initialize ECNTRL */
352 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
354 /* Set the dev->base_addr to the gfar reg region */
355 dev->base_addr = (unsigned long) (priv->regs);
357 SET_NETDEV_DEV(dev, &ofdev->dev);
359 /* Fill in the dev structure */
360 dev->watchdog_timeo = TX_TIMEOUT;
361 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
364 dev->netdev_ops = &gfar_netdev_ops;
365 dev->ethtool_ops = &gfar_ethtool_ops;
367 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
368 priv->rx_csum_enable = 1;
369 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
371 priv->rx_csum_enable = 0;
375 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
376 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
378 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
379 priv->extended_hash = 1;
380 priv->hash_width = 9;
382 priv->hash_regs[0] = &priv->regs->igaddr0;
383 priv->hash_regs[1] = &priv->regs->igaddr1;
384 priv->hash_regs[2] = &priv->regs->igaddr2;
385 priv->hash_regs[3] = &priv->regs->igaddr3;
386 priv->hash_regs[4] = &priv->regs->igaddr4;
387 priv->hash_regs[5] = &priv->regs->igaddr5;
388 priv->hash_regs[6] = &priv->regs->igaddr6;
389 priv->hash_regs[7] = &priv->regs->igaddr7;
390 priv->hash_regs[8] = &priv->regs->gaddr0;
391 priv->hash_regs[9] = &priv->regs->gaddr1;
392 priv->hash_regs[10] = &priv->regs->gaddr2;
393 priv->hash_regs[11] = &priv->regs->gaddr3;
394 priv->hash_regs[12] = &priv->regs->gaddr4;
395 priv->hash_regs[13] = &priv->regs->gaddr5;
396 priv->hash_regs[14] = &priv->regs->gaddr6;
397 priv->hash_regs[15] = &priv->regs->gaddr7;
400 priv->extended_hash = 0;
401 priv->hash_width = 8;
403 priv->hash_regs[0] = &priv->regs->gaddr0;
404 priv->hash_regs[1] = &priv->regs->gaddr1;
405 priv->hash_regs[2] = &priv->regs->gaddr2;
406 priv->hash_regs[3] = &priv->regs->gaddr3;
407 priv->hash_regs[4] = &priv->regs->gaddr4;
408 priv->hash_regs[5] = &priv->regs->gaddr5;
409 priv->hash_regs[6] = &priv->regs->gaddr6;
410 priv->hash_regs[7] = &priv->regs->gaddr7;
413 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
414 priv->padding = DEFAULT_PADDING;
418 if (dev->features & NETIF_F_IP_CSUM)
419 dev->hard_header_len += GMAC_FCB_LEN;
421 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
422 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
423 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
424 priv->num_txbdfree = DEFAULT_TX_RING_SIZE;
426 priv->txcoalescing = DEFAULT_TX_COALESCE;
427 priv->txic = DEFAULT_TXIC;
428 priv->rxcoalescing = DEFAULT_RX_COALESCE;
429 priv->rxic = DEFAULT_RXIC;
431 /* Enable most messages by default */
432 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
434 /* Carrier starts down, phylib will bring it up */
435 netif_carrier_off(dev);
437 err = register_netdev(dev);
440 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
445 device_init_wakeup(&dev->dev,
446 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
448 /* fill out IRQ number and name fields */
449 len_devname = strlen(dev->name);
450 strncpy(&priv->int_name_tx[0], dev->name, len_devname);
451 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
452 strncpy(&priv->int_name_tx[len_devname],
453 "_tx", sizeof("_tx") + 1);
455 strncpy(&priv->int_name_rx[0], dev->name, len_devname);
456 strncpy(&priv->int_name_rx[len_devname],
457 "_rx", sizeof("_rx") + 1);
459 strncpy(&priv->int_name_er[0], dev->name, len_devname);
460 strncpy(&priv->int_name_er[len_devname],
461 "_er", sizeof("_er") + 1);
463 priv->int_name_tx[len_devname] = '\0';
465 /* Create all the sysfs files */
466 gfar_init_sysfs(dev);
468 /* Print out the device info */
469 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
471 /* Even more device info helps when determining which kernel */
472 /* provided which set of benchmarks. */
473 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
474 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
475 dev->name, priv->rx_ring_size, priv->tx_ring_size);
483 of_node_put(priv->phy_node);
485 of_node_put(priv->tbi_node);
490 static int gfar_remove(struct of_device *ofdev)
492 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
495 of_node_put(priv->phy_node);
497 of_node_put(priv->tbi_node);
499 dev_set_drvdata(&ofdev->dev, NULL);
502 free_netdev(priv->ndev);
508 static int gfar_suspend(struct of_device *ofdev, pm_message_t state)
510 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
511 struct net_device *dev = priv->ndev;
515 int magic_packet = priv->wol_en &&
516 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
518 netif_device_detach(dev);
520 if (netif_running(dev)) {
521 spin_lock_irqsave(&priv->txlock, flags);
522 spin_lock(&priv->rxlock);
524 gfar_halt_nodisable(dev);
526 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
527 tempval = gfar_read(&priv->regs->maccfg1);
529 tempval &= ~MACCFG1_TX_EN;
532 tempval &= ~MACCFG1_RX_EN;
534 gfar_write(&priv->regs->maccfg1, tempval);
536 spin_unlock(&priv->rxlock);
537 spin_unlock_irqrestore(&priv->txlock, flags);
539 napi_disable(&priv->napi);
542 /* Enable interrupt on Magic Packet */
543 gfar_write(&priv->regs->imask, IMASK_MAG);
545 /* Enable Magic Packet mode */
546 tempval = gfar_read(&priv->regs->maccfg2);
547 tempval |= MACCFG2_MPEN;
548 gfar_write(&priv->regs->maccfg2, tempval);
550 phy_stop(priv->phydev);
557 static int gfar_resume(struct of_device *ofdev)
559 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
560 struct net_device *dev = priv->ndev;
563 int magic_packet = priv->wol_en &&
564 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
566 if (!netif_running(dev)) {
567 netif_device_attach(dev);
571 if (!magic_packet && priv->phydev)
572 phy_start(priv->phydev);
574 /* Disable Magic Packet mode, in case something
578 spin_lock_irqsave(&priv->txlock, flags);
579 spin_lock(&priv->rxlock);
581 tempval = gfar_read(&priv->regs->maccfg2);
582 tempval &= ~MACCFG2_MPEN;
583 gfar_write(&priv->regs->maccfg2, tempval);
587 spin_unlock(&priv->rxlock);
588 spin_unlock_irqrestore(&priv->txlock, flags);
590 netif_device_attach(dev);
592 napi_enable(&priv->napi);
597 #define gfar_suspend NULL
598 #define gfar_resume NULL
601 /* Reads the controller's registers to determine what interface
602 * connects it to the PHY.
604 static phy_interface_t gfar_get_interface(struct net_device *dev)
606 struct gfar_private *priv = netdev_priv(dev);
607 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
609 if (ecntrl & ECNTRL_SGMII_MODE)
610 return PHY_INTERFACE_MODE_SGMII;
612 if (ecntrl & ECNTRL_TBI_MODE) {
613 if (ecntrl & ECNTRL_REDUCED_MODE)
614 return PHY_INTERFACE_MODE_RTBI;
616 return PHY_INTERFACE_MODE_TBI;
619 if (ecntrl & ECNTRL_REDUCED_MODE) {
620 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
621 return PHY_INTERFACE_MODE_RMII;
623 phy_interface_t interface = priv->interface;
626 * This isn't autodetected right now, so it must
627 * be set by the device tree or platform code.
629 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
630 return PHY_INTERFACE_MODE_RGMII_ID;
632 return PHY_INTERFACE_MODE_RGMII;
636 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
637 return PHY_INTERFACE_MODE_GMII;
639 return PHY_INTERFACE_MODE_MII;
643 /* Initializes driver's PHY state, and attaches to the PHY.
644 * Returns 0 on success.
646 static int init_phy(struct net_device *dev)
648 struct gfar_private *priv = netdev_priv(dev);
649 uint gigabit_support =
650 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
651 SUPPORTED_1000baseT_Full : 0;
652 phy_interface_t interface;
656 priv->oldduplex = -1;
658 interface = gfar_get_interface(dev);
660 if (priv->phy_node) {
661 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link,
664 dev_err(&dev->dev, "error: Could not attach to PHY\n");
669 if (interface == PHY_INTERFACE_MODE_SGMII)
670 gfar_configure_serdes(dev);
672 /* Remove any features not supported by the controller */
673 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
674 priv->phydev->advertising = priv->phydev->supported;
680 * Initialize TBI PHY interface for communicating with the
681 * SERDES lynx PHY on the chip. We communicate with this PHY
682 * through the MDIO bus on each controller, treating it as a
683 * "normal" PHY at the address found in the TBIPA register. We assume
684 * that the TBIPA register is valid. Either the MDIO bus code will set
685 * it to a value that doesn't conflict with other PHYs on the bus, or the
686 * value doesn't matter, as there are no other PHYs on the bus.
688 static void gfar_configure_serdes(struct net_device *dev)
690 struct gfar_private *priv = netdev_priv(dev);
691 struct phy_device *tbiphy;
693 if (!priv->tbi_node) {
694 dev_warn(&dev->dev, "error: SGMII mode requires that the "
695 "device tree specify a tbi-handle\n");
699 tbiphy = of_phy_find_device(priv->tbi_node);
701 dev_err(&dev->dev, "error: Could not get TBI device\n");
706 * If the link is already up, we must already be ok, and don't need to
707 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
708 * everything for us? Resetting it takes the link down and requires
709 * several seconds for it to come back.
711 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
714 /* Single clk mode, mii mode off(for serdes communication) */
715 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
717 phy_write(tbiphy, MII_ADVERTISE,
718 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
719 ADVERTISE_1000XPSE_ASYM);
721 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
722 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
725 static void init_registers(struct net_device *dev)
727 struct gfar_private *priv = netdev_priv(dev);
730 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
732 /* Initialize IMASK */
733 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
735 /* Init hash registers to zero */
736 gfar_write(&priv->regs->igaddr0, 0);
737 gfar_write(&priv->regs->igaddr1, 0);
738 gfar_write(&priv->regs->igaddr2, 0);
739 gfar_write(&priv->regs->igaddr3, 0);
740 gfar_write(&priv->regs->igaddr4, 0);
741 gfar_write(&priv->regs->igaddr5, 0);
742 gfar_write(&priv->regs->igaddr6, 0);
743 gfar_write(&priv->regs->igaddr7, 0);
745 gfar_write(&priv->regs->gaddr0, 0);
746 gfar_write(&priv->regs->gaddr1, 0);
747 gfar_write(&priv->regs->gaddr2, 0);
748 gfar_write(&priv->regs->gaddr3, 0);
749 gfar_write(&priv->regs->gaddr4, 0);
750 gfar_write(&priv->regs->gaddr5, 0);
751 gfar_write(&priv->regs->gaddr6, 0);
752 gfar_write(&priv->regs->gaddr7, 0);
754 /* Zero out the rmon mib registers if it has them */
755 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
756 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
758 /* Mask off the CAM interrupts */
759 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
760 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
763 /* Initialize the max receive buffer length */
764 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
766 /* Initialize the Minimum Frame Length Register */
767 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
771 /* Halt the receive and transmit queues */
772 static void gfar_halt_nodisable(struct net_device *dev)
774 struct gfar_private *priv = netdev_priv(dev);
775 struct gfar __iomem *regs = priv->regs;
778 /* Mask all interrupts */
779 gfar_write(®s->imask, IMASK_INIT_CLEAR);
781 /* Clear all interrupts */
782 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
784 /* Stop the DMA, and wait for it to stop */
785 tempval = gfar_read(&priv->regs->dmactrl);
786 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
787 != (DMACTRL_GRS | DMACTRL_GTS)) {
788 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
789 gfar_write(&priv->regs->dmactrl, tempval);
791 while (!(gfar_read(&priv->regs->ievent) &
792 (IEVENT_GRSC | IEVENT_GTSC)))
797 /* Halt the receive and transmit queues */
798 void gfar_halt(struct net_device *dev)
800 struct gfar_private *priv = netdev_priv(dev);
801 struct gfar __iomem *regs = priv->regs;
804 gfar_halt_nodisable(dev);
806 /* Disable Rx and Tx */
807 tempval = gfar_read(®s->maccfg1);
808 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
809 gfar_write(®s->maccfg1, tempval);
812 void stop_gfar(struct net_device *dev)
814 struct gfar_private *priv = netdev_priv(dev);
815 struct gfar __iomem *regs = priv->regs;
818 phy_stop(priv->phydev);
821 spin_lock_irqsave(&priv->txlock, flags);
822 spin_lock(&priv->rxlock);
826 spin_unlock(&priv->rxlock);
827 spin_unlock_irqrestore(&priv->txlock, flags);
830 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
831 free_irq(priv->interruptError, dev);
832 free_irq(priv->interruptTransmit, dev);
833 free_irq(priv->interruptReceive, dev);
835 free_irq(priv->interruptTransmit, dev);
838 free_skb_resources(priv);
840 dma_free_coherent(&priv->ofdev->dev,
841 sizeof(struct txbd8)*priv->tx_ring_size
842 + sizeof(struct rxbd8)*priv->rx_ring_size,
844 gfar_read(®s->tbase0));
847 /* If there are any tx skbs or rx skbs still around, free them.
848 * Then free tx_skbuff and rx_skbuff */
849 static void free_skb_resources(struct gfar_private *priv)
855 /* Go through all the buffer descriptors and free their data buffers */
856 txbdp = priv->tx_bd_base;
858 for (i = 0; i < priv->tx_ring_size; i++) {
859 if (!priv->tx_skbuff[i])
862 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
863 txbdp->length, DMA_TO_DEVICE);
865 for (j = 0; j < skb_shinfo(priv->tx_skbuff[i])->nr_frags; j++) {
867 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
868 txbdp->length, DMA_TO_DEVICE);
871 dev_kfree_skb_any(priv->tx_skbuff[i]);
872 priv->tx_skbuff[i] = NULL;
875 kfree(priv->tx_skbuff);
877 rxbdp = priv->rx_bd_base;
879 /* rx_skbuff is not guaranteed to be allocated, so only
880 * free it and its contents if it is allocated */
881 if(priv->rx_skbuff != NULL) {
882 for (i = 0; i < priv->rx_ring_size; i++) {
883 if (priv->rx_skbuff[i]) {
884 dma_unmap_single(&priv->ofdev->dev, rxbdp->bufPtr,
885 priv->rx_buffer_size,
888 dev_kfree_skb_any(priv->rx_skbuff[i]);
889 priv->rx_skbuff[i] = NULL;
898 kfree(priv->rx_skbuff);
902 void gfar_start(struct net_device *dev)
904 struct gfar_private *priv = netdev_priv(dev);
905 struct gfar __iomem *regs = priv->regs;
908 /* Enable Rx and Tx in MACCFG1 */
909 tempval = gfar_read(®s->maccfg1);
910 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
911 gfar_write(®s->maccfg1, tempval);
913 /* Initialize DMACTRL to have WWR and WOP */
914 tempval = gfar_read(&priv->regs->dmactrl);
915 tempval |= DMACTRL_INIT_SETTINGS;
916 gfar_write(&priv->regs->dmactrl, tempval);
918 /* Make sure we aren't stopped */
919 tempval = gfar_read(&priv->regs->dmactrl);
920 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
921 gfar_write(&priv->regs->dmactrl, tempval);
923 /* Clear THLT/RHLT, so that the DMA starts polling now */
924 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
925 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
927 /* Unmask the interrupts we look for */
928 gfar_write(®s->imask, IMASK_DEFAULT);
930 dev->trans_start = jiffies;
933 /* Bring the controller up and running */
934 int startup_gfar(struct net_device *dev)
941 struct gfar_private *priv = netdev_priv(dev);
942 struct gfar __iomem *regs = priv->regs;
947 gfar_write(®s->imask, IMASK_INIT_CLEAR);
949 /* Allocate memory for the buffer descriptors */
950 vaddr = (unsigned long) dma_alloc_coherent(&priv->ofdev->dev,
951 sizeof (struct txbd8) * priv->tx_ring_size +
952 sizeof (struct rxbd8) * priv->rx_ring_size,
956 if (netif_msg_ifup(priv))
957 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
962 priv->tx_bd_base = (struct txbd8 *) vaddr;
964 /* enet DMA only understands physical addresses */
965 gfar_write(®s->tbase0, addr);
967 /* Start the rx descriptor ring where the tx ring leaves off */
968 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
969 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
970 priv->rx_bd_base = (struct rxbd8 *) vaddr;
971 gfar_write(®s->rbase0, addr);
973 /* Setup the skbuff rings */
975 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
976 priv->tx_ring_size, GFP_KERNEL);
978 if (NULL == priv->tx_skbuff) {
979 if (netif_msg_ifup(priv))
980 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
986 for (i = 0; i < priv->tx_ring_size; i++)
987 priv->tx_skbuff[i] = NULL;
990 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
991 priv->rx_ring_size, GFP_KERNEL);
993 if (NULL == priv->rx_skbuff) {
994 if (netif_msg_ifup(priv))
995 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
1001 for (i = 0; i < priv->rx_ring_size; i++)
1002 priv->rx_skbuff[i] = NULL;
1004 /* Initialize some variables in our dev structure */
1005 priv->num_txbdfree = priv->tx_ring_size;
1006 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
1007 priv->cur_rx = priv->rx_bd_base;
1008 priv->skb_curtx = priv->skb_dirtytx = 0;
1009 priv->skb_currx = 0;
1011 /* Initialize Transmit Descriptor Ring */
1012 txbdp = priv->tx_bd_base;
1013 for (i = 0; i < priv->tx_ring_size; i++) {
1019 /* Set the last descriptor in the ring to indicate wrap */
1021 txbdp->status |= TXBD_WRAP;
1023 rxbdp = priv->rx_bd_base;
1024 for (i = 0; i < priv->rx_ring_size; i++) {
1025 struct sk_buff *skb;
1027 skb = gfar_new_skb(dev);
1030 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
1033 goto err_rxalloc_fail;
1036 priv->rx_skbuff[i] = skb;
1038 gfar_new_rxbdp(dev, rxbdp, skb);
1043 /* Set the last descriptor in the ring to wrap */
1045 rxbdp->status |= RXBD_WRAP;
1047 /* If the device has multiple interrupts, register for
1048 * them. Otherwise, only register for the one */
1049 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1050 /* Install our interrupt handlers for Error,
1051 * Transmit, and Receive */
1052 if (request_irq(priv->interruptError, gfar_error,
1053 0, priv->int_name_er, dev) < 0) {
1054 if (netif_msg_intr(priv))
1055 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1056 dev->name, priv->interruptError);
1062 if (request_irq(priv->interruptTransmit, gfar_transmit,
1063 0, priv->int_name_tx, dev) < 0) {
1064 if (netif_msg_intr(priv))
1065 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1066 dev->name, priv->interruptTransmit);
1073 if (request_irq(priv->interruptReceive, gfar_receive,
1074 0, priv->int_name_rx, dev) < 0) {
1075 if (netif_msg_intr(priv))
1076 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
1077 dev->name, priv->interruptReceive);
1083 if (request_irq(priv->interruptTransmit, gfar_interrupt,
1084 0, priv->int_name_tx, dev) < 0) {
1085 if (netif_msg_intr(priv))
1086 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1087 dev->name, priv->interruptTransmit);
1094 phy_start(priv->phydev);
1096 /* Configure the coalescing support */
1097 gfar_write(®s->txic, 0);
1098 if (priv->txcoalescing)
1099 gfar_write(®s->txic, priv->txic);
1101 gfar_write(®s->rxic, 0);
1102 if (priv->rxcoalescing)
1103 gfar_write(®s->rxic, priv->rxic);
1105 if (priv->rx_csum_enable)
1106 rctrl |= RCTRL_CHECKSUMMING;
1108 if (priv->extended_hash) {
1109 rctrl |= RCTRL_EXTHASH;
1111 gfar_clear_exact_match(dev);
1112 rctrl |= RCTRL_EMEN;
1115 if (priv->padding) {
1116 rctrl &= ~RCTRL_PAL_MASK;
1117 rctrl |= RCTRL_PADDING(priv->padding);
1120 /* Init rctrl based on our settings */
1121 gfar_write(&priv->regs->rctrl, rctrl);
1123 if (dev->features & NETIF_F_IP_CSUM)
1124 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1126 /* Set the extraction length and index */
1127 attrs = ATTRELI_EL(priv->rx_stash_size) |
1128 ATTRELI_EI(priv->rx_stash_index);
1130 gfar_write(&priv->regs->attreli, attrs);
1132 /* Start with defaults, and add stashing or locking
1133 * depending on the approprate variables */
1134 attrs = ATTR_INIT_SETTINGS;
1136 if (priv->bd_stash_en)
1137 attrs |= ATTR_BDSTASH;
1139 if (priv->rx_stash_size != 0)
1140 attrs |= ATTR_BUFSTASH;
1142 gfar_write(&priv->regs->attr, attrs);
1144 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1145 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1146 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1148 /* Start the controller */
1154 free_irq(priv->interruptTransmit, dev);
1156 free_irq(priv->interruptError, dev);
1160 free_skb_resources(priv);
1162 dma_free_coherent(&priv->ofdev->dev,
1163 sizeof(struct txbd8)*priv->tx_ring_size
1164 + sizeof(struct rxbd8)*priv->rx_ring_size,
1166 gfar_read(®s->tbase0));
1171 /* Called when something needs to use the ethernet device */
1172 /* Returns 0 for success. */
1173 static int gfar_enet_open(struct net_device *dev)
1175 struct gfar_private *priv = netdev_priv(dev);
1178 napi_enable(&priv->napi);
1180 skb_queue_head_init(&priv->rx_recycle);
1182 /* Initialize a bunch of registers */
1183 init_registers(dev);
1185 gfar_set_mac_address(dev);
1187 err = init_phy(dev);
1190 napi_disable(&priv->napi);
1194 err = startup_gfar(dev);
1196 napi_disable(&priv->napi);
1200 netif_start_queue(dev);
1202 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1207 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1209 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1210 cacheable_memzero(fcb, GMAC_FCB_LEN);
1215 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1219 /* If we're here, it's a IP packet with a TCP or UDP
1220 * payload. We set it to checksum, using a pseudo-header
1223 flags = TXFCB_DEFAULT;
1225 /* Tell the controller what the protocol is */
1226 /* And provide the already calculated phcs */
1227 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1229 fcb->phcs = udp_hdr(skb)->check;
1231 fcb->phcs = tcp_hdr(skb)->check;
1233 /* l3os is the distance between the start of the
1234 * frame (skb->data) and the start of the IP hdr.
1235 * l4os is the distance between the start of the
1236 * l3 hdr and the l4 hdr */
1237 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1238 fcb->l4os = skb_network_header_len(skb);
1243 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1245 fcb->flags |= TXFCB_VLN;
1246 fcb->vlctl = vlan_tx_tag_get(skb);
1249 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1250 struct txbd8 *base, int ring_size)
1252 struct txbd8 *new_bd = bdp + stride;
1254 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1257 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1260 return skip_txbd(bdp, 1, base, ring_size);
1263 /* This is called by the kernel when a frame is ready for transmission. */
1264 /* It is pointed to by the dev->hard_start_xmit function pointer */
1265 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1267 struct gfar_private *priv = netdev_priv(dev);
1268 struct txfcb *fcb = NULL;
1269 struct txbd8 *txbdp, *txbdp_start, *base;
1273 unsigned long flags;
1274 unsigned int nr_frags, length;
1276 base = priv->tx_bd_base;
1278 /* make space for additional header when fcb is needed */
1279 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1280 (priv->vlgrp && vlan_tx_tag_present(skb))) &&
1281 (skb_headroom(skb) < GMAC_FCB_LEN)) {
1282 struct sk_buff *skb_new;
1284 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1286 dev->stats.tx_errors++;
1288 return NETDEV_TX_OK;
1294 /* total number of fragments in the SKB */
1295 nr_frags = skb_shinfo(skb)->nr_frags;
1297 spin_lock_irqsave(&priv->txlock, flags);
1299 /* check if there is space to queue this packet */
1300 if ((nr_frags+1) > priv->num_txbdfree) {
1301 /* no space, stop the queue */
1302 netif_stop_queue(dev);
1303 dev->stats.tx_fifo_errors++;
1304 spin_unlock_irqrestore(&priv->txlock, flags);
1305 return NETDEV_TX_BUSY;
1308 /* Update transmit stats */
1309 dev->stats.tx_bytes += skb->len;
1311 txbdp = txbdp_start = priv->cur_tx;
1313 if (nr_frags == 0) {
1314 lstatus = txbdp->lstatus | BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1316 /* Place the fragment addresses and lengths into the TxBDs */
1317 for (i = 0; i < nr_frags; i++) {
1318 /* Point at the next BD, wrapping as needed */
1319 txbdp = next_txbd(txbdp, base, priv->tx_ring_size);
1321 length = skb_shinfo(skb)->frags[i].size;
1323 lstatus = txbdp->lstatus | length |
1324 BD_LFLAG(TXBD_READY);
1326 /* Handle the last BD specially */
1327 if (i == nr_frags - 1)
1328 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
1330 bufaddr = dma_map_page(&priv->ofdev->dev,
1331 skb_shinfo(skb)->frags[i].page,
1332 skb_shinfo(skb)->frags[i].page_offset,
1336 /* set the TxBD length and buffer pointer */
1337 txbdp->bufPtr = bufaddr;
1338 txbdp->lstatus = lstatus;
1341 lstatus = txbdp_start->lstatus;
1344 /* Set up checksumming */
1345 if (CHECKSUM_PARTIAL == skb->ip_summed) {
1346 fcb = gfar_add_fcb(skb);
1347 lstatus |= BD_LFLAG(TXBD_TOE);
1348 gfar_tx_checksum(skb, fcb);
1351 if (priv->vlgrp && vlan_tx_tag_present(skb)) {
1352 if (unlikely(NULL == fcb)) {
1353 fcb = gfar_add_fcb(skb);
1354 lstatus |= BD_LFLAG(TXBD_TOE);
1357 gfar_tx_vlan(skb, fcb);
1360 /* setup the TxBD length and buffer pointer for the first BD */
1361 priv->tx_skbuff[priv->skb_curtx] = skb;
1362 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1363 skb_headlen(skb), DMA_TO_DEVICE);
1365 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
1368 * The powerpc-specific eieio() is used, as wmb() has too strong
1369 * semantics (it requires synchronization between cacheable and
1370 * uncacheable mappings, which eieio doesn't provide and which we
1371 * don't need), thus requiring a more expensive sync instruction. At
1372 * some point, the set of architecture-independent barrier functions
1373 * should be expanded to include weaker barriers.
1377 txbdp_start->lstatus = lstatus;
1379 /* Update the current skb pointer to the next entry we will use
1380 * (wrapping if necessary) */
1381 priv->skb_curtx = (priv->skb_curtx + 1) &
1382 TX_RING_MOD_MASK(priv->tx_ring_size);
1384 priv->cur_tx = next_txbd(txbdp, base, priv->tx_ring_size);
1386 /* reduce TxBD free count */
1387 priv->num_txbdfree -= (nr_frags + 1);
1389 dev->trans_start = jiffies;
1391 /* If the next BD still needs to be cleaned up, then the bds
1392 are full. We need to tell the kernel to stop sending us stuff. */
1393 if (!priv->num_txbdfree) {
1394 netif_stop_queue(dev);
1396 dev->stats.tx_fifo_errors++;
1399 /* Tell the DMA to go go go */
1400 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1403 spin_unlock_irqrestore(&priv->txlock, flags);
1405 return NETDEV_TX_OK;
1408 /* Stops the kernel queue, and halts the controller */
1409 static int gfar_close(struct net_device *dev)
1411 struct gfar_private *priv = netdev_priv(dev);
1413 napi_disable(&priv->napi);
1415 skb_queue_purge(&priv->rx_recycle);
1416 cancel_work_sync(&priv->reset_task);
1419 /* Disconnect from the PHY */
1420 phy_disconnect(priv->phydev);
1421 priv->phydev = NULL;
1423 netif_stop_queue(dev);
1428 /* Changes the mac address if the controller is not running. */
1429 static int gfar_set_mac_address(struct net_device *dev)
1431 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1437 /* Enables and disables VLAN insertion/extraction */
1438 static void gfar_vlan_rx_register(struct net_device *dev,
1439 struct vlan_group *grp)
1441 struct gfar_private *priv = netdev_priv(dev);
1442 unsigned long flags;
1445 spin_lock_irqsave(&priv->rxlock, flags);
1450 /* Enable VLAN tag insertion */
1451 tempval = gfar_read(&priv->regs->tctrl);
1452 tempval |= TCTRL_VLINS;
1454 gfar_write(&priv->regs->tctrl, tempval);
1456 /* Enable VLAN tag extraction */
1457 tempval = gfar_read(&priv->regs->rctrl);
1458 tempval |= RCTRL_VLEX;
1459 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
1460 gfar_write(&priv->regs->rctrl, tempval);
1462 /* Disable VLAN tag insertion */
1463 tempval = gfar_read(&priv->regs->tctrl);
1464 tempval &= ~TCTRL_VLINS;
1465 gfar_write(&priv->regs->tctrl, tempval);
1467 /* Disable VLAN tag extraction */
1468 tempval = gfar_read(&priv->regs->rctrl);
1469 tempval &= ~RCTRL_VLEX;
1470 /* If parse is no longer required, then disable parser */
1471 if (tempval & RCTRL_REQ_PARSER)
1472 tempval |= RCTRL_PRSDEP_INIT;
1474 tempval &= ~RCTRL_PRSDEP_INIT;
1475 gfar_write(&priv->regs->rctrl, tempval);
1478 gfar_change_mtu(dev, dev->mtu);
1480 spin_unlock_irqrestore(&priv->rxlock, flags);
1483 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1485 int tempsize, tempval;
1486 struct gfar_private *priv = netdev_priv(dev);
1487 int oldsize = priv->rx_buffer_size;
1488 int frame_size = new_mtu + ETH_HLEN;
1491 frame_size += VLAN_HLEN;
1493 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1494 if (netif_msg_drv(priv))
1495 printk(KERN_ERR "%s: Invalid MTU setting\n",
1500 if (gfar_uses_fcb(priv))
1501 frame_size += GMAC_FCB_LEN;
1503 frame_size += priv->padding;
1506 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1507 INCREMENTAL_BUFFER_SIZE;
1509 /* Only stop and start the controller if it isn't already
1510 * stopped, and we changed something */
1511 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1514 priv->rx_buffer_size = tempsize;
1518 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1519 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1521 /* If the mtu is larger than the max size for standard
1522 * ethernet frames (ie, a jumbo frame), then set maccfg2
1523 * to allow huge frames, and to check the length */
1524 tempval = gfar_read(&priv->regs->maccfg2);
1526 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1527 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1529 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1531 gfar_write(&priv->regs->maccfg2, tempval);
1533 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1539 /* gfar_reset_task gets scheduled when a packet has not been
1540 * transmitted after a set amount of time.
1541 * For now, assume that clearing out all the structures, and
1542 * starting over will fix the problem.
1544 static void gfar_reset_task(struct work_struct *work)
1546 struct gfar_private *priv = container_of(work, struct gfar_private,
1548 struct net_device *dev = priv->ndev;
1550 if (dev->flags & IFF_UP) {
1551 netif_stop_queue(dev);
1554 netif_start_queue(dev);
1557 netif_tx_schedule_all(dev);
1560 static void gfar_timeout(struct net_device *dev)
1562 struct gfar_private *priv = netdev_priv(dev);
1564 dev->stats.tx_errors++;
1565 schedule_work(&priv->reset_task);
1568 /* Interrupt Handler for Transmit complete */
1569 static int gfar_clean_tx_ring(struct net_device *dev)
1571 struct gfar_private *priv = netdev_priv(dev);
1573 struct txbd8 *lbdp = NULL;
1574 struct txbd8 *base = priv->tx_bd_base;
1575 struct sk_buff *skb;
1577 int tx_ring_size = priv->tx_ring_size;
1583 bdp = priv->dirty_tx;
1584 skb_dirtytx = priv->skb_dirtytx;
1586 while ((skb = priv->tx_skbuff[skb_dirtytx])) {
1587 frags = skb_shinfo(skb)->nr_frags;
1588 lbdp = skip_txbd(bdp, frags, base, tx_ring_size);
1590 lstatus = lbdp->lstatus;
1592 /* Only clean completed frames */
1593 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
1594 (lstatus & BD_LENGTH_MASK))
1597 dma_unmap_single(&priv->ofdev->dev,
1602 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1603 bdp = next_txbd(bdp, base, tx_ring_size);
1605 for (i = 0; i < frags; i++) {
1606 dma_unmap_page(&priv->ofdev->dev,
1610 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
1611 bdp = next_txbd(bdp, base, tx_ring_size);
1615 * If there's room in the queue (limit it to rx_buffer_size)
1616 * we add this skb back into the pool, if it's the right size
1618 if (skb_queue_len(&priv->rx_recycle) < priv->rx_ring_size &&
1619 skb_recycle_check(skb, priv->rx_buffer_size +
1621 __skb_queue_head(&priv->rx_recycle, skb);
1623 dev_kfree_skb_any(skb);
1625 priv->tx_skbuff[skb_dirtytx] = NULL;
1627 skb_dirtytx = (skb_dirtytx + 1) &
1628 TX_RING_MOD_MASK(tx_ring_size);
1631 priv->num_txbdfree += frags + 1;
1634 /* If we freed a buffer, we can restart transmission, if necessary */
1635 if (netif_queue_stopped(dev) && priv->num_txbdfree)
1636 netif_wake_queue(dev);
1638 /* Update dirty indicators */
1639 priv->skb_dirtytx = skb_dirtytx;
1640 priv->dirty_tx = bdp;
1642 dev->stats.tx_packets += howmany;
1647 static void gfar_schedule_cleanup(struct net_device *dev)
1649 struct gfar_private *priv = netdev_priv(dev);
1650 unsigned long flags;
1652 spin_lock_irqsave(&priv->txlock, flags);
1653 spin_lock(&priv->rxlock);
1655 if (napi_schedule_prep(&priv->napi)) {
1656 gfar_write(&priv->regs->imask, IMASK_RTX_DISABLED);
1657 __napi_schedule(&priv->napi);
1660 * Clear IEVENT, so interrupts aren't called again
1661 * because of the packets that have already arrived.
1663 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1666 spin_unlock(&priv->rxlock);
1667 spin_unlock_irqrestore(&priv->txlock, flags);
1670 /* Interrupt Handler for Transmit complete */
1671 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1673 gfar_schedule_cleanup((struct net_device *)dev_id);
1677 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1678 struct sk_buff *skb)
1680 struct gfar_private *priv = netdev_priv(dev);
1683 bdp->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
1684 priv->rx_buffer_size, DMA_FROM_DEVICE);
1686 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
1688 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1689 lstatus |= BD_LFLAG(RXBD_WRAP);
1693 bdp->lstatus = lstatus;
1697 struct sk_buff * gfar_new_skb(struct net_device *dev)
1699 unsigned int alignamount;
1700 struct gfar_private *priv = netdev_priv(dev);
1701 struct sk_buff *skb = NULL;
1703 skb = __skb_dequeue(&priv->rx_recycle);
1705 skb = netdev_alloc_skb(dev,
1706 priv->rx_buffer_size + RXBUF_ALIGNMENT);
1711 alignamount = RXBUF_ALIGNMENT -
1712 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1714 /* We need the data buffer to be aligned properly. We will reserve
1715 * as many bytes as needed to align the data properly
1717 skb_reserve(skb, alignamount);
1722 static inline void count_errors(unsigned short status, struct net_device *dev)
1724 struct gfar_private *priv = netdev_priv(dev);
1725 struct net_device_stats *stats = &dev->stats;
1726 struct gfar_extra_stats *estats = &priv->extra_stats;
1728 /* If the packet was truncated, none of the other errors
1730 if (status & RXBD_TRUNCATED) {
1731 stats->rx_length_errors++;
1737 /* Count the errors, if there were any */
1738 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1739 stats->rx_length_errors++;
1741 if (status & RXBD_LARGE)
1746 if (status & RXBD_NONOCTET) {
1747 stats->rx_frame_errors++;
1748 estats->rx_nonoctet++;
1750 if (status & RXBD_CRCERR) {
1751 estats->rx_crcerr++;
1752 stats->rx_crc_errors++;
1754 if (status & RXBD_OVERRUN) {
1755 estats->rx_overrun++;
1756 stats->rx_crc_errors++;
1760 irqreturn_t gfar_receive(int irq, void *dev_id)
1762 gfar_schedule_cleanup((struct net_device *)dev_id);
1766 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1768 /* If valid headers were found, and valid sums
1769 * were verified, then we tell the kernel that no
1770 * checksumming is necessary. Otherwise, it is */
1771 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1772 skb->ip_summed = CHECKSUM_UNNECESSARY;
1774 skb->ip_summed = CHECKSUM_NONE;
1778 /* gfar_process_frame() -- handle one incoming packet if skb
1780 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1783 struct gfar_private *priv = netdev_priv(dev);
1784 struct rxfcb *fcb = NULL;
1788 /* fcb is at the beginning if exists */
1789 fcb = (struct rxfcb *)skb->data;
1791 /* Remove the FCB from the skb */
1792 /* Remove the padded bytes, if there are any */
1794 skb_pull(skb, amount_pull);
1796 if (priv->rx_csum_enable)
1797 gfar_rx_checksum(skb, fcb);
1799 /* Tell the skb what kind of packet this is */
1800 skb->protocol = eth_type_trans(skb, dev);
1802 /* Send the packet up the stack */
1803 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1804 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
1806 ret = netif_receive_skb(skb);
1808 if (NET_RX_DROP == ret)
1809 priv->extra_stats.kernel_dropped++;
1814 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1815 * until the budget/quota has been reached. Returns the number
1818 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1820 struct rxbd8 *bdp, *base;
1821 struct sk_buff *skb;
1825 struct gfar_private *priv = netdev_priv(dev);
1827 /* Get the first full descriptor */
1829 base = priv->rx_bd_base;
1831 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0) +
1834 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1835 struct sk_buff *newskb;
1838 /* Add another skb for the future */
1839 newskb = gfar_new_skb(dev);
1841 skb = priv->rx_skbuff[priv->skb_currx];
1843 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
1844 priv->rx_buffer_size, DMA_FROM_DEVICE);
1846 /* We drop the frame if we failed to allocate a new buffer */
1847 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1848 bdp->status & RXBD_ERR)) {
1849 count_errors(bdp->status, dev);
1851 if (unlikely(!newskb))
1854 __skb_queue_head(&priv->rx_recycle, skb);
1856 /* Increment the number of packets */
1857 dev->stats.rx_packets++;
1861 pkt_len = bdp->length - ETH_FCS_LEN;
1862 /* Remove the FCS from the packet length */
1863 skb_put(skb, pkt_len);
1864 dev->stats.rx_bytes += pkt_len;
1866 if (in_irq() || irqs_disabled())
1867 printk("Interrupt problem!\n");
1868 gfar_process_frame(dev, skb, amount_pull);
1871 if (netif_msg_rx_err(priv))
1873 "%s: Missing skb!\n", dev->name);
1874 dev->stats.rx_dropped++;
1875 priv->extra_stats.rx_skbmissing++;
1880 priv->rx_skbuff[priv->skb_currx] = newskb;
1882 /* Setup the new bdp */
1883 gfar_new_rxbdp(dev, bdp, newskb);
1885 /* Update to the next pointer */
1886 bdp = next_bd(bdp, base, priv->rx_ring_size);
1888 /* update to point at the next skb */
1890 (priv->skb_currx + 1) &
1891 RX_RING_MOD_MASK(priv->rx_ring_size);
1894 /* Update the current rxbd pointer to be the next one */
1900 static int gfar_poll(struct napi_struct *napi, int budget)
1902 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1903 struct net_device *dev = priv->ndev;
1906 unsigned long flags;
1908 /* Clear IEVENT, so interrupts aren't called again
1909 * because of the packets that have already arrived */
1910 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1912 /* If we fail to get the lock, don't bother with the TX BDs */
1913 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1914 tx_cleaned = gfar_clean_tx_ring(dev);
1915 spin_unlock_irqrestore(&priv->txlock, flags);
1918 rx_cleaned = gfar_clean_rx_ring(dev, budget);
1923 if (rx_cleaned < budget) {
1924 napi_complete(napi);
1926 /* Clear the halt bit in RSTAT */
1927 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1929 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1931 /* If we are coalescing interrupts, update the timer */
1932 /* Otherwise, clear it */
1933 if (likely(priv->rxcoalescing)) {
1934 gfar_write(&priv->regs->rxic, 0);
1935 gfar_write(&priv->regs->rxic, priv->rxic);
1937 if (likely(priv->txcoalescing)) {
1938 gfar_write(&priv->regs->txic, 0);
1939 gfar_write(&priv->regs->txic, priv->txic);
1946 #ifdef CONFIG_NET_POLL_CONTROLLER
1948 * Polling 'interrupt' - used by things like netconsole to send skbs
1949 * without having to re-enable interrupts. It's not called while
1950 * the interrupt routine is executing.
1952 static void gfar_netpoll(struct net_device *dev)
1954 struct gfar_private *priv = netdev_priv(dev);
1956 /* If the device has multiple interrupts, run tx/rx */
1957 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1958 disable_irq(priv->interruptTransmit);
1959 disable_irq(priv->interruptReceive);
1960 disable_irq(priv->interruptError);
1961 gfar_interrupt(priv->interruptTransmit, dev);
1962 enable_irq(priv->interruptError);
1963 enable_irq(priv->interruptReceive);
1964 enable_irq(priv->interruptTransmit);
1966 disable_irq(priv->interruptTransmit);
1967 gfar_interrupt(priv->interruptTransmit, dev);
1968 enable_irq(priv->interruptTransmit);
1973 /* The interrupt handler for devices with one interrupt */
1974 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1976 struct net_device *dev = dev_id;
1977 struct gfar_private *priv = netdev_priv(dev);
1979 /* Save ievent for future reference */
1980 u32 events = gfar_read(&priv->regs->ievent);
1982 /* Check for reception */
1983 if (events & IEVENT_RX_MASK)
1984 gfar_receive(irq, dev_id);
1986 /* Check for transmit completion */
1987 if (events & IEVENT_TX_MASK)
1988 gfar_transmit(irq, dev_id);
1990 /* Check for errors */
1991 if (events & IEVENT_ERR_MASK)
1992 gfar_error(irq, dev_id);
1997 /* Called every time the controller might need to be made
1998 * aware of new link state. The PHY code conveys this
1999 * information through variables in the phydev structure, and this
2000 * function converts those variables into the appropriate
2001 * register values, and can bring down the device if needed.
2003 static void adjust_link(struct net_device *dev)
2005 struct gfar_private *priv = netdev_priv(dev);
2006 struct gfar __iomem *regs = priv->regs;
2007 unsigned long flags;
2008 struct phy_device *phydev = priv->phydev;
2011 spin_lock_irqsave(&priv->txlock, flags);
2013 u32 tempval = gfar_read(®s->maccfg2);
2014 u32 ecntrl = gfar_read(®s->ecntrl);
2016 /* Now we make sure that we can be in full duplex mode.
2017 * If not, we operate in half-duplex mode. */
2018 if (phydev->duplex != priv->oldduplex) {
2020 if (!(phydev->duplex))
2021 tempval &= ~(MACCFG2_FULL_DUPLEX);
2023 tempval |= MACCFG2_FULL_DUPLEX;
2025 priv->oldduplex = phydev->duplex;
2028 if (phydev->speed != priv->oldspeed) {
2030 switch (phydev->speed) {
2033 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2035 ecntrl &= ~(ECNTRL_R100);
2040 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2042 /* Reduced mode distinguishes
2043 * between 10 and 100 */
2044 if (phydev->speed == SPEED_100)
2045 ecntrl |= ECNTRL_R100;
2047 ecntrl &= ~(ECNTRL_R100);
2050 if (netif_msg_link(priv))
2052 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2053 dev->name, phydev->speed);
2057 priv->oldspeed = phydev->speed;
2060 gfar_write(®s->maccfg2, tempval);
2061 gfar_write(®s->ecntrl, ecntrl);
2063 if (!priv->oldlink) {
2067 } else if (priv->oldlink) {
2071 priv->oldduplex = -1;
2074 if (new_state && netif_msg_link(priv))
2075 phy_print_status(phydev);
2077 spin_unlock_irqrestore(&priv->txlock, flags);
2080 /* Update the hash table based on the current list of multicast
2081 * addresses we subscribe to. Also, change the promiscuity of
2082 * the device based on the flags (this function is called
2083 * whenever dev->flags is changed */
2084 static void gfar_set_multi(struct net_device *dev)
2086 struct dev_mc_list *mc_ptr;
2087 struct gfar_private *priv = netdev_priv(dev);
2088 struct gfar __iomem *regs = priv->regs;
2091 if(dev->flags & IFF_PROMISC) {
2092 /* Set RCTRL to PROM */
2093 tempval = gfar_read(®s->rctrl);
2094 tempval |= RCTRL_PROM;
2095 gfar_write(®s->rctrl, tempval);
2097 /* Set RCTRL to not PROM */
2098 tempval = gfar_read(®s->rctrl);
2099 tempval &= ~(RCTRL_PROM);
2100 gfar_write(®s->rctrl, tempval);
2103 if(dev->flags & IFF_ALLMULTI) {
2104 /* Set the hash to rx all multicast frames */
2105 gfar_write(®s->igaddr0, 0xffffffff);
2106 gfar_write(®s->igaddr1, 0xffffffff);
2107 gfar_write(®s->igaddr2, 0xffffffff);
2108 gfar_write(®s->igaddr3, 0xffffffff);
2109 gfar_write(®s->igaddr4, 0xffffffff);
2110 gfar_write(®s->igaddr5, 0xffffffff);
2111 gfar_write(®s->igaddr6, 0xffffffff);
2112 gfar_write(®s->igaddr7, 0xffffffff);
2113 gfar_write(®s->gaddr0, 0xffffffff);
2114 gfar_write(®s->gaddr1, 0xffffffff);
2115 gfar_write(®s->gaddr2, 0xffffffff);
2116 gfar_write(®s->gaddr3, 0xffffffff);
2117 gfar_write(®s->gaddr4, 0xffffffff);
2118 gfar_write(®s->gaddr5, 0xffffffff);
2119 gfar_write(®s->gaddr6, 0xffffffff);
2120 gfar_write(®s->gaddr7, 0xffffffff);
2125 /* zero out the hash */
2126 gfar_write(®s->igaddr0, 0x0);
2127 gfar_write(®s->igaddr1, 0x0);
2128 gfar_write(®s->igaddr2, 0x0);
2129 gfar_write(®s->igaddr3, 0x0);
2130 gfar_write(®s->igaddr4, 0x0);
2131 gfar_write(®s->igaddr5, 0x0);
2132 gfar_write(®s->igaddr6, 0x0);
2133 gfar_write(®s->igaddr7, 0x0);
2134 gfar_write(®s->gaddr0, 0x0);
2135 gfar_write(®s->gaddr1, 0x0);
2136 gfar_write(®s->gaddr2, 0x0);
2137 gfar_write(®s->gaddr3, 0x0);
2138 gfar_write(®s->gaddr4, 0x0);
2139 gfar_write(®s->gaddr5, 0x0);
2140 gfar_write(®s->gaddr6, 0x0);
2141 gfar_write(®s->gaddr7, 0x0);
2143 /* If we have extended hash tables, we need to
2144 * clear the exact match registers to prepare for
2146 if (priv->extended_hash) {
2147 em_num = GFAR_EM_NUM + 1;
2148 gfar_clear_exact_match(dev);
2155 if(dev->mc_count == 0)
2158 /* Parse the list, and set the appropriate bits */
2159 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
2161 gfar_set_mac_for_addr(dev, idx,
2165 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
2173 /* Clears each of the exact match registers to zero, so they
2174 * don't interfere with normal reception */
2175 static void gfar_clear_exact_match(struct net_device *dev)
2178 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
2180 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
2181 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
2184 /* Set the appropriate hash bit for the given addr */
2185 /* The algorithm works like so:
2186 * 1) Take the Destination Address (ie the multicast address), and
2187 * do a CRC on it (little endian), and reverse the bits of the
2189 * 2) Use the 8 most significant bits as a hash into a 256-entry
2190 * table. The table is controlled through 8 32-bit registers:
2191 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
2192 * gaddr7. This means that the 3 most significant bits in the
2193 * hash index which gaddr register to use, and the 5 other bits
2194 * indicate which bit (assuming an IBM numbering scheme, which
2195 * for PowerPC (tm) is usually the case) in the register holds
2197 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
2200 struct gfar_private *priv = netdev_priv(dev);
2201 u32 result = ether_crc(MAC_ADDR_LEN, addr);
2202 int width = priv->hash_width;
2203 u8 whichbit = (result >> (32 - width)) & 0x1f;
2204 u8 whichreg = result >> (32 - width + 5);
2205 u32 value = (1 << (31-whichbit));
2207 tempval = gfar_read(priv->hash_regs[whichreg]);
2209 gfar_write(priv->hash_regs[whichreg], tempval);
2215 /* There are multiple MAC Address register pairs on some controllers
2216 * This function sets the numth pair to a given address
2218 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2220 struct gfar_private *priv = netdev_priv(dev);
2222 char tmpbuf[MAC_ADDR_LEN];
2224 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2228 /* Now copy it into the mac registers backwards, cuz */
2229 /* little endian is silly */
2230 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2231 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2233 gfar_write(macptr, *((u32 *) (tmpbuf)));
2235 tempval = *((u32 *) (tmpbuf + 4));
2237 gfar_write(macptr+1, tempval);
2240 /* GFAR error interrupt handler */
2241 static irqreturn_t gfar_error(int irq, void *dev_id)
2243 struct net_device *dev = dev_id;
2244 struct gfar_private *priv = netdev_priv(dev);
2246 /* Save ievent for future reference */
2247 u32 events = gfar_read(&priv->regs->ievent);
2250 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2252 /* Magic Packet is not an error. */
2253 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2254 (events & IEVENT_MAG))
2255 events &= ~IEVENT_MAG;
2258 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2259 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2260 dev->name, events, gfar_read(&priv->regs->imask));
2262 /* Update the error counters */
2263 if (events & IEVENT_TXE) {
2264 dev->stats.tx_errors++;
2266 if (events & IEVENT_LC)
2267 dev->stats.tx_window_errors++;
2268 if (events & IEVENT_CRL)
2269 dev->stats.tx_aborted_errors++;
2270 if (events & IEVENT_XFUN) {
2271 if (netif_msg_tx_err(priv))
2272 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2273 "packet dropped.\n", dev->name);
2274 dev->stats.tx_dropped++;
2275 priv->extra_stats.tx_underrun++;
2277 /* Reactivate the Tx Queues */
2278 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2280 if (netif_msg_tx_err(priv))
2281 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2283 if (events & IEVENT_BSY) {
2284 dev->stats.rx_errors++;
2285 priv->extra_stats.rx_bsy++;
2287 gfar_receive(irq, dev_id);
2289 if (netif_msg_rx_err(priv))
2290 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2291 dev->name, gfar_read(&priv->regs->rstat));
2293 if (events & IEVENT_BABR) {
2294 dev->stats.rx_errors++;
2295 priv->extra_stats.rx_babr++;
2297 if (netif_msg_rx_err(priv))
2298 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2300 if (events & IEVENT_EBERR) {
2301 priv->extra_stats.eberr++;
2302 if (netif_msg_rx_err(priv))
2303 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2305 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2306 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2308 if (events & IEVENT_BABT) {
2309 priv->extra_stats.tx_babt++;
2310 if (netif_msg_tx_err(priv))
2311 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2316 /* work with hotplug and coldplug */
2317 MODULE_ALIAS("platform:fsl-gianfar");
2319 static struct of_device_id gfar_match[] =
2323 .compatible = "gianfar",
2328 /* Structure for a device driver */
2329 static struct of_platform_driver gfar_driver = {
2330 .name = "fsl-gianfar",
2331 .match_table = gfar_match,
2333 .probe = gfar_probe,
2334 .remove = gfar_remove,
2335 .suspend = gfar_suspend,
2336 .resume = gfar_resume,
2339 static int __init gfar_init(void)
2341 return of_register_platform_driver(&gfar_driver);
2344 static void __exit gfar_exit(void)
2346 of_unregister_platform_driver(&gfar_driver);
2349 module_init(gfar_init);
2350 module_exit(gfar_exit);