1 // SPDX-License-Identifier: GPL-2.0+
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
10 #include <fdt_support.h>
14 #include <asm/cache.h>
18 #include <linux/bug.h>
20 #include "fsl_enetc.h"
22 #define ENETC_DRIVER_NAME "enetc_eth"
25 * sets the MAC address in IERB registers, this setting is persistent and
26 * carried over to Linux.
28 static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn,
31 #ifdef CONFIG_ARCH_LS1028A
33 * LS1028A is the only part with IERB at this time and there are plans to change
34 * its structure, keep this LS1028A specific for now
36 #define IERB_BASE 0x1f0800000ULL
37 #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \
40 static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
42 u16 lower = *(const u16 *)(enetaddr + 4);
43 u32 upper = *(const u32 *)enetaddr;
45 if (ierb_fn_to_pf[devfn] < 0)
48 out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper);
49 out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower);
53 /* sets up primary MAC addresses in DT/IERB */
54 void fdt_fixup_enetc_mac(void *blob)
56 struct pci_child_platdata *ppdata;
57 struct eth_pdata *pdata;
64 uclass_get(UCLASS_ETH, &uc);
65 uclass_foreach_dev(dev, uc) {
66 if (!dev->driver || !dev->driver->name ||
67 strcmp(dev->driver->name, ENETC_DRIVER_NAME))
70 pdata = dev_get_platdata(dev);
71 ppdata = dev_get_parent_platdata(dev);
72 devfn = PCI_FUNC(ppdata->devfn);
74 enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr);
76 snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x",
77 PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn));
78 offset = fdt_path_offset(blob, path);
81 fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6);
87 * - set a more explicit name on the interface
89 static int enetc_bind(struct udevice *dev)
92 static int eth_num_devices;
95 * prefer using PCI function numbers to number interfaces, but these
96 * are only available if dts nodes are present. For PCI they are
97 * optional, handle that case too. Just in case some nodes are present
98 * and some are not, use different naming scheme - enetc-N based on
99 * PCI function # and enetc#N based on interface count
101 if (ofnode_valid(dev->node))
102 sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
104 sprintf(name, "enetc#%u", eth_num_devices++);
105 device_set_name(dev, name);
110 /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
111 static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
113 struct enetc_mdio_priv priv;
115 priv.regs_base = bus->priv;
116 return enetc_mdio_read_priv(&priv, addr, devad, reg);
119 static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
122 struct enetc_mdio_priv priv;
124 priv.regs_base = bus->priv;
125 return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
128 /* only interfaces that can pin out through serdes have internal MDIO */
129 static bool enetc_has_imdio(struct udevice *dev)
131 struct enetc_priv *priv = dev_get_priv(dev);
133 return !!(priv->imdio.priv);
136 /* set up serdes for SGMII */
137 static int enetc_init_sgmii(struct udevice *dev)
139 struct enetc_priv *priv = dev_get_priv(dev);
143 if (!enetc_has_imdio(dev))
146 if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
150 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
151 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
152 * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
155 reg = ENETC_PCS_IF_MODE_SGMII;
156 reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
157 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
158 ENETC_PCS_IF_MODE, reg);
160 /* Dev ability - SGMII */
161 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
162 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
164 /* Adjust link timer for SGMII */
165 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
166 ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
167 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
168 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
170 reg = ENETC_PCS_CR_DEF_VAL;
171 reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
173 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
179 /* set up MAC for RGMII */
180 static int enetc_init_rgmii(struct udevice *dev)
182 struct enetc_priv *priv = dev_get_priv(dev);
185 /* enable RGMII AN */
186 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
187 if_mode |= ENETC_PM_IF_MODE_AN_ENA;
188 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
193 /* set up MAC configuration for the given interface type */
194 static void enetc_setup_mac_iface(struct udevice *dev)
196 struct enetc_priv *priv = dev_get_priv(dev);
199 switch (priv->if_type) {
200 case PHY_INTERFACE_MODE_RGMII:
201 case PHY_INTERFACE_MODE_RGMII_ID:
202 case PHY_INTERFACE_MODE_RGMII_RXID:
203 case PHY_INTERFACE_MODE_RGMII_TXID:
204 enetc_init_rgmii(dev);
206 case PHY_INTERFACE_MODE_XGMII:
207 case PHY_INTERFACE_MODE_USXGMII:
208 case PHY_INTERFACE_MODE_XFI:
209 /* set ifmode to (US)XGMII */
210 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
211 if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
212 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
217 /* set up serdes for SXGMII */
218 static int enetc_init_sxgmii(struct udevice *dev)
220 struct enetc_priv *priv = dev_get_priv(dev);
222 if (!enetc_has_imdio(dev))
225 /* Dev ability - SXGMII */
226 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
227 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
230 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
232 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
237 /* Apply protocol specific configuration to MAC, serdes as needed */
238 static void enetc_start_pcs(struct udevice *dev)
240 struct enetc_priv *priv = dev_get_priv(dev);
243 priv->if_type = PHY_INTERFACE_MODE_NONE;
245 /* register internal MDIO for debug purposes */
246 if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
247 priv->imdio.read = enetc_mdio_read;
248 priv->imdio.write = enetc_mdio_write;
249 priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
250 strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
251 if (!miiphy_get_dev_by_name(priv->imdio.name))
252 mdio_register(&priv->imdio);
255 if (!ofnode_valid(dev->node)) {
256 enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
260 if_str = ofnode_read_string(dev->node, "phy-mode");
262 priv->if_type = phy_get_interface_by_name(if_str);
265 "phy-mode property not found, defaulting to SGMII\n");
266 if (priv->if_type < 0)
267 priv->if_type = PHY_INTERFACE_MODE_NONE;
269 switch (priv->if_type) {
270 case PHY_INTERFACE_MODE_SGMII:
271 case PHY_INTERFACE_MODE_SGMII_2500:
272 enetc_init_sgmii(dev);
274 case PHY_INTERFACE_MODE_XGMII:
275 case PHY_INTERFACE_MODE_USXGMII:
276 case PHY_INTERFACE_MODE_XFI:
277 enetc_init_sxgmii(dev);
282 /* Configure the actual/external ethernet PHY, if one is found */
283 static void enetc_config_phy(struct udevice *dev)
285 struct enetc_priv *priv = dev_get_priv(dev);
288 priv->phy = dm_eth_phy_connect(dev);
293 supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
294 priv->phy->supported &= supported;
295 priv->phy->advertising &= supported;
297 phy_config(priv->phy);
301 * Probe ENETC driver:
302 * - initialize port and station interface BARs
304 static int enetc_probe(struct udevice *dev)
306 struct enetc_priv *priv = dev_get_priv(dev);
308 if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
309 enetc_dbg(dev, "interface disabled\n");
313 priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
314 sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
315 priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
316 sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
318 if (!priv->enetc_txbd || !priv->enetc_rxbd) {
319 /* free should be able to handle NULL, just free all pointers */
320 free(priv->enetc_txbd);
321 free(priv->enetc_rxbd);
326 /* initialize register */
327 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
328 if (!priv->regs_base) {
329 enetc_dbg(dev, "failed to map BAR0\n");
332 priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
334 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
336 enetc_start_pcs(dev);
337 enetc_config_phy(dev);
343 * Remove the driver from an interface:
344 * - free up allocated memory
346 static int enetc_remove(struct udevice *dev)
348 struct enetc_priv *priv = dev_get_priv(dev);
350 free(priv->enetc_txbd);
351 free(priv->enetc_rxbd);
357 * LS1028A is the only part with IERB at this time and there are plans to
358 * change its structure, keep this LS1028A specific for now.
360 #define LS1028A_IERB_BASE 0x1f0800000ULL
361 #define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \
362 + (pf) * 0x100 + (vf) * 8)
363 #define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4)
365 static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
367 struct pci_child_platdata *ppdata = dev_get_parent_platdata(dev);
368 const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
369 struct eth_pdata *plat = dev_get_platdata(dev);
370 int devfn = PCI_FUNC(ppdata->devfn);
371 u8 *addr = plat->enetaddr;
375 if (devfn >= ARRAY_SIZE(devfn_to_pf))
378 pf = devfn_to_pf[devfn];
382 lower = *(const u16 *)(addr + 4);
383 upper = *(const u32 *)addr;
385 out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper);
386 out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower);
391 static int enetc_write_hwaddr(struct udevice *dev)
393 struct eth_pdata *plat = dev_get_platdata(dev);
394 struct enetc_priv *priv = dev_get_priv(dev);
395 u8 *addr = plat->enetaddr;
397 if (IS_ENABLED(CONFIG_ARCH_LS1028A))
398 return enetc_ls1028a_write_hwaddr(dev);
400 u16 lower = *(const u16 *)(addr + 4);
401 u32 upper = *(const u32 *)addr;
403 enetc_write_port(priv, ENETC_PSIPMAR0, upper);
404 enetc_write_port(priv, ENETC_PSIPMAR1, lower);
409 /* Configure port parameters (# of rings, frame size, enable port) */
410 static void enetc_enable_si_port(struct enetc_priv *priv)
414 /* set Rx/Tx BDR count */
415 val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
416 val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
417 enetc_write_port(priv, ENETC_PSICFGR(0), val);
418 /* set Rx max frame size */
419 enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
420 /* enable MAC port */
421 enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
423 enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
424 /* set SI cache policy */
425 enetc_write(priv, ENETC_SICAR0,
426 ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
428 enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
431 /* returns DMA address for a given buffer index */
432 static inline u64 enetc_rxb_address(struct udevice *dev, int i)
434 return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
438 * Setup a single Tx BD Ring (ID = 0):
439 * - set Tx buffer descriptor address
441 * - initialize the producer and consumer index
443 static void enetc_setup_tx_bdr(struct udevice *dev)
445 struct enetc_priv *priv = dev_get_priv(dev);
446 struct bd_ring *tx_bdr = &priv->tx_bdr;
447 u64 tx_bd_add = (u64)priv->enetc_txbd;
449 /* used later to advance to the next Tx BD */
450 tx_bdr->bd_count = ENETC_BD_CNT;
451 tx_bdr->next_prod_idx = 0;
452 tx_bdr->next_cons_idx = 0;
453 tx_bdr->cons_idx = priv->regs_base +
454 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
455 tx_bdr->prod_idx = priv->regs_base +
456 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
458 /* set Tx BD address */
459 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
460 lower_32_bits(tx_bd_add));
461 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
462 upper_32_bits(tx_bd_add));
463 /* set Tx 8 BD count */
464 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
467 /* reset both producer/consumer indexes */
468 enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
469 enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
472 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
476 * Setup a single Rx BD Ring (ID = 0):
477 * - set Rx buffer descriptors address (one descriptor per buffer)
478 * - set buffer size as max frame size
480 * - reset consumer and producer indexes
481 * - set buffer for each descriptor
483 static void enetc_setup_rx_bdr(struct udevice *dev)
485 struct enetc_priv *priv = dev_get_priv(dev);
486 struct bd_ring *rx_bdr = &priv->rx_bdr;
487 u64 rx_bd_add = (u64)priv->enetc_rxbd;
490 /* used later to advance to the next BD produced by ENETC HW */
491 rx_bdr->bd_count = ENETC_BD_CNT;
492 rx_bdr->next_prod_idx = 0;
493 rx_bdr->next_cons_idx = 0;
494 rx_bdr->cons_idx = priv->regs_base +
495 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
496 rx_bdr->prod_idx = priv->regs_base +
497 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
499 /* set Rx BD address */
500 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
501 lower_32_bits(rx_bd_add));
502 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
503 upper_32_bits(rx_bd_add));
504 /* set Rx BD count (multiple of 8) */
505 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
507 /* set Rx buffer size */
508 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
511 memset(priv->enetc_rxbd, 0,
512 rx_bdr->bd_count * sizeof(union enetc_rx_bd));
513 for (i = 0; i < rx_bdr->bd_count; i++) {
514 priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
515 /* each RX buffer must be aligned to 64B */
516 WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
519 /* reset producer (ENETC owned) and consumer (SW owned) index */
520 enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
521 enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
524 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
528 * Start ENETC interface:
530 * - enable access to port and SI registers
532 * - setup TX/RX buffer descriptors
533 * - enable Tx/Rx rings
535 static int enetc_start(struct udevice *dev)
537 struct enetc_priv *priv = dev_get_priv(dev);
539 /* reset and enable the PCI device */
541 dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
542 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
544 enetc_enable_si_port(priv);
546 /* setup Tx/Rx buffer descriptors */
547 enetc_setup_tx_bdr(dev);
548 enetc_setup_rx_bdr(dev);
550 enetc_setup_mac_iface(dev);
553 phy_startup(priv->phy);
559 * Stop the network interface:
560 * - just quiesce it, we can wipe all configuration as _start starts from
563 static void enetc_stop(struct udevice *dev)
565 /* FLR is sufficient to quiesce the device */
567 /* leave the BARs accessible after we stop, this is needed to use
568 * internal MDIO in command line.
570 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
574 * ENETC transmit packet:
575 * - check if Tx BD ring is full
576 * - set buffer/packet address (dma address)
577 * - set final fragment flag
578 * - try while producer index equals consumer index or timeout
580 static int enetc_send(struct udevice *dev, void *packet, int length)
582 struct enetc_priv *priv = dev_get_priv(dev);
583 struct bd_ring *txr = &priv->tx_bdr;
584 void *nv_packet = (void *)packet;
585 int tries = ENETC_POLL_TRIES;
588 pi = txr->next_prod_idx;
589 ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
590 /* Tx ring is full when */
591 if (((pi + 1) % txr->bd_count) == ci) {
592 enetc_dbg(dev, "Tx BDR full\n");
595 enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
596 upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
599 memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
600 priv->enetc_txbd[pi].addr =
601 cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
602 priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
603 priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
604 priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
606 /* send frame: increment producer index */
607 pi = (pi + 1) % txr->bd_count;
608 txr->next_prod_idx = pi;
609 enetc_write_reg(txr->prod_idx, pi);
610 while ((--tries >= 0) &&
611 (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
614 return tries > 0 ? 0 : -ETIMEDOUT;
619 * - wait for the next BD to get ready bit set
620 * - clean up the descriptor
621 * - move on and indicate to HW that the cleaned BD is available for Rx
623 static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
625 struct enetc_priv *priv = dev_get_priv(dev);
626 struct bd_ring *rxr = &priv->rx_bdr;
627 int tries = ENETC_POLL_TRIES;
628 int pi = rxr->next_prod_idx;
629 int ci = rxr->next_cons_idx;
636 status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
637 /* check if current BD is ready to be consumed */
638 rdy = ENETC_RXBD_STATUS_R(status);
639 } while (--tries >= 0 && !rdy);
645 len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
646 *packetp = (uchar *)enetc_rxb_address(dev, pi);
647 enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
648 ENETC_RXBD_STATUS_ERRORS(status),
649 upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
651 /* BD clean up and advance to next in ring */
652 memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
653 priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
654 rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
655 ci = (ci + 1) % rxr->bd_count;
656 rxr->next_cons_idx = ci;
658 /* free up the slot in the ring for HW */
659 enetc_write_reg(rxr->cons_idx, ci);
664 static const struct eth_ops enetc_ops = {
665 .start = enetc_start,
669 .write_hwaddr = enetc_write_hwaddr,
672 U_BOOT_DRIVER(eth_enetc) = {
673 .name = ENETC_DRIVER_NAME,
676 .probe = enetc_probe,
677 .remove = enetc_remove,
679 .priv_auto_alloc_size = sizeof(struct enetc_priv),
680 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
683 static struct pci_device_id enetc_ids[] = {
684 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
688 U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);