2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <asm/cacheflush.h>
51 #include <asm/coldfire.h>
52 #include <asm/mcfsim.h>
57 #if defined(CONFIG_ARM)
58 #define FEC_ALIGNMENT 0xf
60 #define FEC_ALIGNMENT 0x3
63 #define DRIVER_NAME "fec"
65 /* Controller is ENET-MAC */
66 #define FEC_QUIRK_ENET_MAC (1 << 0)
67 /* Controller needs driver to swap frame */
68 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
70 static struct platform_device_id fec_devtype[] = {
76 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
80 static unsigned char macaddr[ETH_ALEN];
81 module_param_array(macaddr, byte, NULL, 0);
82 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
84 #if defined(CONFIG_M5272)
86 * Some hardware gets it MAC address out of local flash memory.
87 * if this is non-zero then assume it is the address to get MAC from.
89 #if defined(CONFIG_NETtel)
90 #define FEC_FLASHMAC 0xf0006006
91 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
92 #define FEC_FLASHMAC 0xf0006000
93 #elif defined(CONFIG_CANCam)
94 #define FEC_FLASHMAC 0xf0020000
95 #elif defined (CONFIG_M5272C3)
96 #define FEC_FLASHMAC (0xffe04000 + 4)
97 #elif defined(CONFIG_MOD5272)
98 #define FEC_FLASHMAC 0xffc0406b
100 #define FEC_FLASHMAC 0
102 #endif /* CONFIG_M5272 */
104 /* The number of Tx and Rx buffers. These are allocated from the page
105 * pool. The code may assume these are power of two, so it it best
106 * to keep them that size.
107 * We don't need to allocate pages for the transmitter. We just use
108 * the skbuffer directly.
110 #define FEC_ENET_RX_PAGES 8
111 #define FEC_ENET_RX_FRSIZE 2048
112 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
113 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
114 #define FEC_ENET_TX_FRSIZE 2048
115 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
116 #define TX_RING_SIZE 16 /* Must be power of two */
117 #define TX_RING_MOD_MASK 15 /* for this to work */
119 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
120 #error "FEC: descriptor ring size constants too large"
123 /* Interrupt events/masks. */
124 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
125 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
126 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
127 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
128 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
129 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
130 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
131 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
132 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
133 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
135 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
137 /* The FEC stores dest/src/type, data, and checksum for receive packets.
139 #define PKT_MAXBUF_SIZE 1518
140 #define PKT_MINBUF_SIZE 64
141 #define PKT_MAXBLR_SIZE 1520
145 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
146 * size bits. Other FEC hardware does not, so we need to take that into
147 * account when setting it.
149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
151 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
153 #define OPT_FRAME_SIZE 0
156 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
157 * tx_bd_base always point to the base of the buffer descriptors. The
158 * cur_rx and cur_tx point to the currently available buffer.
159 * The dirty_tx tracks the current buffer that is being sent by the
160 * controller. The cur_tx and dirty_tx are equal under both completely
161 * empty and completely full conditions. The empty/ready indicator in
162 * the buffer descriptor determines the actual condition.
164 struct fec_enet_private {
165 /* Hardware registers of the FEC device */
168 struct net_device *netdev;
172 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
173 unsigned char *tx_bounce[TX_RING_SIZE];
174 struct sk_buff* tx_skbuff[TX_RING_SIZE];
175 struct sk_buff* rx_skbuff[RX_RING_SIZE];
179 /* CPM dual port RAM relative addresses */
181 /* Address of Rx and Tx buffers */
182 struct bufdesc *rx_bd_base;
183 struct bufdesc *tx_bd_base;
184 /* The next free ring entry */
185 struct bufdesc *cur_rx, *cur_tx;
186 /* The ring entries to be free()ed */
187 struct bufdesc *dirty_tx;
190 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
193 struct platform_device *pdev;
197 /* Phylib and MDIO interface */
198 struct mii_bus *mii_bus;
199 struct phy_device *phy_dev;
202 phy_interface_t phy_interface;
205 struct completion mdio_done;
208 /* FEC MII MMFR bits definition */
209 #define FEC_MMFR_ST (1 << 30)
210 #define FEC_MMFR_OP_READ (2 << 28)
211 #define FEC_MMFR_OP_WRITE (1 << 28)
212 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
213 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
214 #define FEC_MMFR_TA (2 << 16)
215 #define FEC_MMFR_DATA(v) (v & 0xffff)
217 #define FEC_MII_TIMEOUT 1000 /* us */
219 /* Transmitter timeout */
220 #define TX_TIMEOUT (2 * HZ)
222 static void *swap_buffer(void *bufaddr, int len)
225 unsigned int *buf = bufaddr;
227 for (i = 0; i < (len + 3) / 4; i++, buf++)
228 *buf = cpu_to_be32(*buf);
234 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
236 struct fec_enet_private *fep = netdev_priv(ndev);
237 const struct platform_device_id *id_entry =
238 platform_get_device_id(fep->pdev);
241 unsigned short status;
245 /* Link is down or autonegotiation is in progress. */
246 return NETDEV_TX_BUSY;
249 spin_lock_irqsave(&fep->hw_lock, flags);
250 /* Fill in a Tx ring entry */
253 status = bdp->cbd_sc;
255 if (status & BD_ENET_TX_READY) {
256 /* Ooops. All transmit buffers are full. Bail out.
257 * This should not happen, since ndev->tbusy should be set.
259 printk("%s: tx queue full!.\n", ndev->name);
260 spin_unlock_irqrestore(&fep->hw_lock, flags);
261 return NETDEV_TX_BUSY;
264 /* Clear all of the status flags */
265 status &= ~BD_ENET_TX_STATS;
267 /* Set buffer length and buffer pointer */
269 bdp->cbd_datlen = skb->len;
272 * On some FEC implementations data must be aligned on
273 * 4-byte boundaries. Use bounce buffers to copy data
274 * and get it aligned. Ugh.
276 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
278 index = bdp - fep->tx_bd_base;
279 memcpy(fep->tx_bounce[index], skb->data, skb->len);
280 bufaddr = fep->tx_bounce[index];
284 * Some design made an incorrect assumption on endian mode of
285 * the system that it's running on. As the result, driver has to
286 * swap every frame going to and coming from the controller.
288 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
289 swap_buffer(bufaddr, skb->len);
291 /* Save skb pointer */
292 fep->tx_skbuff[fep->skb_cur] = skb;
294 ndev->stats.tx_bytes += skb->len;
295 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK;
297 /* Push the data cache so the CPM does not get stale memory
300 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
301 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
303 /* Send it on its way. Tell FEC it's ready, interrupt when done,
304 * it's the last BD of the frame, and to put the CRC on the end.
306 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
307 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
308 bdp->cbd_sc = status;
310 /* Trigger transmission start */
311 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
313 /* If this was the last BD in the ring, start at the beginning again. */
314 if (status & BD_ENET_TX_WRAP)
315 bdp = fep->tx_bd_base;
319 if (bdp == fep->dirty_tx) {
321 netif_stop_queue(ndev);
326 spin_unlock_irqrestore(&fep->hw_lock, flags);
331 /* This function is called to start or restart the FEC during a link
332 * change. This only happens when switching between half and full
336 fec_restart(struct net_device *ndev, int duplex)
338 struct fec_enet_private *fep = netdev_priv(ndev);
339 const struct platform_device_id *id_entry =
340 platform_get_device_id(fep->pdev);
342 u32 val, temp_mac[2];
344 /* Whack a reset. We should wait for this. */
345 writel(1, fep->hwp + FEC_ECNTRL);
349 * enet-mac reset will reset mac address registers too,
350 * so need to reconfigure it.
352 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
353 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
354 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
355 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
358 /* Clear any outstanding interrupt. */
359 writel(0xffc00000, fep->hwp + FEC_IEVENT);
361 /* Reset all multicast. */
362 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
363 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
365 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
366 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
369 /* Set maximum receive buffer size. */
370 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
372 /* Set receive and transmit descriptor base. */
373 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
374 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE,
375 fep->hwp + FEC_X_DES_START);
377 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base;
378 fep->cur_rx = fep->rx_bd_base;
380 /* Reset SKB transmit buffers. */
381 fep->skb_cur = fep->skb_dirty = 0;
382 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
383 if (fep->tx_skbuff[i]) {
384 dev_kfree_skb_any(fep->tx_skbuff[i]);
385 fep->tx_skbuff[i] = NULL;
389 /* Enable MII mode */
391 /* MII enable / FD enable */
392 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL);
393 writel(0x04, fep->hwp + FEC_X_CNTRL);
395 /* MII enable / No Rcv on Xmit */
396 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL);
397 writel(0x0, fep->hwp + FEC_X_CNTRL);
399 fep->full_duplex = duplex;
402 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
405 * The phy interface and speed need to get configured
406 * differently on enet-mac.
408 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
409 val = readl(fep->hwp + FEC_R_CNTRL);
412 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
418 if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
423 writel(val, fep->hwp + FEC_R_CNTRL);
425 #ifdef FEC_MIIGSK_ENR
426 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
427 /* disable the gasket and wait */
428 writel(0, fep->hwp + FEC_MIIGSK_ENR);
429 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
433 * configure the gasket:
434 * RMII, 50 MHz, no loopback, no echo
436 writel(1, fep->hwp + FEC_MIIGSK_CFGR);
438 /* re-enable the gasket */
439 writel(2, fep->hwp + FEC_MIIGSK_ENR);
444 /* And last, enable the transmit and receive processing */
445 writel(2, fep->hwp + FEC_ECNTRL);
446 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
448 /* Enable interrupts we wish to service */
449 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
453 fec_stop(struct net_device *ndev)
455 struct fec_enet_private *fep = netdev_priv(ndev);
457 /* We cannot expect a graceful transmit stop without link !!! */
459 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
461 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
462 printk("fec_stop : Graceful transmit stop did not complete !\n");
465 /* Whack a reset. We should wait for this. */
466 writel(1, fep->hwp + FEC_ECNTRL);
468 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
469 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
474 fec_timeout(struct net_device *ndev)
476 struct fec_enet_private *fep = netdev_priv(ndev);
478 ndev->stats.tx_errors++;
480 fec_restart(ndev, fep->full_duplex);
481 netif_wake_queue(ndev);
485 fec_enet_tx(struct net_device *ndev)
487 struct fec_enet_private *fep;
489 unsigned short status;
492 fep = netdev_priv(ndev);
493 spin_lock(&fep->hw_lock);
496 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
497 if (bdp == fep->cur_tx && fep->tx_full == 0)
500 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
501 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
502 bdp->cbd_bufaddr = 0;
504 skb = fep->tx_skbuff[fep->skb_dirty];
505 /* Check for errors. */
506 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
507 BD_ENET_TX_RL | BD_ENET_TX_UN |
509 ndev->stats.tx_errors++;
510 if (status & BD_ENET_TX_HB) /* No heartbeat */
511 ndev->stats.tx_heartbeat_errors++;
512 if (status & BD_ENET_TX_LC) /* Late collision */
513 ndev->stats.tx_window_errors++;
514 if (status & BD_ENET_TX_RL) /* Retrans limit */
515 ndev->stats.tx_aborted_errors++;
516 if (status & BD_ENET_TX_UN) /* Underrun */
517 ndev->stats.tx_fifo_errors++;
518 if (status & BD_ENET_TX_CSL) /* Carrier lost */
519 ndev->stats.tx_carrier_errors++;
521 ndev->stats.tx_packets++;
524 if (status & BD_ENET_TX_READY)
525 printk("HEY! Enet xmit interrupt and TX_READY.\n");
527 /* Deferred means some collisions occurred during transmit,
528 * but we eventually sent the packet OK.
530 if (status & BD_ENET_TX_DEF)
531 ndev->stats.collisions++;
533 /* Free the sk buffer associated with this last transmit */
534 dev_kfree_skb_any(skb);
535 fep->tx_skbuff[fep->skb_dirty] = NULL;
536 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK;
538 /* Update pointer to next buffer descriptor to be transmitted */
539 if (status & BD_ENET_TX_WRAP)
540 bdp = fep->tx_bd_base;
544 /* Since we have freed up a buffer, the ring is no longer full
548 if (netif_queue_stopped(ndev))
549 netif_wake_queue(ndev);
553 spin_unlock(&fep->hw_lock);
557 /* During a receive, the cur_rx points to the current incoming buffer.
558 * When we update through the ring, if the next incoming buffer has
559 * not been given to the system, we just set the empty indicator,
560 * effectively tossing the packet.
563 fec_enet_rx(struct net_device *ndev)
565 struct fec_enet_private *fep = netdev_priv(ndev);
566 const struct platform_device_id *id_entry =
567 platform_get_device_id(fep->pdev);
569 unsigned short status;
578 spin_lock(&fep->hw_lock);
580 /* First, grab all of the stats for the incoming packet.
581 * These get messed up if we get called due to a busy condition.
585 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
587 /* Since we have allocated space to hold a complete frame,
588 * the last indicator should be set.
590 if ((status & BD_ENET_RX_LAST) == 0)
591 printk("FEC ENET: rcv is not +last\n");
594 goto rx_processing_done;
596 /* Check for errors. */
597 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
598 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
599 ndev->stats.rx_errors++;
600 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
601 /* Frame too long or too short. */
602 ndev->stats.rx_length_errors++;
604 if (status & BD_ENET_RX_NO) /* Frame alignment */
605 ndev->stats.rx_frame_errors++;
606 if (status & BD_ENET_RX_CR) /* CRC Error */
607 ndev->stats.rx_crc_errors++;
608 if (status & BD_ENET_RX_OV) /* FIFO overrun */
609 ndev->stats.rx_fifo_errors++;
612 /* Report late collisions as a frame error.
613 * On this error, the BD is closed, but we don't know what we
614 * have in the buffer. So, just drop this frame on the floor.
616 if (status & BD_ENET_RX_CL) {
617 ndev->stats.rx_errors++;
618 ndev->stats.rx_frame_errors++;
619 goto rx_processing_done;
622 /* Process the incoming frame. */
623 ndev->stats.rx_packets++;
624 pkt_len = bdp->cbd_datlen;
625 ndev->stats.rx_bytes += pkt_len;
626 data = (__u8*)__va(bdp->cbd_bufaddr);
628 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
629 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
631 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
632 swap_buffer(data, pkt_len);
634 /* This does 16 byte alignment, exactly what we need.
635 * The packet length includes FCS, but we don't want to
636 * include that when passing upstream as it messes up
637 * bridging applications.
639 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN);
641 if (unlikely(!skb)) {
642 printk("%s: Memory squeeze, dropping packet.\n",
644 ndev->stats.rx_dropped++;
646 skb_reserve(skb, NET_IP_ALIGN);
647 skb_put(skb, pkt_len - 4); /* Make room */
648 skb_copy_to_linear_data(skb, data, pkt_len - 4);
649 skb->protocol = eth_type_trans(skb, ndev);
653 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
654 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
656 /* Clear the status flags for this buffer */
657 status &= ~BD_ENET_RX_STATS;
659 /* Mark the buffer empty */
660 status |= BD_ENET_RX_EMPTY;
661 bdp->cbd_sc = status;
663 /* Update BD pointer to next entry */
664 if (status & BD_ENET_RX_WRAP)
665 bdp = fep->rx_bd_base;
668 /* Doing this here will keep the FEC running while we process
669 * incoming frames. On a heavily loaded network, we should be
670 * able to keep up at the expense of system resources.
672 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
676 spin_unlock(&fep->hw_lock);
680 fec_enet_interrupt(int irq, void *dev_id)
682 struct net_device *ndev = dev_id;
683 struct fec_enet_private *fep = netdev_priv(ndev);
685 irqreturn_t ret = IRQ_NONE;
688 int_events = readl(fep->hwp + FEC_IEVENT);
689 writel(int_events, fep->hwp + FEC_IEVENT);
691 if (int_events & FEC_ENET_RXF) {
696 /* Transmit OK, or non-fatal error. Update the buffer
697 * descriptors. FEC handles all errors, we just discover
698 * them as part of the transmit process.
700 if (int_events & FEC_ENET_TXF) {
705 if (int_events & FEC_ENET_MII) {
707 complete(&fep->mdio_done);
709 } while (int_events);
716 /* ------------------------------------------------------------------------- */
717 static void __inline__ fec_get_mac(struct net_device *ndev)
719 struct fec_enet_private *fep = netdev_priv(ndev);
720 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
721 unsigned char *iap, tmpaddr[ETH_ALEN];
724 * try to get mac address in following order:
726 * 1) module parameter via kernel command line in form
727 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
732 * 2) from flash or fuse (via platform data)
734 if (!is_valid_ether_addr(iap)) {
737 iap = (unsigned char *)FEC_FLASHMAC;
740 memcpy(iap, pdata->mac, ETH_ALEN);
745 * 3) FEC mac registers set by bootloader
747 if (!is_valid_ether_addr(iap)) {
748 *((unsigned long *) &tmpaddr[0]) =
749 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
750 *((unsigned short *) &tmpaddr[4]) =
751 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
755 memcpy(ndev->dev_addr, iap, ETH_ALEN);
757 /* Adjust MAC if using macaddr */
759 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
762 /* ------------------------------------------------------------------------- */
767 static void fec_enet_adjust_link(struct net_device *ndev)
769 struct fec_enet_private *fep = netdev_priv(ndev);
770 struct phy_device *phy_dev = fep->phy_dev;
773 int status_change = 0;
775 spin_lock_irqsave(&fep->hw_lock, flags);
777 /* Prevent a state halted on mii error */
778 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
779 phy_dev->state = PHY_RESUMING;
783 /* Duplex link change */
785 if (fep->full_duplex != phy_dev->duplex) {
786 fec_restart(ndev, phy_dev->duplex);
791 /* Link on or off change */
792 if (phy_dev->link != fep->link) {
793 fep->link = phy_dev->link;
795 fec_restart(ndev, phy_dev->duplex);
802 spin_unlock_irqrestore(&fep->hw_lock, flags);
805 phy_print_status(phy_dev);
808 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
810 struct fec_enet_private *fep = bus->priv;
811 unsigned long time_left;
813 fep->mii_timeout = 0;
814 init_completion(&fep->mdio_done);
816 /* start a read op */
817 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
818 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
819 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
821 /* wait for end of transfer */
822 time_left = wait_for_completion_timeout(&fep->mdio_done,
823 usecs_to_jiffies(FEC_MII_TIMEOUT));
824 if (time_left == 0) {
825 fep->mii_timeout = 1;
826 printk(KERN_ERR "FEC: MDIO read timeout\n");
831 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
834 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
837 struct fec_enet_private *fep = bus->priv;
838 unsigned long time_left;
840 fep->mii_timeout = 0;
841 init_completion(&fep->mdio_done);
843 /* start a write op */
844 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
845 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
846 FEC_MMFR_TA | FEC_MMFR_DATA(value),
847 fep->hwp + FEC_MII_DATA);
849 /* wait for end of transfer */
850 time_left = wait_for_completion_timeout(&fep->mdio_done,
851 usecs_to_jiffies(FEC_MII_TIMEOUT));
852 if (time_left == 0) {
853 fep->mii_timeout = 1;
854 printk(KERN_ERR "FEC: MDIO write timeout\n");
861 static int fec_enet_mdio_reset(struct mii_bus *bus)
866 static int fec_enet_mii_probe(struct net_device *ndev)
868 struct fec_enet_private *fep = netdev_priv(ndev);
869 struct phy_device *phy_dev = NULL;
870 char mdio_bus_id[MII_BUS_ID_SIZE];
871 char phy_name[MII_BUS_ID_SIZE + 3];
873 int dev_id = fep->pdev->id;
877 /* check for attached phy */
878 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
879 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
881 if (fep->mii_bus->phy_map[phy_id] == NULL)
883 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
887 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
891 if (phy_id >= PHY_MAX_ADDR) {
892 printk(KERN_INFO "%s: no PHY, assuming direct connection "
893 "to switch\n", ndev->name);
894 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE);
898 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
899 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link, 0,
900 PHY_INTERFACE_MODE_MII);
901 if (IS_ERR(phy_dev)) {
902 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
903 return PTR_ERR(phy_dev);
906 /* mask with MAC supported features */
907 phy_dev->supported &= PHY_BASIC_FEATURES;
908 phy_dev->advertising = phy_dev->supported;
910 fep->phy_dev = phy_dev;
912 fep->full_duplex = 0;
914 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] "
915 "(mii_bus:phy_addr=%s, irq=%d)\n", ndev->name,
916 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
922 static int fec_enet_mii_init(struct platform_device *pdev)
924 static struct mii_bus *fec0_mii_bus;
925 struct net_device *ndev = platform_get_drvdata(pdev);
926 struct fec_enet_private *fep = netdev_priv(ndev);
927 const struct platform_device_id *id_entry =
928 platform_get_device_id(fep->pdev);
932 * The dual fec interfaces are not equivalent with enet-mac.
933 * Here are the differences:
935 * - fec0 supports MII & RMII modes while fec1 only supports RMII
936 * - fec0 acts as the 1588 time master while fec1 is slave
937 * - external phys can only be configured by fec0
939 * That is to say fec1 can not work independently. It only works
940 * when fec0 is working. The reason behind this design is that the
941 * second interface is added primarily for Switch mode.
943 * Because of the last point above, both phys are attached on fec0
944 * mdio interface in board design, and need to be configured by
947 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
948 /* fec1 uses fec0 mii_bus */
949 fep->mii_bus = fec0_mii_bus;
953 fep->mii_timeout = 0;
956 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
958 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1;
959 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
961 fep->mii_bus = mdiobus_alloc();
962 if (fep->mii_bus == NULL) {
967 fep->mii_bus->name = "fec_enet_mii_bus";
968 fep->mii_bus->read = fec_enet_mdio_read;
969 fep->mii_bus->write = fec_enet_mdio_write;
970 fep->mii_bus->reset = fec_enet_mdio_reset;
971 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1);
972 fep->mii_bus->priv = fep;
973 fep->mii_bus->parent = &pdev->dev;
975 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
976 if (!fep->mii_bus->irq) {
978 goto err_out_free_mdiobus;
981 for (i = 0; i < PHY_MAX_ADDR; i++)
982 fep->mii_bus->irq[i] = PHY_POLL;
984 platform_set_drvdata(ndev, fep->mii_bus);
986 if (mdiobus_register(fep->mii_bus))
987 goto err_out_free_mdio_irq;
989 /* save fec0 mii_bus */
990 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
991 fec0_mii_bus = fep->mii_bus;
995 err_out_free_mdio_irq:
996 kfree(fep->mii_bus->irq);
997 err_out_free_mdiobus:
998 mdiobus_free(fep->mii_bus);
1003 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1006 phy_disconnect(fep->phy_dev);
1007 mdiobus_unregister(fep->mii_bus);
1008 kfree(fep->mii_bus->irq);
1009 mdiobus_free(fep->mii_bus);
1012 static int fec_enet_get_settings(struct net_device *ndev,
1013 struct ethtool_cmd *cmd)
1015 struct fec_enet_private *fep = netdev_priv(ndev);
1016 struct phy_device *phydev = fep->phy_dev;
1021 return phy_ethtool_gset(phydev, cmd);
1024 static int fec_enet_set_settings(struct net_device *ndev,
1025 struct ethtool_cmd *cmd)
1027 struct fec_enet_private *fep = netdev_priv(ndev);
1028 struct phy_device *phydev = fep->phy_dev;
1033 return phy_ethtool_sset(phydev, cmd);
1036 static void fec_enet_get_drvinfo(struct net_device *ndev,
1037 struct ethtool_drvinfo *info)
1039 struct fec_enet_private *fep = netdev_priv(ndev);
1041 strcpy(info->driver, fep->pdev->dev.driver->name);
1042 strcpy(info->version, "Revision: 1.0");
1043 strcpy(info->bus_info, dev_name(&ndev->dev));
1046 static struct ethtool_ops fec_enet_ethtool_ops = {
1047 .get_settings = fec_enet_get_settings,
1048 .set_settings = fec_enet_set_settings,
1049 .get_drvinfo = fec_enet_get_drvinfo,
1050 .get_link = ethtool_op_get_link,
1053 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1055 struct fec_enet_private *fep = netdev_priv(ndev);
1056 struct phy_device *phydev = fep->phy_dev;
1058 if (!netif_running(ndev))
1064 return phy_mii_ioctl(phydev, rq, cmd);
1067 static void fec_enet_free_buffers(struct net_device *ndev)
1069 struct fec_enet_private *fep = netdev_priv(ndev);
1071 struct sk_buff *skb;
1072 struct bufdesc *bdp;
1074 bdp = fep->rx_bd_base;
1075 for (i = 0; i < RX_RING_SIZE; i++) {
1076 skb = fep->rx_skbuff[i];
1078 if (bdp->cbd_bufaddr)
1079 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1080 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1086 bdp = fep->tx_bd_base;
1087 for (i = 0; i < TX_RING_SIZE; i++)
1088 kfree(fep->tx_bounce[i]);
1091 static int fec_enet_alloc_buffers(struct net_device *ndev)
1093 struct fec_enet_private *fep = netdev_priv(ndev);
1095 struct sk_buff *skb;
1096 struct bufdesc *bdp;
1098 bdp = fep->rx_bd_base;
1099 for (i = 0; i < RX_RING_SIZE; i++) {
1100 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE);
1102 fec_enet_free_buffers(ndev);
1105 fep->rx_skbuff[i] = skb;
1107 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1108 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1109 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1113 /* Set the last buffer to wrap. */
1115 bdp->cbd_sc |= BD_SC_WRAP;
1117 bdp = fep->tx_bd_base;
1118 for (i = 0; i < TX_RING_SIZE; i++) {
1119 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1122 bdp->cbd_bufaddr = 0;
1126 /* Set the last buffer to wrap. */
1128 bdp->cbd_sc |= BD_SC_WRAP;
1134 fec_enet_open(struct net_device *ndev)
1136 struct fec_enet_private *fep = netdev_priv(ndev);
1139 /* I should reset the ring buffers here, but I don't yet know
1140 * a simple way to do that.
1143 ret = fec_enet_alloc_buffers(ndev);
1147 /* Probe and connect to PHY when open the interface */
1148 ret = fec_enet_mii_probe(ndev);
1150 fec_enet_free_buffers(ndev);
1153 phy_start(fep->phy_dev);
1154 netif_start_queue(ndev);
1160 fec_enet_close(struct net_device *ndev)
1162 struct fec_enet_private *fep = netdev_priv(ndev);
1164 /* Don't know what to do yet. */
1166 netif_stop_queue(ndev);
1170 phy_stop(fep->phy_dev);
1171 phy_disconnect(fep->phy_dev);
1174 fec_enet_free_buffers(ndev);
1179 /* Set or clear the multicast filter for this adaptor.
1180 * Skeleton taken from sunlance driver.
1181 * The CPM Ethernet implementation allows Multicast as well as individual
1182 * MAC address filtering. Some of the drivers check to make sure it is
1183 * a group multicast address, and discard those that are not. I guess I
1184 * will do the same for now, but just remove the test if you want
1185 * individual filtering as well (do the upper net layers want or support
1186 * this kind of feature?).
1189 #define HASH_BITS 6 /* #bits in hash */
1190 #define CRC32_POLY 0xEDB88320
1192 static void set_multicast_list(struct net_device *ndev)
1194 struct fec_enet_private *fep = netdev_priv(ndev);
1195 struct netdev_hw_addr *ha;
1196 unsigned int i, bit, data, crc, tmp;
1199 if (ndev->flags & IFF_PROMISC) {
1200 tmp = readl(fep->hwp + FEC_R_CNTRL);
1202 writel(tmp, fep->hwp + FEC_R_CNTRL);
1206 tmp = readl(fep->hwp + FEC_R_CNTRL);
1208 writel(tmp, fep->hwp + FEC_R_CNTRL);
1210 if (ndev->flags & IFF_ALLMULTI) {
1211 /* Catch all multicast addresses, so set the
1214 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1215 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1220 /* Clear filter and add the addresses in hash register
1222 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1223 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1225 netdev_for_each_mc_addr(ha, ndev) {
1226 /* Only support group multicast for now */
1227 if (!(ha->addr[0] & 1))
1230 /* calculate crc32 value of mac address */
1233 for (i = 0; i < ndev->addr_len; i++) {
1235 for (bit = 0; bit < 8; bit++, data >>= 1) {
1237 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1241 /* only upper 6 bits (HASH_BITS) are used
1242 * which point to specific bit in he hash registers
1244 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1247 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1248 tmp |= 1 << (hash - 32);
1249 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1251 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1253 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1258 /* Set a MAC change in hardware. */
1260 fec_set_mac_address(struct net_device *ndev, void *p)
1262 struct fec_enet_private *fep = netdev_priv(ndev);
1263 struct sockaddr *addr = p;
1265 if (!is_valid_ether_addr(addr->sa_data))
1266 return -EADDRNOTAVAIL;
1268 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1270 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1271 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1272 fep->hwp + FEC_ADDR_LOW);
1273 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1274 fep->hwp + FEC_ADDR_HIGH);
1278 static const struct net_device_ops fec_netdev_ops = {
1279 .ndo_open = fec_enet_open,
1280 .ndo_stop = fec_enet_close,
1281 .ndo_start_xmit = fec_enet_start_xmit,
1282 .ndo_set_multicast_list = set_multicast_list,
1283 .ndo_change_mtu = eth_change_mtu,
1284 .ndo_validate_addr = eth_validate_addr,
1285 .ndo_tx_timeout = fec_timeout,
1286 .ndo_set_mac_address = fec_set_mac_address,
1287 .ndo_do_ioctl = fec_enet_ioctl,
1291 * XXX: We need to clean up on failure exits here.
1294 static int fec_enet_init(struct net_device *ndev)
1296 struct fec_enet_private *fep = netdev_priv(ndev);
1297 struct bufdesc *cbd_base;
1298 struct bufdesc *bdp;
1301 /* Allocate memory for buffer descriptors. */
1302 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1305 printk("FEC: allocate descriptor memory failed?\n");
1309 spin_lock_init(&fep->hw_lock);
1313 /* Get the Ethernet address */
1316 /* Set receive and transmit descriptor base. */
1317 fep->rx_bd_base = cbd_base;
1318 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1320 /* The FEC Ethernet specific entries in the device structure */
1321 ndev->watchdog_timeo = TX_TIMEOUT;
1322 ndev->netdev_ops = &fec_netdev_ops;
1323 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1325 /* Initialize the receive buffer descriptors. */
1326 bdp = fep->rx_bd_base;
1327 for (i = 0; i < RX_RING_SIZE; i++) {
1329 /* Initialize the BD for every fragment in the page. */
1334 /* Set the last buffer to wrap */
1336 bdp->cbd_sc |= BD_SC_WRAP;
1338 /* ...and the same for transmit */
1339 bdp = fep->tx_bd_base;
1340 for (i = 0; i < TX_RING_SIZE; i++) {
1342 /* Initialize the BD for every fragment in the page. */
1344 bdp->cbd_bufaddr = 0;
1348 /* Set the last buffer to wrap */
1350 bdp->cbd_sc |= BD_SC_WRAP;
1352 fec_restart(ndev, 0);
1357 static int __devinit
1358 fec_probe(struct platform_device *pdev)
1360 struct fec_enet_private *fep;
1361 struct fec_platform_data *pdata;
1362 struct net_device *ndev;
1363 int i, irq, ret = 0;
1366 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370 r = request_mem_region(r->start, resource_size(r), pdev->name);
1374 /* Init network device */
1375 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1378 goto failed_alloc_etherdev;
1381 SET_NETDEV_DEV(ndev, &pdev->dev);
1383 /* setup board info structure */
1384 fep = netdev_priv(ndev);
1386 fep->hwp = ioremap(r->start, resource_size(r));
1391 goto failed_ioremap;
1394 platform_set_drvdata(pdev, ndev);
1396 pdata = pdev->dev.platform_data;
1398 fep->phy_interface = pdata->phy;
1400 /* This device has up to three irqs on some platforms */
1401 for (i = 0; i < 3; i++) {
1402 irq = platform_get_irq(pdev, i);
1405 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1408 irq = platform_get_irq(pdev, i);
1409 free_irq(irq, ndev);
1415 fep->clk = clk_get(&pdev->dev, "fec_clk");
1416 if (IS_ERR(fep->clk)) {
1417 ret = PTR_ERR(fep->clk);
1420 clk_enable(fep->clk);
1422 ret = fec_enet_init(ndev);
1426 ret = fec_enet_mii_init(pdev);
1428 goto failed_mii_init;
1430 /* Carrier starts down, phylib will bring it up */
1431 netif_carrier_off(ndev);
1433 ret = register_netdev(ndev);
1435 goto failed_register;
1440 fec_enet_mii_remove(fep);
1443 clk_disable(fep->clk);
1446 for (i = 0; i < 3; i++) {
1447 irq = platform_get_irq(pdev, i);
1449 free_irq(irq, ndev);
1455 failed_alloc_etherdev:
1456 release_mem_region(r->start, resource_size(r));
1461 static int __devexit
1462 fec_drv_remove(struct platform_device *pdev)
1464 struct net_device *ndev = platform_get_drvdata(pdev);
1465 struct fec_enet_private *fep = netdev_priv(ndev);
1468 platform_set_drvdata(pdev, NULL);
1471 fec_enet_mii_remove(fep);
1472 clk_disable(fep->clk);
1475 unregister_netdev(ndev);
1478 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1480 release_mem_region(r->start, resource_size(r));
1487 fec_suspend(struct device *dev)
1489 struct net_device *ndev = dev_get_drvdata(dev);
1490 struct fec_enet_private *fep = netdev_priv(ndev);
1492 if (netif_running(ndev)) {
1494 netif_device_detach(ndev);
1496 clk_disable(fep->clk);
1502 fec_resume(struct device *dev)
1504 struct net_device *ndev = dev_get_drvdata(dev);
1505 struct fec_enet_private *fep = netdev_priv(ndev);
1507 clk_enable(fep->clk);
1508 if (netif_running(ndev)) {
1509 fec_restart(ndev, fep->full_duplex);
1510 netif_device_attach(ndev);
1516 static const struct dev_pm_ops fec_pm_ops = {
1517 .suspend = fec_suspend,
1518 .resume = fec_resume,
1519 .freeze = fec_suspend,
1521 .poweroff = fec_suspend,
1522 .restore = fec_resume,
1526 static struct platform_driver fec_driver = {
1528 .name = DRIVER_NAME,
1529 .owner = THIS_MODULE,
1534 .id_table = fec_devtype,
1536 .remove = __devexit_p(fec_drv_remove),
1540 fec_enet_module_init(void)
1542 printk(KERN_INFO "FEC Ethernet Driver\n");
1544 return platform_driver_register(&fec_driver);
1548 fec_enet_cleanup(void)
1550 platform_driver_unregister(&fec_driver);
1553 module_exit(fec_enet_cleanup);
1554 module_init(fec_enet_module_init);
1556 MODULE_LICENSE("GPL");