2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
7 * Zhangfei Gao <zgao6@marvell.com>
8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include <linux/bitops.h>
26 #include <linux/clk.h>
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
32 #include <linux/interrupt.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
38 #include <linux/phy.h>
39 #include <linux/platform_device.h>
40 #include <linux/pxa168_eth.h>
41 #include <linux/tcp.h>
42 #include <linux/types.h>
43 #include <linux/udp.h>
44 #include <linux/workqueue.h>
46 #include <asm/pgtable.h>
47 #include <asm/cacheflush.h>
49 #define DRIVER_NAME "pxa168-eth"
50 #define DRIVER_VERSION "0.3"
56 #define PHY_ADDRESS 0x0000
58 #define PORT_CONFIG 0x0400
59 #define PORT_CONFIG_EXT 0x0408
60 #define PORT_COMMAND 0x0410
61 #define PORT_STATUS 0x0418
63 #define MAC_ADDR_LOW 0x0430
64 #define MAC_ADDR_HIGH 0x0438
65 #define SDMA_CONFIG 0x0440
66 #define SDMA_CMD 0x0448
67 #define INT_CAUSE 0x0450
68 #define INT_W_CLEAR 0x0454
69 #define INT_MASK 0x0458
70 #define ETH_F_RX_DESC_0 0x0480
71 #define ETH_C_RX_DESC_0 0x04A0
72 #define ETH_C_TX_DESC_1 0x04E4
75 #define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
76 #define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
77 #define SMI_OP_W (0 << 26) /* Write operation */
78 #define SMI_OP_R (1 << 26) /* Read operation */
80 #define PHY_WAIT_ITERATIONS 10
82 #define PXA168_ETH_PHY_ADDR_DEFAULT 0
83 /* RX & TX descriptor command */
84 #define BUF_OWNED_BY_DMA (1 << 31)
86 /* RX descriptor status */
87 #define RX_EN_INT (1 << 23)
88 #define RX_FIRST_DESC (1 << 17)
89 #define RX_LAST_DESC (1 << 16)
90 #define RX_ERROR (1 << 15)
92 /* TX descriptor command */
93 #define TX_EN_INT (1 << 23)
94 #define TX_GEN_CRC (1 << 22)
95 #define TX_ZERO_PADDING (1 << 18)
96 #define TX_FIRST_DESC (1 << 17)
97 #define TX_LAST_DESC (1 << 16)
98 #define TX_ERROR (1 << 15)
101 #define SDMA_CMD_AT (1 << 31)
102 #define SDMA_CMD_TXDL (1 << 24)
103 #define SDMA_CMD_TXDH (1 << 23)
104 #define SDMA_CMD_AR (1 << 15)
105 #define SDMA_CMD_ERD (1 << 7)
107 /* Bit definitions of the Port Config Reg */
108 #define PCR_HS (1 << 12)
109 #define PCR_EN (1 << 7)
110 #define PCR_PM (1 << 0)
112 /* Bit definitions of the Port Config Extend Reg */
113 #define PCXR_2BSM (1 << 28)
114 #define PCXR_DSCP_EN (1 << 21)
115 #define PCXR_MFL_1518 (0 << 14)
116 #define PCXR_MFL_1536 (1 << 14)
117 #define PCXR_MFL_2048 (2 << 14)
118 #define PCXR_MFL_64K (3 << 14)
119 #define PCXR_FLP (1 << 11)
120 #define PCXR_PRIO_TX_OFF 3
121 #define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
123 /* Bit definitions of the SDMA Config Reg */
124 #define SDCR_BSZ_OFF 12
125 #define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
126 #define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
127 #define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
128 #define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
129 #define SDCR_BLMR (1 << 6)
130 #define SDCR_BLMT (1 << 7)
131 #define SDCR_RIFB (1 << 9)
132 #define SDCR_RC_OFF 2
133 #define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
136 * Bit definitions of the Interrupt Cause Reg
137 * and Interrupt MASK Reg is the same
139 #define ICR_RXBUF (1 << 0)
140 #define ICR_TXBUF_H (1 << 2)
141 #define ICR_TXBUF_L (1 << 3)
142 #define ICR_TXEND_H (1 << 6)
143 #define ICR_TXEND_L (1 << 7)
144 #define ICR_RXERR (1 << 8)
145 #define ICR_TXERR_H (1 << 10)
146 #define ICR_TXERR_L (1 << 11)
147 #define ICR_TX_UDR (1 << 13)
148 #define ICR_MII_CH (1 << 28)
150 #define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
151 ICR_TXERR_H | ICR_TXERR_L |\
152 ICR_TXEND_H | ICR_TXEND_L |\
153 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
155 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
157 #define NUM_RX_DESCS 64
158 #define NUM_TX_DESCS 64
161 #define HASH_DELETE 1
162 #define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
163 #define HOP_NUMBER 12
165 /* Bit definitions for Port status */
166 #define PORT_SPEED_100 (1 << 0)
167 #define FULL_DUPLEX (1 << 1)
168 #define FLOW_CONTROL_DISABLED (1 << 2)
169 #define LINK_UP (1 << 3)
171 /* Bit definitions for work to be done */
172 #define WORK_LINK (1 << 0)
173 #define WORK_TX_DONE (1 << 1)
178 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
181 u32 cmd_sts; /* Descriptor command status */
182 u16 byte_cnt; /* Descriptor buffer byte count */
183 u16 buf_size; /* Buffer size */
184 u32 buf_ptr; /* Descriptor buffer pointer */
185 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 cmd_sts; /* Command/status field */
191 u16 byte_cnt; /* buffer byte count */
192 u32 buf_ptr; /* pointer to buffer for this descriptor */
193 u32 next_desc_ptr; /* Pointer to next descriptor */
196 struct pxa168_eth_private {
197 int port_num; /* User Ethernet port number */
200 int rx_resource_err; /* Rx ring resource error flag */
202 /* Next available and first returning Rx resource */
203 int rx_curr_desc_q, rx_used_desc_q;
205 /* Next available and first returning Tx resource */
206 int tx_curr_desc_q, tx_used_desc_q;
208 struct rx_desc *p_rx_desc_area;
209 dma_addr_t rx_desc_dma;
210 int rx_desc_area_size;
211 struct sk_buff **rx_skb;
213 struct tx_desc *p_tx_desc_area;
214 dma_addr_t tx_desc_dma;
215 int tx_desc_area_size;
216 struct sk_buff **tx_skb;
218 struct work_struct tx_timeout_task;
220 struct net_device *dev;
221 struct napi_struct napi;
225 /* Size of Tx Ring per queue */
227 /* Number of tx descriptors in use */
229 /* Size of Rx Ring per queue */
231 /* Number of rx descriptors in use */
235 * Used in case RX Ring is empty, which can occur when
236 * system does not have resources (skb's)
238 struct timer_list timeout;
239 struct mii_bus *smi_bus;
240 struct phy_device *phy;
244 struct pxa168_eth_platform_data *pd;
246 * Ethernet controller base address.
250 /* Pointer to the hardware address filter table */
255 struct addr_table_entry {
260 /* Bit fields of a Hash Table Entry */
261 enum hash_table_entry {
262 HASH_ENTRY_VALID = 1,
264 HASH_ENTRY_RECEIVE_DISCARD = 4,
265 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
268 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
269 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
270 static int pxa168_init_hw(struct pxa168_eth_private *pep);
271 static void eth_port_reset(struct net_device *dev);
272 static void eth_port_start(struct net_device *dev);
273 static int pxa168_eth_open(struct net_device *dev);
274 static int pxa168_eth_stop(struct net_device *dev);
275 static int ethernet_phy_setup(struct net_device *dev);
277 static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
279 return readl(pep->base + offset);
282 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
284 writel(data, pep->base + offset);
287 static void abort_dma(struct pxa168_eth_private *pep)
290 int max_retries = 40;
293 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
297 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
301 } while (max_retries-- > 0 && delay <= 0);
303 if (max_retries <= 0)
304 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__);
307 static int ethernet_phy_get(struct pxa168_eth_private *pep)
309 unsigned int reg_data;
311 reg_data = rdl(pep, PHY_ADDRESS);
313 return (reg_data >> (5 * pep->port_num)) & 0x1f;
316 static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
319 int addr_shift = 5 * pep->port_num;
321 reg_data = rdl(pep, PHY_ADDRESS);
322 reg_data &= ~(0x1f << addr_shift);
323 reg_data |= (phy_addr & 0x1f) << addr_shift;
324 wrl(pep, PHY_ADDRESS, reg_data);
327 static void rxq_refill(struct net_device *dev)
329 struct pxa168_eth_private *pep = netdev_priv(dev);
331 struct rx_desc *p_used_rx_desc;
334 while (pep->rx_desc_count < pep->rx_ring_size) {
337 skb = netdev_alloc_skb(dev, pep->skb_size);
341 skb_reserve(skb, SKB_DMA_REALIGN);
342 pep->rx_desc_count++;
343 /* Get 'used' Rx descriptor */
344 used_rx_desc = pep->rx_used_desc_q;
345 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
346 size = skb_end_pointer(skb) - skb->data;
347 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
351 p_used_rx_desc->buf_size = size;
352 pep->rx_skb[used_rx_desc] = skb;
354 /* Return the descriptor to DMA ownership */
356 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
359 /* Move the used descriptor pointer to the next descriptor */
360 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
362 /* Any Rx return cancels the Rx resource error status */
363 pep->rx_resource_err = 0;
365 skb_reserve(skb, ETH_HW_IP_ALIGN);
369 * If RX ring is empty of SKB, set a timer to try allocating
370 * again at a later time.
372 if (pep->rx_desc_count == 0) {
373 pep->timeout.expires = jiffies + (HZ / 10);
374 add_timer(&pep->timeout);
378 static inline void rxq_refill_timer_wrapper(unsigned long data)
380 struct pxa168_eth_private *pep = (void *)data;
381 napi_schedule(&pep->napi);
384 static inline u8 flip_8_bits(u8 x)
386 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
387 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
388 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
389 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
392 static void nibble_swap_every_byte(unsigned char *mac_addr)
395 for (i = 0; i < ETH_ALEN; i++) {
396 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
397 ((mac_addr[i] & 0xf0) >> 4);
401 static void inverse_every_nibble(unsigned char *mac_addr)
404 for (i = 0; i < ETH_ALEN; i++)
405 mac_addr[i] = flip_8_bits(mac_addr[i]);
409 * ----------------------------------------------------------------------------
410 * This function will calculate the hash function of the address.
412 * mac_addr_orig - MAC address.
414 * return the calculated entry.
416 static u32 hash_function(unsigned char *mac_addr_orig)
423 unsigned char mac_addr[ETH_ALEN];
425 /* Make a copy of MAC address since we are going to performe bit
428 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
430 nibble_swap_every_byte(mac_addr);
431 inverse_every_nibble(mac_addr);
433 addr0 = (mac_addr[5] >> 2) & 0x3f;
434 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
435 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
436 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
438 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
439 hash_result = hash_result & 0x07ff;
444 * ----------------------------------------------------------------------------
445 * This function will add/del an entry to the address table.
448 * mac_addr - MAC address.
449 * skip - if 1, skip this address.Used in case of deleting an entry which is a
450 * part of chain in the hash table.We can't just delete the entry since
451 * that will break the chain.We need to defragment the tables time to
453 * rd - 0 Discard packet upon match.
454 * - 1 Receive packet upon match.
456 * address table entry is added/deleted.
458 * -ENOSPC if table full
460 static int add_del_hash_entry(struct pxa168_eth_private *pep,
461 unsigned char *mac_addr,
462 u32 rd, u32 skip, int del)
464 struct addr_table_entry *entry, *start;
469 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
470 | (((mac_addr[1] >> 0) & 0xf) << 11)
471 | (((mac_addr[0] >> 4) & 0xf) << 7)
472 | (((mac_addr[0] >> 0) & 0xf) << 3)
473 | (((mac_addr[3] >> 4) & 0x1) << 31)
474 | (((mac_addr[3] >> 0) & 0xf) << 27)
475 | (((mac_addr[2] >> 4) & 0xf) << 23)
476 | (((mac_addr[2] >> 0) & 0xf) << 19)
477 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
480 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
481 | (((mac_addr[5] >> 0) & 0xf) << 11)
482 | (((mac_addr[4] >> 4) & 0xf) << 7)
483 | (((mac_addr[4] >> 0) & 0xf) << 3)
484 | (((mac_addr[3] >> 5) & 0x7) << 0);
487 * Pick the appropriate table, start scanning for free/reusable
488 * entries at the index obtained by hashing the specified MAC address
491 entry = start + hash_function(mac_addr);
492 for (i = 0; i < HOP_NUMBER; i++) {
493 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
496 /* if same address put in same position */
497 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
498 (new_low & 0xfffffff8)) &&
499 (le32_to_cpu(entry->hi) == new_high)) {
503 if (entry == start + 0x7ff)
509 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
510 (le32_to_cpu(entry->hi) != new_high) && del)
513 if (i == HOP_NUMBER) {
515 netdev_info(pep->dev,
516 "%s: table section is full, need to "
517 "move to 16kB implementation?\n",
525 * Update the selected entry
531 entry->hi = cpu_to_le32(new_high);
532 entry->lo = cpu_to_le32(new_low);
539 * ----------------------------------------------------------------------------
540 * Create an addressTable entry from MAC address info
541 * found in the specifed net_device struct
543 * Input : pointer to ethernet interface network device structure
546 static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
547 unsigned char *oaddr,
550 /* Delete old entry */
552 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
554 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
557 static int init_hash_table(struct pxa168_eth_private *pep)
560 * Hardware expects CPU to build a hash table based on a predefined
561 * hash function and populate it based on hardware address. The
562 * location of the hash table is identified by 32-bit pointer stored
563 * in HTPR internal register. Two possible sizes exists for the hash
564 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
565 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
568 /* TODO: Add support for 8kB hash table and alternative hash
569 * function.Driver can dynamically switch to them if the 1/2kB hash
572 if (pep->htpr == NULL) {
573 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent,
574 HASH_ADDR_TABLE_SIZE,
575 &pep->htpr_dma, GFP_KERNEL);
576 if (pep->htpr == NULL)
579 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
581 wrl(pep, HTPR, pep->htpr_dma);
585 static void pxa168_eth_set_rx_mode(struct net_device *dev)
587 struct pxa168_eth_private *pep = netdev_priv(dev);
588 struct netdev_hw_addr *ha;
591 val = rdl(pep, PORT_CONFIG);
592 if (dev->flags & IFF_PROMISC)
596 wrl(pep, PORT_CONFIG, val);
599 * Remove the old list of MAC address and add dev->addr
600 * and multicast address.
602 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
603 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
605 netdev_for_each_mc_addr(ha, dev)
606 update_hash_table_mac_address(pep, NULL, ha->addr);
609 static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
611 struct sockaddr *sa = addr;
612 struct pxa168_eth_private *pep = netdev_priv(dev);
613 unsigned char oldMac[ETH_ALEN];
616 if (!is_valid_ether_addr(sa->sa_data))
617 return -EADDRNOTAVAIL;
618 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
619 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
621 mac_h = sa->sa_data[0] << 24;
622 mac_h |= sa->sa_data[1] << 16;
623 mac_h |= sa->sa_data[2] << 8;
624 mac_h |= sa->sa_data[3];
625 mac_l = sa->sa_data[4] << 8;
626 mac_l |= sa->sa_data[5];
627 wrl(pep, MAC_ADDR_HIGH, mac_h);
628 wrl(pep, MAC_ADDR_LOW, mac_l);
630 netif_addr_lock_bh(dev);
631 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
632 netif_addr_unlock_bh(dev);
636 static void eth_port_start(struct net_device *dev)
638 unsigned int val = 0;
639 struct pxa168_eth_private *pep = netdev_priv(dev);
640 int tx_curr_desc, rx_curr_desc;
642 /* Perform PHY reset, if there is a PHY. */
643 if (pep->phy != NULL) {
644 struct ethtool_cmd cmd;
646 pxa168_get_settings(pep->dev, &cmd);
647 phy_init_hw(pep->phy);
648 pxa168_set_settings(pep->dev, &cmd);
651 /* Assignment of Tx CTRP of given queue */
652 tx_curr_desc = pep->tx_curr_desc_q;
653 wrl(pep, ETH_C_TX_DESC_1,
654 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
656 /* Assignment of Rx CRDP of given queue */
657 rx_curr_desc = pep->rx_curr_desc_q;
658 wrl(pep, ETH_C_RX_DESC_0,
659 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
661 wrl(pep, ETH_F_RX_DESC_0,
662 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
664 /* Clear all interrupts */
665 wrl(pep, INT_CAUSE, 0);
667 /* Enable all interrupts for receive, transmit and error. */
668 wrl(pep, INT_MASK, ALL_INTS);
670 val = rdl(pep, PORT_CONFIG);
672 wrl(pep, PORT_CONFIG, val);
674 /* Start RX DMA engine */
675 val = rdl(pep, SDMA_CMD);
677 wrl(pep, SDMA_CMD, val);
680 static void eth_port_reset(struct net_device *dev)
682 struct pxa168_eth_private *pep = netdev_priv(dev);
683 unsigned int val = 0;
685 /* Stop all interrupts for receive, transmit and error. */
686 wrl(pep, INT_MASK, 0);
688 /* Clear all interrupts */
689 wrl(pep, INT_CAUSE, 0);
692 val = rdl(pep, SDMA_CMD);
693 val &= ~SDMA_CMD_ERD; /* abort dma command */
695 /* Abort any transmit and receive operations and put DMA
701 val = rdl(pep, PORT_CONFIG);
703 wrl(pep, PORT_CONFIG, val);
707 * txq_reclaim - Free the tx desc data for completed descriptors
708 * If force is non-zero, frees uncompleted descriptors as well
710 static int txq_reclaim(struct net_device *dev, int force)
712 struct pxa168_eth_private *pep = netdev_priv(dev);
713 struct tx_desc *desc;
723 pep->work_todo &= ~WORK_TX_DONE;
724 while (pep->tx_desc_count > 0) {
725 tx_index = pep->tx_used_desc_q;
726 desc = &pep->p_tx_desc_area[tx_index];
727 cmd_sts = desc->cmd_sts;
728 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
730 goto txq_reclaim_end;
733 goto txq_reclaim_end;
736 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
737 pep->tx_desc_count--;
738 addr = desc->buf_ptr;
739 count = desc->byte_cnt;
740 skb = pep->tx_skb[tx_index];
742 pep->tx_skb[tx_index] = NULL;
744 if (cmd_sts & TX_ERROR) {
746 netdev_err(dev, "Error in TX\n");
747 dev->stats.tx_errors++;
749 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
751 dev_kfree_skb_irq(skb);
755 netif_tx_unlock(dev);
759 static void pxa168_eth_tx_timeout(struct net_device *dev)
761 struct pxa168_eth_private *pep = netdev_priv(dev);
763 netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count);
765 schedule_work(&pep->tx_timeout_task);
768 static void pxa168_eth_tx_timeout_task(struct work_struct *work)
770 struct pxa168_eth_private *pep = container_of(work,
771 struct pxa168_eth_private,
773 struct net_device *dev = pep->dev;
774 pxa168_eth_stop(dev);
775 pxa168_eth_open(dev);
778 static int rxq_process(struct net_device *dev, int budget)
780 struct pxa168_eth_private *pep = netdev_priv(dev);
781 struct net_device_stats *stats = &dev->stats;
782 unsigned int received_packets = 0;
785 while (budget-- > 0) {
786 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
787 struct rx_desc *rx_desc;
788 unsigned int cmd_sts;
790 /* Do not process Rx ring in case of Rx ring resource error */
791 if (pep->rx_resource_err)
793 rx_curr_desc = pep->rx_curr_desc_q;
794 rx_used_desc = pep->rx_used_desc_q;
795 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
796 cmd_sts = rx_desc->cmd_sts;
798 if (cmd_sts & (BUF_OWNED_BY_DMA))
800 skb = pep->rx_skb[rx_curr_desc];
801 pep->rx_skb[rx_curr_desc] = NULL;
803 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
804 pep->rx_curr_desc_q = rx_next_curr_desc;
806 /* Rx descriptors exhausted. */
807 /* Set the Rx ring resource error flag */
808 if (rx_next_curr_desc == rx_used_desc)
809 pep->rx_resource_err = 1;
810 pep->rx_desc_count--;
811 dma_unmap_single(NULL, rx_desc->buf_ptr,
817 * Note byte count includes 4 byte CRC count
820 stats->rx_bytes += rx_desc->byte_cnt;
822 * In case received a packet without first / last bits on OR
823 * the error summary bit is on, the packets needs to be droped.
825 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
826 (RX_FIRST_DESC | RX_LAST_DESC))
827 || (cmd_sts & RX_ERROR)) {
830 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
831 (RX_FIRST_DESC | RX_LAST_DESC)) {
834 "Rx pkt on multiple desc\n");
836 if (cmd_sts & RX_ERROR)
838 dev_kfree_skb_irq(skb);
841 * The -4 is for the CRC in the trailer of the
844 skb_put(skb, rx_desc->byte_cnt - 4);
845 skb->protocol = eth_type_trans(skb, dev);
846 netif_receive_skb(skb);
849 /* Fill RX ring with skb's */
851 return received_packets;
854 static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
855 struct net_device *dev)
860 icr = rdl(pep, INT_CAUSE);
864 wrl(pep, INT_CAUSE, ~icr);
865 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
866 pep->work_todo |= WORK_TX_DONE;
871 if (icr & ICR_MII_CH) {
872 pep->work_todo |= WORK_LINK;
878 static void handle_link_event(struct pxa168_eth_private *pep)
880 struct net_device *dev = pep->dev;
886 port_status = rdl(pep, PORT_STATUS);
887 if (!(port_status & LINK_UP)) {
888 if (netif_carrier_ok(dev)) {
889 netdev_info(dev, "link down\n");
890 netif_carrier_off(dev);
895 if (port_status & PORT_SPEED_100)
900 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
901 fc = (port_status & FLOW_CONTROL_DISABLED) ? 0 : 1;
902 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
903 speed, duplex ? "full" : "half", fc ? "en" : "dis");
904 if (!netif_carrier_ok(dev))
905 netif_carrier_on(dev);
908 static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
910 struct net_device *dev = (struct net_device *)dev_id;
911 struct pxa168_eth_private *pep = netdev_priv(dev);
913 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
915 /* Disable interrupts */
916 wrl(pep, INT_MASK, 0);
917 napi_schedule(&pep->napi);
921 static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
926 * Reserve 2+14 bytes for an ethernet header (the hardware
927 * automatically prepends 2 bytes of dummy data to each
928 * received packet), 16 bytes for up to four VLAN tags, and
929 * 4 bytes for the trailing FCS -- 36 bytes total.
931 skb_size = pep->dev->mtu + 36;
934 * Make sure that the skb size is a multiple of 8 bytes, as
935 * the lower three bits of the receive descriptor's buffer
936 * size field are ignored by the hardware.
938 pep->skb_size = (skb_size + 7) & ~7;
941 * If NET_SKB_PAD is smaller than a cache line,
942 * netdev_alloc_skb() will cause skb->data to be misaligned
943 * to a cache line boundary. If this is the case, include
944 * some extra space to allow re-aligning the data area.
946 pep->skb_size += SKB_DMA_REALIGN;
950 static int set_port_config_ext(struct pxa168_eth_private *pep)
954 pxa168_eth_recalc_skb_size(pep);
955 if (pep->skb_size <= 1518)
956 skb_size = PCXR_MFL_1518;
957 else if (pep->skb_size <= 1536)
958 skb_size = PCXR_MFL_1536;
959 else if (pep->skb_size <= 2048)
960 skb_size = PCXR_MFL_2048;
962 skb_size = PCXR_MFL_64K;
964 /* Extended Port Configuration */
966 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
967 PCXR_DSCP_EN | /* Enable DSCP in IP */
968 skb_size | PCXR_FLP | /* do not force link pass */
969 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
974 static int pxa168_init_hw(struct pxa168_eth_private *pep)
978 /* Disable interrupts */
979 wrl(pep, INT_MASK, 0);
980 wrl(pep, INT_CAUSE, 0);
981 /* Write to ICR to clear interrupts. */
982 wrl(pep, INT_W_CLEAR, 0);
983 /* Abort any transmit and receive operations and put DMA
987 /* Initialize address hash table */
988 err = init_hash_table(pep);
991 /* SDMA configuration */
992 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
993 SDCR_RIFB | /* Rx interrupt on frame */
994 SDCR_BLMT | /* Little endian transmit */
995 SDCR_BLMR | /* Little endian receive */
996 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
997 /* Port Configuration */
998 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
999 set_port_config_ext(pep);
1004 static int rxq_init(struct net_device *dev)
1006 struct pxa168_eth_private *pep = netdev_priv(dev);
1007 struct rx_desc *p_rx_desc;
1008 int size = 0, i = 0;
1009 int rx_desc_num = pep->rx_ring_size;
1011 /* Allocate RX skb rings */
1012 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
1017 /* Allocate RX ring */
1018 pep->rx_desc_count = 0;
1019 size = pep->rx_ring_size * sizeof(struct rx_desc);
1020 pep->rx_desc_area_size = size;
1021 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1024 if (!pep->p_rx_desc_area)
1027 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1028 p_rx_desc = pep->p_rx_desc_area;
1029 for (i = 0; i < rx_desc_num; i++) {
1030 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1031 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1033 /* Save Rx desc pointer to driver struct. */
1034 pep->rx_curr_desc_q = 0;
1035 pep->rx_used_desc_q = 0;
1036 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1043 static void rxq_deinit(struct net_device *dev)
1045 struct pxa168_eth_private *pep = netdev_priv(dev);
1048 /* Free preallocated skb's on RX rings */
1049 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1050 if (pep->rx_skb[curr]) {
1051 dev_kfree_skb(pep->rx_skb[curr]);
1052 pep->rx_desc_count--;
1055 if (pep->rx_desc_count)
1056 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n",
1057 pep->rx_desc_count);
1059 if (pep->p_rx_desc_area)
1060 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1061 pep->p_rx_desc_area, pep->rx_desc_dma);
1065 static int txq_init(struct net_device *dev)
1067 struct pxa168_eth_private *pep = netdev_priv(dev);
1068 struct tx_desc *p_tx_desc;
1069 int size = 0, i = 0;
1070 int tx_desc_num = pep->tx_ring_size;
1072 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
1077 /* Allocate TX ring */
1078 pep->tx_desc_count = 0;
1079 size = pep->tx_ring_size * sizeof(struct tx_desc);
1080 pep->tx_desc_area_size = size;
1081 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1084 if (!pep->p_tx_desc_area)
1086 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1087 p_tx_desc = pep->p_tx_desc_area;
1088 for (i = 0; i < tx_desc_num; i++) {
1089 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1090 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1092 pep->tx_curr_desc_q = 0;
1093 pep->tx_used_desc_q = 0;
1094 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1101 static void txq_deinit(struct net_device *dev)
1103 struct pxa168_eth_private *pep = netdev_priv(dev);
1105 /* Free outstanding skb's on TX ring */
1106 txq_reclaim(dev, 1);
1107 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1109 if (pep->p_tx_desc_area)
1110 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1111 pep->p_tx_desc_area, pep->tx_desc_dma);
1115 static int pxa168_eth_open(struct net_device *dev)
1117 struct pxa168_eth_private *pep = netdev_priv(dev);
1120 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
1122 dev_err(&dev->dev, "can't assign irq\n");
1125 pep->rx_resource_err = 0;
1126 err = rxq_init(dev);
1129 err = txq_init(dev);
1131 goto out_free_rx_skb;
1132 pep->rx_used_desc_q = 0;
1133 pep->rx_curr_desc_q = 0;
1135 /* Fill RX ring with skb's */
1137 pep->rx_used_desc_q = 0;
1138 pep->rx_curr_desc_q = 0;
1139 netif_carrier_off(dev);
1140 eth_port_start(dev);
1141 napi_enable(&pep->napi);
1146 free_irq(dev->irq, dev);
1150 static int pxa168_eth_stop(struct net_device *dev)
1152 struct pxa168_eth_private *pep = netdev_priv(dev);
1153 eth_port_reset(dev);
1155 /* Disable interrupts */
1156 wrl(pep, INT_MASK, 0);
1157 wrl(pep, INT_CAUSE, 0);
1158 /* Write to ICR to clear interrupts. */
1159 wrl(pep, INT_W_CLEAR, 0);
1160 napi_disable(&pep->napi);
1161 del_timer_sync(&pep->timeout);
1162 netif_carrier_off(dev);
1163 free_irq(dev->irq, dev);
1170 static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1173 struct pxa168_eth_private *pep = netdev_priv(dev);
1175 if ((mtu > 9500) || (mtu < 68))
1179 retval = set_port_config_ext(pep);
1181 if (!netif_running(dev))
1185 * Stop and then re-open the interface. This will allocate RX
1186 * skbs of the new MTU.
1187 * There is a possible danger that the open will not succeed,
1188 * due to memory being full.
1190 pxa168_eth_stop(dev);
1191 if (pxa168_eth_open(dev)) {
1193 "fatal error on re-opening device after MTU change\n");
1199 static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1203 tx_desc_curr = pep->tx_curr_desc_q;
1204 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1205 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1206 pep->tx_desc_count++;
1208 return tx_desc_curr;
1211 static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1213 struct pxa168_eth_private *pep =
1214 container_of(napi, struct pxa168_eth_private, napi);
1215 struct net_device *dev = pep->dev;
1218 if (unlikely(pep->work_todo & WORK_LINK)) {
1219 pep->work_todo &= ~(WORK_LINK);
1220 handle_link_event(pep);
1223 * We call txq_reclaim every time since in NAPI interupts are disabled
1224 * and due to this we miss the TX_DONE interrupt,which is not updated in
1225 * interrupt status register.
1227 txq_reclaim(dev, 0);
1228 if (netif_queue_stopped(dev)
1229 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1230 netif_wake_queue(dev);
1232 work_done = rxq_process(dev, budget);
1233 if (work_done < budget) {
1234 napi_complete(napi);
1235 wrl(pep, INT_MASK, ALL_INTS);
1241 static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1243 struct pxa168_eth_private *pep = netdev_priv(dev);
1244 struct net_device_stats *stats = &dev->stats;
1245 struct tx_desc *desc;
1249 tx_index = eth_alloc_tx_desc_index(pep);
1250 desc = &pep->p_tx_desc_area[tx_index];
1252 pep->tx_skb[tx_index] = skb;
1253 desc->byte_cnt = length;
1254 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1256 skb_tx_timestamp(skb);
1259 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1260 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1262 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1264 stats->tx_bytes += length;
1265 stats->tx_packets++;
1266 dev->trans_start = jiffies;
1267 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1268 /* We handled the current skb, but now we are out of space.*/
1269 netif_stop_queue(dev);
1272 return NETDEV_TX_OK;
1275 static int smi_wait_ready(struct pxa168_eth_private *pep)
1279 /* wait for the SMI register to become available */
1280 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1281 if (i == PHY_WAIT_ITERATIONS)
1289 static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1291 struct pxa168_eth_private *pep = bus->priv;
1295 if (smi_wait_ready(pep)) {
1296 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1299 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1300 /* now wait for the data to be valid */
1301 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1302 if (i == PHY_WAIT_ITERATIONS) {
1303 netdev_warn(pep->dev,
1304 "pxa168_eth: SMI bus read not valid\n");
1310 return val & 0xffff;
1313 static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1316 struct pxa168_eth_private *pep = bus->priv;
1318 if (smi_wait_ready(pep)) {
1319 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1323 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1324 SMI_OP_W | (value & 0xffff));
1326 if (smi_wait_ready(pep)) {
1327 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
1334 static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1337 struct pxa168_eth_private *pep = netdev_priv(dev);
1338 if (pep->phy != NULL)
1339 return phy_mii_ioctl(pep->phy, ifr, cmd);
1344 static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1346 struct mii_bus *bus = pep->smi_bus;
1347 struct phy_device *phydev;
1352 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1353 /* Scan entire range */
1354 start = ethernet_phy_get(pep);
1357 /* Use phy addr specific to platform */
1358 start = phy_addr & 0x1f;
1362 for (i = 0; i < num; i++) {
1363 int addr = (start + i) & 0x1f;
1364 if (bus->phy_map[addr] == NULL)
1365 mdiobus_scan(bus, addr);
1367 if (phydev == NULL) {
1368 phydev = bus->phy_map[addr];
1370 ethernet_phy_set_addr(pep, addr);
1377 static void phy_init(struct pxa168_eth_private *pep)
1379 struct phy_device *phy = pep->phy;
1381 phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
1383 if (pep->pd && pep->pd->speed != 0) {
1384 phy->autoneg = AUTONEG_DISABLE;
1385 phy->advertising = 0;
1386 phy->speed = pep->pd->speed;
1387 phy->duplex = pep->pd->duplex;
1389 phy->autoneg = AUTONEG_ENABLE;
1392 phy->supported &= PHY_BASIC_FEATURES;
1393 phy->advertising = phy->supported | ADVERTISED_Autoneg;
1396 phy_start_aneg(phy);
1399 static int ethernet_phy_setup(struct net_device *dev)
1401 struct pxa168_eth_private *pep = netdev_priv(dev);
1403 if (pep->pd && pep->pd->init)
1406 pep->phy = phy_scan(pep, pep->phy_addr & 0x1f);
1407 if (pep->phy != NULL)
1410 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1415 static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1417 struct pxa168_eth_private *pep = netdev_priv(dev);
1420 err = phy_read_status(pep->phy);
1422 err = phy_ethtool_gset(pep->phy, cmd);
1427 static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1429 struct pxa168_eth_private *pep = netdev_priv(dev);
1431 return phy_ethtool_sset(pep->phy, cmd);
1434 static void pxa168_get_drvinfo(struct net_device *dev,
1435 struct ethtool_drvinfo *info)
1437 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1438 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
1439 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1440 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
1443 static const struct ethtool_ops pxa168_ethtool_ops = {
1444 .get_settings = pxa168_get_settings,
1445 .set_settings = pxa168_set_settings,
1446 .get_drvinfo = pxa168_get_drvinfo,
1447 .get_link = ethtool_op_get_link,
1448 .get_ts_info = ethtool_op_get_ts_info,
1451 static const struct net_device_ops pxa168_eth_netdev_ops = {
1452 .ndo_open = pxa168_eth_open,
1453 .ndo_stop = pxa168_eth_stop,
1454 .ndo_start_xmit = pxa168_eth_start_xmit,
1455 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1456 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1457 .ndo_validate_addr = eth_validate_addr,
1458 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1459 .ndo_change_mtu = pxa168_eth_change_mtu,
1460 .ndo_tx_timeout = pxa168_eth_tx_timeout,
1463 static int pxa168_eth_probe(struct platform_device *pdev)
1465 struct pxa168_eth_private *pep = NULL;
1466 struct net_device *dev = NULL;
1467 struct resource *res;
1469 struct device_node *np;
1472 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1474 clk = devm_clk_get(&pdev->dev, NULL);
1476 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n");
1479 clk_prepare_enable(clk);
1481 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1487 platform_set_drvdata(pdev, dev);
1488 pep = netdev_priv(dev);
1491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1496 pep->base = devm_ioremap_resource(&pdev->dev, res);
1497 if (IS_ERR(pep->base)) {
1501 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1503 dev->irq = res->start;
1504 dev->netdev_ops = &pxa168_eth_netdev_ops;
1505 dev->watchdog_timeo = 2 * HZ;
1507 dev->ethtool_ops = &pxa168_ethtool_ops;
1509 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1511 dev_info(&pdev->dev, "Using random mac address\n");
1512 eth_hw_addr_random(dev);
1514 pep->rx_ring_size = NUM_RX_DESCS;
1515 pep->tx_ring_size = NUM_TX_DESCS;
1517 pep->pd = dev_get_platdata(&pdev->dev);
1519 if (pep->pd->rx_queue_size)
1520 pep->rx_ring_size = pep->pd->rx_queue_size;
1522 if (pep->pd->tx_queue_size)
1523 pep->tx_ring_size = pep->pd->tx_queue_size;
1525 pep->port_num = pep->pd->port_number;
1526 pep->phy_addr = pep->pd->phy_addr;
1527 } else if (pdev->dev.of_node) {
1528 of_property_read_u32(pdev->dev.of_node, "port-id",
1531 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1533 of_property_read_u32(np, "reg", &pep->phy_addr);
1536 /* Hardware supports only 3 ports */
1537 BUG_ON(pep->port_num > 2);
1538 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1540 memset(&pep->timeout, 0, sizeof(struct timer_list));
1541 init_timer(&pep->timeout);
1542 pep->timeout.function = rxq_refill_timer_wrapper;
1543 pep->timeout.data = (unsigned long)pep;
1545 pep->smi_bus = mdiobus_alloc();
1546 if (pep->smi_bus == NULL) {
1550 pep->smi_bus->priv = pep;
1551 pep->smi_bus->name = "pxa168_eth smi";
1552 pep->smi_bus->read = pxa168_smi_read;
1553 pep->smi_bus->write = pxa168_smi_write;
1554 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1555 pdev->name, pdev->id);
1556 pep->smi_bus->parent = &pdev->dev;
1557 pep->smi_bus->phy_mask = 0xffffffff;
1558 err = mdiobus_register(pep->smi_bus);
1562 pxa168_init_hw(pep);
1563 err = ethernet_phy_setup(dev);
1566 SET_NETDEV_DEV(dev, &pdev->dev);
1567 err = register_netdev(dev);
1573 mdiobus_unregister(pep->smi_bus);
1575 mdiobus_free(pep->smi_bus);
1586 static int pxa168_eth_remove(struct platform_device *pdev)
1588 struct net_device *dev = platform_get_drvdata(pdev);
1589 struct pxa168_eth_private *pep = netdev_priv(dev);
1592 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1593 pep->htpr, pep->htpr_dma);
1597 clk_disable(pep->clk);
1601 if (pep->phy != NULL)
1602 phy_detach(pep->phy);
1606 mdiobus_unregister(pep->smi_bus);
1607 mdiobus_free(pep->smi_bus);
1608 unregister_netdev(dev);
1609 cancel_work_sync(&pep->tx_timeout_task);
1614 static void pxa168_eth_shutdown(struct platform_device *pdev)
1616 struct net_device *dev = platform_get_drvdata(pdev);
1617 eth_port_reset(dev);
1621 static int pxa168_eth_resume(struct platform_device *pdev)
1626 static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1632 #define pxa168_eth_resume NULL
1633 #define pxa168_eth_suspend NULL
1636 static const struct of_device_id pxa168_eth_of_match[] = {
1637 { .compatible = "marvell,pxa168-eth" },
1640 MODULE_DEVICE_TABLE(of, pxa168_eth_of_match);
1642 static struct platform_driver pxa168_eth_driver = {
1643 .probe = pxa168_eth_probe,
1644 .remove = pxa168_eth_remove,
1645 .shutdown = pxa168_eth_shutdown,
1646 .resume = pxa168_eth_resume,
1647 .suspend = pxa168_eth_suspend,
1649 .name = DRIVER_NAME,
1650 .of_match_table = of_match_ptr(pxa168_eth_of_match),
1654 module_platform_driver(pxa168_eth_driver);
1656 MODULE_LICENSE("GPL");
1657 MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1658 MODULE_ALIAS("platform:pxa168_eth");