1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
73 /* ixgbe_pci_tbl - PCI Device ID Table
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
135 /* required last entry */
138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
140 #ifdef CONFIG_IXGBE_DCA
141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
143 static struct notifier_block dca_notifier = {
144 .notifier_call = ixgbe_notify_dca,
150 #ifdef CONFIG_PCI_IOV
151 static unsigned int max_vfs;
152 module_param(max_vfs, uint, 0);
153 MODULE_PARM_DESC(max_vfs,
154 "Maximum number of virtual functions to allocate per physical function");
155 #endif /* CONFIG_PCI_IOV */
157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_VERSION);
162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
166 struct ixgbe_hw *hw = &adapter->hw;
171 #ifdef CONFIG_PCI_IOV
172 /* disable iov and allow time for transactions to clear */
173 pci_disable_sriov(adapter->pdev);
176 /* turn off device IOV mode */
177 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
178 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
179 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
180 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
181 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
184 /* set default pool back to 0 */
185 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
186 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
187 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
188 IXGBE_WRITE_FLUSH(hw);
190 /* take a breather then clean up driver data */
193 kfree(adapter->vfinfo);
194 adapter->vfinfo = NULL;
196 adapter->num_vfs = 0;
197 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
202 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
203 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
204 schedule_work(&adapter->service_task);
207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
209 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
211 /* flush memory to make sure state is correct before next watchog */
212 smp_mb__before_clear_bit();
213 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
216 struct ixgbe_reg_info {
221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
223 /* General Registers */
224 {IXGBE_CTRL, "CTRL"},
225 {IXGBE_STATUS, "STATUS"},
226 {IXGBE_CTRL_EXT, "CTRL_EXT"},
228 /* Interrupt Registers */
229 {IXGBE_EICR, "EICR"},
232 {IXGBE_SRRCTL(0), "SRRCTL"},
233 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
234 {IXGBE_RDLEN(0), "RDLEN"},
235 {IXGBE_RDH(0), "RDH"},
236 {IXGBE_RDT(0), "RDT"},
237 {IXGBE_RXDCTL(0), "RXDCTL"},
238 {IXGBE_RDBAL(0), "RDBAL"},
239 {IXGBE_RDBAH(0), "RDBAH"},
242 {IXGBE_TDBAL(0), "TDBAL"},
243 {IXGBE_TDBAH(0), "TDBAH"},
244 {IXGBE_TDLEN(0), "TDLEN"},
245 {IXGBE_TDH(0), "TDH"},
246 {IXGBE_TDT(0), "TDT"},
247 {IXGBE_TXDCTL(0), "TXDCTL"},
249 /* List Terminator */
255 * ixgbe_regdump - register printout routine
257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
263 switch (reginfo->ofs) {
264 case IXGBE_SRRCTL(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
268 case IXGBE_DCA_RXCTRL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
284 case IXGBE_RXDCTL(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
293 for (i = 0; i < 64; i++)
294 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
297 for (i = 0; i < 64; i++)
298 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
301 for (i = 0; i < 64; i++)
302 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
305 for (i = 0; i < 64; i++)
306 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
309 for (i = 0; i < 64; i++)
310 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
313 for (i = 0; i < 64; i++)
314 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
316 case IXGBE_TXDCTL(0):
317 for (i = 0; i < 64; i++)
318 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
321 pr_info("%-15s %08x\n", reginfo->name,
322 IXGBE_READ_REG(hw, reginfo->ofs));
326 for (i = 0; i < 8; i++) {
327 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
328 pr_err("%-15s", rname);
329 for (j = 0; j < 8; j++)
330 pr_cont(" %08x", regs[i*8+j]);
337 * ixgbe_dump - Print registers, tx-rings and rx-rings
339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
341 struct net_device *netdev = adapter->netdev;
342 struct ixgbe_hw *hw = &adapter->hw;
343 struct ixgbe_reg_info *reginfo;
345 struct ixgbe_ring *tx_ring;
346 struct ixgbe_tx_buffer *tx_buffer_info;
347 union ixgbe_adv_tx_desc *tx_desc;
348 struct my_u0 { u64 a; u64 b; } *u0;
349 struct ixgbe_ring *rx_ring;
350 union ixgbe_adv_rx_desc *rx_desc;
351 struct ixgbe_rx_buffer *rx_buffer_info;
355 if (!netif_msg_hw(adapter))
358 /* Print netdevice Info */
360 dev_info(&adapter->pdev->dev, "Net device Info\n");
361 pr_info("Device Name state "
362 "trans_start last_rx\n");
363 pr_info("%-15s %016lX %016lX %016lX\n",
370 /* Print Registers */
371 dev_info(&adapter->pdev->dev, "Register Dump\n");
372 pr_info(" Register Name Value\n");
373 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
374 reginfo->name; reginfo++) {
375 ixgbe_regdump(hw, reginfo);
378 /* Print TX Ring Summary */
379 if (!netdev || !netif_running(netdev))
382 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
383 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
387 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
388 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
389 n, tx_ring->next_to_use, tx_ring->next_to_clean,
390 (u64)tx_buffer_info->dma,
391 tx_buffer_info->length,
392 tx_buffer_info->next_to_watch,
393 (u64)tx_buffer_info->time_stamp);
397 if (!netif_msg_tx_done(adapter))
398 goto rx_ring_summary;
400 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
402 /* Transmit Descriptor Formats
404 * Advanced Transmit Descriptor
405 * +--------------------------------------------------------------+
406 * 0 | Buffer Address [63:0] |
407 * +--------------------------------------------------------------+
408 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
409 * +--------------------------------------------------------------+
410 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
413 for (n = 0; n < adapter->num_tx_queues; n++) {
414 tx_ring = adapter->tx_ring[n];
415 pr_info("------------------------------------\n");
416 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
417 pr_info("------------------------------------\n");
418 pr_info("T [desc] [address 63:0 ] "
419 "[PlPOIdStDDt Ln] [bi->dma ] "
420 "leng ntw timestamp bi->skb\n");
422 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
423 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
424 tx_buffer_info = &tx_ring->tx_buffer_info[i];
425 u0 = (struct my_u0 *)tx_desc;
426 pr_info("T [0x%03X] %016llX %016llX %016llX"
427 " %04X %3X %016llX %p", i,
430 (u64)tx_buffer_info->dma,
431 tx_buffer_info->length,
432 tx_buffer_info->next_to_watch,
433 (u64)tx_buffer_info->time_stamp,
434 tx_buffer_info->skb);
435 if (i == tx_ring->next_to_use &&
436 i == tx_ring->next_to_clean)
438 else if (i == tx_ring->next_to_use)
440 else if (i == tx_ring->next_to_clean)
445 if (netif_msg_pktdata(adapter) &&
446 tx_buffer_info->dma != 0)
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16, 1,
449 phys_to_virt(tx_buffer_info->dma),
450 tx_buffer_info->length, true);
454 /* Print RX Rings Summary */
456 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
457 pr_info("Queue [NTU] [NTC]\n");
458 for (n = 0; n < adapter->num_rx_queues; n++) {
459 rx_ring = adapter->rx_ring[n];
460 pr_info("%5d %5X %5X\n",
461 n, rx_ring->next_to_use, rx_ring->next_to_clean);
465 if (!netif_msg_rx_status(adapter))
468 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
470 /* Advanced Receive Descriptor (Read) Format
472 * +-----------------------------------------------------+
473 * 0 | Packet Buffer Address [63:1] |A0/NSE|
474 * +----------------------------------------------+------+
475 * 8 | Header Buffer Address [63:1] | DD |
476 * +-----------------------------------------------------+
479 * Advanced Receive Descriptor (Write-Back) Format
481 * 63 48 47 32 31 30 21 20 16 15 4 3 0
482 * +------------------------------------------------------+
483 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
484 * | Checksum Ident | | | | Type | Type |
485 * +------------------------------------------------------+
486 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
487 * +------------------------------------------------------+
488 * 63 48 47 32 31 20 19 0
490 for (n = 0; n < adapter->num_rx_queues; n++) {
491 rx_ring = adapter->rx_ring[n];
492 pr_info("------------------------------------\n");
493 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
494 pr_info("------------------------------------\n");
495 pr_info("R [desc] [ PktBuf A0] "
496 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
497 "<-- Adv Rx Read format\n");
498 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
499 "[vl er S cks ln] ---------------- [bi->skb] "
500 "<-- Adv Rx Write-Back format\n");
502 for (i = 0; i < rx_ring->count; i++) {
503 rx_buffer_info = &rx_ring->rx_buffer_info[i];
504 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
505 u0 = (struct my_u0 *)rx_desc;
506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
507 if (staterr & IXGBE_RXD_STAT_DD) {
508 /* Descriptor Done */
509 pr_info("RWB[0x%03X] %016llX "
510 "%016llX ---------------- %p", i,
513 rx_buffer_info->skb);
515 pr_info("R [0x%03X] %016llX "
516 "%016llX %016llX %p", i,
519 (u64)rx_buffer_info->dma,
520 rx_buffer_info->skb);
522 if (netif_msg_pktdata(adapter)) {
523 print_hex_dump(KERN_INFO, "",
524 DUMP_PREFIX_ADDRESS, 16, 1,
525 phys_to_virt(rx_buffer_info->dma),
526 rx_ring->rx_buf_len, true);
528 if (rx_ring->rx_buf_len
529 < IXGBE_RXBUFFER_2048)
530 print_hex_dump(KERN_INFO, "",
531 DUMP_PREFIX_ADDRESS, 16, 1,
533 rx_buffer_info->page_dma +
534 rx_buffer_info->page_offset
540 if (i == rx_ring->next_to_use)
542 else if (i == rx_ring->next_to_clean)
554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
583 u8 queue, u8 msix_vector)
586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
598 case ixgbe_mac_82599EB:
600 if (direction == -1) {
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
634 case ixgbe_mac_82599EB:
636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
646 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
647 struct ixgbe_tx_buffer *tx_buffer_info)
649 if (tx_buffer_info->dma) {
650 if (tx_buffer_info->mapped_as_page)
651 dma_unmap_page(tx_ring->dev,
653 tx_buffer_info->length,
656 dma_unmap_single(tx_ring->dev,
658 tx_buffer_info->length,
660 tx_buffer_info->dma = 0;
662 if (tx_buffer_info->skb) {
663 dev_kfree_skb_any(tx_buffer_info->skb);
664 tx_buffer_info->skb = NULL;
666 tx_buffer_info->time_stamp = 0;
667 /* tx_buffer_info must be completely set up in the transmit path */
670 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
672 struct ixgbe_hw *hw = &adapter->hw;
673 struct ixgbe_hw_stats *hwstats = &adapter->stats;
678 if ((hw->fc.current_mode == ixgbe_fc_full) ||
679 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
680 switch (hw->mac.type) {
681 case ixgbe_mac_82598EB:
682 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
685 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
687 hwstats->lxoffrxc += data;
689 /* refill credits (no tx hang) if we received xoff */
693 for (i = 0; i < adapter->num_tx_queues; i++)
694 clear_bit(__IXGBE_HANG_CHECK_ARMED,
695 &adapter->tx_ring[i]->state);
697 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
700 /* update stats for each tc, only valid with PFC enabled */
701 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
702 switch (hw->mac.type) {
703 case ixgbe_mac_82598EB:
704 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
707 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
709 hwstats->pxoffrxc[i] += xoff[i];
712 /* disarm tx queues that have received xoff frames */
713 for (i = 0; i < adapter->num_tx_queues; i++) {
714 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
715 u8 tc = tx_ring->dcb_tc;
718 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
722 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
724 return ring->tx_stats.completed;
727 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
729 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
730 struct ixgbe_hw *hw = &adapter->hw;
732 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
733 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
736 return (head < tail) ?
737 tail - head : (tail + ring->count - head);
742 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
744 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
745 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
746 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
749 clear_check_for_tx_hang(tx_ring);
752 * Check for a hung queue, but be thorough. This verifies
753 * that a transmit has been completed since the previous
754 * check AND there is at least one packet pending. The
755 * ARMED bit is set to indicate a potential hang. The
756 * bit is cleared if a pause frame is received to remove
757 * false hang detection due to PFC or 802.3x frames. By
758 * requiring this to fail twice we avoid races with
759 * pfc clearing the ARMED bit and conditions where we
760 * run the check_tx_hang logic with a transmit completion
761 * pending but without time to complete it yet.
763 if ((tx_done_old == tx_done) && tx_pending) {
764 /* make sure it is true for two checks in a row */
765 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
768 /* update completed stats and continue */
769 tx_ring->tx_stats.tx_done_old = tx_done;
770 /* reset the countdown */
771 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
778 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
779 * @adapter: driver private struct
781 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
784 /* Do the reset outside of interrupt context */
785 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
786 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
787 ixgbe_service_event_schedule(adapter);
792 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
793 * @q_vector: structure containing interrupt and ring information
794 * @tx_ring: tx ring to clean
796 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
797 struct ixgbe_ring *tx_ring)
799 struct ixgbe_adapter *adapter = q_vector->adapter;
800 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
801 struct ixgbe_tx_buffer *tx_buffer_info;
802 unsigned int total_bytes = 0, total_packets = 0;
803 u16 i, eop, count = 0;
805 i = tx_ring->next_to_clean;
806 eop = tx_ring->tx_buffer_info[i].next_to_watch;
807 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
809 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
810 (count < q_vector->tx.work_limit)) {
811 bool cleaned = false;
812 rmb(); /* read buffer_info after eop_desc */
813 for ( ; !cleaned; count++) {
814 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
815 tx_buffer_info = &tx_ring->tx_buffer_info[i];
817 tx_desc->wb.status = 0;
818 cleaned = (i == eop);
821 if (i == tx_ring->count)
824 if (cleaned && tx_buffer_info->skb) {
825 total_bytes += tx_buffer_info->bytecount;
826 total_packets += tx_buffer_info->gso_segs;
829 ixgbe_unmap_and_free_tx_resource(tx_ring,
833 tx_ring->tx_stats.completed++;
834 eop = tx_ring->tx_buffer_info[i].next_to_watch;
835 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
838 tx_ring->next_to_clean = i;
839 tx_ring->stats.bytes += total_bytes;
840 tx_ring->stats.packets += total_packets;
841 u64_stats_update_begin(&tx_ring->syncp);
842 q_vector->tx.total_bytes += total_bytes;
843 q_vector->tx.total_packets += total_packets;
844 u64_stats_update_end(&tx_ring->syncp);
846 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
847 /* schedule immediate reset if we believe we hung */
848 struct ixgbe_hw *hw = &adapter->hw;
849 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
850 e_err(drv, "Detected Tx Unit Hang\n"
852 " TDH, TDT <%x>, <%x>\n"
853 " next_to_use <%x>\n"
854 " next_to_clean <%x>\n"
855 "tx_buffer_info[next_to_clean]\n"
856 " time_stamp <%lx>\n"
858 tx_ring->queue_index,
859 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
860 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
861 tx_ring->next_to_use, eop,
862 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
864 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
867 "tx hang %d detected on queue %d, resetting adapter\n",
868 adapter->tx_timeout_count + 1, tx_ring->queue_index);
870 /* schedule immediate reset if we believe we hung */
871 ixgbe_tx_timeout_reset(adapter);
873 /* the adapter is about to reset, no point in enabling stuff */
877 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
878 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
879 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
880 /* Make sure that anybody stopping the queue after this
881 * sees the new next_to_clean.
884 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
885 !test_bit(__IXGBE_DOWN, &adapter->state)) {
886 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
887 ++tx_ring->tx_stats.restart_queue;
891 return count < q_vector->tx.work_limit;
894 #ifdef CONFIG_IXGBE_DCA
895 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
896 struct ixgbe_ring *rx_ring,
899 struct ixgbe_hw *hw = &adapter->hw;
901 u8 reg_idx = rx_ring->reg_idx;
903 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
904 switch (hw->mac.type) {
905 case ixgbe_mac_82598EB:
906 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
907 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
909 case ixgbe_mac_82599EB:
911 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
912 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
913 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
918 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
919 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
920 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
921 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
924 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
925 struct ixgbe_ring *tx_ring,
928 struct ixgbe_hw *hw = &adapter->hw;
930 u8 reg_idx = tx_ring->reg_idx;
932 switch (hw->mac.type) {
933 case ixgbe_mac_82598EB:
934 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
935 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
936 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
937 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
938 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
940 case ixgbe_mac_82599EB:
942 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
943 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
944 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
945 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
946 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
947 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
954 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
956 struct ixgbe_adapter *adapter = q_vector->adapter;
961 if (q_vector->cpu == cpu)
964 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
965 for (i = 0; i < q_vector->tx.count; i++) {
966 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
967 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
971 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
972 for (i = 0; i < q_vector->rx.count; i++) {
973 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
974 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
983 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
988 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
991 /* always use CB2 mode, difference is masked in the CB driver */
992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
994 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
995 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
999 for (i = 0; i < num_q_vectors; i++) {
1000 adapter->q_vector[i]->cpu = -1;
1001 ixgbe_update_dca(adapter->q_vector[i]);
1005 static int __ixgbe_notify_dca(struct device *dev, void *data)
1007 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1008 unsigned long event = *(unsigned long *)data;
1010 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1014 case DCA_PROVIDER_ADD:
1015 /* if we're already enabled, don't do it again */
1016 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1018 if (dca_add_requester(dev) == 0) {
1019 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1020 ixgbe_setup_dca(adapter);
1023 /* Fall Through since DCA is disabled. */
1024 case DCA_PROVIDER_REMOVE:
1025 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1026 dca_remove_requester(dev);
1027 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1035 #endif /* CONFIG_IXGBE_DCA */
1037 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1038 struct sk_buff *skb)
1040 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1044 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1045 * @adapter: address of board private structure
1046 * @rx_desc: advanced rx descriptor
1048 * Returns : true if it is FCoE pkt
1050 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1051 union ixgbe_adv_rx_desc *rx_desc)
1053 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1055 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1056 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1057 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1058 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1062 * ixgbe_receive_skb - Send a completed packet up the stack
1063 * @adapter: board private structure
1064 * @skb: packet to send up
1065 * @status: hardware indication of status of receive
1066 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1067 * @rx_desc: rx descriptor
1069 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1070 struct sk_buff *skb, u8 status,
1071 struct ixgbe_ring *ring,
1072 union ixgbe_adv_rx_desc *rx_desc)
1074 struct ixgbe_adapter *adapter = q_vector->adapter;
1075 struct napi_struct *napi = &q_vector->napi;
1076 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1077 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1079 if (is_vlan && (tag & VLAN_VID_MASK))
1080 __vlan_hwaccel_put_tag(skb, tag);
1082 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1083 napi_gro_receive(napi, skb);
1089 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1090 * @adapter: address of board private structure
1091 * @status_err: hardware indication of status of receive
1092 * @skb: skb currently being received and modified
1093 * @status_err: status error value of last descriptor in packet
1095 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1096 union ixgbe_adv_rx_desc *rx_desc,
1097 struct sk_buff *skb,
1100 skb->ip_summed = CHECKSUM_NONE;
1102 /* Rx csum disabled */
1103 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1106 /* if IP and error */
1107 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1108 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1109 adapter->hw_csum_rx_error++;
1113 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1116 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1117 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1120 * 82599 errata, UDP frames with a 0 checksum can be marked as
1123 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1124 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1127 adapter->hw_csum_rx_error++;
1131 /* It must be a TCP or UDP packet with a valid checksum */
1132 skb->ip_summed = CHECKSUM_UNNECESSARY;
1135 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1138 * Force memory writes to complete before letting h/w
1139 * know there are new descriptors to fetch. (Only
1140 * applicable for weak-ordered memory model archs,
1144 writel(val, rx_ring->tail);
1148 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1149 * @rx_ring: ring to place buffers on
1150 * @cleaned_count: number of buffers to replace
1152 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1154 union ixgbe_adv_rx_desc *rx_desc;
1155 struct ixgbe_rx_buffer *bi;
1156 struct sk_buff *skb;
1157 u16 i = rx_ring->next_to_use;
1159 /* do nothing if no valid netdev defined */
1160 if (!rx_ring->netdev)
1163 while (cleaned_count--) {
1164 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1165 bi = &rx_ring->rx_buffer_info[i];
1169 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1170 rx_ring->rx_buf_len);
1172 rx_ring->rx_stats.alloc_rx_buff_failed++;
1175 /* initialize queue mapping */
1176 skb_record_rx_queue(skb, rx_ring->queue_index);
1181 bi->dma = dma_map_single(rx_ring->dev,
1183 rx_ring->rx_buf_len,
1185 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1186 rx_ring->rx_stats.alloc_rx_buff_failed++;
1192 if (ring_is_ps_enabled(rx_ring)) {
1194 bi->page = netdev_alloc_page(rx_ring->netdev);
1196 rx_ring->rx_stats.alloc_rx_page_failed++;
1201 if (!bi->page_dma) {
1202 /* use a half page if we're re-using */
1203 bi->page_offset ^= PAGE_SIZE / 2;
1204 bi->page_dma = dma_map_page(rx_ring->dev,
1209 if (dma_mapping_error(rx_ring->dev,
1211 rx_ring->rx_stats.alloc_rx_page_failed++;
1217 /* Refresh the desc even if buffer_addrs didn't change
1218 * because each write-back erases this info. */
1219 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1220 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1222 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1223 rx_desc->read.hdr_addr = 0;
1227 if (i == rx_ring->count)
1232 if (rx_ring->next_to_use != i) {
1233 rx_ring->next_to_use = i;
1234 ixgbe_release_rx_desc(rx_ring, i);
1238 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1240 /* HW will not DMA in data larger than the given buffer, even if it
1241 * parses the (NFS, of course) header to be larger. In that case, it
1242 * fills the header buffer and spills the rest into the page.
1244 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1245 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1246 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1247 if (hlen > IXGBE_RX_HDR_SIZE)
1248 hlen = IXGBE_RX_HDR_SIZE;
1253 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1254 * @skb: pointer to the last skb in the rsc queue
1256 * This function changes a queue full of hw rsc buffers into a completed
1257 * packet. It uses the ->prev pointers to find the first packet and then
1258 * turns it into the frag list owner.
1260 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1262 unsigned int frag_list_size = 0;
1263 unsigned int skb_cnt = 1;
1266 struct sk_buff *prev = skb->prev;
1267 frag_list_size += skb->len;
1273 skb_shinfo(skb)->frag_list = skb->next;
1275 skb->len += frag_list_size;
1276 skb->data_len += frag_list_size;
1277 skb->truesize += frag_list_size;
1278 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1283 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1285 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1286 IXGBE_RXDADV_RSCCNT_MASK);
1289 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1290 struct ixgbe_ring *rx_ring,
1291 int *work_done, int work_to_do)
1293 struct ixgbe_adapter *adapter = q_vector->adapter;
1294 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1295 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1296 struct sk_buff *skb;
1297 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1298 const int current_node = numa_node_id();
1301 #endif /* IXGBE_FCOE */
1304 u16 cleaned_count = 0;
1305 bool pkt_is_rsc = false;
1307 i = rx_ring->next_to_clean;
1308 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1309 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1311 while (staterr & IXGBE_RXD_STAT_DD) {
1314 rmb(); /* read descriptor and rx_buffer_info after status DD */
1316 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1318 skb = rx_buffer_info->skb;
1319 rx_buffer_info->skb = NULL;
1320 prefetch(skb->data);
1322 if (ring_is_rsc_enabled(rx_ring))
1323 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1325 /* if this is a skb from previous receive DMA will be 0 */
1326 if (rx_buffer_info->dma) {
1329 !(staterr & IXGBE_RXD_STAT_EOP) &&
1332 * When HWRSC is enabled, delay unmapping
1333 * of the first packet. It carries the
1334 * header information, HW may still
1335 * access the header after the writeback.
1336 * Only unmap it when EOP is reached
1338 IXGBE_RSC_CB(skb)->delay_unmap = true;
1339 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1341 dma_unmap_single(rx_ring->dev,
1342 rx_buffer_info->dma,
1343 rx_ring->rx_buf_len,
1346 rx_buffer_info->dma = 0;
1348 if (ring_is_ps_enabled(rx_ring)) {
1349 hlen = ixgbe_get_hlen(rx_desc);
1350 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1352 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1357 /* assume packet split since header is unmapped */
1358 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1362 dma_unmap_page(rx_ring->dev,
1363 rx_buffer_info->page_dma,
1366 rx_buffer_info->page_dma = 0;
1367 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1368 rx_buffer_info->page,
1369 rx_buffer_info->page_offset,
1372 if ((page_count(rx_buffer_info->page) == 1) &&
1373 (page_to_nid(rx_buffer_info->page) == current_node))
1374 get_page(rx_buffer_info->page);
1376 rx_buffer_info->page = NULL;
1378 skb->len += upper_len;
1379 skb->data_len += upper_len;
1380 skb->truesize += upper_len;
1384 if (i == rx_ring->count)
1387 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1392 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1393 IXGBE_RXDADV_NEXTP_SHIFT;
1394 next_buffer = &rx_ring->rx_buffer_info[nextp];
1396 next_buffer = &rx_ring->rx_buffer_info[i];
1399 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1400 if (ring_is_ps_enabled(rx_ring)) {
1401 rx_buffer_info->skb = next_buffer->skb;
1402 rx_buffer_info->dma = next_buffer->dma;
1403 next_buffer->skb = skb;
1404 next_buffer->dma = 0;
1406 skb->next = next_buffer->skb;
1407 skb->next->prev = skb;
1409 rx_ring->rx_stats.non_eop_descs++;
1414 skb = ixgbe_transform_rsc_queue(skb);
1415 /* if we got here without RSC the packet is invalid */
1417 __pskb_trim(skb, 0);
1418 rx_buffer_info->skb = skb;
1423 if (ring_is_rsc_enabled(rx_ring)) {
1424 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1425 dma_unmap_single(rx_ring->dev,
1426 IXGBE_RSC_CB(skb)->dma,
1427 rx_ring->rx_buf_len,
1429 IXGBE_RSC_CB(skb)->dma = 0;
1430 IXGBE_RSC_CB(skb)->delay_unmap = false;
1434 if (ring_is_ps_enabled(rx_ring))
1435 rx_ring->rx_stats.rsc_count +=
1436 skb_shinfo(skb)->nr_frags;
1438 rx_ring->rx_stats.rsc_count +=
1439 IXGBE_RSC_CB(skb)->skb_cnt;
1440 rx_ring->rx_stats.rsc_flush++;
1443 /* ERR_MASK will only have valid bits if EOP set */
1444 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1445 dev_kfree_skb_any(skb);
1449 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1450 if (adapter->netdev->features & NETIF_F_RXHASH)
1451 ixgbe_rx_hash(rx_desc, skb);
1453 /* probably a little skewed due to removing CRC */
1454 total_rx_bytes += skb->len;
1457 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1459 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1460 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1461 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1466 #endif /* IXGBE_FCOE */
1467 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1470 rx_desc->wb.upper.status_error = 0;
1473 if (*work_done >= work_to_do)
1476 /* return some buffers to hardware, one at a time is too slow */
1477 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1478 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482 /* use prefetched values */
1484 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1487 rx_ring->next_to_clean = i;
1488 cleaned_count = ixgbe_desc_unused(rx_ring);
1491 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1494 /* include DDPed FCoE data */
1495 if (ddp_bytes > 0) {
1498 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1499 sizeof(struct fc_frame_header) -
1500 sizeof(struct fcoe_crc_eof);
1503 total_rx_bytes += ddp_bytes;
1504 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1506 #endif /* IXGBE_FCOE */
1508 u64_stats_update_begin(&rx_ring->syncp);
1509 rx_ring->stats.packets += total_rx_packets;
1510 rx_ring->stats.bytes += total_rx_bytes;
1511 u64_stats_update_end(&rx_ring->syncp);
1512 q_vector->rx.total_packets += total_rx_packets;
1513 q_vector->rx.total_bytes += total_rx_bytes;
1516 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1518 * ixgbe_configure_msix - Configure MSI-X hardware
1519 * @adapter: board private structure
1521 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1524 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1526 struct ixgbe_q_vector *q_vector;
1527 int i, q_vectors, v_idx, r_idx;
1530 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1533 * Populate the IVAR table and set the ITR values to the
1534 * corresponding register.
1536 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1537 q_vector = adapter->q_vector[v_idx];
1538 /* XXX for_each_set_bit(...) */
1539 r_idx = find_first_bit(q_vector->rx.idx,
1540 adapter->num_rx_queues);
1542 for (i = 0; i < q_vector->rx.count; i++) {
1543 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1544 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1545 r_idx = find_next_bit(q_vector->rx.idx,
1546 adapter->num_rx_queues,
1549 r_idx = find_first_bit(q_vector->tx.idx,
1550 adapter->num_tx_queues);
1552 for (i = 0; i < q_vector->tx.count; i++) {
1553 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1554 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1555 r_idx = find_next_bit(q_vector->tx.idx,
1556 adapter->num_tx_queues,
1560 if (q_vector->tx.count && !q_vector->rx.count)
1562 q_vector->eitr = adapter->tx_eitr_param;
1563 else if (q_vector->rx.count)
1565 q_vector->eitr = adapter->rx_eitr_param;
1567 ixgbe_write_eitr(q_vector);
1568 /* If ATR is enabled, set interrupt affinity */
1569 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1571 * Allocate the affinity_hint cpumask, assign the mask
1572 * for this vector, and set our affinity_hint for
1575 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1578 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1579 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1580 q_vector->affinity_mask);
1584 switch (adapter->hw.mac.type) {
1585 case ixgbe_mac_82598EB:
1586 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1589 case ixgbe_mac_82599EB:
1590 case ixgbe_mac_X540:
1591 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1599 /* set up to autoclear timer, and the vectors */
1600 mask = IXGBE_EIMS_ENABLE_MASK;
1601 if (adapter->num_vfs)
1602 mask &= ~(IXGBE_EIMS_OTHER |
1603 IXGBE_EIMS_MAILBOX |
1606 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1610 enum latency_range {
1614 latency_invalid = 255
1618 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1619 * @q_vector: structure containing interrupt and ring information
1620 * @ring_container: structure containing ring performance data
1622 * Stores a new ITR value based on packets and byte
1623 * counts during the last interrupt. The advantage of per interrupt
1624 * computation is faster updates and more accurate ITR for the current
1625 * traffic pattern. Constants in this function were computed
1626 * based on theoretical maximum wire speed and thresholds were set based
1627 * on testing data as well as attempting to minimize response time
1628 * while increasing bulk throughput.
1629 * this functionality is controlled by the InterruptThrottleRate module
1630 * parameter (see ixgbe_param.c)
1632 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1633 struct ixgbe_ring_container *ring_container)
1636 struct ixgbe_adapter *adapter = q_vector->adapter;
1637 int bytes = ring_container->total_bytes;
1638 int packets = ring_container->total_packets;
1640 u8 itr_setting = ring_container->itr;
1645 /* simple throttlerate management
1646 * 0-20MB/s lowest (100000 ints/s)
1647 * 20-100MB/s low (20000 ints/s)
1648 * 100-1249MB/s bulk (8000 ints/s)
1650 /* what was last interrupt timeslice? */
1651 timepassed_us = 1000000/q_vector->eitr;
1652 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1654 switch (itr_setting) {
1655 case lowest_latency:
1656 if (bytes_perint > adapter->eitr_low)
1657 itr_setting = low_latency;
1660 if (bytes_perint > adapter->eitr_high)
1661 itr_setting = bulk_latency;
1662 else if (bytes_perint <= adapter->eitr_low)
1663 itr_setting = lowest_latency;
1666 if (bytes_perint <= adapter->eitr_high)
1667 itr_setting = low_latency;
1671 /* clear work counters since we have the values we need */
1672 ring_container->total_bytes = 0;
1673 ring_container->total_packets = 0;
1675 /* write updated itr to ring container */
1676 ring_container->itr = itr_setting;
1680 * ixgbe_write_eitr - write EITR register in hardware specific way
1681 * @q_vector: structure containing interrupt and ring information
1683 * This function is made to be called by ethtool and by the driver
1684 * when it needs to update EITR registers at runtime. Hardware
1685 * specific quirks/differences are taken care of here.
1687 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1689 struct ixgbe_adapter *adapter = q_vector->adapter;
1690 struct ixgbe_hw *hw = &adapter->hw;
1691 int v_idx = q_vector->v_idx;
1692 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1694 switch (adapter->hw.mac.type) {
1695 case ixgbe_mac_82598EB:
1696 /* must write high and low 16 bits to reset counter */
1697 itr_reg |= (itr_reg << 16);
1699 case ixgbe_mac_82599EB:
1700 case ixgbe_mac_X540:
1702 * 82599 and X540 can support a value of zero, so allow it for
1703 * max interrupt rate, but there is an errata where it can
1704 * not be zero with RSC
1707 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1711 * set the WDIS bit to not clear the timer bits and cause an
1712 * immediate assertion of the interrupt
1714 itr_reg |= IXGBE_EITR_CNT_WDIS;
1719 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1722 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1724 u32 new_itr = q_vector->eitr;
1727 ixgbe_update_itr(q_vector, &q_vector->tx);
1728 ixgbe_update_itr(q_vector, &q_vector->rx);
1730 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1732 switch (current_itr) {
1733 /* counts and packets in update_itr are dependent on these numbers */
1734 case lowest_latency:
1738 new_itr = 20000; /* aka hwitr = ~200 */
1747 if (new_itr != q_vector->eitr) {
1748 /* do an exponential smoothing */
1749 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1751 /* save the algorithm value here */
1752 q_vector->eitr = new_itr;
1754 ixgbe_write_eitr(q_vector);
1759 * ixgbe_check_overtemp_subtask - check for over tempurature
1760 * @adapter: pointer to adapter
1762 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1764 struct ixgbe_hw *hw = &adapter->hw;
1765 u32 eicr = adapter->interrupt_event;
1767 if (test_bit(__IXGBE_DOWN, &adapter->state))
1770 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1771 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1774 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1776 switch (hw->device_id) {
1777 case IXGBE_DEV_ID_82599_T3_LOM:
1779 * Since the warning interrupt is for both ports
1780 * we don't have to check if:
1781 * - This interrupt wasn't for our port.
1782 * - We may have missed the interrupt so always have to
1783 * check if we got a LSC
1785 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1786 !(eicr & IXGBE_EICR_LSC))
1789 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1791 bool link_up = false;
1793 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1799 /* Check if this is not due to overtemp */
1800 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1805 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1810 "Network adapter has been stopped because it has over heated. "
1811 "Restart the computer. If the problem persists, "
1812 "power off the system and replace the adapter\n");
1814 adapter->interrupt_event = 0;
1817 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1819 struct ixgbe_hw *hw = &adapter->hw;
1821 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1822 (eicr & IXGBE_EICR_GPI_SDP1)) {
1823 e_crit(probe, "Fan has stopped, replace the adapter\n");
1824 /* write to clear the interrupt */
1825 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1829 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1831 struct ixgbe_hw *hw = &adapter->hw;
1833 if (eicr & IXGBE_EICR_GPI_SDP2) {
1834 /* Clear the interrupt */
1835 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1836 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1837 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1838 ixgbe_service_event_schedule(adapter);
1842 if (eicr & IXGBE_EICR_GPI_SDP1) {
1843 /* Clear the interrupt */
1844 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1845 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1846 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1847 ixgbe_service_event_schedule(adapter);
1852 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1854 struct ixgbe_hw *hw = &adapter->hw;
1857 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1858 adapter->link_check_timeout = jiffies;
1859 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1860 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1861 IXGBE_WRITE_FLUSH(hw);
1862 ixgbe_service_event_schedule(adapter);
1866 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1868 struct ixgbe_adapter *adapter = data;
1869 struct ixgbe_hw *hw = &adapter->hw;
1873 * Workaround for Silicon errata. Use clear-by-write instead
1874 * of clear-by-read. Reading with EICS will return the
1875 * interrupt causes without clearing, which later be done
1876 * with the write to EICR.
1878 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1879 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1881 if (eicr & IXGBE_EICR_LSC)
1882 ixgbe_check_lsc(adapter);
1884 if (eicr & IXGBE_EICR_MAILBOX)
1885 ixgbe_msg_task(adapter);
1887 switch (hw->mac.type) {
1888 case ixgbe_mac_82599EB:
1889 case ixgbe_mac_X540:
1890 /* Handle Flow Director Full threshold interrupt */
1891 if (eicr & IXGBE_EICR_FLOW_DIR) {
1892 int reinit_count = 0;
1894 for (i = 0; i < adapter->num_tx_queues; i++) {
1895 struct ixgbe_ring *ring = adapter->tx_ring[i];
1896 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1901 /* no more flow director interrupts until after init */
1902 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1903 eicr &= ~IXGBE_EICR_FLOW_DIR;
1904 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1905 ixgbe_service_event_schedule(adapter);
1908 ixgbe_check_sfp_event(adapter, eicr);
1909 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1910 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1911 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1912 adapter->interrupt_event = eicr;
1913 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1914 ixgbe_service_event_schedule(adapter);
1922 ixgbe_check_fan_failure(adapter, eicr);
1924 /* re-enable the original interrupt state, no lsc, no queues */
1925 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1926 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1927 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1932 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1936 struct ixgbe_hw *hw = &adapter->hw;
1938 switch (hw->mac.type) {
1939 case ixgbe_mac_82598EB:
1940 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1941 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1943 case ixgbe_mac_82599EB:
1944 case ixgbe_mac_X540:
1945 mask = (qmask & 0xFFFFFFFF);
1947 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1948 mask = (qmask >> 32);
1950 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1955 /* skip the flush */
1958 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1962 struct ixgbe_hw *hw = &adapter->hw;
1964 switch (hw->mac.type) {
1965 case ixgbe_mac_82598EB:
1966 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1967 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1969 case ixgbe_mac_82599EB:
1970 case ixgbe_mac_X540:
1971 mask = (qmask & 0xFFFFFFFF);
1973 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1974 mask = (qmask >> 32);
1976 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1981 /* skip the flush */
1984 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1986 struct ixgbe_q_vector *q_vector = data;
1987 struct ixgbe_adapter *adapter = q_vector->adapter;
1988 struct ixgbe_ring *tx_ring;
1991 if (!q_vector->tx.count)
1994 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1995 for (i = 0; i < q_vector->tx.count; i++) {
1996 tx_ring = adapter->tx_ring[r_idx];
1997 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2001 /* EIAM disabled interrupts (on this vector) for us */
2002 napi_schedule(&q_vector->napi);
2008 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2010 * @data: pointer to our q_vector struct for this interrupt vector
2012 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2014 struct ixgbe_q_vector *q_vector = data;
2015 struct ixgbe_adapter *adapter = q_vector->adapter;
2016 struct ixgbe_ring *rx_ring;
2020 #ifdef CONFIG_IXGBE_DCA
2021 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2022 ixgbe_update_dca(q_vector);
2025 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2026 for (i = 0; i < q_vector->rx.count; i++) {
2027 rx_ring = adapter->rx_ring[r_idx];
2028 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2032 if (!q_vector->rx.count)
2035 /* EIAM disabled interrupts (on this vector) for us */
2036 napi_schedule(&q_vector->napi);
2041 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2043 struct ixgbe_q_vector *q_vector = data;
2044 struct ixgbe_adapter *adapter = q_vector->adapter;
2045 struct ixgbe_ring *ring;
2049 if (!q_vector->tx.count && !q_vector->rx.count)
2052 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2053 for (i = 0; i < q_vector->tx.count; i++) {
2054 ring = adapter->tx_ring[r_idx];
2055 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2059 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2060 for (i = 0; i < q_vector->rx.count; i++) {
2061 ring = adapter->rx_ring[r_idx];
2062 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2066 /* EIAM disabled interrupts (on this vector) for us */
2067 napi_schedule(&q_vector->napi);
2073 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2074 * @napi: napi struct with our devices info in it
2075 * @budget: amount of work driver is allowed to do this pass, in packets
2077 * This function is optimized for cleaning one queue only on a single
2080 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2082 struct ixgbe_q_vector *q_vector =
2083 container_of(napi, struct ixgbe_q_vector, napi);
2084 struct ixgbe_adapter *adapter = q_vector->adapter;
2085 struct ixgbe_ring *rx_ring = NULL;
2089 #ifdef CONFIG_IXGBE_DCA
2090 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2091 ixgbe_update_dca(q_vector);
2094 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2095 rx_ring = adapter->rx_ring[r_idx];
2097 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2099 /* If all Rx work done, exit the polling mode */
2100 if (work_done < budget) {
2101 napi_complete(napi);
2102 if (adapter->rx_itr_setting & 1)
2103 ixgbe_set_itr(q_vector);
2104 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2105 ixgbe_irq_enable_queues(adapter,
2106 ((u64)1 << q_vector->v_idx));
2113 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2114 * @napi: napi struct with our devices info in it
2115 * @budget: amount of work driver is allowed to do this pass, in packets
2117 * This function will clean more than one rx queue associated with a
2120 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2122 struct ixgbe_q_vector *q_vector =
2123 container_of(napi, struct ixgbe_q_vector, napi);
2124 struct ixgbe_adapter *adapter = q_vector->adapter;
2125 struct ixgbe_ring *ring = NULL;
2126 int work_done = 0, i;
2128 bool tx_clean_complete = true;
2130 #ifdef CONFIG_IXGBE_DCA
2131 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2132 ixgbe_update_dca(q_vector);
2135 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2136 for (i = 0; i < q_vector->tx.count; i++) {
2137 ring = adapter->tx_ring[r_idx];
2138 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2139 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2143 /* attempt to distribute budget to each queue fairly, but don't allow
2144 * the budget to go below 1 because we'll exit polling */
2145 budget /= (q_vector->rx.count ?: 1);
2146 budget = max(budget, 1);
2147 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2148 for (i = 0; i < q_vector->rx.count; i++) {
2149 ring = adapter->rx_ring[r_idx];
2150 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2151 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2155 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2156 ring = adapter->rx_ring[r_idx];
2157 /* If all Rx work done, exit the polling mode */
2158 if (work_done < budget) {
2159 napi_complete(napi);
2160 if (adapter->rx_itr_setting & 1)
2161 ixgbe_set_itr(q_vector);
2162 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2163 ixgbe_irq_enable_queues(adapter,
2164 ((u64)1 << q_vector->v_idx));
2172 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2173 * @napi: napi struct with our devices info in it
2174 * @budget: amount of work driver is allowed to do this pass, in packets
2176 * This function is optimized for cleaning one queue only on a single
2179 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2181 struct ixgbe_q_vector *q_vector =
2182 container_of(napi, struct ixgbe_q_vector, napi);
2183 struct ixgbe_adapter *adapter = q_vector->adapter;
2184 struct ixgbe_ring *tx_ring = NULL;
2188 #ifdef CONFIG_IXGBE_DCA
2189 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2190 ixgbe_update_dca(q_vector);
2193 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2194 tx_ring = adapter->tx_ring[r_idx];
2196 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2199 /* If all Tx work done, exit the polling mode */
2200 if (work_done < budget) {
2201 napi_complete(napi);
2202 if (adapter->tx_itr_setting & 1)
2203 ixgbe_set_itr(q_vector);
2204 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2205 ixgbe_irq_enable_queues(adapter,
2206 ((u64)1 << q_vector->v_idx));
2212 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2215 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2216 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2218 set_bit(r_idx, q_vector->rx.idx);
2219 q_vector->rx.count++;
2220 rx_ring->q_vector = q_vector;
2223 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2226 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2227 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2229 set_bit(t_idx, q_vector->tx.idx);
2230 q_vector->tx.count++;
2231 tx_ring->q_vector = q_vector;
2232 q_vector->tx.work_limit = a->tx_work_limit;
2236 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2237 * @adapter: board private structure to initialize
2239 * This function maps descriptor rings to the queue-specific vectors
2240 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2241 * one vector per ring/queue, but on a constrained vector budget, we
2242 * group the rings as "efficiently" as possible. You would add new
2243 * mapping configurations in here.
2245 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2249 int rxr_idx = 0, txr_idx = 0;
2250 int rxr_remaining = adapter->num_rx_queues;
2251 int txr_remaining = adapter->num_tx_queues;
2256 /* No mapping required if MSI-X is disabled. */
2257 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2260 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2263 * The ideal configuration...
2264 * We have enough vectors to map one per queue.
2266 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2267 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2268 map_vector_to_rxq(adapter, v_start, rxr_idx);
2270 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2271 map_vector_to_txq(adapter, v_start, txr_idx);
2277 * If we don't have enough vectors for a 1-to-1
2278 * mapping, we'll have to group them so there are
2279 * multiple queues per vector.
2281 /* Re-adjusting *qpv takes care of the remainder. */
2282 for (i = v_start; i < q_vectors; i++) {
2283 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2284 for (j = 0; j < rqpv; j++) {
2285 map_vector_to_rxq(adapter, i, rxr_idx);
2289 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2290 for (j = 0; j < tqpv; j++) {
2291 map_vector_to_txq(adapter, i, txr_idx);
2301 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2302 * @adapter: board private structure
2304 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2305 * interrupts from the kernel.
2307 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2309 struct net_device *netdev = adapter->netdev;
2310 irqreturn_t (*handler)(int, void *);
2311 int i, vector, q_vectors, err;
2314 /* Decrement for Other and TCP Timer vectors */
2315 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2317 err = ixgbe_map_rings_to_vectors(adapter);
2321 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2322 ? &ixgbe_msix_clean_many : \
2323 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2324 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2326 for (vector = 0; vector < q_vectors; vector++) {
2327 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2328 handler = SET_HANDLER(q_vector);
2330 if (handler == &ixgbe_msix_clean_rx) {
2331 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2332 "%s-%s-%d", netdev->name, "rx", ri++);
2333 } else if (handler == &ixgbe_msix_clean_tx) {
2334 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2335 "%s-%s-%d", netdev->name, "tx", ti++);
2336 } else if (handler == &ixgbe_msix_clean_many) {
2337 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2338 "%s-%s-%d", netdev->name, "TxRx", ri++);
2341 /* skip this unused q_vector */
2344 err = request_irq(adapter->msix_entries[vector].vector,
2345 handler, 0, q_vector->name,
2348 e_err(probe, "request_irq failed for MSIX interrupt "
2349 "Error: %d\n", err);
2350 goto free_queue_irqs;
2354 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2355 err = request_irq(adapter->msix_entries[vector].vector,
2356 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2358 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2359 goto free_queue_irqs;
2365 for (i = vector - 1; i >= 0; i--)
2366 free_irq(adapter->msix_entries[--vector].vector,
2367 adapter->q_vector[i]);
2368 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2369 pci_disable_msix(adapter->pdev);
2370 kfree(adapter->msix_entries);
2371 adapter->msix_entries = NULL;
2376 * ixgbe_irq_enable - Enable default interrupt generation settings
2377 * @adapter: board private structure
2379 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2384 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2385 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2386 mask |= IXGBE_EIMS_GPI_SDP0;
2387 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2388 mask |= IXGBE_EIMS_GPI_SDP1;
2389 switch (adapter->hw.mac.type) {
2390 case ixgbe_mac_82599EB:
2391 case ixgbe_mac_X540:
2392 mask |= IXGBE_EIMS_ECC;
2393 mask |= IXGBE_EIMS_GPI_SDP1;
2394 mask |= IXGBE_EIMS_GPI_SDP2;
2395 if (adapter->num_vfs)
2396 mask |= IXGBE_EIMS_MAILBOX;
2401 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2402 mask |= IXGBE_EIMS_FLOW_DIR;
2404 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2406 ixgbe_irq_enable_queues(adapter, ~0);
2408 IXGBE_WRITE_FLUSH(&adapter->hw);
2410 if (adapter->num_vfs > 32) {
2411 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2412 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2417 * ixgbe_intr - legacy mode Interrupt Handler
2418 * @irq: interrupt number
2419 * @data: pointer to a network interface device structure
2421 static irqreturn_t ixgbe_intr(int irq, void *data)
2423 struct ixgbe_adapter *adapter = data;
2424 struct ixgbe_hw *hw = &adapter->hw;
2425 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2429 * Workaround for silicon errata on 82598. Mask the interrupts
2430 * before the read of EICR.
2432 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2434 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2435 * therefore no explict interrupt disable is necessary */
2436 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2439 * shared interrupt alert!
2440 * make sure interrupts are enabled because the read will
2441 * have disabled interrupts due to EIAM
2442 * finish the workaround of silicon errata on 82598. Unmask
2443 * the interrupt that we masked before the EICR read.
2445 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2446 ixgbe_irq_enable(adapter, true, true);
2447 return IRQ_NONE; /* Not our interrupt */
2450 if (eicr & IXGBE_EICR_LSC)
2451 ixgbe_check_lsc(adapter);
2453 switch (hw->mac.type) {
2454 case ixgbe_mac_82599EB:
2455 ixgbe_check_sfp_event(adapter, eicr);
2456 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2457 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2458 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2459 adapter->interrupt_event = eicr;
2460 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2461 ixgbe_service_event_schedule(adapter);
2469 ixgbe_check_fan_failure(adapter, eicr);
2471 if (napi_schedule_prep(&(q_vector->napi))) {
2472 /* would disable interrupts here but EIAM disabled it */
2473 __napi_schedule(&(q_vector->napi));
2477 * re-enable link(maybe) and non-queue interrupts, no flush.
2478 * ixgbe_poll will re-enable the queue interrupts
2481 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2482 ixgbe_irq_enable(adapter, false, false);
2487 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2489 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2491 for (i = 0; i < q_vectors; i++) {
2492 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2493 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2494 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2495 q_vector->rx.count = 0;
2496 q_vector->tx.count = 0;
2501 * ixgbe_request_irq - initialize interrupts
2502 * @adapter: board private structure
2504 * Attempts to configure interrupts using the best available
2505 * capabilities of the hardware and kernel.
2507 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2509 struct net_device *netdev = adapter->netdev;
2512 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2513 err = ixgbe_request_msix_irqs(adapter);
2514 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2515 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2516 netdev->name, adapter);
2518 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2519 netdev->name, adapter);
2523 e_err(probe, "request_irq failed, Error %d\n", err);
2528 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2530 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2533 q_vectors = adapter->num_msix_vectors;
2536 free_irq(adapter->msix_entries[i].vector, adapter);
2539 for (; i >= 0; i--) {
2540 /* free only the irqs that were actually requested */
2541 if (!adapter->q_vector[i]->rx.count &&
2542 !adapter->q_vector[i]->tx.count)
2545 free_irq(adapter->msix_entries[i].vector,
2546 adapter->q_vector[i]);
2549 ixgbe_reset_q_vectors(adapter);
2551 free_irq(adapter->pdev->irq, adapter);
2556 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2557 * @adapter: board private structure
2559 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2561 switch (adapter->hw.mac.type) {
2562 case ixgbe_mac_82598EB:
2563 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2565 case ixgbe_mac_82599EB:
2566 case ixgbe_mac_X540:
2567 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2569 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2570 if (adapter->num_vfs > 32)
2571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2576 IXGBE_WRITE_FLUSH(&adapter->hw);
2577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2579 for (i = 0; i < adapter->num_msix_vectors; i++)
2580 synchronize_irq(adapter->msix_entries[i].vector);
2582 synchronize_irq(adapter->pdev->irq);
2587 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2590 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2592 struct ixgbe_hw *hw = &adapter->hw;
2594 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2595 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2597 ixgbe_set_ivar(adapter, 0, 0, 0);
2598 ixgbe_set_ivar(adapter, 1, 0, 0);
2600 map_vector_to_rxq(adapter, 0, 0);
2601 map_vector_to_txq(adapter, 0, 0);
2603 e_info(hw, "Legacy interrupt IVAR setup done\n");
2607 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2608 * @adapter: board private structure
2609 * @ring: structure containing ring specific data
2611 * Configure the Tx descriptor ring after a reset.
2613 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2614 struct ixgbe_ring *ring)
2616 struct ixgbe_hw *hw = &adapter->hw;
2617 u64 tdba = ring->dma;
2620 u8 reg_idx = ring->reg_idx;
2622 /* disable queue to avoid issues while updating state */
2623 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2624 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2625 txdctl & ~IXGBE_TXDCTL_ENABLE);
2626 IXGBE_WRITE_FLUSH(hw);
2628 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2629 (tdba & DMA_BIT_MASK(32)));
2630 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2631 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2632 ring->count * sizeof(union ixgbe_adv_tx_desc));
2633 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2634 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2635 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2637 /* configure fetching thresholds */
2638 if (adapter->rx_itr_setting == 0) {
2639 /* cannot set wthresh when itr==0 */
2640 txdctl &= ~0x007F0000;
2642 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2643 txdctl |= (8 << 16);
2645 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2646 /* PThresh workaround for Tx hang with DFP enabled. */
2650 /* reinitialize flowdirector state */
2651 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2652 adapter->atr_sample_rate) {
2653 ring->atr_sample_rate = adapter->atr_sample_rate;
2654 ring->atr_count = 0;
2655 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2657 ring->atr_sample_rate = 0;
2660 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2663 txdctl |= IXGBE_TXDCTL_ENABLE;
2664 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2666 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2667 if (hw->mac.type == ixgbe_mac_82598EB &&
2668 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2671 /* poll to verify queue is enabled */
2673 usleep_range(1000, 2000);
2674 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2675 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2677 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2680 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2682 struct ixgbe_hw *hw = &adapter->hw;
2685 u8 tcs = netdev_get_num_tc(adapter->netdev);
2687 if (hw->mac.type == ixgbe_mac_82598EB)
2690 /* disable the arbiter while setting MTQC */
2691 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2692 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2693 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2695 /* set transmit pool layout */
2696 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2697 case (IXGBE_FLAG_SRIOV_ENABLED):
2698 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2699 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2703 reg = IXGBE_MTQC_64Q_1PB;
2705 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2707 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2709 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2711 /* Enable Security TX Buffer IFG for multiple pb */
2713 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2714 reg |= IXGBE_SECTX_DCB;
2715 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2720 /* re-enable the arbiter */
2721 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2722 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2726 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2727 * @adapter: board private structure
2729 * Configure the Tx unit of the MAC after a reset.
2731 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2733 struct ixgbe_hw *hw = &adapter->hw;
2737 ixgbe_setup_mtqc(adapter);
2739 if (hw->mac.type != ixgbe_mac_82598EB) {
2740 /* DMATXCTL.EN must be before Tx queues are enabled */
2741 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2742 dmatxctl |= IXGBE_DMATXCTL_TE;
2743 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2746 /* Setup the HW Tx Head and Tail descriptor pointers */
2747 for (i = 0; i < adapter->num_tx_queues; i++)
2748 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2751 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2753 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2754 struct ixgbe_ring *rx_ring)
2757 u8 reg_idx = rx_ring->reg_idx;
2759 switch (adapter->hw.mac.type) {
2760 case ixgbe_mac_82598EB: {
2761 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2762 const int mask = feature[RING_F_RSS].mask;
2763 reg_idx = reg_idx & mask;
2766 case ixgbe_mac_82599EB:
2767 case ixgbe_mac_X540:
2772 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2774 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2775 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2776 if (adapter->num_vfs)
2777 srrctl |= IXGBE_SRRCTL_DROP_EN;
2779 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2780 IXGBE_SRRCTL_BSIZEHDR_MASK;
2782 if (ring_is_ps_enabled(rx_ring)) {
2783 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2784 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2786 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2788 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2790 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2791 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2792 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2795 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2798 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2800 struct ixgbe_hw *hw = &adapter->hw;
2801 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2802 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2803 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2804 u32 mrqc = 0, reta = 0;
2807 u8 tcs = netdev_get_num_tc(adapter->netdev);
2808 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2811 maxq = min(maxq, adapter->num_tx_queues / tcs);
2813 /* Fill out hash function seeds */
2814 for (i = 0; i < 10; i++)
2815 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2817 /* Fill out redirection table */
2818 for (i = 0, j = 0; i < 128; i++, j++) {
2821 /* reta = 4-byte sliding window of
2822 * 0x00..(indices-1)(indices-1)00..etc. */
2823 reta = (reta << 8) | (j * 0x11);
2825 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2828 /* Disable indicating checksum in descriptor, enables RSS hash */
2829 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2830 rxcsum |= IXGBE_RXCSUM_PCSD;
2831 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2833 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2834 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2835 mrqc = IXGBE_MRQC_RSSEN;
2837 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2838 | IXGBE_FLAG_SRIOV_ENABLED);
2841 case (IXGBE_FLAG_RSS_ENABLED):
2843 mrqc = IXGBE_MRQC_RSSEN;
2845 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2847 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2849 case (IXGBE_FLAG_SRIOV_ENABLED):
2850 mrqc = IXGBE_MRQC_VMDQEN;
2857 /* Perform hash on these packet types */
2858 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2859 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2860 | IXGBE_MRQC_RSS_FIELD_IPV6
2861 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2863 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2867 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2868 * @adapter: address of board private structure
2869 * @index: index of ring to set
2871 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2872 struct ixgbe_ring *ring)
2874 struct ixgbe_hw *hw = &adapter->hw;
2877 u8 reg_idx = ring->reg_idx;
2879 if (!ring_is_rsc_enabled(ring))
2882 rx_buf_len = ring->rx_buf_len;
2883 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2884 rscctrl |= IXGBE_RSCCTL_RSCEN;
2886 * we must limit the number of descriptors so that the
2887 * total size of max desc * buf_len is not greater
2890 if (ring_is_ps_enabled(ring)) {
2891 #if (MAX_SKB_FRAGS > 16)
2892 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2893 #elif (MAX_SKB_FRAGS > 8)
2894 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2895 #elif (MAX_SKB_FRAGS > 4)
2896 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2898 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2901 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2902 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2903 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2904 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2906 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2908 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2912 * ixgbe_set_uta - Set unicast filter table address
2913 * @adapter: board private structure
2915 * The unicast table address is a register array of 32-bit registers.
2916 * The table is meant to be used in a way similar to how the MTA is used
2917 * however due to certain limitations in the hardware it is necessary to
2918 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2919 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2921 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2923 struct ixgbe_hw *hw = &adapter->hw;
2926 /* The UTA table only exists on 82599 hardware and newer */
2927 if (hw->mac.type < ixgbe_mac_82599EB)
2930 /* we only need to do this if VMDq is enabled */
2931 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2934 for (i = 0; i < 128; i++)
2935 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2938 #define IXGBE_MAX_RX_DESC_POLL 10
2939 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2940 struct ixgbe_ring *ring)
2942 struct ixgbe_hw *hw = &adapter->hw;
2943 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2945 u8 reg_idx = ring->reg_idx;
2947 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2948 if (hw->mac.type == ixgbe_mac_82598EB &&
2949 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2953 usleep_range(1000, 2000);
2954 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2955 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2958 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2959 "the polling period\n", reg_idx);
2963 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2964 struct ixgbe_ring *ring)
2966 struct ixgbe_hw *hw = &adapter->hw;
2967 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2969 u8 reg_idx = ring->reg_idx;
2971 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2972 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2974 /* write value back with RXDCTL.ENABLE bit cleared */
2975 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2977 if (hw->mac.type == ixgbe_mac_82598EB &&
2978 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2981 /* the hardware may take up to 100us to really disable the rx queue */
2984 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2985 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2988 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2989 "the polling period\n", reg_idx);
2993 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2994 struct ixgbe_ring *ring)
2996 struct ixgbe_hw *hw = &adapter->hw;
2997 u64 rdba = ring->dma;
2999 u8 reg_idx = ring->reg_idx;
3001 /* disable queue to avoid issues while updating state */
3002 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3003 ixgbe_disable_rx_queue(adapter, ring);
3005 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3006 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3007 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3008 ring->count * sizeof(union ixgbe_adv_rx_desc));
3009 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3010 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3011 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3013 ixgbe_configure_srrctl(adapter, ring);
3014 ixgbe_configure_rscctl(adapter, ring);
3016 /* If operating in IOV mode set RLPML for X540 */
3017 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3018 hw->mac.type == ixgbe_mac_X540) {
3019 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3020 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3021 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3024 if (hw->mac.type == ixgbe_mac_82598EB) {
3026 * enable cache line friendly hardware writes:
3027 * PTHRESH=32 descriptors (half the internal cache),
3028 * this also removes ugly rx_no_buffer_count increment
3029 * HTHRESH=4 descriptors (to minimize latency on fetch)
3030 * WTHRESH=8 burst writeback up to two cache lines
3032 rxdctl &= ~0x3FFFFF;
3036 /* enable receive descriptor ring */
3037 rxdctl |= IXGBE_RXDCTL_ENABLE;
3038 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3040 ixgbe_rx_desc_queue_enable(adapter, ring);
3041 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3044 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3046 struct ixgbe_hw *hw = &adapter->hw;
3049 /* PSRTYPE must be initialized in non 82598 adapters */
3050 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3051 IXGBE_PSRTYPE_UDPHDR |
3052 IXGBE_PSRTYPE_IPV4HDR |
3053 IXGBE_PSRTYPE_L2HDR |
3054 IXGBE_PSRTYPE_IPV6HDR;
3056 if (hw->mac.type == ixgbe_mac_82598EB)
3059 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3060 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3062 for (p = 0; p < adapter->num_rx_pools; p++)
3063 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3067 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3069 struct ixgbe_hw *hw = &adapter->hw;
3072 u32 reg_offset, vf_shift;
3075 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3078 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3079 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3080 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3081 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3083 vf_shift = adapter->num_vfs % 32;
3084 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3086 /* Enable only the PF's pool for Tx/Rx */
3087 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3088 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3089 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3090 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3091 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3093 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3094 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3097 * Set up VF register offsets for selected VT Mode,
3098 * i.e. 32 or 64 VFs for SR-IOV
3100 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3101 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3102 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3103 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3105 /* enable Tx loopback for VF/PF communication */
3106 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3107 /* Enable MAC Anti-Spoofing */
3108 hw->mac.ops.set_mac_anti_spoofing(hw,
3109 (adapter->antispoofing_enabled =
3110 (adapter->num_vfs != 0)),
3114 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3116 struct ixgbe_hw *hw = &adapter->hw;
3117 struct net_device *netdev = adapter->netdev;
3118 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3120 struct ixgbe_ring *rx_ring;
3124 /* Decide whether to use packet split mode or not */
3126 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3128 /* Do not use packet split if we're in SR-IOV Mode */
3129 if (adapter->num_vfs)
3130 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3132 /* Disable packet split due to 82599 erratum #45 */
3133 if (hw->mac.type == ixgbe_mac_82599EB)
3134 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3136 /* Set the RX buffer length according to the mode */
3137 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3138 rx_buf_len = IXGBE_RX_HDR_SIZE;
3140 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3141 (netdev->mtu <= ETH_DATA_LEN))
3142 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3144 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3148 /* adjust max frame to be able to do baby jumbo for FCoE */
3149 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3150 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3151 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3153 #endif /* IXGBE_FCOE */
3154 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3155 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3156 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3157 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3159 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3162 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3163 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3164 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3165 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3168 * Setup the HW Rx Head and Tail Descriptor Pointers and
3169 * the Base and Length of the Rx Descriptor Ring
3171 for (i = 0; i < adapter->num_rx_queues; i++) {
3172 rx_ring = adapter->rx_ring[i];
3173 rx_ring->rx_buf_len = rx_buf_len;
3175 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3176 set_ring_ps_enabled(rx_ring);
3178 clear_ring_ps_enabled(rx_ring);
3180 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3181 set_ring_rsc_enabled(rx_ring);
3183 clear_ring_rsc_enabled(rx_ring);
3186 if (netdev->features & NETIF_F_FCOE_MTU) {
3187 struct ixgbe_ring_feature *f;
3188 f = &adapter->ring_feature[RING_F_FCOE];
3189 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3190 clear_ring_ps_enabled(rx_ring);
3191 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3192 rx_ring->rx_buf_len =
3193 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3194 } else if (!ring_is_rsc_enabled(rx_ring) &&
3195 !ring_is_ps_enabled(rx_ring)) {
3196 rx_ring->rx_buf_len =
3197 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3200 #endif /* IXGBE_FCOE */
3204 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3206 struct ixgbe_hw *hw = &adapter->hw;
3207 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3209 switch (hw->mac.type) {
3210 case ixgbe_mac_82598EB:
3212 * For VMDq support of different descriptor types or
3213 * buffer sizes through the use of multiple SRRCTL
3214 * registers, RDRXCTL.MVMEN must be set to 1
3216 * also, the manual doesn't mention it clearly but DCA hints
3217 * will only use queue 0's tags unless this bit is set. Side
3218 * effects of setting this bit are only that SRRCTL must be
3219 * fully programmed [0..15]
3221 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3223 case ixgbe_mac_82599EB:
3224 case ixgbe_mac_X540:
3225 /* Disable RSC for ACK packets */
3226 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3227 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3228 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3229 /* hardware requires some bits to be set by default */
3230 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3231 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3234 /* We should do nothing since we don't know this hardware */
3238 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3242 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3243 * @adapter: board private structure
3245 * Configure the Rx unit of the MAC after a reset.
3247 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3249 struct ixgbe_hw *hw = &adapter->hw;
3253 /* disable receives while setting up the descriptors */
3254 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3255 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3257 ixgbe_setup_psrtype(adapter);
3258 ixgbe_setup_rdrxctl(adapter);
3260 /* Program registers for the distribution of queues */
3261 ixgbe_setup_mrqc(adapter);
3263 ixgbe_set_uta(adapter);
3265 /* set_rx_buffer_len must be called before ring initialization */
3266 ixgbe_set_rx_buffer_len(adapter);
3269 * Setup the HW Rx Head and Tail Descriptor Pointers and
3270 * the Base and Length of the Rx Descriptor Ring
3272 for (i = 0; i < adapter->num_rx_queues; i++)
3273 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3275 /* disable drop enable for 82598 parts */
3276 if (hw->mac.type == ixgbe_mac_82598EB)
3277 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3279 /* enable all receives */
3280 rxctrl |= IXGBE_RXCTRL_RXEN;
3281 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3284 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3286 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3287 struct ixgbe_hw *hw = &adapter->hw;
3288 int pool_ndx = adapter->num_vfs;
3290 /* add VID to filter table */
3291 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3292 set_bit(vid, adapter->active_vlans);
3295 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3297 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3298 struct ixgbe_hw *hw = &adapter->hw;
3299 int pool_ndx = adapter->num_vfs;
3301 /* remove VID from filter table */
3302 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3303 clear_bit(vid, adapter->active_vlans);
3307 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3308 * @adapter: driver data
3310 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3312 struct ixgbe_hw *hw = &adapter->hw;
3315 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3316 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3317 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3321 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3322 * @adapter: driver data
3324 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3326 struct ixgbe_hw *hw = &adapter->hw;
3329 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3330 vlnctrl |= IXGBE_VLNCTRL_VFE;
3331 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3332 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3336 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3337 * @adapter: driver data
3339 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3341 struct ixgbe_hw *hw = &adapter->hw;
3345 switch (hw->mac.type) {
3346 case ixgbe_mac_82598EB:
3347 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3348 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3349 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3351 case ixgbe_mac_82599EB:
3352 case ixgbe_mac_X540:
3353 for (i = 0; i < adapter->num_rx_queues; i++) {
3354 j = adapter->rx_ring[i]->reg_idx;
3355 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3356 vlnctrl &= ~IXGBE_RXDCTL_VME;
3357 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3366 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3367 * @adapter: driver data
3369 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3371 struct ixgbe_hw *hw = &adapter->hw;
3375 switch (hw->mac.type) {
3376 case ixgbe_mac_82598EB:
3377 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3378 vlnctrl |= IXGBE_VLNCTRL_VME;
3379 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3381 case ixgbe_mac_82599EB:
3382 case ixgbe_mac_X540:
3383 for (i = 0; i < adapter->num_rx_queues; i++) {
3384 j = adapter->rx_ring[i]->reg_idx;
3385 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3386 vlnctrl |= IXGBE_RXDCTL_VME;
3387 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3395 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3399 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3401 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3402 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3406 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3407 * @netdev: network interface device structure
3409 * Writes unicast address list to the RAR table.
3410 * Returns: -ENOMEM on failure/insufficient address space
3411 * 0 on no addresses written
3412 * X on writing X addresses to the RAR table
3414 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3416 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3417 struct ixgbe_hw *hw = &adapter->hw;
3418 unsigned int vfn = adapter->num_vfs;
3419 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3422 /* return ENOMEM indicating insufficient memory for addresses */
3423 if (netdev_uc_count(netdev) > rar_entries)
3426 if (!netdev_uc_empty(netdev) && rar_entries) {
3427 struct netdev_hw_addr *ha;
3428 /* return error if we do not support writing to RAR table */
3429 if (!hw->mac.ops.set_rar)
3432 netdev_for_each_uc_addr(ha, netdev) {
3435 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3440 /* write the addresses in reverse order to avoid write combining */
3441 for (; rar_entries > 0 ; rar_entries--)
3442 hw->mac.ops.clear_rar(hw, rar_entries);
3448 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3449 * @netdev: network interface device structure
3451 * The set_rx_method entry point is called whenever the unicast/multicast
3452 * address list or the network interface flags are updated. This routine is
3453 * responsible for configuring the hardware for proper unicast, multicast and
3456 void ixgbe_set_rx_mode(struct net_device *netdev)
3458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3459 struct ixgbe_hw *hw = &adapter->hw;
3460 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3463 /* Check for Promiscuous and All Multicast modes */
3465 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3467 /* set all bits that we expect to always be set */
3468 fctrl |= IXGBE_FCTRL_BAM;
3469 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3470 fctrl |= IXGBE_FCTRL_PMCF;
3472 /* clear the bits we are changing the status of */
3473 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3475 if (netdev->flags & IFF_PROMISC) {
3476 hw->addr_ctrl.user_set_promisc = true;
3477 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3478 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3479 /* don't hardware filter vlans in promisc mode */
3480 ixgbe_vlan_filter_disable(adapter);
3482 if (netdev->flags & IFF_ALLMULTI) {
3483 fctrl |= IXGBE_FCTRL_MPE;
3484 vmolr |= IXGBE_VMOLR_MPE;
3487 * Write addresses to the MTA, if the attempt fails
3488 * then we should just turn on promiscuous mode so
3489 * that we can at least receive multicast traffic
3491 hw->mac.ops.update_mc_addr_list(hw, netdev);
3492 vmolr |= IXGBE_VMOLR_ROMPE;
3494 ixgbe_vlan_filter_enable(adapter);
3495 hw->addr_ctrl.user_set_promisc = false;
3497 * Write addresses to available RAR registers, if there is not
3498 * sufficient space to store all the addresses then enable
3499 * unicast promiscuous mode
3501 count = ixgbe_write_uc_addr_list(netdev);
3503 fctrl |= IXGBE_FCTRL_UPE;
3504 vmolr |= IXGBE_VMOLR_ROPE;
3508 if (adapter->num_vfs) {
3509 ixgbe_restore_vf_multicasts(adapter);
3510 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3511 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3513 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3516 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3518 if (netdev->features & NETIF_F_HW_VLAN_RX)
3519 ixgbe_vlan_strip_enable(adapter);
3521 ixgbe_vlan_strip_disable(adapter);
3524 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3527 struct ixgbe_q_vector *q_vector;
3528 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3530 /* legacy and MSI only use one vector */
3531 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3534 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3535 struct napi_struct *napi;
3536 q_vector = adapter->q_vector[q_idx];
3537 napi = &q_vector->napi;
3538 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3539 if (!q_vector->rx.count || !q_vector->tx.count) {
3540 if (q_vector->tx.count == 1)
3541 napi->poll = &ixgbe_clean_txonly;
3542 else if (q_vector->rx.count == 1)
3543 napi->poll = &ixgbe_clean_rxonly;
3551 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3554 struct ixgbe_q_vector *q_vector;
3555 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3557 /* legacy and MSI only use one vector */
3558 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3561 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3562 q_vector = adapter->q_vector[q_idx];
3563 napi_disable(&q_vector->napi);
3567 #ifdef CONFIG_IXGBE_DCB
3569 * ixgbe_configure_dcb - Configure DCB hardware
3570 * @adapter: ixgbe adapter struct
3572 * This is called by the driver on open to configure the DCB hardware.
3573 * This is also called by the gennetlink interface when reconfiguring
3576 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3578 struct ixgbe_hw *hw = &adapter->hw;
3579 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3581 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3582 if (hw->mac.type == ixgbe_mac_82598EB)
3583 netif_set_gso_max_size(adapter->netdev, 65536);
3587 if (hw->mac.type == ixgbe_mac_82598EB)
3588 netif_set_gso_max_size(adapter->netdev, 32768);
3591 /* Enable VLAN tag insert/strip */
3592 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3594 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3596 /* reconfigure the hardware */
3597 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3599 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3600 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3602 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3604 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3606 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3608 struct net_device *dev = adapter->netdev;
3610 if (adapter->ixgbe_ieee_ets)
3611 dev->dcbnl_ops->ieee_setets(dev,
3612 adapter->ixgbe_ieee_ets);
3613 if (adapter->ixgbe_ieee_pfc)
3614 dev->dcbnl_ops->ieee_setpfc(dev,
3615 adapter->ixgbe_ieee_pfc);
3618 /* Enable RSS Hash per TC */
3619 if (hw->mac.type != ixgbe_mac_82598EB) {
3623 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3625 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3630 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3632 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3638 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3641 int num_tc = netdev_get_num_tc(adapter->netdev);
3642 struct ixgbe_hw *hw = &adapter->hw;
3644 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3645 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3646 hdrm = 64 << adapter->fdir_pballoc;
3648 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3651 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3653 struct ixgbe_hw *hw = &adapter->hw;
3654 struct hlist_node *node, *node2;
3655 struct ixgbe_fdir_filter *filter;
3657 spin_lock(&adapter->fdir_perfect_lock);
3659 if (!hlist_empty(&adapter->fdir_filter_list))
3660 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3662 hlist_for_each_entry_safe(filter, node, node2,
3663 &adapter->fdir_filter_list, fdir_node) {
3664 ixgbe_fdir_write_perfect_filter_82599(hw,
3667 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3668 IXGBE_FDIR_DROP_QUEUE :
3669 adapter->rx_ring[filter->action]->reg_idx);
3672 spin_unlock(&adapter->fdir_perfect_lock);
3675 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3677 struct net_device *netdev = adapter->netdev;
3678 struct ixgbe_hw *hw = &adapter->hw;
3681 ixgbe_configure_pb(adapter);
3682 #ifdef CONFIG_IXGBE_DCB
3683 ixgbe_configure_dcb(adapter);
3686 ixgbe_set_rx_mode(netdev);
3687 ixgbe_restore_vlan(adapter);
3690 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3691 ixgbe_configure_fcoe(adapter);
3693 #endif /* IXGBE_FCOE */
3694 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3695 for (i = 0; i < adapter->num_tx_queues; i++)
3696 adapter->tx_ring[i]->atr_sample_rate =
3697 adapter->atr_sample_rate;
3698 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3699 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3700 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3701 adapter->fdir_pballoc);
3702 ixgbe_fdir_filter_restore(adapter);
3704 ixgbe_configure_virtualization(adapter);
3706 ixgbe_configure_tx(adapter);
3707 ixgbe_configure_rx(adapter);
3710 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3712 switch (hw->phy.type) {
3713 case ixgbe_phy_sfp_avago:
3714 case ixgbe_phy_sfp_ftl:
3715 case ixgbe_phy_sfp_intel:
3716 case ixgbe_phy_sfp_unknown:
3717 case ixgbe_phy_sfp_passive_tyco:
3718 case ixgbe_phy_sfp_passive_unknown:
3719 case ixgbe_phy_sfp_active_unknown:
3720 case ixgbe_phy_sfp_ftl_active:
3728 * ixgbe_sfp_link_config - set up SFP+ link
3729 * @adapter: pointer to private adapter struct
3731 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3734 * We are assuming the worst case scenerio here, and that
3735 * is that an SFP was inserted/removed after the reset
3736 * but before SFP detection was enabled. As such the best
3737 * solution is to just start searching as soon as we start
3739 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3740 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3742 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3746 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3747 * @hw: pointer to private hardware struct
3749 * Returns 0 on success, negative on failure
3751 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3754 bool negotiation, link_up = false;
3755 u32 ret = IXGBE_ERR_LINK_SETUP;
3757 if (hw->mac.ops.check_link)
3758 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3763 autoneg = hw->phy.autoneg_advertised;
3764 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3765 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3770 if (hw->mac.ops.setup_link)
3771 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3776 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3778 struct ixgbe_hw *hw = &adapter->hw;
3781 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3782 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3784 gpie |= IXGBE_GPIE_EIAME;
3786 * use EIAM to auto-mask when MSI-X interrupt is asserted
3787 * this saves a register write for every interrupt
3789 switch (hw->mac.type) {
3790 case ixgbe_mac_82598EB:
3791 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3793 case ixgbe_mac_82599EB:
3794 case ixgbe_mac_X540:
3796 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3797 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3801 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3802 * specifically only auto mask tx and rx interrupts */
3803 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3806 /* XXX: to interrupt immediately for EICS writes, enable this */
3807 /* gpie |= IXGBE_GPIE_EIMEN; */
3809 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3810 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3811 gpie |= IXGBE_GPIE_VTMODE_64;
3814 /* Enable fan failure interrupt */
3815 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3816 gpie |= IXGBE_SDP1_GPIEN;
3818 if (hw->mac.type == ixgbe_mac_82599EB) {
3819 gpie |= IXGBE_SDP1_GPIEN;
3820 gpie |= IXGBE_SDP2_GPIEN;
3823 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3826 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3828 struct ixgbe_hw *hw = &adapter->hw;
3832 ixgbe_get_hw_control(adapter);
3833 ixgbe_setup_gpie(adapter);
3835 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3836 ixgbe_configure_msix(adapter);
3838 ixgbe_configure_msi_and_legacy(adapter);
3840 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3841 if (hw->mac.ops.enable_tx_laser &&
3842 ((hw->phy.multispeed_fiber) ||
3843 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3844 (hw->mac.type == ixgbe_mac_82599EB))))
3845 hw->mac.ops.enable_tx_laser(hw);
3847 clear_bit(__IXGBE_DOWN, &adapter->state);
3848 ixgbe_napi_enable_all(adapter);
3850 if (ixgbe_is_sfp(hw)) {
3851 ixgbe_sfp_link_config(adapter);
3853 err = ixgbe_non_sfp_link_config(hw);
3855 e_err(probe, "link_config FAILED %d\n", err);
3858 /* clear any pending interrupts, may auto mask */
3859 IXGBE_READ_REG(hw, IXGBE_EICR);
3860 ixgbe_irq_enable(adapter, true, true);
3863 * If this adapter has a fan, check to see if we had a failure
3864 * before we enabled the interrupt.
3866 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3867 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3868 if (esdp & IXGBE_ESDP_SDP1)
3869 e_crit(drv, "Fan has stopped, replace the adapter\n");
3872 /* enable transmits */
3873 netif_tx_start_all_queues(adapter->netdev);
3875 /* bring the link up in the watchdog, this could race with our first
3876 * link up interrupt but shouldn't be a problem */
3877 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3878 adapter->link_check_timeout = jiffies;
3879 mod_timer(&adapter->service_timer, jiffies);
3881 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3882 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3883 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3884 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3889 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3891 WARN_ON(in_interrupt());
3892 /* put off any impending NetWatchDogTimeout */
3893 adapter->netdev->trans_start = jiffies;
3895 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3896 usleep_range(1000, 2000);
3897 ixgbe_down(adapter);
3899 * If SR-IOV enabled then wait a bit before bringing the adapter
3900 * back up to give the VFs time to respond to the reset. The
3901 * two second wait is based upon the watchdog timer cycle in
3904 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3907 clear_bit(__IXGBE_RESETTING, &adapter->state);
3910 int ixgbe_up(struct ixgbe_adapter *adapter)
3912 /* hardware has been reset, we need to reload some things */
3913 ixgbe_configure(adapter);
3915 return ixgbe_up_complete(adapter);
3918 void ixgbe_reset(struct ixgbe_adapter *adapter)
3920 struct ixgbe_hw *hw = &adapter->hw;
3923 /* lock SFP init bit to prevent race conditions with the watchdog */
3924 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3925 usleep_range(1000, 2000);
3927 /* clear all SFP and link config related flags while holding SFP_INIT */
3928 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3929 IXGBE_FLAG2_SFP_NEEDS_RESET);
3930 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3932 err = hw->mac.ops.init_hw(hw);
3935 case IXGBE_ERR_SFP_NOT_PRESENT:
3936 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3938 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3939 e_dev_err("master disable timed out\n");
3941 case IXGBE_ERR_EEPROM_VERSION:
3942 /* We are running on a pre-production device, log a warning */
3943 e_dev_warn("This device is a pre-production adapter/LOM. "
3944 "Please be aware there may be issuesassociated with "
3945 "your hardware. If you are experiencing problems "
3946 "please contact your Intel or hardware "
3947 "representative who provided you with this "
3951 e_dev_err("Hardware Error: %d\n", err);
3954 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3956 /* reprogram the RAR[0] in case user changed it. */
3957 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3962 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3963 * @rx_ring: ring to free buffers from
3965 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3967 struct device *dev = rx_ring->dev;
3971 /* ring already cleared, nothing to do */
3972 if (!rx_ring->rx_buffer_info)
3975 /* Free all the Rx ring sk_buffs */
3976 for (i = 0; i < rx_ring->count; i++) {
3977 struct ixgbe_rx_buffer *rx_buffer_info;
3979 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3980 if (rx_buffer_info->dma) {
3981 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3982 rx_ring->rx_buf_len,
3984 rx_buffer_info->dma = 0;
3986 if (rx_buffer_info->skb) {
3987 struct sk_buff *skb = rx_buffer_info->skb;
3988 rx_buffer_info->skb = NULL;
3990 struct sk_buff *this = skb;
3991 if (IXGBE_RSC_CB(this)->delay_unmap) {
3992 dma_unmap_single(dev,
3993 IXGBE_RSC_CB(this)->dma,
3994 rx_ring->rx_buf_len,
3996 IXGBE_RSC_CB(this)->dma = 0;
3997 IXGBE_RSC_CB(skb)->delay_unmap = false;
4000 dev_kfree_skb(this);
4003 if (!rx_buffer_info->page)
4005 if (rx_buffer_info->page_dma) {
4006 dma_unmap_page(dev, rx_buffer_info->page_dma,
4007 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4008 rx_buffer_info->page_dma = 0;
4010 put_page(rx_buffer_info->page);
4011 rx_buffer_info->page = NULL;
4012 rx_buffer_info->page_offset = 0;
4015 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4016 memset(rx_ring->rx_buffer_info, 0, size);
4018 /* Zero out the descriptor ring */
4019 memset(rx_ring->desc, 0, rx_ring->size);
4021 rx_ring->next_to_clean = 0;
4022 rx_ring->next_to_use = 0;
4026 * ixgbe_clean_tx_ring - Free Tx Buffers
4027 * @tx_ring: ring to be cleaned
4029 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4031 struct ixgbe_tx_buffer *tx_buffer_info;
4035 /* ring already cleared, nothing to do */
4036 if (!tx_ring->tx_buffer_info)
4039 /* Free all the Tx ring sk_buffs */
4040 for (i = 0; i < tx_ring->count; i++) {
4041 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4042 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4045 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4046 memset(tx_ring->tx_buffer_info, 0, size);
4048 /* Zero out the descriptor ring */
4049 memset(tx_ring->desc, 0, tx_ring->size);
4051 tx_ring->next_to_use = 0;
4052 tx_ring->next_to_clean = 0;
4056 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4057 * @adapter: board private structure
4059 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4063 for (i = 0; i < adapter->num_rx_queues; i++)
4064 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4068 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4069 * @adapter: board private structure
4071 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4075 for (i = 0; i < adapter->num_tx_queues; i++)
4076 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4079 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4081 struct hlist_node *node, *node2;
4082 struct ixgbe_fdir_filter *filter;
4084 spin_lock(&adapter->fdir_perfect_lock);
4086 hlist_for_each_entry_safe(filter, node, node2,
4087 &adapter->fdir_filter_list, fdir_node) {
4088 hlist_del(&filter->fdir_node);
4091 adapter->fdir_filter_count = 0;
4093 spin_unlock(&adapter->fdir_perfect_lock);
4096 void ixgbe_down(struct ixgbe_adapter *adapter)
4098 struct net_device *netdev = adapter->netdev;
4099 struct ixgbe_hw *hw = &adapter->hw;
4102 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4104 /* signal that we are down to the interrupt handler */
4105 set_bit(__IXGBE_DOWN, &adapter->state);
4107 /* disable receives */
4108 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4109 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4111 /* disable all enabled rx queues */
4112 for (i = 0; i < adapter->num_rx_queues; i++)
4113 /* this call also flushes the previous write */
4114 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4116 usleep_range(10000, 20000);
4118 netif_tx_stop_all_queues(netdev);
4120 /* call carrier off first to avoid false dev_watchdog timeouts */
4121 netif_carrier_off(netdev);
4122 netif_tx_disable(netdev);
4124 ixgbe_irq_disable(adapter);
4126 ixgbe_napi_disable_all(adapter);
4128 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4129 IXGBE_FLAG2_RESET_REQUESTED);
4130 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4132 del_timer_sync(&adapter->service_timer);
4134 /* disable receive for all VFs and wait one second */
4135 if (adapter->num_vfs) {
4136 /* ping all the active vfs to let them know we are going down */
4137 ixgbe_ping_all_vfs(adapter);
4139 /* Disable all VFTE/VFRE TX/RX */
4140 ixgbe_disable_tx_rx(adapter);
4142 /* Mark all the VFs as inactive */
4143 for (i = 0 ; i < adapter->num_vfs; i++)
4144 adapter->vfinfo[i].clear_to_send = 0;
4147 /* Cleanup the affinity_hint CPU mask memory and callback */
4148 for (i = 0; i < num_q_vectors; i++) {
4149 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4150 /* clear the affinity_mask in the IRQ descriptor */
4151 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4152 /* release the CPU mask memory */
4153 free_cpumask_var(q_vector->affinity_mask);
4156 /* disable transmits in the hardware now that interrupts are off */
4157 for (i = 0; i < adapter->num_tx_queues; i++) {
4158 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4159 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4162 /* Disable the Tx DMA engine on 82599 and X540 */
4163 switch (hw->mac.type) {
4164 case ixgbe_mac_82599EB:
4165 case ixgbe_mac_X540:
4166 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4167 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4168 ~IXGBE_DMATXCTL_TE));
4174 if (!pci_channel_offline(adapter->pdev))
4175 ixgbe_reset(adapter);
4177 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4178 if (hw->mac.ops.disable_tx_laser &&
4179 ((hw->phy.multispeed_fiber) ||
4180 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4181 (hw->mac.type == ixgbe_mac_82599EB))))
4182 hw->mac.ops.disable_tx_laser(hw);
4184 ixgbe_clean_all_tx_rings(adapter);
4185 ixgbe_clean_all_rx_rings(adapter);
4187 #ifdef CONFIG_IXGBE_DCA
4188 /* since we reset the hardware DCA settings were cleared */
4189 ixgbe_setup_dca(adapter);
4194 * ixgbe_poll - NAPI Rx polling callback
4195 * @napi: structure for representing this polling device
4196 * @budget: how many packets driver is allowed to clean
4198 * This function is used for legacy and MSI, NAPI mode
4200 static int ixgbe_poll(struct napi_struct *napi, int budget)
4202 struct ixgbe_q_vector *q_vector =
4203 container_of(napi, struct ixgbe_q_vector, napi);
4204 struct ixgbe_adapter *adapter = q_vector->adapter;
4205 int tx_clean_complete, work_done = 0;
4207 #ifdef CONFIG_IXGBE_DCA
4208 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4209 ixgbe_update_dca(q_vector);
4212 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4213 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4215 if (!tx_clean_complete)
4218 /* If budget not fully consumed, exit the polling mode */
4219 if (work_done < budget) {
4220 napi_complete(napi);
4221 if (adapter->rx_itr_setting & 1)
4222 ixgbe_set_itr(q_vector);
4223 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4224 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4230 * ixgbe_tx_timeout - Respond to a Tx Hang
4231 * @netdev: network interface device structure
4233 static void ixgbe_tx_timeout(struct net_device *netdev)
4235 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4237 /* Do the reset outside of interrupt context */
4238 ixgbe_tx_timeout_reset(adapter);
4242 * ixgbe_set_rss_queues: Allocate queues for RSS
4243 * @adapter: board private structure to initialize
4245 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4246 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4249 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4252 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4254 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4256 adapter->num_rx_queues = f->indices;
4257 adapter->num_tx_queues = f->indices;
4267 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4268 * @adapter: board private structure to initialize
4270 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4271 * to the original CPU that initiated the Tx session. This runs in addition
4272 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4273 * Rx load across CPUs using RSS.
4276 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4279 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4281 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4284 /* Flow Director must have RSS enabled */
4285 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4286 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4287 adapter->num_tx_queues = f_fdir->indices;
4288 adapter->num_rx_queues = f_fdir->indices;
4291 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4298 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4299 * @adapter: board private structure to initialize
4301 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4302 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4303 * rx queues out of the max number of rx queues, instead, it is used as the
4304 * index of the first rx queue used by FCoE.
4307 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4309 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4311 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4314 f->indices = min((int)num_online_cpus(), f->indices);
4316 adapter->num_rx_queues = 1;
4317 adapter->num_tx_queues = 1;
4319 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4320 e_info(probe, "FCoE enabled with RSS\n");
4321 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4322 ixgbe_set_fdir_queues(adapter);
4324 ixgbe_set_rss_queues(adapter);
4327 /* adding FCoE rx rings to the end */
4328 f->mask = adapter->num_rx_queues;
4329 adapter->num_rx_queues += f->indices;
4330 adapter->num_tx_queues += f->indices;
4334 #endif /* IXGBE_FCOE */
4336 /* Artificial max queue cap per traffic class in DCB mode */
4337 #define DCB_QUEUE_CAP 8
4339 #ifdef CONFIG_IXGBE_DCB
4340 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4342 int per_tc_q, q, i, offset = 0;
4343 struct net_device *dev = adapter->netdev;
4344 int tcs = netdev_get_num_tc(dev);
4349 /* Map queue offset and counts onto allocated tx queues */
4350 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4351 q = min((int)num_online_cpus(), per_tc_q);
4353 for (i = 0; i < tcs; i++) {
4354 netdev_set_prio_tc_map(dev, i, i);
4355 netdev_set_tc_queue(dev, i, q, offset);
4359 adapter->num_tx_queues = q * tcs;
4360 adapter->num_rx_queues = q * tcs;
4363 /* FCoE enabled queues require special configuration indexed
4364 * by feature specific indices and mask. Here we map FCoE
4365 * indices onto the DCB queue pairs allowing FCoE to own
4366 * configuration later.
4368 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4370 struct ixgbe_ring_feature *f =
4371 &adapter->ring_feature[RING_F_FCOE];
4373 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4374 f->indices = dev->tc_to_txq[tc].count;
4375 f->mask = dev->tc_to_txq[tc].offset;
4384 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4385 * @adapter: board private structure to initialize
4387 * IOV doesn't actually use anything, so just NAK the
4388 * request for now and let the other queue routines
4389 * figure out what to do.
4391 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4397 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4398 * @adapter: board private structure to initialize
4400 * This is the top level queue allocation routine. The order here is very
4401 * important, starting with the "most" number of features turned on at once,
4402 * and ending with the smallest set of features. This way large combinations
4403 * can be allocated if they're turned on, and smaller combinations are the
4404 * fallthrough conditions.
4407 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4409 /* Start with base case */
4410 adapter->num_rx_queues = 1;
4411 adapter->num_tx_queues = 1;
4412 adapter->num_rx_pools = adapter->num_rx_queues;
4413 adapter->num_rx_queues_per_pool = 1;
4415 if (ixgbe_set_sriov_queues(adapter))
4418 #ifdef CONFIG_IXGBE_DCB
4419 if (ixgbe_set_dcb_queues(adapter))
4424 if (ixgbe_set_fcoe_queues(adapter))
4427 #endif /* IXGBE_FCOE */
4428 if (ixgbe_set_fdir_queues(adapter))
4431 if (ixgbe_set_rss_queues(adapter))
4434 /* fallback to base case */
4435 adapter->num_rx_queues = 1;
4436 adapter->num_tx_queues = 1;
4439 /* Notify the stack of the (possibly) reduced queue counts. */
4440 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4441 return netif_set_real_num_rx_queues(adapter->netdev,
4442 adapter->num_rx_queues);
4445 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4448 int err, vector_threshold;
4450 /* We'll want at least 3 (vector_threshold):
4453 * 3) Other (Link Status Change, etc.)
4454 * 4) TCP Timer (optional)
4456 vector_threshold = MIN_MSIX_COUNT;
4458 /* The more we get, the more we will assign to Tx/Rx Cleanup
4459 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4460 * Right now, we simply care about how many we'll get; we'll
4461 * set them up later while requesting irq's.
4463 while (vectors >= vector_threshold) {
4464 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4466 if (!err) /* Success in acquiring all requested vectors. */
4469 vectors = 0; /* Nasty failure, quit now */
4470 else /* err == number of vectors we should try again with */
4474 if (vectors < vector_threshold) {
4475 /* Can't allocate enough MSI-X interrupts? Oh well.
4476 * This just means we'll go with either a single MSI
4477 * vector or fall back to legacy interrupts.
4479 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4480 "Unable to allocate MSI-X interrupts\n");
4481 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4482 kfree(adapter->msix_entries);
4483 adapter->msix_entries = NULL;
4485 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4487 * Adjust for only the vectors we'll use, which is minimum
4488 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4489 * vectors we were allocated.
4491 adapter->num_msix_vectors = min(vectors,
4492 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4497 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4498 * @adapter: board private structure to initialize
4500 * Cache the descriptor ring offsets for RSS to the assigned rings.
4503 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4507 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4510 for (i = 0; i < adapter->num_rx_queues; i++)
4511 adapter->rx_ring[i]->reg_idx = i;
4512 for (i = 0; i < adapter->num_tx_queues; i++)
4513 adapter->tx_ring[i]->reg_idx = i;
4518 #ifdef CONFIG_IXGBE_DCB
4520 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4521 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4522 unsigned int *tx, unsigned int *rx)
4524 struct net_device *dev = adapter->netdev;
4525 struct ixgbe_hw *hw = &adapter->hw;
4526 u8 num_tcs = netdev_get_num_tc(dev);
4531 switch (hw->mac.type) {
4532 case ixgbe_mac_82598EB:
4536 case ixgbe_mac_82599EB:
4537 case ixgbe_mac_X540:
4542 } else if (tc < 5) {
4543 *tx = ((tc + 2) << 4);
4545 } else if (tc < num_tcs) {
4546 *tx = ((tc + 8) << 3);
4549 } else if (num_tcs == 4) {
4575 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4576 * @adapter: board private structure to initialize
4578 * Cache the descriptor ring offsets for DCB to the assigned rings.
4581 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4583 struct net_device *dev = adapter->netdev;
4585 u8 num_tcs = netdev_get_num_tc(dev);
4590 for (i = 0, k = 0; i < num_tcs; i++) {
4591 unsigned int tx_s, rx_s;
4592 u16 count = dev->tc_to_txq[i].count;
4594 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4595 for (j = 0; j < count; j++, k++) {
4596 adapter->tx_ring[k]->reg_idx = tx_s + j;
4597 adapter->rx_ring[k]->reg_idx = rx_s + j;
4598 adapter->tx_ring[k]->dcb_tc = i;
4599 adapter->rx_ring[k]->dcb_tc = i;
4608 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4609 * @adapter: board private structure to initialize
4611 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4614 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4619 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4620 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4621 for (i = 0; i < adapter->num_rx_queues; i++)
4622 adapter->rx_ring[i]->reg_idx = i;
4623 for (i = 0; i < adapter->num_tx_queues; i++)
4624 adapter->tx_ring[i]->reg_idx = i;
4633 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4634 * @adapter: board private structure to initialize
4636 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4639 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4641 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4643 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4645 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4648 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4649 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4650 ixgbe_cache_ring_fdir(adapter);
4652 ixgbe_cache_ring_rss(adapter);
4654 fcoe_rx_i = f->mask;
4655 fcoe_tx_i = f->mask;
4657 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4658 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4659 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4664 #endif /* IXGBE_FCOE */
4666 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4667 * @adapter: board private structure to initialize
4669 * SR-IOV doesn't use any descriptor rings but changes the default if
4670 * no other mapping is used.
4673 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4675 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4676 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4677 if (adapter->num_vfs)
4684 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4685 * @adapter: board private structure to initialize
4687 * Once we know the feature-set enabled for the device, we'll cache
4688 * the register offset the descriptor ring is assigned to.
4690 * Note, the order the various feature calls is important. It must start with
4691 * the "most" features enabled at the same time, then trickle down to the
4692 * least amount of features turned on at once.
4694 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4696 /* start with default case */
4697 adapter->rx_ring[0]->reg_idx = 0;
4698 adapter->tx_ring[0]->reg_idx = 0;
4700 if (ixgbe_cache_ring_sriov(adapter))
4703 #ifdef CONFIG_IXGBE_DCB
4704 if (ixgbe_cache_ring_dcb(adapter))
4709 if (ixgbe_cache_ring_fcoe(adapter))
4711 #endif /* IXGBE_FCOE */
4713 if (ixgbe_cache_ring_fdir(adapter))
4716 if (ixgbe_cache_ring_rss(adapter))
4721 * ixgbe_alloc_queues - Allocate memory for all rings
4722 * @adapter: board private structure to initialize
4724 * We allocate one ring per queue at run-time since we don't know the
4725 * number of queues at compile-time. The polling_netdev array is
4726 * intended for Multiqueue, but should work fine with a single queue.
4728 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4730 int rx = 0, tx = 0, nid = adapter->node;
4732 if (nid < 0 || !node_online(nid))
4733 nid = first_online_node;
4735 for (; tx < adapter->num_tx_queues; tx++) {
4736 struct ixgbe_ring *ring;
4738 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4740 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4742 goto err_allocation;
4743 ring->count = adapter->tx_ring_count;
4744 ring->queue_index = tx;
4745 ring->numa_node = nid;
4746 ring->dev = &adapter->pdev->dev;
4747 ring->netdev = adapter->netdev;
4749 adapter->tx_ring[tx] = ring;
4752 for (; rx < adapter->num_rx_queues; rx++) {
4753 struct ixgbe_ring *ring;
4755 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4757 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4759 goto err_allocation;
4760 ring->count = adapter->rx_ring_count;
4761 ring->queue_index = rx;
4762 ring->numa_node = nid;
4763 ring->dev = &adapter->pdev->dev;
4764 ring->netdev = adapter->netdev;
4766 adapter->rx_ring[rx] = ring;
4769 ixgbe_cache_ring_register(adapter);
4775 kfree(adapter->tx_ring[--tx]);
4778 kfree(adapter->rx_ring[--rx]);
4783 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4784 * @adapter: board private structure to initialize
4786 * Attempt to configure the interrupts using the best available
4787 * capabilities of the hardware and the kernel.
4789 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4791 struct ixgbe_hw *hw = &adapter->hw;
4793 int vector, v_budget;
4796 * It's easy to be greedy for MSI-X vectors, but it really
4797 * doesn't do us much good if we have a lot more vectors
4798 * than CPU's. So let's be conservative and only ask for
4799 * (roughly) the same number of vectors as there are CPU's.
4801 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4802 (int)num_online_cpus()) + NON_Q_VECTORS;
4805 * At the same time, hardware can only support a maximum of
4806 * hw.mac->max_msix_vectors vectors. With features
4807 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4808 * descriptor queues supported by our device. Thus, we cap it off in
4809 * those rare cases where the cpu count also exceeds our vector limit.
4811 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4813 /* A failure in MSI-X entry allocation isn't fatal, but it does
4814 * mean we disable MSI-X capabilities of the adapter. */
4815 adapter->msix_entries = kcalloc(v_budget,
4816 sizeof(struct msix_entry), GFP_KERNEL);
4817 if (adapter->msix_entries) {
4818 for (vector = 0; vector < v_budget; vector++)
4819 adapter->msix_entries[vector].entry = vector;
4821 ixgbe_acquire_msix_vectors(adapter, v_budget);
4823 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4827 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4828 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4829 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4831 "ATR is not supported while multiple "
4832 "queues are disabled. Disabling Flow Director\n");
4834 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4835 adapter->atr_sample_rate = 0;
4836 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4837 ixgbe_disable_sriov(adapter);
4839 err = ixgbe_set_num_queues(adapter);
4843 err = pci_enable_msi(adapter->pdev);
4845 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4847 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4848 "Unable to allocate MSI interrupt, "
4849 "falling back to legacy. Error: %d\n", err);
4859 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4860 * @adapter: board private structure to initialize
4862 * We allocate one q_vector per queue interrupt. If allocation fails we
4865 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4867 int q_idx, num_q_vectors;
4868 struct ixgbe_q_vector *q_vector;
4869 int (*poll)(struct napi_struct *, int);
4871 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4872 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4873 poll = &ixgbe_clean_rxtx_many;
4879 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4880 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4881 GFP_KERNEL, adapter->node);
4883 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4887 q_vector->adapter = adapter;
4888 if (q_vector->tx.count && !q_vector->rx.count)
4889 q_vector->eitr = adapter->tx_eitr_param;
4891 q_vector->eitr = adapter->rx_eitr_param;
4892 q_vector->v_idx = q_idx;
4893 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4894 adapter->q_vector[q_idx] = q_vector;
4902 q_vector = adapter->q_vector[q_idx];
4903 netif_napi_del(&q_vector->napi);
4905 adapter->q_vector[q_idx] = NULL;
4911 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4912 * @adapter: board private structure to initialize
4914 * This function frees the memory allocated to the q_vectors. In addition if
4915 * NAPI is enabled it will delete any references to the NAPI struct prior
4916 * to freeing the q_vector.
4918 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4920 int q_idx, num_q_vectors;
4922 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4923 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4927 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4928 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4929 adapter->q_vector[q_idx] = NULL;
4930 netif_napi_del(&q_vector->napi);
4935 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4937 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4938 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4939 pci_disable_msix(adapter->pdev);
4940 kfree(adapter->msix_entries);
4941 adapter->msix_entries = NULL;
4942 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4943 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4944 pci_disable_msi(adapter->pdev);
4949 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4950 * @adapter: board private structure to initialize
4952 * We determine which interrupt scheme to use based on...
4953 * - Kernel support (MSI, MSI-X)
4954 * - which can be user-defined (via MODULE_PARAM)
4955 * - Hardware queue count (num_*_queues)
4956 * - defined by miscellaneous hardware support/features (RSS, etc.)
4958 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4962 /* Number of supported queues */
4963 err = ixgbe_set_num_queues(adapter);
4967 err = ixgbe_set_interrupt_capability(adapter);
4969 e_dev_err("Unable to setup interrupt capabilities\n");
4970 goto err_set_interrupt;
4973 err = ixgbe_alloc_q_vectors(adapter);
4975 e_dev_err("Unable to allocate memory for queue vectors\n");
4976 goto err_alloc_q_vectors;
4979 err = ixgbe_alloc_queues(adapter);
4981 e_dev_err("Unable to allocate memory for queues\n");
4982 goto err_alloc_queues;
4985 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4986 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4987 adapter->num_rx_queues, adapter->num_tx_queues);
4989 set_bit(__IXGBE_DOWN, &adapter->state);
4994 ixgbe_free_q_vectors(adapter);
4995 err_alloc_q_vectors:
4996 ixgbe_reset_interrupt_capability(adapter);
5002 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5003 * @adapter: board private structure to clear interrupt scheme on
5005 * We go through and clear interrupt specific resources and reset the structure
5006 * to pre-load conditions
5008 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5012 for (i = 0; i < adapter->num_tx_queues; i++) {
5013 kfree(adapter->tx_ring[i]);
5014 adapter->tx_ring[i] = NULL;
5016 for (i = 0; i < adapter->num_rx_queues; i++) {
5017 struct ixgbe_ring *ring = adapter->rx_ring[i];
5019 /* ixgbe_get_stats64() might access this ring, we must wait
5020 * a grace period before freeing it.
5022 kfree_rcu(ring, rcu);
5023 adapter->rx_ring[i] = NULL;
5026 adapter->num_tx_queues = 0;
5027 adapter->num_rx_queues = 0;
5029 ixgbe_free_q_vectors(adapter);
5030 ixgbe_reset_interrupt_capability(adapter);
5034 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5035 * @adapter: board private structure to initialize
5037 * ixgbe_sw_init initializes the Adapter private data structure.
5038 * Fields are initialized based on PCI device information and
5039 * OS network device settings (MTU size).
5041 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5043 struct ixgbe_hw *hw = &adapter->hw;
5044 struct pci_dev *pdev = adapter->pdev;
5045 struct net_device *dev = adapter->netdev;
5047 #ifdef CONFIG_IXGBE_DCB
5049 struct tc_configuration *tc;
5051 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5053 /* PCI config space info */
5055 hw->vendor_id = pdev->vendor;
5056 hw->device_id = pdev->device;
5057 hw->revision_id = pdev->revision;
5058 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5059 hw->subsystem_device_id = pdev->subsystem_device;
5061 /* Set capability flags */
5062 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5063 adapter->ring_feature[RING_F_RSS].indices = rss;
5064 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5065 switch (hw->mac.type) {
5066 case ixgbe_mac_82598EB:
5067 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5068 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5069 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5071 case ixgbe_mac_82599EB:
5072 case ixgbe_mac_X540:
5073 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5074 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5075 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5076 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5077 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5078 /* Flow Director hash filters enabled */
5079 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5080 adapter->atr_sample_rate = 20;
5081 adapter->ring_feature[RING_F_FDIR].indices =
5082 IXGBE_MAX_FDIR_INDICES;
5083 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5085 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5086 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5087 adapter->ring_feature[RING_F_FCOE].indices = 0;
5088 #ifdef CONFIG_IXGBE_DCB
5089 /* Default traffic class to use for FCoE */
5090 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5092 #endif /* IXGBE_FCOE */
5098 /* n-tuple support exists, always init our spinlock */
5099 spin_lock_init(&adapter->fdir_perfect_lock);
5101 #ifdef CONFIG_IXGBE_DCB
5102 /* Configure DCB traffic classes */
5103 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5104 tc = &adapter->dcb_cfg.tc_config[j];
5105 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5106 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5107 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5108 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5109 tc->dcb_pfc = pfc_disabled;
5111 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5112 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5113 adapter->dcb_cfg.pfc_mode_enable = false;
5114 adapter->dcb_set_bitmap = 0x00;
5115 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5116 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5121 /* default flow control settings */
5122 hw->fc.requested_mode = ixgbe_fc_full;
5123 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5125 adapter->last_lfc_mode = hw->fc.current_mode;
5127 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5128 hw->fc.low_water = FC_LOW_WATER(max_frame);
5129 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5130 hw->fc.send_xon = true;
5131 hw->fc.disable_fc_autoneg = false;
5133 /* enable itr by default in dynamic mode */
5134 adapter->rx_itr_setting = 1;
5135 adapter->rx_eitr_param = 20000;
5136 adapter->tx_itr_setting = 1;
5137 adapter->tx_eitr_param = 10000;
5139 /* set defaults for eitr in MegaBytes */
5140 adapter->eitr_low = 10;
5141 adapter->eitr_high = 20;
5143 /* set default ring sizes */
5144 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5145 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5147 /* set default work limits */
5148 adapter->tx_work_limit = adapter->tx_ring_count;
5150 /* initialize eeprom parameters */
5151 if (ixgbe_init_eeprom_params_generic(hw)) {
5152 e_dev_err("EEPROM initialization failed\n");
5156 /* enable rx csum by default */
5157 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5159 /* get assigned NUMA node */
5160 adapter->node = dev_to_node(&pdev->dev);
5162 set_bit(__IXGBE_DOWN, &adapter->state);
5168 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5169 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5171 * Return 0 on success, negative on failure
5173 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5175 struct device *dev = tx_ring->dev;
5178 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5179 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5180 if (!tx_ring->tx_buffer_info)
5181 tx_ring->tx_buffer_info = vzalloc(size);
5182 if (!tx_ring->tx_buffer_info)
5185 /* round up to nearest 4K */
5186 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5187 tx_ring->size = ALIGN(tx_ring->size, 4096);
5189 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5190 &tx_ring->dma, GFP_KERNEL);
5194 tx_ring->next_to_use = 0;
5195 tx_ring->next_to_clean = 0;
5199 vfree(tx_ring->tx_buffer_info);
5200 tx_ring->tx_buffer_info = NULL;
5201 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5206 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5207 * @adapter: board private structure
5209 * If this function returns with an error, then it's possible one or
5210 * more of the rings is populated (while the rest are not). It is the
5211 * callers duty to clean those orphaned rings.
5213 * Return 0 on success, negative on failure
5215 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5219 for (i = 0; i < adapter->num_tx_queues; i++) {
5220 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5223 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5231 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5232 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5234 * Returns 0 on success, negative on failure
5236 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5238 struct device *dev = rx_ring->dev;
5241 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5242 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5243 if (!rx_ring->rx_buffer_info)
5244 rx_ring->rx_buffer_info = vzalloc(size);
5245 if (!rx_ring->rx_buffer_info)
5248 /* Round up to nearest 4K */
5249 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5250 rx_ring->size = ALIGN(rx_ring->size, 4096);
5252 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5253 &rx_ring->dma, GFP_KERNEL);
5258 rx_ring->next_to_clean = 0;
5259 rx_ring->next_to_use = 0;
5263 vfree(rx_ring->rx_buffer_info);
5264 rx_ring->rx_buffer_info = NULL;
5265 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5270 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5271 * @adapter: board private structure
5273 * If this function returns with an error, then it's possible one or
5274 * more of the rings is populated (while the rest are not). It is the
5275 * callers duty to clean those orphaned rings.
5277 * Return 0 on success, negative on failure
5279 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5283 for (i = 0; i < adapter->num_rx_queues; i++) {
5284 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5287 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5295 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5296 * @tx_ring: Tx descriptor ring for a specific queue
5298 * Free all transmit software resources
5300 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5302 ixgbe_clean_tx_ring(tx_ring);
5304 vfree(tx_ring->tx_buffer_info);
5305 tx_ring->tx_buffer_info = NULL;
5307 /* if not set, then don't free */
5311 dma_free_coherent(tx_ring->dev, tx_ring->size,
5312 tx_ring->desc, tx_ring->dma);
5314 tx_ring->desc = NULL;
5318 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5319 * @adapter: board private structure
5321 * Free all transmit software resources
5323 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5327 for (i = 0; i < adapter->num_tx_queues; i++)
5328 if (adapter->tx_ring[i]->desc)
5329 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5333 * ixgbe_free_rx_resources - Free Rx Resources
5334 * @rx_ring: ring to clean the resources from
5336 * Free all receive software resources
5338 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5340 ixgbe_clean_rx_ring(rx_ring);
5342 vfree(rx_ring->rx_buffer_info);
5343 rx_ring->rx_buffer_info = NULL;
5345 /* if not set, then don't free */
5349 dma_free_coherent(rx_ring->dev, rx_ring->size,
5350 rx_ring->desc, rx_ring->dma);
5352 rx_ring->desc = NULL;
5356 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5357 * @adapter: board private structure
5359 * Free all receive software resources
5361 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5365 for (i = 0; i < adapter->num_rx_queues; i++)
5366 if (adapter->rx_ring[i]->desc)
5367 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5371 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5372 * @netdev: network interface device structure
5373 * @new_mtu: new value for maximum frame size
5375 * Returns 0 on success, negative on failure
5377 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5379 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5380 struct ixgbe_hw *hw = &adapter->hw;
5381 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5383 /* MTU < 68 is an error and causes problems on some kernels */
5384 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5385 hw->mac.type != ixgbe_mac_X540) {
5386 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5389 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5393 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5394 /* must set new MTU before calling down or up */
5395 netdev->mtu = new_mtu;
5397 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5398 hw->fc.low_water = FC_LOW_WATER(max_frame);
5400 if (netif_running(netdev))
5401 ixgbe_reinit_locked(adapter);
5407 * ixgbe_open - Called when a network interface is made active
5408 * @netdev: network interface device structure
5410 * Returns 0 on success, negative value on failure
5412 * The open entry point is called when a network interface is made
5413 * active by the system (IFF_UP). At this point all resources needed
5414 * for transmit and receive operations are allocated, the interrupt
5415 * handler is registered with the OS, the watchdog timer is started,
5416 * and the stack is notified that the interface is ready.
5418 static int ixgbe_open(struct net_device *netdev)
5420 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5423 /* disallow open during test */
5424 if (test_bit(__IXGBE_TESTING, &adapter->state))
5427 netif_carrier_off(netdev);
5429 /* allocate transmit descriptors */
5430 err = ixgbe_setup_all_tx_resources(adapter);
5434 /* allocate receive descriptors */
5435 err = ixgbe_setup_all_rx_resources(adapter);
5439 ixgbe_configure(adapter);
5441 err = ixgbe_request_irq(adapter);
5445 err = ixgbe_up_complete(adapter);
5449 netif_tx_start_all_queues(netdev);
5454 ixgbe_release_hw_control(adapter);
5455 ixgbe_free_irq(adapter);
5458 ixgbe_free_all_rx_resources(adapter);
5460 ixgbe_free_all_tx_resources(adapter);
5461 ixgbe_reset(adapter);
5467 * ixgbe_close - Disables a network interface
5468 * @netdev: network interface device structure
5470 * Returns 0, this is not allowed to fail
5472 * The close entry point is called when an interface is de-activated
5473 * by the OS. The hardware is still under the drivers control, but
5474 * needs to be disabled. A global MAC reset is issued to stop the
5475 * hardware, and all transmit and receive resources are freed.
5477 static int ixgbe_close(struct net_device *netdev)
5479 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5481 ixgbe_down(adapter);
5482 ixgbe_free_irq(adapter);
5484 ixgbe_fdir_filter_exit(adapter);
5486 ixgbe_free_all_tx_resources(adapter);
5487 ixgbe_free_all_rx_resources(adapter);
5489 ixgbe_release_hw_control(adapter);
5495 static int ixgbe_resume(struct pci_dev *pdev)
5497 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5498 struct net_device *netdev = adapter->netdev;
5501 pci_set_power_state(pdev, PCI_D0);
5502 pci_restore_state(pdev);
5504 * pci_restore_state clears dev->state_saved so call
5505 * pci_save_state to restore it.
5507 pci_save_state(pdev);
5509 err = pci_enable_device_mem(pdev);
5511 e_dev_err("Cannot enable PCI device from suspend\n");
5514 pci_set_master(pdev);
5516 pci_wake_from_d3(pdev, false);
5518 err = ixgbe_init_interrupt_scheme(adapter);
5520 e_dev_err("Cannot initialize interrupts for device\n");
5524 ixgbe_reset(adapter);
5526 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5528 if (netif_running(netdev)) {
5529 err = ixgbe_open(netdev);
5534 netif_device_attach(netdev);
5538 #endif /* CONFIG_PM */
5540 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5542 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5543 struct net_device *netdev = adapter->netdev;
5544 struct ixgbe_hw *hw = &adapter->hw;
5546 u32 wufc = adapter->wol;
5551 netif_device_detach(netdev);
5553 if (netif_running(netdev)) {
5554 ixgbe_down(adapter);
5555 ixgbe_free_irq(adapter);
5556 ixgbe_free_all_tx_resources(adapter);
5557 ixgbe_free_all_rx_resources(adapter);
5560 ixgbe_clear_interrupt_scheme(adapter);
5562 kfree(adapter->ixgbe_ieee_pfc);
5563 kfree(adapter->ixgbe_ieee_ets);
5567 retval = pci_save_state(pdev);
5573 ixgbe_set_rx_mode(netdev);
5575 /* turn on all-multi mode if wake on multicast is enabled */
5576 if (wufc & IXGBE_WUFC_MC) {
5577 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5578 fctrl |= IXGBE_FCTRL_MPE;
5579 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5582 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5583 ctrl |= IXGBE_CTRL_GIO_DIS;
5584 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5586 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5588 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5589 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5592 switch (hw->mac.type) {
5593 case ixgbe_mac_82598EB:
5594 pci_wake_from_d3(pdev, false);
5596 case ixgbe_mac_82599EB:
5597 case ixgbe_mac_X540:
5598 pci_wake_from_d3(pdev, !!wufc);
5604 *enable_wake = !!wufc;
5606 ixgbe_release_hw_control(adapter);
5608 pci_disable_device(pdev);
5614 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5619 retval = __ixgbe_shutdown(pdev, &wake);
5624 pci_prepare_to_sleep(pdev);
5626 pci_wake_from_d3(pdev, false);
5627 pci_set_power_state(pdev, PCI_D3hot);
5632 #endif /* CONFIG_PM */
5634 static void ixgbe_shutdown(struct pci_dev *pdev)
5638 __ixgbe_shutdown(pdev, &wake);
5640 if (system_state == SYSTEM_POWER_OFF) {
5641 pci_wake_from_d3(pdev, wake);
5642 pci_set_power_state(pdev, PCI_D3hot);
5647 * ixgbe_update_stats - Update the board statistics counters.
5648 * @adapter: board private structure
5650 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5652 struct net_device *netdev = adapter->netdev;
5653 struct ixgbe_hw *hw = &adapter->hw;
5654 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5656 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5657 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5658 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5659 u64 bytes = 0, packets = 0;
5661 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5662 test_bit(__IXGBE_RESETTING, &adapter->state))
5665 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5668 for (i = 0; i < 16; i++)
5669 adapter->hw_rx_no_dma_resources +=
5670 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5671 for (i = 0; i < adapter->num_rx_queues; i++) {
5672 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5673 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5675 adapter->rsc_total_count = rsc_count;
5676 adapter->rsc_total_flush = rsc_flush;
5679 for (i = 0; i < adapter->num_rx_queues; i++) {
5680 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5681 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5682 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5683 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5684 bytes += rx_ring->stats.bytes;
5685 packets += rx_ring->stats.packets;
5687 adapter->non_eop_descs = non_eop_descs;
5688 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5689 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5690 netdev->stats.rx_bytes = bytes;
5691 netdev->stats.rx_packets = packets;
5695 /* gather some stats to the adapter struct that are per queue */
5696 for (i = 0; i < adapter->num_tx_queues; i++) {
5697 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5698 restart_queue += tx_ring->tx_stats.restart_queue;
5699 tx_busy += tx_ring->tx_stats.tx_busy;
5700 bytes += tx_ring->stats.bytes;
5701 packets += tx_ring->stats.packets;
5703 adapter->restart_queue = restart_queue;
5704 adapter->tx_busy = tx_busy;
5705 netdev->stats.tx_bytes = bytes;
5706 netdev->stats.tx_packets = packets;
5708 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5709 for (i = 0; i < 8; i++) {
5710 /* for packet buffers not used, the register should read 0 */
5711 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5713 hwstats->mpc[i] += mpc;
5714 total_mpc += hwstats->mpc[i];
5715 if (hw->mac.type == ixgbe_mac_82598EB)
5716 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5717 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5718 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5719 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5720 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5721 switch (hw->mac.type) {
5722 case ixgbe_mac_82598EB:
5723 hwstats->pxonrxc[i] +=
5724 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5726 case ixgbe_mac_82599EB:
5727 case ixgbe_mac_X540:
5728 hwstats->pxonrxc[i] +=
5729 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5734 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5735 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5737 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5738 /* work around hardware counting issue */
5739 hwstats->gprc -= missed_rx;
5741 ixgbe_update_xoff_received(adapter);
5743 /* 82598 hardware only has a 32 bit counter in the high register */
5744 switch (hw->mac.type) {
5745 case ixgbe_mac_82598EB:
5746 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5747 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5748 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5749 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5751 case ixgbe_mac_X540:
5752 /* OS2BMC stats are X540 only*/
5753 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5754 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5755 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5756 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5757 case ixgbe_mac_82599EB:
5758 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5759 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5760 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5761 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5762 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5763 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5764 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5765 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5766 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5768 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5769 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5770 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5771 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5772 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5773 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5774 #endif /* IXGBE_FCOE */
5779 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5780 hwstats->bprc += bprc;
5781 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5782 if (hw->mac.type == ixgbe_mac_82598EB)
5783 hwstats->mprc -= bprc;
5784 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5785 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5786 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5787 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5788 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5789 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5790 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5791 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5792 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5793 hwstats->lxontxc += lxon;
5794 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5795 hwstats->lxofftxc += lxoff;
5796 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5797 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5798 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5800 * 82598 errata - tx of flow control packets is included in tx counters
5802 xon_off_tot = lxon + lxoff;
5803 hwstats->gptc -= xon_off_tot;
5804 hwstats->mptc -= xon_off_tot;
5805 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5806 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5807 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5808 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5809 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5810 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5811 hwstats->ptc64 -= xon_off_tot;
5812 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5813 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5814 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5815 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5816 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5817 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5819 /* Fill out the OS statistics structure */
5820 netdev->stats.multicast = hwstats->mprc;
5823 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5824 netdev->stats.rx_dropped = 0;
5825 netdev->stats.rx_length_errors = hwstats->rlec;
5826 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5827 netdev->stats.rx_missed_errors = total_mpc;
5831 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5832 * @adapter - pointer to the device adapter structure
5834 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5836 struct ixgbe_hw *hw = &adapter->hw;
5839 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5842 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5844 /* if interface is down do nothing */
5845 if (test_bit(__IXGBE_DOWN, &adapter->state))
5848 /* do nothing if we are not using signature filters */
5849 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5852 adapter->fdir_overflow++;
5854 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5855 for (i = 0; i < adapter->num_tx_queues; i++)
5856 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5857 &(adapter->tx_ring[i]->state));
5858 /* re-enable flow director interrupts */
5859 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5861 e_err(probe, "failed to finish FDIR re-initialization, "
5862 "ignored adding FDIR ATR filters\n");
5867 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5868 * @adapter - pointer to the device adapter structure
5870 * This function serves two purposes. First it strobes the interrupt lines
5871 * in order to make certain interrupts are occuring. Secondly it sets the
5872 * bits needed to check for TX hangs. As a result we should immediately
5873 * determine if a hang has occured.
5875 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5877 struct ixgbe_hw *hw = &adapter->hw;
5881 /* If we're down or resetting, just bail */
5882 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5883 test_bit(__IXGBE_RESETTING, &adapter->state))
5886 /* Force detection of hung controller */
5887 if (netif_carrier_ok(adapter->netdev)) {
5888 for (i = 0; i < adapter->num_tx_queues; i++)
5889 set_check_for_tx_hang(adapter->tx_ring[i]);
5892 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5894 * for legacy and MSI interrupts don't set any bits
5895 * that are enabled for EIAM, because this operation
5896 * would set *both* EIMS and EICS for any bit in EIAM
5898 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5899 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5901 /* get one bit for every active tx/rx interrupt vector */
5902 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5903 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5904 if (qv->rx.count || qv->tx.count)
5905 eics |= ((u64)1 << i);
5909 /* Cause software interrupt to ensure rings are cleaned */
5910 ixgbe_irq_rearm_queues(adapter, eics);
5915 * ixgbe_watchdog_update_link - update the link status
5916 * @adapter - pointer to the device adapter structure
5917 * @link_speed - pointer to a u32 to store the link_speed
5919 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5921 struct ixgbe_hw *hw = &adapter->hw;
5922 u32 link_speed = adapter->link_speed;
5923 bool link_up = adapter->link_up;
5926 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5929 if (hw->mac.ops.check_link) {
5930 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5932 /* always assume link is up, if no check link function */
5933 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5937 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5938 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5939 hw->mac.ops.fc_enable(hw, i);
5941 hw->mac.ops.fc_enable(hw, 0);
5946 time_after(jiffies, (adapter->link_check_timeout +
5947 IXGBE_TRY_LINK_TIMEOUT))) {
5948 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5949 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5950 IXGBE_WRITE_FLUSH(hw);
5953 adapter->link_up = link_up;
5954 adapter->link_speed = link_speed;
5958 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5959 * print link up message
5960 * @adapter - pointer to the device adapter structure
5962 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5964 struct net_device *netdev = adapter->netdev;
5965 struct ixgbe_hw *hw = &adapter->hw;
5966 u32 link_speed = adapter->link_speed;
5967 bool flow_rx, flow_tx;
5969 /* only continue if link was previously down */
5970 if (netif_carrier_ok(netdev))
5973 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5975 switch (hw->mac.type) {
5976 case ixgbe_mac_82598EB: {
5977 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5978 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5979 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5980 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5983 case ixgbe_mac_X540:
5984 case ixgbe_mac_82599EB: {
5985 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5986 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5987 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5988 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5996 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5997 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5999 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6001 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6004 ((flow_rx && flow_tx) ? "RX/TX" :
6006 (flow_tx ? "TX" : "None"))));
6008 netif_carrier_on(netdev);
6009 ixgbe_check_vf_rate_limit(adapter);
6013 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6014 * print link down message
6015 * @adapter - pointer to the adapter structure
6017 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6019 struct net_device *netdev = adapter->netdev;
6020 struct ixgbe_hw *hw = &adapter->hw;
6022 adapter->link_up = false;
6023 adapter->link_speed = 0;
6025 /* only continue if link was up previously */
6026 if (!netif_carrier_ok(netdev))
6029 /* poll for SFP+ cable when link is down */
6030 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6031 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6033 e_info(drv, "NIC Link is Down\n");
6034 netif_carrier_off(netdev);
6038 * ixgbe_watchdog_flush_tx - flush queues on link down
6039 * @adapter - pointer to the device adapter structure
6041 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6044 int some_tx_pending = 0;
6046 if (!netif_carrier_ok(adapter->netdev)) {
6047 for (i = 0; i < adapter->num_tx_queues; i++) {
6048 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6049 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6050 some_tx_pending = 1;
6055 if (some_tx_pending) {
6056 /* We've lost link, so the controller stops DMA,
6057 * but we've got queued Tx work that's never going
6058 * to get done, so reset controller to flush Tx.
6059 * (Do the reset outside of interrupt context).
6061 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6066 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6070 /* Do not perform spoof check for 82598 */
6071 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6074 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6077 * ssvpc register is cleared on read, if zero then no
6078 * spoofed packets in the last interval.
6083 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6087 * ixgbe_watchdog_subtask - check and bring link up
6088 * @adapter - pointer to the device adapter structure
6090 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6092 /* if interface is down do nothing */
6093 if (test_bit(__IXGBE_DOWN, &adapter->state))
6096 ixgbe_watchdog_update_link(adapter);
6098 if (adapter->link_up)
6099 ixgbe_watchdog_link_is_up(adapter);
6101 ixgbe_watchdog_link_is_down(adapter);
6103 ixgbe_spoof_check(adapter);
6104 ixgbe_update_stats(adapter);
6106 ixgbe_watchdog_flush_tx(adapter);
6110 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6111 * @adapter - the ixgbe adapter structure
6113 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6115 struct ixgbe_hw *hw = &adapter->hw;
6118 /* not searching for SFP so there is nothing to do here */
6119 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6120 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6123 /* someone else is in init, wait until next service event */
6124 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6127 err = hw->phy.ops.identify_sfp(hw);
6128 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6131 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6132 /* If no cable is present, then we need to reset
6133 * the next time we find a good cable. */
6134 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6141 /* exit if reset not needed */
6142 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6145 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6148 * A module may be identified correctly, but the EEPROM may not have
6149 * support for that module. setup_sfp() will fail in that case, so
6150 * we should not allow that module to load.
6152 if (hw->mac.type == ixgbe_mac_82598EB)
6153 err = hw->phy.ops.reset(hw);
6155 err = hw->mac.ops.setup_sfp(hw);
6157 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6160 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6161 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6164 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6166 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6167 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6168 e_dev_err("failed to initialize because an unsupported "
6169 "SFP+ module type was detected.\n");
6170 e_dev_err("Reload the driver after installing a "
6171 "supported module.\n");
6172 unregister_netdev(adapter->netdev);
6177 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6178 * @adapter - the ixgbe adapter structure
6180 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6182 struct ixgbe_hw *hw = &adapter->hw;
6186 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6189 /* someone else is in init, wait until next service event */
6190 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6193 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6195 autoneg = hw->phy.autoneg_advertised;
6196 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6197 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6198 hw->mac.autotry_restart = false;
6199 if (hw->mac.ops.setup_link)
6200 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6202 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6203 adapter->link_check_timeout = jiffies;
6204 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6208 * ixgbe_service_timer - Timer Call-back
6209 * @data: pointer to adapter cast into an unsigned long
6211 static void ixgbe_service_timer(unsigned long data)
6213 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6214 unsigned long next_event_offset;
6216 /* poll faster when waiting for link */
6217 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6218 next_event_offset = HZ / 10;
6220 next_event_offset = HZ * 2;
6222 /* Reset the timer */
6223 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6225 ixgbe_service_event_schedule(adapter);
6228 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6230 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6233 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6235 /* If we're already down or resetting, just bail */
6236 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6237 test_bit(__IXGBE_RESETTING, &adapter->state))
6240 ixgbe_dump(adapter);
6241 netdev_err(adapter->netdev, "Reset adapter\n");
6242 adapter->tx_timeout_count++;
6244 ixgbe_reinit_locked(adapter);
6248 * ixgbe_service_task - manages and runs subtasks
6249 * @work: pointer to work_struct containing our data
6251 static void ixgbe_service_task(struct work_struct *work)
6253 struct ixgbe_adapter *adapter = container_of(work,
6254 struct ixgbe_adapter,
6257 ixgbe_reset_subtask(adapter);
6258 ixgbe_sfp_detection_subtask(adapter);
6259 ixgbe_sfp_link_config_subtask(adapter);
6260 ixgbe_check_overtemp_subtask(adapter);
6261 ixgbe_watchdog_subtask(adapter);
6262 ixgbe_fdir_reinit_subtask(adapter);
6263 ixgbe_check_hang_subtask(adapter);
6265 ixgbe_service_event_complete(adapter);
6268 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6269 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6271 struct ixgbe_adv_tx_context_desc *context_desc;
6272 u16 i = tx_ring->next_to_use;
6274 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6277 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6279 /* set bits to identify this as an advanced context descriptor */
6280 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6282 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6283 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6284 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6285 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6288 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6289 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6292 u32 vlan_macip_lens, type_tucmd;
6293 u32 mss_l4len_idx, l4len;
6295 if (!skb_is_gso(skb))
6298 if (skb_header_cloned(skb)) {
6299 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6304 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6305 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6307 if (protocol == __constant_htons(ETH_P_IP)) {
6308 struct iphdr *iph = ip_hdr(skb);
6311 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6315 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6316 } else if (skb_is_gso_v6(skb)) {
6317 ipv6_hdr(skb)->payload_len = 0;
6318 tcp_hdr(skb)->check =
6319 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6320 &ipv6_hdr(skb)->daddr,
6324 l4len = tcp_hdrlen(skb);
6325 *hdr_len = skb_transport_offset(skb) + l4len;
6327 /* mss_l4len_id: use 1 as index for TSO */
6328 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6329 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6330 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6332 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6333 vlan_macip_lens = skb_network_header_len(skb);
6334 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6335 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6337 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6343 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6344 struct sk_buff *skb, u32 tx_flags,
6347 u32 vlan_macip_lens = 0;
6348 u32 mss_l4len_idx = 0;
6351 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6352 if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6357 case __constant_htons(ETH_P_IP):
6358 vlan_macip_lens |= skb_network_header_len(skb);
6359 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6360 l4_hdr = ip_hdr(skb)->protocol;
6362 case __constant_htons(ETH_P_IPV6):
6363 vlan_macip_lens |= skb_network_header_len(skb);
6364 l4_hdr = ipv6_hdr(skb)->nexthdr;
6367 if (unlikely(net_ratelimit())) {
6368 dev_warn(tx_ring->dev,
6369 "partial checksum but proto=%x!\n",
6377 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6378 mss_l4len_idx = tcp_hdrlen(skb) <<
6379 IXGBE_ADVTXD_L4LEN_SHIFT;
6382 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6383 mss_l4len_idx = sizeof(struct sctphdr) <<
6384 IXGBE_ADVTXD_L4LEN_SHIFT;
6387 mss_l4len_idx = sizeof(struct udphdr) <<
6388 IXGBE_ADVTXD_L4LEN_SHIFT;
6391 if (unlikely(net_ratelimit())) {
6392 dev_warn(tx_ring->dev,
6393 "partial checksum but l4 proto=%x!\n",
6400 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6401 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6403 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6404 type_tucmd, mss_l4len_idx);
6406 return (skb->ip_summed == CHECKSUM_PARTIAL);
6409 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6410 struct ixgbe_ring *tx_ring,
6411 struct sk_buff *skb, u32 tx_flags,
6412 unsigned int first, const u8 hdr_len)
6414 struct device *dev = tx_ring->dev;
6415 struct ixgbe_tx_buffer *tx_buffer_info;
6417 unsigned int total = skb->len;
6418 unsigned int offset = 0, size, count = 0;
6419 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6421 unsigned int bytecount = skb->len;
6425 i = tx_ring->next_to_use;
6427 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6428 /* excluding fcoe_crc_eof for FCoE */
6429 total -= sizeof(struct fcoe_crc_eof);
6431 len = min(skb_headlen(skb), total);
6433 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6434 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6436 tx_buffer_info->length = size;
6437 tx_buffer_info->mapped_as_page = false;
6438 tx_buffer_info->dma = dma_map_single(dev,
6440 size, DMA_TO_DEVICE);
6441 if (dma_mapping_error(dev, tx_buffer_info->dma))
6443 tx_buffer_info->time_stamp = jiffies;
6444 tx_buffer_info->next_to_watch = i;
6453 if (i == tx_ring->count)
6458 for (f = 0; f < nr_frags; f++) {
6459 struct skb_frag_struct *frag;
6461 frag = &skb_shinfo(skb)->frags[f];
6462 len = min((unsigned int)frag->size, total);
6463 offset = frag->page_offset;
6467 if (i == tx_ring->count)
6470 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6471 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6473 tx_buffer_info->length = size;
6474 tx_buffer_info->dma = dma_map_page(dev,
6478 tx_buffer_info->mapped_as_page = true;
6479 if (dma_mapping_error(dev, tx_buffer_info->dma))
6481 tx_buffer_info->time_stamp = jiffies;
6482 tx_buffer_info->next_to_watch = i;
6493 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6494 gso_segs = skb_shinfo(skb)->gso_segs;
6496 /* adjust for FCoE Sequence Offload */
6497 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6498 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6499 skb_shinfo(skb)->gso_size);
6500 #endif /* IXGBE_FCOE */
6501 bytecount += (gso_segs - 1) * hdr_len;
6503 /* multiply data chunks by size of headers */
6504 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6505 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6506 tx_ring->tx_buffer_info[i].skb = skb;
6507 tx_ring->tx_buffer_info[first].next_to_watch = i;
6512 e_dev_err("TX DMA map failed\n");
6514 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6515 tx_buffer_info->dma = 0;
6516 tx_buffer_info->time_stamp = 0;
6517 tx_buffer_info->next_to_watch = 0;
6521 /* clear timestamp and dma mappings for remaining portion of packet */
6524 i += tx_ring->count;
6526 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6527 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6533 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6534 int tx_flags, int count, u32 paylen, u8 hdr_len)
6536 union ixgbe_adv_tx_desc *tx_desc = NULL;
6537 struct ixgbe_tx_buffer *tx_buffer_info;
6538 u32 olinfo_status = 0, cmd_type_len = 0;
6540 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6542 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6544 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6546 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6547 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6549 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6550 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6552 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6553 IXGBE_ADVTXD_POPTS_SHIFT;
6555 /* use index 1 context for tso */
6556 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6557 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6558 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6559 IXGBE_ADVTXD_POPTS_SHIFT;
6561 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6562 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6563 IXGBE_ADVTXD_POPTS_SHIFT;
6565 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6566 olinfo_status |= IXGBE_ADVTXD_CC;
6567 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6568 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6569 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6572 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6574 i = tx_ring->next_to_use;
6576 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6577 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6578 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6579 tx_desc->read.cmd_type_len =
6580 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6581 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6583 if (i == tx_ring->count)
6587 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6590 * Force memory writes to complete before letting h/w
6591 * know there are new descriptors to fetch. (Only
6592 * applicable for weak-ordered memory model archs,
6597 tx_ring->next_to_use = i;
6598 writel(i, tx_ring->tail);
6601 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6602 u32 tx_flags, __be16 protocol)
6604 struct ixgbe_q_vector *q_vector = ring->q_vector;
6605 union ixgbe_atr_hash_dword input = { .dword = 0 };
6606 union ixgbe_atr_hash_dword common = { .dword = 0 };
6608 unsigned char *network;
6610 struct ipv6hdr *ipv6;
6615 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6619 /* do nothing if sampling is disabled */
6620 if (!ring->atr_sample_rate)
6625 /* snag network header to get L4 type and address */
6626 hdr.network = skb_network_header(skb);
6628 /* Currently only IPv4/IPv6 with TCP is supported */
6629 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6630 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6631 (protocol != __constant_htons(ETH_P_IP) ||
6632 hdr.ipv4->protocol != IPPROTO_TCP))
6637 /* skip this packet since the socket is closing */
6641 /* sample on all syn packets or once every atr sample count */
6642 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6645 /* reset sample count */
6646 ring->atr_count = 0;
6648 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6651 * src and dst are inverted, think how the receiver sees them
6653 * The input is broken into two sections, a non-compressed section
6654 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6655 * is XORed together and stored in the compressed dword.
6657 input.formatted.vlan_id = vlan_id;
6660 * since src port and flex bytes occupy the same word XOR them together
6661 * and write the value to source port portion of compressed dword
6664 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6666 common.port.src ^= th->dest ^ protocol;
6667 common.port.dst ^= th->source;
6669 if (protocol == __constant_htons(ETH_P_IP)) {
6670 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6671 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6673 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6674 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6675 hdr.ipv6->saddr.s6_addr32[1] ^
6676 hdr.ipv6->saddr.s6_addr32[2] ^
6677 hdr.ipv6->saddr.s6_addr32[3] ^
6678 hdr.ipv6->daddr.s6_addr32[0] ^
6679 hdr.ipv6->daddr.s6_addr32[1] ^
6680 hdr.ipv6->daddr.s6_addr32[2] ^
6681 hdr.ipv6->daddr.s6_addr32[3];
6684 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6685 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6686 input, common, ring->queue_index);
6689 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6691 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6692 /* Herbert's original patch had:
6693 * smp_mb__after_netif_stop_queue();
6694 * but since that doesn't exist yet, just open code it. */
6697 /* We need to check again in a case another CPU has just
6698 * made room available. */
6699 if (likely(ixgbe_desc_unused(tx_ring) < size))
6702 /* A reprieve! - use start_queue because it doesn't call schedule */
6703 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6704 ++tx_ring->tx_stats.restart_queue;
6708 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6710 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6712 return __ixgbe_maybe_stop_tx(tx_ring, size);
6715 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6717 struct ixgbe_adapter *adapter = netdev_priv(dev);
6718 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6721 __be16 protocol = vlan_get_protocol(skb);
6723 if (((protocol == htons(ETH_P_FCOE)) ||
6724 (protocol == htons(ETH_P_FIP))) &&
6725 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6726 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6727 txq += adapter->ring_feature[RING_F_FCOE].mask;
6732 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6733 while (unlikely(txq >= dev->real_num_tx_queues))
6734 txq -= dev->real_num_tx_queues;
6738 return skb_tx_hash(dev, skb);
6741 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6742 struct ixgbe_adapter *adapter,
6743 struct ixgbe_ring *tx_ring)
6747 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6751 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6756 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6757 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6758 * + 2 desc gap to keep tail from touching head,
6759 * + 1 desc for context descriptor,
6760 * otherwise try next time
6762 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6763 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6764 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6766 count += skb_shinfo(skb)->nr_frags;
6768 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6769 tx_ring->tx_stats.tx_busy++;
6770 return NETDEV_TX_BUSY;
6773 protocol = vlan_get_protocol(skb);
6775 if (vlan_tx_tag_present(skb)) {
6776 tx_flags |= vlan_tx_tag_get(skb);
6777 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6778 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6779 tx_flags |= tx_ring->dcb_tc << 13;
6781 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6782 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6783 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6784 skb->priority != TC_PRIO_CONTROL) {
6785 tx_flags |= tx_ring->dcb_tc << 13;
6786 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6787 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6791 /* for FCoE with DCB, we force the priority to what
6792 * was specified by the switch */
6793 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6794 (protocol == htons(ETH_P_FCOE)))
6795 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6798 /* record the location of the first descriptor for this packet */
6799 first = tx_ring->next_to_use;
6801 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6803 /* setup tx offload for FCoE */
6804 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6808 tx_flags |= IXGBE_TX_FLAGS_FSO;
6809 #endif /* IXGBE_FCOE */
6811 if (protocol == htons(ETH_P_IP))
6812 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6813 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6817 tx_flags |= IXGBE_TX_FLAGS_TSO;
6818 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6819 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6822 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6824 /* add the ATR filter if ATR is on */
6825 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6826 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6827 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6828 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6831 tx_ring->tx_buffer_info[first].time_stamp = 0;
6832 tx_ring->next_to_use = first;
6836 return NETDEV_TX_OK;
6839 dev_kfree_skb_any(skb);
6840 return NETDEV_TX_OK;
6843 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6845 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6846 struct ixgbe_ring *tx_ring;
6848 tx_ring = adapter->tx_ring[skb->queue_mapping];
6849 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6853 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6854 * @netdev: network interface device structure
6855 * @p: pointer to an address structure
6857 * Returns 0 on success, negative on failure
6859 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6861 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6862 struct ixgbe_hw *hw = &adapter->hw;
6863 struct sockaddr *addr = p;
6865 if (!is_valid_ether_addr(addr->sa_data))
6866 return -EADDRNOTAVAIL;
6868 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6869 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6871 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6878 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6880 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6881 struct ixgbe_hw *hw = &adapter->hw;
6885 if (prtad != hw->phy.mdio.prtad)
6887 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6893 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6894 u16 addr, u16 value)
6896 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6897 struct ixgbe_hw *hw = &adapter->hw;
6899 if (prtad != hw->phy.mdio.prtad)
6901 return hw->phy.ops.write_reg(hw, addr, devad, value);
6904 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6906 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6908 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6912 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6914 * @netdev: network interface device structure
6916 * Returns non-zero on failure
6918 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6921 struct ixgbe_adapter *adapter = netdev_priv(dev);
6922 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6924 if (is_valid_ether_addr(mac->san_addr)) {
6926 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6933 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6935 * @netdev: network interface device structure
6937 * Returns non-zero on failure
6939 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6942 struct ixgbe_adapter *adapter = netdev_priv(dev);
6943 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6945 if (is_valid_ether_addr(mac->san_addr)) {
6947 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6953 #ifdef CONFIG_NET_POLL_CONTROLLER
6955 * Polling 'interrupt' - used by things like netconsole to send skbs
6956 * without having to re-enable interrupts. It's not called while
6957 * the interrupt routine is executing.
6959 static void ixgbe_netpoll(struct net_device *netdev)
6961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6964 /* if interface is down do nothing */
6965 if (test_bit(__IXGBE_DOWN, &adapter->state))
6968 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6969 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6970 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6971 for (i = 0; i < num_q_vectors; i++) {
6972 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6973 ixgbe_msix_clean_many(0, q_vector);
6976 ixgbe_intr(adapter->pdev->irq, netdev);
6978 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6982 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6983 struct rtnl_link_stats64 *stats)
6985 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6989 for (i = 0; i < adapter->num_rx_queues; i++) {
6990 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6996 start = u64_stats_fetch_begin_bh(&ring->syncp);
6997 packets = ring->stats.packets;
6998 bytes = ring->stats.bytes;
6999 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7000 stats->rx_packets += packets;
7001 stats->rx_bytes += bytes;
7005 for (i = 0; i < adapter->num_tx_queues; i++) {
7006 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7012 start = u64_stats_fetch_begin_bh(&ring->syncp);
7013 packets = ring->stats.packets;
7014 bytes = ring->stats.bytes;
7015 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7016 stats->tx_packets += packets;
7017 stats->tx_bytes += bytes;
7021 /* following stats updated by ixgbe_watchdog_task() */
7022 stats->multicast = netdev->stats.multicast;
7023 stats->rx_errors = netdev->stats.rx_errors;
7024 stats->rx_length_errors = netdev->stats.rx_length_errors;
7025 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7026 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7030 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7031 * #adapter: pointer to ixgbe_adapter
7032 * @tc: number of traffic classes currently enabled
7034 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7035 * 802.1Q priority maps to a packet buffer that exists.
7037 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7039 struct ixgbe_hw *hw = &adapter->hw;
7043 /* 82598 have a static priority to TC mapping that can not
7044 * be changed so no validation is needed.
7046 if (hw->mac.type == ixgbe_mac_82598EB)
7049 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7052 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7053 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7055 /* If up2tc is out of bounds default to zero */
7057 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7061 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7067 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7070 * @netdev: net device to configure
7071 * @tc: number of traffic classes to enable
7073 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7075 struct ixgbe_adapter *adapter = netdev_priv(dev);
7076 struct ixgbe_hw *hw = &adapter->hw;
7078 /* If DCB is anabled do not remove traffic classes, multiple
7079 * traffic classes are required to implement DCB
7081 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7084 /* Hardware supports up to 8 traffic classes */
7085 if (tc > MAX_TRAFFIC_CLASS ||
7086 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7089 /* Hardware has to reinitialize queues and interrupts to
7090 * match packet buffer alignment. Unfortunantly, the
7091 * hardware is not flexible enough to do this dynamically.
7093 if (netif_running(dev))
7095 ixgbe_clear_interrupt_scheme(adapter);
7098 netdev_set_num_tc(dev, tc);
7100 netdev_reset_tc(dev);
7102 ixgbe_init_interrupt_scheme(adapter);
7103 ixgbe_validate_rtr(adapter, tc);
7104 if (netif_running(dev))
7110 void ixgbe_do_reset(struct net_device *netdev)
7112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7114 if (netif_running(netdev))
7115 ixgbe_reinit_locked(adapter);
7117 ixgbe_reset(adapter);
7120 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7122 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7125 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7126 data &= ~NETIF_F_HW_VLAN_RX;
7129 /* return error if RXHASH is being enabled when RSS is not supported */
7130 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7131 data &= ~NETIF_F_RXHASH;
7133 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7134 if (!(data & NETIF_F_RXCSUM))
7135 data &= ~NETIF_F_LRO;
7137 /* Turn off LRO if not RSC capable or invalid ITR settings */
7138 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7139 data &= ~NETIF_F_LRO;
7140 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7141 (adapter->rx_itr_setting != 1 &&
7142 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7143 data &= ~NETIF_F_LRO;
7144 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7150 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7152 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7153 bool need_reset = false;
7155 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7156 if (!(data & NETIF_F_RXCSUM))
7157 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7159 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7161 /* Make sure RSC matches LRO, reset if change */
7162 if (!!(data & NETIF_F_LRO) !=
7163 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7164 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7165 switch (adapter->hw.mac.type) {
7166 case ixgbe_mac_X540:
7167 case ixgbe_mac_82599EB:
7176 * Check if Flow Director n-tuple support was enabled or disabled. If
7177 * the state changed, we need to reset.
7179 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7180 /* turn off ATR, enable perfect filters and reset */
7181 if (data & NETIF_F_NTUPLE) {
7182 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7183 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7186 } else if (!(data & NETIF_F_NTUPLE)) {
7187 /* turn off Flow Director, set ATR and reset */
7188 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7189 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7190 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7191 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7196 ixgbe_do_reset(netdev);
7202 static const struct net_device_ops ixgbe_netdev_ops = {
7203 .ndo_open = ixgbe_open,
7204 .ndo_stop = ixgbe_close,
7205 .ndo_start_xmit = ixgbe_xmit_frame,
7206 .ndo_select_queue = ixgbe_select_queue,
7207 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7208 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7209 .ndo_validate_addr = eth_validate_addr,
7210 .ndo_set_mac_address = ixgbe_set_mac,
7211 .ndo_change_mtu = ixgbe_change_mtu,
7212 .ndo_tx_timeout = ixgbe_tx_timeout,
7213 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7214 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7215 .ndo_do_ioctl = ixgbe_ioctl,
7216 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7217 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7218 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7219 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7220 .ndo_get_stats64 = ixgbe_get_stats64,
7221 .ndo_setup_tc = ixgbe_setup_tc,
7222 #ifdef CONFIG_NET_POLL_CONTROLLER
7223 .ndo_poll_controller = ixgbe_netpoll,
7226 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7227 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7228 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7229 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7230 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7231 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7232 #endif /* IXGBE_FCOE */
7233 .ndo_set_features = ixgbe_set_features,
7234 .ndo_fix_features = ixgbe_fix_features,
7237 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7238 const struct ixgbe_info *ii)
7240 #ifdef CONFIG_PCI_IOV
7241 struct ixgbe_hw *hw = &adapter->hw;
7243 int num_vf_macvlans, i;
7244 struct vf_macvlans *mv_list;
7246 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7249 /* The 82599 supports up to 64 VFs per physical function
7250 * but this implementation limits allocation to 63 so that
7251 * basic networking resources are still available to the
7254 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7255 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7256 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7258 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7262 num_vf_macvlans = hw->mac.num_rar_entries -
7263 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7265 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7266 sizeof(struct vf_macvlans),
7269 /* Initialize list of VF macvlans */
7270 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7271 for (i = 0; i < num_vf_macvlans; i++) {
7273 mv_list->free = true;
7274 mv_list->rar_entry = hw->mac.num_rar_entries -
7275 (i + adapter->num_vfs + 1);
7276 list_add(&mv_list->l, &adapter->vf_mvs.l);
7281 /* If call to enable VFs succeeded then allocate memory
7282 * for per VF control structures.
7285 kcalloc(adapter->num_vfs,
7286 sizeof(struct vf_data_storage), GFP_KERNEL);
7287 if (adapter->vfinfo) {
7288 /* Now that we're sure SR-IOV is enabled
7289 * and memory allocated set up the mailbox parameters
7291 ixgbe_init_mbx_params_pf(hw);
7292 memcpy(&hw->mbx.ops, ii->mbx_ops,
7293 sizeof(hw->mbx.ops));
7295 /* Disable RSC when in SR-IOV mode */
7296 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7297 IXGBE_FLAG2_RSC_ENABLED);
7302 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7303 "SRIOV disabled\n");
7304 pci_disable_sriov(adapter->pdev);
7307 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7308 adapter->num_vfs = 0;
7309 #endif /* CONFIG_PCI_IOV */
7313 * ixgbe_probe - Device Initialization Routine
7314 * @pdev: PCI device information struct
7315 * @ent: entry in ixgbe_pci_tbl
7317 * Returns 0 on success, negative on failure
7319 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7320 * The OS initialization, configuring of the adapter private structure,
7321 * and a hardware reset occur.
7323 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7324 const struct pci_device_id *ent)
7326 struct net_device *netdev;
7327 struct ixgbe_adapter *adapter = NULL;
7328 struct ixgbe_hw *hw;
7329 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7330 static int cards_found;
7331 int i, err, pci_using_dac;
7332 u8 part_str[IXGBE_PBANUM_LENGTH];
7333 unsigned int indices = num_possible_cpus();
7339 /* Catch broken hardware that put the wrong VF device ID in
7340 * the PCIe SR-IOV capability.
7342 if (pdev->is_virtfn) {
7343 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7344 pci_name(pdev), pdev->vendor, pdev->device);
7348 err = pci_enable_device_mem(pdev);
7352 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7353 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7356 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7358 err = dma_set_coherent_mask(&pdev->dev,
7362 "No usable DMA configuration, aborting\n");
7369 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7370 IORESOURCE_MEM), ixgbe_driver_name);
7373 "pci_request_selected_regions failed 0x%x\n", err);
7377 pci_enable_pcie_error_reporting(pdev);
7379 pci_set_master(pdev);
7380 pci_save_state(pdev);
7382 #ifdef CONFIG_IXGBE_DCB
7383 indices *= MAX_TRAFFIC_CLASS;
7386 if (ii->mac == ixgbe_mac_82598EB)
7387 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7389 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7392 indices += min_t(unsigned int, num_possible_cpus(),
7393 IXGBE_MAX_FCOE_INDICES);
7395 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7398 goto err_alloc_etherdev;
7401 SET_NETDEV_DEV(netdev, &pdev->dev);
7403 adapter = netdev_priv(netdev);
7404 pci_set_drvdata(pdev, adapter);
7406 adapter->netdev = netdev;
7407 adapter->pdev = pdev;
7410 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7412 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7413 pci_resource_len(pdev, 0));
7419 for (i = 1; i <= 5; i++) {
7420 if (pci_resource_len(pdev, i) == 0)
7424 netdev->netdev_ops = &ixgbe_netdev_ops;
7425 ixgbe_set_ethtool_ops(netdev);
7426 netdev->watchdog_timeo = 5 * HZ;
7427 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7429 adapter->bd_number = cards_found;
7432 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7433 hw->mac.type = ii->mac;
7436 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7437 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7438 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7439 if (!(eec & (1 << 8)))
7440 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7443 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7444 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7445 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7446 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7447 hw->phy.mdio.mmds = 0;
7448 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7449 hw->phy.mdio.dev = netdev;
7450 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7451 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7453 ii->get_invariants(hw);
7455 /* setup the private structure */
7456 err = ixgbe_sw_init(adapter);
7460 /* Make it possible the adapter to be woken up via WOL */
7461 switch (adapter->hw.mac.type) {
7462 case ixgbe_mac_82599EB:
7463 case ixgbe_mac_X540:
7464 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7471 * If there is a fan on this device and it has failed log the
7474 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7475 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7476 if (esdp & IXGBE_ESDP_SDP1)
7477 e_crit(probe, "Fan has stopped, replace the adapter\n");
7480 /* reset_hw fills in the perm_addr as well */
7481 hw->phy.reset_if_overtemp = true;
7482 err = hw->mac.ops.reset_hw(hw);
7483 hw->phy.reset_if_overtemp = false;
7484 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7485 hw->mac.type == ixgbe_mac_82598EB) {
7487 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7488 e_dev_err("failed to load because an unsupported SFP+ "
7489 "module type was detected.\n");
7490 e_dev_err("Reload the driver after installing a supported "
7494 e_dev_err("HW Init failed: %d\n", err);
7498 ixgbe_probe_vf(adapter, ii);
7500 netdev->features = NETIF_F_SG |
7503 NETIF_F_HW_VLAN_TX |
7504 NETIF_F_HW_VLAN_RX |
7505 NETIF_F_HW_VLAN_FILTER |
7512 netdev->hw_features = netdev->features;
7514 switch (adapter->hw.mac.type) {
7515 case ixgbe_mac_82599EB:
7516 case ixgbe_mac_X540:
7517 netdev->features |= NETIF_F_SCTP_CSUM;
7518 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7525 netdev->vlan_features |= NETIF_F_TSO;
7526 netdev->vlan_features |= NETIF_F_TSO6;
7527 netdev->vlan_features |= NETIF_F_IP_CSUM;
7528 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7529 netdev->vlan_features |= NETIF_F_SG;
7531 netdev->priv_flags |= IFF_UNICAST_FLT;
7533 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7534 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7535 IXGBE_FLAG_DCB_ENABLED);
7537 #ifdef CONFIG_IXGBE_DCB
7538 netdev->dcbnl_ops = &dcbnl_ops;
7542 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7543 if (hw->mac.ops.get_device_caps) {
7544 hw->mac.ops.get_device_caps(hw, &device_caps);
7545 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7546 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7549 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7550 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7551 netdev->vlan_features |= NETIF_F_FSO;
7552 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7554 #endif /* IXGBE_FCOE */
7555 if (pci_using_dac) {
7556 netdev->features |= NETIF_F_HIGHDMA;
7557 netdev->vlan_features |= NETIF_F_HIGHDMA;
7560 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7561 netdev->hw_features |= NETIF_F_LRO;
7562 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7563 netdev->features |= NETIF_F_LRO;
7565 /* make sure the EEPROM is good */
7566 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7567 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7572 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7573 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7575 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7576 e_dev_err("invalid MAC address\n");
7581 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7582 if (hw->mac.ops.disable_tx_laser &&
7583 ((hw->phy.multispeed_fiber) ||
7584 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7585 (hw->mac.type == ixgbe_mac_82599EB))))
7586 hw->mac.ops.disable_tx_laser(hw);
7588 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7589 (unsigned long) adapter);
7591 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7592 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7594 err = ixgbe_init_interrupt_scheme(adapter);
7598 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7599 netdev->hw_features &= ~NETIF_F_RXHASH;
7600 netdev->features &= ~NETIF_F_RXHASH;
7603 switch (pdev->device) {
7604 case IXGBE_DEV_ID_82599_SFP:
7605 /* Only this subdevice supports WOL */
7606 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7607 adapter->wol = IXGBE_WUFC_MAG;
7609 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7610 /* All except this subdevice support WOL */
7611 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7612 adapter->wol = IXGBE_WUFC_MAG;
7614 case IXGBE_DEV_ID_82599_KX4:
7615 adapter->wol = IXGBE_WUFC_MAG;
7621 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7623 /* pick up the PCI bus settings for reporting later */
7624 hw->mac.ops.get_bus_info(hw);
7626 /* print bus type/speed/width info */
7627 e_dev_info("(PCI Express:%s:%s) %pM\n",
7628 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7629 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7631 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7632 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7633 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7637 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7639 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7640 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7641 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7642 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7645 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7646 hw->mac.type, hw->phy.type, part_str);
7648 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7649 e_dev_warn("PCI-Express bandwidth available for this card is "
7650 "not sufficient for optimal performance.\n");
7651 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7655 /* save off EEPROM version number */
7656 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7658 /* reset the hardware with the new settings */
7659 err = hw->mac.ops.start_hw(hw);
7661 if (err == IXGBE_ERR_EEPROM_VERSION) {
7662 /* We are running on a pre-production device, log a warning */
7663 e_dev_warn("This device is a pre-production adapter/LOM. "
7664 "Please be aware there may be issues associated "
7665 "with your hardware. If you are experiencing "
7666 "problems please contact your Intel or hardware "
7667 "representative who provided you with this "
7670 strcpy(netdev->name, "eth%d");
7671 err = register_netdev(netdev);
7675 /* carrier off reporting is important to ethtool even BEFORE open */
7676 netif_carrier_off(netdev);
7678 #ifdef CONFIG_IXGBE_DCA
7679 if (dca_add_requester(&pdev->dev) == 0) {
7680 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7681 ixgbe_setup_dca(adapter);
7684 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7685 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7686 for (i = 0; i < adapter->num_vfs; i++)
7687 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7690 /* Inform firmware of driver version */
7691 if (hw->mac.ops.set_fw_drv_ver)
7692 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7695 /* add san mac addr to netdev */
7696 ixgbe_add_sanmac_netdev(netdev);
7698 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7703 ixgbe_release_hw_control(adapter);
7704 ixgbe_clear_interrupt_scheme(adapter);
7707 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7708 ixgbe_disable_sriov(adapter);
7709 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7710 iounmap(hw->hw_addr);
7712 free_netdev(netdev);
7714 pci_release_selected_regions(pdev,
7715 pci_select_bars(pdev, IORESOURCE_MEM));
7718 pci_disable_device(pdev);
7723 * ixgbe_remove - Device Removal Routine
7724 * @pdev: PCI device information struct
7726 * ixgbe_remove is called by the PCI subsystem to alert the driver
7727 * that it should release a PCI device. The could be caused by a
7728 * Hot-Plug event, or because the driver is going to be removed from
7731 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7733 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7734 struct net_device *netdev = adapter->netdev;
7736 set_bit(__IXGBE_DOWN, &adapter->state);
7737 cancel_work_sync(&adapter->service_task);
7739 #ifdef CONFIG_IXGBE_DCA
7740 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7741 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7742 dca_remove_requester(&pdev->dev);
7743 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7748 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7749 ixgbe_cleanup_fcoe(adapter);
7751 #endif /* IXGBE_FCOE */
7753 /* remove the added san mac */
7754 ixgbe_del_sanmac_netdev(netdev);
7756 if (netdev->reg_state == NETREG_REGISTERED)
7757 unregister_netdev(netdev);
7759 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7760 ixgbe_disable_sriov(adapter);
7762 ixgbe_clear_interrupt_scheme(adapter);
7764 ixgbe_release_hw_control(adapter);
7766 iounmap(adapter->hw.hw_addr);
7767 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7770 e_dev_info("complete\n");
7772 free_netdev(netdev);
7774 pci_disable_pcie_error_reporting(pdev);
7776 pci_disable_device(pdev);
7780 * ixgbe_io_error_detected - called when PCI error is detected
7781 * @pdev: Pointer to PCI device
7782 * @state: The current pci connection state
7784 * This function is called after a PCI bus error affecting
7785 * this device has been detected.
7787 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7788 pci_channel_state_t state)
7790 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7791 struct net_device *netdev = adapter->netdev;
7793 netif_device_detach(netdev);
7795 if (state == pci_channel_io_perm_failure)
7796 return PCI_ERS_RESULT_DISCONNECT;
7798 if (netif_running(netdev))
7799 ixgbe_down(adapter);
7800 pci_disable_device(pdev);
7802 /* Request a slot reset. */
7803 return PCI_ERS_RESULT_NEED_RESET;
7807 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7808 * @pdev: Pointer to PCI device
7810 * Restart the card from scratch, as if from a cold-boot.
7812 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7814 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7815 pci_ers_result_t result;
7818 if (pci_enable_device_mem(pdev)) {
7819 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7820 result = PCI_ERS_RESULT_DISCONNECT;
7822 pci_set_master(pdev);
7823 pci_restore_state(pdev);
7824 pci_save_state(pdev);
7826 pci_wake_from_d3(pdev, false);
7828 ixgbe_reset(adapter);
7829 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7830 result = PCI_ERS_RESULT_RECOVERED;
7833 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7835 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7836 "failed 0x%0x\n", err);
7837 /* non-fatal, continue */
7844 * ixgbe_io_resume - called when traffic can start flowing again.
7845 * @pdev: Pointer to PCI device
7847 * This callback is called when the error recovery driver tells us that
7848 * its OK to resume normal operation.
7850 static void ixgbe_io_resume(struct pci_dev *pdev)
7852 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7853 struct net_device *netdev = adapter->netdev;
7855 if (netif_running(netdev)) {
7856 if (ixgbe_up(adapter)) {
7857 e_info(probe, "ixgbe_up failed after reset\n");
7862 netif_device_attach(netdev);
7865 static struct pci_error_handlers ixgbe_err_handler = {
7866 .error_detected = ixgbe_io_error_detected,
7867 .slot_reset = ixgbe_io_slot_reset,
7868 .resume = ixgbe_io_resume,
7871 static struct pci_driver ixgbe_driver = {
7872 .name = ixgbe_driver_name,
7873 .id_table = ixgbe_pci_tbl,
7874 .probe = ixgbe_probe,
7875 .remove = __devexit_p(ixgbe_remove),
7877 .suspend = ixgbe_suspend,
7878 .resume = ixgbe_resume,
7880 .shutdown = ixgbe_shutdown,
7881 .err_handler = &ixgbe_err_handler
7885 * ixgbe_init_module - Driver Registration Routine
7887 * ixgbe_init_module is the first routine called when the driver is
7888 * loaded. All it does is register with the PCI subsystem.
7890 static int __init ixgbe_init_module(void)
7893 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7894 pr_info("%s\n", ixgbe_copyright);
7896 #ifdef CONFIG_IXGBE_DCA
7897 dca_register_notify(&dca_notifier);
7900 ret = pci_register_driver(&ixgbe_driver);
7904 module_init(ixgbe_init_module);
7907 * ixgbe_exit_module - Driver Exit Cleanup Routine
7909 * ixgbe_exit_module is called just before the driver is removed
7912 static void __exit ixgbe_exit_module(void)
7914 #ifdef CONFIG_IXGBE_DCA
7915 dca_unregister_notify(&dca_notifier);
7917 pci_unregister_driver(&ixgbe_driver);
7918 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7921 #ifdef CONFIG_IXGBE_DCA
7922 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7927 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7928 __ixgbe_notify_dca);
7930 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7933 #endif /* CONFIG_IXGBE_DCA */
7935 module_exit(ixgbe_exit_module);