drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include "igb.h"
  61
  62 #define MAJ 4
  63 #define MIN 1
  64 #define BUILD 2
  65 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  66 __stringify(BUILD) "-k"
  67 char igb_driver_name[] = "igb";
  68 char igb_driver_version[] = DRV_VERSION;
  69 static const char igb_driver_string[] =
  70                                 "Intel(R) Gigabit Ethernet Network Driver";
  71 static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation.";
  72
  73 static const struct e1000_info *igb_info_tbl[] = {
  74         [board_82575] = &e1000_82575_info,
  75 };
  76
  77 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 108         /* required last entry */
 109         {0, }
 110 };
 111
 112 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 113
 114 void igb_reset(struct igb_adapter *);
 115 static int igb_setup_all_tx_resources(struct igb_adapter *);
 116 static int igb_setup_all_rx_resources(struct igb_adapter *);
 117 static void igb_free_all_tx_resources(struct igb_adapter *);
 118 static void igb_free_all_rx_resources(struct igb_adapter *);
 119 static void igb_setup_mrqc(struct igb_adapter *);
 120 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 121 static void igb_remove(struct pci_dev *pdev);
 122 static int igb_sw_init(struct igb_adapter *);
 123 static int igb_open(struct net_device *);
 124 static int igb_close(struct net_device *);
 125 static void igb_configure(struct igb_adapter *);
 126 static void igb_configure_tx(struct igb_adapter *);
 127 static void igb_configure_rx(struct igb_adapter *);
 128 static void igb_clean_all_tx_rings(struct igb_adapter *);
 129 static void igb_clean_all_rx_rings(struct igb_adapter *);
 130 static void igb_clean_tx_ring(struct igb_ring *);
 131 static void igb_clean_rx_ring(struct igb_ring *);
 132 static void igb_set_rx_mode(struct net_device *);
 133 static void igb_update_phy_info(unsigned long);
 134 static void igb_watchdog(unsigned long);
 135 static void igb_watchdog_task(struct work_struct *);
 136 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 137 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 138                                                  struct rtnl_link_stats64 *stats);
 139 static int igb_change_mtu(struct net_device *, int);
 140 static int igb_set_mac(struct net_device *, void *);
 141 static void igb_set_uta(struct igb_adapter *adapter);
 142 static irqreturn_t igb_intr(int irq, void *);
 143 static irqreturn_t igb_intr_msi(int irq, void *);
 144 static irqreturn_t igb_msix_other(int irq, void *);
 145 static irqreturn_t igb_msix_ring(int irq, void *);
 146 #ifdef CONFIG_IGB_DCA
 147 static void igb_update_dca(struct igb_q_vector *);
 148 static void igb_setup_dca(struct igb_adapter *);
 149 #endif /* CONFIG_IGB_DCA */
 150 static int igb_poll(struct napi_struct *, int);
 151 static bool igb_clean_tx_irq(struct igb_q_vector *);
 152 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 153 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 154 static void igb_tx_timeout(struct net_device *);
 155 static void igb_reset_task(struct work_struct *);
 156 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 157 static int igb_vlan_rx_add_vid(struct net_device *, u16);
 158 static int igb_vlan_rx_kill_vid(struct net_device *, u16);
 159 static void igb_restore_vlan(struct igb_adapter *);
 160 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 161 static void igb_ping_all_vfs(struct igb_adapter *);
 162 static void igb_msg_task(struct igb_adapter *);
 163 static void igb_vmm_control(struct igb_adapter *);
 164 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 165 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 166 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 167 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 168                                int vf, u16 vlan, u8 qos);
 169 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 170 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 171                                  struct ifla_vf_info *ivi);
 172 static void igb_check_vf_rate_limit(struct igb_adapter *);
 173
 174 #ifdef CONFIG_PCI_IOV
 175 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 176 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
 177 #endif
 178
 179 #ifdef CONFIG_PM
 180 #ifdef CONFIG_PM_SLEEP
 181 static int igb_suspend(struct device *);
 182 #endif
 183 static int igb_resume(struct device *);
 184 #ifdef CONFIG_PM_RUNTIME
 185 static int igb_runtime_suspend(struct device *dev);
 186 static int igb_runtime_resume(struct device *dev);
 187 static int igb_runtime_idle(struct device *dev);
 188 #endif
 189 static const struct dev_pm_ops igb_pm_ops = {
 190         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 191         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 192                         igb_runtime_idle)
 193 };
 194 #endif
 195 static void igb_shutdown(struct pci_dev *);
 196 #ifdef CONFIG_IGB_DCA
 197 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 198 static struct notifier_block dca_notifier = {
 199         .notifier_call  = igb_notify_dca,
 200         .next           = NULL,
 201         .priority       = 0
 202 };
 203 #endif
 204 #ifdef CONFIG_NET_POLL_CONTROLLER
 205 /* for netdump / net console */
 206 static void igb_netpoll(struct net_device *);
 207 #endif
 208 #ifdef CONFIG_PCI_IOV
 209 static unsigned int max_vfs = 0;
 210 module_param(max_vfs, uint, 0);
 211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 212                  "per physical function");
 213 #endif /* CONFIG_PCI_IOV */
 214
 215 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 216                      pci_channel_state_t);
 217 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 218 static void igb_io_resume(struct pci_dev *);
 219
 220 static const struct pci_error_handlers igb_err_handler = {
 221         .error_detected = igb_io_error_detected,
 222         .slot_reset = igb_io_slot_reset,
 223         .resume = igb_io_resume,
 224 };
 225
 226 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 227
 228 static struct pci_driver igb_driver = {
 229         .name     = igb_driver_name,
 230         .id_table = igb_pci_tbl,
 231         .probe    = igb_probe,
 232         .remove   = igb_remove,
 233 #ifdef CONFIG_PM
 234         .driver.pm = &igb_pm_ops,
 235 #endif
 236         .shutdown = igb_shutdown,
 237         .err_handler = &igb_err_handler
 238 };
 239
 240 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 242 MODULE_LICENSE("GPL");
 243 MODULE_VERSION(DRV_VERSION);
 244
 245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 246 static int debug = -1;
 247 module_param(debug, int, 0);
 248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 249
 250 struct igb_reg_info {
 251         u32 ofs;
 252         char *name;
 253 };
 254
 255 static const struct igb_reg_info igb_reg_info_tbl[] = {
 256
 257         /* General Registers */
 258         {E1000_CTRL, "CTRL"},
 259         {E1000_STATUS, "STATUS"},
 260         {E1000_CTRL_EXT, "CTRL_EXT"},
 261
 262         /* Interrupt Registers */
 263         {E1000_ICR, "ICR"},
 264
 265         /* RX Registers */
 266         {E1000_RCTL, "RCTL"},
 267         {E1000_RDLEN(0), "RDLEN"},
 268         {E1000_RDH(0), "RDH"},
 269         {E1000_RDT(0), "RDT"},
 270         {E1000_RXDCTL(0), "RXDCTL"},
 271         {E1000_RDBAL(0), "RDBAL"},
 272         {E1000_RDBAH(0), "RDBAH"},
 273
 274         /* TX Registers */
 275         {E1000_TCTL, "TCTL"},
 276         {E1000_TDBAL(0), "TDBAL"},
 277         {E1000_TDBAH(0), "TDBAH"},
 278         {E1000_TDLEN(0), "TDLEN"},
 279         {E1000_TDH(0), "TDH"},
 280         {E1000_TDT(0), "TDT"},
 281         {E1000_TXDCTL(0), "TXDCTL"},
 282         {E1000_TDFH, "TDFH"},
 283         {E1000_TDFT, "TDFT"},
 284         {E1000_TDFHS, "TDFHS"},
 285         {E1000_TDFPC, "TDFPC"},
 286
 287         /* List Terminator */
 288         {}
 289 };
 290
 291 /*
 292  * igb_regdump - register printout routine
 293  */
 294 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 295 {
 296         int n = 0;
 297         char rname[16];
 298         u32 regs[8];
 299
 300         switch (reginfo->ofs) {
 301         case E1000_RDLEN(0):
 302                 for (n = 0; n < 4; n++)
 303                         regs[n] = rd32(E1000_RDLEN(n));
 304                 break;
 305         case E1000_RDH(0):
 306                 for (n = 0; n < 4; n++)
 307                         regs[n] = rd32(E1000_RDH(n));
 308                 break;
 309         case E1000_RDT(0):
 310                 for (n = 0; n < 4; n++)
 311                         regs[n] = rd32(E1000_RDT(n));
 312                 break;
 313         case E1000_RXDCTL(0):
 314                 for (n = 0; n < 4; n++)
 315                         regs[n] = rd32(E1000_RXDCTL(n));
 316                 break;
 317         case E1000_RDBAL(0):
 318                 for (n = 0; n < 4; n++)
 319                         regs[n] = rd32(E1000_RDBAL(n));
 320                 break;
 321         case E1000_RDBAH(0):
 322                 for (n = 0; n < 4; n++)
 323                         regs[n] = rd32(E1000_RDBAH(n));
 324                 break;
 325         case E1000_TDBAL(0):
 326                 for (n = 0; n < 4; n++)
 327                         regs[n] = rd32(E1000_RDBAL(n));
 328                 break;
 329         case E1000_TDBAH(0):
 330                 for (n = 0; n < 4; n++)
 331                         regs[n] = rd32(E1000_TDBAH(n));
 332                 break;
 333         case E1000_TDLEN(0):
 334                 for (n = 0; n < 4; n++)
 335                         regs[n] = rd32(E1000_TDLEN(n));
 336                 break;
 337         case E1000_TDH(0):
 338                 for (n = 0; n < 4; n++)
 339                         regs[n] = rd32(E1000_TDH(n));
 340                 break;
 341         case E1000_TDT(0):
 342                 for (n = 0; n < 4; n++)
 343                         regs[n] = rd32(E1000_TDT(n));
 344                 break;
 345         case E1000_TXDCTL(0):
 346                 for (n = 0; n < 4; n++)
 347                         regs[n] = rd32(E1000_TXDCTL(n));
 348                 break;
 349         default:
 350                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 351                 return;
 352         }
 353
 354         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 355         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 356                 regs[2], regs[3]);
 357 }
 358
 359 /*
 360  * igb_dump - Print registers, tx-rings and rx-rings
 361  */
 362 static void igb_dump(struct igb_adapter *adapter)
 363 {
 364         struct net_device *netdev = adapter->netdev;
 365         struct e1000_hw *hw = &adapter->hw;
 366         struct igb_reg_info *reginfo;
 367         struct igb_ring *tx_ring;
 368         union e1000_adv_tx_desc *tx_desc;
 369         struct my_u0 { u64 a; u64 b; } *u0;
 370         struct igb_ring *rx_ring;
 371         union e1000_adv_rx_desc *rx_desc;
 372         u32 staterr;
 373         u16 i, n;
 374
 375         if (!netif_msg_hw(adapter))
 376                 return;
 377
 378         /* Print netdevice Info */
 379         if (netdev) {
 380                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 381                 pr_info("Device Name     state            trans_start      "
 382                         "last_rx\n");
 383                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 384                         netdev->state, netdev->trans_start, netdev->last_rx);
 385         }
 386
 387         /* Print Registers */
 388         dev_info(&adapter->pdev->dev, "Register Dump\n");
 389         pr_info(" Register Name   Value\n");
 390         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 391              reginfo->name; reginfo++) {
 392                 igb_regdump(hw, reginfo);
 393         }
 394
 395         /* Print TX Ring Summary */
 396         if (!netdev || !netif_running(netdev))
 397                 goto exit;
 398
 399         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 400         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 401         for (n = 0; n < adapter->num_tx_queues; n++) {
 402                 struct igb_tx_buffer *buffer_info;
 403                 tx_ring = adapter->tx_ring[n];
 404                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 405                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 406                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 407                         (u64)dma_unmap_addr(buffer_info, dma),
 408                         dma_unmap_len(buffer_info, len),
 409                         buffer_info->next_to_watch,
 410                         (u64)buffer_info->time_stamp);
 411         }
 412
 413         /* Print TX Rings */
 414         if (!netif_msg_tx_done(adapter))
 415                 goto rx_ring_summary;
 416
 417         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 418
 419         /* Transmit Descriptor Formats
 420          *
 421          * Advanced Transmit Descriptor
 422          *   +--------------------------------------------------------------+
 423          * 0 |         Buffer Address [63:0]                                |
 424          *   +--------------------------------------------------------------+
 425          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 426          *   +--------------------------------------------------------------+
 427          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 428          */
 429
 430         for (n = 0; n < adapter->num_tx_queues; n++) {
 431                 tx_ring = adapter->tx_ring[n];
 432                 pr_info("------------------------------------\n");
 433                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 434                 pr_info("------------------------------------\n");
 435                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 436                         "[bi->dma       ] leng  ntw timestamp        "
 437                         "bi->skb\n");
 438
 439                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 440                         const char *next_desc;
 441                         struct igb_tx_buffer *buffer_info;
 442                         tx_desc = IGB_TX_DESC(tx_ring, i);
 443                         buffer_info = &tx_ring->tx_buffer_info[i];
 444                         u0 = (struct my_u0 *)tx_desc;
 445                         if (i == tx_ring->next_to_use &&
 446                             i == tx_ring->next_to_clean)
 447                                 next_desc = " NTC/U";
 448                         else if (i == tx_ring->next_to_use)
 449                                 next_desc = " NTU";
 450                         else if (i == tx_ring->next_to_clean)
 451                                 next_desc = " NTC";
 452                         else
 453                                 next_desc = "";
 454
 455                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 456                                 " %04X  %p %016llX %p%s\n", i,
 457                                 le64_to_cpu(u0->a),
 458                                 le64_to_cpu(u0->b),
 459                                 (u64)dma_unmap_addr(buffer_info, dma),
 460                                 dma_unmap_len(buffer_info, len),
 461                                 buffer_info->next_to_watch,
 462                                 (u64)buffer_info->time_stamp,
 463                                 buffer_info->skb, next_desc);
 464
 465                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 466                                 print_hex_dump(KERN_INFO, "",
 467                                         DUMP_PREFIX_ADDRESS,
 468                                         16, 1, buffer_info->skb->data,
 469                                         dma_unmap_len(buffer_info, len),
 470                                         true);
 471                 }
 472         }
 473
 474         /* Print RX Rings Summary */
 475 rx_ring_summary:
 476         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 477         pr_info("Queue [NTU] [NTC]\n");
 478         for (n = 0; n < adapter->num_rx_queues; n++) {
 479                 rx_ring = adapter->rx_ring[n];
 480                 pr_info(" %5d %5X %5X\n",
 481                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 482         }
 483
 484         /* Print RX Rings */
 485         if (!netif_msg_rx_status(adapter))
 486                 goto exit;
 487
 488         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 489
 490         /* Advanced Receive Descriptor (Read) Format
 491          *    63                                           1        0
 492          *    +-----------------------------------------------------+
 493          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 494          *    +----------------------------------------------+------+
 495          *  8 |       Header Buffer Address [63:1]           |  DD  |
 496          *    +-----------------------------------------------------+
 497          *
 498          *
 499          * Advanced Receive Descriptor (Write-Back) Format
 500          *
 501          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 502          *   +------------------------------------------------------+
 503          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 504          *   | Checksum   Ident  |   |           |    | Type | Type |
 505          *   +------------------------------------------------------+
 506          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 507          *   +------------------------------------------------------+
 508          *   63       48 47    32 31            20 19               0
 509          */
 510
 511         for (n = 0; n < adapter->num_rx_queues; n++) {
 512                 rx_ring = adapter->rx_ring[n];
 513                 pr_info("------------------------------------\n");
 514                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 515                 pr_info("------------------------------------\n");
 516                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 517                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 518                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 519                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 520
 521                 for (i = 0; i < rx_ring->count; i++) {
 522                         const char *next_desc;
 523                         struct igb_rx_buffer *buffer_info;
 524                         buffer_info = &rx_ring->rx_buffer_info[i];
 525                         rx_desc = IGB_RX_DESC(rx_ring, i);
 526                         u0 = (struct my_u0 *)rx_desc;
 527                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 528
 529                         if (i == rx_ring->next_to_use)
 530                                 next_desc = " NTU";
 531                         else if (i == rx_ring->next_to_clean)
 532                                 next_desc = " NTC";
 533                         else
 534                                 next_desc = "";
 535
 536                         if (staterr & E1000_RXD_STAT_DD) {
 537                                 /* Descriptor Done */
 538                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 539                                         "RWB", i,
 540                                         le64_to_cpu(u0->a),
 541                                         le64_to_cpu(u0->b),
 542                                         next_desc);
 543                         } else {
 544                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 545                                         "R  ", i,
 546                                         le64_to_cpu(u0->a),
 547                                         le64_to_cpu(u0->b),
 548                                         (u64)buffer_info->dma,
 549                                         next_desc);
 550
 551                                 if (netif_msg_pktdata(adapter) &&
 552                                     buffer_info->dma && buffer_info->page) {
 553                                         print_hex_dump(KERN_INFO, "",
 554                                           DUMP_PREFIX_ADDRESS,
 555                                           16, 1,
 556                                           page_address(buffer_info->page) +
 557                                                       buffer_info->page_offset,
 558                                           IGB_RX_BUFSZ, true);
 559                                 }
 560                         }
 561                 }
 562         }
 563
 564 exit:
 565         return;
 566 }
 567
 568 /**
 569  * igb_get_hw_dev - return device
 570  * used by hardware layer to print debugging information
 571  **/
 572 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 573 {
 574         struct igb_adapter *adapter = hw->back;
 575         return adapter->netdev;
 576 }
 577
 578 /**
 579  * igb_init_module - Driver Registration Routine
 580  *
 581  * igb_init_module is the first routine called when the driver is
 582  * loaded. All it does is register with the PCI subsystem.
 583  **/
 584 static int __init igb_init_module(void)
 585 {
 586         int ret;
 587         pr_info("%s - version %s\n",
 588                igb_driver_string, igb_driver_version);
 589
 590         pr_info("%s\n", igb_copyright);
 591
 592 #ifdef CONFIG_IGB_DCA
 593         dca_register_notify(&dca_notifier);
 594 #endif
 595         ret = pci_register_driver(&igb_driver);
 596         return ret;
 597 }
 598
 599 module_init(igb_init_module);
 600
 601 /**
 602  * igb_exit_module - Driver Exit Cleanup Routine
 603  *
 604  * igb_exit_module is called just before the driver is removed
 605  * from memory.
 606  **/
 607 static void __exit igb_exit_module(void)
 608 {
 609 #ifdef CONFIG_IGB_DCA
 610         dca_unregister_notify(&dca_notifier);
 611 #endif
 612         pci_unregister_driver(&igb_driver);
 613 }
 614
 615 module_exit(igb_exit_module);
 616
 617 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 618 /**
 619  * igb_cache_ring_register - Descriptor ring to register mapping
 620  * @adapter: board private structure to initialize
 621  *
 622  * Once we know the feature-set enabled for the device, we'll cache
 623  * the register offset the descriptor ring is assigned to.
 624  **/
 625 static void igb_cache_ring_register(struct igb_adapter *adapter)
 626 {
 627         int i = 0, j = 0;
 628         u32 rbase_offset = adapter->vfs_allocated_count;
 629
 630         switch (adapter->hw.mac.type) {
 631         case e1000_82576:
 632                 /* The queues are allocated for virtualization such that VF 0
 633                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 634                  * In order to avoid collision we start at the first free queue
 635                  * and continue consuming queues in the same sequence
 636                  */
 637                 if (adapter->vfs_allocated_count) {
 638                         for (; i < adapter->rss_queues; i++)
 639                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 640                                                                Q_IDX_82576(i);
 641                 }
 642         case e1000_82575:
 643         case e1000_82580:
 644         case e1000_i350:
 645         case e1000_i210:
 646         case e1000_i211:
 647         default:
 648                 for (; i < adapter->num_rx_queues; i++)
 649                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 650                 for (; j < adapter->num_tx_queues; j++)
 651                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 652                 break;
 653         }
 654 }
 655
 656 /**
 657  *  igb_write_ivar - configure ivar for given MSI-X vector
 658  *  @hw: pointer to the HW structure
 659  *  @msix_vector: vector number we are allocating to a given ring
 660  *  @index: row index of IVAR register to write within IVAR table
 661  *  @offset: column offset of in IVAR, should be multiple of 8
 662  *
 663  *  This function is intended to handle the writing of the IVAR register
 664  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 665  *  each containing an cause allocation for an Rx and Tx ring, and a
 666  *  variable number of rows depending on the number of queues supported.
 667  **/
 668 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 669                            int index, int offset)
 670 {
 671         u32 ivar = array_rd32(E1000_IVAR0, index);
 672
 673         /* clear any bits that are currently set */
 674         ivar &= ~((u32)0xFF << offset);
 675
 676         /* write vector and valid bit */
 677         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 678
 679         array_wr32(E1000_IVAR0, index, ivar);
 680 }
 681
 682 #define IGB_N0_QUEUE -1
 683 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 684 {
 685         struct igb_adapter *adapter = q_vector->adapter;
 686         struct e1000_hw *hw = &adapter->hw;
 687         int rx_queue = IGB_N0_QUEUE;
 688         int tx_queue = IGB_N0_QUEUE;
 689         u32 msixbm = 0;
 690
 691         if (q_vector->rx.ring)
 692                 rx_queue = q_vector->rx.ring->reg_idx;
 693         if (q_vector->tx.ring)
 694                 tx_queue = q_vector->tx.ring->reg_idx;
 695
 696         switch (hw->mac.type) {
 697         case e1000_82575:
 698                 /* The 82575 assigns vectors using a bitmask, which matches the
 699                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 700                    or more queues to a vector, we write the appropriate bits
 701                    into the MSIXBM register for that vector. */
 702                 if (rx_queue > IGB_N0_QUEUE)
 703                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 704                 if (tx_queue > IGB_N0_QUEUE)
 705                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 706                 if (!adapter->msix_entries && msix_vector == 0)
 707                         msixbm |= E1000_EIMS_OTHER;
 708                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 709                 q_vector->eims_value = msixbm;
 710                 break;
 711         case e1000_82576:
 712                 /*
 713                  * 82576 uses a table that essentially consists of 2 columns
 714                  * with 8 rows.  The ordering is column-major so we use the
 715                  * lower 3 bits as the row index, and the 4th bit as the
 716                  * column offset.
 717                  */
 718                 if (rx_queue > IGB_N0_QUEUE)
 719                         igb_write_ivar(hw, msix_vector,
 720                                        rx_queue & 0x7,
 721                                        (rx_queue & 0x8) << 1);
 722                 if (tx_queue > IGB_N0_QUEUE)
 723                         igb_write_ivar(hw, msix_vector,
 724                                        tx_queue & 0x7,
 725                                        ((tx_queue & 0x8) << 1) + 8);
 726                 q_vector->eims_value = 1 << msix_vector;
 727                 break;
 728         case e1000_82580:
 729         case e1000_i350:
 730         case e1000_i210:
 731         case e1000_i211:
 732                 /*
 733                  * On 82580 and newer adapters the scheme is similar to 82576
 734                  * however instead of ordering column-major we have things
 735                  * ordered row-major.  So we traverse the table by using
 736                  * bit 0 as the column offset, and the remaining bits as the
 737                  * row index.
 738                  */
 739                 if (rx_queue > IGB_N0_QUEUE)
 740                         igb_write_ivar(hw, msix_vector,
 741                                        rx_queue >> 1,
 742                                        (rx_queue & 0x1) << 4);
 743                 if (tx_queue > IGB_N0_QUEUE)
 744                         igb_write_ivar(hw, msix_vector,
 745                                        tx_queue >> 1,
 746                                        ((tx_queue & 0x1) << 4) + 8);
 747                 q_vector->eims_value = 1 << msix_vector;
 748                 break;
 749         default:
 750                 BUG();
 751                 break;
 752         }
 753
 754         /* add q_vector eims value to global eims_enable_mask */
 755         adapter->eims_enable_mask |= q_vector->eims_value;
 756
 757         /* configure q_vector to set itr on first interrupt */
 758         q_vector->set_itr = 1;
 759 }
 760
 761 /**
 762  * igb_configure_msix - Configure MSI-X hardware
 763  *
 764  * igb_configure_msix sets up the hardware to properly
 765  * generate MSI-X interrupts.
 766  **/
 767 static void igb_configure_msix(struct igb_adapter *adapter)
 768 {
 769         u32 tmp;
 770         int i, vector = 0;
 771         struct e1000_hw *hw = &adapter->hw;
 772
 773         adapter->eims_enable_mask = 0;
 774
 775         /* set vector for other causes, i.e. link changes */
 776         switch (hw->mac.type) {
 777         case e1000_82575:
 778                 tmp = rd32(E1000_CTRL_EXT);
 779                 /* enable MSI-X PBA support*/
 780                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 781
 782                 /* Auto-Mask interrupts upon ICR read. */
 783                 tmp |= E1000_CTRL_EXT_EIAME;
 784                 tmp |= E1000_CTRL_EXT_IRCA;
 785
 786                 wr32(E1000_CTRL_EXT, tmp);
 787
 788                 /* enable msix_other interrupt */
 789                 array_wr32(E1000_MSIXBM(0), vector++,
 790                                       E1000_EIMS_OTHER);
 791                 adapter->eims_other = E1000_EIMS_OTHER;
 792
 793                 break;
 794
 795         case e1000_82576:
 796         case e1000_82580:
 797         case e1000_i350:
 798         case e1000_i210:
 799         case e1000_i211:
 800                 /* Turn on MSI-X capability first, or our settings
 801                  * won't stick.  And it will take days to debug. */
 802                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 803                                 E1000_GPIE_PBA | E1000_GPIE_EIAME |
 804                                 E1000_GPIE_NSICR);
 805
 806                 /* enable msix_other interrupt */
 807                 adapter->eims_other = 1 << vector;
 808                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 809
 810                 wr32(E1000_IVAR_MISC, tmp);
 811                 break;
 812         default:
 813                 /* do nothing, since nothing else supports MSI-X */
 814                 break;
 815         } /* switch (hw->mac.type) */
 816
 817         adapter->eims_enable_mask |= adapter->eims_other;
 818
 819         for (i = 0; i < adapter->num_q_vectors; i++)
 820                 igb_assign_vector(adapter->q_vector[i], vector++);
 821
 822         wrfl();
 823 }
 824
 825 /**
 826  * igb_request_msix - Initialize MSI-X interrupts
 827  *
 828  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 829  * kernel.
 830  **/
 831 static int igb_request_msix(struct igb_adapter *adapter)
 832 {
 833         struct net_device *netdev = adapter->netdev;
 834         struct e1000_hw *hw = &adapter->hw;
 835         int i, err = 0, vector = 0, free_vector = 0;
 836
 837         err = request_irq(adapter->msix_entries[vector].vector,
 838                           igb_msix_other, 0, netdev->name, adapter);
 839         if (err)
 840                 goto err_out;
 841
 842         for (i = 0; i < adapter->num_q_vectors; i++) {
 843                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 844
 845                 vector++;
 846
 847                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 848
 849                 if (q_vector->rx.ring && q_vector->tx.ring)
 850                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 851                                 q_vector->rx.ring->queue_index);
 852                 else if (q_vector->tx.ring)
 853                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 854                                 q_vector->tx.ring->queue_index);
 855                 else if (q_vector->rx.ring)
 856                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 857                                 q_vector->rx.ring->queue_index);
 858                 else
 859                         sprintf(q_vector->name, "%s-unused", netdev->name);
 860
 861                 err = request_irq(adapter->msix_entries[vector].vector,
 862                                   igb_msix_ring, 0, q_vector->name,
 863                                   q_vector);
 864                 if (err)
 865                         goto err_free;
 866         }
 867
 868         igb_configure_msix(adapter);
 869         return 0;
 870
 871 err_free:
 872         /* free already assigned IRQs */
 873         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 874
 875         vector--;
 876         for (i = 0; i < vector; i++) {
 877                 free_irq(adapter->msix_entries[free_vector++].vector,
 878                          adapter->q_vector[i]);
 879         }
 880 err_out:
 881         return err;
 882 }
 883
 884 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 885 {
 886         if (adapter->msix_entries) {
 887                 pci_disable_msix(adapter->pdev);
 888                 kfree(adapter->msix_entries);
 889                 adapter->msix_entries = NULL;
 890         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 891                 pci_disable_msi(adapter->pdev);
 892         }
 893 }
 894
 895 /**
 896  * igb_free_q_vector - Free memory allocated for specific interrupt vector
 897  * @adapter: board private structure to initialize
 898  * @v_idx: Index of vector to be freed
 899  *
 900  * This function frees the memory allocated to the q_vector.  In addition if
 901  * NAPI is enabled it will delete any references to the NAPI struct prior
 902  * to freeing the q_vector.
 903  **/
 904 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 905 {
 906         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
 907
 908         if (q_vector->tx.ring)
 909                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
 910
 911         if (q_vector->rx.ring)
 912                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
 913
 914         adapter->q_vector[v_idx] = NULL;
 915         netif_napi_del(&q_vector->napi);
 916
 917         /*
 918          * ixgbe_get_stats64() might access the rings on this vector,
 919          * we must wait a grace period before freeing it.
 920          */
 921         kfree_rcu(q_vector, rcu);
 922 }
 923
 924 /**
 925  * igb_free_q_vectors - Free memory allocated for interrupt vectors
 926  * @adapter: board private structure to initialize
 927  *
 928  * This function frees the memory allocated to the q_vectors.  In addition if
 929  * NAPI is enabled it will delete any references to the NAPI struct prior
 930  * to freeing the q_vector.
 931  **/
 932 static void igb_free_q_vectors(struct igb_adapter *adapter)
 933 {
 934         int v_idx = adapter->num_q_vectors;
 935
 936         adapter->num_tx_queues = 0;
 937         adapter->num_rx_queues = 0;
 938         adapter->num_q_vectors = 0;
 939
 940         while (v_idx--)
 941                 igb_free_q_vector(adapter, v_idx);
 942 }
 943
 944 /**
 945  * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
 946  *
 947  * This function resets the device so that it has 0 rx queues, tx queues, and
 948  * MSI-X interrupts allocated.
 949  */
 950 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
 951 {
 952         igb_free_q_vectors(adapter);
 953         igb_reset_interrupt_capability(adapter);
 954 }
 955
 956 /**
 957  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 958  *
 959  * Attempt to configure interrupts using the best available
 960  * capabilities of the hardware and kernel.
 961  **/
 962 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
 963 {
 964         int err;
 965         int numvecs, i;
 966
 967         if (!msix)
 968                 goto msi_only;
 969
 970         /* Number of supported queues. */
 971         adapter->num_rx_queues = adapter->rss_queues;
 972         if (adapter->vfs_allocated_count)
 973                 adapter->num_tx_queues = 1;
 974         else
 975                 adapter->num_tx_queues = adapter->rss_queues;
 976
 977         /* start with one vector for every rx queue */
 978         numvecs = adapter->num_rx_queues;
 979
 980         /* if tx handler is separate add 1 for every tx queue */
 981         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
 982                 numvecs += adapter->num_tx_queues;
 983
 984         /* store the number of vectors reserved for queues */
 985         adapter->num_q_vectors = numvecs;
 986
 987         /* add 1 vector for link status interrupts */
 988         numvecs++;
 989         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 990                                         GFP_KERNEL);
 991
 992         if (!adapter->msix_entries)
 993                 goto msi_only;
 994
 995         for (i = 0; i < numvecs; i++)
 996                 adapter->msix_entries[i].entry = i;
 997
 998         err = pci_enable_msix(adapter->pdev,
 999                               adapter->msix_entries,
1000                               numvecs);
1001         if (err == 0)
1002                 return;
1003
1004         igb_reset_interrupt_capability(adapter);
1005
1006         /* If we can't do MSI-X, try MSI */
1007 msi_only:
1008 #ifdef CONFIG_PCI_IOV
1009         /* disable SR-IOV for non MSI-X configurations */
1010         if (adapter->vf_data) {
1011                 struct e1000_hw *hw = &adapter->hw;
1012                 /* disable iov and allow time for transactions to clear */
1013                 pci_disable_sriov(adapter->pdev);
1014                 msleep(500);
1015
1016                 kfree(adapter->vf_data);
1017                 adapter->vf_data = NULL;
1018                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1019                 wrfl();
1020                 msleep(100);
1021                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1022         }
1023 #endif
1024         adapter->vfs_allocated_count = 0;
1025         adapter->rss_queues = 1;
1026         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1027         adapter->num_rx_queues = 1;
1028         adapter->num_tx_queues = 1;
1029         adapter->num_q_vectors = 1;
1030         if (!pci_enable_msi(adapter->pdev))
1031                 adapter->flags |= IGB_FLAG_HAS_MSI;
1032 }
1033
1034 static void igb_add_ring(struct igb_ring *ring,
1035                          struct igb_ring_container *head)
1036 {
1037         head->ring = ring;
1038         head->count++;
1039 }
1040
1041 /**
1042  * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1043  * @adapter: board private structure to initialize
1044  * @v_count: q_vectors allocated on adapter, used for ring interleaving
1045  * @v_idx: index of vector in adapter struct
1046  * @txr_count: total number of Tx rings to allocate
1047  * @txr_idx: index of first Tx ring to allocate
1048  * @rxr_count: total number of Rx rings to allocate
1049  * @rxr_idx: index of first Rx ring to allocate
1050  *
1051  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
1052  **/
1053 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1054                               int v_count, int v_idx,
1055                               int txr_count, int txr_idx,
1056                               int rxr_count, int rxr_idx)
1057 {
1058         struct igb_q_vector *q_vector;
1059         struct igb_ring *ring;
1060         int ring_count, size;
1061
1062         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1063         if (txr_count > 1 || rxr_count > 1)
1064                 return -ENOMEM;
1065
1066         ring_count = txr_count + rxr_count;
1067         size = sizeof(struct igb_q_vector) +
1068                (sizeof(struct igb_ring) * ring_count);
1069
1070         /* allocate q_vector and rings */
1071         q_vector = kzalloc(size, GFP_KERNEL);
1072         if (!q_vector)
1073                 return -ENOMEM;
1074
1075         /* initialize NAPI */
1076         netif_napi_add(adapter->netdev, &q_vector->napi,
1077                        igb_poll, 64);
1078
1079         /* tie q_vector and adapter together */
1080         adapter->q_vector[v_idx] = q_vector;
1081         q_vector->adapter = adapter;
1082
1083         /* initialize work limits */
1084         q_vector->tx.work_limit = adapter->tx_work_limit;
1085
1086         /* initialize ITR configuration */
1087         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1088         q_vector->itr_val = IGB_START_ITR;
1089
1090         /* initialize pointer to rings */
1091         ring = q_vector->ring;
1092
1093         if (txr_count) {
1094                 /* assign generic ring traits */
1095                 ring->dev = &adapter->pdev->dev;
1096                 ring->netdev = adapter->netdev;
1097
1098                 /* configure backlink on ring */
1099                 ring->q_vector = q_vector;
1100
1101                 /* update q_vector Tx values */
1102                 igb_add_ring(ring, &q_vector->tx);
1103
1104                 /* For 82575, context index must be unique per ring. */
1105                 if (adapter->hw.mac.type == e1000_82575)
1106                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1107
1108                 /* apply Tx specific ring traits */
1109                 ring->count = adapter->tx_ring_count;
1110                 ring->queue_index = txr_idx;
1111
1112                 /* assign ring to adapter */
1113                 adapter->tx_ring[txr_idx] = ring;
1114
1115                 /* push pointer to next ring */
1116                 ring++;
1117         }
1118
1119         if (rxr_count) {
1120                 /* assign generic ring traits */
1121                 ring->dev = &adapter->pdev->dev;
1122                 ring->netdev = adapter->netdev;
1123
1124                 /* configure backlink on ring */
1125                 ring->q_vector = q_vector;
1126
1127                 /* update q_vector Rx values */
1128                 igb_add_ring(ring, &q_vector->rx);
1129
1130                 /* set flag indicating ring supports SCTP checksum offload */
1131                 if (adapter->hw.mac.type >= e1000_82576)
1132                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1133
1134                 /*
1135                  * On i350, i210, and i211, loopback VLAN packets
1136                  * have the tag byte-swapped.
1137                  * */
1138                 if (adapter->hw.mac.type >= e1000_i350)
1139                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1140
1141                 /* apply Rx specific ring traits */
1142                 ring->count = adapter->rx_ring_count;
1143                 ring->queue_index = rxr_idx;
1144
1145                 /* assign ring to adapter */
1146                 adapter->rx_ring[rxr_idx] = ring;
1147         }
1148
1149         return 0;
1150 }
1151
1152
1153 /**
1154  * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1155  * @adapter: board private structure to initialize
1156  *
1157  * We allocate one q_vector per queue interrupt.  If allocation fails we
1158  * return -ENOMEM.
1159  **/
1160 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1161 {
1162         int q_vectors = adapter->num_q_vectors;
1163         int rxr_remaining = adapter->num_rx_queues;
1164         int txr_remaining = adapter->num_tx_queues;
1165         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1166         int err;
1167
1168         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1169                 for (; rxr_remaining; v_idx++) {
1170                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1171                                                  0, 0, 1, rxr_idx);
1172
1173                         if (err)
1174                                 goto err_out;
1175
1176                         /* update counts and index */
1177                         rxr_remaining--;
1178                         rxr_idx++;
1179                 }
1180         }
1181
1182         for (; v_idx < q_vectors; v_idx++) {
1183                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1184                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1185                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1186                                          tqpv, txr_idx, rqpv, rxr_idx);
1187
1188                 if (err)
1189                         goto err_out;
1190
1191                 /* update counts and index */
1192                 rxr_remaining -= rqpv;
1193                 txr_remaining -= tqpv;
1194                 rxr_idx++;
1195                 txr_idx++;
1196         }
1197
1198         return 0;
1199
1200 err_out:
1201         adapter->num_tx_queues = 0;
1202         adapter->num_rx_queues = 0;
1203         adapter->num_q_vectors = 0;
1204
1205         while (v_idx--)
1206                 igb_free_q_vector(adapter, v_idx);
1207
1208         return -ENOMEM;
1209 }
1210
1211 /**
1212  * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1213  *
1214  * This function initializes the interrupts and allocates all of the queues.
1215  **/
1216 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1217 {
1218         struct pci_dev *pdev = adapter->pdev;
1219         int err;
1220
1221         igb_set_interrupt_capability(adapter, msix);
1222
1223         err = igb_alloc_q_vectors(adapter);
1224         if (err) {
1225                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1226                 goto err_alloc_q_vectors;
1227         }
1228
1229         igb_cache_ring_register(adapter);
1230
1231         return 0;
1232
1233 err_alloc_q_vectors:
1234         igb_reset_interrupt_capability(adapter);
1235         return err;
1236 }
1237
1238 /**
1239  * igb_request_irq - initialize interrupts
1240  *
1241  * Attempts to configure interrupts using the best available
1242  * capabilities of the hardware and kernel.
1243  **/
1244 static int igb_request_irq(struct igb_adapter *adapter)
1245 {
1246         struct net_device *netdev = adapter->netdev;
1247         struct pci_dev *pdev = adapter->pdev;
1248         int err = 0;
1249
1250         if (adapter->msix_entries) {
1251                 err = igb_request_msix(adapter);
1252                 if (!err)
1253                         goto request_done;
1254                 /* fall back to MSI */
1255                 igb_free_all_tx_resources(adapter);
1256                 igb_free_all_rx_resources(adapter);
1257
1258                 igb_clear_interrupt_scheme(adapter);
1259                 err = igb_init_interrupt_scheme(adapter, false);
1260                 if (err)
1261                         goto request_done;
1262
1263                 igb_setup_all_tx_resources(adapter);
1264                 igb_setup_all_rx_resources(adapter);
1265                 igb_configure(adapter);
1266         }
1267
1268         igb_assign_vector(adapter->q_vector[0], 0);
1269
1270         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1271                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1272                                   netdev->name, adapter);
1273                 if (!err)
1274                         goto request_done;
1275
1276                 /* fall back to legacy interrupts */
1277                 igb_reset_interrupt_capability(adapter);
1278                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1279         }
1280
1281         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1282                           netdev->name, adapter);
1283
1284         if (err)
1285                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1286                         err);
1287
1288 request_done:
1289         return err;
1290 }
1291
1292 static void igb_free_irq(struct igb_adapter *adapter)
1293 {
1294         if (adapter->msix_entries) {
1295                 int vector = 0, i;
1296
1297                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1298
1299                 for (i = 0; i < adapter->num_q_vectors; i++)
1300                         free_irq(adapter->msix_entries[vector++].vector,
1301                                  adapter->q_vector[i]);
1302         } else {
1303                 free_irq(adapter->pdev->irq, adapter);
1304         }
1305 }
1306
1307 /**
1308  * igb_irq_disable - Mask off interrupt generation on the NIC
1309  * @adapter: board private structure
1310  **/
1311 static void igb_irq_disable(struct igb_adapter *adapter)
1312 {
1313         struct e1000_hw *hw = &adapter->hw;
1314
1315         /*
1316          * we need to be careful when disabling interrupts.  The VFs are also
1317          * mapped into these registers and so clearing the bits can cause
1318          * issues on the VF drivers so we only need to clear what we set
1319          */
1320         if (adapter->msix_entries) {
1321                 u32 regval = rd32(E1000_EIAM);
1322                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1323                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1324                 regval = rd32(E1000_EIAC);
1325                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1326         }
1327
1328         wr32(E1000_IAM, 0);
1329         wr32(E1000_IMC, ~0);
1330         wrfl();
1331         if (adapter->msix_entries) {
1332                 int i;
1333                 for (i = 0; i < adapter->num_q_vectors; i++)
1334                         synchronize_irq(adapter->msix_entries[i].vector);
1335         } else {
1336                 synchronize_irq(adapter->pdev->irq);
1337         }
1338 }
1339
1340 /**
1341  * igb_irq_enable - Enable default interrupt generation settings
1342  * @adapter: board private structure
1343  **/
1344 static void igb_irq_enable(struct igb_adapter *adapter)
1345 {
1346         struct e1000_hw *hw = &adapter->hw;
1347
1348         if (adapter->msix_entries) {
1349                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1350                 u32 regval = rd32(E1000_EIAC);
1351                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1352                 regval = rd32(E1000_EIAM);
1353                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1354                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1355                 if (adapter->vfs_allocated_count) {
1356                         wr32(E1000_MBVFIMR, 0xFF);
1357                         ims |= E1000_IMS_VMMB;
1358                 }
1359                 wr32(E1000_IMS, ims);
1360         } else {
1361                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1362                                 E1000_IMS_DRSTA);
1363                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1364                                 E1000_IMS_DRSTA);
1365         }
1366 }
1367
1368 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1369 {
1370         struct e1000_hw *hw = &adapter->hw;
1371         u16 vid = adapter->hw.mng_cookie.vlan_id;
1372         u16 old_vid = adapter->mng_vlan_id;
1373
1374         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1375                 /* add VID to filter table */
1376                 igb_vfta_set(hw, vid, true);
1377                 adapter->mng_vlan_id = vid;
1378         } else {
1379                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1380         }
1381
1382         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1383             (vid != old_vid) &&
1384             !test_bit(old_vid, adapter->active_vlans)) {
1385                 /* remove VID from filter table */
1386                 igb_vfta_set(hw, old_vid, false);
1387         }
1388 }
1389
1390 /**
1391  * igb_release_hw_control - release control of the h/w to f/w
1392  * @adapter: address of board private structure
1393  *
1394  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1395  * For ASF and Pass Through versions of f/w this means that the
1396  * driver is no longer loaded.
1397  *
1398  **/
1399 static void igb_release_hw_control(struct igb_adapter *adapter)
1400 {
1401         struct e1000_hw *hw = &adapter->hw;
1402         u32 ctrl_ext;
1403
1404         /* Let firmware take over control of h/w */
1405         ctrl_ext = rd32(E1000_CTRL_EXT);
1406         wr32(E1000_CTRL_EXT,
1407                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1408 }
1409
1410 /**
1411  * igb_get_hw_control - get control of the h/w from f/w
1412  * @adapter: address of board private structure
1413  *
1414  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1415  * For ASF and Pass Through versions of f/w this means that
1416  * the driver is loaded.
1417  *
1418  **/
1419 static void igb_get_hw_control(struct igb_adapter *adapter)
1420 {
1421         struct e1000_hw *hw = &adapter->hw;
1422         u32 ctrl_ext;
1423
1424         /* Let firmware know the driver has taken over */
1425         ctrl_ext = rd32(E1000_CTRL_EXT);
1426         wr32(E1000_CTRL_EXT,
1427                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1428 }
1429
1430 /**
1431  * igb_configure - configure the hardware for RX and TX
1432  * @adapter: private board structure
1433  **/
1434 static void igb_configure(struct igb_adapter *adapter)
1435 {
1436         struct net_device *netdev = adapter->netdev;
1437         int i;
1438
1439         igb_get_hw_control(adapter);
1440         igb_set_rx_mode(netdev);
1441
1442         igb_restore_vlan(adapter);
1443
1444         igb_setup_tctl(adapter);
1445         igb_setup_mrqc(adapter);
1446         igb_setup_rctl(adapter);
1447
1448         igb_configure_tx(adapter);
1449         igb_configure_rx(adapter);
1450
1451         igb_rx_fifo_flush_82575(&adapter->hw);
1452
1453         /* call igb_desc_unused which always leaves
1454          * at least 1 descriptor unused to make sure
1455          * next_to_use != next_to_clean */
1456         for (i = 0; i < adapter->num_rx_queues; i++) {
1457                 struct igb_ring *ring = adapter->rx_ring[i];
1458                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1459         }
1460 }
1461
1462 /**
1463  * igb_power_up_link - Power up the phy/serdes link
1464  * @adapter: address of board private structure
1465  **/
1466 void igb_power_up_link(struct igb_adapter *adapter)
1467 {
1468         igb_reset_phy(&adapter->hw);
1469
1470         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1471                 igb_power_up_phy_copper(&adapter->hw);
1472         else
1473                 igb_power_up_serdes_link_82575(&adapter->hw);
1474 }
1475
1476 /**
1477  * igb_power_down_link - Power down the phy/serdes link
1478  * @adapter: address of board private structure
1479  */
1480 static void igb_power_down_link(struct igb_adapter *adapter)
1481 {
1482         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1483                 igb_power_down_phy_copper_82575(&adapter->hw);
1484         else
1485                 igb_shutdown_serdes_link_82575(&adapter->hw);
1486 }
1487
1488 /**
1489  * igb_up - Open the interface and prepare it to handle traffic
1490  * @adapter: board private structure
1491  **/
1492 int igb_up(struct igb_adapter *adapter)
1493 {
1494         struct e1000_hw *hw = &adapter->hw;
1495         int i;
1496
1497         /* hardware has been reset, we need to reload some things */
1498         igb_configure(adapter);
1499
1500         clear_bit(__IGB_DOWN, &adapter->state);
1501
1502         for (i = 0; i < adapter->num_q_vectors; i++)
1503                 napi_enable(&(adapter->q_vector[i]->napi));
1504
1505         if (adapter->msix_entries)
1506                 igb_configure_msix(adapter);
1507         else
1508                 igb_assign_vector(adapter->q_vector[0], 0);
1509
1510         /* Clear any pending interrupts. */
1511         rd32(E1000_ICR);
1512         igb_irq_enable(adapter);
1513
1514         /* notify VFs that reset has been completed */
1515         if (adapter->vfs_allocated_count) {
1516                 u32 reg_data = rd32(E1000_CTRL_EXT);
1517                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1518                 wr32(E1000_CTRL_EXT, reg_data);
1519         }
1520
1521         netif_tx_start_all_queues(adapter->netdev);
1522
1523         /* start the watchdog. */
1524         hw->mac.get_link_status = 1;
1525         schedule_work(&adapter->watchdog_task);
1526
1527         return 0;
1528 }
1529
1530 void igb_down(struct igb_adapter *adapter)
1531 {
1532         struct net_device *netdev = adapter->netdev;
1533         struct e1000_hw *hw = &adapter->hw;
1534         u32 tctl, rctl;
1535         int i;
1536
1537         /* signal that we're down so the interrupt handler does not
1538          * reschedule our watchdog timer */
1539         set_bit(__IGB_DOWN, &adapter->state);
1540
1541         /* disable receives in the hardware */
1542         rctl = rd32(E1000_RCTL);
1543         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1544         /* flush and sleep below */
1545
1546         netif_tx_stop_all_queues(netdev);
1547
1548         /* disable transmits in the hardware */
1549         tctl = rd32(E1000_TCTL);
1550         tctl &= ~E1000_TCTL_EN;
1551         wr32(E1000_TCTL, tctl);
1552         /* flush both disables and wait for them to finish */
1553         wrfl();
1554         msleep(10);
1555
1556         for (i = 0; i < adapter->num_q_vectors; i++)
1557                 napi_disable(&(adapter->q_vector[i]->napi));
1558
1559         igb_irq_disable(adapter);
1560
1561         del_timer_sync(&adapter->watchdog_timer);
1562         del_timer_sync(&adapter->phy_info_timer);
1563
1564         netif_carrier_off(netdev);
1565
1566         /* record the stats before reset*/
1567         spin_lock(&adapter->stats64_lock);
1568         igb_update_stats(adapter, &adapter->stats64);
1569         spin_unlock(&adapter->stats64_lock);
1570
1571         adapter->link_speed = 0;
1572         adapter->link_duplex = 0;
1573
1574         if (!pci_channel_offline(adapter->pdev))
1575                 igb_reset(adapter);
1576         igb_clean_all_tx_rings(adapter);
1577         igb_clean_all_rx_rings(adapter);
1578 #ifdef CONFIG_IGB_DCA
1579
1580         /* since we reset the hardware DCA settings were cleared */
1581         igb_setup_dca(adapter);
1582 #endif
1583 }
1584
1585 void igb_reinit_locked(struct igb_adapter *adapter)
1586 {
1587         WARN_ON(in_interrupt());
1588         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1589                 msleep(1);
1590         igb_down(adapter);
1591         igb_up(adapter);
1592         clear_bit(__IGB_RESETTING, &adapter->state);
1593 }
1594
1595 void igb_reset(struct igb_adapter *adapter)
1596 {
1597         struct pci_dev *pdev = adapter->pdev;
1598         struct e1000_hw *hw = &adapter->hw;
1599         struct e1000_mac_info *mac = &hw->mac;
1600         struct e1000_fc_info *fc = &hw->fc;
1601         u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1602
1603         /* Repartition Pba for greater than 9k mtu
1604          * To take effect CTRL.RST is required.
1605          */
1606         switch (mac->type) {
1607         case e1000_i350:
1608         case e1000_82580:
1609                 pba = rd32(E1000_RXPBS);
1610                 pba = igb_rxpbs_adjust_82580(pba);
1611                 break;
1612         case e1000_82576:
1613                 pba = rd32(E1000_RXPBS);
1614                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1615                 break;
1616         case e1000_82575:
1617         case e1000_i210:
1618         case e1000_i211:
1619         default:
1620                 pba = E1000_PBA_34K;
1621                 break;
1622         }
1623
1624         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1625             (mac->type < e1000_82576)) {
1626                 /* adjust PBA for jumbo frames */
1627                 wr32(E1000_PBA, pba);
1628
1629                 /* To maintain wire speed transmits, the Tx FIFO should be
1630                  * large enough to accommodate two full transmit packets,
1631                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1632                  * the Rx FIFO should be large enough to accommodate at least
1633                  * one full receive packet and is similarly rounded up and
1634                  * expressed in KB. */
1635                 pba = rd32(E1000_PBA);
1636                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1637                 tx_space = pba >> 16;
1638                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1639                 pba &= 0xffff;
1640                 /* the tx fifo also stores 16 bytes of information about the tx
1641                  * but don't include ethernet FCS because hardware appends it */
1642                 min_tx_space = (adapter->max_frame_size +
1643                                 sizeof(union e1000_adv_tx_desc) -
1644                                 ETH_FCS_LEN) * 2;
1645                 min_tx_space = ALIGN(min_tx_space, 1024);
1646                 min_tx_space >>= 10;
1647                 /* software strips receive CRC, so leave room for it */
1648                 min_rx_space = adapter->max_frame_size;
1649                 min_rx_space = ALIGN(min_rx_space, 1024);
1650                 min_rx_space >>= 10;
1651
1652                 /* If current Tx allocation is less than the min Tx FIFO size,
1653                  * and the min Tx FIFO size is less than the current Rx FIFO
1654                  * allocation, take space away from current Rx allocation */
1655                 if (tx_space < min_tx_space &&
1656                     ((min_tx_space - tx_space) < pba)) {
1657                         pba = pba - (min_tx_space - tx_space);
1658
1659                         /* if short on rx space, rx wins and must trump tx
1660                          * adjustment */
1661                         if (pba < min_rx_space)
1662                                 pba = min_rx_space;
1663                 }
1664                 wr32(E1000_PBA, pba);
1665         }
1666
1667         /* flow control settings */
1668         /* The high water mark must be low enough to fit one full frame
1669          * (or the size used for early receive) above it in the Rx FIFO.
1670          * Set it to the lower of:
1671          * - 90% of the Rx FIFO size, or
1672          * - the full Rx FIFO size minus one full frame */
1673         hwm = min(((pba << 10) * 9 / 10),
1674                         ((pba << 10) - 2 * adapter->max_frame_size));
1675
1676         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
1677         fc->low_water = fc->high_water - 16;
1678         fc->pause_time = 0xFFFF;
1679         fc->send_xon = 1;
1680         fc->current_mode = fc->requested_mode;
1681
1682         /* disable receive for all VFs and wait one second */
1683         if (adapter->vfs_allocated_count) {
1684                 int i;
1685                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1686                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1687
1688                 /* ping all the active vfs to let them know we are going down */
1689                 igb_ping_all_vfs(adapter);
1690
1691                 /* disable transmits and receives */
1692                 wr32(E1000_VFRE, 0);
1693                 wr32(E1000_VFTE, 0);
1694         }
1695
1696         /* Allow time for pending master requests to run */
1697         hw->mac.ops.reset_hw(hw);
1698         wr32(E1000_WUC, 0);
1699
1700         if (hw->mac.ops.init_hw(hw))
1701                 dev_err(&pdev->dev, "Hardware Error\n");
1702
1703         /*
1704          * Flow control settings reset on hardware reset, so guarantee flow
1705          * control is off when forcing speed.
1706          */
1707         if (!hw->mac.autoneg)
1708                 igb_force_mac_fc(hw);
1709
1710         igb_init_dmac(adapter, pba);
1711         if (!netif_running(adapter->netdev))
1712                 igb_power_down_link(adapter);
1713
1714         igb_update_mng_vlan(adapter);
1715
1716         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1717         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1718
1719         /* Re-enable PTP, where applicable. */
1720         igb_ptp_reset(adapter);
1721
1722         igb_get_phy_info(hw);
1723 }
1724
1725 static netdev_features_t igb_fix_features(struct net_device *netdev,
1726         netdev_features_t features)
1727 {
1728         /*
1729          * Since there is no support for separate rx/tx vlan accel
1730          * enable/disable make sure tx flag is always in same state as rx.
1731          */
1732         if (features & NETIF_F_HW_VLAN_RX)
1733                 features |= NETIF_F_HW_VLAN_TX;
1734         else
1735                 features &= ~NETIF_F_HW_VLAN_TX;
1736
1737         return features;
1738 }
1739
1740 static int igb_set_features(struct net_device *netdev,
1741         netdev_features_t features)
1742 {
1743         netdev_features_t changed = netdev->features ^ features;
1744         struct igb_adapter *adapter = netdev_priv(netdev);
1745
1746         if (changed & NETIF_F_HW_VLAN_RX)
1747                 igb_vlan_mode(netdev, features);
1748
1749         if (!(changed & NETIF_F_RXALL))
1750                 return 0;
1751
1752         netdev->features = features;
1753
1754         if (netif_running(netdev))
1755                 igb_reinit_locked(adapter);
1756         else
1757                 igb_reset(adapter);
1758
1759         return 0;
1760 }
1761
1762 static const struct net_device_ops igb_netdev_ops = {
1763         .ndo_open               = igb_open,
1764         .ndo_stop               = igb_close,
1765         .ndo_start_xmit         = igb_xmit_frame,
1766         .ndo_get_stats64        = igb_get_stats64,
1767         .ndo_set_rx_mode        = igb_set_rx_mode,
1768         .ndo_set_mac_address    = igb_set_mac,
1769         .ndo_change_mtu         = igb_change_mtu,
1770         .ndo_do_ioctl           = igb_ioctl,
1771         .ndo_tx_timeout         = igb_tx_timeout,
1772         .ndo_validate_addr      = eth_validate_addr,
1773         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1774         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1775         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1776         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1777         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1778         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1779 #ifdef CONFIG_NET_POLL_CONTROLLER
1780         .ndo_poll_controller    = igb_netpoll,
1781 #endif
1782         .ndo_fix_features       = igb_fix_features,
1783         .ndo_set_features       = igb_set_features,
1784 };
1785
1786 /**
1787  * igb_set_fw_version - Configure version string for ethtool
1788  * @adapter: adapter struct
1789  *
1790  **/
1791 void igb_set_fw_version(struct igb_adapter *adapter)
1792 {
1793         struct e1000_hw *hw = &adapter->hw;
1794         struct e1000_fw_version fw;
1795
1796         igb_get_fw_version(hw, &fw);
1797
1798         switch (hw->mac.type) {
1799         case e1000_i211:
1800                 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1801                          "%2d.%2d-%d",
1802                          fw.invm_major, fw.invm_minor, fw.invm_img_type);
1803                 break;
1804
1805         default:
1806                 /* if option is rom valid, display its version too */
1807                 if (fw.or_valid) {
1808                         snprintf(adapter->fw_version,
1809                                  sizeof(adapter->fw_version),
1810                                  "%d.%d, 0x%08x, %d.%d.%d",
1811                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1812                                  fw.or_major, fw.or_build, fw.or_patch);
1813                 /* no option rom */
1814                 } else {
1815                         snprintf(adapter->fw_version,
1816                                  sizeof(adapter->fw_version),
1817                                  "%d.%d, 0x%08x",
1818                                  fw.eep_major, fw.eep_minor, fw.etrack_id);
1819                 }
1820                 break;
1821         }
1822         return;
1823 }
1824
1825 /**
1826  * igb_probe - Device Initialization Routine
1827  * @pdev: PCI device information struct
1828  * @ent: entry in igb_pci_tbl
1829  *
1830  * Returns 0 on success, negative on failure
1831  *
1832  * igb_probe initializes an adapter identified by a pci_dev structure.
1833  * The OS initialization, configuring of the adapter private structure,
1834  * and a hardware reset occur.
1835  **/
1836 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1837 {
1838         struct net_device *netdev;
1839         struct igb_adapter *adapter;
1840         struct e1000_hw *hw;
1841         u16 eeprom_data = 0;
1842         s32 ret_val;
1843         static int global_quad_port_a; /* global quad port a indication */
1844         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1845         unsigned long mmio_start, mmio_len;
1846         int err, pci_using_dac;
1847         u8 part_str[E1000_PBANUM_LENGTH];
1848
1849         /* Catch broken hardware that put the wrong VF device ID in
1850          * the PCIe SR-IOV capability.
1851          */
1852         if (pdev->is_virtfn) {
1853                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1854                         pci_name(pdev), pdev->vendor, pdev->device);
1855                 return -EINVAL;
1856         }
1857
1858         err = pci_enable_device_mem(pdev);
1859         if (err)
1860                 return err;
1861
1862         pci_using_dac = 0;
1863         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1864         if (!err) {
1865                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1866                 if (!err)
1867                         pci_using_dac = 1;
1868         } else {
1869                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1870                 if (err) {
1871                         err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1872                         if (err) {
1873                                 dev_err(&pdev->dev, "No usable DMA "
1874                                         "configuration, aborting\n");
1875                                 goto err_dma;
1876                         }
1877                 }
1878         }
1879
1880         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1881                                            IORESOURCE_MEM),
1882                                            igb_driver_name);
1883         if (err)
1884                 goto err_pci_reg;
1885
1886         pci_enable_pcie_error_reporting(pdev);
1887
1888         pci_set_master(pdev);
1889         pci_save_state(pdev);
1890
1891         err = -ENOMEM;
1892         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1893                                    IGB_MAX_TX_QUEUES);
1894         if (!netdev)
1895                 goto err_alloc_etherdev;
1896
1897         SET_NETDEV_DEV(netdev, &pdev->dev);
1898
1899         pci_set_drvdata(pdev, netdev);
1900         adapter = netdev_priv(netdev);
1901         adapter->netdev = netdev;
1902         adapter->pdev = pdev;
1903         hw = &adapter->hw;
1904         hw->back = adapter;
1905         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1906
1907         mmio_start = pci_resource_start(pdev, 0);
1908         mmio_len = pci_resource_len(pdev, 0);
1909
1910         err = -EIO;
1911         hw->hw_addr = ioremap(mmio_start, mmio_len);
1912         if (!hw->hw_addr)
1913                 goto err_ioremap;
1914
1915         netdev->netdev_ops = &igb_netdev_ops;
1916         igb_set_ethtool_ops(netdev);
1917         netdev->watchdog_timeo = 5 * HZ;
1918
1919         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1920
1921         netdev->mem_start = mmio_start;
1922         netdev->mem_end = mmio_start + mmio_len;
1923
1924         /* PCI config space info */
1925         hw->vendor_id = pdev->vendor;
1926         hw->device_id = pdev->device;
1927         hw->revision_id = pdev->revision;
1928         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1929         hw->subsystem_device_id = pdev->subsystem_device;
1930
1931         /* Copy the default MAC, PHY and NVM function pointers */
1932         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1933         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1934         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1935         /* Initialize skew-specific constants */
1936         err = ei->get_invariants(hw);
1937         if (err)
1938                 goto err_sw_init;
1939
1940         /* setup the private structure */
1941         err = igb_sw_init(adapter);
1942         if (err)
1943                 goto err_sw_init;
1944
1945         igb_get_bus_info_pcie(hw);
1946
1947         hw->phy.autoneg_wait_to_complete = false;
1948
1949         /* Copper options */
1950         if (hw->phy.media_type == e1000_media_type_copper) {
1951                 hw->phy.mdix = AUTO_ALL_MODES;
1952                 hw->phy.disable_polarity_correction = false;
1953                 hw->phy.ms_type = e1000_ms_hw_default;
1954         }
1955
1956         if (igb_check_reset_block(hw))
1957                 dev_info(&pdev->dev,
1958                         "PHY reset is blocked due to SOL/IDER session.\n");
1959
1960         /*
1961          * features is initialized to 0 in allocation, it might have bits
1962          * set by igb_sw_init so we should use an or instead of an
1963          * assignment.
1964          */
1965         netdev->features |= NETIF_F_SG |
1966                             NETIF_F_IP_CSUM |
1967                             NETIF_F_IPV6_CSUM |
1968                             NETIF_F_TSO |
1969                             NETIF_F_TSO6 |
1970                             NETIF_F_RXHASH |
1971                             NETIF_F_RXCSUM |
1972                             NETIF_F_HW_VLAN_RX |
1973                             NETIF_F_HW_VLAN_TX;
1974
1975         /* copy netdev features into list of user selectable features */
1976         netdev->hw_features |= netdev->features;
1977         netdev->hw_features |= NETIF_F_RXALL;
1978
1979         /* set this bit last since it cannot be part of hw_features */
1980         netdev->features |= NETIF_F_HW_VLAN_FILTER;
1981
1982         netdev->vlan_features |= NETIF_F_TSO |
1983                                  NETIF_F_TSO6 |
1984                                  NETIF_F_IP_CSUM |
1985                                  NETIF_F_IPV6_CSUM |
1986                                  NETIF_F_SG;
1987
1988         netdev->priv_flags |= IFF_SUPP_NOFCS;
1989
1990         if (pci_using_dac) {
1991                 netdev->features |= NETIF_F_HIGHDMA;
1992                 netdev->vlan_features |= NETIF_F_HIGHDMA;
1993         }
1994
1995         if (hw->mac.type >= e1000_82576) {
1996                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
1997                 netdev->features |= NETIF_F_SCTP_CSUM;
1998         }
1999
2000         netdev->priv_flags |= IFF_UNICAST_FLT;
2001
2002         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2003
2004         /* before reading the NVM, reset the controller to put the device in a
2005          * known good starting state */
2006         hw->mac.ops.reset_hw(hw);
2007
2008         /*
2009          * make sure the NVM is good , i211 parts have special NVM that
2010          * doesn't contain a checksum
2011          */
2012         if (hw->mac.type != e1000_i211) {
2013                 if (hw->nvm.ops.validate(hw) < 0) {
2014                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2015                         err = -EIO;
2016                         goto err_eeprom;
2017                 }
2018         }
2019
2020         /* copy the MAC address out of the NVM */
2021         if (hw->mac.ops.read_mac_addr(hw))
2022                 dev_err(&pdev->dev, "NVM Read Error\n");
2023
2024         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2025
2026         if (!is_valid_ether_addr(netdev->dev_addr)) {
2027                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2028                 err = -EIO;
2029                 goto err_eeprom;
2030         }
2031
2032         /* get firmware version for ethtool -i */
2033         igb_set_fw_version(adapter);
2034
2035         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2036                     (unsigned long) adapter);
2037         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2038                     (unsigned long) adapter);
2039
2040         INIT_WORK(&adapter->reset_task, igb_reset_task);
2041         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2042
2043         /* Initialize link properties that are user-changeable */
2044         adapter->fc_autoneg = true;
2045         hw->mac.autoneg = true;
2046         hw->phy.autoneg_advertised = 0x2f;
2047
2048         hw->fc.requested_mode = e1000_fc_default;
2049         hw->fc.current_mode = e1000_fc_default;
2050
2051         igb_validate_mdi_setting(hw);
2052
2053         /* By default, support wake on port A */
2054         if (hw->bus.func == 0)
2055                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2056
2057         /* Check the NVM for wake support on non-port A ports */
2058         if (hw->mac.type >= e1000_82580)
2059                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2060                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2061                                  &eeprom_data);
2062         else if (hw->bus.func == 1)
2063                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2064
2065         if (eeprom_data & IGB_EEPROM_APME)
2066                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2067
2068         /* now that we have the eeprom settings, apply the special cases where
2069          * the eeprom may be wrong or the board simply won't support wake on
2070          * lan on a particular port */
2071         switch (pdev->device) {
2072         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2073                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2074                 break;
2075         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2076         case E1000_DEV_ID_82576_FIBER:
2077         case E1000_DEV_ID_82576_SERDES:
2078                 /* Wake events only supported on port A for dual fiber
2079                  * regardless of eeprom setting */
2080                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2081                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2082                 break;
2083         case E1000_DEV_ID_82576_QUAD_COPPER:
2084         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2085                 /* if quad port adapter, disable WoL on all but port A */
2086                 if (global_quad_port_a != 0)
2087                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2088                 else
2089                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2090                 /* Reset for multiple quad port adapters */
2091                 if (++global_quad_port_a == 4)
2092                         global_quad_port_a = 0;
2093                 break;
2094         default:
2095                 /* If the device can't wake, don't set software support */
2096                 if (!device_can_wakeup(&adapter->pdev->dev))
2097                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2098         }
2099
2100         /* initialize the wol settings based on the eeprom settings */
2101         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2102                 adapter->wol |= E1000_WUFC_MAG;
2103
2104         /* Some vendors want WoL disabled by default, but still supported */
2105         if ((hw->mac.type == e1000_i350) &&
2106             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2107                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2108                 adapter->wol = 0;
2109         }
2110
2111         device_set_wakeup_enable(&adapter->pdev->dev,
2112                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2113
2114         /* reset the hardware with the new settings */
2115         igb_reset(adapter);
2116
2117         /* let the f/w know that the h/w is now under the control of the
2118          * driver. */
2119         igb_get_hw_control(adapter);
2120
2121         strcpy(netdev->name, "eth%d");
2122         err = register_netdev(netdev);
2123         if (err)
2124                 goto err_register;
2125
2126         /* carrier off reporting is important to ethtool even BEFORE open */
2127         netif_carrier_off(netdev);
2128
2129 #ifdef CONFIG_IGB_DCA
2130         if (dca_add_requester(&pdev->dev) == 0) {
2131                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2132                 dev_info(&pdev->dev, "DCA enabled\n");
2133                 igb_setup_dca(adapter);
2134         }
2135
2136 #endif
2137
2138         /* do hw tstamp init after resetting */
2139         igb_ptp_init(adapter);
2140
2141         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2142         /* print bus type/speed/width info */
2143         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2144                  netdev->name,
2145                  ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2146                   (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2147                                                             "unknown"),
2148                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2149                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2150                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2151                    "unknown"),
2152                  netdev->dev_addr);
2153
2154         ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2155         if (ret_val)
2156                 strcpy(part_str, "Unknown");
2157         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2158         dev_info(&pdev->dev,
2159                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2160                 adapter->msix_entries ? "MSI-X" :
2161                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2162                 adapter->num_rx_queues, adapter->num_tx_queues);
2163         switch (hw->mac.type) {
2164         case e1000_i350:
2165         case e1000_i210:
2166         case e1000_i211:
2167                 igb_set_eee_i350(hw);
2168                 break;
2169         default:
2170                 break;
2171         }
2172
2173         pm_runtime_put_noidle(&pdev->dev);
2174         return 0;
2175
2176 err_register:
2177         igb_release_hw_control(adapter);
2178 err_eeprom:
2179         if (!igb_check_reset_block(hw))
2180                 igb_reset_phy(hw);
2181
2182         if (hw->flash_address)
2183                 iounmap(hw->flash_address);
2184 err_sw_init:
2185         igb_clear_interrupt_scheme(adapter);
2186         iounmap(hw->hw_addr);
2187 err_ioremap:
2188         free_netdev(netdev);
2189 err_alloc_etherdev:
2190         pci_release_selected_regions(pdev,
2191                                      pci_select_bars(pdev, IORESOURCE_MEM));
2192 err_pci_reg:
2193 err_dma:
2194         pci_disable_device(pdev);
2195         return err;
2196 }
2197
2198 /**
2199  * igb_remove - Device Removal Routine
2200  * @pdev: PCI device information struct
2201  *
2202  * igb_remove is called by the PCI subsystem to alert the driver
2203  * that it should release a PCI device.  The could be caused by a
2204  * Hot-Plug event, or because the driver is going to be removed from
2205  * memory.
2206  **/
2207 static void igb_remove(struct pci_dev *pdev)
2208 {
2209         struct net_device *netdev = pci_get_drvdata(pdev);
2210         struct igb_adapter *adapter = netdev_priv(netdev);
2211         struct e1000_hw *hw = &adapter->hw;
2212
2213         pm_runtime_get_noresume(&pdev->dev);
2214         igb_ptp_stop(adapter);
2215
2216         /*
2217          * The watchdog timer may be rescheduled, so explicitly
2218          * disable watchdog from being rescheduled.
2219          */
2220         set_bit(__IGB_DOWN, &adapter->state);
2221         del_timer_sync(&adapter->watchdog_timer);
2222         del_timer_sync(&adapter->phy_info_timer);
2223
2224         cancel_work_sync(&adapter->reset_task);
2225         cancel_work_sync(&adapter->watchdog_task);
2226
2227 #ifdef CONFIG_IGB_DCA
2228         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2229                 dev_info(&pdev->dev, "DCA disabled\n");
2230                 dca_remove_requester(&pdev->dev);
2231                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2232                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2233         }
2234 #endif
2235
2236         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2237          * would have already happened in close and is redundant. */
2238         igb_release_hw_control(adapter);
2239
2240         unregister_netdev(netdev);
2241
2242         igb_clear_interrupt_scheme(adapter);
2243
2244 #ifdef CONFIG_PCI_IOV
2245         /* reclaim resources allocated to VFs */
2246         if (adapter->vf_data) {
2247                 /* disable iov and allow time for transactions to clear */
2248                 if (igb_vfs_are_assigned(adapter)) {
2249                         dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
2250                 } else {
2251                         pci_disable_sriov(pdev);
2252                         msleep(500);
2253                 }
2254
2255                 kfree(adapter->vf_data);
2256                 adapter->vf_data = NULL;
2257                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2258                 wrfl();
2259                 msleep(100);
2260                 dev_info(&pdev->dev, "IOV Disabled\n");
2261         }
2262 #endif
2263
2264         iounmap(hw->hw_addr);
2265         if (hw->flash_address)
2266                 iounmap(hw->flash_address);
2267         pci_release_selected_regions(pdev,
2268                                      pci_select_bars(pdev, IORESOURCE_MEM));
2269
2270         kfree(adapter->shadow_vfta);
2271         free_netdev(netdev);
2272
2273         pci_disable_pcie_error_reporting(pdev);
2274
2275         pci_disable_device(pdev);
2276 }
2277
2278 /**
2279  * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2280  * @adapter: board private structure to initialize
2281  *
2282  * This function initializes the vf specific data storage and then attempts to
2283  * allocate the VFs.  The reason for ordering it this way is because it is much
2284  * mor expensive time wise to disable SR-IOV than it is to allocate and free
2285  * the memory for the VFs.
2286  **/
2287 static void igb_probe_vfs(struct igb_adapter *adapter)
2288 {
2289 #ifdef CONFIG_PCI_IOV
2290         struct pci_dev *pdev = adapter->pdev;
2291         struct e1000_hw *hw = &adapter->hw;
2292         int old_vfs = pci_num_vf(adapter->pdev);
2293         int i;
2294
2295         /* Virtualization features not supported on i210 family. */
2296         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2297                 return;
2298
2299         if (old_vfs) {
2300                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override "
2301                          "max_vfs setting of %d\n", old_vfs, max_vfs);
2302                 adapter->vfs_allocated_count = old_vfs;
2303         }
2304
2305         if (!adapter->vfs_allocated_count)
2306                 return;
2307
2308         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2309                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2310
2311         /* if allocation failed then we do not support SR-IOV */
2312         if (!adapter->vf_data) {
2313                 adapter->vfs_allocated_count = 0;
2314                 dev_err(&pdev->dev, "Unable to allocate memory for VF "
2315                         "Data Storage\n");
2316                 goto out;
2317         }
2318
2319         if (!old_vfs) {
2320                 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count))
2321                         goto err_out;
2322         }
2323         dev_info(&pdev->dev, "%d VFs allocated\n",
2324                  adapter->vfs_allocated_count);
2325         for (i = 0; i < adapter->vfs_allocated_count; i++)
2326                 igb_vf_configure(adapter, i);
2327
2328         /* DMA Coalescing is not supported in IOV mode. */
2329         adapter->flags &= ~IGB_FLAG_DMAC;
2330         goto out;
2331 err_out:
2332         kfree(adapter->vf_data);
2333         adapter->vf_data = NULL;
2334         adapter->vfs_allocated_count = 0;
2335 out:
2336         return;
2337 #endif /* CONFIG_PCI_IOV */
2338 }
2339
2340 /**
2341  * igb_sw_init - Initialize general software structures (struct igb_adapter)
2342  * @adapter: board private structure to initialize
2343  *
2344  * igb_sw_init initializes the Adapter private data structure.
2345  * Fields are initialized based on PCI device information and
2346  * OS network device settings (MTU size).
2347  **/
2348 static int igb_sw_init(struct igb_adapter *adapter)
2349 {
2350         struct e1000_hw *hw = &adapter->hw;
2351         struct net_device *netdev = adapter->netdev;
2352         struct pci_dev *pdev = adapter->pdev;
2353         u32 max_rss_queues;
2354
2355         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2356
2357         /* set default ring sizes */
2358         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2359         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2360
2361         /* set default ITR values */
2362         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2363         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2364
2365         /* set default work limits */
2366         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2367
2368         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2369                                   VLAN_HLEN;
2370         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2371
2372         spin_lock_init(&adapter->stats64_lock);
2373 #ifdef CONFIG_PCI_IOV
2374         switch (hw->mac.type) {
2375         case e1000_82576:
2376         case e1000_i350:
2377                 if (max_vfs > 7) {
2378                         dev_warn(&pdev->dev,
2379                                  "Maximum of 7 VFs per PF, using max\n");
2380                         adapter->vfs_allocated_count = 7;
2381                 } else
2382                         adapter->vfs_allocated_count = max_vfs;
2383                 break;
2384         default:
2385                 break;
2386         }
2387 #endif /* CONFIG_PCI_IOV */
2388
2389         /* Determine the maximum number of RSS queues supported. */
2390         switch (hw->mac.type) {
2391         case e1000_i211:
2392                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2393                 break;
2394         case e1000_82575:
2395         case e1000_i210:
2396                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2397                 break;
2398         case e1000_i350:
2399                 /* I350 cannot do RSS and SR-IOV at the same time */
2400                 if (!!adapter->vfs_allocated_count) {
2401                         max_rss_queues = 1;
2402                         break;
2403                 }
2404                 /* fall through */
2405         case e1000_82576:
2406                 if (!!adapter->vfs_allocated_count) {
2407                         max_rss_queues = 2;
2408                         break;
2409                 }
2410                 /* fall through */
2411         case e1000_82580:
2412         default:
2413                 max_rss_queues = IGB_MAX_RX_QUEUES;
2414                 break;
2415         }
2416
2417         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2418
2419         /* Determine if we need to pair queues. */
2420         switch (hw->mac.type) {
2421         case e1000_82575:
2422         case e1000_i211:
2423                 /* Device supports enough interrupts without queue pairing. */
2424                 break;
2425         case e1000_82576:
2426                 /*
2427                  * If VFs are going to be allocated with RSS queues then we
2428                  * should pair the queues in order to conserve interrupts due
2429                  * to limited supply.
2430                  */
2431                 if ((adapter->rss_queues > 1) &&
2432                     (adapter->vfs_allocated_count > 6))
2433                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2434                 /* fall through */
2435         case e1000_82580:
2436         case e1000_i350:
2437         case e1000_i210:
2438         default:
2439                 /*
2440                  * If rss_queues > half of max_rss_queues, pair the queues in
2441                  * order to conserve interrupts due to limited supply.
2442                  */
2443                 if (adapter->rss_queues > (max_rss_queues / 2))
2444                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2445                 break;
2446         }
2447
2448         /* Setup and initialize a copy of the hw vlan table array */
2449         adapter->shadow_vfta = kzalloc(sizeof(u32) *
2450                                 E1000_VLAN_FILTER_TBL_SIZE,
2451                                 GFP_ATOMIC);
2452
2453         /* This call may decrease the number of queues */
2454         if (igb_init_interrupt_scheme(adapter, true)) {
2455                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2456                 return -ENOMEM;
2457         }
2458
2459         igb_probe_vfs(adapter);
2460
2461         /* Explicitly disable IRQ since the NIC can be in any state. */
2462         igb_irq_disable(adapter);
2463
2464         if (hw->mac.type >= e1000_i350)
2465                 adapter->flags &= ~IGB_FLAG_DMAC;
2466
2467         set_bit(__IGB_DOWN, &adapter->state);
2468         return 0;
2469 }
2470
2471 /**
2472  * igb_open - Called when a network interface is made active
2473  * @netdev: network interface device structure
2474  *
2475  * Returns 0 on success, negative value on failure
2476  *
2477  * The open entry point is called when a network interface is made
2478  * active by the system (IFF_UP).  At this point all resources needed
2479  * for transmit and receive operations are allocated, the interrupt
2480  * handler is registered with the OS, the watchdog timer is started,
2481  * and the stack is notified that the interface is ready.
2482  **/
2483 static int __igb_open(struct net_device *netdev, bool resuming)
2484 {
2485         struct igb_adapter *adapter = netdev_priv(netdev);
2486         struct e1000_hw *hw = &adapter->hw;
2487         struct pci_dev *pdev = adapter->pdev;
2488         int err;
2489         int i;
2490
2491         /* disallow open during test */
2492         if (test_bit(__IGB_TESTING, &adapter->state)) {
2493                 WARN_ON(resuming);
2494                 return -EBUSY;
2495         }
2496
2497         if (!resuming)
2498                 pm_runtime_get_sync(&pdev->dev);
2499
2500         netif_carrier_off(netdev);
2501
2502         /* allocate transmit descriptors */
2503         err = igb_setup_all_tx_resources(adapter);
2504         if (err)
2505                 goto err_setup_tx;
2506
2507         /* allocate receive descriptors */
2508         err = igb_setup_all_rx_resources(adapter);
2509         if (err)
2510                 goto err_setup_rx;
2511
2512         igb_power_up_link(adapter);
2513
2514         /* before we allocate an interrupt, we must be ready to handle it.
2515          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2516          * as soon as we call pci_request_irq, so we have to setup our
2517          * clean_rx handler before we do so.  */
2518         igb_configure(adapter);
2519
2520         err = igb_request_irq(adapter);
2521         if (err)
2522                 goto err_req_irq;
2523
2524         /* Notify the stack of the actual queue counts. */
2525         err = netif_set_real_num_tx_queues(adapter->netdev,
2526                                            adapter->num_tx_queues);
2527         if (err)
2528                 goto err_set_queues;
2529
2530         err = netif_set_real_num_rx_queues(adapter->netdev,
2531                                            adapter->num_rx_queues);
2532         if (err)
2533                 goto err_set_queues;
2534
2535         /* From here on the code is the same as igb_up() */
2536         clear_bit(__IGB_DOWN, &adapter->state);
2537
2538         for (i = 0; i < adapter->num_q_vectors; i++)
2539                 napi_enable(&(adapter->q_vector[i]->napi));
2540
2541         /* Clear any pending interrupts. */
2542         rd32(E1000_ICR);
2543
2544         igb_irq_enable(adapter);
2545
2546         /* notify VFs that reset has been completed */
2547         if (adapter->vfs_allocated_count) {
2548                 u32 reg_data = rd32(E1000_CTRL_EXT);
2549                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2550                 wr32(E1000_CTRL_EXT, reg_data);
2551         }
2552
2553         netif_tx_start_all_queues(netdev);
2554
2555         if (!resuming)
2556                 pm_runtime_put(&pdev->dev);
2557
2558         /* start the watchdog. */
2559         hw->mac.get_link_status = 1;
2560         schedule_work(&adapter->watchdog_task);
2561
2562         return 0;
2563
2564 err_set_queues:
2565         igb_free_irq(adapter);
2566 err_req_irq:
2567         igb_release_hw_control(adapter);
2568         igb_power_down_link(adapter);
2569         igb_free_all_rx_resources(adapter);
2570 err_setup_rx:
2571         igb_free_all_tx_resources(adapter);
2572 err_setup_tx:
2573         igb_reset(adapter);
2574         if (!resuming)
2575                 pm_runtime_put(&pdev->dev);
2576
2577         return err;
2578 }
2579
2580 static int igb_open(struct net_device *netdev)
2581 {
2582         return __igb_open(netdev, false);
2583 }
2584
2585 /**
2586  * igb_close - Disables a network interface
2587  * @netdev: network interface device structure
2588  *
2589  * Returns 0, this is not allowed to fail
2590  *
2591  * The close entry point is called when an interface is de-activated
2592  * by the OS.  The hardware is still under the driver's control, but
2593  * needs to be disabled.  A global MAC reset is issued to stop the
2594  * hardware, and all transmit and receive resources are freed.
2595  **/
2596 static int __igb_close(struct net_device *netdev, bool suspending)
2597 {
2598         struct igb_adapter *adapter = netdev_priv(netdev);
2599         struct pci_dev *pdev = adapter->pdev;
2600
2601         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2602
2603         if (!suspending)
2604                 pm_runtime_get_sync(&pdev->dev);
2605
2606         igb_down(adapter);
2607         igb_free_irq(adapter);
2608
2609         igb_free_all_tx_resources(adapter);
2610         igb_free_all_rx_resources(adapter);
2611
2612         if (!suspending)
2613                 pm_runtime_put_sync(&pdev->dev);
2614         return 0;
2615 }
2616
2617 static int igb_close(struct net_device *netdev)
2618 {
2619         return __igb_close(netdev, false);
2620 }
2621
2622 /**
2623  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2624  * @tx_ring: tx descriptor ring (for a specific queue) to setup
2625  *
2626  * Return 0 on success, negative on failure
2627  **/
2628 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2629 {
2630         struct device *dev = tx_ring->dev;
2631         int size;
2632
2633         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2634
2635         tx_ring->tx_buffer_info = vzalloc(size);
2636         if (!tx_ring->tx_buffer_info)
2637                 goto err;
2638
2639         /* round up to nearest 4K */
2640         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2641         tx_ring->size = ALIGN(tx_ring->size, 4096);
2642
2643         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2644                                            &tx_ring->dma, GFP_KERNEL);
2645         if (!tx_ring->desc)
2646                 goto err;
2647
2648         tx_ring->next_to_use = 0;
2649         tx_ring->next_to_clean = 0;
2650
2651         return 0;
2652
2653 err:
2654         vfree(tx_ring->tx_buffer_info);
2655         tx_ring->tx_buffer_info = NULL;
2656         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2657         return -ENOMEM;
2658 }
2659
2660 /**
2661  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2662  *                                (Descriptors) for all queues
2663  * @adapter: board private structure
2664  *
2665  * Return 0 on success, negative on failure
2666  **/
2667 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2668 {
2669         struct pci_dev *pdev = adapter->pdev;
2670         int i, err = 0;
2671
2672         for (i = 0; i < adapter->num_tx_queues; i++) {
2673                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2674                 if (err) {
2675                         dev_err(&pdev->dev,
2676                                 "Allocation for Tx Queue %u failed\n", i);
2677                         for (i--; i >= 0; i--)
2678                                 igb_free_tx_resources(adapter->tx_ring[i]);
2679                         break;
2680                 }
2681         }
2682
2683         return err;
2684 }
2685
2686 /**
2687  * igb_setup_tctl - configure the transmit control registers
2688  * @adapter: Board private structure
2689  **/
2690 void igb_setup_tctl(struct igb_adapter *adapter)
2691 {
2692         struct e1000_hw *hw = &adapter->hw;
2693         u32 tctl;
2694
2695         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2696         wr32(E1000_TXDCTL(0), 0);
2697
2698         /* Program the Transmit Control Register */
2699         tctl = rd32(E1000_TCTL);
2700         tctl &= ~E1000_TCTL_CT;
2701         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2702                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2703
2704         igb_config_collision_dist(hw);
2705
2706         /* Enable transmits */
2707         tctl |= E1000_TCTL_EN;
2708
2709         wr32(E1000_TCTL, tctl);
2710 }
2711
2712 /**
2713  * igb_configure_tx_ring - Configure transmit ring after Reset
2714  * @adapter: board private structure
2715  * @ring: tx ring to configure
2716  *
2717  * Configure a transmit ring after a reset.
2718  **/
2719 void igb_configure_tx_ring(struct igb_adapter *adapter,
2720                            struct igb_ring *ring)
2721 {
2722         struct e1000_hw *hw = &adapter->hw;
2723         u32 txdctl = 0;
2724         u64 tdba = ring->dma;
2725         int reg_idx = ring->reg_idx;
2726
2727         /* disable the queue */
2728         wr32(E1000_TXDCTL(reg_idx), 0);
2729         wrfl();
2730         mdelay(10);
2731
2732         wr32(E1000_TDLEN(reg_idx),
2733                         ring->count * sizeof(union e1000_adv_tx_desc));
2734         wr32(E1000_TDBAL(reg_idx),
2735                         tdba & 0x00000000ffffffffULL);
2736         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2737
2738         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2739         wr32(E1000_TDH(reg_idx), 0);
2740         writel(0, ring->tail);
2741
2742         txdctl |= IGB_TX_PTHRESH;
2743         txdctl |= IGB_TX_HTHRESH << 8;
2744         txdctl |= IGB_TX_WTHRESH << 16;
2745
2746         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2747         wr32(E1000_TXDCTL(reg_idx), txdctl);
2748 }
2749
2750 /**
2751  * igb_configure_tx - Configure transmit Unit after Reset
2752  * @adapter: board private structure
2753  *
2754  * Configure the Tx unit of the MAC after a reset.
2755  **/
2756 static void igb_configure_tx(struct igb_adapter *adapter)
2757 {
2758         int i;
2759
2760         for (i = 0; i < adapter->num_tx_queues; i++)
2761                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2762 }
2763
2764 /**
2765  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2766  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2767  *
2768  * Returns 0 on success, negative on failure
2769  **/
2770 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2771 {
2772         struct device *dev = rx_ring->dev;
2773         int size;
2774
2775         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2776
2777         rx_ring->rx_buffer_info = vzalloc(size);
2778         if (!rx_ring->rx_buffer_info)
2779                 goto err;
2780
2781         /* Round up to nearest 4K */
2782         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
2783         rx_ring->size = ALIGN(rx_ring->size, 4096);
2784
2785         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2786                                            &rx_ring->dma, GFP_KERNEL);
2787         if (!rx_ring->desc)
2788                 goto err;
2789
2790         rx_ring->next_to_alloc = 0;
2791         rx_ring->next_to_clean = 0;
2792         rx_ring->next_to_use = 0;
2793
2794         return 0;
2795
2796 err:
2797         vfree(rx_ring->rx_buffer_info);
2798         rx_ring->rx_buffer_info = NULL;
2799         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2800         return -ENOMEM;
2801 }
2802
2803 /**
2804  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2805  *                                (Descriptors) for all queues
2806  * @adapter: board private structure
2807  *
2808  * Return 0 on success, negative on failure
2809  **/
2810 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2811 {
2812         struct pci_dev *pdev = adapter->pdev;
2813         int i, err = 0;
2814
2815         for (i = 0; i < adapter->num_rx_queues; i++) {
2816                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
2817                 if (err) {
2818                         dev_err(&pdev->dev,
2819                                 "Allocation for Rx Queue %u failed\n", i);
2820                         for (i--; i >= 0; i--)
2821                                 igb_free_rx_resources(adapter->rx_ring[i]);
2822                         break;
2823                 }
2824         }
2825
2826         return err;
2827 }
2828
2829 /**
2830  * igb_setup_mrqc - configure the multiple receive queue control registers
2831  * @adapter: Board private structure
2832  **/
2833 static void igb_setup_mrqc(struct igb_adapter *adapter)
2834 {
2835         struct e1000_hw *hw = &adapter->hw;
2836         u32 mrqc, rxcsum;
2837         u32 j, num_rx_queues, shift = 0;
2838         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
2839                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
2840                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
2841                                         0xFA01ACBE };
2842
2843         /* Fill out hash function seeds */
2844         for (j = 0; j < 10; j++)
2845                 wr32(E1000_RSSRK(j), rsskey[j]);
2846
2847         num_rx_queues = adapter->rss_queues;
2848
2849         switch (hw->mac.type) {
2850         case e1000_82575:
2851                 shift = 6;
2852                 break;
2853         case e1000_82576:
2854                 /* 82576 supports 2 RSS queues for SR-IOV */
2855                 if (adapter->vfs_allocated_count) {
2856                         shift = 3;
2857                         num_rx_queues = 2;
2858                 }
2859                 break;
2860         default:
2861                 break;
2862         }
2863
2864         /*
2865          * Populate the indirection table 4 entries at a time.  To do this
2866          * we are generating the results for n and n+2 and then interleaving
2867          * those with the results with n+1 and n+3.
2868          */
2869         for (j = 0; j < 32; j++) {
2870                 /* first pass generates n and n+2 */
2871                 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
2872                 u32 reta = (base & 0x07800780) >> (7 - shift);
2873
2874                 /* second pass generates n+1 and n+3 */
2875                 base += 0x00010001 * num_rx_queues;
2876                 reta |= (base & 0x07800780) << (1 + shift);
2877
2878                 wr32(E1000_RETA(j), reta);
2879         }
2880
2881         /*
2882          * Disable raw packet checksumming so that RSS hash is placed in
2883          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
2884          * offloads as they are enabled by default
2885          */
2886         rxcsum = rd32(E1000_RXCSUM);
2887         rxcsum |= E1000_RXCSUM_PCSD;
2888
2889         if (adapter->hw.mac.type >= e1000_82576)
2890                 /* Enable Receive Checksum Offload for SCTP */
2891                 rxcsum |= E1000_RXCSUM_CRCOFL;
2892
2893         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2894         wr32(E1000_RXCSUM, rxcsum);
2895
2896         /* Generate RSS hash based on packet types, TCP/UDP
2897          * port numbers and/or IPv4/v6 src and dst addresses
2898          */
2899         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
2900                E1000_MRQC_RSS_FIELD_IPV4_TCP |
2901                E1000_MRQC_RSS_FIELD_IPV6 |
2902                E1000_MRQC_RSS_FIELD_IPV6_TCP |
2903                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2904
2905         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2906                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2907         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2908                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2909
2910         /* If VMDq is enabled then we set the appropriate mode for that, else
2911          * we default to RSS so that an RSS hash is calculated per packet even
2912          * if we are only using one queue */
2913         if (adapter->vfs_allocated_count) {
2914                 if (hw->mac.type > e1000_82575) {
2915                         /* Set the default pool for the PF's first queue */
2916                         u32 vtctl = rd32(E1000_VT_CTL);
2917                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2918                                    E1000_VT_CTL_DISABLE_DEF_POOL);
2919                         vtctl |= adapter->vfs_allocated_count <<
2920                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2921                         wr32(E1000_VT_CTL, vtctl);
2922                 }
2923                 if (adapter->rss_queues > 1)
2924                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2925                 else
2926                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
2927         } else {
2928                 if (hw->mac.type != e1000_i211)
2929                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
2930         }
2931         igb_vmm_control(adapter);
2932
2933         wr32(E1000_MRQC, mrqc);
2934 }
2935
2936 /**
2937  * igb_setup_rctl - configure the receive control registers
2938  * @adapter: Board private structure
2939  **/
2940 void igb_setup_rctl(struct igb_adapter *adapter)
2941 {
2942         struct e1000_hw *hw = &adapter->hw;
2943         u32 rctl;
2944
2945         rctl = rd32(E1000_RCTL);
2946
2947         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2948         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2949
2950         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2951                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2952
2953         /*
2954          * enable stripping of CRC. It's unlikely this will break BMC
2955          * redirection as it did with e1000. Newer features require
2956          * that the HW strips the CRC.
2957          */
2958         rctl |= E1000_RCTL_SECRC;
2959
2960         /* disable store bad packets and clear size bits. */
2961         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2962
2963         /* enable LPE to prevent packets larger than max_frame_size */
2964         rctl |= E1000_RCTL_LPE;
2965
2966         /* disable queue 0 to prevent tail write w/o re-config */
2967         wr32(E1000_RXDCTL(0), 0);
2968
2969         /* Attention!!!  For SR-IOV PF driver operations you must enable
2970          * queue drop for all VF and PF queues to prevent head of line blocking
2971          * if an un-trusted VF does not provide descriptors to hardware.
2972          */
2973         if (adapter->vfs_allocated_count) {
2974                 /* set all queue drop enable bits */
2975                 wr32(E1000_QDE, ALL_QUEUES);
2976         }
2977
2978         /* This is useful for sniffing bad packets. */
2979         if (adapter->netdev->features & NETIF_F_RXALL) {
2980                 /* UPE and MPE will be handled by normal PROMISC logic
2981                  * in e1000e_set_rx_mode */
2982                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
2983                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
2984                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
2985
2986                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
2987                           E1000_RCTL_DPF | /* Allow filtered pause */
2988                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
2989                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
2990                  * and that breaks VLANs.
2991                  */
2992         }
2993
2994         wr32(E1000_RCTL, rctl);
2995 }
2996
2997 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
2998                                    int vfn)
2999 {
3000         struct e1000_hw *hw = &adapter->hw;
3001         u32 vmolr;
3002
3003         /* if it isn't the PF check to see if VFs are enabled and
3004          * increase the size to support vlan tags */
3005         if (vfn < adapter->vfs_allocated_count &&
3006             adapter->vf_data[vfn].vlans_enabled)
3007                 size += VLAN_TAG_SIZE;
3008
3009         vmolr = rd32(E1000_VMOLR(vfn));
3010         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3011         vmolr |= size | E1000_VMOLR_LPE;
3012         wr32(E1000_VMOLR(vfn), vmolr);
3013
3014         return 0;
3015 }
3016
3017 /**
3018  * igb_rlpml_set - set maximum receive packet size
3019  * @adapter: board private structure
3020  *
3021  * Configure maximum receivable packet size.
3022  **/
3023 static void igb_rlpml_set(struct igb_adapter *adapter)
3024 {
3025         u32 max_frame_size = adapter->max_frame_size;
3026         struct e1000_hw *hw = &adapter->hw;
3027         u16 pf_id = adapter->vfs_allocated_count;
3028
3029         if (pf_id) {
3030                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3031                 /*
3032                  * If we're in VMDQ or SR-IOV mode, then set global RLPML
3033                  * to our max jumbo frame size, in case we need to enable
3034                  * jumbo frames on one of the rings later.
3035                  * This will not pass over-length frames into the default
3036                  * queue because it's gated by the VMOLR.RLPML.
3037                  */
3038                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3039         }
3040
3041         wr32(E1000_RLPML, max_frame_size);
3042 }
3043
3044 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3045                                  int vfn, bool aupe)
3046 {
3047         struct e1000_hw *hw = &adapter->hw;
3048         u32 vmolr;
3049
3050         /*
3051          * This register exists only on 82576 and newer so if we are older then
3052          * we should exit and do nothing
3053          */
3054         if (hw->mac.type < e1000_82576)
3055                 return;
3056
3057         vmolr = rd32(E1000_VMOLR(vfn));
3058         vmolr |= E1000_VMOLR_STRVLAN;      /* Strip vlan tags */
3059         if (aupe)
3060                 vmolr |= E1000_VMOLR_AUPE;        /* Accept untagged packets */
3061         else
3062                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3063
3064         /* clear all bits that might not be set */
3065         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3066
3067         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3068                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3069         /*
3070          * for VMDq only allow the VFs and pool 0 to accept broadcast and
3071          * multicast packets
3072          */
3073         if (vfn <= adapter->vfs_allocated_count)
3074                 vmolr |= E1000_VMOLR_BAM;          /* Accept broadcast */
3075
3076         wr32(E1000_VMOLR(vfn), vmolr);
3077 }
3078
3079 /**
3080  * igb_configure_rx_ring - Configure a receive ring after Reset
3081  * @adapter: board private structure
3082  * @ring: receive ring to be configured
3083  *
3084  * Configure the Rx unit of the MAC after a reset.
3085  **/
3086 void igb_configure_rx_ring(struct igb_adapter *adapter,
3087                            struct igb_ring *ring)
3088 {
3089         struct e1000_hw *hw = &adapter->hw;
3090         u64 rdba = ring->dma;
3091         int reg_idx = ring->reg_idx;
3092         u32 srrctl = 0, rxdctl = 0;
3093
3094         /* disable the queue */
3095         wr32(E1000_RXDCTL(reg_idx), 0);
3096
3097         /* Set DMA base address registers */
3098         wr32(E1000_RDBAL(reg_idx),
3099              rdba & 0x00000000ffffffffULL);
3100         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3101         wr32(E1000_RDLEN(reg_idx),
3102                        ring->count * sizeof(union e1000_adv_rx_desc));
3103
3104         /* initialize head and tail */
3105         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3106         wr32(E1000_RDH(reg_idx), 0);
3107         writel(0, ring->tail);
3108
3109         /* set descriptor configuration */
3110         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3111         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3112         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3113         if (hw->mac.type >= e1000_82580)
3114                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3115         /* Only set Drop Enable if we are supporting multiple queues */
3116         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3117                 srrctl |= E1000_SRRCTL_DROP_EN;
3118
3119         wr32(E1000_SRRCTL(reg_idx), srrctl);
3120
3121         /* set filtering for VMDQ pools */
3122         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3123
3124         rxdctl |= IGB_RX_PTHRESH;
3125         rxdctl |= IGB_RX_HTHRESH << 8;
3126         rxdctl |= IGB_RX_WTHRESH << 16;
3127
3128         /* enable receive descriptor fetching */
3129         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3130         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3131 }
3132
3133 /**
3134  * igb_configure_rx - Configure receive Unit after Reset
3135  * @adapter: board private structure
3136  *
3137  * Configure the Rx unit of the MAC after a reset.
3138  **/
3139 static void igb_configure_rx(struct igb_adapter *adapter)
3140 {
3141         int i;
3142
3143         /* set UTA to appropriate mode */
3144         igb_set_uta(adapter);
3145
3146         /* set the correct pool for the PF default MAC address in entry 0 */
3147         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3148                          adapter->vfs_allocated_count);
3149
3150         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3151          * the Base and Length of the Rx Descriptor Ring */
3152         for (i = 0; i < adapter->num_rx_queues; i++)
3153                 igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3154 }
3155
3156 /**
3157  * igb_free_tx_resources - Free Tx Resources per Queue
3158  * @tx_ring: Tx descriptor ring for a specific queue
3159  *
3160  * Free all transmit software resources
3161  **/
3162 void igb_free_tx_resources(struct igb_ring *tx_ring)
3163 {
3164         igb_clean_tx_ring(tx_ring);
3165
3166         vfree(tx_ring->tx_buffer_info);
3167         tx_ring->tx_buffer_info = NULL;
3168
3169         /* if not set, then don't free */
3170         if (!tx_ring->desc)
3171                 return;
3172
3173         dma_free_coherent(tx_ring->dev, tx_ring->size,
3174                           tx_ring->desc, tx_ring->dma);
3175
3176         tx_ring->desc = NULL;
3177 }
3178
3179 /**
3180  * igb_free_all_tx_resources - Free Tx Resources for All Queues
3181  * @adapter: board private structure
3182  *
3183  * Free all transmit software resources
3184  **/
3185 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3186 {
3187         int i;
3188
3189         for (i = 0; i < adapter->num_tx_queues; i++)
3190                 igb_free_tx_resources(adapter->tx_ring[i]);
3191 }
3192
3193 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3194                                     struct igb_tx_buffer *tx_buffer)
3195 {
3196         if (tx_buffer->skb) {
3197                 dev_kfree_skb_any(tx_buffer->skb);
3198                 if (dma_unmap_len(tx_buffer, len))
3199                         dma_unmap_single(ring->dev,
3200                                          dma_unmap_addr(tx_buffer, dma),
3201                                          dma_unmap_len(tx_buffer, len),
3202                                          DMA_TO_DEVICE);
3203         } else if (dma_unmap_len(tx_buffer, len)) {
3204                 dma_unmap_page(ring->dev,
3205                                dma_unmap_addr(tx_buffer, dma),
3206                                dma_unmap_len(tx_buffer, len),
3207                                DMA_TO_DEVICE);
3208         }
3209         tx_buffer->next_to_watch = NULL;
3210         tx_buffer->skb = NULL;
3211         dma_unmap_len_set(tx_buffer, len, 0);
3212         /* buffer_info must be completely set up in the transmit path */
3213 }
3214
3215 /**
3216  * igb_clean_tx_ring - Free Tx Buffers
3217  * @tx_ring: ring to be cleaned
3218  **/
3219 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3220 {
3221         struct igb_tx_buffer *buffer_info;
3222         unsigned long size;
3223         u16 i;
3224
3225         if (!tx_ring->tx_buffer_info)
3226                 return;
3227         /* Free all the Tx ring sk_buffs */
3228
3229         for (i = 0; i < tx_ring->count; i++) {
3230                 buffer_info = &tx_ring->tx_buffer_info[i];
3231                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3232         }
3233
3234         netdev_tx_reset_queue(txring_txq(tx_ring));
3235
3236         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3237         memset(tx_ring->tx_buffer_info, 0, size);
3238
3239         /* Zero out the descriptor ring */
3240         memset(tx_ring->desc, 0, tx_ring->size);
3241
3242         tx_ring->next_to_use = 0;
3243         tx_ring->next_to_clean = 0;
3244 }
3245
3246 /**
3247  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3248  * @adapter: board private structure
3249  **/
3250 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3251 {
3252         int i;
3253
3254         for (i = 0; i < adapter->num_tx_queues; i++)
3255                 igb_clean_tx_ring(adapter->tx_ring[i]);
3256 }
3257
3258 /**
3259  * igb_free_rx_resources - Free Rx Resources
3260  * @rx_ring: ring to clean the resources from
3261  *
3262  * Free all receive software resources
3263  **/
3264 void igb_free_rx_resources(struct igb_ring *rx_ring)
3265 {
3266         igb_clean_rx_ring(rx_ring);
3267
3268         vfree(rx_ring->rx_buffer_info);
3269         rx_ring->rx_buffer_info = NULL;
3270
3271         /* if not set, then don't free */
3272         if (!rx_ring->desc)
3273                 return;
3274
3275         dma_free_coherent(rx_ring->dev, rx_ring->size,
3276                           rx_ring->desc, rx_ring->dma);
3277
3278         rx_ring->desc = NULL;
3279 }
3280
3281 /**
3282  * igb_free_all_rx_resources - Free Rx Resources for All Queues
3283  * @adapter: board private structure
3284  *
3285  * Free all receive software resources
3286  **/
3287 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3288 {
3289         int i;
3290
3291         for (i = 0; i < adapter->num_rx_queues; i++)
3292                 igb_free_rx_resources(adapter->rx_ring[i]);
3293 }
3294
3295 /**
3296  * igb_clean_rx_ring - Free Rx Buffers per Queue
3297  * @rx_ring: ring to free buffers from
3298  **/
3299 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3300 {
3301         unsigned long size;
3302         u16 i;
3303
3304         if (rx_ring->skb)
3305                 dev_kfree_skb(rx_ring->skb);
3306         rx_ring->skb = NULL;
3307
3308         if (!rx_ring->rx_buffer_info)
3309                 return;
3310
3311         /* Free all the Rx ring sk_buffs */
3312         for (i = 0; i < rx_ring->count; i++) {
3313                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3314
3315                 if (!buffer_info->page)
3316                         continue;
3317
3318                 dma_unmap_page(rx_ring->dev,
3319                                buffer_info->dma,
3320                                PAGE_SIZE,
3321                                DMA_FROM_DEVICE);
3322                 __free_page(buffer_info->page);
3323
3324                 buffer_info->page = NULL;
3325         }
3326
3327         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3328         memset(rx_ring->rx_buffer_info, 0, size);
3329
3330         /* Zero out the descriptor ring */
3331         memset(rx_ring->desc, 0, rx_ring->size);
3332
3333         rx_ring->next_to_alloc = 0;
3334         rx_ring->next_to_clean = 0;
3335         rx_ring->next_to_use = 0;
3336 }
3337
3338 /**
3339  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3340  * @adapter: board private structure
3341  **/
3342 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3343 {
3344         int i;
3345
3346         for (i = 0; i < adapter->num_rx_queues; i++)
3347                 igb_clean_rx_ring(adapter->rx_ring[i]);
3348 }
3349
3350 /**
3351  * igb_set_mac - Change the Ethernet Address of the NIC
3352  * @netdev: network interface device structure
3353  * @p: pointer to an address structure
3354  *
3355  * Returns 0 on success, negative on failure
3356  **/
3357 static int igb_set_mac(struct net_device *netdev, void *p)
3358 {
3359         struct igb_adapter *adapter = netdev_priv(netdev);
3360         struct e1000_hw *hw = &adapter->hw;
3361         struct sockaddr *addr = p;
3362
3363         if (!is_valid_ether_addr(addr->sa_data))
3364                 return -EADDRNOTAVAIL;
3365
3366         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3367         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3368
3369         /* set the correct pool for the new PF MAC address in entry 0 */
3370         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3371                          adapter->vfs_allocated_count);
3372
3373         return 0;
3374 }
3375
3376 /**
3377  * igb_write_mc_addr_list - write multicast addresses to MTA
3378  * @netdev: network interface device structure
3379  *
3380  * Writes multicast address list to the MTA hash table.
3381  * Returns: -ENOMEM on failure
3382  *                0 on no addresses written
3383  *                X on writing X addresses to MTA
3384  **/
3385 static int igb_write_mc_addr_list(struct net_device *netdev)
3386 {
3387         struct igb_adapter *adapter = netdev_priv(netdev);
3388         struct e1000_hw *hw = &adapter->hw;
3389         struct netdev_hw_addr *ha;
3390         u8  *mta_list;
3391         int i;
3392
3393         if (netdev_mc_empty(netdev)) {
3394                 /* nothing to program, so clear mc list */
3395                 igb_update_mc_addr_list(hw, NULL, 0);
3396                 igb_restore_vf_multicasts(adapter);
3397                 return 0;
3398         }
3399
3400         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3401         if (!mta_list)
3402                 return -ENOMEM;
3403
3404         /* The shared function expects a packed array of only addresses. */
3405         i = 0;
3406         netdev_for_each_mc_addr(ha, netdev)
3407                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3408
3409         igb_update_mc_addr_list(hw, mta_list, i);
3410         kfree(mta_list);
3411
3412         return netdev_mc_count(netdev);
3413 }
3414
3415 /**
3416  * igb_write_uc_addr_list - write unicast addresses to RAR table
3417  * @netdev: network interface device structure
3418  *
3419  * Writes unicast address list to the RAR table.
3420  * Returns: -ENOMEM on failure/insufficient address space
3421  *                0 on no addresses written
3422  *                X on writing X addresses to the RAR table
3423  **/
3424 static int igb_write_uc_addr_list(struct net_device *netdev)
3425 {
3426         struct igb_adapter *adapter = netdev_priv(netdev);
3427         struct e1000_hw *hw = &adapter->hw;
3428         unsigned int vfn = adapter->vfs_allocated_count;
3429         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3430         int count = 0;
3431
3432         /* return ENOMEM indicating insufficient memory for addresses */
3433         if (netdev_uc_count(netdev) > rar_entries)
3434                 return -ENOMEM;
3435
3436         if (!netdev_uc_empty(netdev) && rar_entries) {
3437                 struct netdev_hw_addr *ha;
3438
3439                 netdev_for_each_uc_addr(ha, netdev) {
3440                         if (!rar_entries)
3441                                 break;
3442                         igb_rar_set_qsel(adapter, ha->addr,
3443                                          rar_entries--,
3444                                          vfn);
3445                         count++;
3446                 }
3447         }
3448         /* write the addresses in reverse order to avoid write combining */
3449         for (; rar_entries > 0 ; rar_entries--) {
3450                 wr32(E1000_RAH(rar_entries), 0);
3451                 wr32(E1000_RAL(rar_entries), 0);
3452         }
3453         wrfl();
3454
3455         return count;
3456 }
3457
3458 /**
3459  * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3460  * @netdev: network interface device structure
3461  *
3462  * The set_rx_mode entry point is called whenever the unicast or multicast
3463  * address lists or the network interface flags are updated.  This routine is
3464  * responsible for configuring the hardware for proper unicast, multicast,
3465  * promiscuous mode, and all-multi behavior.
3466  **/
3467 static void igb_set_rx_mode(struct net_device *netdev)
3468 {
3469         struct igb_adapter *adapter = netdev_priv(netdev);
3470         struct e1000_hw *hw = &adapter->hw;
3471         unsigned int vfn = adapter->vfs_allocated_count;
3472         u32 rctl, vmolr = 0;
3473         int count;
3474
3475         /* Check for Promiscuous and All Multicast modes */
3476         rctl = rd32(E1000_RCTL);
3477
3478         /* clear the effected bits */
3479         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3480
3481         if (netdev->flags & IFF_PROMISC) {
3482                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3483                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3484         } else {
3485                 if (netdev->flags & IFF_ALLMULTI) {
3486                         rctl |= E1000_RCTL_MPE;
3487                         vmolr |= E1000_VMOLR_MPME;
3488                 } else {
3489                         /*
3490                          * Write addresses to the MTA, if the attempt fails
3491                          * then we should just turn on promiscuous mode so
3492                          * that we can at least receive multicast traffic
3493                          */
3494                         count = igb_write_mc_addr_list(netdev);
3495                         if (count < 0) {
3496                                 rctl |= E1000_RCTL_MPE;
3497                                 vmolr |= E1000_VMOLR_MPME;
3498                         } else if (count) {
3499                                 vmolr |= E1000_VMOLR_ROMPE;
3500                         }
3501                 }
3502                 /*
3503                  * Write addresses to available RAR registers, if there is not
3504                  * sufficient space to store all the addresses then enable
3505                  * unicast promiscuous mode
3506                  */
3507                 count = igb_write_uc_addr_list(netdev);
3508                 if (count < 0) {
3509                         rctl |= E1000_RCTL_UPE;
3510                         vmolr |= E1000_VMOLR_ROPE;
3511                 }
3512                 rctl |= E1000_RCTL_VFE;
3513         }
3514         wr32(E1000_RCTL, rctl);
3515
3516         /*
3517          * In order to support SR-IOV and eventually VMDq it is necessary to set
3518          * the VMOLR to enable the appropriate modes.  Without this workaround
3519          * we will have issues with VLAN tag stripping not being done for frames
3520          * that are only arriving because we are the default pool
3521          */
3522         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3523                 return;
3524
3525         vmolr |= rd32(E1000_VMOLR(vfn)) &
3526                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3527         wr32(E1000_VMOLR(vfn), vmolr);
3528         igb_restore_vf_multicasts(adapter);
3529 }
3530
3531 static void igb_check_wvbr(struct igb_adapter *adapter)
3532 {
3533         struct e1000_hw *hw = &adapter->hw;
3534         u32 wvbr = 0;
3535
3536         switch (hw->mac.type) {
3537         case e1000_82576:
3538         case e1000_i350:
3539                 if (!(wvbr = rd32(E1000_WVBR)))
3540                         return;
3541                 break;
3542         default:
3543                 break;
3544         }
3545
3546         adapter->wvbr |= wvbr;
3547 }
3548
3549 #define IGB_STAGGERED_QUEUE_OFFSET 8
3550
3551 static void igb_spoof_check(struct igb_adapter *adapter)
3552 {
3553         int j;
3554
3555         if (!adapter->wvbr)
3556                 return;
3557
3558         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3559                 if (adapter->wvbr & (1 << j) ||
3560                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3561                         dev_warn(&adapter->pdev->dev,
3562                                 "Spoof event(s) detected on VF %d\n", j);
3563                         adapter->wvbr &=
3564                                 ~((1 << j) |
3565                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3566                 }
3567         }
3568 }
3569
3570 /* Need to wait a few seconds after link up to get diagnostic information from
3571  * the phy */
3572 static void igb_update_phy_info(unsigned long data)
3573 {
3574         struct igb_adapter *adapter = (struct igb_adapter *) data;
3575         igb_get_phy_info(&adapter->hw);
3576 }
3577
3578 /**
3579  * igb_has_link - check shared code for link and determine up/down
3580  * @adapter: pointer to driver private info
3581  **/
3582 bool igb_has_link(struct igb_adapter *adapter)
3583 {
3584         struct e1000_hw *hw = &adapter->hw;
3585         bool link_active = false;
3586         s32 ret_val = 0;
3587
3588         /* get_link_status is set on LSC (link status) interrupt or
3589          * rx sequence error interrupt.  get_link_status will stay
3590          * false until the e1000_check_for_link establishes link
3591          * for copper adapters ONLY
3592          */
3593         switch (hw->phy.media_type) {
3594         case e1000_media_type_copper:
3595                 if (hw->mac.get_link_status) {
3596                         ret_val = hw->mac.ops.check_for_link(hw);
3597                         link_active = !hw->mac.get_link_status;
3598                 } else {
3599                         link_active = true;
3600                 }
3601                 break;
3602         case e1000_media_type_internal_serdes:
3603                 ret_val = hw->mac.ops.check_for_link(hw);
3604                 link_active = hw->mac.serdes_has_link;
3605                 break;
3606         default:
3607         case e1000_media_type_unknown:
3608                 break;
3609         }
3610
3611         return link_active;
3612 }
3613
3614 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3615 {
3616         bool ret = false;
3617         u32 ctrl_ext, thstat;
3618
3619         /* check for thermal sensor event on i350 copper only */
3620         if (hw->mac.type == e1000_i350) {
3621                 thstat = rd32(E1000_THSTAT);
3622                 ctrl_ext = rd32(E1000_CTRL_EXT);
3623
3624                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3625                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3626                         ret = !!(thstat & event);
3627                 }
3628         }
3629
3630         return ret;
3631 }
3632
3633 /**
3634  * igb_watchdog - Timer Call-back
3635  * @data: pointer to adapter cast into an unsigned long
3636  **/
3637 static void igb_watchdog(unsigned long data)
3638 {
3639         struct igb_adapter *adapter = (struct igb_adapter *)data;
3640         /* Do the rest outside of interrupt context */
3641         schedule_work(&adapter->watchdog_task);
3642 }
3643
3644 static void igb_watchdog_task(struct work_struct *work)
3645 {
3646         struct igb_adapter *adapter = container_of(work,
3647                                                    struct igb_adapter,
3648                                                    watchdog_task);
3649         struct e1000_hw *hw = &adapter->hw;
3650         struct net_device *netdev = adapter->netdev;
3651         u32 link;
3652         int i;
3653
3654         link = igb_has_link(adapter);
3655         if (link) {
3656                 /* Cancel scheduled suspend requests. */
3657                 pm_runtime_resume(netdev->dev.parent);
3658
3659                 if (!netif_carrier_ok(netdev)) {
3660                         u32 ctrl;
3661                         hw->mac.ops.get_speed_and_duplex(hw,
3662                                                          &adapter->link_speed,
3663                                                          &adapter->link_duplex);
3664
3665                         ctrl = rd32(E1000_CTRL);
3666                         /* Links status message must follow this format */
3667                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3668                                "Duplex, Flow Control: %s\n",
3669                                netdev->name,
3670                                adapter->link_speed,
3671                                adapter->link_duplex == FULL_DUPLEX ?
3672                                "Full" : "Half",
3673                                (ctrl & E1000_CTRL_TFCE) &&
3674                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3675                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3676                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3677
3678                         /* check for thermal sensor event */
3679                         if (igb_thermal_sensor_event(hw,
3680                             E1000_THSTAT_LINK_THROTTLE)) {
3681                                 netdev_info(netdev, "The network adapter link "
3682                                             "speed was downshifted because it "
3683                                             "overheated\n");
3684                         }
3685
3686                         /* adjust timeout factor according to speed/duplex */
3687                         adapter->tx_timeout_factor = 1;
3688                         switch (adapter->link_speed) {
3689                         case SPEED_10:
3690                                 adapter->tx_timeout_factor = 14;
3691                                 break;
3692                         case SPEED_100:
3693                                 /* maybe add some timeout factor ? */
3694                                 break;
3695                         }
3696
3697                         netif_carrier_on(netdev);
3698
3699                         igb_ping_all_vfs(adapter);
3700                         igb_check_vf_rate_limit(adapter);
3701
3702                         /* link state has changed, schedule phy info update */
3703                         if (!test_bit(__IGB_DOWN, &adapter->state))
3704                                 mod_timer(&adapter->phy_info_timer,
3705                                           round_jiffies(jiffies + 2 * HZ));
3706                 }
3707         } else {
3708                 if (netif_carrier_ok(netdev)) {
3709                         adapter->link_speed = 0;
3710                         adapter->link_duplex = 0;
3711
3712                         /* check for thermal sensor event */
3713                         if (igb_thermal_sensor_event(hw,
3714                             E1000_THSTAT_PWR_DOWN)) {
3715                                 netdev_err(netdev, "The network adapter was "
3716                                            "stopped because it overheated\n");
3717                         }
3718
3719                         /* Links status message must follow this format */
3720                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
3721                                netdev->name);
3722                         netif_carrier_off(netdev);
3723
3724                         igb_ping_all_vfs(adapter);
3725
3726                         /* link state has changed, schedule phy info update */
3727                         if (!test_bit(__IGB_DOWN, &adapter->state))
3728                                 mod_timer(&adapter->phy_info_timer,
3729                                           round_jiffies(jiffies + 2 * HZ));
3730
3731                         pm_schedule_suspend(netdev->dev.parent,
3732                                             MSEC_PER_SEC * 5);
3733                 }
3734         }
3735
3736         spin_lock(&adapter->stats64_lock);
3737         igb_update_stats(adapter, &adapter->stats64);
3738         spin_unlock(&adapter->stats64_lock);
3739
3740         for (i = 0; i < adapter->num_tx_queues; i++) {
3741                 struct igb_ring *tx_ring = adapter->tx_ring[i];
3742                 if (!netif_carrier_ok(netdev)) {
3743                         /* We've lost link, so the controller stops DMA,
3744                          * but we've got queued Tx work that's never going
3745                          * to get done, so reset controller to flush Tx.
3746                          * (Do the reset outside of interrupt context). */
3747                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3748                                 adapter->tx_timeout_count++;
3749                                 schedule_work(&adapter->reset_task);
3750                                 /* return immediately since reset is imminent */
3751                                 return;
3752                         }
3753                 }
3754
3755                 /* Force detection of hung controller every watchdog period */
3756                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3757         }
3758
3759         /* Cause software interrupt to ensure rx ring is cleaned */
3760         if (adapter->msix_entries) {
3761                 u32 eics = 0;
3762                 for (i = 0; i < adapter->num_q_vectors; i++)
3763                         eics |= adapter->q_vector[i]->eims_value;
3764                 wr32(E1000_EICS, eics);
3765         } else {
3766                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
3767         }
3768
3769         igb_spoof_check(adapter);
3770
3771         /* Reset the timer */
3772         if (!test_bit(__IGB_DOWN, &adapter->state))
3773                 mod_timer(&adapter->watchdog_timer,
3774                           round_jiffies(jiffies + 2 * HZ));
3775 }
3776
3777 enum latency_range {
3778         lowest_latency = 0,
3779         low_latency = 1,
3780         bulk_latency = 2,
3781         latency_invalid = 255
3782 };
3783
3784 /**
3785  * igb_update_ring_itr - update the dynamic ITR value based on packet size
3786  *
3787  *      Stores a new ITR value based on strictly on packet size.  This
3788  *      algorithm is less sophisticated than that used in igb_update_itr,
3789  *      due to the difficulty of synchronizing statistics across multiple
3790  *      receive rings.  The divisors and thresholds used by this function
3791  *      were determined based on theoretical maximum wire speed and testing
3792  *      data, in order to minimize response time while increasing bulk
3793  *      throughput.
3794  *      This functionality is controlled by the InterruptThrottleRate module
3795  *      parameter (see igb_param.c)
3796  *      NOTE:  This function is called only when operating in a multiqueue
3797  *             receive environment.
3798  * @q_vector: pointer to q_vector
3799  **/
3800 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3801 {
3802         int new_val = q_vector->itr_val;
3803         int avg_wire_size = 0;
3804         struct igb_adapter *adapter = q_vector->adapter;
3805         unsigned int packets;
3806
3807         /* For non-gigabit speeds, just fix the interrupt rate at 4000
3808          * ints/sec - ITR timer value of 120 ticks.
3809          */
3810         if (adapter->link_speed != SPEED_1000) {
3811                 new_val = IGB_4K_ITR;
3812                 goto set_itr_val;
3813         }
3814
3815         packets = q_vector->rx.total_packets;
3816         if (packets)
3817                 avg_wire_size = q_vector->rx.total_bytes / packets;
3818
3819         packets = q_vector->tx.total_packets;
3820         if (packets)
3821                 avg_wire_size = max_t(u32, avg_wire_size,
3822                                       q_vector->tx.total_bytes / packets);
3823
3824         /* if avg_wire_size isn't set no work was done */
3825         if (!avg_wire_size)
3826                 goto clear_counts;
3827
3828         /* Add 24 bytes to size to account for CRC, preamble, and gap */
3829         avg_wire_size += 24;
3830
3831         /* Don't starve jumbo frames */
3832         avg_wire_size = min(avg_wire_size, 3000);
3833
3834         /* Give a little boost to mid-size frames */
3835         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
3836                 new_val = avg_wire_size / 3;
3837         else
3838                 new_val = avg_wire_size / 2;
3839
3840         /* conservative mode (itr 3) eliminates the lowest_latency setting */
3841         if (new_val < IGB_20K_ITR &&
3842             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3843              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3844                 new_val = IGB_20K_ITR;
3845
3846 set_itr_val:
3847         if (new_val != q_vector->itr_val) {
3848                 q_vector->itr_val = new_val;
3849                 q_vector->set_itr = 1;
3850         }
3851 clear_counts:
3852         q_vector->rx.total_bytes = 0;
3853         q_vector->rx.total_packets = 0;
3854         q_vector->tx.total_bytes = 0;
3855         q_vector->tx.total_packets = 0;
3856 }
3857
3858 /**
3859  * igb_update_itr - update the dynamic ITR value based on statistics
3860  *      Stores a new ITR value based on packets and byte
3861  *      counts during the last interrupt.  The advantage of per interrupt
3862  *      computation is faster updates and more accurate ITR for the current
3863  *      traffic pattern.  Constants in this function were computed
3864  *      based on theoretical maximum wire speed and thresholds were set based
3865  *      on testing data as well as attempting to minimize response time
3866  *      while increasing bulk throughput.
3867  *      this functionality is controlled by the InterruptThrottleRate module
3868  *      parameter (see igb_param.c)
3869  *      NOTE:  These calculations are only valid when operating in a single-
3870  *             queue environment.
3871  * @q_vector: pointer to q_vector
3872  * @ring_container: ring info to update the itr for
3873  **/
3874 static void igb_update_itr(struct igb_q_vector *q_vector,
3875                            struct igb_ring_container *ring_container)
3876 {
3877         unsigned int packets = ring_container->total_packets;
3878         unsigned int bytes = ring_container->total_bytes;
3879         u8 itrval = ring_container->itr;
3880
3881         /* no packets, exit with status unchanged */
3882         if (packets == 0)
3883                 return;
3884
3885         switch (itrval) {
3886         case lowest_latency:
3887                 /* handle TSO and jumbo frames */
3888                 if (bytes/packets > 8000)
3889                         itrval = bulk_latency;
3890                 else if ((packets < 5) && (bytes > 512))
3891                         itrval = low_latency;
3892                 break;
3893         case low_latency:  /* 50 usec aka 20000 ints/s */
3894                 if (bytes > 10000) {
3895                         /* this if handles the TSO accounting */
3896                         if (bytes/packets > 8000) {
3897                                 itrval = bulk_latency;
3898                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
3899                                 itrval = bulk_latency;
3900                         } else if ((packets > 35)) {
3901                                 itrval = lowest_latency;
3902                         }
3903                 } else if (bytes/packets > 2000) {
3904                         itrval = bulk_latency;
3905                 } else if (packets <= 2 && bytes < 512) {
3906                         itrval = lowest_latency;
3907                 }
3908                 break;
3909         case bulk_latency: /* 250 usec aka 4000 ints/s */
3910                 if (bytes > 25000) {
3911                         if (packets > 35)
3912                                 itrval = low_latency;
3913                 } else if (bytes < 1500) {
3914                         itrval = low_latency;
3915                 }
3916                 break;
3917         }
3918
3919         /* clear work counters since we have the values we need */
3920         ring_container->total_bytes = 0;
3921         ring_container->total_packets = 0;
3922
3923         /* write updated itr to ring container */
3924         ring_container->itr = itrval;
3925 }
3926
3927 static void igb_set_itr(struct igb_q_vector *q_vector)
3928 {
3929         struct igb_adapter *adapter = q_vector->adapter;
3930         u32 new_itr = q_vector->itr_val;
3931         u8 current_itr = 0;
3932
3933         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
3934         if (adapter->link_speed != SPEED_1000) {
3935                 current_itr = 0;
3936                 new_itr = IGB_4K_ITR;
3937                 goto set_itr_now;
3938         }
3939
3940         igb_update_itr(q_vector, &q_vector->tx);
3941         igb_update_itr(q_vector, &q_vector->rx);
3942
3943         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3944
3945         /* conservative mode (itr 3) eliminates the lowest_latency setting */
3946         if (current_itr == lowest_latency &&
3947             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
3948              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3949                 current_itr = low_latency;
3950
3951         switch (current_itr) {
3952         /* counts and packets in update_itr are dependent on these numbers */
3953         case lowest_latency:
3954                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
3955                 break;
3956         case low_latency:
3957                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
3958                 break;
3959         case bulk_latency:
3960                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
3961                 break;
3962         default:
3963                 break;
3964         }
3965
3966 set_itr_now:
3967         if (new_itr != q_vector->itr_val) {
3968                 /* this attempts to bias the interrupt rate towards Bulk
3969                  * by adding intermediate steps when interrupt rate is
3970                  * increasing */
3971                 new_itr = new_itr > q_vector->itr_val ?
3972                              max((new_itr * q_vector->itr_val) /
3973                                  (new_itr + (q_vector->itr_val >> 2)),
3974                                  new_itr) :
3975                              new_itr;
3976                 /* Don't write the value here; it resets the adapter's
3977                  * internal timer, and causes us to delay far longer than
3978                  * we should between interrupts.  Instead, we write the ITR
3979                  * value at the beginning of the next interrupt so the timing
3980                  * ends up being correct.
3981                  */
3982                 q_vector->itr_val = new_itr;
3983                 q_vector->set_itr = 1;
3984         }
3985 }
3986
3987 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
3988                             u32 type_tucmd, u32 mss_l4len_idx)
3989 {
3990         struct e1000_adv_tx_context_desc *context_desc;
3991         u16 i = tx_ring->next_to_use;
3992
3993         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
3994
3995         i++;
3996         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3997
3998         /* set bits to identify this as an advanced context descriptor */
3999         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4000
4001         /* For 82575, context index must be unique per ring. */
4002         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4003                 mss_l4len_idx |= tx_ring->reg_idx << 4;
4004
4005         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4006         context_desc->seqnum_seed       = 0;
4007         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4008         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4009 }
4010
4011 static int igb_tso(struct igb_ring *tx_ring,
4012                    struct igb_tx_buffer *first,
4013                    u8 *hdr_len)
4014 {
4015         struct sk_buff *skb = first->skb;
4016         u32 vlan_macip_lens, type_tucmd;
4017         u32 mss_l4len_idx, l4len;
4018
4019         if (skb->ip_summed != CHECKSUM_PARTIAL)
4020                 return 0;
4021
4022         if (!skb_is_gso(skb))
4023                 return 0;
4024
4025         if (skb_header_cloned(skb)) {
4026                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4027                 if (err)
4028                         return err;
4029         }
4030
4031         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4032         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4033
4034         if (first->protocol == __constant_htons(ETH_P_IP)) {
4035                 struct iphdr *iph = ip_hdr(skb);
4036                 iph->tot_len = 0;
4037                 iph->check = 0;
4038                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4039                                                          iph->daddr, 0,
4040                                                          IPPROTO_TCP,
4041                                                          0);
4042                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4043                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4044                                    IGB_TX_FLAGS_CSUM |
4045                                    IGB_TX_FLAGS_IPV4;
4046         } else if (skb_is_gso_v6(skb)) {
4047                 ipv6_hdr(skb)->payload_len = 0;
4048                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4049                                                        &ipv6_hdr(skb)->daddr,
4050                                                        0, IPPROTO_TCP, 0);
4051                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4052                                    IGB_TX_FLAGS_CSUM;
4053         }
4054
4055         /* compute header lengths */
4056         l4len = tcp_hdrlen(skb);
4057         *hdr_len = skb_transport_offset(skb) + l4len;
4058
4059         /* update gso size and bytecount with header size */
4060         first->gso_segs = skb_shinfo(skb)->gso_segs;
4061         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4062
4063         /* MSS L4LEN IDX */
4064         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4065         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4066
4067         /* VLAN MACLEN IPLEN */
4068         vlan_macip_lens = skb_network_header_len(skb);
4069         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4070         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4071
4072         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4073
4074         return 1;
4075 }
4076
4077 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4078 {
4079         struct sk_buff *skb = first->skb;
4080         u32 vlan_macip_lens = 0;
4081         u32 mss_l4len_idx = 0;
4082         u32 type_tucmd = 0;
4083
4084         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4085                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4086                         return;
4087         } else {
4088                 u8 l4_hdr = 0;
4089                 switch (first->protocol) {
4090                 case __constant_htons(ETH_P_IP):
4091                         vlan_macip_lens |= skb_network_header_len(skb);
4092                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4093                         l4_hdr = ip_hdr(skb)->protocol;
4094                         break;
4095                 case __constant_htons(ETH_P_IPV6):
4096                         vlan_macip_lens |= skb_network_header_len(skb);
4097                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4098                         break;
4099                 default:
4100                         if (unlikely(net_ratelimit())) {
4101                                 dev_warn(tx_ring->dev,
4102                                  "partial checksum but proto=%x!\n",
4103                                  first->protocol);
4104                         }
4105                         break;
4106                 }
4107
4108                 switch (l4_hdr) {
4109                 case IPPROTO_TCP:
4110                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4111                         mss_l4len_idx = tcp_hdrlen(skb) <<
4112                                         E1000_ADVTXD_L4LEN_SHIFT;
4113                         break;
4114                 case IPPROTO_SCTP:
4115                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4116                         mss_l4len_idx = sizeof(struct sctphdr) <<
4117                                         E1000_ADVTXD_L4LEN_SHIFT;
4118                         break;
4119                 case IPPROTO_UDP:
4120                         mss_l4len_idx = sizeof(struct udphdr) <<
4121                                         E1000_ADVTXD_L4LEN_SHIFT;
4122                         break;
4123                 default:
4124                         if (unlikely(net_ratelimit())) {
4125                                 dev_warn(tx_ring->dev,
4126                                  "partial checksum but l4 proto=%x!\n",
4127                                  l4_hdr);
4128                         }
4129                         break;
4130                 }
4131
4132                 /* update TX checksum flag */
4133                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4134         }
4135
4136         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4137         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4138
4139         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4140 }
4141
4142 #define IGB_SET_FLAG(_input, _flag, _result) \
4143         ((_flag <= _result) ? \
4144          ((u32)(_input & _flag) * (_result / _flag)) : \
4145          ((u32)(_input & _flag) / (_flag / _result)))
4146
4147 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4148 {
4149         /* set type for advanced descriptor with frame checksum insertion */
4150         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4151                        E1000_ADVTXD_DCMD_DEXT |
4152                        E1000_ADVTXD_DCMD_IFCS;
4153
4154         /* set HW vlan bit if vlan is present */
4155         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4156                                  (E1000_ADVTXD_DCMD_VLE));
4157
4158         /* set segmentation bits for TSO */
4159         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4160                                  (E1000_ADVTXD_DCMD_TSE));
4161
4162         /* set timestamp bit if present */
4163         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4164                                  (E1000_ADVTXD_MAC_TSTAMP));
4165
4166         /* insert frame checksum */
4167         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4168
4169         return cmd_type;
4170 }
4171
4172 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4173                                  union e1000_adv_tx_desc *tx_desc,
4174                                  u32 tx_flags, unsigned int paylen)
4175 {
4176         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4177
4178         /* 82575 requires a unique index per ring */
4179         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4180                 olinfo_status |= tx_ring->reg_idx << 4;
4181
4182         /* insert L4 checksum */
4183         olinfo_status |= IGB_SET_FLAG(tx_flags,
4184                                       IGB_TX_FLAGS_CSUM,
4185                                       (E1000_TXD_POPTS_TXSM << 8));
4186
4187         /* insert IPv4 checksum */
4188         olinfo_status |= IGB_SET_FLAG(tx_flags,
4189                                       IGB_TX_FLAGS_IPV4,
4190                                       (E1000_TXD_POPTS_IXSM << 8));
4191
4192         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4193 }
4194
4195 /*
4196  * The largest size we can write to the descriptor is 65535.  In order to
4197  * maintain a power of two alignment we have to limit ourselves to 32K.
4198  */
4199 #define IGB_MAX_TXD_PWR 15
4200 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
4201
4202 static void igb_tx_map(struct igb_ring *tx_ring,
4203                        struct igb_tx_buffer *first,
4204                        const u8 hdr_len)
4205 {
4206         struct sk_buff *skb = first->skb;
4207         struct igb_tx_buffer *tx_buffer;
4208         union e1000_adv_tx_desc *tx_desc;
4209         struct skb_frag_struct *frag;
4210         dma_addr_t dma;
4211         unsigned int data_len, size;
4212         u32 tx_flags = first->tx_flags;
4213         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4214         u16 i = tx_ring->next_to_use;
4215
4216         tx_desc = IGB_TX_DESC(tx_ring, i);
4217
4218         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4219
4220         size = skb_headlen(skb);
4221         data_len = skb->data_len;
4222
4223         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4224
4225         tx_buffer = first;
4226
4227         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4228                 if (dma_mapping_error(tx_ring->dev, dma))
4229                         goto dma_error;
4230
4231                 /* record length, and DMA address */
4232                 dma_unmap_len_set(tx_buffer, len, size);
4233                 dma_unmap_addr_set(tx_buffer, dma, dma);
4234
4235                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4236
4237                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4238                         tx_desc->read.cmd_type_len =
4239                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4240
4241                         i++;
4242                         tx_desc++;
4243                         if (i == tx_ring->count) {
4244                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4245                                 i = 0;
4246                         }
4247                         tx_desc->read.olinfo_status = 0;
4248
4249                         dma += IGB_MAX_DATA_PER_TXD;
4250                         size -= IGB_MAX_DATA_PER_TXD;
4251
4252                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4253                 }
4254
4255                 if (likely(!data_len))
4256                         break;
4257
4258                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4259
4260                 i++;
4261                 tx_desc++;
4262                 if (i == tx_ring->count) {
4263                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4264                         i = 0;
4265                 }
4266                 tx_desc->read.olinfo_status = 0;
4267
4268                 size = skb_frag_size(frag);
4269                 data_len -= size;
4270
4271                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4272                                        size, DMA_TO_DEVICE);
4273
4274                 tx_buffer = &tx_ring->tx_buffer_info[i];
4275         }
4276
4277         /* write last descriptor with RS and EOP bits */
4278         cmd_type |= size | IGB_TXD_DCMD;
4279         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4280
4281         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4282
4283         /* set the timestamp */
4284         first->time_stamp = jiffies;
4285
4286         /*
4287          * Force memory writes to complete before letting h/w know there
4288          * are new descriptors to fetch.  (Only applicable for weak-ordered
4289          * memory model archs, such as IA-64).
4290          *
4291          * We also need this memory barrier to make certain all of the
4292          * status bits have been updated before next_to_watch is written.
4293          */
4294         wmb();
4295
4296         /* set next_to_watch value indicating a packet is present */
4297         first->next_to_watch = tx_desc;
4298
4299         i++;
4300         if (i == tx_ring->count)
4301                 i = 0;
4302
4303         tx_ring->next_to_use = i;
4304
4305         writel(i, tx_ring->tail);
4306
4307         /* we need this if more than one processor can write to our tail
4308          * at a time, it syncronizes IO on IA64/Altix systems */
4309         mmiowb();
4310
4311         return;
4312
4313 dma_error:
4314         dev_err(tx_ring->dev, "TX DMA map failed\n");
4315
4316         /* clear dma mappings for failed tx_buffer_info map */
4317         for (;;) {
4318                 tx_buffer = &tx_ring->tx_buffer_info[i];
4319                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4320                 if (tx_buffer == first)
4321                         break;
4322                 if (i == 0)
4323                         i = tx_ring->count;
4324                 i--;
4325         }
4326
4327         tx_ring->next_to_use = i;
4328 }
4329
4330 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4331 {
4332         struct net_device *netdev = tx_ring->netdev;
4333
4334         netif_stop_subqueue(netdev, tx_ring->queue_index);
4335
4336         /* Herbert's original patch had:
4337          *  smp_mb__after_netif_stop_queue();
4338          * but since that doesn't exist yet, just open code it. */
4339         smp_mb();
4340
4341         /* We need to check again in a case another CPU has just
4342          * made room available. */
4343         if (igb_desc_unused(tx_ring) < size)
4344                 return -EBUSY;
4345
4346         /* A reprieve! */
4347         netif_wake_subqueue(netdev, tx_ring->queue_index);
4348
4349         u64_stats_update_begin(&tx_ring->tx_syncp2);
4350         tx_ring->tx_stats.restart_queue2++;
4351         u64_stats_update_end(&tx_ring->tx_syncp2);
4352
4353         return 0;
4354 }
4355
4356 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4357 {
4358         if (igb_desc_unused(tx_ring) >= size)
4359                 return 0;
4360         return __igb_maybe_stop_tx(tx_ring, size);
4361 }
4362
4363 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4364                                 struct igb_ring *tx_ring)
4365 {
4366         struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4367         struct igb_tx_buffer *first;
4368         int tso;
4369         u32 tx_flags = 0;
4370         __be16 protocol = vlan_get_protocol(skb);
4371         u8 hdr_len = 0;
4372
4373         /* need: 1 descriptor per page,
4374          *       + 2 desc gap to keep tail from touching head,
4375          *       + 1 desc for skb->data,
4376          *       + 1 desc for context descriptor,
4377          * otherwise try next time */
4378         if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4379                 /* this is a hard error */
4380                 return NETDEV_TX_BUSY;
4381         }
4382
4383         /* record the location of the first descriptor for this packet */
4384         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4385         first->skb = skb;
4386         first->bytecount = skb->len;
4387         first->gso_segs = 1;
4388
4389         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4390                      !(adapter->ptp_tx_skb))) {
4391                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4392                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4393
4394                 adapter->ptp_tx_skb = skb_get(skb);
4395                 if (adapter->hw.mac.type == e1000_82576)
4396                         schedule_work(&adapter->ptp_tx_work);
4397         }
4398
4399         if (vlan_tx_tag_present(skb)) {
4400                 tx_flags |= IGB_TX_FLAGS_VLAN;
4401                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4402         }
4403
4404         /* record initial flags and protocol */
4405         first->tx_flags = tx_flags;
4406         first->protocol = protocol;
4407
4408         tso = igb_tso(tx_ring, first, &hdr_len);
4409         if (tso < 0)
4410                 goto out_drop;
4411         else if (!tso)
4412                 igb_tx_csum(tx_ring, first);
4413
4414         igb_tx_map(tx_ring, first, hdr_len);
4415
4416         /* Make sure there is space in the ring for the next send. */
4417         igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4418
4419         return NETDEV_TX_OK;
4420
4421 out_drop:
4422         igb_unmap_and_free_tx_resource(tx_ring, first);
4423
4424         return NETDEV_TX_OK;
4425 }
4426
4427 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4428                                                     struct sk_buff *skb)
4429 {
4430         unsigned int r_idx = skb->queue_mapping;
4431
4432         if (r_idx >= adapter->num_tx_queues)
4433                 r_idx = r_idx % adapter->num_tx_queues;
4434
4435         return adapter->tx_ring[r_idx];
4436 }
4437
4438 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4439                                   struct net_device *netdev)
4440 {
4441         struct igb_adapter *adapter = netdev_priv(netdev);
4442
4443         if (test_bit(__IGB_DOWN, &adapter->state)) {
4444                 dev_kfree_skb_any(skb);
4445                 return NETDEV_TX_OK;
4446         }
4447
4448         if (skb->len <= 0) {
4449                 dev_kfree_skb_any(skb);
4450                 return NETDEV_TX_OK;
4451         }
4452
4453         /*
4454          * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4455          * in order to meet this minimum size requirement.
4456          */
4457         if (unlikely(skb->len < 17)) {
4458                 if (skb_pad(skb, 17 - skb->len))
4459                         return NETDEV_TX_OK;
4460                 skb->len = 17;
4461                 skb_set_tail_pointer(skb, 17);
4462         }
4463
4464         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4465 }
4466
4467 /**
4468  * igb_tx_timeout - Respond to a Tx Hang
4469  * @netdev: network interface device structure
4470  **/
4471 static void igb_tx_timeout(struct net_device *netdev)
4472 {
4473         struct igb_adapter *adapter = netdev_priv(netdev);
4474         struct e1000_hw *hw = &adapter->hw;
4475
4476         /* Do the reset outside of interrupt context */
4477         adapter->tx_timeout_count++;
4478
4479         if (hw->mac.type >= e1000_82580)
4480                 hw->dev_spec._82575.global_device_reset = true;
4481
4482         schedule_work(&adapter->reset_task);
4483         wr32(E1000_EICS,
4484              (adapter->eims_enable_mask & ~adapter->eims_other));
4485 }
4486
4487 static void igb_reset_task(struct work_struct *work)
4488 {
4489         struct igb_adapter *adapter;
4490         adapter = container_of(work, struct igb_adapter, reset_task);
4491
4492         igb_dump(adapter);
4493         netdev_err(adapter->netdev, "Reset adapter\n");
4494         igb_reinit_locked(adapter);
4495 }
4496
4497 /**
4498  * igb_get_stats64 - Get System Network Statistics
4499  * @netdev: network interface device structure
4500  * @stats: rtnl_link_stats64 pointer
4501  *
4502  **/
4503 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4504                                                  struct rtnl_link_stats64 *stats)
4505 {
4506         struct igb_adapter *adapter = netdev_priv(netdev);
4507
4508         spin_lock(&adapter->stats64_lock);
4509         igb_update_stats(adapter, &adapter->stats64);
4510         memcpy(stats, &adapter->stats64, sizeof(*stats));
4511         spin_unlock(&adapter->stats64_lock);
4512
4513         return stats;
4514 }
4515
4516 /**
4517  * igb_change_mtu - Change the Maximum Transfer Unit
4518  * @netdev: network interface device structure
4519  * @new_mtu: new value for maximum frame size
4520  *
4521  * Returns 0 on success, negative on failure
4522  **/
4523 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4524 {
4525         struct igb_adapter *adapter = netdev_priv(netdev);
4526         struct pci_dev *pdev = adapter->pdev;
4527         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4528
4529         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4530                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4531                 return -EINVAL;
4532         }
4533
4534 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4535         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4536                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4537                 return -EINVAL;
4538         }
4539
4540         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4541                 msleep(1);
4542
4543         /* igb_down has a dependency on max_frame_size */
4544         adapter->max_frame_size = max_frame;
4545
4546         if (netif_running(netdev))
4547                 igb_down(adapter);
4548
4549         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4550                  netdev->mtu, new_mtu);
4551         netdev->mtu = new_mtu;
4552
4553         if (netif_running(netdev))
4554                 igb_up(adapter);
4555         else
4556                 igb_reset(adapter);
4557
4558         clear_bit(__IGB_RESETTING, &adapter->state);
4559
4560         return 0;
4561 }
4562
4563 /**
4564  * igb_update_stats - Update the board statistics counters
4565  * @adapter: board private structure
4566  **/
4567
4568 void igb_update_stats(struct igb_adapter *adapter,
4569                       struct rtnl_link_stats64 *net_stats)
4570 {
4571         struct e1000_hw *hw = &adapter->hw;
4572         struct pci_dev *pdev = adapter->pdev;
4573         u32 reg, mpc;
4574         u16 phy_tmp;
4575         int i;
4576         u64 bytes, packets;
4577         unsigned int start;
4578         u64 _bytes, _packets;
4579
4580 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4581
4582         /*
4583          * Prevent stats update while adapter is being reset, or if the pci
4584          * connection is down.
4585          */
4586         if (adapter->link_speed == 0)
4587                 return;
4588         if (pci_channel_offline(pdev))
4589                 return;
4590
4591         bytes = 0;
4592         packets = 0;
4593         for (i = 0; i < adapter->num_rx_queues; i++) {
4594                 u32 rqdpc = rd32(E1000_RQDPC(i));
4595                 struct igb_ring *ring = adapter->rx_ring[i];
4596
4597                 if (rqdpc) {
4598                         ring->rx_stats.drops += rqdpc;
4599                         net_stats->rx_fifo_errors += rqdpc;
4600                 }
4601
4602                 do {
4603                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4604                         _bytes = ring->rx_stats.bytes;
4605                         _packets = ring->rx_stats.packets;
4606                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4607                 bytes += _bytes;
4608                 packets += _packets;
4609         }
4610
4611         net_stats->rx_bytes = bytes;
4612         net_stats->rx_packets = packets;
4613
4614         bytes = 0;
4615         packets = 0;
4616         for (i = 0; i < adapter->num_tx_queues; i++) {
4617                 struct igb_ring *ring = adapter->tx_ring[i];
4618                 do {
4619                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4620                         _bytes = ring->tx_stats.bytes;
4621                         _packets = ring->tx_stats.packets;
4622                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4623                 bytes += _bytes;
4624                 packets += _packets;
4625         }
4626         net_stats->tx_bytes = bytes;
4627         net_stats->tx_packets = packets;
4628
4629         /* read stats registers */
4630         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4631         adapter->stats.gprc += rd32(E1000_GPRC);
4632         adapter->stats.gorc += rd32(E1000_GORCL);
4633         rd32(E1000_GORCH); /* clear GORCL */
4634         adapter->stats.bprc += rd32(E1000_BPRC);
4635         adapter->stats.mprc += rd32(E1000_MPRC);
4636         adapter->stats.roc += rd32(E1000_ROC);
4637
4638         adapter->stats.prc64 += rd32(E1000_PRC64);
4639         adapter->stats.prc127 += rd32(E1000_PRC127);
4640         adapter->stats.prc255 += rd32(E1000_PRC255);
4641         adapter->stats.prc511 += rd32(E1000_PRC511);
4642         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4643         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4644         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4645         adapter->stats.sec += rd32(E1000_SEC);
4646
4647         mpc = rd32(E1000_MPC);
4648         adapter->stats.mpc += mpc;
4649         net_stats->rx_fifo_errors += mpc;
4650         adapter->stats.scc += rd32(E1000_SCC);
4651         adapter->stats.ecol += rd32(E1000_ECOL);
4652         adapter->stats.mcc += rd32(E1000_MCC);
4653         adapter->stats.latecol += rd32(E1000_LATECOL);
4654         adapter->stats.dc += rd32(E1000_DC);
4655         adapter->stats.rlec += rd32(E1000_RLEC);
4656         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4657         adapter->stats.xontxc += rd32(E1000_XONTXC);
4658         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4659         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4660         adapter->stats.fcruc += rd32(E1000_FCRUC);
4661         adapter->stats.gptc += rd32(E1000_GPTC);
4662         adapter->stats.gotc += rd32(E1000_GOTCL);
4663         rd32(E1000_GOTCH); /* clear GOTCL */
4664         adapter->stats.rnbc += rd32(E1000_RNBC);
4665         adapter->stats.ruc += rd32(E1000_RUC);
4666         adapter->stats.rfc += rd32(E1000_RFC);
4667         adapter->stats.rjc += rd32(E1000_RJC);
4668         adapter->stats.tor += rd32(E1000_TORH);
4669         adapter->stats.tot += rd32(E1000_TOTH);
4670         adapter->stats.tpr += rd32(E1000_TPR);
4671
4672         adapter->stats.ptc64 += rd32(E1000_PTC64);
4673         adapter->stats.ptc127 += rd32(E1000_PTC127);
4674         adapter->stats.ptc255 += rd32(E1000_PTC255);
4675         adapter->stats.ptc511 += rd32(E1000_PTC511);
4676         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4677         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4678
4679         adapter->stats.mptc += rd32(E1000_MPTC);
4680         adapter->stats.bptc += rd32(E1000_BPTC);
4681
4682         adapter->stats.tpt += rd32(E1000_TPT);
4683         adapter->stats.colc += rd32(E1000_COLC);
4684
4685         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4686         /* read internal phy specific stats */
4687         reg = rd32(E1000_CTRL_EXT);
4688         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4689                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4690
4691                 /* this stat has invalid values on i210/i211 */
4692                 if ((hw->mac.type != e1000_i210) &&
4693                     (hw->mac.type != e1000_i211))
4694                         adapter->stats.tncrs += rd32(E1000_TNCRS);
4695         }
4696
4697         adapter->stats.tsctc += rd32(E1000_TSCTC);
4698         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4699
4700         adapter->stats.iac += rd32(E1000_IAC);
4701         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4702         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4703         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4704         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4705         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4706         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4707         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4708         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4709
4710         /* Fill out the OS statistics structure */
4711         net_stats->multicast = adapter->stats.mprc;
4712         net_stats->collisions = adapter->stats.colc;
4713
4714         /* Rx Errors */
4715
4716         /* RLEC on some newer hardware can be incorrect so build
4717          * our own version based on RUC and ROC */
4718         net_stats->rx_errors = adapter->stats.rxerrc +
4719                 adapter->stats.crcerrs + adapter->stats.algnerrc +
4720                 adapter->stats.ruc + adapter->stats.roc +
4721                 adapter->stats.cexterr;
4722         net_stats->rx_length_errors = adapter->stats.ruc +
4723                                       adapter->stats.roc;
4724         net_stats->rx_crc_errors = adapter->stats.crcerrs;
4725         net_stats->rx_frame_errors = adapter->stats.algnerrc;
4726         net_stats->rx_missed_errors = adapter->stats.mpc;
4727
4728         /* Tx Errors */
4729         net_stats->tx_errors = adapter->stats.ecol +
4730                                adapter->stats.latecol;
4731         net_stats->tx_aborted_errors = adapter->stats.ecol;
4732         net_stats->tx_window_errors = adapter->stats.latecol;
4733         net_stats->tx_carrier_errors = adapter->stats.tncrs;
4734
4735         /* Tx Dropped needs to be maintained elsewhere */
4736
4737         /* Phy Stats */
4738         if (hw->phy.media_type == e1000_media_type_copper) {
4739                 if ((adapter->link_speed == SPEED_1000) &&
4740                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4741                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4742                         adapter->phy_stats.idle_errors += phy_tmp;
4743                 }
4744         }
4745
4746         /* Management Stats */
4747         adapter->stats.mgptc += rd32(E1000_MGTPTC);
4748         adapter->stats.mgprc += rd32(E1000_MGTPRC);
4749         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4750
4751         /* OS2BMC Stats */
4752         reg = rd32(E1000_MANC);
4753         if (reg & E1000_MANC_EN_BMC2OS) {
4754                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
4755                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
4756                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
4757                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
4758         }
4759 }
4760
4761 static irqreturn_t igb_msix_other(int irq, void *data)
4762 {
4763         struct igb_adapter *adapter = data;
4764         struct e1000_hw *hw = &adapter->hw;
4765         u32 icr = rd32(E1000_ICR);
4766         /* reading ICR causes bit 31 of EICR to be cleared */
4767
4768         if (icr & E1000_ICR_DRSTA)
4769                 schedule_work(&adapter->reset_task);
4770
4771         if (icr & E1000_ICR_DOUTSYNC) {
4772                 /* HW is reporting DMA is out of sync */
4773                 adapter->stats.doosync++;
4774                 /* The DMA Out of Sync is also indication of a spoof event
4775                  * in IOV mode. Check the Wrong VM Behavior register to
4776                  * see if it is really a spoof event. */
4777                 igb_check_wvbr(adapter);
4778         }
4779
4780         /* Check for a mailbox event */
4781         if (icr & E1000_ICR_VMMB)
4782                 igb_msg_task(adapter);
4783
4784         if (icr & E1000_ICR_LSC) {
4785                 hw->mac.get_link_status = 1;
4786                 /* guard against interrupt when we're going down */
4787                 if (!test_bit(__IGB_DOWN, &adapter->state))
4788                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4789         }
4790
4791         if (icr & E1000_ICR_TS) {
4792                 u32 tsicr = rd32(E1000_TSICR);
4793
4794                 if (tsicr & E1000_TSICR_TXTS) {
4795                         /* acknowledge the interrupt */
4796                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
4797                         /* retrieve hardware timestamp */
4798                         schedule_work(&adapter->ptp_tx_work);
4799                 }
4800         }
4801
4802         wr32(E1000_EIMS, adapter->eims_other);
4803
4804         return IRQ_HANDLED;
4805 }
4806
4807 static void igb_write_itr(struct igb_q_vector *q_vector)
4808 {
4809         struct igb_adapter *adapter = q_vector->adapter;
4810         u32 itr_val = q_vector->itr_val & 0x7FFC;
4811
4812         if (!q_vector->set_itr)
4813                 return;
4814
4815         if (!itr_val)
4816                 itr_val = 0x4;
4817
4818         if (adapter->hw.mac.type == e1000_82575)
4819                 itr_val |= itr_val << 16;
4820         else
4821                 itr_val |= E1000_EITR_CNT_IGNR;
4822
4823         writel(itr_val, q_vector->itr_register);
4824         q_vector->set_itr = 0;
4825 }
4826
4827 static irqreturn_t igb_msix_ring(int irq, void *data)
4828 {
4829         struct igb_q_vector *q_vector = data;
4830
4831         /* Write the ITR value calculated from the previous interrupt. */
4832         igb_write_itr(q_vector);
4833
4834         napi_schedule(&q_vector->napi);
4835
4836         return IRQ_HANDLED;
4837 }
4838
4839 #ifdef CONFIG_IGB_DCA
4840 static void igb_update_tx_dca(struct igb_adapter *adapter,
4841                               struct igb_ring *tx_ring,
4842                               int cpu)
4843 {
4844         struct e1000_hw *hw = &adapter->hw;
4845         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
4846
4847         if (hw->mac.type != e1000_82575)
4848                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
4849
4850         /*
4851          * We can enable relaxed ordering for reads, but not writes when
4852          * DCA is enabled.  This is due to a known issue in some chipsets
4853          * which will cause the DCA tag to be cleared.
4854          */
4855         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
4856                   E1000_DCA_TXCTRL_DATA_RRO_EN |
4857                   E1000_DCA_TXCTRL_DESC_DCA_EN;
4858
4859         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
4860 }
4861
4862 static void igb_update_rx_dca(struct igb_adapter *adapter,
4863                               struct igb_ring *rx_ring,
4864                               int cpu)
4865 {
4866         struct e1000_hw *hw = &adapter->hw;
4867         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
4868
4869         if (hw->mac.type != e1000_82575)
4870                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
4871
4872         /*
4873          * We can enable relaxed ordering for reads, but not writes when
4874          * DCA is enabled.  This is due to a known issue in some chipsets
4875          * which will cause the DCA tag to be cleared.
4876          */
4877         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
4878                   E1000_DCA_RXCTRL_DESC_DCA_EN;
4879
4880         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
4881 }
4882
4883 static void igb_update_dca(struct igb_q_vector *q_vector)
4884 {
4885         struct igb_adapter *adapter = q_vector->adapter;
4886         int cpu = get_cpu();
4887
4888         if (q_vector->cpu == cpu)
4889                 goto out_no_update;
4890
4891         if (q_vector->tx.ring)
4892                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
4893
4894         if (q_vector->rx.ring)
4895                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
4896
4897         q_vector->cpu = cpu;
4898 out_no_update:
4899         put_cpu();
4900 }
4901
4902 static void igb_setup_dca(struct igb_adapter *adapter)
4903 {
4904         struct e1000_hw *hw = &adapter->hw;
4905         int i;
4906
4907         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
4908                 return;
4909
4910         /* Always use CB2 mode, difference is masked in the CB driver. */
4911         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
4912
4913         for (i = 0; i < adapter->num_q_vectors; i++) {
4914                 adapter->q_vector[i]->cpu = -1;
4915                 igb_update_dca(adapter->q_vector[i]);
4916         }
4917 }
4918
4919 static int __igb_notify_dca(struct device *dev, void *data)
4920 {
4921         struct net_device *netdev = dev_get_drvdata(dev);
4922         struct igb_adapter *adapter = netdev_priv(netdev);
4923         struct pci_dev *pdev = adapter->pdev;
4924         struct e1000_hw *hw = &adapter->hw;
4925         unsigned long event = *(unsigned long *)data;
4926
4927         switch (event) {
4928         case DCA_PROVIDER_ADD:
4929                 /* if already enabled, don't do it again */
4930                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
4931                         break;
4932                 if (dca_add_requester(dev) == 0) {
4933                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
4934                         dev_info(&pdev->dev, "DCA enabled\n");
4935                         igb_setup_dca(adapter);
4936                         break;
4937                 }
4938                 /* Fall Through since DCA is disabled. */
4939         case DCA_PROVIDER_REMOVE:
4940                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
4941                         /* without this a class_device is left
4942                          * hanging around in the sysfs model */
4943                         dca_remove_requester(dev);
4944                         dev_info(&pdev->dev, "DCA disabled\n");
4945                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
4946                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
4947                 }
4948                 break;
4949         }
4950
4951         return 0;
4952 }
4953
4954 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
4955                           void *p)
4956 {
4957         int ret_val;
4958
4959         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
4960                                          __igb_notify_dca);
4961
4962         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4963 }
4964 #endif /* CONFIG_IGB_DCA */
4965
4966 #ifdef CONFIG_PCI_IOV
4967 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
4968 {
4969         unsigned char mac_addr[ETH_ALEN];
4970
4971         eth_random_addr(mac_addr);
4972         igb_set_vf_mac(adapter, vf, mac_addr);
4973
4974         return 0;
4975 }
4976
4977 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
4978 {
4979         struct pci_dev *pdev = adapter->pdev;
4980         struct pci_dev *vfdev;
4981         int dev_id;
4982
4983         switch (adapter->hw.mac.type) {
4984         case e1000_82576:
4985                 dev_id = IGB_82576_VF_DEV_ID;
4986                 break;
4987         case e1000_i350:
4988                 dev_id = IGB_I350_VF_DEV_ID;
4989                 break;
4990         default:
4991                 return false;
4992         }
4993
4994         /* loop through all the VFs to see if we own any that are assigned */
4995         vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
4996         while (vfdev) {
4997                 /* if we don't own it we don't care */
4998                 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
4999                         /* if it is assigned we cannot release it */
5000                         if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
5001                                 return true;
5002                 }
5003
5004                 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
5005         }
5006
5007         return false;
5008 }
5009
5010 #endif
5011 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5012 {
5013         struct e1000_hw *hw = &adapter->hw;
5014         u32 ping;
5015         int i;
5016
5017         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5018                 ping = E1000_PF_CONTROL_MSG;
5019                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5020                         ping |= E1000_VT_MSGTYPE_CTS;
5021                 igb_write_mbx(hw, &ping, 1, i);
5022         }
5023 }
5024
5025 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5026 {
5027         struct e1000_hw *hw = &adapter->hw;
5028         u32 vmolr = rd32(E1000_VMOLR(vf));
5029         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5030
5031         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5032                             IGB_VF_FLAG_MULTI_PROMISC);
5033         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5034
5035         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5036                 vmolr |= E1000_VMOLR_MPME;
5037                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5038                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5039         } else {
5040                 /*
5041                  * if we have hashes and we are clearing a multicast promisc
5042                  * flag we need to write the hashes to the MTA as this step
5043                  * was previously skipped
5044                  */
5045                 if (vf_data->num_vf_mc_hashes > 30) {
5046                         vmolr |= E1000_VMOLR_MPME;
5047                 } else if (vf_data->num_vf_mc_hashes) {
5048                         int j;
5049                         vmolr |= E1000_VMOLR_ROMPE;
5050                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5051                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5052                 }
5053         }
5054
5055         wr32(E1000_VMOLR(vf), vmolr);
5056
5057         /* there are flags left unprocessed, likely not supported */
5058         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5059                 return -EINVAL;
5060
5061         return 0;
5062
5063 }
5064
5065 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5066                                   u32 *msgbuf, u32 vf)
5067 {
5068         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5069         u16 *hash_list = (u16 *)&msgbuf[1];
5070         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5071         int i;
5072
5073         /* salt away the number of multicast addresses assigned
5074          * to this VF for later use to restore when the PF multi cast
5075          * list changes
5076          */
5077         vf_data->num_vf_mc_hashes = n;
5078
5079         /* only up to 30 hash values supported */
5080         if (n > 30)
5081                 n = 30;
5082
5083         /* store the hashes for later use */
5084         for (i = 0; i < n; i++)
5085                 vf_data->vf_mc_hashes[i] = hash_list[i];
5086
5087         /* Flush and reset the mta with the new values */
5088         igb_set_rx_mode(adapter->netdev);
5089
5090         return 0;
5091 }
5092
5093 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5094 {
5095         struct e1000_hw *hw = &adapter->hw;
5096         struct vf_data_storage *vf_data;
5097         int i, j;
5098
5099         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5100                 u32 vmolr = rd32(E1000_VMOLR(i));
5101                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5102
5103                 vf_data = &adapter->vf_data[i];
5104
5105                 if ((vf_data->num_vf_mc_hashes > 30) ||
5106                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5107                         vmolr |= E1000_VMOLR_MPME;
5108                 } else if (vf_data->num_vf_mc_hashes) {
5109                         vmolr |= E1000_VMOLR_ROMPE;
5110                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5111                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5112                 }
5113                 wr32(E1000_VMOLR(i), vmolr);
5114         }
5115 }
5116
5117 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5118 {
5119         struct e1000_hw *hw = &adapter->hw;
5120         u32 pool_mask, reg, vid;
5121         int i;
5122
5123         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5124
5125         /* Find the vlan filter for this id */
5126         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5127                 reg = rd32(E1000_VLVF(i));
5128
5129                 /* remove the vf from the pool */
5130                 reg &= ~pool_mask;
5131
5132                 /* if pool is empty then remove entry from vfta */
5133                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5134                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5135                         reg = 0;
5136                         vid = reg & E1000_VLVF_VLANID_MASK;
5137                         igb_vfta_set(hw, vid, false);
5138                 }
5139
5140                 wr32(E1000_VLVF(i), reg);
5141         }
5142
5143         adapter->vf_data[vf].vlans_enabled = 0;
5144 }
5145
5146 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5147 {
5148         struct e1000_hw *hw = &adapter->hw;
5149         u32 reg, i;
5150
5151         /* The vlvf table only exists on 82576 hardware and newer */
5152         if (hw->mac.type < e1000_82576)
5153                 return -1;
5154
5155         /* we only need to do this if VMDq is enabled */
5156         if (!adapter->vfs_allocated_count)
5157                 return -1;
5158
5159         /* Find the vlan filter for this id */
5160         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5161                 reg = rd32(E1000_VLVF(i));
5162                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5163                     vid == (reg & E1000_VLVF_VLANID_MASK))
5164                         break;
5165         }
5166
5167         if (add) {
5168                 if (i == E1000_VLVF_ARRAY_SIZE) {
5169                         /* Did not find a matching VLAN ID entry that was
5170                          * enabled.  Search for a free filter entry, i.e.
5171                          * one without the enable bit set
5172                          */
5173                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5174                                 reg = rd32(E1000_VLVF(i));
5175                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5176                                         break;
5177                         }
5178                 }
5179                 if (i < E1000_VLVF_ARRAY_SIZE) {
5180                         /* Found an enabled/available entry */
5181                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5182
5183                         /* if !enabled we need to set this up in vfta */
5184                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5185                                 /* add VID to filter table */
5186                                 igb_vfta_set(hw, vid, true);
5187                                 reg |= E1000_VLVF_VLANID_ENABLE;
5188                         }
5189                         reg &= ~E1000_VLVF_VLANID_MASK;
5190                         reg |= vid;
5191                         wr32(E1000_VLVF(i), reg);
5192
5193                         /* do not modify RLPML for PF devices */
5194                         if (vf >= adapter->vfs_allocated_count)
5195                                 return 0;
5196
5197                         if (!adapter->vf_data[vf].vlans_enabled) {
5198                                 u32 size;
5199                                 reg = rd32(E1000_VMOLR(vf));
5200                                 size = reg & E1000_VMOLR_RLPML_MASK;
5201                                 size += 4;
5202                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5203                                 reg |= size;
5204                                 wr32(E1000_VMOLR(vf), reg);
5205                         }
5206
5207                         adapter->vf_data[vf].vlans_enabled++;
5208                 }
5209         } else {
5210                 if (i < E1000_VLVF_ARRAY_SIZE) {
5211                         /* remove vf from the pool */
5212                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5213                         /* if pool is empty then remove entry from vfta */
5214                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5215                                 reg = 0;
5216                                 igb_vfta_set(hw, vid, false);
5217                         }
5218                         wr32(E1000_VLVF(i), reg);
5219
5220                         /* do not modify RLPML for PF devices */
5221                         if (vf >= adapter->vfs_allocated_count)
5222                                 return 0;
5223
5224                         adapter->vf_data[vf].vlans_enabled--;
5225                         if (!adapter->vf_data[vf].vlans_enabled) {
5226                                 u32 size;
5227                                 reg = rd32(E1000_VMOLR(vf));
5228                                 size = reg & E1000_VMOLR_RLPML_MASK;
5229                                 size -= 4;
5230                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5231                                 reg |= size;
5232                                 wr32(E1000_VMOLR(vf), reg);
5233                         }
5234                 }
5235         }
5236         return 0;
5237 }
5238
5239 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5240 {
5241         struct e1000_hw *hw = &adapter->hw;
5242
5243         if (vid)
5244                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5245         else
5246                 wr32(E1000_VMVIR(vf), 0);
5247 }
5248
5249 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5250                                int vf, u16 vlan, u8 qos)
5251 {
5252         int err = 0;
5253         struct igb_adapter *adapter = netdev_priv(netdev);
5254
5255         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5256                 return -EINVAL;
5257         if (vlan || qos) {
5258                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5259                 if (err)
5260                         goto out;
5261                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5262                 igb_set_vmolr(adapter, vf, !vlan);
5263                 adapter->vf_data[vf].pf_vlan = vlan;
5264                 adapter->vf_data[vf].pf_qos = qos;
5265                 dev_info(&adapter->pdev->dev,
5266                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5267                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5268                         dev_warn(&adapter->pdev->dev,
5269                                  "The VF VLAN has been set,"
5270                                  " but the PF device is not up.\n");
5271                         dev_warn(&adapter->pdev->dev,
5272                                  "Bring the PF device up before"
5273                                  " attempting to use the VF device.\n");
5274                 }
5275         } else {
5276                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5277                                    false, vf);
5278                 igb_set_vmvir(adapter, vlan, vf);
5279                 igb_set_vmolr(adapter, vf, true);
5280                 adapter->vf_data[vf].pf_vlan = 0;
5281                 adapter->vf_data[vf].pf_qos = 0;
5282        }
5283 out:
5284        return err;
5285 }
5286
5287 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5288 {
5289         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5290         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5291
5292         return igb_vlvf_set(adapter, vid, add, vf);
5293 }
5294
5295 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5296 {
5297         /* clear flags - except flag that indicates PF has set the MAC */
5298         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5299         adapter->vf_data[vf].last_nack = jiffies;
5300
5301         /* reset offloads to defaults */
5302         igb_set_vmolr(adapter, vf, true);
5303
5304         /* reset vlans for device */
5305         igb_clear_vf_vfta(adapter, vf);
5306         if (adapter->vf_data[vf].pf_vlan)
5307                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5308                                     adapter->vf_data[vf].pf_vlan,
5309                                     adapter->vf_data[vf].pf_qos);
5310         else
5311                 igb_clear_vf_vfta(adapter, vf);
5312
5313         /* reset multicast table array for vf */
5314         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5315
5316         /* Flush and reset the mta with the new values */
5317         igb_set_rx_mode(adapter->netdev);
5318 }
5319
5320 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5321 {
5322         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5323
5324         /* generate a new mac address as we were hotplug removed/added */
5325         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5326                 eth_random_addr(vf_mac);
5327
5328         /* process remaining reset events */
5329         igb_vf_reset(adapter, vf);
5330 }
5331
5332 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5333 {
5334         struct e1000_hw *hw = &adapter->hw;
5335         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5336         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5337         u32 reg, msgbuf[3];
5338         u8 *addr = (u8 *)(&msgbuf[1]);
5339
5340         /* process all the same items cleared in a function level reset */
5341         igb_vf_reset(adapter, vf);
5342
5343         /* set vf mac address */
5344         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5345
5346         /* enable transmit and receive for vf */
5347         reg = rd32(E1000_VFTE);
5348         wr32(E1000_VFTE, reg | (1 << vf));
5349         reg = rd32(E1000_VFRE);
5350         wr32(E1000_VFRE, reg | (1 << vf));
5351
5352         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5353
5354         /* reply to reset with ack and vf mac address */
5355         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5356         memcpy(addr, vf_mac, 6);
5357         igb_write_mbx(hw, msgbuf, 3, vf);
5358 }
5359
5360 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5361 {
5362         /*
5363          * The VF MAC Address is stored in a packed array of bytes
5364          * starting at the second 32 bit word of the msg array
5365          */
5366         unsigned char *addr = (char *)&msg[1];
5367         int err = -1;
5368
5369         if (is_valid_ether_addr(addr))
5370                 err = igb_set_vf_mac(adapter, vf, addr);
5371
5372         return err;
5373 }
5374
5375 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5376 {
5377         struct e1000_hw *hw = &adapter->hw;
5378         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5379         u32 msg = E1000_VT_MSGTYPE_NACK;
5380
5381         /* if device isn't clear to send it shouldn't be reading either */
5382         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5383             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5384                 igb_write_mbx(hw, &msg, 1, vf);
5385                 vf_data->last_nack = jiffies;
5386         }
5387 }
5388
5389 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5390 {
5391         struct pci_dev *pdev = adapter->pdev;
5392         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5393         struct e1000_hw *hw = &adapter->hw;
5394         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5395         s32 retval;
5396
5397         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5398
5399         if (retval) {
5400                 /* if receive failed revoke VF CTS stats and restart init */
5401                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5402                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5403                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5404                         return;
5405                 goto out;
5406         }
5407
5408         /* this is a message we already processed, do nothing */
5409         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5410                 return;
5411
5412         /*
5413          * until the vf completes a reset it should not be
5414          * allowed to start any configuration.
5415          */
5416
5417         if (msgbuf[0] == E1000_VF_RESET) {
5418                 igb_vf_reset_msg(adapter, vf);
5419                 return;
5420         }
5421
5422         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5423                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5424                         return;
5425                 retval = -1;
5426                 goto out;
5427         }
5428
5429         switch ((msgbuf[0] & 0xFFFF)) {
5430         case E1000_VF_SET_MAC_ADDR:
5431                 retval = -EINVAL;
5432                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5433                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5434                 else
5435                         dev_warn(&pdev->dev,
5436                                  "VF %d attempted to override administratively "
5437                                  "set MAC address\nReload the VF driver to "
5438                                  "resume operations\n", vf);
5439                 break;
5440         case E1000_VF_SET_PROMISC:
5441                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5442                 break;
5443         case E1000_VF_SET_MULTICAST:
5444                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5445                 break;
5446         case E1000_VF_SET_LPE:
5447                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5448                 break;
5449         case E1000_VF_SET_VLAN:
5450                 retval = -1;
5451                 if (vf_data->pf_vlan)
5452                         dev_warn(&pdev->dev,
5453                                  "VF %d attempted to override administratively "
5454                                  "set VLAN tag\nReload the VF driver to "
5455                                  "resume operations\n", vf);
5456                 else
5457                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5458                 break;
5459         default:
5460                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5461                 retval = -1;
5462                 break;
5463         }
5464
5465         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5466 out:
5467         /* notify the VF of the results of what it sent us */
5468         if (retval)
5469                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5470         else
5471                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5472
5473         igb_write_mbx(hw, msgbuf, 1, vf);
5474 }
5475
5476 static void igb_msg_task(struct igb_adapter *adapter)
5477 {
5478         struct e1000_hw *hw = &adapter->hw;
5479         u32 vf;
5480
5481         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5482                 /* process any reset requests */
5483                 if (!igb_check_for_rst(hw, vf))
5484                         igb_vf_reset_event(adapter, vf);
5485
5486                 /* process any messages pending */
5487                 if (!igb_check_for_msg(hw, vf))
5488                         igb_rcv_msg_from_vf(adapter, vf);
5489
5490                 /* process any acks */
5491                 if (!igb_check_for_ack(hw, vf))
5492                         igb_rcv_ack_from_vf(adapter, vf);
5493         }
5494 }
5495
5496 /**
5497  *  igb_set_uta - Set unicast filter table address
5498  *  @adapter: board private structure
5499  *
5500  *  The unicast table address is a register array of 32-bit registers.
5501  *  The table is meant to be used in a way similar to how the MTA is used
5502  *  however due to certain limitations in the hardware it is necessary to
5503  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5504  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5505  **/
5506 static void igb_set_uta(struct igb_adapter *adapter)
5507 {
5508         struct e1000_hw *hw = &adapter->hw;
5509         int i;
5510
5511         /* The UTA table only exists on 82576 hardware and newer */
5512         if (hw->mac.type < e1000_82576)
5513                 return;
5514
5515         /* we only need to do this if VMDq is enabled */
5516         if (!adapter->vfs_allocated_count)
5517                 return;
5518
5519         for (i = 0; i < hw->mac.uta_reg_count; i++)
5520                 array_wr32(E1000_UTA, i, ~0);
5521 }
5522
5523 /**
5524  * igb_intr_msi - Interrupt Handler
5525  * @irq: interrupt number
5526  * @data: pointer to a network interface device structure
5527  **/
5528 static irqreturn_t igb_intr_msi(int irq, void *data)
5529 {
5530         struct igb_adapter *adapter = data;
5531         struct igb_q_vector *q_vector = adapter->q_vector[0];
5532         struct e1000_hw *hw = &adapter->hw;
5533         /* read ICR disables interrupts using IAM */
5534         u32 icr = rd32(E1000_ICR);
5535
5536         igb_write_itr(q_vector);
5537
5538         if (icr & E1000_ICR_DRSTA)
5539                 schedule_work(&adapter->reset_task);
5540
5541         if (icr & E1000_ICR_DOUTSYNC) {
5542                 /* HW is reporting DMA is out of sync */
5543                 adapter->stats.doosync++;
5544         }
5545
5546         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5547                 hw->mac.get_link_status = 1;
5548                 if (!test_bit(__IGB_DOWN, &adapter->state))
5549                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5550         }
5551
5552         if (icr & E1000_ICR_TS) {
5553                 u32 tsicr = rd32(E1000_TSICR);
5554
5555                 if (tsicr & E1000_TSICR_TXTS) {
5556                         /* acknowledge the interrupt */
5557                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5558                         /* retrieve hardware timestamp */
5559                         schedule_work(&adapter->ptp_tx_work);
5560                 }
5561         }
5562
5563         napi_schedule(&q_vector->napi);
5564
5565         return IRQ_HANDLED;
5566 }
5567
5568 /**
5569  * igb_intr - Legacy Interrupt Handler
5570  * @irq: interrupt number
5571  * @data: pointer to a network interface device structure
5572  **/
5573 static irqreturn_t igb_intr(int irq, void *data)
5574 {
5575         struct igb_adapter *adapter = data;
5576         struct igb_q_vector *q_vector = adapter->q_vector[0];
5577         struct e1000_hw *hw = &adapter->hw;
5578         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5579          * need for the IMC write */
5580         u32 icr = rd32(E1000_ICR);
5581
5582         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5583          * not set, then the adapter didn't send an interrupt */
5584         if (!(icr & E1000_ICR_INT_ASSERTED))
5585                 return IRQ_NONE;
5586
5587         igb_write_itr(q_vector);
5588
5589         if (icr & E1000_ICR_DRSTA)
5590                 schedule_work(&adapter->reset_task);
5591
5592         if (icr & E1000_ICR_DOUTSYNC) {
5593                 /* HW is reporting DMA is out of sync */
5594                 adapter->stats.doosync++;
5595         }
5596
5597         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5598                 hw->mac.get_link_status = 1;
5599                 /* guard against interrupt when we're going down */
5600                 if (!test_bit(__IGB_DOWN, &adapter->state))
5601                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5602         }
5603
5604         if (icr & E1000_ICR_TS) {
5605                 u32 tsicr = rd32(E1000_TSICR);
5606
5607                 if (tsicr & E1000_TSICR_TXTS) {
5608                         /* acknowledge the interrupt */
5609                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5610                         /* retrieve hardware timestamp */
5611                         schedule_work(&adapter->ptp_tx_work);
5612                 }
5613         }
5614
5615         napi_schedule(&q_vector->napi);
5616
5617         return IRQ_HANDLED;
5618 }
5619
5620 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5621 {
5622         struct igb_adapter *adapter = q_vector->adapter;
5623         struct e1000_hw *hw = &adapter->hw;
5624
5625         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5626             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5627                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5628                         igb_set_itr(q_vector);
5629                 else
5630                         igb_update_ring_itr(q_vector);
5631         }
5632
5633         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5634                 if (adapter->msix_entries)
5635                         wr32(E1000_EIMS, q_vector->eims_value);
5636                 else
5637                         igb_irq_enable(adapter);
5638         }
5639 }
5640
5641 /**
5642  * igb_poll - NAPI Rx polling callback
5643  * @napi: napi polling structure
5644  * @budget: count of how many packets we should handle
5645  **/
5646 static int igb_poll(struct napi_struct *napi, int budget)
5647 {
5648         struct igb_q_vector *q_vector = container_of(napi,
5649                                                      struct igb_q_vector,
5650                                                      napi);
5651         bool clean_complete = true;
5652
5653 #ifdef CONFIG_IGB_DCA
5654         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5655                 igb_update_dca(q_vector);
5656 #endif
5657         if (q_vector->tx.ring)
5658                 clean_complete = igb_clean_tx_irq(q_vector);
5659
5660         if (q_vector->rx.ring)
5661                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5662
5663         /* If all work not completed, return budget and keep polling */
5664         if (!clean_complete)
5665                 return budget;
5666
5667         /* If not enough Rx work done, exit the polling mode */
5668         napi_complete(napi);
5669         igb_ring_irq_enable(q_vector);
5670
5671         return 0;
5672 }
5673
5674 /**
5675  * igb_clean_tx_irq - Reclaim resources after transmit completes
5676  * @q_vector: pointer to q_vector containing needed info
5677  *
5678  * returns true if ring is completely cleaned
5679  **/
5680 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5681 {
5682         struct igb_adapter *adapter = q_vector->adapter;
5683         struct igb_ring *tx_ring = q_vector->tx.ring;
5684         struct igb_tx_buffer *tx_buffer;
5685         union e1000_adv_tx_desc *tx_desc;
5686         unsigned int total_bytes = 0, total_packets = 0;
5687         unsigned int budget = q_vector->tx.work_limit;
5688         unsigned int i = tx_ring->next_to_clean;
5689
5690         if (test_bit(__IGB_DOWN, &adapter->state))
5691                 return true;
5692
5693         tx_buffer = &tx_ring->tx_buffer_info[i];
5694         tx_desc = IGB_TX_DESC(tx_ring, i);
5695         i -= tx_ring->count;
5696
5697         do {
5698                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5699
5700                 /* if next_to_watch is not set then there is no work pending */
5701                 if (!eop_desc)
5702                         break;
5703
5704                 /* prevent any other reads prior to eop_desc */
5705                 rmb();
5706
5707                 /* if DD is not set pending work has not been completed */
5708                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5709                         break;
5710
5711                 /* clear next_to_watch to prevent false hangs */
5712                 tx_buffer->next_to_watch = NULL;
5713
5714                 /* update the statistics for this packet */
5715                 total_bytes += tx_buffer->bytecount;
5716                 total_packets += tx_buffer->gso_segs;
5717
5718                 /* free the skb */
5719                 dev_kfree_skb_any(tx_buffer->skb);
5720
5721                 /* unmap skb header data */
5722                 dma_unmap_single(tx_ring->dev,
5723                                  dma_unmap_addr(tx_buffer, dma),
5724                                  dma_unmap_len(tx_buffer, len),
5725                                  DMA_TO_DEVICE);
5726
5727                 /* clear tx_buffer data */
5728                 tx_buffer->skb = NULL;
5729                 dma_unmap_len_set(tx_buffer, len, 0);
5730
5731                 /* clear last DMA location and unmap remaining buffers */
5732                 while (tx_desc != eop_desc) {
5733                         tx_buffer++;
5734                         tx_desc++;
5735                         i++;
5736                         if (unlikely(!i)) {
5737                                 i -= tx_ring->count;
5738                                 tx_buffer = tx_ring->tx_buffer_info;
5739                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5740                         }
5741
5742                         /* unmap any remaining paged data */
5743                         if (dma_unmap_len(tx_buffer, len)) {
5744                                 dma_unmap_page(tx_ring->dev,
5745                                                dma_unmap_addr(tx_buffer, dma),
5746                                                dma_unmap_len(tx_buffer, len),
5747                                                DMA_TO_DEVICE);
5748                                 dma_unmap_len_set(tx_buffer, len, 0);
5749                         }
5750                 }
5751
5752                 /* move us one more past the eop_desc for start of next pkt */
5753                 tx_buffer++;
5754                 tx_desc++;
5755                 i++;
5756                 if (unlikely(!i)) {
5757                         i -= tx_ring->count;
5758                         tx_buffer = tx_ring->tx_buffer_info;
5759                         tx_desc = IGB_TX_DESC(tx_ring, 0);
5760                 }
5761
5762                 /* issue prefetch for next Tx descriptor */
5763                 prefetch(tx_desc);
5764
5765                 /* update budget accounting */
5766                 budget--;
5767         } while (likely(budget));
5768
5769         netdev_tx_completed_queue(txring_txq(tx_ring),
5770                                   total_packets, total_bytes);
5771         i += tx_ring->count;
5772         tx_ring->next_to_clean = i;
5773         u64_stats_update_begin(&tx_ring->tx_syncp);
5774         tx_ring->tx_stats.bytes += total_bytes;
5775         tx_ring->tx_stats.packets += total_packets;
5776         u64_stats_update_end(&tx_ring->tx_syncp);
5777         q_vector->tx.total_bytes += total_bytes;
5778         q_vector->tx.total_packets += total_packets;
5779
5780         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
5781                 struct e1000_hw *hw = &adapter->hw;
5782
5783                 /* Detect a transmit hang in hardware, this serializes the
5784                  * check with the clearing of time_stamp and movement of i */
5785                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5786                 if (tx_buffer->next_to_watch &&
5787                     time_after(jiffies, tx_buffer->time_stamp +
5788                                (adapter->tx_timeout_factor * HZ)) &&
5789                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5790
5791                         /* detected Tx unit hang */
5792                         dev_err(tx_ring->dev,
5793                                 "Detected Tx Unit Hang\n"
5794                                 "  Tx Queue             <%d>\n"
5795                                 "  TDH                  <%x>\n"
5796                                 "  TDT                  <%x>\n"
5797                                 "  next_to_use          <%x>\n"
5798                                 "  next_to_clean        <%x>\n"
5799                                 "buffer_info[next_to_clean]\n"
5800                                 "  time_stamp           <%lx>\n"
5801                                 "  next_to_watch        <%p>\n"
5802                                 "  jiffies              <%lx>\n"
5803                                 "  desc.status          <%x>\n",
5804                                 tx_ring->queue_index,
5805                                 rd32(E1000_TDH(tx_ring->reg_idx)),
5806                                 readl(tx_ring->tail),
5807                                 tx_ring->next_to_use,
5808                                 tx_ring->next_to_clean,
5809                                 tx_buffer->time_stamp,
5810                                 tx_buffer->next_to_watch,
5811                                 jiffies,
5812                                 tx_buffer->next_to_watch->wb.status);
5813                         netif_stop_subqueue(tx_ring->netdev,
5814                                             tx_ring->queue_index);
5815
5816                         /* we are about to reset, no point in enabling stuff */
5817                         return true;
5818                 }
5819         }
5820
5821         if (unlikely(total_packets &&
5822                      netif_carrier_ok(tx_ring->netdev) &&
5823                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
5824                 /* Make sure that anybody stopping the queue after this
5825                  * sees the new next_to_clean.
5826                  */
5827                 smp_mb();
5828                 if (__netif_subqueue_stopped(tx_ring->netdev,
5829                                              tx_ring->queue_index) &&
5830                     !(test_bit(__IGB_DOWN, &adapter->state))) {
5831                         netif_wake_subqueue(tx_ring->netdev,
5832                                             tx_ring->queue_index);
5833
5834                         u64_stats_update_begin(&tx_ring->tx_syncp);
5835                         tx_ring->tx_stats.restart_queue++;
5836                         u64_stats_update_end(&tx_ring->tx_syncp);
5837                 }
5838         }
5839
5840         return !!budget;
5841 }
5842
5843 /**
5844  * igb_reuse_rx_page - page flip buffer and store it back on the ring
5845  * @rx_ring: rx descriptor ring to store buffers on
5846  * @old_buff: donor buffer to have page reused
5847  *
5848  * Synchronizes page for reuse by the adapter
5849  **/
5850 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
5851                               struct igb_rx_buffer *old_buff)
5852 {
5853         struct igb_rx_buffer *new_buff;
5854         u16 nta = rx_ring->next_to_alloc;
5855
5856         new_buff = &rx_ring->rx_buffer_info[nta];
5857
5858         /* update, and store next to alloc */
5859         nta++;
5860         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
5861
5862         /* transfer page from old buffer to new buffer */
5863         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
5864
5865         /* sync the buffer for use by the device */
5866         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
5867                                          old_buff->page_offset,
5868                                          IGB_RX_BUFSZ,
5869                                          DMA_FROM_DEVICE);
5870 }
5871
5872 /**
5873  * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
5874  * @rx_ring: rx descriptor ring to transact packets on
5875  * @rx_buffer: buffer containing page to add
5876  * @rx_desc: descriptor containing length of buffer written by hardware
5877  * @skb: sk_buff to place the data into
5878  *
5879  * This function will add the data contained in rx_buffer->page to the skb.
5880  * This is done either through a direct copy if the data in the buffer is
5881  * less than the skb header size, otherwise it will just attach the page as
5882  * a frag to the skb.
5883  *
5884  * The function will then update the page offset if necessary and return
5885  * true if the buffer can be reused by the adapter.
5886  **/
5887 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
5888                             struct igb_rx_buffer *rx_buffer,
5889                             union e1000_adv_rx_desc *rx_desc,
5890                             struct sk_buff *skb)
5891 {
5892         struct page *page = rx_buffer->page;
5893         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
5894
5895         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
5896                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
5897
5898                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
5899                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
5900                         va += IGB_TS_HDR_LEN;
5901                         size -= IGB_TS_HDR_LEN;
5902                 }
5903
5904                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
5905
5906                 /* we can reuse buffer as-is, just make sure it is local */
5907                 if (likely(page_to_nid(page) == numa_node_id()))
5908                         return true;
5909
5910                 /* this page cannot be reused so discard it */
5911                 put_page(page);
5912                 return false;
5913         }
5914
5915         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
5916                         rx_buffer->page_offset, size, IGB_RX_BUFSZ);
5917
5918         /* avoid re-using remote pages */
5919         if (unlikely(page_to_nid(page) != numa_node_id()))
5920                 return false;
5921
5922 #if (PAGE_SIZE < 8192)
5923         /* if we are only owner of page we can reuse it */
5924         if (unlikely(page_count(page) != 1))
5925                 return false;
5926
5927         /* flip page offset to other buffer */
5928         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
5929
5930         /*
5931          * since we are the only owner of the page and we need to
5932          * increment it, just set the value to 2 in order to avoid
5933          * an unnecessary locked operation
5934          */
5935         atomic_set(&page->_count, 2);
5936 #else
5937         /* move offset up to the next cache line */
5938         rx_buffer->page_offset += SKB_DATA_ALIGN(size);
5939
5940         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
5941                 return false;
5942
5943         /* bump ref count on page before it is given to the stack */
5944         get_page(page);
5945 #endif
5946
5947         return true;
5948 }
5949
5950 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
5951                                            union e1000_adv_rx_desc *rx_desc,
5952                                            struct sk_buff *skb)
5953 {
5954         struct igb_rx_buffer *rx_buffer;
5955         struct page *page;
5956
5957         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
5958
5959         /*
5960          * This memory barrier is needed to keep us from reading
5961          * any other fields out of the rx_desc until we know the
5962          * RXD_STAT_DD bit is set
5963          */
5964         rmb();
5965
5966         page = rx_buffer->page;
5967         prefetchw(page);
5968
5969         if (likely(!skb)) {
5970                 void *page_addr = page_address(page) +
5971                                   rx_buffer->page_offset;
5972
5973                 /* prefetch first cache line of first page */
5974                 prefetch(page_addr);
5975 #if L1_CACHE_BYTES < 128
5976                 prefetch(page_addr + L1_CACHE_BYTES);
5977 #endif
5978
5979                 /* allocate a skb to store the frags */
5980                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
5981                                                 IGB_RX_HDR_LEN);
5982                 if (unlikely(!skb)) {
5983                         rx_ring->rx_stats.alloc_failed++;
5984                         return NULL;
5985                 }
5986
5987                 /*
5988                  * we will be copying header into skb->data in
5989                  * pskb_may_pull so it is in our interest to prefetch
5990                  * it now to avoid a possible cache miss
5991                  */
5992                 prefetchw(skb->data);
5993         }
5994
5995         /* we are reusing so sync this buffer for CPU use */
5996         dma_sync_single_range_for_cpu(rx_ring->dev,
5997                                       rx_buffer->dma,
5998                                       rx_buffer->page_offset,
5999                                       IGB_RX_BUFSZ,
6000                                       DMA_FROM_DEVICE);
6001
6002         /* pull page into skb */
6003         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6004                 /* hand second half of page back to the ring */
6005                 igb_reuse_rx_page(rx_ring, rx_buffer);
6006         } else {
6007                 /* we are not reusing the buffer so unmap it */
6008                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6009                                PAGE_SIZE, DMA_FROM_DEVICE);
6010         }
6011
6012         /* clear contents of rx_buffer */
6013         rx_buffer->page = NULL;
6014
6015         return skb;
6016 }
6017
6018 static inline void igb_rx_checksum(struct igb_ring *ring,
6019                                    union e1000_adv_rx_desc *rx_desc,
6020                                    struct sk_buff *skb)
6021 {
6022         skb_checksum_none_assert(skb);
6023
6024         /* Ignore Checksum bit is set */
6025         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6026                 return;
6027
6028         /* Rx checksum disabled via ethtool */
6029         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6030                 return;
6031
6032         /* TCP/UDP checksum error bit is set */
6033         if (igb_test_staterr(rx_desc,
6034                              E1000_RXDEXT_STATERR_TCPE |
6035                              E1000_RXDEXT_STATERR_IPE)) {
6036                 /*
6037                  * work around errata with sctp packets where the TCPE aka
6038                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6039                  * packets, (aka let the stack check the crc32c)
6040                  */
6041                 if (!((skb->len == 60) &&
6042                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6043                         u64_stats_update_begin(&ring->rx_syncp);
6044                         ring->rx_stats.csum_err++;
6045                         u64_stats_update_end(&ring->rx_syncp);
6046                 }
6047                 /* let the stack verify checksum errors */
6048                 return;
6049         }
6050         /* It must be a TCP or UDP packet with a valid checksum */
6051         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6052                                       E1000_RXD_STAT_UDPCS))
6053                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6054
6055         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6056                 le32_to_cpu(rx_desc->wb.upper.status_error));
6057 }
6058
6059 static inline void igb_rx_hash(struct igb_ring *ring,
6060                                union e1000_adv_rx_desc *rx_desc,
6061                                struct sk_buff *skb)
6062 {
6063         if (ring->netdev->features & NETIF_F_RXHASH)
6064                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6065 }
6066
6067 /**
6068  * igb_is_non_eop - process handling of non-EOP buffers
6069  * @rx_ring: Rx ring being processed
6070  * @rx_desc: Rx descriptor for current buffer
6071  * @skb: current socket buffer containing buffer in progress
6072  *
6073  * This function updates next to clean.  If the buffer is an EOP buffer
6074  * this function exits returning false, otherwise it will place the
6075  * sk_buff in the next buffer to be chained and return true indicating
6076  * that this is in fact a non-EOP buffer.
6077  **/
6078 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6079                            union e1000_adv_rx_desc *rx_desc)
6080 {
6081         u32 ntc = rx_ring->next_to_clean + 1;
6082
6083         /* fetch, update, and store next to clean */
6084         ntc = (ntc < rx_ring->count) ? ntc : 0;
6085         rx_ring->next_to_clean = ntc;
6086
6087         prefetch(IGB_RX_DESC(rx_ring, ntc));
6088
6089         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6090                 return false;
6091
6092         return true;
6093 }
6094
6095 /**
6096  * igb_get_headlen - determine size of header for LRO/GRO
6097  * @data: pointer to the start of the headers
6098  * @max_len: total length of section to find headers in
6099  *
6100  * This function is meant to determine the length of headers that will
6101  * be recognized by hardware for LRO, and GRO offloads.  The main
6102  * motivation of doing this is to only perform one pull for IPv4 TCP
6103  * packets so that we can do basic things like calculating the gso_size
6104  * based on the average data per packet.
6105  **/
6106 static unsigned int igb_get_headlen(unsigned char *data,
6107                                     unsigned int max_len)
6108 {
6109         union {
6110                 unsigned char *network;
6111                 /* l2 headers */
6112                 struct ethhdr *eth;
6113                 struct vlan_hdr *vlan;
6114                 /* l3 headers */
6115                 struct iphdr *ipv4;
6116                 struct ipv6hdr *ipv6;
6117         } hdr;
6118         __be16 protocol;
6119         u8 nexthdr = 0; /* default to not TCP */
6120         u8 hlen;
6121
6122         /* this should never happen, but better safe than sorry */
6123         if (max_len < ETH_HLEN)
6124                 return max_len;
6125
6126         /* initialize network frame pointer */
6127         hdr.network = data;
6128
6129         /* set first protocol and move network header forward */
6130         protocol = hdr.eth->h_proto;
6131         hdr.network += ETH_HLEN;
6132
6133         /* handle any vlan tag if present */
6134         if (protocol == __constant_htons(ETH_P_8021Q)) {
6135                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6136                         return max_len;
6137
6138                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6139                 hdr.network += VLAN_HLEN;
6140         }
6141
6142         /* handle L3 protocols */
6143         if (protocol == __constant_htons(ETH_P_IP)) {
6144                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6145                         return max_len;
6146
6147                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6148                 hlen = (hdr.network[0] & 0x0F) << 2;
6149
6150                 /* verify hlen meets minimum size requirements */
6151                 if (hlen < sizeof(struct iphdr))
6152                         return hdr.network - data;
6153
6154                 /* record next protocol if header is present */
6155                 if (!hdr.ipv4->frag_off)
6156                         nexthdr = hdr.ipv4->protocol;
6157         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6158                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6159                         return max_len;
6160
6161                 /* record next protocol */
6162                 nexthdr = hdr.ipv6->nexthdr;
6163                 hlen = sizeof(struct ipv6hdr);
6164         } else {
6165                 return hdr.network - data;
6166         }
6167
6168         /* relocate pointer to start of L4 header */
6169         hdr.network += hlen;
6170
6171         /* finally sort out TCP */
6172         if (nexthdr == IPPROTO_TCP) {
6173                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6174                         return max_len;
6175
6176                 /* access doff as a u8 to avoid unaligned access on ia64 */
6177                 hlen = (hdr.network[12] & 0xF0) >> 2;
6178
6179                 /* verify hlen meets minimum size requirements */
6180                 if (hlen < sizeof(struct tcphdr))
6181                         return hdr.network - data;
6182
6183                 hdr.network += hlen;
6184         } else if (nexthdr == IPPROTO_UDP) {
6185                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6186                         return max_len;
6187
6188                 hdr.network += sizeof(struct udphdr);
6189         }
6190
6191         /*
6192          * If everything has gone correctly hdr.network should be the
6193          * data section of the packet and will be the end of the header.
6194          * If not then it probably represents the end of the last recognized
6195          * header.
6196          */
6197         if ((hdr.network - data) < max_len)
6198                 return hdr.network - data;
6199         else
6200                 return max_len;
6201 }
6202
6203 /**
6204  * igb_pull_tail - igb specific version of skb_pull_tail
6205  * @rx_ring: rx descriptor ring packet is being transacted on
6206  * @rx_desc: pointer to the EOP Rx descriptor
6207  * @skb: pointer to current skb being adjusted
6208  *
6209  * This function is an igb specific version of __pskb_pull_tail.  The
6210  * main difference between this version and the original function is that
6211  * this function can make several assumptions about the state of things
6212  * that allow for significant optimizations versus the standard function.
6213  * As a result we can do things like drop a frag and maintain an accurate
6214  * truesize for the skb.
6215  */
6216 static void igb_pull_tail(struct igb_ring *rx_ring,
6217                           union e1000_adv_rx_desc *rx_desc,
6218                           struct sk_buff *skb)
6219 {
6220         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6221         unsigned char *va;
6222         unsigned int pull_len;
6223
6224         /*
6225          * it is valid to use page_address instead of kmap since we are
6226          * working with pages allocated out of the lomem pool per
6227          * alloc_page(GFP_ATOMIC)
6228          */
6229         va = skb_frag_address(frag);
6230
6231         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6232                 /* retrieve timestamp from buffer */
6233                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6234
6235                 /* update pointers to remove timestamp header */
6236                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6237                 frag->page_offset += IGB_TS_HDR_LEN;
6238                 skb->data_len -= IGB_TS_HDR_LEN;
6239                 skb->len -= IGB_TS_HDR_LEN;
6240
6241                 /* move va to start of packet data */
6242                 va += IGB_TS_HDR_LEN;
6243         }
6244
6245         /*
6246          * we need the header to contain the greater of either ETH_HLEN or
6247          * 60 bytes if the skb->len is less than 60 for skb_pad.
6248          */
6249         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6250
6251         /* align pull length to size of long to optimize memcpy performance */
6252         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6253
6254         /* update all of the pointers */
6255         skb_frag_size_sub(frag, pull_len);
6256         frag->page_offset += pull_len;
6257         skb->data_len -= pull_len;
6258         skb->tail += pull_len;
6259 }
6260
6261 /**
6262  * igb_cleanup_headers - Correct corrupted or empty headers
6263  * @rx_ring: rx descriptor ring packet is being transacted on
6264  * @rx_desc: pointer to the EOP Rx descriptor
6265  * @skb: pointer to current skb being fixed
6266  *
6267  * Address the case where we are pulling data in on pages only
6268  * and as such no data is present in the skb header.
6269  *
6270  * In addition if skb is not at least 60 bytes we need to pad it so that
6271  * it is large enough to qualify as a valid Ethernet frame.
6272  *
6273  * Returns true if an error was encountered and skb was freed.
6274  **/
6275 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6276                                 union e1000_adv_rx_desc *rx_desc,
6277                                 struct sk_buff *skb)
6278 {
6279
6280         if (unlikely((igb_test_staterr(rx_desc,
6281                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6282                 struct net_device *netdev = rx_ring->netdev;
6283                 if (!(netdev->features & NETIF_F_RXALL)) {
6284                         dev_kfree_skb_any(skb);
6285                         return true;
6286                 }
6287         }
6288
6289         /* place header in linear portion of buffer */
6290         if (skb_is_nonlinear(skb))
6291                 igb_pull_tail(rx_ring, rx_desc, skb);
6292
6293         /* if skb_pad returns an error the skb was freed */
6294         if (unlikely(skb->len < 60)) {
6295                 int pad_len = 60 - skb->len;
6296
6297                 if (skb_pad(skb, pad_len))
6298                         return true;
6299                 __skb_put(skb, pad_len);
6300         }
6301
6302         return false;
6303 }
6304
6305 /**
6306  * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6307  * @rx_ring: rx descriptor ring packet is being transacted on
6308  * @rx_desc: pointer to the EOP Rx descriptor
6309  * @skb: pointer to current skb being populated
6310  *
6311  * This function checks the ring, descriptor, and packet information in
6312  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6313  * other fields within the skb.
6314  **/
6315 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6316                                    union e1000_adv_rx_desc *rx_desc,
6317                                    struct sk_buff *skb)
6318 {
6319         struct net_device *dev = rx_ring->netdev;
6320
6321         igb_rx_hash(rx_ring, rx_desc, skb);
6322
6323         igb_rx_checksum(rx_ring, rx_desc, skb);
6324
6325         igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6326
6327         if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6328             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6329                 u16 vid;
6330                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6331                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6332                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6333                 else
6334                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6335
6336                 __vlan_hwaccel_put_tag(skb, vid);
6337         }
6338
6339         skb_record_rx_queue(skb, rx_ring->queue_index);
6340
6341         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6342 }
6343
6344 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6345 {
6346         struct igb_ring *rx_ring = q_vector->rx.ring;
6347         struct sk_buff *skb = rx_ring->skb;
6348         unsigned int total_bytes = 0, total_packets = 0;
6349         u16 cleaned_count = igb_desc_unused(rx_ring);
6350
6351         do {
6352                 union e1000_adv_rx_desc *rx_desc;
6353
6354                 /* return some buffers to hardware, one at a time is too slow */
6355                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6356                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6357                         cleaned_count = 0;
6358                 }
6359
6360                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6361
6362                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6363                         break;
6364
6365                 /* retrieve a buffer from the ring */
6366                 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6367
6368                 /* exit if we failed to retrieve a buffer */
6369                 if (!skb)
6370                         break;
6371
6372                 cleaned_count++;
6373
6374                 /* fetch next buffer in frame if non-eop */
6375                 if (igb_is_non_eop(rx_ring, rx_desc))
6376                         continue;
6377
6378                 /* verify the packet layout is correct */
6379                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6380                         skb = NULL;
6381                         continue;
6382                 }
6383
6384                 /* probably a little skewed due to removing CRC */
6385                 total_bytes += skb->len;
6386
6387                 /* populate checksum, timestamp, VLAN, and protocol */
6388                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6389
6390                 napi_gro_receive(&q_vector->napi, skb);
6391
6392                 /* reset skb pointer */
6393                 skb = NULL;
6394
6395                 /* update budget accounting */
6396                 total_packets++;
6397         } while (likely(total_packets < budget));
6398
6399         /* place incomplete frames back on ring for completion */
6400         rx_ring->skb = skb;
6401
6402         u64_stats_update_begin(&rx_ring->rx_syncp);
6403         rx_ring->rx_stats.packets += total_packets;
6404         rx_ring->rx_stats.bytes += total_bytes;
6405         u64_stats_update_end(&rx_ring->rx_syncp);
6406         q_vector->rx.total_packets += total_packets;
6407         q_vector->rx.total_bytes += total_bytes;
6408
6409         if (cleaned_count)
6410                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6411
6412         return (total_packets < budget);
6413 }
6414
6415 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6416                                   struct igb_rx_buffer *bi)
6417 {
6418         struct page *page = bi->page;
6419         dma_addr_t dma;
6420
6421         /* since we are recycling buffers we should seldom need to alloc */
6422         if (likely(page))
6423                 return true;
6424
6425         /* alloc new page for storage */
6426         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6427         if (unlikely(!page)) {
6428                 rx_ring->rx_stats.alloc_failed++;
6429                 return false;
6430         }
6431
6432         /* map page for use */
6433         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6434
6435         /*
6436          * if mapping failed free memory back to system since
6437          * there isn't much point in holding memory we can't use
6438          */
6439         if (dma_mapping_error(rx_ring->dev, dma)) {
6440                 __free_page(page);
6441
6442                 rx_ring->rx_stats.alloc_failed++;
6443                 return false;
6444         }
6445
6446         bi->dma = dma;
6447         bi->page = page;
6448         bi->page_offset = 0;
6449
6450         return true;
6451 }
6452
6453 /**
6454  * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6455  * @adapter: address of board private structure
6456  **/
6457 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6458 {
6459         union e1000_adv_rx_desc *rx_desc;
6460         struct igb_rx_buffer *bi;
6461         u16 i = rx_ring->next_to_use;
6462
6463         /* nothing to do */
6464         if (!cleaned_count)
6465                 return;
6466
6467         rx_desc = IGB_RX_DESC(rx_ring, i);
6468         bi = &rx_ring->rx_buffer_info[i];
6469         i -= rx_ring->count;
6470
6471         do {
6472                 if (!igb_alloc_mapped_page(rx_ring, bi))
6473                         break;
6474
6475                 /*
6476                  * Refresh the desc even if buffer_addrs didn't change
6477                  * because each write-back erases this info.
6478                  */
6479                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
6480
6481                 rx_desc++;
6482                 bi++;
6483                 i++;
6484                 if (unlikely(!i)) {
6485                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6486                         bi = rx_ring->rx_buffer_info;
6487                         i -= rx_ring->count;
6488                 }
6489
6490                 /* clear the hdr_addr for the next_to_use descriptor */
6491                 rx_desc->read.hdr_addr = 0;
6492
6493                 cleaned_count--;
6494         } while (cleaned_count);
6495
6496         i += rx_ring->count;
6497
6498         if (rx_ring->next_to_use != i) {
6499                 /* record the next descriptor to use */
6500                 rx_ring->next_to_use = i;
6501
6502                 /* update next to alloc since we have filled the ring */
6503                 rx_ring->next_to_alloc = i;
6504
6505                 /*
6506                  * Force memory writes to complete before letting h/w
6507                  * know there are new descriptors to fetch.  (Only
6508                  * applicable for weak-ordered memory model archs,
6509                  * such as IA-64).
6510                  */
6511                 wmb();
6512                 writel(i, rx_ring->tail);
6513         }
6514 }
6515
6516 /**
6517  * igb_mii_ioctl -
6518  * @netdev:
6519  * @ifreq:
6520  * @cmd:
6521  **/
6522 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6523 {
6524         struct igb_adapter *adapter = netdev_priv(netdev);
6525         struct mii_ioctl_data *data = if_mii(ifr);
6526
6527         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6528                 return -EOPNOTSUPP;
6529
6530         switch (cmd) {
6531         case SIOCGMIIPHY:
6532                 data->phy_id = adapter->hw.phy.addr;
6533                 break;
6534         case SIOCGMIIREG:
6535                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6536                                      &data->val_out))
6537                         return -EIO;
6538                 break;
6539         case SIOCSMIIREG:
6540         default:
6541                 return -EOPNOTSUPP;
6542         }
6543         return 0;
6544 }
6545
6546 /**
6547  * igb_ioctl -
6548  * @netdev:
6549  * @ifreq:
6550  * @cmd:
6551  **/
6552 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6553 {
6554         switch (cmd) {
6555         case SIOCGMIIPHY:
6556         case SIOCGMIIREG:
6557         case SIOCSMIIREG:
6558                 return igb_mii_ioctl(netdev, ifr, cmd);
6559         case SIOCSHWTSTAMP:
6560                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6561         default:
6562                 return -EOPNOTSUPP;
6563         }
6564 }
6565
6566 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6567 {
6568         struct igb_adapter *adapter = hw->back;
6569
6570         if (pcie_capability_read_word(adapter->pdev, reg, value))
6571                 return -E1000_ERR_CONFIG;
6572
6573         return 0;
6574 }
6575
6576 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6577 {
6578         struct igb_adapter *adapter = hw->back;
6579
6580         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6581                 return -E1000_ERR_CONFIG;
6582
6583         return 0;
6584 }
6585
6586 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6587 {
6588         struct igb_adapter *adapter = netdev_priv(netdev);
6589         struct e1000_hw *hw = &adapter->hw;
6590         u32 ctrl, rctl;
6591         bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6592
6593         if (enable) {
6594                 /* enable VLAN tag insert/strip */
6595                 ctrl = rd32(E1000_CTRL);
6596                 ctrl |= E1000_CTRL_VME;
6597                 wr32(E1000_CTRL, ctrl);
6598
6599                 /* Disable CFI check */
6600                 rctl = rd32(E1000_RCTL);
6601                 rctl &= ~E1000_RCTL_CFIEN;
6602                 wr32(E1000_RCTL, rctl);
6603         } else {
6604                 /* disable VLAN tag insert/strip */
6605                 ctrl = rd32(E1000_CTRL);
6606                 ctrl &= ~E1000_CTRL_VME;
6607                 wr32(E1000_CTRL, ctrl);
6608         }
6609
6610         igb_rlpml_set(adapter);
6611 }
6612
6613 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6614 {
6615         struct igb_adapter *adapter = netdev_priv(netdev);
6616         struct e1000_hw *hw = &adapter->hw;
6617         int pf_id = adapter->vfs_allocated_count;
6618
6619         /* attempt to add filter to vlvf array */
6620         igb_vlvf_set(adapter, vid, true, pf_id);
6621
6622         /* add the filter since PF can receive vlans w/o entry in vlvf */
6623         igb_vfta_set(hw, vid, true);
6624
6625         set_bit(vid, adapter->active_vlans);
6626
6627         return 0;
6628 }
6629
6630 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6631 {
6632         struct igb_adapter *adapter = netdev_priv(netdev);
6633         struct e1000_hw *hw = &adapter->hw;
6634         int pf_id = adapter->vfs_allocated_count;
6635         s32 err;
6636
6637         /* remove vlan from VLVF table array */
6638         err = igb_vlvf_set(adapter, vid, false, pf_id);
6639
6640         /* if vid was not present in VLVF just remove it from table */
6641         if (err)
6642                 igb_vfta_set(hw, vid, false);
6643
6644         clear_bit(vid, adapter->active_vlans);
6645
6646         return 0;
6647 }
6648
6649 static void igb_restore_vlan(struct igb_adapter *adapter)
6650 {
6651         u16 vid;
6652
6653         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
6654
6655         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
6656                 igb_vlan_rx_add_vid(adapter->netdev, vid);
6657 }
6658
6659 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6660 {
6661         struct pci_dev *pdev = adapter->pdev;
6662         struct e1000_mac_info *mac = &adapter->hw.mac;
6663
6664         mac->autoneg = 0;
6665
6666         /* Make sure dplx is at most 1 bit and lsb of speed is not set
6667          * for the switch() below to work */
6668         if ((spd & 1) || (dplx & ~1))
6669                 goto err_inval;
6670
6671         /* Fiber NIC's only allow 1000 Gbps Full duplex */
6672         if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6673             spd != SPEED_1000 &&
6674             dplx != DUPLEX_FULL)
6675                 goto err_inval;
6676
6677         switch (spd + dplx) {
6678         case SPEED_10 + DUPLEX_HALF:
6679                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
6680                 break;
6681         case SPEED_10 + DUPLEX_FULL:
6682                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
6683                 break;
6684         case SPEED_100 + DUPLEX_HALF:
6685                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
6686                 break;
6687         case SPEED_100 + DUPLEX_FULL:
6688                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
6689                 break;
6690         case SPEED_1000 + DUPLEX_FULL:
6691                 mac->autoneg = 1;
6692                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
6693                 break;
6694         case SPEED_1000 + DUPLEX_HALF: /* not supported */
6695         default:
6696                 goto err_inval;
6697         }
6698
6699         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
6700         adapter->hw.phy.mdix = AUTO_ALL_MODES;
6701
6702         return 0;
6703
6704 err_inval:
6705         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
6706         return -EINVAL;
6707 }
6708
6709 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
6710                           bool runtime)
6711 {
6712         struct net_device *netdev = pci_get_drvdata(pdev);
6713         struct igb_adapter *adapter = netdev_priv(netdev);
6714         struct e1000_hw *hw = &adapter->hw;
6715         u32 ctrl, rctl, status;
6716         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6717 #ifdef CONFIG_PM
6718         int retval = 0;
6719 #endif
6720
6721         netif_device_detach(netdev);
6722
6723         if (netif_running(netdev))
6724                 __igb_close(netdev, true);
6725
6726         igb_clear_interrupt_scheme(adapter);
6727
6728 #ifdef CONFIG_PM
6729         retval = pci_save_state(pdev);
6730         if (retval)
6731                 return retval;
6732 #endif
6733
6734         status = rd32(E1000_STATUS);
6735         if (status & E1000_STATUS_LU)
6736                 wufc &= ~E1000_WUFC_LNKC;
6737
6738         if (wufc) {
6739                 igb_setup_rctl(adapter);
6740                 igb_set_rx_mode(netdev);
6741
6742                 /* turn on all-multi mode if wake on multicast is enabled */
6743                 if (wufc & E1000_WUFC_MC) {
6744                         rctl = rd32(E1000_RCTL);
6745                         rctl |= E1000_RCTL_MPE;
6746                         wr32(E1000_RCTL, rctl);
6747                 }
6748
6749                 ctrl = rd32(E1000_CTRL);
6750                 /* advertise wake from D3Cold */
6751                 #define E1000_CTRL_ADVD3WUC 0x00100000
6752                 /* phy power management enable */
6753                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
6754                 ctrl |= E1000_CTRL_ADVD3WUC;
6755                 wr32(E1000_CTRL, ctrl);
6756
6757                 /* Allow time for pending master requests to run */
6758                 igb_disable_pcie_master(hw);
6759
6760                 wr32(E1000_WUC, E1000_WUC_PME_EN);
6761                 wr32(E1000_WUFC, wufc);
6762         } else {
6763                 wr32(E1000_WUC, 0);
6764                 wr32(E1000_WUFC, 0);
6765         }
6766
6767         *enable_wake = wufc || adapter->en_mng_pt;
6768         if (!*enable_wake)
6769                 igb_power_down_link(adapter);
6770         else
6771                 igb_power_up_link(adapter);
6772
6773         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
6774          * would have already happened in close and is redundant. */
6775         igb_release_hw_control(adapter);
6776
6777         pci_disable_device(pdev);
6778
6779         return 0;
6780 }
6781
6782 #ifdef CONFIG_PM
6783 #ifdef CONFIG_PM_SLEEP
6784 static int igb_suspend(struct device *dev)
6785 {
6786         int retval;
6787         bool wake;
6788         struct pci_dev *pdev = to_pci_dev(dev);
6789
6790         retval = __igb_shutdown(pdev, &wake, 0);
6791         if (retval)
6792                 return retval;
6793
6794         if (wake) {
6795                 pci_prepare_to_sleep(pdev);
6796         } else {
6797                 pci_wake_from_d3(pdev, false);
6798                 pci_set_power_state(pdev, PCI_D3hot);
6799         }
6800
6801         return 0;
6802 }
6803 #endif /* CONFIG_PM_SLEEP */
6804
6805 static int igb_resume(struct device *dev)
6806 {
6807         struct pci_dev *pdev = to_pci_dev(dev);
6808         struct net_device *netdev = pci_get_drvdata(pdev);
6809         struct igb_adapter *adapter = netdev_priv(netdev);
6810         struct e1000_hw *hw = &adapter->hw;
6811         u32 err;
6812
6813         pci_set_power_state(pdev, PCI_D0);
6814         pci_restore_state(pdev);
6815         pci_save_state(pdev);
6816
6817         err = pci_enable_device_mem(pdev);
6818         if (err) {
6819                 dev_err(&pdev->dev,
6820                         "igb: Cannot enable PCI device from suspend\n");
6821                 return err;
6822         }
6823         pci_set_master(pdev);
6824
6825         pci_enable_wake(pdev, PCI_D3hot, 0);
6826         pci_enable_wake(pdev, PCI_D3cold, 0);
6827
6828         if (igb_init_interrupt_scheme(adapter, true)) {
6829                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
6830                 return -ENOMEM;
6831         }
6832
6833         igb_reset(adapter);
6834
6835         /* let the f/w know that the h/w is now under the control of the
6836          * driver. */
6837         igb_get_hw_control(adapter);
6838
6839         wr32(E1000_WUS, ~0);
6840
6841         if (netdev->flags & IFF_UP) {
6842                 rtnl_lock();
6843                 err = __igb_open(netdev, true);
6844                 rtnl_unlock();
6845                 if (err)
6846                         return err;
6847         }
6848
6849         netif_device_attach(netdev);
6850         return 0;
6851 }
6852
6853 #ifdef CONFIG_PM_RUNTIME
6854 static int igb_runtime_idle(struct device *dev)
6855 {
6856         struct pci_dev *pdev = to_pci_dev(dev);
6857         struct net_device *netdev = pci_get_drvdata(pdev);
6858         struct igb_adapter *adapter = netdev_priv(netdev);
6859
6860         if (!igb_has_link(adapter))
6861                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
6862
6863         return -EBUSY;
6864 }
6865
6866 static int igb_runtime_suspend(struct device *dev)
6867 {
6868         struct pci_dev *pdev = to_pci_dev(dev);
6869         int retval;
6870         bool wake;
6871
6872         retval = __igb_shutdown(pdev, &wake, 1);
6873         if (retval)
6874                 return retval;
6875
6876         if (wake) {
6877                 pci_prepare_to_sleep(pdev);
6878         } else {
6879                 pci_wake_from_d3(pdev, false);
6880                 pci_set_power_state(pdev, PCI_D3hot);
6881         }
6882
6883         return 0;
6884 }
6885
6886 static int igb_runtime_resume(struct device *dev)
6887 {
6888         return igb_resume(dev);
6889 }
6890 #endif /* CONFIG_PM_RUNTIME */
6891 #endif
6892
6893 static void igb_shutdown(struct pci_dev *pdev)
6894 {
6895         bool wake;
6896
6897         __igb_shutdown(pdev, &wake, 0);
6898
6899         if (system_state == SYSTEM_POWER_OFF) {
6900                 pci_wake_from_d3(pdev, wake);
6901                 pci_set_power_state(pdev, PCI_D3hot);
6902         }
6903 }
6904
6905 #ifdef CONFIG_NET_POLL_CONTROLLER
6906 /*
6907  * Polling 'interrupt' - used by things like netconsole to send skbs
6908  * without having to re-enable interrupts. It's not called while
6909  * the interrupt routine is executing.
6910  */
6911 static void igb_netpoll(struct net_device *netdev)
6912 {
6913         struct igb_adapter *adapter = netdev_priv(netdev);
6914         struct e1000_hw *hw = &adapter->hw;
6915         struct igb_q_vector *q_vector;
6916         int i;
6917
6918         for (i = 0; i < adapter->num_q_vectors; i++) {
6919                 q_vector = adapter->q_vector[i];
6920                 if (adapter->msix_entries)
6921                         wr32(E1000_EIMC, q_vector->eims_value);
6922                 else
6923                         igb_irq_disable(adapter);
6924                 napi_schedule(&q_vector->napi);
6925         }
6926 }
6927 #endif /* CONFIG_NET_POLL_CONTROLLER */
6928
6929 /**
6930  * igb_io_error_detected - called when PCI error is detected
6931  * @pdev: Pointer to PCI device
6932  * @state: The current pci connection state
6933  *
6934  * This function is called after a PCI bus error affecting
6935  * this device has been detected.
6936  */
6937 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
6938                                               pci_channel_state_t state)
6939 {
6940         struct net_device *netdev = pci_get_drvdata(pdev);
6941         struct igb_adapter *adapter = netdev_priv(netdev);
6942
6943         netif_device_detach(netdev);
6944
6945         if (state == pci_channel_io_perm_failure)
6946                 return PCI_ERS_RESULT_DISCONNECT;
6947
6948         if (netif_running(netdev))
6949                 igb_down(adapter);
6950         pci_disable_device(pdev);
6951
6952         /* Request a slot slot reset. */
6953         return PCI_ERS_RESULT_NEED_RESET;
6954 }
6955
6956 /**
6957  * igb_io_slot_reset - called after the pci bus has been reset.
6958  * @pdev: Pointer to PCI device
6959  *
6960  * Restart the card from scratch, as if from a cold-boot. Implementation
6961  * resembles the first-half of the igb_resume routine.
6962  */
6963 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
6964 {
6965         struct net_device *netdev = pci_get_drvdata(pdev);
6966         struct igb_adapter *adapter = netdev_priv(netdev);
6967         struct e1000_hw *hw = &adapter->hw;
6968         pci_ers_result_t result;
6969         int err;
6970
6971         if (pci_enable_device_mem(pdev)) {
6972                 dev_err(&pdev->dev,
6973                         "Cannot re-enable PCI device after reset.\n");
6974                 result = PCI_ERS_RESULT_DISCONNECT;
6975         } else {
6976                 pci_set_master(pdev);
6977                 pci_restore_state(pdev);
6978                 pci_save_state(pdev);
6979
6980                 pci_enable_wake(pdev, PCI_D3hot, 0);
6981                 pci_enable_wake(pdev, PCI_D3cold, 0);
6982
6983                 igb_reset(adapter);
6984                 wr32(E1000_WUS, ~0);
6985                 result = PCI_ERS_RESULT_RECOVERED;
6986         }
6987
6988         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6989         if (err) {
6990                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
6991                         "failed 0x%0x\n", err);
6992                 /* non-fatal, continue */
6993         }
6994
6995         return result;
6996 }
6997
6998 /**
6999  * igb_io_resume - called when traffic can start flowing again.
7000  * @pdev: Pointer to PCI device
7001  *
7002  * This callback is called when the error recovery driver tells us that
7003  * its OK to resume normal operation. Implementation resembles the
7004  * second-half of the igb_resume routine.
7005  */
7006 static void igb_io_resume(struct pci_dev *pdev)
7007 {
7008         struct net_device *netdev = pci_get_drvdata(pdev);
7009         struct igb_adapter *adapter = netdev_priv(netdev);
7010
7011         if (netif_running(netdev)) {
7012                 if (igb_up(adapter)) {
7013                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7014                         return;
7015                 }
7016         }
7017
7018         netif_device_attach(netdev);
7019
7020         /* let the f/w know that the h/w is now under the control of the
7021          * driver. */
7022         igb_get_hw_control(adapter);
7023 }
7024
7025 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7026                              u8 qsel)
7027 {
7028         u32 rar_low, rar_high;
7029         struct e1000_hw *hw = &adapter->hw;
7030
7031         /* HW expects these in little endian so we reverse the byte order
7032          * from network order (big endian) to little endian
7033          */
7034         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7035                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7036         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7037
7038         /* Indicate to hardware the Address is Valid. */
7039         rar_high |= E1000_RAH_AV;
7040
7041         if (hw->mac.type == e1000_82575)
7042                 rar_high |= E1000_RAH_POOL_1 * qsel;
7043         else
7044                 rar_high |= E1000_RAH_POOL_1 << qsel;
7045
7046         wr32(E1000_RAL(index), rar_low);
7047         wrfl();
7048         wr32(E1000_RAH(index), rar_high);
7049         wrfl();
7050 }
7051
7052 static int igb_set_vf_mac(struct igb_adapter *adapter,
7053                           int vf, unsigned char *mac_addr)
7054 {
7055         struct e1000_hw *hw = &adapter->hw;
7056         /* VF MAC addresses start at end of receive addresses and moves
7057          * torwards the first, as a result a collision should not be possible */
7058         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7059
7060         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7061
7062         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7063
7064         return 0;
7065 }
7066
7067 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7068 {
7069         struct igb_adapter *adapter = netdev_priv(netdev);
7070         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7071                 return -EINVAL;
7072         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7073         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7074         dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7075                                       " change effective.");
7076         if (test_bit(__IGB_DOWN, &adapter->state)) {
7077                 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7078                          " but the PF device is not up.\n");
7079                 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7080                          " attempting to use the VF device.\n");
7081         }
7082         return igb_set_vf_mac(adapter, vf, mac);
7083 }
7084
7085 static int igb_link_mbps(int internal_link_speed)
7086 {
7087         switch (internal_link_speed) {
7088         case SPEED_100:
7089                 return 100;
7090         case SPEED_1000:
7091                 return 1000;
7092         default:
7093                 return 0;
7094         }
7095 }
7096
7097 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7098                                   int link_speed)
7099 {
7100         int rf_dec, rf_int;
7101         u32 bcnrc_val;
7102
7103         if (tx_rate != 0) {
7104                 /* Calculate the rate factor values to set */
7105                 rf_int = link_speed / tx_rate;
7106                 rf_dec = (link_speed - (rf_int * tx_rate));
7107                 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7108
7109                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7110                 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7111                                E1000_RTTBCNRC_RF_INT_MASK);
7112                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7113         } else {
7114                 bcnrc_val = 0;
7115         }
7116
7117         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7118         /*
7119          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7120          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7121          */
7122         wr32(E1000_RTTBCNRM, 0x14);
7123         wr32(E1000_RTTBCNRC, bcnrc_val);
7124 }
7125
7126 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7127 {
7128         int actual_link_speed, i;
7129         bool reset_rate = false;
7130
7131         /* VF TX rate limit was not set or not supported */
7132         if ((adapter->vf_rate_link_speed == 0) ||
7133             (adapter->hw.mac.type != e1000_82576))
7134                 return;
7135
7136         actual_link_speed = igb_link_mbps(adapter->link_speed);
7137         if (actual_link_speed != adapter->vf_rate_link_speed) {
7138                 reset_rate = true;
7139                 adapter->vf_rate_link_speed = 0;
7140                 dev_info(&adapter->pdev->dev,
7141                          "Link speed has been changed. VF Transmit "
7142                          "rate is disabled\n");
7143         }
7144
7145         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7146                 if (reset_rate)
7147                         adapter->vf_data[i].tx_rate = 0;
7148
7149                 igb_set_vf_rate_limit(&adapter->hw, i,
7150                                       adapter->vf_data[i].tx_rate,
7151                                       actual_link_speed);
7152         }
7153 }
7154
7155 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7156 {
7157         struct igb_adapter *adapter = netdev_priv(netdev);
7158         struct e1000_hw *hw = &adapter->hw;
7159         int actual_link_speed;
7160
7161         if (hw->mac.type != e1000_82576)
7162                 return -EOPNOTSUPP;
7163
7164         actual_link_speed = igb_link_mbps(adapter->link_speed);
7165         if ((vf >= adapter->vfs_allocated_count) ||
7166             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7167             (tx_rate < 0) || (tx_rate > actual_link_speed))
7168                 return -EINVAL;
7169
7170         adapter->vf_rate_link_speed = actual_link_speed;
7171         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7172         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7173
7174         return 0;
7175 }
7176
7177 static int igb_ndo_get_vf_config(struct net_device *netdev,
7178                                  int vf, struct ifla_vf_info *ivi)
7179 {
7180         struct igb_adapter *adapter = netdev_priv(netdev);
7181         if (vf >= adapter->vfs_allocated_count)
7182                 return -EINVAL;
7183         ivi->vf = vf;
7184         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7185         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7186         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7187         ivi->qos = adapter->vf_data[vf].pf_qos;
7188         return 0;
7189 }
7190
7191 static void igb_vmm_control(struct igb_adapter *adapter)
7192 {
7193         struct e1000_hw *hw = &adapter->hw;
7194         u32 reg;
7195
7196         switch (hw->mac.type) {
7197         case e1000_82575:
7198         case e1000_i210:
7199         case e1000_i211:
7200         default:
7201                 /* replication is not supported for 82575 */
7202                 return;
7203         case e1000_82576:
7204                 /* notify HW that the MAC is adding vlan tags */
7205                 reg = rd32(E1000_DTXCTL);
7206                 reg |= E1000_DTXCTL_VLAN_ADDED;
7207                 wr32(E1000_DTXCTL, reg);
7208         case e1000_82580:
7209                 /* enable replication vlan tag stripping */
7210                 reg = rd32(E1000_RPLOLR);
7211                 reg |= E1000_RPLOLR_STRVLAN;
7212                 wr32(E1000_RPLOLR, reg);
7213         case e1000_i350:
7214                 /* none of the above registers are supported by i350 */
7215                 break;
7216         }
7217
7218         if (adapter->vfs_allocated_count) {
7219                 igb_vmdq_set_loopback_pf(hw, true);
7220                 igb_vmdq_set_replication_pf(hw, true);
7221                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7222                                                 adapter->vfs_allocated_count);
7223         } else {
7224                 igb_vmdq_set_loopback_pf(hw, false);
7225                 igb_vmdq_set_replication_pf(hw, false);
7226         }
7227 }
7228
7229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7230 {
7231         struct e1000_hw *hw = &adapter->hw;
7232         u32 dmac_thr;
7233         u16 hwm;
7234
7235         if (hw->mac.type > e1000_82580) {
7236                 if (adapter->flags & IGB_FLAG_DMAC) {
7237                         u32 reg;
7238
7239                         /* force threshold to 0. */
7240                         wr32(E1000_DMCTXTH, 0);
7241
7242                         /*
7243                          * DMA Coalescing high water mark needs to be greater
7244                          * than the Rx threshold. Set hwm to PBA - max frame
7245                          * size in 16B units, capping it at PBA - 6KB.
7246                          */
7247                         hwm = 64 * pba - adapter->max_frame_size / 16;
7248                         if (hwm < 64 * (pba - 6))
7249                                 hwm = 64 * (pba - 6);
7250                         reg = rd32(E1000_FCRTC);
7251                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7252                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7253                                 & E1000_FCRTC_RTH_COAL_MASK);
7254                         wr32(E1000_FCRTC, reg);
7255
7256                         /*
7257                          * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7258                          * frame size, capping it at PBA - 10KB.
7259                          */
7260                         dmac_thr = pba - adapter->max_frame_size / 512;
7261                         if (dmac_thr < pba - 10)
7262                                 dmac_thr = pba - 10;
7263                         reg = rd32(E1000_DMACR);
7264                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7265                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7266                                 & E1000_DMACR_DMACTHR_MASK);
7267
7268                         /* transition to L0x or L1 if available..*/
7269                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7270
7271                         /* watchdog timer= +-1000 usec in 32usec intervals */
7272                         reg |= (1000 >> 5);
7273
7274                         /* Disable BMC-to-OS Watchdog Enable */
7275                         reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7276                         wr32(E1000_DMACR, reg);
7277
7278                         /*
7279                          * no lower threshold to disable
7280                          * coalescing(smart fifb)-UTRESH=0
7281                          */
7282                         wr32(E1000_DMCRTRH, 0);
7283
7284                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7285
7286                         wr32(E1000_DMCTLX, reg);
7287
7288                         /*
7289                          * free space in tx packet buffer to wake from
7290                          * DMA coal
7291                          */
7292                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7293                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7294
7295                         /*
7296                          * make low power state decision controlled
7297                          * by DMA coal
7298                          */
7299                         reg = rd32(E1000_PCIEMISC);
7300                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7301                         wr32(E1000_PCIEMISC, reg);
7302                 } /* endif adapter->dmac is not disabled */
7303         } else if (hw->mac.type == e1000_82580) {
7304                 u32 reg = rd32(E1000_PCIEMISC);
7305                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7306                 wr32(E1000_DMACR, 0);
7307         }
7308 }
7309
7310 /* igb_main.c */