drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2012 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/init.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/bitops.h>
  36 #include <linux/irq.h>
  37 #include <linux/delay.h>
  38 #include <asm/byteorder.h>
  39 #include <linux/time.h>
  40 #include <linux/ethtool.h>
  41 #include <linux/mii.h>
  42 #include <linux/if_vlan.h>
  43 #include <net/ip.h>
  44 #include <net/ipv6.h>
  45 #include <net/tcp.h>
  46 #include <net/checksum.h>
  47 #include <net/ip6_checksum.h>
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/crc32c.h>
  51 #include <linux/prefetch.h>
  52 #include <linux/zlib.h>
  53 #include <linux/io.h>
  54 #include <linux/semaphore.h>
  55 #include <linux/stringify.h>
  56 #include <linux/vmalloc.h>
  57
  58 #include "bnx2x.h"
  59 #include "bnx2x_init.h"
  60 #include "bnx2x_init_ops.h"
  61 #include "bnx2x_cmn.h"
  62 #include "bnx2x_vfpf.h"
  63 #include "bnx2x_sriov.h"
  64 #include "bnx2x_dcb.h"
  65 #include "bnx2x_sp.h"
  66
  67 #include <linux/firmware.h>
  68 #include "bnx2x_fw_file_hdr.h"
  69 /* FW files */
  70 #define FW_FILE_VERSION                                 \
  71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  78
  79 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
  80
  81 /* Time in jiffies before concluding the transmitter is hung */
  82 #define TX_TIMEOUT              (5*HZ)
  83
  84 static char version[] =
  85         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  86         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  87
  88 MODULE_AUTHOR("Eliezer Tamir");
  89 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  90                    "BCM57710/57711/57711E/"
  91                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  92                    "57840/57840_MF Driver");
  93 MODULE_LICENSE("GPL");
  94 MODULE_VERSION(DRV_MODULE_VERSION);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  97 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  98
  99
 100 int num_queues;
 101 module_param(num_queues, int, 0);
 102 MODULE_PARM_DESC(num_queues,
 103                  " Set number of queues (default is as a number of CPUs)");
 104
 105 static int disable_tpa;
 106 module_param(disable_tpa, int, 0);
 107 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 108
 109 #define INT_MODE_INTx                   1
 110 #define INT_MODE_MSI                    2
 111 int int_mode;
 112 module_param(int_mode, int, 0);
 113 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 114                                 "(1 INT#x; 2 MSI)");
 115
 116 static int dropless_fc;
 117 module_param(dropless_fc, int, 0);
 118 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 119
 120 static int mrrs = -1;
 121 module_param(mrrs, int, 0);
 122 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 123
 124 static int debug;
 125 module_param(debug, int, 0);
 126 MODULE_PARM_DESC(debug, " Default debug msglevel");
 127
 128
 129
 130 struct workqueue_struct *bnx2x_wq;
 131
 132 enum bnx2x_board_type {
 133         BCM57710 = 0,
 134         BCM57711,
 135         BCM57711E,
 136         BCM57712,
 137         BCM57712_MF,
 138         BCM57712_VF,
 139         BCM57800,
 140         BCM57800_MF,
 141         BCM57800_VF,
 142         BCM57810,
 143         BCM57810_MF,
 144         BCM57810_VF,
 145         BCM57840_4_10,
 146         BCM57840_2_20,
 147         BCM57840_MF,
 148         BCM57840_VF,
 149         BCM57811,
 150         BCM57811_MF,
 151         BCM57840_O,
 152         BCM57840_MFO,
 153         BCM57811_VF
 154 };
 155
 156 /* indexed by board_type, above */
 157 static struct {
 158         char *name;
 159 } board_info[] = {
 160         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 161         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 162         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 163         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 164         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 165         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 166         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 167         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 168         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 169         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 170         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 171         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 173         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 174         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 175         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 176         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 177         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 178         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 179         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 180         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 181 };
 182
 183 #ifndef PCI_DEVICE_ID_NX2_57710
 184 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 185 #endif
 186 #ifndef PCI_DEVICE_ID_NX2_57711
 187 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 188 #endif
 189 #ifndef PCI_DEVICE_ID_NX2_57711E
 190 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57712
 193 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 196 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57800
 199 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 202 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57810
 205 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 208 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57840_O
 211 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 214 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 217 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 220 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 223 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57811
 226 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 229 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 230 #endif
 231 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 232         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 233         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 234         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 235         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 236         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 237         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 238         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 239         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 240         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 241         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 242         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 243         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 244         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 245         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 246         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 247         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 248         { 0 }
 249 };
 250
 251 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 252
 253 /* Global resources for unloading a previously loaded device */
 254 #define BNX2X_PREV_WAIT_NEEDED 1
 255 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 256 static LIST_HEAD(bnx2x_prev_list);
 257 /****************************************************************************
 258 * General service functions
 259 ****************************************************************************/
 260
 261 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 262                                        u32 addr, dma_addr_t mapping)
 263 {
 264         REG_WR(bp,  addr, U64_LO(mapping));
 265         REG_WR(bp,  addr + 4, U64_HI(mapping));
 266 }
 267
 268 static void storm_memset_spq_addr(struct bnx2x *bp,
 269                                   dma_addr_t mapping, u16 abs_fid)
 270 {
 271         u32 addr = XSEM_REG_FAST_MEMORY +
 272                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 273
 274         __storm_memset_dma_mapping(bp, addr, mapping);
 275 }
 276
 277 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 278                                   u16 pf_id)
 279 {
 280         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 281                 pf_id);
 282         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 283                 pf_id);
 284         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 285                 pf_id);
 286         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 287                 pf_id);
 288 }
 289
 290 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 291                                  u8 enable)
 292 {
 293         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 294                 enable);
 295         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 296                 enable);
 297         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 298                 enable);
 299         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 300                 enable);
 301 }
 302
 303 static void storm_memset_eq_data(struct bnx2x *bp,
 304                                  struct event_ring_data *eq_data,
 305                                 u16 pfid)
 306 {
 307         size_t size = sizeof(struct event_ring_data);
 308
 309         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 310
 311         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 312 }
 313
 314 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 315                                  u16 pfid)
 316 {
 317         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 318         REG_WR16(bp, addr, eq_prod);
 319 }
 320
 321 /* used only at init
 322  * locking is done by mcp
 323  */
 324 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 325 {
 326         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 327         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 328         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 329                                PCICFG_VENDOR_ID_OFFSET);
 330 }
 331
 332 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 333 {
 334         u32 val;
 335
 336         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 337         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 338         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 339                                PCICFG_VENDOR_ID_OFFSET);
 340
 341         return val;
 342 }
 343
 344 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 345 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 346 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 347 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 348 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 349
 350
 351 /* copy command into DMAE command memory and set DMAE command go */
 352 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 353 {
 354         u32 cmd_offset;
 355         int i;
 356
 357         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 358         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 359                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 360         }
 361         REG_WR(bp, dmae_reg_go_c[idx], 1);
 362 }
 363
 364 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 365 {
 366         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 367                            DMAE_CMD_C_ENABLE);
 368 }
 369
 370 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 371 {
 372         return opcode & ~DMAE_CMD_SRC_RESET;
 373 }
 374
 375 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 376                              bool with_comp, u8 comp_type)
 377 {
 378         u32 opcode = 0;
 379
 380         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 381                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 382
 383         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 384
 385         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 386         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 387                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 388         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 389
 390 #ifdef __BIG_ENDIAN
 391         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 392 #else
 393         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 394 #endif
 395         if (with_comp)
 396                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 397         return opcode;
 398 }
 399
 400 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 401                                       struct dmae_command *dmae,
 402                                       u8 src_type, u8 dst_type)
 403 {
 404         memset(dmae, 0, sizeof(struct dmae_command));
 405
 406         /* set the opcode */
 407         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 408                                          true, DMAE_COMP_PCI);
 409
 410         /* fill in the completion parameters */
 411         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 412         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 413         dmae->comp_val = DMAE_COMP_VAL;
 414 }
 415
 416 /* issue a dmae command over the init-channel and wailt for completion */
 417 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
 418                                       struct dmae_command *dmae)
 419 {
 420         u32 *wb_comp = bnx2x_sp(bp, wb_comp);
 421         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 422         int rc = 0;
 423
 424         /*
 425          * Lock the dmae channel. Disable BHs to prevent a dead-lock
 426          * as long as this code is called both from syscall context and
 427          * from ndo_set_rx_mode() flow that may be called from BH.
 428          */
 429         spin_lock_bh(&bp->dmae_lock);
 430
 431         /* reset completion */
 432         *wb_comp = 0;
 433
 434         /* post the command on the channel used for initializations */
 435         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 436
 437         /* wait for completion */
 438         udelay(5);
 439         while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 440
 441                 if (!cnt ||
 442                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 443                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 444                         BNX2X_ERR("DMAE timeout!\n");
 445                         rc = DMAE_TIMEOUT;
 446                         goto unlock;
 447                 }
 448                 cnt--;
 449                 udelay(50);
 450         }
 451         if (*wb_comp & DMAE_PCI_ERR_FLAG) {
 452                 BNX2X_ERR("DMAE PCI error!\n");
 453                 rc = DMAE_PCI_ERROR;
 454         }
 455
 456 unlock:
 457         spin_unlock_bh(&bp->dmae_lock);
 458         return rc;
 459 }
 460
 461 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 462                       u32 len32)
 463 {
 464         struct dmae_command dmae;
 465
 466         if (!bp->dmae_ready) {
 467                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 468
 469                 if (CHIP_IS_E1(bp))
 470                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 471                 else
 472                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 473                 return;
 474         }
 475
 476         /* set opcode and fixed command fields */
 477         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 478
 479         /* fill in addresses and len */
 480         dmae.src_addr_lo = U64_LO(dma_addr);
 481         dmae.src_addr_hi = U64_HI(dma_addr);
 482         dmae.dst_addr_lo = dst_addr >> 2;
 483         dmae.dst_addr_hi = 0;
 484         dmae.len = len32;
 485
 486         /* issue the command and wait for completion */
 487         bnx2x_issue_dmae_with_comp(bp, &dmae);
 488 }
 489
 490 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 491 {
 492         struct dmae_command dmae;
 493
 494         if (!bp->dmae_ready) {
 495                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 496                 int i;
 497
 498                 if (CHIP_IS_E1(bp))
 499                         for (i = 0; i < len32; i++)
 500                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 501                 else
 502                         for (i = 0; i < len32; i++)
 503                                 data[i] = REG_RD(bp, src_addr + i*4);
 504
 505                 return;
 506         }
 507
 508         /* set opcode and fixed command fields */
 509         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 510
 511         /* fill in addresses and len */
 512         dmae.src_addr_lo = src_addr >> 2;
 513         dmae.src_addr_hi = 0;
 514         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 515         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 516         dmae.len = len32;
 517
 518         /* issue the command and wait for completion */
 519         bnx2x_issue_dmae_with_comp(bp, &dmae);
 520 }
 521
 522 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 523                                       u32 addr, u32 len)
 524 {
 525         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 526         int offset = 0;
 527
 528         while (len > dmae_wr_max) {
 529                 bnx2x_write_dmae(bp, phys_addr + offset,
 530                                  addr + offset, dmae_wr_max);
 531                 offset += dmae_wr_max * 4;
 532                 len -= dmae_wr_max;
 533         }
 534
 535         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 536 }
 537
 538 static int bnx2x_mc_assert(struct bnx2x *bp)
 539 {
 540         char last_idx;
 541         int i, rc = 0;
 542         u32 row0, row1, row2, row3;
 543
 544         /* XSTORM */
 545         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 546                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 547         if (last_idx)
 548                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 549
 550         /* print the asserts */
 551         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 552
 553                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 554                               XSTORM_ASSERT_LIST_OFFSET(i));
 555                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 556                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 557                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 558                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 559                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 560                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 561
 562                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 563                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 564                                   i, row3, row2, row1, row0);
 565                         rc++;
 566                 } else {
 567                         break;
 568                 }
 569         }
 570
 571         /* TSTORM */
 572         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 573                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 574         if (last_idx)
 575                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 576
 577         /* print the asserts */
 578         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 579
 580                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 581                               TSTORM_ASSERT_LIST_OFFSET(i));
 582                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 583                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 584                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 585                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 586                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 587                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 588
 589                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 590                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 591                                   i, row3, row2, row1, row0);
 592                         rc++;
 593                 } else {
 594                         break;
 595                 }
 596         }
 597
 598         /* CSTORM */
 599         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 600                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 601         if (last_idx)
 602                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 603
 604         /* print the asserts */
 605         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 606
 607                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 608                               CSTORM_ASSERT_LIST_OFFSET(i));
 609                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 610                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 611                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 612                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 613                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 614                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 615
 616                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 617                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 618                                   i, row3, row2, row1, row0);
 619                         rc++;
 620                 } else {
 621                         break;
 622                 }
 623         }
 624
 625         /* USTORM */
 626         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 627                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 628         if (last_idx)
 629                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 630
 631         /* print the asserts */
 632         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 633
 634                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 635                               USTORM_ASSERT_LIST_OFFSET(i));
 636                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 637                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 638                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 639                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 640                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 641                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 642
 643                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 644                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 645                                   i, row3, row2, row1, row0);
 646                         rc++;
 647                 } else {
 648                         break;
 649                 }
 650         }
 651
 652         return rc;
 653 }
 654
 655 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 656 {
 657         u32 addr, val;
 658         u32 mark, offset;
 659         __be32 data[9];
 660         int word;
 661         u32 trace_shmem_base;
 662         if (BP_NOMCP(bp)) {
 663                 BNX2X_ERR("NO MCP - can not dump\n");
 664                 return;
 665         }
 666         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 667                 (bp->common.bc_ver & 0xff0000) >> 16,
 668                 (bp->common.bc_ver & 0xff00) >> 8,
 669                 (bp->common.bc_ver & 0xff));
 670
 671         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 672         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 673                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 674
 675         if (BP_PATH(bp) == 0)
 676                 trace_shmem_base = bp->common.shmem_base;
 677         else
 678                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 679         addr = trace_shmem_base - 0x800;
 680
 681         /* validate TRCB signature */
 682         mark = REG_RD(bp, addr);
 683         if (mark != MFW_TRACE_SIGNATURE) {
 684                 BNX2X_ERR("Trace buffer signature is missing.");
 685                 return ;
 686         }
 687
 688         /* read cyclic buffer pointer */
 689         addr += 4;
 690         mark = REG_RD(bp, addr);
 691         mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
 692                         + ((mark + 0x3) & ~0x3) - 0x08000000;
 693         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 694
 695         printk("%s", lvl);
 696         for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
 697                 for (word = 0; word < 8; word++)
 698                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 699                 data[8] = 0x0;
 700                 pr_cont("%s", (char *)data);
 701         }
 702         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 703                 for (word = 0; word < 8; word++)
 704                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 705                 data[8] = 0x0;
 706                 pr_cont("%s", (char *)data);
 707         }
 708         printk("%s" "end of fw dump\n", lvl);
 709 }
 710
 711 static void bnx2x_fw_dump(struct bnx2x *bp)
 712 {
 713         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 714 }
 715
 716 void bnx2x_panic_dump(struct bnx2x *bp)
 717 {
 718         int i;
 719         u16 j;
 720         struct hc_sp_status_block_data sp_sb_data;
 721         int func = BP_FUNC(bp);
 722 #ifdef BNX2X_STOP_ON_ERROR
 723         u16 start = 0, end = 0;
 724         u8 cos;
 725 #endif
 726
 727         bp->stats_state = STATS_STATE_DISABLED;
 728         bp->eth_stats.unrecoverable_error++;
 729         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 730
 731         BNX2X_ERR("begin crash dump -----------------\n");
 732
 733         /* Indices */
 734         /* Common */
 735         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 736                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 737                   bp->spq_prod_idx, bp->stats_counter);
 738         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 739                   bp->def_status_blk->atten_status_block.attn_bits,
 740                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 741                   bp->def_status_blk->atten_status_block.status_block_id,
 742                   bp->def_status_blk->atten_status_block.attn_bits_index);
 743         BNX2X_ERR("     def (");
 744         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 745                 pr_cont("0x%x%s",
 746                         bp->def_status_blk->sp_sb.index_values[i],
 747                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 748
 749         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 750                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 751                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 752                         i*sizeof(u32));
 753
 754         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 755                sp_sb_data.igu_sb_id,
 756                sp_sb_data.igu_seg_id,
 757                sp_sb_data.p_func.pf_id,
 758                sp_sb_data.p_func.vnic_id,
 759                sp_sb_data.p_func.vf_id,
 760                sp_sb_data.p_func.vf_valid,
 761                sp_sb_data.state);
 762
 763
 764         for_each_eth_queue(bp, i) {
 765                 struct bnx2x_fastpath *fp = &bp->fp[i];
 766                 int loop;
 767                 struct hc_status_block_data_e2 sb_data_e2;
 768                 struct hc_status_block_data_e1x sb_data_e1x;
 769                 struct hc_status_block_sm  *hc_sm_p =
 770                         CHIP_IS_E1x(bp) ?
 771                         sb_data_e1x.common.state_machine :
 772                         sb_data_e2.common.state_machine;
 773                 struct hc_index_data *hc_index_p =
 774                         CHIP_IS_E1x(bp) ?
 775                         sb_data_e1x.index_data :
 776                         sb_data_e2.index_data;
 777                 u8 data_size, cos;
 778                 u32 *sb_data_p;
 779                 struct bnx2x_fp_txdata txdata;
 780
 781                 /* Rx */
 782                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 783                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 784                           fp->rx_comp_prod,
 785                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 786                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 787                           fp->rx_sge_prod, fp->last_max_sge,
 788                           le16_to_cpu(fp->fp_hc_idx));
 789
 790                 /* Tx */
 791                 for_each_cos_in_tx_queue(fp, cos)
 792                 {
 793                         txdata = *fp->txdata_ptr[cos];
 794                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 795                                   i, txdata.tx_pkt_prod,
 796                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 797                                   txdata.tx_bd_cons,
 798                                   le16_to_cpu(*txdata.tx_cons_sb));
 799                 }
 800
 801                 loop = CHIP_IS_E1x(bp) ?
 802                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 803
 804                 /* host sb data */
 805
 806                 if (IS_FCOE_FP(fp))
 807                         continue;
 808
 809                 BNX2X_ERR("     run indexes (");
 810                 for (j = 0; j < HC_SB_MAX_SM; j++)
 811                         pr_cont("0x%x%s",
 812                                fp->sb_running_index[j],
 813                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
 814
 815                 BNX2X_ERR("     indexes (");
 816                 for (j = 0; j < loop; j++)
 817                         pr_cont("0x%x%s",
 818                                fp->sb_index_values[j],
 819                                (j == loop - 1) ? ")" : " ");
 820                 /* fw sb data */
 821                 data_size = CHIP_IS_E1x(bp) ?
 822                         sizeof(struct hc_status_block_data_e1x) :
 823                         sizeof(struct hc_status_block_data_e2);
 824                 data_size /= sizeof(u32);
 825                 sb_data_p = CHIP_IS_E1x(bp) ?
 826                         (u32 *)&sb_data_e1x :
 827                         (u32 *)&sb_data_e2;
 828                 /* copy sb data in here */
 829                 for (j = 0; j < data_size; j++)
 830                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 831                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
 832                                 j * sizeof(u32));
 833
 834                 if (!CHIP_IS_E1x(bp)) {
 835                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 836                                 sb_data_e2.common.p_func.pf_id,
 837                                 sb_data_e2.common.p_func.vf_id,
 838                                 sb_data_e2.common.p_func.vf_valid,
 839                                 sb_data_e2.common.p_func.vnic_id,
 840                                 sb_data_e2.common.same_igu_sb_1b,
 841                                 sb_data_e2.common.state);
 842                 } else {
 843                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
 844                                 sb_data_e1x.common.p_func.pf_id,
 845                                 sb_data_e1x.common.p_func.vf_id,
 846                                 sb_data_e1x.common.p_func.vf_valid,
 847                                 sb_data_e1x.common.p_func.vnic_id,
 848                                 sb_data_e1x.common.same_igu_sb_1b,
 849                                 sb_data_e1x.common.state);
 850                 }
 851
 852                 /* SB_SMs data */
 853                 for (j = 0; j < HC_SB_MAX_SM; j++) {
 854                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
 855                                 j, hc_sm_p[j].__flags,
 856                                 hc_sm_p[j].igu_sb_id,
 857                                 hc_sm_p[j].igu_seg_id,
 858                                 hc_sm_p[j].time_to_expire,
 859                                 hc_sm_p[j].timer_value);
 860                 }
 861
 862                 /* Indecies data */
 863                 for (j = 0; j < loop; j++) {
 864                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
 865                                hc_index_p[j].flags,
 866                                hc_index_p[j].timeout);
 867                 }
 868         }
 869
 870 #ifdef BNX2X_STOP_ON_ERROR
 871         /* Rings */
 872         /* Rx */
 873         for_each_valid_rx_queue(bp, i) {
 874                 struct bnx2x_fastpath *fp = &bp->fp[i];
 875
 876                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
 877                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
 878                 for (j = start; j != end; j = RX_BD(j + 1)) {
 879                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
 880                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
 881
 882                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
 883                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
 884                 }
 885
 886                 start = RX_SGE(fp->rx_sge_prod);
 887                 end = RX_SGE(fp->last_max_sge);
 888                 for (j = start; j != end; j = RX_SGE(j + 1)) {
 889                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
 890                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
 891
 892                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
 893                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
 894                 }
 895
 896                 start = RCQ_BD(fp->rx_comp_cons - 10);
 897                 end = RCQ_BD(fp->rx_comp_cons + 503);
 898                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
 899                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
 900
 901                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
 902                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
 903                 }
 904         }
 905
 906         /* Tx */
 907         for_each_valid_tx_queue(bp, i) {
 908                 struct bnx2x_fastpath *fp = &bp->fp[i];
 909                 for_each_cos_in_tx_queue(fp, cos) {
 910                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
 911
 912                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
 913                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
 914                         for (j = start; j != end; j = TX_BD(j + 1)) {
 915                                 struct sw_tx_bd *sw_bd =
 916                                         &txdata->tx_buf_ring[j];
 917
 918                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
 919                                           i, cos, j, sw_bd->skb,
 920                                           sw_bd->first_bd);
 921                         }
 922
 923                         start = TX_BD(txdata->tx_bd_cons - 10);
 924                         end = TX_BD(txdata->tx_bd_cons + 254);
 925                         for (j = start; j != end; j = TX_BD(j + 1)) {
 926                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
 927
 928                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
 929                                           i, cos, j, tx_bd[0], tx_bd[1],
 930                                           tx_bd[2], tx_bd[3]);
 931                         }
 932                 }
 933         }
 934 #endif
 935         bnx2x_fw_dump(bp);
 936         bnx2x_mc_assert(bp);
 937         BNX2X_ERR("end crash dump -----------------\n");
 938 }
 939
 940 /*
 941  * FLR Support for E2
 942  *
 943  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
 944  * initialization.
 945  */
 946 #define FLR_WAIT_USEC           10000   /* 10 miliseconds */
 947 #define FLR_WAIT_INTERVAL       50      /* usec */
 948 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
 949
 950 struct pbf_pN_buf_regs {
 951         int pN;
 952         u32 init_crd;
 953         u32 crd;
 954         u32 crd_freed;
 955 };
 956
 957 struct pbf_pN_cmd_regs {
 958         int pN;
 959         u32 lines_occup;
 960         u32 lines_freed;
 961 };
 962
 963 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
 964                                      struct pbf_pN_buf_regs *regs,
 965                                      u32 poll_count)
 966 {
 967         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
 968         u32 cur_cnt = poll_count;
 969
 970         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
 971         crd = crd_start = REG_RD(bp, regs->crd);
 972         init_crd = REG_RD(bp, regs->init_crd);
 973
 974         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
 975         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
 976         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
 977
 978         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
 979                (init_crd - crd_start))) {
 980                 if (cur_cnt--) {
 981                         udelay(FLR_WAIT_INTERVAL);
 982                         crd = REG_RD(bp, regs->crd);
 983                         crd_freed = REG_RD(bp, regs->crd_freed);
 984                 } else {
 985                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
 986                            regs->pN);
 987                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
 988                            regs->pN, crd);
 989                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
 990                            regs->pN, crd_freed);
 991                         break;
 992                 }
 993         }
 994         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
 995            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
 996 }
 997
 998 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
 999                                      struct pbf_pN_cmd_regs *regs,
1000                                      u32 poll_count)
1001 {
1002         u32 occup, to_free, freed, freed_start;
1003         u32 cur_cnt = poll_count;
1004
1005         occup = to_free = REG_RD(bp, regs->lines_occup);
1006         freed = freed_start = REG_RD(bp, regs->lines_freed);
1007
1008         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1009         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1010
1011         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1012                 if (cur_cnt--) {
1013                         udelay(FLR_WAIT_INTERVAL);
1014                         occup = REG_RD(bp, regs->lines_occup);
1015                         freed = REG_RD(bp, regs->lines_freed);
1016                 } else {
1017                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1018                            regs->pN);
1019                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1020                            regs->pN, occup);
1021                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1022                            regs->pN, freed);
1023                         break;
1024                 }
1025         }
1026         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1027            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1028 }
1029
1030 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1031                                     u32 expected, u32 poll_count)
1032 {
1033         u32 cur_cnt = poll_count;
1034         u32 val;
1035
1036         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1037                 udelay(FLR_WAIT_INTERVAL);
1038
1039         return val;
1040 }
1041
1042 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1043                                            char *msg, u32 poll_cnt)
1044 {
1045         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1046         if (val != 0) {
1047                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1048                 return 1;
1049         }
1050         return 0;
1051 }
1052
1053 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1054 {
1055         /* adjust polling timeout */
1056         if (CHIP_REV_IS_EMUL(bp))
1057                 return FLR_POLL_CNT * 2000;
1058
1059         if (CHIP_REV_IS_FPGA(bp))
1060                 return FLR_POLL_CNT * 120;
1061
1062         return FLR_POLL_CNT;
1063 }
1064
1065 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1066 {
1067         struct pbf_pN_cmd_regs cmd_regs[] = {
1068                 {0, (CHIP_IS_E3B0(bp)) ?
1069                         PBF_REG_TQ_OCCUPANCY_Q0 :
1070                         PBF_REG_P0_TQ_OCCUPANCY,
1071                     (CHIP_IS_E3B0(bp)) ?
1072                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1073                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1074                 {1, (CHIP_IS_E3B0(bp)) ?
1075                         PBF_REG_TQ_OCCUPANCY_Q1 :
1076                         PBF_REG_P1_TQ_OCCUPANCY,
1077                     (CHIP_IS_E3B0(bp)) ?
1078                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1079                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1080                 {4, (CHIP_IS_E3B0(bp)) ?
1081                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1082                         PBF_REG_P4_TQ_OCCUPANCY,
1083                     (CHIP_IS_E3B0(bp)) ?
1084                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1085                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1086         };
1087
1088         struct pbf_pN_buf_regs buf_regs[] = {
1089                 {0, (CHIP_IS_E3B0(bp)) ?
1090                         PBF_REG_INIT_CRD_Q0 :
1091                         PBF_REG_P0_INIT_CRD ,
1092                     (CHIP_IS_E3B0(bp)) ?
1093                         PBF_REG_CREDIT_Q0 :
1094                         PBF_REG_P0_CREDIT,
1095                     (CHIP_IS_E3B0(bp)) ?
1096                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1097                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1098                 {1, (CHIP_IS_E3B0(bp)) ?
1099                         PBF_REG_INIT_CRD_Q1 :
1100                         PBF_REG_P1_INIT_CRD,
1101                     (CHIP_IS_E3B0(bp)) ?
1102                         PBF_REG_CREDIT_Q1 :
1103                         PBF_REG_P1_CREDIT,
1104                     (CHIP_IS_E3B0(bp)) ?
1105                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1106                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1107                 {4, (CHIP_IS_E3B0(bp)) ?
1108                         PBF_REG_INIT_CRD_LB_Q :
1109                         PBF_REG_P4_INIT_CRD,
1110                     (CHIP_IS_E3B0(bp)) ?
1111                         PBF_REG_CREDIT_LB_Q :
1112                         PBF_REG_P4_CREDIT,
1113                     (CHIP_IS_E3B0(bp)) ?
1114                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1115                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1116         };
1117
1118         int i;
1119
1120         /* Verify the command queues are flushed P0, P1, P4 */
1121         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1122                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1123
1124
1125         /* Verify the transmission buffers are flushed P0, P1, P4 */
1126         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1127                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1128 }
1129
1130 #define OP_GEN_PARAM(param) \
1131         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1132
1133 #define OP_GEN_TYPE(type) \
1134         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1135
1136 #define OP_GEN_AGG_VECT(index) \
1137         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1138
1139
1140 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1141                                          u32 poll_cnt)
1142 {
1143         struct sdm_op_gen op_gen = {0};
1144
1145         u32 comp_addr = BAR_CSTRORM_INTMEM +
1146                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1147         int ret = 0;
1148
1149         if (REG_RD(bp, comp_addr)) {
1150                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1151                 return 1;
1152         }
1153
1154         op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1155         op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1156         op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1157         op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1158
1159         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1160         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1161
1162         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1163                 BNX2X_ERR("FW final cleanup did not succeed\n");
1164                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1165                    (REG_RD(bp, comp_addr)));
1166                 ret = 1;
1167         }
1168         /* Zero completion for nxt FLR */
1169         REG_WR(bp, comp_addr, 0);
1170
1171         return ret;
1172 }
1173
1174 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1175 {
1176         u16 status;
1177
1178         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1179         return status & PCI_EXP_DEVSTA_TRPND;
1180 }
1181
1182 /* PF FLR specific routines
1183 */
1184 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1185 {
1186
1187         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1188         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1189                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1190                         "CFC PF usage counter timed out",
1191                         poll_cnt))
1192                 return 1;
1193
1194
1195         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1196         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1197                         DORQ_REG_PF_USAGE_CNT,
1198                         "DQ PF usage counter timed out",
1199                         poll_cnt))
1200                 return 1;
1201
1202         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1203         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1204                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1205                         "QM PF usage counter timed out",
1206                         poll_cnt))
1207                 return 1;
1208
1209         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1210         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1211                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1212                         "Timers VNIC usage counter timed out",
1213                         poll_cnt))
1214                 return 1;
1215         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1216                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1217                         "Timers NUM_SCANS usage counter timed out",
1218                         poll_cnt))
1219                 return 1;
1220
1221         /* Wait DMAE PF usage counter to zero */
1222         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1223                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1224                         "DMAE dommand register timed out",
1225                         poll_cnt))
1226                 return 1;
1227
1228         return 0;
1229 }
1230
1231 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1232 {
1233         u32 val;
1234
1235         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1236         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1237
1238         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1239         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1240
1241         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1242         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1243
1244         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1245         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1246
1247         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1248         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1249
1250         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1251         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1252
1253         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1254         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1255
1256         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1257         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1258            val);
1259 }
1260
1261 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1262 {
1263         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1264
1265         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1266
1267         /* Re-enable PF target read access */
1268         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1269
1270         /* Poll HW usage counters */
1271         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1272         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1273                 return -EBUSY;
1274
1275         /* Zero the igu 'trailing edge' and 'leading edge' */
1276
1277         /* Send the FW cleanup command */
1278         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1279                 return -EBUSY;
1280
1281         /* ATC cleanup */
1282
1283         /* Verify TX hw is flushed */
1284         bnx2x_tx_hw_flushed(bp, poll_cnt);
1285
1286         /* Wait 100ms (not adjusted according to platform) */
1287         msleep(100);
1288
1289         /* Verify no pending pci transactions */
1290         if (bnx2x_is_pcie_pending(bp->pdev))
1291                 BNX2X_ERR("PCIE Transactions still pending\n");
1292
1293         /* Debug */
1294         bnx2x_hw_enable_status(bp);
1295
1296         /*
1297          * Master enable - Due to WB DMAE writes performed before this
1298          * register is re-initialized as part of the regular function init
1299          */
1300         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1301
1302         return 0;
1303 }
1304
1305 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1306 {
1307         int port = BP_PORT(bp);
1308         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1309         u32 val = REG_RD(bp, addr);
1310         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1311         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1312         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1313
1314         if (msix) {
1315                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1316                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1317                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1318                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1319                 if (single_msix)
1320                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1321         } else if (msi) {
1322                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1323                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1324                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1325                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1326         } else {
1327                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1328                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1329                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1330                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1331
1332                 if (!CHIP_IS_E1(bp)) {
1333                         DP(NETIF_MSG_IFUP,
1334                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1335
1336                         REG_WR(bp, addr, val);
1337
1338                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1339                 }
1340         }
1341
1342         if (CHIP_IS_E1(bp))
1343                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1344
1345         DP(NETIF_MSG_IFUP,
1346            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1347            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1348
1349         REG_WR(bp, addr, val);
1350         /*
1351          * Ensure that HC_CONFIG is written before leading/trailing edge config
1352          */
1353         mmiowb();
1354         barrier();
1355
1356         if (!CHIP_IS_E1(bp)) {
1357                 /* init leading/trailing edge */
1358                 if (IS_MF(bp)) {
1359                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1360                         if (bp->port.pmf)
1361                                 /* enable nig and gpio3 attention */
1362                                 val |= 0x1100;
1363                 } else
1364                         val = 0xffff;
1365
1366                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1367                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1368         }
1369
1370         /* Make sure that interrupts are indeed enabled from here on */
1371         mmiowb();
1372 }
1373
1374 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1375 {
1376         u32 val;
1377         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1378         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1379         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1380
1381         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1382
1383         if (msix) {
1384                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1385                          IGU_PF_CONF_SINGLE_ISR_EN);
1386                 val |= (IGU_PF_CONF_FUNC_EN |
1387                         IGU_PF_CONF_MSI_MSIX_EN |
1388                         IGU_PF_CONF_ATTN_BIT_EN);
1389
1390                 if (single_msix)
1391                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1392         } else if (msi) {
1393                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1394                 val |= (IGU_PF_CONF_FUNC_EN |
1395                         IGU_PF_CONF_MSI_MSIX_EN |
1396                         IGU_PF_CONF_ATTN_BIT_EN |
1397                         IGU_PF_CONF_SINGLE_ISR_EN);
1398         } else {
1399                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1400                 val |= (IGU_PF_CONF_FUNC_EN |
1401                         IGU_PF_CONF_INT_LINE_EN |
1402                         IGU_PF_CONF_ATTN_BIT_EN |
1403                         IGU_PF_CONF_SINGLE_ISR_EN);
1404         }
1405
1406         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1407            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1408
1409         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1410
1411         if (val & IGU_PF_CONF_INT_LINE_EN)
1412                 pci_intx(bp->pdev, true);
1413
1414         barrier();
1415
1416         /* init leading/trailing edge */
1417         if (IS_MF(bp)) {
1418                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1419                 if (bp->port.pmf)
1420                         /* enable nig and gpio3 attention */
1421                         val |= 0x1100;
1422         } else
1423                 val = 0xffff;
1424
1425         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1426         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1427
1428         /* Make sure that interrupts are indeed enabled from here on */
1429         mmiowb();
1430 }
1431
1432 void bnx2x_int_enable(struct bnx2x *bp)
1433 {
1434         if (bp->common.int_block == INT_BLOCK_HC)
1435                 bnx2x_hc_int_enable(bp);
1436         else
1437                 bnx2x_igu_int_enable(bp);
1438 }
1439
1440 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1441 {
1442         int port = BP_PORT(bp);
1443         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1444         u32 val = REG_RD(bp, addr);
1445
1446         /*
1447          * in E1 we must use only PCI configuration space to disable
1448          * MSI/MSIX capablility
1449          * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1450          */
1451         if (CHIP_IS_E1(bp)) {
1452                 /*  Since IGU_PF_CONF_MSI_MSIX_EN still always on
1453                  *  Use mask register to prevent from HC sending interrupts
1454                  *  after we exit the function
1455                  */
1456                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1457
1458                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1459                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1460                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1461         } else
1462                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1463                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1464                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
1465                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1466
1467         DP(NETIF_MSG_IFDOWN,
1468            "write %x to HC %d (addr 0x%x)\n",
1469            val, port, addr);
1470
1471         /* flush all outstanding writes */
1472         mmiowb();
1473
1474         REG_WR(bp, addr, val);
1475         if (REG_RD(bp, addr) != val)
1476                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1477 }
1478
1479 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1480 {
1481         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1482
1483         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1484                  IGU_PF_CONF_INT_LINE_EN |
1485                  IGU_PF_CONF_ATTN_BIT_EN);
1486
1487         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1488
1489         /* flush all outstanding writes */
1490         mmiowb();
1491
1492         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1493         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1494                 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1495 }
1496
1497 static void bnx2x_int_disable(struct bnx2x *bp)
1498 {
1499         if (bp->common.int_block == INT_BLOCK_HC)
1500                 bnx2x_hc_int_disable(bp);
1501         else
1502                 bnx2x_igu_int_disable(bp);
1503 }
1504
1505 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1506 {
1507         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1508         int i, offset;
1509
1510         if (disable_hw)
1511                 /* prevent the HW from sending interrupts */
1512                 bnx2x_int_disable(bp);
1513
1514         /* make sure all ISRs are done */
1515         if (msix) {
1516                 synchronize_irq(bp->msix_table[0].vector);
1517                 offset = 1;
1518                 if (CNIC_SUPPORT(bp))
1519                         offset++;
1520                 for_each_eth_queue(bp, i)
1521                         synchronize_irq(bp->msix_table[offset++].vector);
1522         } else
1523                 synchronize_irq(bp->pdev->irq);
1524
1525         /* make sure sp_task is not running */
1526         cancel_delayed_work(&bp->sp_task);
1527         cancel_delayed_work(&bp->period_task);
1528         flush_workqueue(bnx2x_wq);
1529 }
1530
1531 /* fast path */
1532
1533 /*
1534  * General service functions
1535  */
1536
1537 /* Return true if succeeded to acquire the lock */
1538 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1539 {
1540         u32 lock_status;
1541         u32 resource_bit = (1 << resource);
1542         int func = BP_FUNC(bp);
1543         u32 hw_lock_control_reg;
1544
1545         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1546            "Trying to take a lock on resource %d\n", resource);
1547
1548         /* Validating that the resource is within range */
1549         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1550                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1551                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1552                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1553                 return false;
1554         }
1555
1556         if (func <= 5)
1557                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1558         else
1559                 hw_lock_control_reg =
1560                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1561
1562         /* Try to acquire the lock */
1563         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1564         lock_status = REG_RD(bp, hw_lock_control_reg);
1565         if (lock_status & resource_bit)
1566                 return true;
1567
1568         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1569            "Failed to get a lock on resource %d\n", resource);
1570         return false;
1571 }
1572
1573 /**
1574  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1575  *
1576  * @bp: driver handle
1577  *
1578  * Returns the recovery leader resource id according to the engine this function
1579  * belongs to. Currently only only 2 engines is supported.
1580  */
1581 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1582 {
1583         if (BP_PATH(bp))
1584                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1585         else
1586                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1587 }
1588
1589 /**
1590  * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1591  *
1592  * @bp: driver handle
1593  *
1594  * Tries to aquire a leader lock for current engine.
1595  */
1596 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1597 {
1598         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1599 }
1600
1601 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1602
1603
1604 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1605 {
1606         struct bnx2x *bp = fp->bp;
1607         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1608         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1609         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1610         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1611
1612         DP(BNX2X_MSG_SP,
1613            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1614            fp->index, cid, command, bp->state,
1615            rr_cqe->ramrod_cqe.ramrod_type);
1616
1617         switch (command) {
1618         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1619                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1620                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1621                 break;
1622
1623         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1624                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1625                 drv_cmd = BNX2X_Q_CMD_SETUP;
1626                 break;
1627
1628         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1629                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1630                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1631                 break;
1632
1633         case (RAMROD_CMD_ID_ETH_HALT):
1634                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1635                 drv_cmd = BNX2X_Q_CMD_HALT;
1636                 break;
1637
1638         case (RAMROD_CMD_ID_ETH_TERMINATE):
1639                 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1640                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1641                 break;
1642
1643         case (RAMROD_CMD_ID_ETH_EMPTY):
1644                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1645                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1646                 break;
1647
1648         default:
1649                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1650                           command, fp->index);
1651                 return;
1652         }
1653
1654         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1655             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1656                 /* q_obj->complete_cmd() failure means that this was
1657                  * an unexpected completion.
1658                  *
1659                  * In this case we don't want to increase the bp->spq_left
1660                  * because apparently we haven't sent this command the first
1661                  * place.
1662                  */
1663 #ifdef BNX2X_STOP_ON_ERROR
1664                 bnx2x_panic();
1665 #else
1666                 return;
1667 #endif
1668
1669         smp_mb__before_atomic_inc();
1670         atomic_inc(&bp->cq_spq_left);
1671         /* push the change in bp->spq_left and towards the memory */
1672         smp_mb__after_atomic_inc();
1673
1674         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1675
1676         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1677             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1678                 /* if Q update ramrod is completed for last Q in AFEX vif set
1679                  * flow, then ACK MCP at the end
1680                  *
1681                  * mark pending ACK to MCP bit.
1682                  * prevent case that both bits are cleared.
1683                  * At the end of load/unload driver checks that
1684                  * sp_state is cleaerd, and this order prevents
1685                  * races
1686                  */
1687                 smp_mb__before_clear_bit();
1688                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1689                 wmb();
1690                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1691                 smp_mb__after_clear_bit();
1692
1693                 /* schedule workqueue to send ack to MCP */
1694                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1695         }
1696
1697         return;
1698 }
1699
1700 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1701                         u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1702 {
1703         u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1704
1705         bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1706                                  start);
1707 }
1708
1709 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1710 {
1711         struct bnx2x *bp = netdev_priv(dev_instance);
1712         u16 status = bnx2x_ack_int(bp);
1713         u16 mask;
1714         int i;
1715         u8 cos;
1716
1717         /* Return here if interrupt is shared and it's not for us */
1718         if (unlikely(status == 0)) {
1719                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1720                 return IRQ_NONE;
1721         }
1722         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1723
1724 #ifdef BNX2X_STOP_ON_ERROR
1725         if (unlikely(bp->panic))
1726                 return IRQ_HANDLED;
1727 #endif
1728
1729         for_each_eth_queue(bp, i) {
1730                 struct bnx2x_fastpath *fp = &bp->fp[i];
1731
1732                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1733                 if (status & mask) {
1734                         /* Handle Rx or Tx according to SB id */
1735                         prefetch(fp->rx_cons_sb);
1736                         for_each_cos_in_tx_queue(fp, cos)
1737                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1738                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1739                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1740                         status &= ~mask;
1741                 }
1742         }
1743
1744         if (CNIC_SUPPORT(bp)) {
1745                 mask = 0x2;
1746                 if (status & (mask | 0x1)) {
1747                         struct cnic_ops *c_ops = NULL;
1748
1749                         if (likely(bp->state == BNX2X_STATE_OPEN)) {
1750                                 rcu_read_lock();
1751                                 c_ops = rcu_dereference(bp->cnic_ops);
1752                                 if (c_ops)
1753                                         c_ops->cnic_handler(bp->cnic_data,
1754                                                             NULL);
1755                                 rcu_read_unlock();
1756                         }
1757
1758                         status &= ~mask;
1759                 }
1760         }
1761
1762         if (unlikely(status & 0x1)) {
1763                 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1764
1765                 status &= ~0x1;
1766                 if (!status)
1767                         return IRQ_HANDLED;
1768         }
1769
1770         if (unlikely(status))
1771                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1772                    status);
1773
1774         return IRQ_HANDLED;
1775 }
1776
1777 /* Link */
1778
1779 /*
1780  * General service functions
1781  */
1782
1783 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1784 {
1785         u32 lock_status;
1786         u32 resource_bit = (1 << resource);
1787         int func = BP_FUNC(bp);
1788         u32 hw_lock_control_reg;
1789         int cnt;
1790
1791         /* Validating that the resource is within range */
1792         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1793                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1794                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1795                 return -EINVAL;
1796         }
1797
1798         if (func <= 5) {
1799                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1800         } else {
1801                 hw_lock_control_reg =
1802                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1803         }
1804
1805         /* Validating that the resource is not already taken */
1806         lock_status = REG_RD(bp, hw_lock_control_reg);
1807         if (lock_status & resource_bit) {
1808                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1809                    lock_status, resource_bit);
1810                 return -EEXIST;
1811         }
1812
1813         /* Try for 5 second every 5ms */
1814         for (cnt = 0; cnt < 1000; cnt++) {
1815                 /* Try to acquire the lock */
1816                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1817                 lock_status = REG_RD(bp, hw_lock_control_reg);
1818                 if (lock_status & resource_bit)
1819                         return 0;
1820
1821                 msleep(5);
1822         }
1823         BNX2X_ERR("Timeout\n");
1824         return -EAGAIN;
1825 }
1826
1827 int bnx2x_release_leader_lock(struct bnx2x *bp)
1828 {
1829         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1830 }
1831
1832 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1833 {
1834         u32 lock_status;
1835         u32 resource_bit = (1 << resource);
1836         int func = BP_FUNC(bp);
1837         u32 hw_lock_control_reg;
1838
1839         /* Validating that the resource is within range */
1840         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1841                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1842                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1843                 return -EINVAL;
1844         }
1845
1846         if (func <= 5) {
1847                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1848         } else {
1849                 hw_lock_control_reg =
1850                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1851         }
1852
1853         /* Validating that the resource is currently taken */
1854         lock_status = REG_RD(bp, hw_lock_control_reg);
1855         if (!(lock_status & resource_bit)) {
1856                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1857                    lock_status, resource_bit);
1858                 return -EFAULT;
1859         }
1860
1861         REG_WR(bp, hw_lock_control_reg, resource_bit);
1862         return 0;
1863 }
1864
1865
1866 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1867 {
1868         /* The GPIO should be swapped if swap register is set and active */
1869         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1870                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1871         int gpio_shift = gpio_num +
1872                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1873         u32 gpio_mask = (1 << gpio_shift);
1874         u32 gpio_reg;
1875         int value;
1876
1877         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1878                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1879                 return -EINVAL;
1880         }
1881
1882         /* read GPIO value */
1883         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1884
1885         /* get the requested pin value */
1886         if ((gpio_reg & gpio_mask) == gpio_mask)
1887                 value = 1;
1888         else
1889                 value = 0;
1890
1891         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
1892
1893         return value;
1894 }
1895
1896 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1897 {
1898         /* The GPIO should be swapped if swap register is set and active */
1899         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1900                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1901         int gpio_shift = gpio_num +
1902                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1903         u32 gpio_mask = (1 << gpio_shift);
1904         u32 gpio_reg;
1905
1906         if (gpio_num > MISC_REGISTERS_GPIO_3) {
1907                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1908                 return -EINVAL;
1909         }
1910
1911         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1912         /* read GPIO and mask except the float bits */
1913         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1914
1915         switch (mode) {
1916         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1917                 DP(NETIF_MSG_LINK,
1918                    "Set GPIO %d (shift %d) -> output low\n",
1919                    gpio_num, gpio_shift);
1920                 /* clear FLOAT and set CLR */
1921                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1922                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1923                 break;
1924
1925         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1926                 DP(NETIF_MSG_LINK,
1927                    "Set GPIO %d (shift %d) -> output high\n",
1928                    gpio_num, gpio_shift);
1929                 /* clear FLOAT and set SET */
1930                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1931                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1932                 break;
1933
1934         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1935                 DP(NETIF_MSG_LINK,
1936                    "Set GPIO %d (shift %d) -> input\n",
1937                    gpio_num, gpio_shift);
1938                 /* set FLOAT */
1939                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1940                 break;
1941
1942         default:
1943                 break;
1944         }
1945
1946         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1947         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1948
1949         return 0;
1950 }
1951
1952 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1953 {
1954         u32 gpio_reg = 0;
1955         int rc = 0;
1956
1957         /* Any port swapping should be handled by caller. */
1958
1959         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1960         /* read GPIO and mask except the float bits */
1961         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1962         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1963         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1964         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1965
1966         switch (mode) {
1967         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1968                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1969                 /* set CLR */
1970                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1971                 break;
1972
1973         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1974                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1975                 /* set SET */
1976                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1977                 break;
1978
1979         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1980                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1981                 /* set FLOAT */
1982                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1983                 break;
1984
1985         default:
1986                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1987                 rc = -EINVAL;
1988                 break;
1989         }
1990
1991         if (rc == 0)
1992                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1993
1994         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1995
1996         return rc;
1997 }
1998
1999 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2000 {
2001         /* The GPIO should be swapped if swap register is set and active */
2002         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2003                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2004         int gpio_shift = gpio_num +
2005                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2006         u32 gpio_mask = (1 << gpio_shift);
2007         u32 gpio_reg;
2008
2009         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2010                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2011                 return -EINVAL;
2012         }
2013
2014         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2015         /* read GPIO int */
2016         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2017
2018         switch (mode) {
2019         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2020                 DP(NETIF_MSG_LINK,
2021                    "Clear GPIO INT %d (shift %d) -> output low\n",
2022                    gpio_num, gpio_shift);
2023                 /* clear SET and set CLR */
2024                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2025                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2026                 break;
2027
2028         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2029                 DP(NETIF_MSG_LINK,
2030                    "Set GPIO INT %d (shift %d) -> output high\n",
2031                    gpio_num, gpio_shift);
2032                 /* clear CLR and set SET */
2033                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2034                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2035                 break;
2036
2037         default:
2038                 break;
2039         }
2040
2041         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2042         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2043
2044         return 0;
2045 }
2046
2047 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2048 {
2049         u32 spio_reg;
2050
2051         /* Only 2 SPIOs are configurable */
2052         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2053                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2054                 return -EINVAL;
2055         }
2056
2057         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2058         /* read SPIO and mask except the float bits */
2059         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2060
2061         switch (mode) {
2062         case MISC_SPIO_OUTPUT_LOW:
2063                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2064                 /* clear FLOAT and set CLR */
2065                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2066                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2067                 break;
2068
2069         case MISC_SPIO_OUTPUT_HIGH:
2070                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2071                 /* clear FLOAT and set SET */
2072                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2073                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2074                 break;
2075
2076         case MISC_SPIO_INPUT_HI_Z:
2077                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2078                 /* set FLOAT */
2079                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2080                 break;
2081
2082         default:
2083                 break;
2084         }
2085
2086         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2087         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2088
2089         return 0;
2090 }
2091
2092 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2093 {
2094         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2095         switch (bp->link_vars.ieee_fc &
2096                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2097         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2098                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2099                                                    ADVERTISED_Pause);
2100                 break;
2101
2102         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2103                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2104                                                   ADVERTISED_Pause);
2105                 break;
2106
2107         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2108                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2109                 break;
2110
2111         default:
2112                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2113                                                    ADVERTISED_Pause);
2114                 break;
2115         }
2116 }
2117
2118 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2119 {
2120         /* Initialize link parameters structure variables
2121          * It is recommended to turn off RX FC for jumbo frames
2122          *  for better performance
2123          */
2124         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2125                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2126         else
2127                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2128 }
2129
2130 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2131 {
2132         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2133         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2134
2135         if (!BP_NOMCP(bp)) {
2136                 bnx2x_set_requested_fc(bp);
2137                 bnx2x_acquire_phy_lock(bp);
2138
2139                 if (load_mode == LOAD_DIAG) {
2140                         struct link_params *lp = &bp->link_params;
2141                         lp->loopback_mode = LOOPBACK_XGXS;
2142                         /* do PHY loopback at 10G speed, if possible */
2143                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2144                                 if (lp->speed_cap_mask[cfx_idx] &
2145                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2146                                         lp->req_line_speed[cfx_idx] =
2147                                         SPEED_10000;
2148                                 else
2149                                         lp->req_line_speed[cfx_idx] =
2150                                         SPEED_1000;
2151                         }
2152                 }
2153
2154                 if (load_mode == LOAD_LOOPBACK_EXT) {
2155                         struct link_params *lp = &bp->link_params;
2156                         lp->loopback_mode = LOOPBACK_EXT;
2157                 }
2158
2159                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2160
2161                 bnx2x_release_phy_lock(bp);
2162
2163                 bnx2x_calc_fc_adv(bp);
2164
2165                 if (bp->link_vars.link_up) {
2166                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2167                         bnx2x_link_report(bp);
2168                 }
2169                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2170                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2171                 return rc;
2172         }
2173         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2174         return -EINVAL;
2175 }
2176
2177 void bnx2x_link_set(struct bnx2x *bp)
2178 {
2179         if (!BP_NOMCP(bp)) {
2180                 bnx2x_acquire_phy_lock(bp);
2181                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2182                 bnx2x_release_phy_lock(bp);
2183
2184                 bnx2x_calc_fc_adv(bp);
2185         } else
2186                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2187 }
2188
2189 static void bnx2x__link_reset(struct bnx2x *bp)
2190 {
2191         if (!BP_NOMCP(bp)) {
2192                 bnx2x_acquire_phy_lock(bp);
2193                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2194                 bnx2x_release_phy_lock(bp);
2195         } else
2196                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2197 }
2198
2199 void bnx2x_force_link_reset(struct bnx2x *bp)
2200 {
2201         bnx2x_acquire_phy_lock(bp);
2202         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2203         bnx2x_release_phy_lock(bp);
2204 }
2205
2206 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2207 {
2208         u8 rc = 0;
2209
2210         if (!BP_NOMCP(bp)) {
2211                 bnx2x_acquire_phy_lock(bp);
2212                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2213                                      is_serdes);
2214                 bnx2x_release_phy_lock(bp);
2215         } else
2216                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2217
2218         return rc;
2219 }
2220
2221
2222 /* Calculates the sum of vn_min_rates.
2223    It's needed for further normalizing of the min_rates.
2224    Returns:
2225      sum of vn_min_rates.
2226        or
2227      0 - if all the min_rates are 0.
2228      In the later case fainess algorithm should be deactivated.
2229      If not all min_rates are zero then those that are zeroes will be set to 1.
2230  */
2231 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2232                                       struct cmng_init_input *input)
2233 {
2234         int all_zero = 1;
2235         int vn;
2236
2237         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2238                 u32 vn_cfg = bp->mf_config[vn];
2239                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2240                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2241
2242                 /* Skip hidden vns */
2243                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2244                         vn_min_rate = 0;
2245                 /* If min rate is zero - set it to 1 */
2246                 else if (!vn_min_rate)
2247                         vn_min_rate = DEF_MIN_RATE;
2248                 else
2249                         all_zero = 0;
2250
2251                 input->vnic_min_rate[vn] = vn_min_rate;
2252         }
2253
2254         /* if ETS or all min rates are zeros - disable fairness */
2255         if (BNX2X_IS_ETS_ENABLED(bp)) {
2256                 input->flags.cmng_enables &=
2257                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2258                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2259         } else if (all_zero) {
2260                 input->flags.cmng_enables &=
2261                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2262                 DP(NETIF_MSG_IFUP,
2263                    "All MIN values are zeroes fairness will be disabled\n");
2264         } else
2265                 input->flags.cmng_enables |=
2266                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2267 }
2268
2269 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2270                                     struct cmng_init_input *input)
2271 {
2272         u16 vn_max_rate;
2273         u32 vn_cfg = bp->mf_config[vn];
2274
2275         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2276                 vn_max_rate = 0;
2277         else {
2278                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2279
2280                 if (IS_MF_SI(bp)) {
2281                         /* maxCfg in percents of linkspeed */
2282                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2283                 } else /* SD modes */
2284                         /* maxCfg is absolute in 100Mb units */
2285                         vn_max_rate = maxCfg * 100;
2286         }
2287
2288         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2289
2290         input->vnic_max_rate[vn] = vn_max_rate;
2291 }
2292
2293
2294 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2295 {
2296         if (CHIP_REV_IS_SLOW(bp))
2297                 return CMNG_FNS_NONE;
2298         if (IS_MF(bp))
2299                 return CMNG_FNS_MINMAX;
2300
2301         return CMNG_FNS_NONE;
2302 }
2303
2304 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2305 {
2306         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2307
2308         if (BP_NOMCP(bp))
2309                 return; /* what should be the default bvalue in this case */
2310
2311         /* For 2 port configuration the absolute function number formula
2312          * is:
2313          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2314          *
2315          *      and there are 4 functions per port
2316          *
2317          * For 4 port configuration it is
2318          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2319          *
2320          *      and there are 2 functions per port
2321          */
2322         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2323                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2324
2325                 if (func >= E1H_FUNC_MAX)
2326                         break;
2327
2328                 bp->mf_config[vn] =
2329                         MF_CFG_RD(bp, func_mf_config[func].config);
2330         }
2331         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2332                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2333                 bp->flags |= MF_FUNC_DIS;
2334         } else {
2335                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2336                 bp->flags &= ~MF_FUNC_DIS;
2337         }
2338 }
2339
2340 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2341 {
2342         struct cmng_init_input input;
2343         memset(&input, 0, sizeof(struct cmng_init_input));
2344
2345         input.port_rate = bp->link_vars.line_speed;
2346
2347         if (cmng_type == CMNG_FNS_MINMAX) {
2348                 int vn;
2349
2350                 /* read mf conf from shmem */
2351                 if (read_cfg)
2352                         bnx2x_read_mf_cfg(bp);
2353
2354                 /* vn_weight_sum and enable fairness if not 0 */
2355                 bnx2x_calc_vn_min(bp, &input);
2356
2357                 /* calculate and set min-max rate for each vn */
2358                 if (bp->port.pmf)
2359                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2360                                 bnx2x_calc_vn_max(bp, vn, &input);
2361
2362                 /* always enable rate shaping and fairness */
2363                 input.flags.cmng_enables |=
2364                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2365
2366                 bnx2x_init_cmng(&input, &bp->cmng);
2367                 return;
2368         }
2369
2370         /* rate shaping and fairness are disabled */
2371         DP(NETIF_MSG_IFUP,
2372            "rate shaping and fairness are disabled\n");
2373 }
2374
2375 static void storm_memset_cmng(struct bnx2x *bp,
2376                               struct cmng_init *cmng,
2377                               u8 port)
2378 {
2379         int vn;
2380         size_t size = sizeof(struct cmng_struct_per_port);
2381
2382         u32 addr = BAR_XSTRORM_INTMEM +
2383                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2384
2385         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2386
2387         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2388                 int func = func_by_vn(bp, vn);
2389
2390                 addr = BAR_XSTRORM_INTMEM +
2391                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2392                 size = sizeof(struct rate_shaping_vars_per_vn);
2393                 __storm_memset_struct(bp, addr, size,
2394                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2395
2396                 addr = BAR_XSTRORM_INTMEM +
2397                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2398                 size = sizeof(struct fairness_vars_per_vn);
2399                 __storm_memset_struct(bp, addr, size,
2400                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2401         }
2402 }
2403
2404 /* This function is called upon link interrupt */
2405 static void bnx2x_link_attn(struct bnx2x *bp)
2406 {
2407         /* Make sure that we are synced with the current statistics */
2408         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2409
2410         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2411
2412         if (bp->link_vars.link_up) {
2413
2414                 /* dropless flow control */
2415                 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2416                         int port = BP_PORT(bp);
2417                         u32 pause_enabled = 0;
2418
2419                         if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2420                                 pause_enabled = 1;
2421
2422                         REG_WR(bp, BAR_USTRORM_INTMEM +
2423                                USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2424                                pause_enabled);
2425                 }
2426
2427                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2428                         struct host_port_stats *pstats;
2429
2430                         pstats = bnx2x_sp(bp, port_stats);
2431                         /* reset old mac stats */
2432                         memset(&(pstats->mac_stx[0]), 0,
2433                                sizeof(struct mac_stx));
2434                 }
2435                 if (bp->state == BNX2X_STATE_OPEN)
2436                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2437         }
2438
2439         if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2440                 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2441
2442                 if (cmng_fns != CMNG_FNS_NONE) {
2443                         bnx2x_cmng_fns_init(bp, false, cmng_fns);
2444                         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2445                 } else
2446                         /* rate shaping and fairness are disabled */
2447                         DP(NETIF_MSG_IFUP,
2448                            "single function mode without fairness\n");
2449         }
2450
2451         __bnx2x_link_report(bp);
2452
2453         if (IS_MF(bp))
2454                 bnx2x_link_sync_notify(bp);
2455 }
2456
2457 void bnx2x__link_status_update(struct bnx2x *bp)
2458 {
2459         if (bp->state != BNX2X_STATE_OPEN)
2460                 return;
2461
2462         /* read updated dcb configuration */
2463         bnx2x_dcbx_pmf_update(bp);
2464
2465         bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2466
2467         if (bp->link_vars.link_up)
2468                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2469         else
2470                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2471
2472         /* indicate link status */
2473         bnx2x_link_report(bp);
2474 }
2475
2476 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2477                                   u16 vlan_val, u8 allowed_prio)
2478 {
2479         struct bnx2x_func_state_params func_params = {0};
2480         struct bnx2x_func_afex_update_params *f_update_params =
2481                 &func_params.params.afex_update;
2482
2483         func_params.f_obj = &bp->func_obj;
2484         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2485
2486         /* no need to wait for RAMROD completion, so don't
2487          * set RAMROD_COMP_WAIT flag
2488          */
2489
2490         f_update_params->vif_id = vifid;
2491         f_update_params->afex_default_vlan = vlan_val;
2492         f_update_params->allowed_priorities = allowed_prio;
2493
2494         /* if ramrod can not be sent, response to MCP immediately */
2495         if (bnx2x_func_state_change(bp, &func_params) < 0)
2496                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2497
2498         return 0;
2499 }
2500
2501 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2502                                           u16 vif_index, u8 func_bit_map)
2503 {
2504         struct bnx2x_func_state_params func_params = {0};
2505         struct bnx2x_func_afex_viflists_params *update_params =
2506                 &func_params.params.afex_viflists;
2507         int rc;
2508         u32 drv_msg_code;
2509
2510         /* validate only LIST_SET and LIST_GET are received from switch */
2511         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2512                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2513                           cmd_type);
2514
2515         func_params.f_obj = &bp->func_obj;
2516         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2517
2518         /* set parameters according to cmd_type */
2519         update_params->afex_vif_list_command = cmd_type;
2520         update_params->vif_list_index = cpu_to_le16(vif_index);
2521         update_params->func_bit_map =
2522                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2523         update_params->func_to_clear = 0;
2524         drv_msg_code =
2525                 (cmd_type == VIF_LIST_RULE_GET) ?
2526                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2527                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2528
2529         /* if ramrod can not be sent, respond to MCP immediately for
2530          * SET and GET requests (other are not triggered from MCP)
2531          */
2532         rc = bnx2x_func_state_change(bp, &func_params);
2533         if (rc < 0)
2534                 bnx2x_fw_command(bp, drv_msg_code, 0);
2535
2536         return 0;
2537 }
2538
2539 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2540 {
2541         struct afex_stats afex_stats;
2542         u32 func = BP_ABS_FUNC(bp);
2543         u32 mf_config;
2544         u16 vlan_val;
2545         u32 vlan_prio;
2546         u16 vif_id;
2547         u8 allowed_prio;
2548         u8 vlan_mode;
2549         u32 addr_to_write, vifid, addrs, stats_type, i;
2550
2551         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2552                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2553                 DP(BNX2X_MSG_MCP,
2554                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2555                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2556         }
2557
2558         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2559                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2560                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2561                 DP(BNX2X_MSG_MCP,
2562                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2563                    vifid, addrs);
2564                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2565                                                addrs);
2566         }
2567
2568         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2569                 addr_to_write = SHMEM2_RD(bp,
2570                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2571                 stats_type = SHMEM2_RD(bp,
2572                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2573
2574                 DP(BNX2X_MSG_MCP,
2575                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2576                    addr_to_write);
2577
2578                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2579
2580                 /* write response to scratchpad, for MCP */
2581                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2582                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2583                                *(((u32 *)(&afex_stats))+i));
2584
2585                 /* send ack message to MCP */
2586                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2587         }
2588
2589         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2590                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2591                 bp->mf_config[BP_VN(bp)] = mf_config;
2592                 DP(BNX2X_MSG_MCP,
2593                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2594                    mf_config);
2595
2596                 /* if VIF_SET is "enabled" */
2597                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2598                         /* set rate limit directly to internal RAM */
2599                         struct cmng_init_input cmng_input;
2600                         struct rate_shaping_vars_per_vn m_rs_vn;
2601                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2602                         u32 addr = BAR_XSTRORM_INTMEM +
2603                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2604
2605                         bp->mf_config[BP_VN(bp)] = mf_config;
2606
2607                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2608                         m_rs_vn.vn_counter.rate =
2609                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2610                         m_rs_vn.vn_counter.quota =
2611                                 (m_rs_vn.vn_counter.rate *
2612                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2613
2614                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2615
2616                         /* read relevant values from mf_cfg struct in shmem */
2617                         vif_id =
2618                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2619                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2620                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2621                         vlan_val =
2622                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2623                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2624                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2625                         vlan_prio = (mf_config &
2626                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2627                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2628                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2629                         vlan_mode =
2630                                 (MF_CFG_RD(bp,
2631                                            func_mf_config[func].afex_config) &
2632                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2633                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2634                         allowed_prio =
2635                                 (MF_CFG_RD(bp,
2636                                            func_mf_config[func].afex_config) &
2637                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2638                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2639
2640                         /* send ramrod to FW, return in case of failure */
2641                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2642                                                    allowed_prio))
2643                                 return;
2644
2645                         bp->afex_def_vlan_tag = vlan_val;
2646                         bp->afex_vlan_mode = vlan_mode;
2647                 } else {
2648                         /* notify link down because BP->flags is disabled */
2649                         bnx2x_link_report(bp);
2650
2651                         /* send INVALID VIF ramrod to FW */
2652                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2653
2654                         /* Reset the default afex VLAN */
2655                         bp->afex_def_vlan_tag = -1;
2656                 }
2657         }
2658 }
2659
2660 static void bnx2x_pmf_update(struct bnx2x *bp)
2661 {
2662         int port = BP_PORT(bp);
2663         u32 val;
2664
2665         bp->port.pmf = 1;
2666         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2667
2668         /*
2669          * We need the mb() to ensure the ordering between the writing to
2670          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2671          */
2672         smp_mb();
2673
2674         /* queue a periodic task */
2675         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2676
2677         bnx2x_dcbx_pmf_update(bp);
2678
2679         /* enable nig attention */
2680         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2681         if (bp->common.int_block == INT_BLOCK_HC) {
2682                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2683                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2684         } else if (!CHIP_IS_E1x(bp)) {
2685                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2686                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2687         }
2688
2689         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2690 }
2691
2692 /* end of Link */
2693
2694 /* slow path */
2695
2696 /*
2697  * General service functions
2698  */
2699
2700 /* send the MCP a request, block until there is a reply */
2701 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2702 {
2703         int mb_idx = BP_FW_MB_IDX(bp);
2704         u32 seq;
2705         u32 rc = 0;
2706         u32 cnt = 1;
2707         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2708
2709         mutex_lock(&bp->fw_mb_mutex);
2710         seq = ++bp->fw_seq;
2711         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2712         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2713
2714         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2715                         (command | seq), param);
2716
2717         do {
2718                 /* let the FW do it's magic ... */
2719                 msleep(delay);
2720
2721                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2722
2723                 /* Give the FW up to 5 second (500*10ms) */
2724         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2725
2726         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2727            cnt*delay, rc, seq);
2728
2729         /* is this a reply to our command? */
2730         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2731                 rc &= FW_MSG_CODE_MASK;
2732         else {
2733                 /* FW BUG! */
2734                 BNX2X_ERR("FW failed to respond!\n");
2735                 bnx2x_fw_dump(bp);
2736                 rc = 0;
2737         }
2738         mutex_unlock(&bp->fw_mb_mutex);
2739
2740         return rc;
2741 }
2742
2743
2744 static void storm_memset_func_cfg(struct bnx2x *bp,
2745                                  struct tstorm_eth_function_common_config *tcfg,
2746                                  u16 abs_fid)
2747 {
2748         size_t size = sizeof(struct tstorm_eth_function_common_config);
2749
2750         u32 addr = BAR_TSTRORM_INTMEM +
2751                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2752
2753         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2754 }
2755
2756 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2757 {
2758         if (CHIP_IS_E1x(bp)) {
2759                 struct tstorm_eth_function_common_config tcfg = {0};
2760
2761                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2762         }
2763
2764         /* Enable the function in the FW */
2765         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2766         storm_memset_func_en(bp, p->func_id, 1);
2767
2768         /* spq */
2769         if (p->func_flgs & FUNC_FLG_SPQ) {
2770                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2771                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2772                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2773         }
2774 }
2775
2776 /**
2777  * bnx2x_get_tx_only_flags - Return common flags
2778  *
2779  * @bp          device handle
2780  * @fp          queue handle
2781  * @zero_stats  TRUE if statistics zeroing is needed
2782  *
2783  * Return the flags that are common for the Tx-only and not normal connections.
2784  */
2785 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2786                                             struct bnx2x_fastpath *fp,
2787                                             bool zero_stats)
2788 {
2789         unsigned long flags = 0;
2790
2791         /* PF driver will always initialize the Queue to an ACTIVE state */
2792         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2793
2794         /* tx only connections collect statistics (on the same index as the
2795          *  parent connection). The statistics are zeroed when the parent
2796          *  connection is initialized.
2797          */
2798
2799         __set_bit(BNX2X_Q_FLG_STATS, &flags);
2800         if (zero_stats)
2801                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2802
2803
2804         return flags;
2805 }
2806
2807 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2808                                        struct bnx2x_fastpath *fp,
2809                                        bool leading)
2810 {
2811         unsigned long flags = 0;
2812
2813         /* calculate other queue flags */
2814         if (IS_MF_SD(bp))
2815                 __set_bit(BNX2X_Q_FLG_OV, &flags);
2816
2817         if (IS_FCOE_FP(fp)) {
2818                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2819                 /* For FCoE - force usage of default priority (for afex) */
2820                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2821         }
2822
2823         if (!fp->disable_tpa) {
2824                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2825                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2826                 if (fp->mode == TPA_MODE_GRO)
2827                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2828         }
2829
2830         if (leading) {
2831                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2832                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2833         }
2834
2835         /* Always set HW VLAN stripping */
2836         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2837
2838         /* configure silent vlan removal */
2839         if (IS_MF_AFEX(bp))
2840                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2841
2842
2843         return flags | bnx2x_get_common_flags(bp, fp, true);
2844 }
2845
2846 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2847         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2848         u8 cos)
2849 {
2850         gen_init->stat_id = bnx2x_stats_id(fp);
2851         gen_init->spcl_id = fp->cl_id;
2852
2853         /* Always use mini-jumbo MTU for FCoE L2 ring */
2854         if (IS_FCOE_FP(fp))
2855                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2856         else
2857                 gen_init->mtu = bp->dev->mtu;
2858
2859         gen_init->cos = cos;
2860 }
2861
2862 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2863         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2864         struct bnx2x_rxq_setup_params *rxq_init)
2865 {
2866         u8 max_sge = 0;
2867         u16 sge_sz = 0;
2868         u16 tpa_agg_size = 0;
2869
2870         if (!fp->disable_tpa) {
2871                 pause->sge_th_lo = SGE_TH_LO(bp);
2872                 pause->sge_th_hi = SGE_TH_HI(bp);
2873
2874                 /* validate SGE ring has enough to cross high threshold */
2875                 WARN_ON(bp->dropless_fc &&
2876                                 pause->sge_th_hi + FW_PREFETCH_CNT >
2877                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2878
2879                 tpa_agg_size = min_t(u32,
2880                         (min_t(u32, 8, MAX_SKB_FRAGS) *
2881                         SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2882                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2883                         SGE_PAGE_SHIFT;
2884                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2885                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2886                 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2887                                     0xffff);
2888         }
2889
2890         /* pause - not for e1 */
2891         if (!CHIP_IS_E1(bp)) {
2892                 pause->bd_th_lo = BD_TH_LO(bp);
2893                 pause->bd_th_hi = BD_TH_HI(bp);
2894
2895                 pause->rcq_th_lo = RCQ_TH_LO(bp);
2896                 pause->rcq_th_hi = RCQ_TH_HI(bp);
2897                 /*
2898                  * validate that rings have enough entries to cross
2899                  * high thresholds
2900                  */
2901                 WARN_ON(bp->dropless_fc &&
2902                                 pause->bd_th_hi + FW_PREFETCH_CNT >
2903                                 bp->rx_ring_size);
2904                 WARN_ON(bp->dropless_fc &&
2905                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
2906                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2907
2908                 pause->pri_map = 1;
2909         }
2910
2911         /* rxq setup */
2912         rxq_init->dscr_map = fp->rx_desc_mapping;
2913         rxq_init->sge_map = fp->rx_sge_mapping;
2914         rxq_init->rcq_map = fp->rx_comp_mapping;
2915         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2916
2917         /* This should be a maximum number of data bytes that may be
2918          * placed on the BD (not including paddings).
2919          */
2920         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2921                 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2922
2923         rxq_init->cl_qzone_id = fp->cl_qzone_id;
2924         rxq_init->tpa_agg_sz = tpa_agg_size;
2925         rxq_init->sge_buf_sz = sge_sz;
2926         rxq_init->max_sges_pkt = max_sge;
2927         rxq_init->rss_engine_id = BP_FUNC(bp);
2928         rxq_init->mcast_engine_id = BP_FUNC(bp);
2929
2930         /* Maximum number or simultaneous TPA aggregation for this Queue.
2931          *
2932          * For PF Clients it should be the maximum avaliable number.
2933          * VF driver(s) may want to define it to a smaller value.
2934          */
2935         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2936
2937         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2938         rxq_init->fw_sb_id = fp->fw_sb_id;
2939
2940         if (IS_FCOE_FP(fp))
2941                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2942         else
2943                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2944         /* configure silent vlan removal
2945          * if multi function mode is afex, then mask default vlan
2946          */
2947         if (IS_MF_AFEX(bp)) {
2948                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2949                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2950         }
2951 }
2952
2953 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2954         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2955         u8 cos)
2956 {
2957         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2958         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2959         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2960         txq_init->fw_sb_id = fp->fw_sb_id;
2961
2962         /*
2963          * set the tss leading client id for TX classfication ==
2964          * leading RSS client id
2965          */
2966         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2967
2968         if (IS_FCOE_FP(fp)) {
2969                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2970                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2971         }
2972 }
2973
2974 static void bnx2x_pf_init(struct bnx2x *bp)
2975 {
2976         struct bnx2x_func_init_params func_init = {0};
2977         struct event_ring_data eq_data = { {0} };
2978         u16 flags;
2979
2980         if (!CHIP_IS_E1x(bp)) {
2981                 /* reset IGU PF statistics: MSIX + ATTN */
2982                 /* PF */
2983                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2984                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2985                            (CHIP_MODE_IS_4_PORT(bp) ?
2986                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2987                 /* ATTN */
2988                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2989                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2990                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2991                            (CHIP_MODE_IS_4_PORT(bp) ?
2992                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2993         }
2994
2995         /* function setup flags */
2996         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2997
2998         /* This flag is relevant for E1x only.
2999          * E2 doesn't have a TPA configuration in a function level.
3000          */
3001         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3002
3003         func_init.func_flgs = flags;
3004         func_init.pf_id = BP_FUNC(bp);
3005         func_init.func_id = BP_FUNC(bp);
3006         func_init.spq_map = bp->spq_mapping;
3007         func_init.spq_prod = bp->spq_prod_idx;
3008
3009         bnx2x_func_init(bp, &func_init);
3010
3011         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3012
3013         /*
3014          * Congestion management values depend on the link rate
3015          * There is no active link so initial link rate is set to 10 Gbps.
3016          * When the link comes up The congestion management values are
3017          * re-calculated according to the actual link rate.
3018          */
3019         bp->link_vars.line_speed = SPEED_10000;
3020         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3021
3022         /* Only the PMF sets the HW */
3023         if (bp->port.pmf)
3024                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3025
3026         /* init Event Queue */
3027         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3028         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3029         eq_data.producer = bp->eq_prod;
3030         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3031         eq_data.sb_id = DEF_SB_ID;
3032         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3033 }
3034
3035
3036 static void bnx2x_e1h_disable(struct bnx2x *bp)
3037 {
3038         int port = BP_PORT(bp);
3039
3040         bnx2x_tx_disable(bp);
3041
3042         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3043 }
3044
3045 static void bnx2x_e1h_enable(struct bnx2x *bp)
3046 {
3047         int port = BP_PORT(bp);
3048
3049         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3050
3051         /* Tx queue should be only reenabled */
3052         netif_tx_wake_all_queues(bp->dev);
3053
3054         /*
3055          * Should not call netif_carrier_on since it will be called if the link
3056          * is up when checking for link state
3057          */
3058 }
3059
3060 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3061
3062 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3063 {
3064         struct eth_stats_info *ether_stat =
3065                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3066
3067         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3068                 ETH_STAT_INFO_VERSION_LEN);
3069
3070         bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3071                                         DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3072                                         ether_stat->mac_local);
3073
3074         ether_stat->mtu_size = bp->dev->mtu;
3075
3076         if (bp->dev->features & NETIF_F_RXCSUM)
3077                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3078         if (bp->dev->features & NETIF_F_TSO)
3079                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3080         ether_stat->feature_flags |= bp->common.boot_mode;
3081
3082         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3083
3084         ether_stat->txq_size = bp->tx_ring_size;
3085         ether_stat->rxq_size = bp->rx_ring_size;
3086 }
3087
3088 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3089 {
3090         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3091         struct fcoe_stats_info *fcoe_stat =
3092                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3093
3094         if (!CNIC_LOADED(bp))
3095                 return;
3096
3097         memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3098                bp->fip_mac, ETH_ALEN);
3099
3100         fcoe_stat->qos_priority =
3101                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3102
3103         /* insert FCoE stats from ramrod response */
3104         if (!NO_FCOE(bp)) {
3105                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3106                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3107                         tstorm_queue_statistics;
3108
3109                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3110                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3111                         xstorm_queue_statistics;
3112
3113                 struct fcoe_statistics_params *fw_fcoe_stat =
3114                         &bp->fw_stats_data->fcoe;
3115
3116                 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3117                        fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3118
3119                 ADD_64(fcoe_stat->rx_bytes_hi,
3120                        fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3121                        fcoe_stat->rx_bytes_lo,
3122                        fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3123
3124                 ADD_64(fcoe_stat->rx_bytes_hi,
3125                        fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3126                        fcoe_stat->rx_bytes_lo,
3127                        fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3128
3129                 ADD_64(fcoe_stat->rx_bytes_hi,
3130                        fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3131                        fcoe_stat->rx_bytes_lo,
3132                        fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3133
3134                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3135                        fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3136
3137                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3138                        fcoe_q_tstorm_stats->rcv_ucast_pkts);
3139
3140                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3141                        fcoe_q_tstorm_stats->rcv_bcast_pkts);
3142
3143                 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3144                        fcoe_q_tstorm_stats->rcv_mcast_pkts);
3145
3146                 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3147                        fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3148
3149                 ADD_64(fcoe_stat->tx_bytes_hi,
3150                        fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3151                        fcoe_stat->tx_bytes_lo,
3152                        fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3153
3154                 ADD_64(fcoe_stat->tx_bytes_hi,
3155                        fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3156                        fcoe_stat->tx_bytes_lo,
3157                        fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3158
3159                 ADD_64(fcoe_stat->tx_bytes_hi,
3160                        fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3161                        fcoe_stat->tx_bytes_lo,
3162                        fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3163
3164                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3165                        fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3166
3167                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3168                        fcoe_q_xstorm_stats->ucast_pkts_sent);
3169
3170                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3171                        fcoe_q_xstorm_stats->bcast_pkts_sent);
3172
3173                 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3174                        fcoe_q_xstorm_stats->mcast_pkts_sent);
3175         }
3176
3177         /* ask L5 driver to add data to the struct */
3178         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3179 }
3180
3181 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3182 {
3183         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3184         struct iscsi_stats_info *iscsi_stat =
3185                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3186
3187         if (!CNIC_LOADED(bp))
3188                 return;
3189
3190         memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3191                bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3192
3193         iscsi_stat->qos_priority =
3194                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3195
3196         /* ask L5 driver to add data to the struct */
3197         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3198 }
3199
3200 /* called due to MCP event (on pmf):
3201  *      reread new bandwidth configuration
3202  *      configure FW
3203  *      notify others function about the change
3204  */
3205 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3206 {
3207         if (bp->link_vars.link_up) {
3208                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3209                 bnx2x_link_sync_notify(bp);
3210         }
3211         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3212 }
3213
3214 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3215 {
3216         bnx2x_config_mf_bw(bp);
3217         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3218 }
3219
3220 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3221 {
3222         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3223         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3224 }
3225
3226 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3227 {
3228         enum drv_info_opcode op_code;
3229         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3230
3231         /* if drv_info version supported by MFW doesn't match - send NACK */
3232         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3233                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3234                 return;
3235         }
3236
3237         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3238                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3239
3240         memset(&bp->slowpath->drv_info_to_mcp, 0,
3241                sizeof(union drv_info_to_mcp));
3242
3243         switch (op_code) {
3244         case ETH_STATS_OPCODE:
3245                 bnx2x_drv_info_ether_stat(bp);
3246                 break;
3247         case FCOE_STATS_OPCODE:
3248                 bnx2x_drv_info_fcoe_stat(bp);
3249                 break;
3250         case ISCSI_STATS_OPCODE:
3251                 bnx2x_drv_info_iscsi_stat(bp);
3252                 break;
3253         default:
3254                 /* if op code isn't supported - send NACK */
3255                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3256                 return;
3257         }
3258
3259         /* if we got drv_info attn from MFW then these fields are defined in
3260          * shmem2 for sure
3261          */
3262         SHMEM2_WR(bp, drv_info_host_addr_lo,
3263                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3264         SHMEM2_WR(bp, drv_info_host_addr_hi,
3265                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3266
3267         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3268 }
3269
3270 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3271 {
3272         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3273
3274         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3275
3276                 /*
3277                  * This is the only place besides the function initialization
3278                  * where the bp->flags can change so it is done without any
3279                  * locks
3280                  */
3281                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3282                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3283                         bp->flags |= MF_FUNC_DIS;
3284
3285                         bnx2x_e1h_disable(bp);
3286                 } else {
3287                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3288                         bp->flags &= ~MF_FUNC_DIS;
3289
3290                         bnx2x_e1h_enable(bp);
3291                 }
3292                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3293         }
3294         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3295                 bnx2x_config_mf_bw(bp);
3296                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3297         }
3298
3299         /* Report results to MCP */
3300         if (dcc_event)
3301                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3302         else
3303                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3304 }
3305
3306 /* must be called under the spq lock */
3307 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3308 {
3309         struct eth_spe *next_spe = bp->spq_prod_bd;
3310
3311         if (bp->spq_prod_bd == bp->spq_last_bd) {
3312                 bp->spq_prod_bd = bp->spq;
3313                 bp->spq_prod_idx = 0;
3314                 DP(BNX2X_MSG_SP, "end of spq\n");
3315         } else {
3316                 bp->spq_prod_bd++;
3317                 bp->spq_prod_idx++;
3318         }
3319         return next_spe;
3320 }
3321
3322 /* must be called under the spq lock */
3323 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3324 {
3325         int func = BP_FUNC(bp);
3326
3327         /*
3328          * Make sure that BD data is updated before writing the producer:
3329          * BD data is written to the memory, the producer is read from the
3330          * memory, thus we need a full memory barrier to ensure the ordering.
3331          */
3332         mb();
3333
3334         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3335                  bp->spq_prod_idx);
3336         mmiowb();
3337 }
3338
3339 /**
3340  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3341  *
3342  * @cmd:        command to check
3343  * @cmd_type:   command type
3344  */
3345 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3346 {
3347         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3348             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3349             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3350             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3351             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3352             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3353             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3354                 return true;
3355         else
3356                 return false;
3357
3358 }
3359
3360
3361 /**
3362  * bnx2x_sp_post - place a single command on an SP ring
3363  *
3364  * @bp:         driver handle
3365  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3366  * @cid:        SW CID the command is related to
3367  * @data_hi:    command private data address (high 32 bits)
3368  * @data_lo:    command private data address (low 32 bits)
3369  * @cmd_type:   command type (e.g. NONE, ETH)
3370  *
3371  * SP data is handled as if it's always an address pair, thus data fields are
3372  * not swapped to little endian in upper functions. Instead this function swaps
3373  * data as if it's two u32 fields.
3374  */
3375 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3376                   u32 data_hi, u32 data_lo, int cmd_type)
3377 {
3378         struct eth_spe *spe;
3379         u16 type;
3380         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3381
3382 #ifdef BNX2X_STOP_ON_ERROR
3383         if (unlikely(bp->panic)) {
3384                 BNX2X_ERR("Can't post SP when there is panic\n");
3385                 return -EIO;
3386         }
3387 #endif
3388
3389         spin_lock_bh(&bp->spq_lock);
3390
3391         if (common) {
3392                 if (!atomic_read(&bp->eq_spq_left)) {
3393                         BNX2X_ERR("BUG! EQ ring full!\n");
3394                         spin_unlock_bh(&bp->spq_lock);
3395                         bnx2x_panic();
3396                         return -EBUSY;
3397                 }
3398         } else if (!atomic_read(&bp->cq_spq_left)) {
3399                         BNX2X_ERR("BUG! SPQ ring full!\n");
3400                         spin_unlock_bh(&bp->spq_lock);
3401                         bnx2x_panic();
3402                         return -EBUSY;
3403         }
3404
3405         spe = bnx2x_sp_get_next(bp);
3406
3407         /* CID needs port number to be encoded int it */
3408         spe->hdr.conn_and_cmd_data =
3409                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3410                                     HW_CID(bp, cid));
3411
3412         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3413
3414         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3415                  SPE_HDR_FUNCTION_ID);
3416
3417         spe->hdr.type = cpu_to_le16(type);
3418
3419         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3420         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3421
3422         /*
3423          * It's ok if the actual decrement is issued towards the memory
3424          * somewhere between the spin_lock and spin_unlock. Thus no
3425          * more explict memory barrier is needed.
3426          */
3427         if (common)
3428                 atomic_dec(&bp->eq_spq_left);
3429         else
3430                 atomic_dec(&bp->cq_spq_left);
3431
3432
3433         DP(BNX2X_MSG_SP,
3434            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3435            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3436            (u32)(U64_LO(bp->spq_mapping) +
3437            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3438            HW_CID(bp, cid), data_hi, data_lo, type,
3439            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3440
3441         bnx2x_sp_prod_update(bp);
3442         spin_unlock_bh(&bp->spq_lock);
3443         return 0;
3444 }
3445
3446 /* acquire split MCP access lock register */
3447 static int bnx2x_acquire_alr(struct bnx2x *bp)
3448 {
3449         u32 j, val;
3450         int rc = 0;
3451
3452         might_sleep();
3453         for (j = 0; j < 1000; j++) {
3454                 val = (1UL << 31);
3455                 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3456                 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3457                 if (val & (1L << 31))
3458                         break;
3459
3460                 msleep(5);
3461         }
3462         if (!(val & (1L << 31))) {
3463                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3464                 rc = -EBUSY;
3465         }
3466
3467         return rc;
3468 }
3469
3470 /* release split MCP access lock register */
3471 static void bnx2x_release_alr(struct bnx2x *bp)
3472 {
3473         REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3474 }
3475
3476 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3477 #define BNX2X_DEF_SB_IDX        0x0002
3478
3479 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3480 {
3481         struct host_sp_status_block *def_sb = bp->def_status_blk;
3482         u16 rc = 0;
3483
3484         barrier(); /* status block is written to by the chip */
3485         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3486                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3487                 rc |= BNX2X_DEF_SB_ATT_IDX;
3488         }
3489
3490         if (bp->def_idx != def_sb->sp_sb.running_index) {
3491                 bp->def_idx = def_sb->sp_sb.running_index;
3492                 rc |= BNX2X_DEF_SB_IDX;
3493         }
3494
3495         /* Do not reorder: indecies reading should complete before handling */
3496         barrier();
3497         return rc;
3498 }
3499
3500 /*
3501  * slow path service functions
3502  */
3503
3504 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3505 {
3506         int port = BP_PORT(bp);
3507         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3508                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3509         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3510                                        NIG_REG_MASK_INTERRUPT_PORT0;
3511         u32 aeu_mask;
3512         u32 nig_mask = 0;
3513         u32 reg_addr;
3514
3515         if (bp->attn_state & asserted)
3516                 BNX2X_ERR("IGU ERROR\n");
3517
3518         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3519         aeu_mask = REG_RD(bp, aeu_addr);
3520
3521         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3522            aeu_mask, asserted);
3523         aeu_mask &= ~(asserted & 0x3ff);
3524         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3525
3526         REG_WR(bp, aeu_addr, aeu_mask);
3527         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3528
3529         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3530         bp->attn_state |= asserted;
3531         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3532
3533         if (asserted & ATTN_HARD_WIRED_MASK) {
3534                 if (asserted & ATTN_NIG_FOR_FUNC) {
3535
3536                         bnx2x_acquire_phy_lock(bp);
3537
3538                         /* save nig interrupt mask */
3539                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3540
3541                         /* If nig_mask is not set, no need to call the update
3542                          * function.
3543                          */
3544                         if (nig_mask) {
3545                                 REG_WR(bp, nig_int_mask_addr, 0);
3546
3547                                 bnx2x_link_attn(bp);
3548                         }
3549
3550                         /* handle unicore attn? */
3551                 }
3552                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3553                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3554
3555                 if (asserted & GPIO_2_FUNC)
3556                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3557
3558                 if (asserted & GPIO_3_FUNC)
3559                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3560
3561                 if (asserted & GPIO_4_FUNC)
3562                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3563
3564                 if (port == 0) {
3565                         if (asserted & ATTN_GENERAL_ATTN_1) {
3566                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3567                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3568                         }
3569                         if (asserted & ATTN_GENERAL_ATTN_2) {
3570                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3571                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3572                         }
3573                         if (asserted & ATTN_GENERAL_ATTN_3) {
3574                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3575                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3576                         }
3577                 } else {
3578                         if (asserted & ATTN_GENERAL_ATTN_4) {
3579                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3580                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3581                         }
3582                         if (asserted & ATTN_GENERAL_ATTN_5) {
3583                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3584                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3585                         }
3586                         if (asserted & ATTN_GENERAL_ATTN_6) {
3587                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3588                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3589                         }
3590                 }
3591
3592         } /* if hardwired */
3593
3594         if (bp->common.int_block == INT_BLOCK_HC)
3595                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3596                             COMMAND_REG_ATTN_BITS_SET);
3597         else
3598                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3599
3600         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3601            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3602         REG_WR(bp, reg_addr, asserted);
3603
3604         /* now set back the mask */
3605         if (asserted & ATTN_NIG_FOR_FUNC) {
3606                 /* Verify that IGU ack through BAR was written before restoring
3607                  * NIG mask. This loop should exit after 2-3 iterations max.
3608                  */
3609                 if (bp->common.int_block != INT_BLOCK_HC) {
3610                         u32 cnt = 0, igu_acked;
3611                         do {
3612                                 igu_acked = REG_RD(bp,
3613                                                    IGU_REG_ATTENTION_ACK_BITS);
3614                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3615                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3616                         if (!igu_acked)
3617                                 DP(NETIF_MSG_HW,
3618                                    "Failed to verify IGU ack on time\n");
3619                         barrier();
3620                 }
3621                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3622                 bnx2x_release_phy_lock(bp);
3623         }
3624 }
3625
3626 static void bnx2x_fan_failure(struct bnx2x *bp)
3627 {
3628         int port = BP_PORT(bp);
3629         u32 ext_phy_config;
3630         /* mark the failure */
3631         ext_phy_config =
3632                 SHMEM_RD(bp,
3633                          dev_info.port_hw_config[port].external_phy_config);
3634
3635         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3636         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3637         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3638                  ext_phy_config);
3639
3640         /* log the failure */
3641         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3642                             "Please contact OEM Support for assistance\n");
3643
3644         /*
3645          * Scheudle device reset (unload)
3646          * This is due to some boards consuming sufficient power when driver is
3647          * up to overheat if fan fails.
3648          */
3649         smp_mb__before_clear_bit();
3650         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3651         smp_mb__after_clear_bit();
3652         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3653
3654 }
3655
3656 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3657 {
3658         int port = BP_PORT(bp);
3659         int reg_offset;
3660         u32 val;
3661
3662         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3663                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3664
3665         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3666
3667                 val = REG_RD(bp, reg_offset);
3668                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3669                 REG_WR(bp, reg_offset, val);
3670
3671                 BNX2X_ERR("SPIO5 hw attention\n");
3672
3673                 /* Fan failure attention */
3674                 bnx2x_hw_reset_phy(&bp->link_params);
3675                 bnx2x_fan_failure(bp);
3676         }
3677
3678         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3679                 bnx2x_acquire_phy_lock(bp);
3680                 bnx2x_handle_module_detect_int(&bp->link_params);
3681                 bnx2x_release_phy_lock(bp);
3682         }
3683
3684         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3685
3686                 val = REG_RD(bp, reg_offset);
3687                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3688                 REG_WR(bp, reg_offset, val);
3689
3690                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3691                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3692                 bnx2x_panic();
3693         }
3694 }
3695
3696 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3697 {
3698         u32 val;
3699
3700         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3701
3702                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3703                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3704                 /* DORQ discard attention */
3705                 if (val & 0x2)
3706                         BNX2X_ERR("FATAL error from DORQ\n");
3707         }
3708
3709         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3710
3711                 int port = BP_PORT(bp);
3712                 int reg_offset;
3713
3714                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3715                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3716
3717                 val = REG_RD(bp, reg_offset);
3718                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3719                 REG_WR(bp, reg_offset, val);
3720
3721                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3722                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3723                 bnx2x_panic();
3724         }
3725 }
3726
3727 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3728 {
3729         u32 val;
3730
3731         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3732
3733                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3734                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3735                 /* CFC error attention */
3736                 if (val & 0x2)
3737                         BNX2X_ERR("FATAL error from CFC\n");
3738         }
3739
3740         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3741                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3742                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3743                 /* RQ_USDMDP_FIFO_OVERFLOW */
3744                 if (val & 0x18000)
3745                         BNX2X_ERR("FATAL error from PXP\n");
3746
3747                 if (!CHIP_IS_E1x(bp)) {
3748                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3749                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3750                 }
3751         }
3752
3753         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3754
3755                 int port = BP_PORT(bp);
3756                 int reg_offset;
3757
3758                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3759                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3760
3761                 val = REG_RD(bp, reg_offset);
3762                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3763                 REG_WR(bp, reg_offset, val);
3764
3765                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3766                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3767                 bnx2x_panic();
3768         }
3769 }
3770
3771 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3772 {
3773         u32 val;
3774
3775         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3776
3777                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3778                         int func = BP_FUNC(bp);
3779
3780                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3781                         bnx2x_read_mf_cfg(bp);
3782                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3783                                         func_mf_config[BP_ABS_FUNC(bp)].config);
3784                         val = SHMEM_RD(bp,
3785                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
3786                         if (val & DRV_STATUS_DCC_EVENT_MASK)
3787                                 bnx2x_dcc_event(bp,
3788                                             (val & DRV_STATUS_DCC_EVENT_MASK));
3789
3790                         if (val & DRV_STATUS_SET_MF_BW)
3791                                 bnx2x_set_mf_bw(bp);
3792
3793                         if (val & DRV_STATUS_DRV_INFO_REQ)
3794                                 bnx2x_handle_drv_info_req(bp);
3795                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3796                                 bnx2x_pmf_update(bp);
3797
3798                         if (bp->port.pmf &&
3799                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3800                                 bp->dcbx_enabled > 0)
3801                                 /* start dcbx state machine */
3802                                 bnx2x_dcbx_set_params(bp,
3803                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
3804                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
3805                                 bnx2x_handle_afex_cmd(bp,
3806                                         val & DRV_STATUS_AFEX_EVENT_MASK);
3807                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3808                                 bnx2x_handle_eee_event(bp);
3809                         if (bp->link_vars.periodic_flags &
3810                             PERIODIC_FLAGS_LINK_EVENT) {
3811                                 /*  sync with link */
3812                                 bnx2x_acquire_phy_lock(bp);
3813                                 bp->link_vars.periodic_flags &=
3814                                         ~PERIODIC_FLAGS_LINK_EVENT;
3815                                 bnx2x_release_phy_lock(bp);
3816                                 if (IS_MF(bp))
3817                                         bnx2x_link_sync_notify(bp);
3818                                 bnx2x_link_report(bp);
3819                         }
3820                         /* Always call it here: bnx2x_link_report() will
3821                          * prevent the link indication duplication.
3822                          */
3823                         bnx2x__link_status_update(bp);
3824                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3825
3826                         BNX2X_ERR("MC assert!\n");
3827                         bnx2x_mc_assert(bp);
3828                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3829                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3830                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3831                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3832                         bnx2x_panic();
3833
3834                 } else if (attn & BNX2X_MCP_ASSERT) {
3835
3836                         BNX2X_ERR("MCP assert!\n");
3837                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3838                         bnx2x_fw_dump(bp);
3839
3840                 } else
3841                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3842         }
3843
3844         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3845                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3846                 if (attn & BNX2X_GRC_TIMEOUT) {
3847                         val = CHIP_IS_E1(bp) ? 0 :
3848                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3849                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
3850                 }
3851                 if (attn & BNX2X_GRC_RSV) {
3852                         val = CHIP_IS_E1(bp) ? 0 :
3853                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3854                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
3855                 }
3856                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3857         }
3858 }
3859
3860 /*
3861  * Bits map:
3862  * 0-7   - Engine0 load counter.
3863  * 8-15  - Engine1 load counter.
3864  * 16    - Engine0 RESET_IN_PROGRESS bit.
3865  * 17    - Engine1 RESET_IN_PROGRESS bit.
3866  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3867  *         on the engine
3868  * 19    - Engine1 ONE_IS_LOADED.
3869  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
3870  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
3871  *         just the one belonging to its engine).
3872  *
3873  */
3874 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
3875
3876 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
3877 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
3878 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
3879 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
3880 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
3881 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
3882 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
3883
3884 /*
3885  * Set the GLOBAL_RESET bit.
3886  *
3887  * Should be run under rtnl lock
3888  */
3889 void bnx2x_set_reset_global(struct bnx2x *bp)
3890 {
3891         u32 val;
3892         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3893         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3894         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3895         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3896 }
3897
3898 /*
3899  * Clear the GLOBAL_RESET bit.
3900  *
3901  * Should be run under rtnl lock
3902  */
3903 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3904 {
3905         u32 val;
3906         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3907         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3908         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3909         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3910 }
3911
3912 /*
3913  * Checks the GLOBAL_RESET bit.
3914  *
3915  * should be run under rtnl lock
3916  */
3917 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3918 {
3919         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3920
3921         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3922         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3923 }
3924
3925 /*
3926  * Clear RESET_IN_PROGRESS bit for the current engine.
3927  *
3928  * Should be run under rtnl lock
3929  */
3930 static void bnx2x_set_reset_done(struct bnx2x *bp)
3931 {
3932         u32 val;
3933         u32 bit = BP_PATH(bp) ?
3934                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3935         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3936         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3937
3938         /* Clear the bit */
3939         val &= ~bit;
3940         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3941
3942         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3943 }
3944
3945 /*
3946  * Set RESET_IN_PROGRESS for the current engine.
3947  *
3948  * should be run under rtnl lock
3949  */
3950 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3951 {
3952         u32 val;
3953         u32 bit = BP_PATH(bp) ?
3954                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3955         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3956         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3957
3958         /* Set the bit */
3959         val |= bit;
3960         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3961         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3962 }
3963
3964 /*
3965  * Checks the RESET_IN_PROGRESS bit for the given engine.
3966  * should be run under rtnl lock
3967  */
3968 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3969 {
3970         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3971         u32 bit = engine ?
3972                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3973
3974         /* return false if bit is set */
3975         return (val & bit) ? false : true;
3976 }
3977
3978 /*
3979  * set pf load for the current pf.
3980  *
3981  * should be run under rtnl lock
3982  */
3983 void bnx2x_set_pf_load(struct bnx2x *bp)
3984 {
3985         u32 val1, val;
3986         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3987                              BNX2X_PATH0_LOAD_CNT_MASK;
3988         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3989                              BNX2X_PATH0_LOAD_CNT_SHIFT;
3990
3991         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3992         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3993
3994         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3995
3996         /* get the current counter value */
3997         val1 = (val & mask) >> shift;
3998
3999         /* set bit of that PF */
4000         val1 |= (1 << bp->pf_num);
4001
4002         /* clear the old value */
4003         val &= ~mask;
4004
4005         /* set the new one */
4006         val |= ((val1 << shift) & mask);
4007
4008         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4009         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4010 }
4011
4012 /**
4013  * bnx2x_clear_pf_load - clear pf load mark
4014  *
4015  * @bp:         driver handle
4016  *
4017  * Should be run under rtnl lock.
4018  * Decrements the load counter for the current engine. Returns
4019  * whether other functions are still loaded
4020  */
4021 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4022 {
4023         u32 val1, val;
4024         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4025                              BNX2X_PATH0_LOAD_CNT_MASK;
4026         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4027                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4028
4029         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4030         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4031         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4032
4033         /* get the current counter value */
4034         val1 = (val & mask) >> shift;
4035
4036         /* clear bit of that PF */
4037         val1 &= ~(1 << bp->pf_num);
4038
4039         /* clear the old value */
4040         val &= ~mask;
4041
4042         /* set the new one */
4043         val |= ((val1 << shift) & mask);
4044
4045         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4046         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4047         return val1 != 0;
4048 }
4049
4050 /*
4051  * Read the load status for the current engine.
4052  *
4053  * should be run under rtnl lock
4054  */
4055 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4056 {
4057         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4058                              BNX2X_PATH0_LOAD_CNT_MASK);
4059         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4060                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4061         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4062
4063         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4064
4065         val = (val & mask) >> shift;
4066
4067         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4068            engine, val);
4069
4070         return val != 0;
4071 }
4072
4073 static void _print_next_block(int idx, const char *blk)
4074 {
4075         pr_cont("%s%s", idx ? ", " : "", blk);
4076 }
4077
4078 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4079                                            bool print)
4080 {
4081         int i = 0;
4082         u32 cur_bit = 0;
4083         for (i = 0; sig; i++) {
4084                 cur_bit = ((u32)0x1 << i);
4085                 if (sig & cur_bit) {
4086                         switch (cur_bit) {
4087                         case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4088                                 if (print)
4089                                         _print_next_block(par_num++, "BRB");
4090                                 break;
4091                         case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4092                                 if (print)
4093                                         _print_next_block(par_num++, "PARSER");
4094                                 break;
4095                         case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4096                                 if (print)
4097                                         _print_next_block(par_num++, "TSDM");
4098                                 break;
4099                         case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4100                                 if (print)
4101                                         _print_next_block(par_num++,
4102                                                           "SEARCHER");
4103                                 break;
4104                         case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4105                                 if (print)
4106                                         _print_next_block(par_num++, "TCM");
4107                                 break;
4108                         case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4109                                 if (print)
4110                                         _print_next_block(par_num++, "TSEMI");
4111                                 break;
4112                         case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4113                                 if (print)
4114                                         _print_next_block(par_num++, "XPB");
4115                                 break;
4116                         }
4117
4118                         /* Clear the bit */
4119                         sig &= ~cur_bit;
4120                 }
4121         }
4122
4123         return par_num;
4124 }
4125
4126 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4127                                            bool *global, bool print)
4128 {
4129         int i = 0;
4130         u32 cur_bit = 0;
4131         for (i = 0; sig; i++) {
4132                 cur_bit = ((u32)0x1 << i);
4133                 if (sig & cur_bit) {
4134                         switch (cur_bit) {
4135                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4136                                 if (print)
4137                                         _print_next_block(par_num++, "PBF");
4138                                 break;
4139                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4140                                 if (print)
4141                                         _print_next_block(par_num++, "QM");
4142                                 break;
4143                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4144                                 if (print)
4145                                         _print_next_block(par_num++, "TM");
4146                                 break;
4147                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4148                                 if (print)
4149                                         _print_next_block(par_num++, "XSDM");
4150                                 break;
4151                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4152                                 if (print)
4153                                         _print_next_block(par_num++, "XCM");
4154                                 break;
4155                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4156                                 if (print)
4157                                         _print_next_block(par_num++, "XSEMI");
4158                                 break;
4159                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4160                                 if (print)
4161                                         _print_next_block(par_num++,
4162                                                           "DOORBELLQ");
4163                                 break;
4164                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4165                                 if (print)
4166                                         _print_next_block(par_num++, "NIG");
4167                                 break;
4168                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4169                                 if (print)
4170                                         _print_next_block(par_num++,
4171                                                           "VAUX PCI CORE");
4172                                 *global = true;
4173                                 break;
4174                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4175                                 if (print)
4176                                         _print_next_block(par_num++, "DEBUG");
4177                                 break;
4178                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4179                                 if (print)
4180                                         _print_next_block(par_num++, "USDM");
4181                                 break;
4182                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4183                                 if (print)
4184                                         _print_next_block(par_num++, "UCM");
4185                                 break;
4186                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4187                                 if (print)
4188                                         _print_next_block(par_num++, "USEMI");
4189                                 break;
4190                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4191                                 if (print)
4192                                         _print_next_block(par_num++, "UPB");
4193                                 break;
4194                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4195                                 if (print)
4196                                         _print_next_block(par_num++, "CSDM");
4197                                 break;
4198                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4199                                 if (print)
4200                                         _print_next_block(par_num++, "CCM");
4201                                 break;
4202                         }
4203
4204                         /* Clear the bit */
4205                         sig &= ~cur_bit;
4206                 }
4207         }
4208
4209         return par_num;
4210 }
4211
4212 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4213                                            bool print)
4214 {
4215         int i = 0;
4216         u32 cur_bit = 0;
4217         for (i = 0; sig; i++) {
4218                 cur_bit = ((u32)0x1 << i);
4219                 if (sig & cur_bit) {
4220                         switch (cur_bit) {
4221                         case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4222                                 if (print)
4223                                         _print_next_block(par_num++, "CSEMI");
4224                                 break;
4225                         case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4226                                 if (print)
4227                                         _print_next_block(par_num++, "PXP");
4228                                 break;
4229                         case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4230                                 if (print)
4231                                         _print_next_block(par_num++,
4232                                         "PXPPCICLOCKCLIENT");
4233                                 break;
4234                         case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4235                                 if (print)
4236                                         _print_next_block(par_num++, "CFC");
4237                                 break;
4238                         case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4239                                 if (print)
4240                                         _print_next_block(par_num++, "CDU");
4241                                 break;
4242                         case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4243                                 if (print)
4244                                         _print_next_block(par_num++, "DMAE");
4245                                 break;
4246                         case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4247                                 if (print)
4248                                         _print_next_block(par_num++, "IGU");
4249                                 break;
4250                         case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4251                                 if (print)
4252                                         _print_next_block(par_num++, "MISC");
4253                                 break;
4254                         }
4255
4256                         /* Clear the bit */
4257                         sig &= ~cur_bit;
4258                 }
4259         }
4260
4261         return par_num;
4262 }
4263
4264 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4265                                            bool *global, bool print)
4266 {
4267         int i = 0;
4268         u32 cur_bit = 0;
4269         for (i = 0; sig; i++) {
4270                 cur_bit = ((u32)0x1 << i);
4271                 if (sig & cur_bit) {
4272                         switch (cur_bit) {
4273                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4274                                 if (print)
4275                                         _print_next_block(par_num++, "MCP ROM");
4276                                 *global = true;
4277                                 break;
4278                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4279                                 if (print)
4280                                         _print_next_block(par_num++,
4281                                                           "MCP UMP RX");
4282                                 *global = true;
4283                                 break;
4284                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4285                                 if (print)
4286                                         _print_next_block(par_num++,
4287                                                           "MCP UMP TX");
4288                                 *global = true;
4289                                 break;
4290                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4291                                 if (print)
4292                                         _print_next_block(par_num++,
4293                                                           "MCP SCPAD");
4294                                 *global = true;
4295                                 break;
4296                         }
4297
4298                         /* Clear the bit */
4299                         sig &= ~cur_bit;
4300                 }
4301         }
4302
4303         return par_num;
4304 }
4305
4306 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4307                                            bool print)
4308 {
4309         int i = 0;
4310         u32 cur_bit = 0;
4311         for (i = 0; sig; i++) {
4312                 cur_bit = ((u32)0x1 << i);
4313                 if (sig & cur_bit) {
4314                         switch (cur_bit) {
4315                         case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4316                                 if (print)
4317                                         _print_next_block(par_num++, "PGLUE_B");
4318                                 break;
4319                         case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4320                                 if (print)
4321                                         _print_next_block(par_num++, "ATC");
4322                                 break;
4323                         }
4324
4325                         /* Clear the bit */
4326                         sig &= ~cur_bit;
4327                 }
4328         }
4329
4330         return par_num;
4331 }
4332
4333 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4334                               u32 *sig)
4335 {
4336         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4337             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4338             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4339             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4340             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4341                 int par_num = 0;
4342                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4343                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4344                           sig[0] & HW_PRTY_ASSERT_SET_0,
4345                           sig[1] & HW_PRTY_ASSERT_SET_1,
4346                           sig[2] & HW_PRTY_ASSERT_SET_2,
4347                           sig[3] & HW_PRTY_ASSERT_SET_3,
4348                           sig[4] & HW_PRTY_ASSERT_SET_4);
4349                 if (print)
4350                         netdev_err(bp->dev,
4351                                    "Parity errors detected in blocks: ");
4352                 par_num = bnx2x_check_blocks_with_parity0(
4353                         sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4354                 par_num = bnx2x_check_blocks_with_parity1(
4355                         sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4356                 par_num = bnx2x_check_blocks_with_parity2(
4357                         sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4358                 par_num = bnx2x_check_blocks_with_parity3(
4359                         sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4360                 par_num = bnx2x_check_blocks_with_parity4(
4361                         sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4362
4363                 if (print)
4364                         pr_cont("\n");
4365
4366                 return true;
4367         } else
4368                 return false;
4369 }
4370
4371 /**
4372  * bnx2x_chk_parity_attn - checks for parity attentions.
4373  *
4374  * @bp:         driver handle
4375  * @global:     true if there was a global attention
4376  * @print:      show parity attention in syslog
4377  */
4378 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4379 {
4380         struct attn_route attn = { {0} };
4381         int port = BP_PORT(bp);
4382
4383         attn.sig[0] = REG_RD(bp,
4384                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4385                              port*4);
4386         attn.sig[1] = REG_RD(bp,
4387                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4388                              port*4);
4389         attn.sig[2] = REG_RD(bp,
4390                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4391                              port*4);
4392         attn.sig[3] = REG_RD(bp,
4393                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4394                              port*4);
4395
4396         if (!CHIP_IS_E1x(bp))
4397                 attn.sig[4] = REG_RD(bp,
4398                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4399                                      port*4);
4400
4401         return bnx2x_parity_attn(bp, global, print, attn.sig);
4402 }
4403
4404
4405 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4406 {
4407         u32 val;
4408         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4409
4410                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4411                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4412                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4413                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4414                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4415                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4416                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4417                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4418                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4419                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4420                 if (val &
4421                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4422                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4423                 if (val &
4424                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4425                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4426                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4427                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4428                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4429                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4430                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4431                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4432         }
4433         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4434                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4435                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4436                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4437                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4438                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4439                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4440                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4441                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4442                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4443                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4444                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4445                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4446                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4447                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4448         }
4449
4450         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4451                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4452                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4453                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4454                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4455         }
4456
4457 }
4458
4459 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4460 {
4461         struct attn_route attn, *group_mask;
4462         int port = BP_PORT(bp);
4463         int index;
4464         u32 reg_addr;
4465         u32 val;
4466         u32 aeu_mask;
4467         bool global = false;
4468
4469         /* need to take HW lock because MCP or other port might also
4470            try to handle this event */
4471         bnx2x_acquire_alr(bp);
4472
4473         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4474 #ifndef BNX2X_STOP_ON_ERROR
4475                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4476                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4477                 /* Disable HW interrupts */
4478                 bnx2x_int_disable(bp);
4479                 /* In case of parity errors don't handle attentions so that
4480                  * other function would "see" parity errors.
4481                  */
4482 #else
4483                 bnx2x_panic();
4484 #endif
4485                 bnx2x_release_alr(bp);
4486                 return;
4487         }
4488
4489         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4490         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4491         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4492         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4493         if (!CHIP_IS_E1x(bp))
4494                 attn.sig[4] =
4495                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4496         else
4497                 attn.sig[4] = 0;
4498
4499         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4500            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4501
4502         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4503                 if (deasserted & (1 << index)) {
4504                         group_mask = &bp->attn_group[index];
4505
4506                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4507                            index,
4508                            group_mask->sig[0], group_mask->sig[1],
4509                            group_mask->sig[2], group_mask->sig[3],
4510                            group_mask->sig[4]);
4511
4512                         bnx2x_attn_int_deasserted4(bp,
4513                                         attn.sig[4] & group_mask->sig[4]);
4514                         bnx2x_attn_int_deasserted3(bp,
4515                                         attn.sig[3] & group_mask->sig[3]);
4516                         bnx2x_attn_int_deasserted1(bp,
4517                                         attn.sig[1] & group_mask->sig[1]);
4518                         bnx2x_attn_int_deasserted2(bp,
4519                                         attn.sig[2] & group_mask->sig[2]);
4520                         bnx2x_attn_int_deasserted0(bp,
4521                                         attn.sig[0] & group_mask->sig[0]);
4522                 }
4523         }
4524
4525         bnx2x_release_alr(bp);
4526
4527         if (bp->common.int_block == INT_BLOCK_HC)
4528                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4529                             COMMAND_REG_ATTN_BITS_CLR);
4530         else
4531                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4532
4533         val = ~deasserted;
4534         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4535            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4536         REG_WR(bp, reg_addr, val);
4537
4538         if (~bp->attn_state & deasserted)
4539                 BNX2X_ERR("IGU ERROR\n");
4540
4541         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4542                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4543
4544         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4545         aeu_mask = REG_RD(bp, reg_addr);
4546
4547         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4548            aeu_mask, deasserted);
4549         aeu_mask |= (deasserted & 0x3ff);
4550         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4551
4552         REG_WR(bp, reg_addr, aeu_mask);
4553         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4554
4555         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4556         bp->attn_state &= ~deasserted;
4557         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4558 }
4559
4560 static void bnx2x_attn_int(struct bnx2x *bp)
4561 {
4562         /* read local copy of bits */
4563         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4564                                                                 attn_bits);
4565         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4566                                                                 attn_bits_ack);
4567         u32 attn_state = bp->attn_state;
4568
4569         /* look for changed bits */
4570         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4571         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4572
4573         DP(NETIF_MSG_HW,
4574            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4575            attn_bits, attn_ack, asserted, deasserted);
4576
4577         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4578                 BNX2X_ERR("BAD attention state\n");
4579
4580         /* handle bits that were raised */
4581         if (asserted)
4582                 bnx2x_attn_int_asserted(bp, asserted);
4583
4584         if (deasserted)
4585                 bnx2x_attn_int_deasserted(bp, deasserted);
4586 }
4587
4588 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4589                       u16 index, u8 op, u8 update)
4590 {
4591         u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4592
4593         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4594                              igu_addr);
4595 }
4596
4597 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4598 {
4599         /* No memory barriers */
4600         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4601         mmiowb(); /* keep prod updates ordered */
4602 }
4603
4604 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4605                                       union event_ring_elem *elem)
4606 {
4607         u8 err = elem->message.error;
4608
4609         if (!bp->cnic_eth_dev.starting_cid  ||
4610             (cid < bp->cnic_eth_dev.starting_cid &&
4611             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4612                 return 1;
4613
4614         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4615
4616         if (unlikely(err)) {
4617
4618                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4619                           cid);
4620                 bnx2x_panic_dump(bp);
4621         }
4622         bnx2x_cnic_cfc_comp(bp, cid, err);
4623         return 0;
4624 }
4625
4626 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4627 {
4628         struct bnx2x_mcast_ramrod_params rparam;
4629         int rc;
4630
4631         memset(&rparam, 0, sizeof(rparam));
4632
4633         rparam.mcast_obj = &bp->mcast_obj;
4634
4635         netif_addr_lock_bh(bp->dev);
4636
4637         /* Clear pending state for the last command */
4638         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4639
4640         /* If there are pending mcast commands - send them */
4641         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4642                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4643                 if (rc < 0)
4644                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4645                                   rc);
4646         }
4647
4648         netif_addr_unlock_bh(bp->dev);
4649 }
4650
4651 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4652                                             union event_ring_elem *elem)
4653 {
4654         unsigned long ramrod_flags = 0;
4655         int rc = 0;
4656         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4657         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4658
4659         /* Always push next commands out, don't wait here */
4660         __set_bit(RAMROD_CONT, &ramrod_flags);
4661
4662         switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4663         case BNX2X_FILTER_MAC_PENDING:
4664                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4665                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4666                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4667                 else
4668                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4669
4670                 break;
4671         case BNX2X_FILTER_MCAST_PENDING:
4672                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4673                 /* This is only relevant for 57710 where multicast MACs are
4674                  * configured as unicast MACs using the same ramrod.
4675                  */
4676                 bnx2x_handle_mcast_eqe(bp);
4677                 return;
4678         default:
4679                 BNX2X_ERR("Unsupported classification command: %d\n",
4680                           elem->message.data.eth_event.echo);
4681                 return;
4682         }
4683
4684         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4685
4686         if (rc < 0)
4687                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4688         else if (rc > 0)
4689                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4690
4691 }
4692
4693 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4694
4695 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4696 {
4697         netif_addr_lock_bh(bp->dev);
4698
4699         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4700
4701         /* Send rx_mode command again if was requested */
4702         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4703                 bnx2x_set_storm_rx_mode(bp);
4704         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4705                                     &bp->sp_state))
4706                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4707         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4708                                     &bp->sp_state))
4709                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4710
4711         netif_addr_unlock_bh(bp->dev);
4712 }
4713
4714 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4715                                               union event_ring_elem *elem)
4716 {
4717         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4718                 DP(BNX2X_MSG_SP,
4719                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4720                    elem->message.data.vif_list_event.func_bit_map);
4721                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4722                         elem->message.data.vif_list_event.func_bit_map);
4723         } else if (elem->message.data.vif_list_event.echo ==
4724                    VIF_LIST_RULE_SET) {
4725                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4726                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4727         }
4728 }
4729
4730 /* called with rtnl_lock */
4731 static void bnx2x_after_function_update(struct bnx2x *bp)
4732 {
4733         int q, rc;
4734         struct bnx2x_fastpath *fp;
4735         struct bnx2x_queue_state_params queue_params = {NULL};
4736         struct bnx2x_queue_update_params *q_update_params =
4737                 &queue_params.params.update;
4738
4739         /* Send Q update command with afex vlan removal values  for all Qs */
4740         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4741
4742         /* set silent vlan removal values according to vlan mode */
4743         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4744                   &q_update_params->update_flags);
4745         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4746                   &q_update_params->update_flags);
4747         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4748
4749         /* in access mode mark mask and value are 0 to strip all vlans */
4750         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4751                 q_update_params->silent_removal_value = 0;
4752                 q_update_params->silent_removal_mask = 0;
4753         } else {
4754                 q_update_params->silent_removal_value =
4755                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4756                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4757         }
4758
4759         for_each_eth_queue(bp, q) {
4760                 /* Set the appropriate Queue object */
4761                 fp = &bp->fp[q];
4762                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4763
4764                 /* send the ramrod */
4765                 rc = bnx2x_queue_state_change(bp, &queue_params);
4766                 if (rc < 0)
4767                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4768                                   q);
4769         }
4770
4771         if (!NO_FCOE(bp)) {
4772                 fp = &bp->fp[FCOE_IDX(bp)];
4773                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4774
4775                 /* clear pending completion bit */
4776                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4777
4778                 /* mark latest Q bit */
4779                 smp_mb__before_clear_bit();
4780                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4781                 smp_mb__after_clear_bit();
4782
4783                 /* send Q update ramrod for FCoE Q */
4784                 rc = bnx2x_queue_state_change(bp, &queue_params);
4785                 if (rc < 0)
4786                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4787                                   q);
4788         } else {
4789                 /* If no FCoE ring - ACK MCP now */
4790                 bnx2x_link_report(bp);
4791                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4792         }
4793 }
4794
4795 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4796         struct bnx2x *bp, u32 cid)
4797 {
4798         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4799
4800         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4801                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4802         else
4803                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4804 }
4805
4806 static void bnx2x_eq_int(struct bnx2x *bp)
4807 {
4808         u16 hw_cons, sw_cons, sw_prod;
4809         union event_ring_elem *elem;
4810         u8 echo;
4811         u32 cid;
4812         u8 opcode;
4813         int spqe_cnt = 0;
4814         struct bnx2x_queue_sp_obj *q_obj;
4815         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4816         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4817
4818         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4819
4820         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4821          * when we get the the next-page we nned to adjust so the loop
4822          * condition below will be met. The next element is the size of a
4823          * regular element and hence incrementing by 1
4824          */
4825         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4826                 hw_cons++;
4827
4828         /* This function may never run in parallel with itself for a
4829          * specific bp, thus there is no need in "paired" read memory
4830          * barrier here.
4831          */
4832         sw_cons = bp->eq_cons;
4833         sw_prod = bp->eq_prod;
4834
4835         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
4836                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4837
4838         for (; sw_cons != hw_cons;
4839               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4840
4841
4842                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4843
4844                 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4845                 opcode = elem->message.opcode;
4846
4847
4848                 /* handle eq element */
4849                 switch (opcode) {
4850                 case EVENT_RING_OPCODE_STAT_QUERY:
4851                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4852                            "got statistics comp event %d\n",
4853                            bp->stats_comp++);
4854                         /* nothing to do with stats comp */
4855                         goto next_spqe;
4856
4857                 case EVENT_RING_OPCODE_CFC_DEL:
4858                         /* handle according to cid range */
4859                         /*
4860                          * we may want to verify here that the bp state is
4861                          * HALTING
4862                          */
4863                         DP(BNX2X_MSG_SP,
4864                            "got delete ramrod for MULTI[%d]\n", cid);
4865
4866                         if (CNIC_LOADED(bp) &&
4867                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4868                                 goto next_spqe;
4869
4870                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
4871
4872                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4873                                 break;
4874
4875
4876
4877                         goto next_spqe;
4878
4879                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4880                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4881                         if (f_obj->complete_cmd(bp, f_obj,
4882                                                 BNX2X_F_CMD_TX_STOP))
4883                                 break;
4884                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4885                         goto next_spqe;
4886
4887                 case EVENT_RING_OPCODE_START_TRAFFIC:
4888                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4889                         if (f_obj->complete_cmd(bp, f_obj,
4890                                                 BNX2X_F_CMD_TX_START))
4891                                 break;
4892                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4893                         goto next_spqe;
4894
4895                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4896                         echo = elem->message.data.function_update_event.echo;
4897                         if (echo == SWITCH_UPDATE) {
4898                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4899                                    "got FUNC_SWITCH_UPDATE ramrod\n");
4900                                 if (f_obj->complete_cmd(
4901                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
4902                                         break;
4903
4904                         } else {
4905                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4906                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
4907                                 f_obj->complete_cmd(bp, f_obj,
4908                                                     BNX2X_F_CMD_AFEX_UPDATE);
4909
4910                                 /* We will perform the Queues update from
4911                                  * sp_rtnl task as all Queue SP operations
4912                                  * should run under rtnl_lock.
4913                                  */
4914                                 smp_mb__before_clear_bit();
4915                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4916                                         &bp->sp_rtnl_state);
4917                                 smp_mb__after_clear_bit();
4918
4919                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4920                         }
4921
4922                         goto next_spqe;
4923
4924                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4925                         f_obj->complete_cmd(bp, f_obj,
4926                                             BNX2X_F_CMD_AFEX_VIFLISTS);
4927                         bnx2x_after_afex_vif_lists(bp, elem);
4928                         goto next_spqe;
4929                 case EVENT_RING_OPCODE_FUNCTION_START:
4930                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4931                            "got FUNC_START ramrod\n");
4932                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4933                                 break;
4934
4935                         goto next_spqe;
4936
4937                 case EVENT_RING_OPCODE_FUNCTION_STOP:
4938                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4939                            "got FUNC_STOP ramrod\n");
4940                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4941                                 break;
4942
4943                         goto next_spqe;
4944                 }
4945
4946                 switch (opcode | bp->state) {
4947                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4948                       BNX2X_STATE_OPEN):
4949                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4950                       BNX2X_STATE_OPENING_WAIT4_PORT):
4951                         cid = elem->message.data.eth_event.echo &
4952                                 BNX2X_SWCID_MASK;
4953                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4954                            cid);
4955                         rss_raw->clear_pending(rss_raw);
4956                         break;
4957
4958                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4959                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4960                 case (EVENT_RING_OPCODE_SET_MAC |
4961                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4962                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4963                       BNX2X_STATE_OPEN):
4964                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4965                       BNX2X_STATE_DIAG):
4966                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4967                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4968                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4969                         bnx2x_handle_classification_eqe(bp, elem);
4970                         break;
4971
4972                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4973                       BNX2X_STATE_OPEN):
4974                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4975                       BNX2X_STATE_DIAG):
4976                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4977                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4978                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4979                         bnx2x_handle_mcast_eqe(bp);
4980                         break;
4981
4982                 case (EVENT_RING_OPCODE_FILTERS_RULES |
4983                       BNX2X_STATE_OPEN):
4984                 case (EVENT_RING_OPCODE_FILTERS_RULES |
4985                       BNX2X_STATE_DIAG):
4986                 case (EVENT_RING_OPCODE_FILTERS_RULES |
4987                       BNX2X_STATE_CLOSING_WAIT4_HALT):
4988                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4989                         bnx2x_handle_rx_mode_eqe(bp);
4990                         break;
4991                 default:
4992                         /* unknown event log error and continue */
4993                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4994                                   elem->message.opcode, bp->state);
4995                 }
4996 next_spqe:
4997                 spqe_cnt++;
4998         } /* for */
4999
5000         smp_mb__before_atomic_inc();
5001         atomic_add(spqe_cnt, &bp->eq_spq_left);
5002
5003         bp->eq_cons = sw_cons;
5004         bp->eq_prod = sw_prod;
5005         /* Make sure that above mem writes were issued towards the memory */
5006         smp_wmb();
5007
5008         /* update producer */
5009         bnx2x_update_eq_prod(bp, bp->eq_prod);
5010 }
5011
5012 static void bnx2x_sp_task(struct work_struct *work)
5013 {
5014         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5015         u16 status;
5016
5017         status = bnx2x_update_dsb_idx(bp);
5018 /*      if (status == 0)                                     */
5019 /*              BNX2X_ERR("spurious slowpath interrupt!\n"); */
5020
5021         DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
5022
5023         /* HW attentions */
5024         if (status & BNX2X_DEF_SB_ATT_IDX) {
5025                 bnx2x_attn_int(bp);
5026                 status &= ~BNX2X_DEF_SB_ATT_IDX;
5027         }
5028
5029         /* SP events: STAT_QUERY and others */
5030         if (status & BNX2X_DEF_SB_IDX) {
5031                 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5032
5033                 if (FCOE_INIT(bp) &&
5034                     (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5035                         /*
5036                          * Prevent local bottom-halves from running as
5037                          * we are going to change the local NAPI list.
5038                          */
5039                         local_bh_disable();
5040                         napi_schedule(&bnx2x_fcoe(bp, napi));
5041                         local_bh_enable();
5042                 }
5043
5044                 /* Handle EQ completions */
5045                 bnx2x_eq_int(bp);
5046
5047                 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5048                         le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5049
5050                 status &= ~BNX2X_DEF_SB_IDX;
5051         }
5052
5053         if (unlikely(status))
5054                 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5055                    status);
5056
5057         bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5058              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5059
5060         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5061         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5062                                &bp->sp_state)) {
5063                 bnx2x_link_report(bp);
5064                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5065         }
5066 }
5067
5068 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5069 {
5070         struct net_device *dev = dev_instance;
5071         struct bnx2x *bp = netdev_priv(dev);
5072
5073         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5074                      IGU_INT_DISABLE, 0);
5075
5076 #ifdef BNX2X_STOP_ON_ERROR
5077         if (unlikely(bp->panic))
5078                 return IRQ_HANDLED;
5079 #endif
5080
5081         if (CNIC_LOADED(bp)) {
5082                 struct cnic_ops *c_ops;
5083
5084                 rcu_read_lock();
5085                 c_ops = rcu_dereference(bp->cnic_ops);
5086                 if (c_ops)
5087                         c_ops->cnic_handler(bp->cnic_data, NULL);
5088                 rcu_read_unlock();
5089         }
5090
5091         queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5092
5093         return IRQ_HANDLED;
5094 }
5095
5096 /* end of slow path */
5097
5098
5099 void bnx2x_drv_pulse(struct bnx2x *bp)
5100 {
5101         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5102                  bp->fw_drv_pulse_wr_seq);
5103 }
5104
5105
5106 static void bnx2x_timer(unsigned long data)
5107 {
5108         struct bnx2x *bp = (struct bnx2x *) data;
5109
5110         if (!netif_running(bp->dev))
5111                 return;
5112
5113         if (!BP_NOMCP(bp)) {
5114                 int mb_idx = BP_FW_MB_IDX(bp);
5115                 u32 drv_pulse;
5116                 u32 mcp_pulse;
5117
5118                 ++bp->fw_drv_pulse_wr_seq;
5119                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5120                 /* TBD - add SYSTEM_TIME */
5121                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5122                 bnx2x_drv_pulse(bp);
5123
5124                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5125                              MCP_PULSE_SEQ_MASK);
5126                 /* The delta between driver pulse and mcp response
5127                  * should be 1 (before mcp response) or 0 (after mcp response)
5128                  */
5129                 if ((drv_pulse != mcp_pulse) &&
5130                     (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5131                         /* someone lost a heartbeat... */
5132                         BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5133                                   drv_pulse, mcp_pulse);
5134                 }
5135         }
5136
5137         if (bp->state == BNX2X_STATE_OPEN)
5138                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5139
5140         mod_timer(&bp->timer, jiffies + bp->current_interval);
5141 }
5142
5143 /* end of Statistics */
5144
5145 /* nic init */
5146
5147 /*
5148  * nic init service functions
5149  */
5150
5151 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5152 {
5153         u32 i;
5154         if (!(len%4) && !(addr%4))
5155                 for (i = 0; i < len; i += 4)
5156                         REG_WR(bp, addr + i, fill);
5157         else
5158                 for (i = 0; i < len; i++)
5159                         REG_WR8(bp, addr + i, fill);
5160
5161 }
5162
5163 /* helper: writes FP SP data to FW - data_size in dwords */
5164 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5165                                 int fw_sb_id,
5166                                 u32 *sb_data_p,
5167                                 u32 data_size)
5168 {
5169         int index;
5170         for (index = 0; index < data_size; index++)
5171                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5172                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5173                         sizeof(u32)*index,
5174                         *(sb_data_p + index));
5175 }
5176
5177 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5178 {
5179         u32 *sb_data_p;
5180         u32 data_size = 0;
5181         struct hc_status_block_data_e2 sb_data_e2;
5182         struct hc_status_block_data_e1x sb_data_e1x;
5183
5184         /* disable the function first */
5185         if (!CHIP_IS_E1x(bp)) {
5186                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5187                 sb_data_e2.common.state = SB_DISABLED;
5188                 sb_data_e2.common.p_func.vf_valid = false;
5189                 sb_data_p = (u32 *)&sb_data_e2;
5190                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5191         } else {
5192                 memset(&sb_data_e1x, 0,
5193                        sizeof(struct hc_status_block_data_e1x));
5194                 sb_data_e1x.common.state = SB_DISABLED;
5195                 sb_data_e1x.common.p_func.vf_valid = false;
5196                 sb_data_p = (u32 *)&sb_data_e1x;
5197                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5198         }
5199         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5200
5201         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5202                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5203                         CSTORM_STATUS_BLOCK_SIZE);
5204         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5205                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5206                         CSTORM_SYNC_BLOCK_SIZE);
5207 }
5208
5209 /* helper:  writes SP SB data to FW */
5210 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5211                 struct hc_sp_status_block_data *sp_sb_data)
5212 {
5213         int func = BP_FUNC(bp);
5214         int i;
5215         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5216                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5217                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5218                         i*sizeof(u32),
5219                         *((u32 *)sp_sb_data + i));
5220 }
5221
5222 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5223 {
5224         int func = BP_FUNC(bp);
5225         struct hc_sp_status_block_data sp_sb_data;
5226         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5227
5228         sp_sb_data.state = SB_DISABLED;
5229         sp_sb_data.p_func.vf_valid = false;
5230
5231         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5232
5233         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5234                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5235                         CSTORM_SP_STATUS_BLOCK_SIZE);
5236         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5237                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5238                         CSTORM_SP_SYNC_BLOCK_SIZE);
5239
5240 }
5241
5242
5243 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5244                                            int igu_sb_id, int igu_seg_id)
5245 {
5246         hc_sm->igu_sb_id = igu_sb_id;
5247         hc_sm->igu_seg_id = igu_seg_id;
5248         hc_sm->timer_value = 0xFF;
5249         hc_sm->time_to_expire = 0xFFFFFFFF;
5250 }
5251
5252
5253 /* allocates state machine ids. */
5254 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5255 {
5256         /* zero out state machine indices */
5257         /* rx indices */
5258         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5259
5260         /* tx indices */
5261         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5262         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5263         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5264         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5265
5266         /* map indices */
5267         /* rx indices */
5268         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5269                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5270
5271         /* tx indices */
5272         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5273                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5274         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5275                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5276         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5277                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5278         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5279                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5280 }
5281
5282 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5283                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5284 {
5285         int igu_seg_id;
5286
5287         struct hc_status_block_data_e2 sb_data_e2;
5288         struct hc_status_block_data_e1x sb_data_e1x;
5289         struct hc_status_block_sm  *hc_sm_p;
5290         int data_size;
5291         u32 *sb_data_p;
5292
5293         if (CHIP_INT_MODE_IS_BC(bp))
5294                 igu_seg_id = HC_SEG_ACCESS_NORM;
5295         else
5296                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5297
5298         bnx2x_zero_fp_sb(bp, fw_sb_id);
5299
5300         if (!CHIP_IS_E1x(bp)) {
5301                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5302                 sb_data_e2.common.state = SB_ENABLED;
5303                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5304                 sb_data_e2.common.p_func.vf_id = vfid;
5305                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5306                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5307                 sb_data_e2.common.same_igu_sb_1b = true;
5308                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5309                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5310                 hc_sm_p = sb_data_e2.common.state_machine;
5311                 sb_data_p = (u32 *)&sb_data_e2;
5312                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5313                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5314         } else {
5315                 memset(&sb_data_e1x, 0,
5316                        sizeof(struct hc_status_block_data_e1x));
5317                 sb_data_e1x.common.state = SB_ENABLED;
5318                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5319                 sb_data_e1x.common.p_func.vf_id = 0xff;
5320                 sb_data_e1x.common.p_func.vf_valid = false;
5321                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5322                 sb_data_e1x.common.same_igu_sb_1b = true;
5323                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5324                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5325                 hc_sm_p = sb_data_e1x.common.state_machine;
5326                 sb_data_p = (u32 *)&sb_data_e1x;
5327                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5328                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5329         }
5330
5331         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5332                                        igu_sb_id, igu_seg_id);
5333         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5334                                        igu_sb_id, igu_seg_id);
5335
5336         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5337
5338         /* write indecies to HW */
5339         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5340 }
5341
5342 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5343                                      u16 tx_usec, u16 rx_usec)
5344 {
5345         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5346                                     false, rx_usec);
5347         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5348                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5349                                        tx_usec);
5350         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5351                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5352                                        tx_usec);
5353         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5354                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5355                                        tx_usec);
5356 }
5357
5358 static void bnx2x_init_def_sb(struct bnx2x *bp)
5359 {
5360         struct host_sp_status_block *def_sb = bp->def_status_blk;
5361         dma_addr_t mapping = bp->def_status_blk_mapping;
5362         int igu_sp_sb_index;
5363         int igu_seg_id;
5364         int port = BP_PORT(bp);
5365         int func = BP_FUNC(bp);
5366         int reg_offset, reg_offset_en5;
5367         u64 section;
5368         int index;
5369         struct hc_sp_status_block_data sp_sb_data;
5370         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5371
5372         if (CHIP_INT_MODE_IS_BC(bp)) {
5373                 igu_sp_sb_index = DEF_SB_IGU_ID;
5374                 igu_seg_id = HC_SEG_ACCESS_DEF;
5375         } else {
5376                 igu_sp_sb_index = bp->igu_dsb_id;
5377                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5378         }
5379
5380         /* ATTN */
5381         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5382                                             atten_status_block);
5383         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5384
5385         bp->attn_state = 0;
5386
5387         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5388                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5389         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5390                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5391         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5392                 int sindex;
5393                 /* take care of sig[0]..sig[4] */
5394                 for (sindex = 0; sindex < 4; sindex++)
5395                         bp->attn_group[index].sig[sindex] =
5396                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5397
5398                 if (!CHIP_IS_E1x(bp))
5399                         /*
5400                          * enable5 is separate from the rest of the registers,
5401                          * and therefore the address skip is 4
5402                          * and not 16 between the different groups
5403                          */
5404                         bp->attn_group[index].sig[4] = REG_RD(bp,
5405                                         reg_offset_en5 + 0x4*index);
5406                 else
5407                         bp->attn_group[index].sig[4] = 0;
5408         }
5409
5410         if (bp->common.int_block == INT_BLOCK_HC) {
5411                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5412                                      HC_REG_ATTN_MSG0_ADDR_L);
5413
5414                 REG_WR(bp, reg_offset, U64_LO(section));
5415                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5416         } else if (!CHIP_IS_E1x(bp)) {
5417                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5418                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5419         }
5420
5421         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5422                                             sp_sb);
5423
5424         bnx2x_zero_sp_sb(bp);
5425
5426         sp_sb_data.state                = SB_ENABLED;
5427         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5428         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5429         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5430         sp_sb_data.igu_seg_id           = igu_seg_id;
5431         sp_sb_data.p_func.pf_id         = func;
5432         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5433         sp_sb_data.p_func.vf_id         = 0xff;
5434
5435         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5436
5437         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5438 }
5439
5440 void bnx2x_update_coalesce(struct bnx2x *bp)
5441 {
5442         int i;
5443
5444         for_each_eth_queue(bp, i)
5445                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5446                                          bp->tx_ticks, bp->rx_ticks);
5447 }
5448
5449 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5450 {
5451         spin_lock_init(&bp->spq_lock);
5452         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5453
5454         bp->spq_prod_idx = 0;
5455         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5456         bp->spq_prod_bd = bp->spq;
5457         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5458 }
5459
5460 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5461 {
5462         int i;
5463         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5464                 union event_ring_elem *elem =
5465                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5466
5467                 elem->next_page.addr.hi =
5468                         cpu_to_le32(U64_HI(bp->eq_mapping +
5469                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5470                 elem->next_page.addr.lo =
5471                         cpu_to_le32(U64_LO(bp->eq_mapping +
5472                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5473         }
5474         bp->eq_cons = 0;
5475         bp->eq_prod = NUM_EQ_DESC;
5476         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5477         /* we want a warning message before it gets rought... */
5478         atomic_set(&bp->eq_spq_left,
5479                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5480 }
5481
5482
5483 /* called with netif_addr_lock_bh() */
5484 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5485                          unsigned long rx_mode_flags,
5486                          unsigned long rx_accept_flags,
5487                          unsigned long tx_accept_flags,
5488                          unsigned long ramrod_flags)
5489 {
5490         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5491         int rc;
5492
5493         memset(&ramrod_param, 0, sizeof(ramrod_param));
5494
5495         /* Prepare ramrod parameters */
5496         ramrod_param.cid = 0;
5497         ramrod_param.cl_id = cl_id;
5498         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5499         ramrod_param.func_id = BP_FUNC(bp);
5500
5501         ramrod_param.pstate = &bp->sp_state;
5502         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5503
5504         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5505         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5506
5507         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5508
5509         ramrod_param.ramrod_flags = ramrod_flags;
5510         ramrod_param.rx_mode_flags = rx_mode_flags;
5511
5512         ramrod_param.rx_accept_flags = rx_accept_flags;
5513         ramrod_param.tx_accept_flags = tx_accept_flags;
5514
5515         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5516         if (rc < 0) {
5517                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5518                 return;
5519         }
5520 }
5521
5522 /* called with netif_addr_lock_bh() */
5523 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5524 {
5525         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5526         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5527
5528         if (!NO_FCOE(bp))
5529
5530                 /* Configure rx_mode of FCoE Queue */
5531                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5532
5533         switch (bp->rx_mode) {
5534         case BNX2X_RX_MODE_NONE:
5535                 /*
5536                  * 'drop all' supersedes any accept flags that may have been
5537                  * passed to the function.
5538                  */
5539                 break;
5540         case BNX2X_RX_MODE_NORMAL:
5541                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5542                 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5543                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5544
5545                 /* internal switching mode */
5546                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5547                 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5548                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5549
5550                 break;
5551         case BNX2X_RX_MODE_ALLMULTI:
5552                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5553                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5554                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5555
5556                 /* internal switching mode */
5557                 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5558                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5559                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5560
5561                 break;
5562         case BNX2X_RX_MODE_PROMISC:
5563                 /* According to deffinition of SI mode, iface in promisc mode
5564                  * should receive matched and unmatched (in resolution of port)
5565                  * unicast packets.
5566                  */
5567                 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5568                 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5569                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5570                 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5571
5572                 /* internal switching mode */
5573                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5574                 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5575
5576                 if (IS_MF_SI(bp))
5577                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5578                 else
5579                         __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5580
5581                 break;
5582         default:
5583                 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5584                 return;
5585         }
5586
5587         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5588                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5589                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5590         }
5591
5592         __set_bit(RAMROD_RX, &ramrod_flags);
5593         __set_bit(RAMROD_TX, &ramrod_flags);
5594
5595         bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5596                             tx_accept_flags, ramrod_flags);
5597 }
5598
5599 static void bnx2x_init_internal_common(struct bnx2x *bp)
5600 {
5601         int i;
5602
5603         if (IS_MF_SI(bp))
5604                 /*
5605                  * In switch independent mode, the TSTORM needs to accept
5606                  * packets that failed classification, since approximate match
5607                  * mac addresses aren't written to NIG LLH
5608                  */
5609                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5610                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5611         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5612                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5613                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5614
5615         /* Zero this manually as its initialization is
5616            currently missing in the initTool */
5617         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5618                 REG_WR(bp, BAR_USTRORM_INTMEM +
5619                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
5620         if (!CHIP_IS_E1x(bp)) {
5621                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5622                         CHIP_INT_MODE_IS_BC(bp) ?
5623                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5624         }
5625 }
5626
5627 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5628 {
5629         switch (load_code) {
5630         case FW_MSG_CODE_DRV_LOAD_COMMON:
5631         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5632                 bnx2x_init_internal_common(bp);
5633                 /* no break */
5634
5635         case FW_MSG_CODE_DRV_LOAD_PORT:
5636                 /* nothing to do */
5637                 /* no break */
5638
5639         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5640                 /* internal memory per function is
5641                    initialized inside bnx2x_pf_init */
5642                 break;
5643
5644         default:
5645                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5646                 break;
5647         }
5648 }
5649
5650 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5651 {
5652         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5653 }
5654
5655 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5656 {
5657         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5658 }
5659
5660 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5661 {
5662         if (CHIP_IS_E1x(fp->bp))
5663                 return BP_L_ID(fp->bp) + fp->index;
5664         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
5665                 return bnx2x_fp_igu_sb_id(fp);
5666 }
5667
5668 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5669 {
5670         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5671         u8 cos;
5672         unsigned long q_type = 0;
5673         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5674         fp->rx_queue = fp_idx;
5675         fp->cid = fp_idx;
5676         fp->cl_id = bnx2x_fp_cl_id(fp);
5677         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5678         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5679         /* qZone id equals to FW (per path) client id */
5680         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
5681
5682         /* init shortcut */
5683         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5684
5685         /* Setup SB indicies */
5686         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5687
5688         /* Configure Queue State object */
5689         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5690         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5691
5692         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5693
5694         /* init tx data */
5695         for_each_cos_in_tx_queue(fp, cos) {
5696                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5697                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5698                                   FP_COS_TO_TXQ(fp, cos, bp),
5699                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
5700                 cids[cos] = fp->txdata_ptr[cos]->cid;
5701         }
5702
5703         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5704                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5705                              bnx2x_sp_mapping(bp, q_rdata), q_type);
5706
5707         /**
5708          * Configure classification DBs: Always enable Tx switching
5709          */
5710         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5711
5712         DP(NETIF_MSG_IFUP, "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
5713                    fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5714                    fp->igu_sb_id);
5715         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5716                       fp->fw_sb_id, fp->igu_sb_id);
5717
5718         bnx2x_update_fpsb_idx(fp);
5719 }
5720
5721 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5722 {
5723         int i;
5724
5725         for (i = 1; i <= NUM_TX_RINGS; i++) {
5726                 struct eth_tx_next_bd *tx_next_bd =
5727                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5728
5729                 tx_next_bd->addr_hi =
5730                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5731                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5732                 tx_next_bd->addr_lo =
5733                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5734                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5735         }
5736
5737         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5738         txdata->tx_db.data.zero_fill1 = 0;
5739         txdata->tx_db.data.prod = 0;
5740
5741         txdata->tx_pkt_prod = 0;
5742         txdata->tx_pkt_cons = 0;
5743         txdata->tx_bd_prod = 0;
5744         txdata->tx_bd_cons = 0;
5745         txdata->tx_pkt = 0;
5746 }
5747
5748 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5749 {
5750         int i;
5751
5752         for_each_tx_queue_cnic(bp, i)
5753                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5754 }
5755 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5756 {
5757         int i;
5758         u8 cos;
5759
5760         for_each_eth_queue(bp, i)
5761                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5762                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5763 }
5764
5765 void bnx2x_nic_init_cnic(struct bnx2x *bp)
5766 {
5767         if (!NO_FCOE(bp))
5768                 bnx2x_init_fcoe_fp(bp);
5769
5770         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5771                       BNX2X_VF_ID_INVALID, false,
5772                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5773
5774         /* ensure status block indices were read */
5775         rmb();
5776         bnx2x_init_rx_rings_cnic(bp);
5777         bnx2x_init_tx_rings_cnic(bp);
5778
5779         /* flush all */
5780         mb();
5781         mmiowb();
5782 }
5783
5784 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5785 {
5786         int i;
5787
5788         for_each_eth_queue(bp, i)
5789                 bnx2x_init_eth_fp(bp, i);
5790         /* Initialize MOD_ABS interrupts */
5791         bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5792                                bp->common.shmem_base, bp->common.shmem2_base,
5793                                BP_PORT(bp));
5794         /* ensure status block indices were read */
5795         rmb();
5796
5797         bnx2x_init_def_sb(bp);
5798         bnx2x_update_dsb_idx(bp);
5799         bnx2x_init_rx_rings(bp);
5800         bnx2x_init_tx_rings(bp);
5801         bnx2x_init_sp_ring(bp);
5802         bnx2x_init_eq_ring(bp);
5803         bnx2x_init_internal(bp, load_code);
5804         bnx2x_pf_init(bp);
5805         bnx2x_stats_init(bp);
5806
5807         /* flush all before enabling interrupts */
5808         mb();
5809         mmiowb();
5810
5811         bnx2x_int_enable(bp);
5812
5813         /* Check for SPIO5 */
5814         bnx2x_attn_int_deasserted0(bp,
5815                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5816                                    AEU_INPUTS_ATTN_BITS_SPIO5);
5817 }
5818
5819 /* end of nic init */
5820
5821 /*
5822  * gzip service functions
5823  */
5824
5825 static int bnx2x_gunzip_init(struct bnx2x *bp)
5826 {
5827         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5828                                             &bp->gunzip_mapping, GFP_KERNEL);
5829         if (bp->gunzip_buf  == NULL)
5830                 goto gunzip_nomem1;
5831
5832         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5833         if (bp->strm  == NULL)
5834                 goto gunzip_nomem2;
5835
5836         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5837         if (bp->strm->workspace == NULL)
5838                 goto gunzip_nomem3;
5839
5840         return 0;
5841
5842 gunzip_nomem3:
5843         kfree(bp->strm);
5844         bp->strm = NULL;
5845
5846 gunzip_nomem2:
5847         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5848                           bp->gunzip_mapping);
5849         bp->gunzip_buf = NULL;
5850
5851 gunzip_nomem1:
5852         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5853         return -ENOMEM;
5854 }
5855
5856 static void bnx2x_gunzip_end(struct bnx2x *bp)
5857 {
5858         if (bp->strm) {
5859                 vfree(bp->strm->workspace);
5860                 kfree(bp->strm);
5861                 bp->strm = NULL;
5862         }
5863
5864         if (bp->gunzip_buf) {
5865                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5866                                   bp->gunzip_mapping);
5867                 bp->gunzip_buf = NULL;
5868         }
5869 }
5870
5871 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5872 {
5873         int n, rc;
5874
5875         /* check gzip header */
5876         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5877                 BNX2X_ERR("Bad gzip header\n");
5878                 return -EINVAL;
5879         }
5880
5881         n = 10;
5882
5883 #define FNAME                           0x8
5884
5885         if (zbuf[3] & FNAME)
5886                 while ((zbuf[n++] != 0) && (n < len));
5887
5888         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5889         bp->strm->avail_in = len - n;
5890         bp->strm->next_out = bp->gunzip_buf;
5891         bp->strm->avail_out = FW_BUF_SIZE;
5892
5893         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5894         if (rc != Z_OK)
5895                 return rc;
5896
5897         rc = zlib_inflate(bp->strm, Z_FINISH);
5898         if ((rc != Z_OK) && (rc != Z_STREAM_END))
5899                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5900                            bp->strm->msg);
5901
5902         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5903         if (bp->gunzip_outlen & 0x3)
5904                 netdev_err(bp->dev,
5905                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5906                                 bp->gunzip_outlen);
5907         bp->gunzip_outlen >>= 2;
5908
5909         zlib_inflateEnd(bp->strm);
5910
5911         if (rc == Z_STREAM_END)
5912                 return 0;
5913
5914         return rc;
5915 }
5916
5917 /* nic load/unload */
5918
5919 /*
5920  * General service functions
5921  */
5922
5923 /* send a NIG loopback debug packet */
5924 static void bnx2x_lb_pckt(struct bnx2x *bp)
5925 {
5926         u32 wb_write[3];
5927
5928         /* Ethernet source and destination addresses */
5929         wb_write[0] = 0x55555555;
5930         wb_write[1] = 0x55555555;
5931         wb_write[2] = 0x20;             /* SOP */
5932         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5933
5934         /* NON-IP protocol */
5935         wb_write[0] = 0x09000000;
5936         wb_write[1] = 0x55555555;
5937         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
5938         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5939 }
5940
5941 /* some of the internal memories
5942  * are not directly readable from the driver
5943  * to test them we send debug packets
5944  */
5945 static int bnx2x_int_mem_test(struct bnx2x *bp)
5946 {
5947         int factor;
5948         int count, i;
5949         u32 val = 0;
5950
5951         if (CHIP_REV_IS_FPGA(bp))
5952                 factor = 120;
5953         else if (CHIP_REV_IS_EMUL(bp))
5954                 factor = 200;
5955         else
5956                 factor = 1;
5957
5958         /* Disable inputs of parser neighbor blocks */
5959         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5960         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5961         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5962         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5963
5964         /*  Write 0 to parser credits for CFC search request */
5965         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5966
5967         /* send Ethernet packet */
5968         bnx2x_lb_pckt(bp);
5969
5970         /* TODO do i reset NIG statistic? */
5971         /* Wait until NIG register shows 1 packet of size 0x10 */
5972         count = 1000 * factor;
5973         while (count) {
5974
5975                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5976                 val = *bnx2x_sp(bp, wb_data[0]);
5977                 if (val == 0x10)
5978                         break;
5979
5980                 msleep(10);
5981                 count--;
5982         }
5983         if (val != 0x10) {
5984                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
5985                 return -1;
5986         }
5987
5988         /* Wait until PRS register shows 1 packet */
5989         count = 1000 * factor;
5990         while (count) {
5991                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5992                 if (val == 1)
5993                         break;
5994
5995                 msleep(10);
5996                 count--;
5997         }
5998         if (val != 0x1) {
5999                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6000                 return -2;
6001         }
6002
6003         /* Reset and init BRB, PRS */
6004         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6005         msleep(50);
6006         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6007         msleep(50);
6008         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6009         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6010
6011         DP(NETIF_MSG_HW, "part2\n");
6012
6013         /* Disable inputs of parser neighbor blocks */
6014         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6015         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6016         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6017         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6018
6019         /* Write 0 to parser credits for CFC search request */
6020         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6021
6022         /* send 10 Ethernet packets */
6023         for (i = 0; i < 10; i++)
6024                 bnx2x_lb_pckt(bp);
6025
6026         /* Wait until NIG register shows 10 + 1
6027            packets of size 11*0x10 = 0xb0 */
6028         count = 1000 * factor;
6029         while (count) {
6030
6031                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6032                 val = *bnx2x_sp(bp, wb_data[0]);
6033                 if (val == 0xb0)
6034                         break;
6035
6036                 msleep(10);
6037                 count--;
6038         }
6039         if (val != 0xb0) {
6040                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6041                 return -3;
6042         }
6043
6044         /* Wait until PRS register shows 2 packets */
6045         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6046         if (val != 2)
6047                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6048
6049         /* Write 1 to parser credits for CFC search request */
6050         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6051
6052         /* Wait until PRS register shows 3 packets */
6053         msleep(10 * factor);
6054         /* Wait until NIG register shows 1 packet of size 0x10 */
6055         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6056         if (val != 3)
6057                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6058
6059         /* clear NIG EOP FIFO */
6060         for (i = 0; i < 11; i++)
6061                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6062         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6063         if (val != 1) {
6064                 BNX2X_ERR("clear of NIG failed\n");
6065                 return -4;
6066         }
6067
6068         /* Reset and init BRB, PRS, NIG */
6069         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6070         msleep(50);
6071         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6072         msleep(50);
6073         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6074         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6075         if (!CNIC_SUPPORT(bp))
6076                 /* set NIC mode */
6077                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6078
6079         /* Enable inputs of parser neighbor blocks */
6080         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6081         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6082         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6083         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6084
6085         DP(NETIF_MSG_HW, "done\n");
6086
6087         return 0; /* OK */
6088 }
6089
6090 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6091 {
6092         u32 val;
6093
6094         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6095         if (!CHIP_IS_E1x(bp))
6096                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6097         else
6098                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6099         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6100         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6101         /*
6102          * mask read length error interrupts in brb for parser
6103          * (parsing unit and 'checksum and crc' unit)
6104          * these errors are legal (PU reads fixed length and CAC can cause
6105          * read length error on truncated packets)
6106          */
6107         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6108         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6109         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6110         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6111         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6112         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6113 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6114 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6115         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6116         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6117         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6118 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6119 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6120         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6121         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6122         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6123         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6124 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6125 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6126
6127         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6128                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6129                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6130         if (!CHIP_IS_E1x(bp))
6131                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6132                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6133         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6134
6135         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6136         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6137         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6138 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6139
6140         if (!CHIP_IS_E1x(bp))
6141                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6142                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6143
6144         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6145         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6146 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6147         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6148 }
6149
6150 static void bnx2x_reset_common(struct bnx2x *bp)
6151 {
6152         u32 val = 0x1400;
6153
6154         /* reset_common */
6155         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6156                0xd3ffff7f);
6157
6158         if (CHIP_IS_E3(bp)) {
6159                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6160                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6161         }
6162
6163         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6164 }
6165
6166 static void bnx2x_setup_dmae(struct bnx2x *bp)
6167 {
6168         bp->dmae_ready = 0;
6169         spin_lock_init(&bp->dmae_lock);
6170 }
6171
6172 static void bnx2x_init_pxp(struct bnx2x *bp)
6173 {
6174         u16 devctl;
6175         int r_order, w_order;
6176
6177         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6178         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6179         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6180         if (bp->mrrs == -1)
6181                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6182         else {
6183                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6184                 r_order = bp->mrrs;
6185         }
6186
6187         bnx2x_init_pxp_arb(bp, r_order, w_order);
6188 }
6189
6190 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6191 {
6192         int is_required;
6193         u32 val;
6194         int port;
6195
6196         if (BP_NOMCP(bp))
6197                 return;
6198
6199         is_required = 0;
6200         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6201               SHARED_HW_CFG_FAN_FAILURE_MASK;
6202
6203         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6204                 is_required = 1;
6205
6206         /*
6207          * The fan failure mechanism is usually related to the PHY type since
6208          * the power consumption of the board is affected by the PHY. Currently,
6209          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6210          */
6211         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6212                 for (port = PORT_0; port < PORT_MAX; port++) {
6213                         is_required |=
6214                                 bnx2x_fan_failure_det_req(
6215                                         bp,
6216                                         bp->common.shmem_base,
6217                                         bp->common.shmem2_base,
6218                                         port);
6219                 }
6220
6221         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6222
6223         if (is_required == 0)
6224                 return;
6225
6226         /* Fan failure is indicated by SPIO 5 */
6227         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6228
6229         /* set to active low mode */
6230         val = REG_RD(bp, MISC_REG_SPIO_INT);
6231         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6232         REG_WR(bp, MISC_REG_SPIO_INT, val);
6233
6234         /* enable interrupt to signal the IGU */
6235         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6236         val |= MISC_SPIO_SPIO5;
6237         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6238 }
6239
6240 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6241 {
6242         u32 offset = 0;
6243
6244         if (CHIP_IS_E1(bp))
6245                 return;
6246         if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6247                 return;
6248
6249         switch (BP_ABS_FUNC(bp)) {
6250         case 0:
6251                 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6252                 break;
6253         case 1:
6254                 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6255                 break;
6256         case 2:
6257                 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6258                 break;
6259         case 3:
6260                 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6261                 break;
6262         case 4:
6263                 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6264                 break;
6265         case 5:
6266                 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6267                 break;
6268         case 6:
6269                 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6270                 break;
6271         case 7:
6272                 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6273                 break;
6274         default:
6275                 return;
6276         }
6277
6278         REG_WR(bp, offset, pretend_func_num);
6279         REG_RD(bp, offset);
6280         DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6281 }
6282
6283 void bnx2x_pf_disable(struct bnx2x *bp)
6284 {
6285         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6286         val &= ~IGU_PF_CONF_FUNC_EN;
6287
6288         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6289         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6290         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6291 }
6292
6293 static void bnx2x__common_init_phy(struct bnx2x *bp)
6294 {
6295         u32 shmem_base[2], shmem2_base[2];
6296         /* Avoid common init in case MFW supports LFA */
6297         if (SHMEM2_RD(bp, size) >
6298             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6299                 return;
6300         shmem_base[0] =  bp->common.shmem_base;
6301         shmem2_base[0] = bp->common.shmem2_base;
6302         if (!CHIP_IS_E1x(bp)) {
6303                 shmem_base[1] =
6304                         SHMEM2_RD(bp, other_shmem_base_addr);
6305                 shmem2_base[1] =
6306                         SHMEM2_RD(bp, other_shmem2_base_addr);
6307         }
6308         bnx2x_acquire_phy_lock(bp);
6309         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6310                               bp->common.chip_id);
6311         bnx2x_release_phy_lock(bp);
6312 }
6313
6314 /**
6315  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6316  *
6317  * @bp:         driver handle
6318  */
6319 static int bnx2x_init_hw_common(struct bnx2x *bp)
6320 {
6321         u32 val;
6322
6323         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6324
6325         /*
6326          * take the UNDI lock to protect undi_unload flow from accessing
6327          * registers while we're resetting the chip
6328          */
6329         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6330
6331         bnx2x_reset_common(bp);
6332         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6333
6334         val = 0xfffc;
6335         if (CHIP_IS_E3(bp)) {
6336                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6337                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6338         }
6339         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6340
6341         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6342
6343         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6344
6345         if (!CHIP_IS_E1x(bp)) {
6346                 u8 abs_func_id;
6347
6348                 /**
6349                  * 4-port mode or 2-port mode we need to turn of master-enable
6350                  * for everyone, after that, turn it back on for self.
6351                  * so, we disregard multi-function or not, and always disable
6352                  * for all functions on the given path, this means 0,2,4,6 for
6353                  * path 0 and 1,3,5,7 for path 1
6354                  */
6355                 for (abs_func_id = BP_PATH(bp);
6356                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6357                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6358                                 REG_WR(bp,
6359                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6360                                     1);
6361                                 continue;
6362                         }
6363
6364                         bnx2x_pretend_func(bp, abs_func_id);
6365                         /* clear pf enable */
6366                         bnx2x_pf_disable(bp);
6367                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6368                 }
6369         }
6370
6371         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6372         if (CHIP_IS_E1(bp)) {
6373                 /* enable HW interrupt from PXP on USDM overflow
6374                    bit 16 on INT_MASK_0 */
6375                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6376         }
6377
6378         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6379         bnx2x_init_pxp(bp);
6380
6381 #ifdef __BIG_ENDIAN
6382         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6383         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6384         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6385         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6386         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6387         /* make sure this value is 0 */
6388         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6389
6390 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6391         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6392         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6393         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6394         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6395 #endif
6396
6397         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6398
6399         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6400                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6401
6402         /* let the HW do it's magic ... */
6403         msleep(100);
6404         /* finish PXP init */
6405         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6406         if (val != 1) {
6407                 BNX2X_ERR("PXP2 CFG failed\n");
6408                 return -EBUSY;
6409         }
6410         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6411         if (val != 1) {
6412                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6413                 return -EBUSY;
6414         }
6415
6416         /* Timers bug workaround E2 only. We need to set the entire ILT to
6417          * have entries with value "0" and valid bit on.
6418          * This needs to be done by the first PF that is loaded in a path
6419          * (i.e. common phase)
6420          */
6421         if (!CHIP_IS_E1x(bp)) {
6422 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6423  * (i.e. vnic3) to start even if it is marked as "scan-off".
6424  * This occurs when a different function (func2,3) is being marked
6425  * as "scan-off". Real-life scenario for example: if a driver is being
6426  * load-unloaded while func6,7 are down. This will cause the timer to access
6427  * the ilt, translate to a logical address and send a request to read/write.
6428  * Since the ilt for the function that is down is not valid, this will cause
6429  * a translation error which is unrecoverable.
6430  * The Workaround is intended to make sure that when this happens nothing fatal
6431  * will occur. The workaround:
6432  *      1.  First PF driver which loads on a path will:
6433  *              a.  After taking the chip out of reset, by using pretend,
6434  *                  it will write "0" to the following registers of
6435  *                  the other vnics.
6436  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6437  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6438  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6439  *                  And for itself it will write '1' to
6440  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6441  *                  dmae-operations (writing to pram for example.)
6442  *                  note: can be done for only function 6,7 but cleaner this
6443  *                        way.
6444  *              b.  Write zero+valid to the entire ILT.
6445  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6446  *                  VNIC3 (of that port). The range allocated will be the
6447  *                  entire ILT. This is needed to prevent  ILT range error.
6448  *      2.  Any PF driver load flow:
6449  *              a.  ILT update with the physical addresses of the allocated
6450  *                  logical pages.
6451  *              b.  Wait 20msec. - note that this timeout is needed to make
6452  *                  sure there are no requests in one of the PXP internal
6453  *                  queues with "old" ILT addresses.
6454  *              c.  PF enable in the PGLC.
6455  *              d.  Clear the was_error of the PF in the PGLC. (could have
6456  *                  occured while driver was down)
6457  *              e.  PF enable in the CFC (WEAK + STRONG)
6458  *              f.  Timers scan enable
6459  *      3.  PF driver unload flow:
6460  *              a.  Clear the Timers scan_en.
6461  *              b.  Polling for scan_on=0 for that PF.
6462  *              c.  Clear the PF enable bit in the PXP.
6463  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6464  *              e.  Write zero+valid to all ILT entries (The valid bit must
6465  *                  stay set)
6466  *              f.  If this is VNIC 3 of a port then also init
6467  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6468  *                  to the last enrty in the ILT.
6469  *
6470  *      Notes:
6471  *      Currently the PF error in the PGLC is non recoverable.
6472  *      In the future the there will be a recovery routine for this error.
6473  *      Currently attention is masked.
6474  *      Having an MCP lock on the load/unload process does not guarantee that
6475  *      there is no Timer disable during Func6/7 enable. This is because the
6476  *      Timers scan is currently being cleared by the MCP on FLR.
6477  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6478  *      there is error before clearing it. But the flow above is simpler and
6479  *      more general.
6480  *      All ILT entries are written by zero+valid and not just PF6/7
6481  *      ILT entries since in the future the ILT entries allocation for
6482  *      PF-s might be dynamic.
6483  */
6484                 struct ilt_client_info ilt_cli;
6485                 struct bnx2x_ilt ilt;
6486                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6487                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6488
6489                 /* initialize dummy TM client */
6490                 ilt_cli.start = 0;
6491                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6492                 ilt_cli.client_num = ILT_CLIENT_TM;
6493
6494                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6495                  * Step 2: set the timers first/last ilt entry to point
6496                  * to the entire range to prevent ILT range error for 3rd/4th
6497                  * vnic (this code assumes existance of the vnic)
6498                  *
6499                  * both steps performed by call to bnx2x_ilt_client_init_op()
6500                  * with dummy TM client
6501                  *
6502                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6503                  * and his brother are split registers
6504                  */
6505                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6506                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6507                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6508
6509                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6510                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6511                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6512         }
6513
6514
6515         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6516         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6517
6518         if (!CHIP_IS_E1x(bp)) {
6519                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6520                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6521                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6522
6523                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6524
6525                 /* let the HW do it's magic ... */
6526                 do {
6527                         msleep(200);
6528                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6529                 } while (factor-- && (val != 1));
6530
6531                 if (val != 1) {
6532                         BNX2X_ERR("ATC_INIT failed\n");
6533                         return -EBUSY;
6534                 }
6535         }
6536
6537         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6538
6539         /* clean the DMAE memory */
6540         bp->dmae_ready = 1;
6541         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6542
6543         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6544
6545         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6546
6547         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6548
6549         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6550
6551         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6552         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6553         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6554         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6555
6556         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6557
6558
6559         /* QM queues pointers table */
6560         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6561
6562         /* soft reset pulse */
6563         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6564         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6565
6566         if (CNIC_SUPPORT(bp))
6567                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6568
6569         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6570         REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6571         if (!CHIP_REV_IS_SLOW(bp))
6572                 /* enable hw interrupt from doorbell Q */
6573                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6574
6575         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6576
6577         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6578         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6579
6580         if (!CHIP_IS_E1(bp))
6581                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6582
6583         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6584                 if (IS_MF_AFEX(bp)) {
6585                         /* configure that VNTag and VLAN headers must be
6586                          * received in afex mode
6587                          */
6588                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6589                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6590                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6591                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6592                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6593                 } else {
6594                         /* Bit-map indicating which L2 hdrs may appear
6595                          * after the basic Ethernet header
6596                          */
6597                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6598                                bp->path_has_ovlan ? 7 : 6);
6599                 }
6600         }
6601
6602         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6603         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6604         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6605         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6606
6607         if (!CHIP_IS_E1x(bp)) {
6608                 /* reset VFC memories */
6609                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6610                            VFC_MEMORIES_RST_REG_CAM_RST |
6611                            VFC_MEMORIES_RST_REG_RAM_RST);
6612                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6613                            VFC_MEMORIES_RST_REG_CAM_RST |
6614                            VFC_MEMORIES_RST_REG_RAM_RST);
6615
6616                 msleep(20);
6617         }
6618
6619         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6620         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6621         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6622         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6623
6624         /* sync semi rtc */
6625         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6626                0x80000000);
6627         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6628                0x80000000);
6629
6630         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6631         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6632         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6633
6634         if (!CHIP_IS_E1x(bp)) {
6635                 if (IS_MF_AFEX(bp)) {
6636                         /* configure that VNTag and VLAN headers must be
6637                          * sent in afex mode
6638                          */
6639                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6640                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6641                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6642                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6643                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6644                 } else {
6645                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6646                                bp->path_has_ovlan ? 7 : 6);
6647                 }
6648         }
6649
6650         REG_WR(bp, SRC_REG_SOFT_RST, 1);
6651
6652         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6653
6654         if (CNIC_SUPPORT(bp)) {
6655                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6656                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6657                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6658                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6659                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6660                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6661                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6662                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6663                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6664                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6665         }
6666         REG_WR(bp, SRC_REG_SOFT_RST, 0);
6667
6668         if (sizeof(union cdu_context) != 1024)
6669                 /* we currently assume that a context is 1024 bytes */
6670                 dev_alert(&bp->pdev->dev,
6671                           "please adjust the size of cdu_context(%ld)\n",
6672                           (long)sizeof(union cdu_context));
6673
6674         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6675         val = (4 << 24) + (0 << 12) + 1024;
6676         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6677
6678         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6679         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6680         /* enable context validation interrupt from CFC */
6681         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6682
6683         /* set the thresholds to prevent CFC/CDU race */
6684         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6685
6686         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6687
6688         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6689                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6690
6691         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6692         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6693
6694         /* Reset PCIE errors for debug */
6695         REG_WR(bp, 0x2814, 0xffffffff);
6696         REG_WR(bp, 0x3820, 0xffffffff);
6697
6698         if (!CHIP_IS_E1x(bp)) {
6699                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6700                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6701                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6702                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6703                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6704                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6705                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6706                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6707                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6708                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6709                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6710         }
6711
6712         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6713         if (!CHIP_IS_E1(bp)) {
6714                 /* in E3 this done in per-port section */
6715                 if (!CHIP_IS_E3(bp))
6716                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6717         }
6718         if (CHIP_IS_E1H(bp))
6719                 /* not applicable for E2 (and above ...) */
6720                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6721
6722         if (CHIP_REV_IS_SLOW(bp))
6723                 msleep(200);
6724
6725         /* finish CFC init */
6726         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6727         if (val != 1) {
6728                 BNX2X_ERR("CFC LL_INIT failed\n");
6729                 return -EBUSY;
6730         }
6731         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6732         if (val != 1) {
6733                 BNX2X_ERR("CFC AC_INIT failed\n");
6734                 return -EBUSY;
6735         }
6736         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6737         if (val != 1) {
6738                 BNX2X_ERR("CFC CAM_INIT failed\n");
6739                 return -EBUSY;
6740         }
6741         REG_WR(bp, CFC_REG_DEBUG0, 0);
6742
6743         if (CHIP_IS_E1(bp)) {
6744                 /* read NIG statistic
6745                    to see if this is our first up since powerup */
6746                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6747                 val = *bnx2x_sp(bp, wb_data[0]);
6748
6749                 /* do internal memory self test */
6750                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6751                         BNX2X_ERR("internal mem self test failed\n");
6752                         return -EBUSY;
6753                 }
6754         }
6755
6756         bnx2x_setup_fan_failure_detection(bp);
6757
6758         /* clear PXP2 attentions */
6759         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6760
6761         bnx2x_enable_blocks_attention(bp);
6762         bnx2x_enable_blocks_parity(bp);
6763
6764         if (!BP_NOMCP(bp)) {
6765                 if (CHIP_IS_E1x(bp))
6766                         bnx2x__common_init_phy(bp);
6767         } else
6768                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6769
6770         return 0;
6771 }
6772
6773 /**
6774  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6775  *
6776  * @bp:         driver handle
6777  */
6778 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6779 {
6780         int rc = bnx2x_init_hw_common(bp);
6781
6782         if (rc)
6783                 return rc;
6784
6785         /* In E2 2-PORT mode, same ext phy is used for the two paths */
6786         if (!BP_NOMCP(bp))
6787                 bnx2x__common_init_phy(bp);
6788
6789         return 0;
6790 }
6791
6792 static int bnx2x_init_hw_port(struct bnx2x *bp)
6793 {
6794         int port = BP_PORT(bp);
6795         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6796         u32 low, high;
6797         u32 val;
6798
6799
6800         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
6801
6802         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6803
6804         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6805         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6806         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6807
6808         /* Timers bug workaround: disables the pf_master bit in pglue at
6809          * common phase, we need to enable it here before any dmae access are
6810          * attempted. Therefore we manually added the enable-master to the
6811          * port phase (it also happens in the function phase)
6812          */
6813         if (!CHIP_IS_E1x(bp))
6814                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6815
6816         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6817         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6818         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6819         bnx2x_init_block(bp, BLOCK_QM, init_phase);
6820
6821         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6822         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6823         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6824         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6825
6826         /* QM cid (connection) count */
6827         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6828
6829         if (CNIC_SUPPORT(bp)) {
6830                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6831                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6832                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6833         }
6834
6835         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6836
6837         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6838
6839         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6840
6841                 if (IS_MF(bp))
6842                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6843                 else if (bp->dev->mtu > 4096) {
6844                         if (bp->flags & ONE_PORT_FLAG)
6845                                 low = 160;
6846                         else {
6847                                 val = bp->dev->mtu;
6848                                 /* (24*1024 + val*4)/256 */
6849                                 low = 96 + (val/64) +
6850                                                 ((val % 64) ? 1 : 0);
6851                         }
6852                 } else
6853                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6854                 high = low + 56;        /* 14*1024/256 */
6855                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6856                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6857         }
6858
6859         if (CHIP_MODE_IS_4_PORT(bp))
6860                 REG_WR(bp, (BP_PORT(bp) ?
6861                             BRB1_REG_MAC_GUARANTIED_1 :
6862                             BRB1_REG_MAC_GUARANTIED_0), 40);
6863
6864
6865         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6866         if (CHIP_IS_E3B0(bp)) {
6867                 if (IS_MF_AFEX(bp)) {
6868                         /* configure headers for AFEX mode */
6869                         REG_WR(bp, BP_PORT(bp) ?
6870                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6871                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6872                         REG_WR(bp, BP_PORT(bp) ?
6873                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6874                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6875                         REG_WR(bp, BP_PORT(bp) ?
6876                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6877                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6878                 } else {
6879                         /* Ovlan exists only if we are in multi-function +
6880                          * switch-dependent mode, in switch-independent there
6881                          * is no ovlan headers
6882                          */
6883                         REG_WR(bp, BP_PORT(bp) ?
6884                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6885                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6886                                (bp->path_has_ovlan ? 7 : 6));
6887                 }
6888         }
6889
6890         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6891         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6892         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6893         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6894
6895         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6896         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6897         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6898         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6899
6900         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6901         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6902
6903         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6904
6905         if (CHIP_IS_E1x(bp)) {
6906                 /* configure PBF to work without PAUSE mtu 9000 */
6907                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6908
6909                 /* update threshold */
6910                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6911                 /* update init credit */
6912                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6913
6914                 /* probe changes */
6915                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6916                 udelay(50);
6917                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6918         }
6919
6920         if (CNIC_SUPPORT(bp))
6921                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6922
6923         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6924         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6925
6926         if (CHIP_IS_E1(bp)) {
6927                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6928                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6929         }
6930         bnx2x_init_block(bp, BLOCK_HC, init_phase);
6931
6932         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6933
6934         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6935         /* init aeu_mask_attn_func_0/1:
6936          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6937          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6938          *             bits 4-7 are used for "per vn group attention" */
6939         val = IS_MF(bp) ? 0xF7 : 0x7;
6940         /* Enable DCBX attention for all but E1 */
6941         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6942         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6943
6944         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6945
6946         if (!CHIP_IS_E1x(bp)) {
6947                 /* Bit-map indicating which L2 hdrs may appear after the
6948                  * basic Ethernet header
6949                  */
6950                 if (IS_MF_AFEX(bp))
6951                         REG_WR(bp, BP_PORT(bp) ?
6952                                NIG_REG_P1_HDRS_AFTER_BASIC :
6953                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6954                 else
6955                         REG_WR(bp, BP_PORT(bp) ?
6956                                NIG_REG_P1_HDRS_AFTER_BASIC :
6957                                NIG_REG_P0_HDRS_AFTER_BASIC,
6958                                IS_MF_SD(bp) ? 7 : 6);
6959
6960                 if (CHIP_IS_E3(bp))
6961                         REG_WR(bp, BP_PORT(bp) ?
6962                                    NIG_REG_LLH1_MF_MODE :
6963                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
6964         }
6965         if (!CHIP_IS_E3(bp))
6966                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6967
6968         if (!CHIP_IS_E1(bp)) {
6969                 /* 0x2 disable mf_ov, 0x1 enable */
6970                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6971                        (IS_MF_SD(bp) ? 0x1 : 0x2));
6972
6973                 if (!CHIP_IS_E1x(bp)) {
6974                         val = 0;
6975                         switch (bp->mf_mode) {
6976                         case MULTI_FUNCTION_SD:
6977                                 val = 1;
6978                                 break;
6979                         case MULTI_FUNCTION_SI:
6980                         case MULTI_FUNCTION_AFEX:
6981                                 val = 2;
6982                                 break;
6983                         }
6984
6985                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6986                                                   NIG_REG_LLH0_CLS_TYPE), val);
6987                 }
6988                 {
6989                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6990                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6991                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6992                 }
6993         }
6994
6995
6996         /* If SPIO5 is set to generate interrupts, enable it for this port */
6997         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6998         if (val & MISC_SPIO_SPIO5) {
6999                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7000                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7001                 val = REG_RD(bp, reg_addr);
7002                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7003                 REG_WR(bp, reg_addr, val);
7004         }
7005
7006         return 0;
7007 }
7008
7009 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7010 {
7011         int reg;
7012         u32 wb_write[2];
7013
7014         if (CHIP_IS_E1(bp))
7015                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7016         else
7017                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7018
7019         wb_write[0] = ONCHIP_ADDR1(addr);
7020         wb_write[1] = ONCHIP_ADDR2(addr);
7021         REG_WR_DMAE(bp, reg, wb_write, 2);
7022 }
7023
7024 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
7025                                    u8 idu_sb_id, bool is_Pf)
7026 {
7027         u32 data, ctl, cnt = 100;
7028         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7029         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7030         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7031         u32 sb_bit =  1 << (idu_sb_id%32);
7032         u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7033         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7034
7035         /* Not supported in BC mode */
7036         if (CHIP_INT_MODE_IS_BC(bp))
7037                 return;
7038
7039         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7040                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7041                 IGU_REGULAR_CLEANUP_SET                         |
7042                 IGU_REGULAR_BCLEANUP;
7043
7044         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7045               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7046               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7047
7048         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7049                          data, igu_addr_data);
7050         REG_WR(bp, igu_addr_data, data);
7051         mmiowb();
7052         barrier();
7053         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7054                           ctl, igu_addr_ctl);
7055         REG_WR(bp, igu_addr_ctl, ctl);
7056         mmiowb();
7057         barrier();
7058
7059         /* wait for clean up to finish */
7060         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7061                 msleep(20);
7062
7063
7064         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7065                 DP(NETIF_MSG_HW,
7066                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7067                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7068         }
7069 }
7070
7071 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7072 {
7073         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7074 }
7075
7076 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7077 {
7078         u32 i, base = FUNC_ILT_BASE(func);
7079         for (i = base; i < base + ILT_PER_FUNC; i++)
7080                 bnx2x_ilt_wr(bp, i, 0);
7081 }
7082
7083
7084 static void bnx2x_init_searcher(struct bnx2x *bp)
7085 {
7086         int port = BP_PORT(bp);
7087         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7088         /* T1 hash bits value determines the T1 number of entries */
7089         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7090 }
7091
7092 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7093 {
7094         int rc;
7095         struct bnx2x_func_state_params func_params = {NULL};
7096         struct bnx2x_func_switch_update_params *switch_update_params =
7097                 &func_params.params.switch_update;
7098
7099         /* Prepare parameters for function state transitions */
7100         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7101         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7102
7103         func_params.f_obj = &bp->func_obj;
7104         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7105
7106         /* Function parameters */
7107         switch_update_params->suspend = suspend;
7108
7109         rc = bnx2x_func_state_change(bp, &func_params);
7110
7111         return rc;
7112 }
7113
7114 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7115 {
7116         int rc, i, port = BP_PORT(bp);
7117         int vlan_en = 0, mac_en[NUM_MACS];
7118
7119
7120         /* Close input from network */
7121         if (bp->mf_mode == SINGLE_FUNCTION) {
7122                 bnx2x_set_rx_filter(&bp->link_params, 0);
7123         } else {
7124                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7125                                    NIG_REG_LLH0_FUNC_EN);
7126                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7127                           NIG_REG_LLH0_FUNC_EN, 0);
7128                 for (i = 0; i < NUM_MACS; i++) {
7129                         mac_en[i] = REG_RD(bp, port ?
7130                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7131                                               4 * i) :
7132                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7133                                               4 * i));
7134                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7135                                               4 * i) :
7136                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7137                 }
7138         }
7139
7140         /* Close BMC to host */
7141         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7142                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7143
7144         /* Suspend Tx switching to the PF. Completion of this ramrod
7145          * further guarantees that all the packets of that PF / child
7146          * VFs in BRB were processed by the Parser, so it is safe to
7147          * change the NIC_MODE register.
7148          */
7149         rc = bnx2x_func_switch_update(bp, 1);
7150         if (rc) {
7151                 BNX2X_ERR("Can't suspend tx-switching!\n");
7152                 return rc;
7153         }
7154
7155         /* Change NIC_MODE register */
7156         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7157
7158         /* Open input from network */
7159         if (bp->mf_mode == SINGLE_FUNCTION) {
7160                 bnx2x_set_rx_filter(&bp->link_params, 1);
7161         } else {
7162                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7163                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7164                 for (i = 0; i < NUM_MACS; i++) {
7165                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7166                                               4 * i) :
7167                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7168                                   mac_en[i]);
7169                 }
7170         }
7171
7172         /* Enable BMC to host */
7173         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7174                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7175
7176         /* Resume Tx switching to the PF */
7177         rc = bnx2x_func_switch_update(bp, 0);
7178         if (rc) {
7179                 BNX2X_ERR("Can't resume tx-switching!\n");
7180                 return rc;
7181         }
7182
7183         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7184         return 0;
7185 }
7186
7187 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7188 {
7189         int rc;
7190
7191         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7192
7193         if (CONFIGURE_NIC_MODE(bp)) {
7194                 /* Configrue searcher as part of function hw init */
7195                 bnx2x_init_searcher(bp);
7196
7197                 /* Reset NIC mode */
7198                 rc = bnx2x_reset_nic_mode(bp);
7199                 if (rc)
7200                         BNX2X_ERR("Can't change NIC mode!\n");
7201                 return rc;
7202         }
7203
7204         return 0;
7205 }
7206
7207 static int bnx2x_init_hw_func(struct bnx2x *bp)
7208 {
7209         int port = BP_PORT(bp);
7210         int func = BP_FUNC(bp);
7211         int init_phase = PHASE_PF0 + func;
7212         struct bnx2x_ilt *ilt = BP_ILT(bp);
7213         u16 cdu_ilt_start;
7214         u32 addr, val;
7215         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7216         int i, main_mem_width, rc;
7217
7218         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7219
7220         /* FLR cleanup - hmmm */
7221         if (!CHIP_IS_E1x(bp)) {
7222                 rc = bnx2x_pf_flr_clnup(bp);
7223                 if (rc)
7224                         return rc;
7225         }
7226
7227         /* set MSI reconfigure capability */
7228         if (bp->common.int_block == INT_BLOCK_HC) {
7229                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7230                 val = REG_RD(bp, addr);
7231                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7232                 REG_WR(bp, addr, val);
7233         }
7234
7235         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7236         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7237
7238         ilt = BP_ILT(bp);
7239         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7240
7241         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7242                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7243                 ilt->lines[cdu_ilt_start + i].page_mapping =
7244                         bp->context[i].cxt_mapping;
7245                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7246         }
7247         bnx2x_ilt_init_op(bp, INITOP_SET);
7248
7249         if (!CONFIGURE_NIC_MODE(bp)) {
7250                 bnx2x_init_searcher(bp);
7251                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7252                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7253         } else {
7254                 /* Set NIC mode */
7255                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7256                 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7257
7258         }
7259
7260         if (!CHIP_IS_E1x(bp)) {
7261                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7262
7263                 /* Turn on a single ISR mode in IGU if driver is going to use
7264                  * INT#x or MSI
7265                  */
7266                 if (!(bp->flags & USING_MSIX_FLAG))
7267                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7268                 /*
7269                  * Timers workaround bug: function init part.
7270                  * Need to wait 20msec after initializing ILT,
7271                  * needed to make sure there are no requests in
7272                  * one of the PXP internal queues with "old" ILT addresses
7273                  */
7274                 msleep(20);
7275                 /*
7276                  * Master enable - Due to WB DMAE writes performed before this
7277                  * register is re-initialized as part of the regular function
7278                  * init
7279                  */
7280                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7281                 /* Enable the function in IGU */
7282                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7283         }
7284
7285         bp->dmae_ready = 1;
7286
7287         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7288
7289         if (!CHIP_IS_E1x(bp))
7290                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7291
7292         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7293         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7294         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7295         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7296         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7297         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7298         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7299         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7300         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7301         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7302         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7303         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7304         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7305
7306         if (!CHIP_IS_E1x(bp))
7307                 REG_WR(bp, QM_REG_PF_EN, 1);
7308
7309         if (!CHIP_IS_E1x(bp)) {
7310                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7311                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7312                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7313                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7314         }
7315         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7316
7317         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7318         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7319         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7320         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7321         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7322         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7323         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7324         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7325         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7326         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7327         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7328         if (!CHIP_IS_E1x(bp))
7329                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7330
7331         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7332
7333         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7334
7335         if (!CHIP_IS_E1x(bp))
7336                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7337
7338         if (IS_MF(bp)) {
7339                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7340                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7341         }
7342
7343         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7344
7345         /* HC init per function */
7346         if (bp->common.int_block == INT_BLOCK_HC) {
7347                 if (CHIP_IS_E1H(bp)) {
7348                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7349
7350                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7351                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7352                 }
7353                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7354
7355         } else {
7356                 int num_segs, sb_idx, prod_offset;
7357
7358                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7359
7360                 if (!CHIP_IS_E1x(bp)) {
7361                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7362                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7363                 }
7364
7365                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7366
7367                 if (!CHIP_IS_E1x(bp)) {
7368                         int dsb_idx = 0;
7369                         /**
7370                          * Producer memory:
7371                          * E2 mode: address 0-135 match to the mapping memory;
7372                          * 136 - PF0 default prod; 137 - PF1 default prod;
7373                          * 138 - PF2 default prod; 139 - PF3 default prod;
7374                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7375                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7376                          * 144-147 reserved.
7377                          *
7378                          * E1.5 mode - In backward compatible mode;
7379                          * for non default SB; each even line in the memory
7380                          * holds the U producer and each odd line hold
7381                          * the C producer. The first 128 producers are for
7382                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7383                          * producers are for the DSB for each PF.
7384                          * Each PF has five segments: (the order inside each
7385                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7386                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7387                          * 144-147 attn prods;
7388                          */
7389                         /* non-default-status-blocks */
7390                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7391                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7392                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7393                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7394                                         num_segs;
7395
7396                                 for (i = 0; i < num_segs; i++) {
7397                                         addr = IGU_REG_PROD_CONS_MEMORY +
7398                                                         (prod_offset + i) * 4;
7399                                         REG_WR(bp, addr, 0);
7400                                 }
7401                                 /* send consumer update with value 0 */
7402                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7403                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7404                                 bnx2x_igu_clear_sb(bp,
7405                                                    bp->igu_base_sb + sb_idx);
7406                         }
7407
7408                         /* default-status-blocks */
7409                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7410                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7411
7412                         if (CHIP_MODE_IS_4_PORT(bp))
7413                                 dsb_idx = BP_FUNC(bp);
7414                         else
7415                                 dsb_idx = BP_VN(bp);
7416
7417                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7418                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7419                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7420
7421                         /*
7422                          * igu prods come in chunks of E1HVN_MAX (4) -
7423                          * does not matters what is the current chip mode
7424                          */
7425                         for (i = 0; i < (num_segs * E1HVN_MAX);
7426                              i += E1HVN_MAX) {
7427                                 addr = IGU_REG_PROD_CONS_MEMORY +
7428                                                         (prod_offset + i)*4;
7429                                 REG_WR(bp, addr, 0);
7430                         }
7431                         /* send consumer update with 0 */
7432                         if (CHIP_INT_MODE_IS_BC(bp)) {
7433                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7434                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7435                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7436                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7437                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7438                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7439                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7440                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7441                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7442                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7443                         } else {
7444                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7445                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7446                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7447                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7448                         }
7449                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7450
7451                         /* !!! these should become driver const once
7452                            rf-tool supports split-68 const */
7453                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7454                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7455                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7456                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7457                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7458                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7459                 }
7460         }
7461
7462         /* Reset PCIE errors for debug */
7463         REG_WR(bp, 0x2114, 0xffffffff);
7464         REG_WR(bp, 0x2120, 0xffffffff);
7465
7466         if (CHIP_IS_E1x(bp)) {
7467                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7468                 main_mem_base = HC_REG_MAIN_MEMORY +
7469                                 BP_PORT(bp) * (main_mem_size * 4);
7470                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7471                 main_mem_width = 8;
7472
7473                 val = REG_RD(bp, main_mem_prty_clr);
7474                 if (val)
7475                         DP(NETIF_MSG_HW,
7476                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7477                            val);
7478
7479                 /* Clear "false" parity errors in MSI-X table */
7480                 for (i = main_mem_base;
7481                      i < main_mem_base + main_mem_size * 4;
7482                      i += main_mem_width) {
7483                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7484                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7485                                          i, main_mem_width / 4);
7486                 }
7487                 /* Clear HC parity attention */
7488                 REG_RD(bp, main_mem_prty_clr);
7489         }
7490
7491 #ifdef BNX2X_STOP_ON_ERROR
7492         /* Enable STORMs SP logging */
7493         REG_WR8(bp, BAR_USTRORM_INTMEM +
7494                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7495         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7496                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7497         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7498                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7499         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7500                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7501 #endif
7502
7503         bnx2x_phy_probe(&bp->link_params);
7504
7505         return 0;
7506 }
7507
7508
7509 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7510 {
7511         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7512
7513         if (!CHIP_IS_E1x(bp))
7514                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7515                                sizeof(struct host_hc_status_block_e2));
7516         else
7517                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7518                                sizeof(struct host_hc_status_block_e1x));
7519
7520         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7521 }
7522
7523 void bnx2x_free_mem(struct bnx2x *bp)
7524 {
7525         int i;
7526
7527         /* fastpath */
7528         bnx2x_free_fp_mem(bp);
7529         /* end of fastpath */
7530
7531         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7532                        sizeof(struct host_sp_status_block));
7533
7534         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7535                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7536
7537         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7538                        sizeof(struct bnx2x_slowpath));
7539
7540         for (i = 0; i < L2_ILT_LINES(bp); i++)
7541                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7542                                bp->context[i].size);
7543         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7544
7545         BNX2X_FREE(bp->ilt->lines);
7546
7547         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7548
7549         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7550                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7551 }
7552
7553 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7554 {
7555         int num_groups;
7556         int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7557
7558         /* number of queues for statistics is number of eth queues + FCoE */
7559         u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7560
7561         /* Total number of FW statistics requests =
7562          * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7563          * num of queues
7564          */
7565         bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7566
7567
7568         /* Request is built from stats_query_header and an array of
7569          * stats_query_cmd_group each of which contains
7570          * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7571          * configured in the stats_query_header.
7572          */
7573         num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7574                      (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7575
7576         bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7577                         num_groups * sizeof(struct stats_query_cmd_group);
7578
7579         /* Data for statistics requests + stats_conter
7580          *
7581          * stats_counter holds per-STORM counters that are incremented
7582          * when STORM has finished with the current request.
7583          *
7584          * memory for FCoE offloaded statistics are counted anyway,
7585          * even if they will not be sent.
7586          */
7587         bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7588                 sizeof(struct per_pf_stats) +
7589                 sizeof(struct fcoe_statistics_params) +
7590                 sizeof(struct per_queue_stats) * num_queue_stats +
7591                 sizeof(struct stats_counter);
7592
7593         BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7594                         bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7595
7596         /* Set shortcuts */
7597         bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7598         bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7599
7600         bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7601                 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7602
7603         bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7604                                    bp->fw_stats_req_sz;
7605         return 0;
7606
7607 alloc_mem_err:
7608         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7609                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7610         BNX2X_ERR("Can't allocate memory\n");
7611         return -ENOMEM;
7612 }
7613
7614 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7615 {
7616         if (!CHIP_IS_E1x(bp))
7617                 /* size = the status block + ramrod buffers */
7618                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7619                                 sizeof(struct host_hc_status_block_e2));
7620         else
7621                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7622                                 &bp->cnic_sb_mapping,
7623                                 sizeof(struct
7624                                        host_hc_status_block_e1x));
7625
7626         if (CONFIGURE_NIC_MODE(bp))
7627                 /* allocate searcher T2 table, as it wan't allocated before */
7628                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7629
7630         /* write address to which L5 should insert its values */
7631         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7632                 &bp->slowpath->drv_info_to_mcp;
7633
7634         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7635                 goto alloc_mem_err;
7636
7637         return 0;
7638
7639 alloc_mem_err:
7640         bnx2x_free_mem_cnic(bp);
7641         BNX2X_ERR("Can't allocate memory\n");
7642         return -ENOMEM;
7643 }
7644
7645 int bnx2x_alloc_mem(struct bnx2x *bp)
7646 {
7647         int i, allocated, context_size;
7648
7649         if (!CONFIGURE_NIC_MODE(bp))
7650                 /* allocate searcher T2 table */
7651                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7652
7653         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7654                         sizeof(struct host_sp_status_block));
7655
7656         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7657                         sizeof(struct bnx2x_slowpath));
7658
7659         /* Allocated memory for FW statistics  */
7660         if (bnx2x_alloc_fw_stats_mem(bp))
7661                 goto alloc_mem_err;
7662
7663         /* Allocate memory for CDU context:
7664          * This memory is allocated separately and not in the generic ILT
7665          * functions because CDU differs in few aspects:
7666          * 1. There are multiple entities allocating memory for context -
7667          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7668          * its own ILT lines.
7669          * 2. Since CDU page-size is not a single 4KB page (which is the case
7670          * for the other ILT clients), to be efficient we want to support
7671          * allocation of sub-page-size in the last entry.
7672          * 3. Context pointers are used by the driver to pass to FW / update
7673          * the context (for the other ILT clients the pointers are used just to
7674          * free the memory during unload).
7675          */
7676         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7677
7678         for (i = 0, allocated = 0; allocated < context_size; i++) {
7679                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7680                                           (context_size - allocated));
7681                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7682                                 &bp->context[i].cxt_mapping,
7683                                 bp->context[i].size);
7684                 allocated += bp->context[i].size;
7685         }
7686         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7687
7688         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7689                 goto alloc_mem_err;
7690
7691         /* Slow path ring */
7692         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7693
7694         /* EQ */
7695         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7696                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
7697
7698
7699         /* fastpath */
7700         /* need to be done at the end, since it's self adjusting to amount
7701          * of memory available for RSS queues
7702          */
7703         if (bnx2x_alloc_fp_mem(bp))
7704                 goto alloc_mem_err;
7705         return 0;
7706
7707 alloc_mem_err:
7708         bnx2x_free_mem(bp);
7709         BNX2X_ERR("Can't allocate memory\n");
7710         return -ENOMEM;
7711 }
7712
7713 /*
7714  * Init service functions
7715  */
7716
7717 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7718                       struct bnx2x_vlan_mac_obj *obj, bool set,
7719                       int mac_type, unsigned long *ramrod_flags)
7720 {
7721         int rc;
7722         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7723
7724         memset(&ramrod_param, 0, sizeof(ramrod_param));
7725
7726         /* Fill general parameters */
7727         ramrod_param.vlan_mac_obj = obj;
7728         ramrod_param.ramrod_flags = *ramrod_flags;
7729
7730         /* Fill a user request section if needed */
7731         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7732                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7733
7734                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7735
7736                 /* Set the command: ADD or DEL */
7737                 if (set)
7738                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7739                 else
7740                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7741         }
7742
7743         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7744
7745         if (rc == -EEXIST) {
7746                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7747                 /* do not treat adding same MAC as error */
7748                 rc = 0;
7749         } else if (rc < 0)
7750                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7751
7752         return rc;
7753 }
7754
7755 int bnx2x_del_all_macs(struct bnx2x *bp,
7756                        struct bnx2x_vlan_mac_obj *mac_obj,
7757                        int mac_type, bool wait_for_comp)
7758 {
7759         int rc;
7760         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7761
7762         /* Wait for completion of requested */
7763         if (wait_for_comp)
7764                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7765
7766         /* Set the mac type of addresses we want to clear */
7767         __set_bit(mac_type, &vlan_mac_flags);
7768
7769         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7770         if (rc < 0)
7771                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7772
7773         return rc;
7774 }
7775
7776 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7777 {
7778         unsigned long ramrod_flags = 0;
7779
7780         if (is_zero_ether_addr(bp->dev->dev_addr) &&
7781             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7782                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7783                    "Ignoring Zero MAC for STORAGE SD mode\n");
7784                 return 0;
7785         }
7786
7787         DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7788
7789         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7790         /* Eth MAC is set on RSS leading client (fp[0]) */
7791         return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7792                                  set, BNX2X_ETH_MAC, &ramrod_flags);
7793 }
7794
7795 int bnx2x_setup_leading(struct bnx2x *bp)
7796 {
7797         return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7798 }
7799
7800 /**
7801  * bnx2x_set_int_mode - configure interrupt mode
7802  *
7803  * @bp:         driver handle
7804  *
7805  * In case of MSI-X it will also try to enable MSI-X.
7806  */
7807 int bnx2x_set_int_mode(struct bnx2x *bp)
7808 {
7809         int rc = 0;
7810
7811         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7812                 return -EINVAL;
7813
7814         switch (int_mode) {
7815         case BNX2X_INT_MODE_MSIX:
7816                 /* attempt to enable msix */
7817                 rc = bnx2x_enable_msix(bp);
7818
7819                 /* msix attained */
7820                 if (!rc)
7821                         return 0;
7822
7823                 /* vfs use only msix */
7824                 if (rc && IS_VF(bp))
7825                         return rc;
7826
7827                 /* failed to enable multiple MSI-X */
7828                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7829                                bp->num_queues,
7830                                1 + bp->num_cnic_queues);
7831
7832                 /* falling through... */
7833         case BNX2X_INT_MODE_MSI:
7834                 bnx2x_enable_msi(bp);
7835
7836                 /* falling through... */
7837         case BNX2X_INT_MODE_INTX:
7838                 bp->num_ethernet_queues = 1;
7839                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7840                 BNX2X_DEV_INFO("set number of queues to 1\n");
7841                 break;
7842         default:
7843                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7844                 return -EINVAL;
7845         }
7846         return 0;
7847 }
7848
7849 /* must be called prior to any HW initializations */
7850 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7851 {
7852         return L2_ILT_LINES(bp);
7853 }
7854
7855 void bnx2x_ilt_set_info(struct bnx2x *bp)
7856 {
7857         struct ilt_client_info *ilt_client;
7858         struct bnx2x_ilt *ilt = BP_ILT(bp);
7859         u16 line = 0;
7860
7861         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7862         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7863
7864         /* CDU */
7865         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7866         ilt_client->client_num = ILT_CLIENT_CDU;
7867         ilt_client->page_size = CDU_ILT_PAGE_SZ;
7868         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7869         ilt_client->start = line;
7870         line += bnx2x_cid_ilt_lines(bp);
7871
7872         if (CNIC_SUPPORT(bp))
7873                 line += CNIC_ILT_LINES;
7874         ilt_client->end = line - 1;
7875
7876         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7877            ilt_client->start,
7878            ilt_client->end,
7879            ilt_client->page_size,
7880            ilt_client->flags,
7881            ilog2(ilt_client->page_size >> 12));
7882
7883         /* QM */
7884         if (QM_INIT(bp->qm_cid_count)) {
7885                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7886                 ilt_client->client_num = ILT_CLIENT_QM;
7887                 ilt_client->page_size = QM_ILT_PAGE_SZ;
7888                 ilt_client->flags = 0;
7889                 ilt_client->start = line;
7890
7891                 /* 4 bytes for each cid */
7892                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7893                                                          QM_ILT_PAGE_SZ);
7894
7895                 ilt_client->end = line - 1;
7896
7897                 DP(NETIF_MSG_IFUP,
7898                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7899                    ilt_client->start,
7900                    ilt_client->end,
7901                    ilt_client->page_size,
7902                    ilt_client->flags,
7903                    ilog2(ilt_client->page_size >> 12));
7904
7905         }
7906
7907         if (CNIC_SUPPORT(bp)) {
7908                 /* SRC */
7909                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7910                 ilt_client->client_num = ILT_CLIENT_SRC;
7911                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7912                 ilt_client->flags = 0;
7913                 ilt_client->start = line;
7914                 line += SRC_ILT_LINES;
7915                 ilt_client->end = line - 1;
7916
7917                 DP(NETIF_MSG_IFUP,
7918                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7919                    ilt_client->start,
7920                    ilt_client->end,
7921                    ilt_client->page_size,
7922                    ilt_client->flags,
7923                    ilog2(ilt_client->page_size >> 12));
7924
7925                 /* TM */
7926                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7927                 ilt_client->client_num = ILT_CLIENT_TM;
7928                 ilt_client->page_size = TM_ILT_PAGE_SZ;
7929                 ilt_client->flags = 0;
7930                 ilt_client->start = line;
7931                 line += TM_ILT_LINES;
7932                 ilt_client->end = line - 1;
7933
7934                 DP(NETIF_MSG_IFUP,
7935                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7936                    ilt_client->start,
7937                    ilt_client->end,
7938                    ilt_client->page_size,
7939                    ilt_client->flags,
7940                    ilog2(ilt_client->page_size >> 12));
7941         }
7942
7943         BUG_ON(line > ILT_MAX_LINES);
7944 }
7945
7946 /**
7947  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7948  *
7949  * @bp:                 driver handle
7950  * @fp:                 pointer to fastpath
7951  * @init_params:        pointer to parameters structure
7952  *
7953  * parameters configured:
7954  *      - HC configuration
7955  *      - Queue's CDU context
7956  */
7957 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7958         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7959 {
7960
7961         u8 cos;
7962         int cxt_index, cxt_offset;
7963
7964         /* FCoE Queue uses Default SB, thus has no HC capabilities */
7965         if (!IS_FCOE_FP(fp)) {
7966                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7967                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7968
7969                 /* If HC is supporterd, enable host coalescing in the transition
7970                  * to INIT state.
7971                  */
7972                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7973                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7974
7975                 /* HC rate */
7976                 init_params->rx.hc_rate = bp->rx_ticks ?
7977                         (1000000 / bp->rx_ticks) : 0;
7978                 init_params->tx.hc_rate = bp->tx_ticks ?
7979                         (1000000 / bp->tx_ticks) : 0;
7980
7981                 /* FW SB ID */
7982                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7983                         fp->fw_sb_id;
7984
7985                 /*
7986                  * CQ index among the SB indices: FCoE clients uses the default
7987                  * SB, therefore it's different.
7988                  */
7989                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7990                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7991         }
7992
7993         /* set maximum number of COSs supported by this queue */
7994         init_params->max_cos = fp->max_cos;
7995
7996         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7997             fp->index, init_params->max_cos);
7998
7999         /* set the context pointers queue object */
8000         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8001                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8002                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8003                                 ILT_PAGE_CIDS);
8004                 init_params->cxts[cos] =
8005                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8006         }
8007 }
8008
8009 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8010                         struct bnx2x_queue_state_params *q_params,
8011                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8012                         int tx_index, bool leading)
8013 {
8014         memset(tx_only_params, 0, sizeof(*tx_only_params));
8015
8016         /* Set the command */
8017         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8018
8019         /* Set tx-only QUEUE flags: don't zero statistics */
8020         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8021
8022         /* choose the index of the cid to send the slow path on */
8023         tx_only_params->cid_index = tx_index;
8024
8025         /* Set general TX_ONLY_SETUP parameters */
8026         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8027
8028         /* Set Tx TX_ONLY_SETUP parameters */
8029         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8030
8031         DP(NETIF_MSG_IFUP,
8032            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8033            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8034            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8035            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8036
8037         /* send the ramrod */
8038         return bnx2x_queue_state_change(bp, q_params);
8039 }
8040
8041
8042 /**
8043  * bnx2x_setup_queue - setup queue
8044  *
8045  * @bp:         driver handle
8046  * @fp:         pointer to fastpath
8047  * @leading:    is leading
8048  *
8049  * This function performs 2 steps in a Queue state machine
8050  *      actually: 1) RESET->INIT 2) INIT->SETUP
8051  */
8052
8053 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8054                        bool leading)
8055 {
8056         struct bnx2x_queue_state_params q_params = {NULL};
8057         struct bnx2x_queue_setup_params *setup_params =
8058                                                 &q_params.params.setup;
8059         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8060                                                 &q_params.params.tx_only;
8061         int rc;
8062         u8 tx_index;
8063
8064         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8065
8066         /* reset IGU state skip FCoE L2 queue */
8067         if (!IS_FCOE_FP(fp))
8068                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8069                              IGU_INT_ENABLE, 0);
8070
8071         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8072         /* We want to wait for completion in this context */
8073         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8074
8075         /* Prepare the INIT parameters */
8076         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8077
8078         /* Set the command */
8079         q_params.cmd = BNX2X_Q_CMD_INIT;
8080
8081         /* Change the state to INIT */
8082         rc = bnx2x_queue_state_change(bp, &q_params);
8083         if (rc) {
8084                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8085                 return rc;
8086         }
8087
8088         DP(NETIF_MSG_IFUP, "init complete\n");
8089
8090
8091         /* Now move the Queue to the SETUP state... */
8092         memset(setup_params, 0, sizeof(*setup_params));
8093
8094         /* Set QUEUE flags */
8095         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8096
8097         /* Set general SETUP parameters */
8098         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8099                                 FIRST_TX_COS_INDEX);
8100
8101         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8102                             &setup_params->rxq_params);
8103
8104         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8105                            FIRST_TX_COS_INDEX);
8106
8107         /* Set the command */
8108         q_params.cmd = BNX2X_Q_CMD_SETUP;
8109
8110         if (IS_FCOE_FP(fp))
8111                 bp->fcoe_init = true;
8112
8113         /* Change the state to SETUP */
8114         rc = bnx2x_queue_state_change(bp, &q_params);
8115         if (rc) {
8116                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8117                 return rc;
8118         }
8119
8120         /* loop through the relevant tx-only indices */
8121         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8122               tx_index < fp->max_cos;
8123               tx_index++) {
8124
8125                 /* prepare and send tx-only ramrod*/
8126                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8127                                           tx_only_params, tx_index, leading);
8128                 if (rc) {
8129                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8130                                   fp->index, tx_index);
8131                         return rc;
8132                 }
8133         }
8134
8135         return rc;
8136 }
8137
8138 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8139 {
8140         struct bnx2x_fastpath *fp = &bp->fp[index];
8141         struct bnx2x_fp_txdata *txdata;
8142         struct bnx2x_queue_state_params q_params = {NULL};
8143         int rc, tx_index;
8144
8145         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8146
8147         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8148         /* We want to wait for completion in this context */
8149         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8150
8151
8152         /* close tx-only connections */
8153         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8154              tx_index < fp->max_cos;
8155              tx_index++){
8156
8157                 /* ascertain this is a normal queue*/
8158                 txdata = fp->txdata_ptr[tx_index];
8159
8160                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8161                                                         txdata->txq_index);
8162
8163                 /* send halt terminate on tx-only connection */
8164                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8165                 memset(&q_params.params.terminate, 0,
8166                        sizeof(q_params.params.terminate));
8167                 q_params.params.terminate.cid_index = tx_index;
8168
8169                 rc = bnx2x_queue_state_change(bp, &q_params);
8170                 if (rc)
8171                         return rc;
8172
8173                 /* send halt terminate on tx-only connection */
8174                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8175                 memset(&q_params.params.cfc_del, 0,
8176                        sizeof(q_params.params.cfc_del));
8177                 q_params.params.cfc_del.cid_index = tx_index;
8178                 rc = bnx2x_queue_state_change(bp, &q_params);
8179                 if (rc)
8180                         return rc;
8181         }
8182         /* Stop the primary connection: */
8183         /* ...halt the connection */
8184         q_params.cmd = BNX2X_Q_CMD_HALT;
8185         rc = bnx2x_queue_state_change(bp, &q_params);
8186         if (rc)
8187                 return rc;
8188
8189         /* ...terminate the connection */
8190         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8191         memset(&q_params.params.terminate, 0,
8192                sizeof(q_params.params.terminate));
8193         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8194         rc = bnx2x_queue_state_change(bp, &q_params);
8195         if (rc)
8196                 return rc;
8197         /* ...delete cfc entry */
8198         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8199         memset(&q_params.params.cfc_del, 0,
8200                sizeof(q_params.params.cfc_del));
8201         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8202         return bnx2x_queue_state_change(bp, &q_params);
8203 }
8204
8205
8206 static void bnx2x_reset_func(struct bnx2x *bp)
8207 {
8208         int port = BP_PORT(bp);
8209         int func = BP_FUNC(bp);
8210         int i;
8211
8212         /* Disable the function in the FW */
8213         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8214         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8215         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8216         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8217
8218         /* FP SBs */
8219         for_each_eth_queue(bp, i) {
8220                 struct bnx2x_fastpath *fp = &bp->fp[i];
8221                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8222                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8223                            SB_DISABLED);
8224         }
8225
8226         if (CNIC_LOADED(bp))
8227                 /* CNIC SB */
8228                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8229                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8230                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8231
8232         /* SP SB */
8233         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8234                    CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8235                    SB_DISABLED);
8236
8237         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8238                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8239                        0);
8240
8241         /* Configure IGU */
8242         if (bp->common.int_block == INT_BLOCK_HC) {
8243                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8244                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8245         } else {
8246                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8247                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8248         }
8249
8250         if (CNIC_LOADED(bp)) {
8251                 /* Disable Timer scan */
8252                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8253                 /*
8254                  * Wait for at least 10ms and up to 2 second for the timers
8255                  * scan to complete
8256                  */
8257                 for (i = 0; i < 200; i++) {
8258                         msleep(10);
8259                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8260                                 break;
8261                 }
8262         }
8263         /* Clear ILT */
8264         bnx2x_clear_func_ilt(bp, func);
8265
8266         /* Timers workaround bug for E2: if this is vnic-3,
8267          * we need to set the entire ilt range for this timers.
8268          */
8269         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8270                 struct ilt_client_info ilt_cli;
8271                 /* use dummy TM client */
8272                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8273                 ilt_cli.start = 0;
8274                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8275                 ilt_cli.client_num = ILT_CLIENT_TM;
8276
8277                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8278         }
8279
8280         /* this assumes that reset_port() called before reset_func()*/
8281         if (!CHIP_IS_E1x(bp))
8282                 bnx2x_pf_disable(bp);
8283
8284         bp->dmae_ready = 0;
8285 }
8286
8287 static void bnx2x_reset_port(struct bnx2x *bp)
8288 {
8289         int port = BP_PORT(bp);
8290         u32 val;
8291
8292         /* Reset physical Link */
8293         bnx2x__link_reset(bp);
8294
8295         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8296
8297         /* Do not rcv packets to BRB */
8298         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8299         /* Do not direct rcv packets that are not for MCP to the BRB */
8300         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8301                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8302
8303         /* Configure AEU */
8304         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8305
8306         msleep(100);
8307         /* Check for BRB port occupancy */
8308         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8309         if (val)
8310                 DP(NETIF_MSG_IFDOWN,
8311                    "BRB1 is not empty  %d blocks are occupied\n", val);
8312
8313         /* TODO: Close Doorbell port? */
8314 }
8315
8316 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8317 {
8318         struct bnx2x_func_state_params func_params = {NULL};
8319
8320         /* Prepare parameters for function state transitions */
8321         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8322
8323         func_params.f_obj = &bp->func_obj;
8324         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8325
8326         func_params.params.hw_init.load_phase = load_code;
8327
8328         return bnx2x_func_state_change(bp, &func_params);
8329 }
8330
8331 static int bnx2x_func_stop(struct bnx2x *bp)
8332 {
8333         struct bnx2x_func_state_params func_params = {NULL};
8334         int rc;
8335
8336         /* Prepare parameters for function state transitions */
8337         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8338         func_params.f_obj = &bp->func_obj;
8339         func_params.cmd = BNX2X_F_CMD_STOP;
8340
8341         /*
8342          * Try to stop the function the 'good way'. If fails (in case
8343          * of a parity error during bnx2x_chip_cleanup()) and we are
8344          * not in a debug mode, perform a state transaction in order to
8345          * enable further HW_RESET transaction.
8346          */
8347         rc = bnx2x_func_state_change(bp, &func_params);
8348         if (rc) {
8349 #ifdef BNX2X_STOP_ON_ERROR
8350                 return rc;
8351 #else
8352                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8353                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8354                 return bnx2x_func_state_change(bp, &func_params);
8355 #endif
8356         }
8357
8358         return 0;
8359 }
8360
8361 /**
8362  * bnx2x_send_unload_req - request unload mode from the MCP.
8363  *
8364  * @bp:                 driver handle
8365  * @unload_mode:        requested function's unload mode
8366  *
8367  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8368  */
8369 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8370 {
8371         u32 reset_code = 0;
8372         int port = BP_PORT(bp);
8373
8374         /* Select the UNLOAD request mode */
8375         if (unload_mode == UNLOAD_NORMAL)
8376                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8377
8378         else if (bp->flags & NO_WOL_FLAG)
8379                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8380
8381         else if (bp->wol) {
8382                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8383                 u8 *mac_addr = bp->dev->dev_addr;
8384                 u32 val;
8385                 u16 pmc;
8386
8387                 /* The mac address is written to entries 1-4 to
8388                  * preserve entry 0 which is used by the PMF
8389                  */
8390                 u8 entry = (BP_VN(bp) + 1)*8;
8391
8392                 val = (mac_addr[0] << 8) | mac_addr[1];
8393                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8394
8395                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8396                       (mac_addr[4] << 8) | mac_addr[5];
8397                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8398
8399                 /* Enable the PME and clear the status */
8400                 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8401                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8402                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8403
8404                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8405
8406         } else
8407                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8408
8409         /* Send the request to the MCP */
8410         if (!BP_NOMCP(bp))
8411                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8412         else {
8413                 int path = BP_PATH(bp);
8414
8415                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8416                    path, load_count[path][0], load_count[path][1],
8417                    load_count[path][2]);
8418                 load_count[path][0]--;
8419                 load_count[path][1 + port]--;
8420                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8421                    path, load_count[path][0], load_count[path][1],
8422                    load_count[path][2]);
8423                 if (load_count[path][0] == 0)
8424                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8425                 else if (load_count[path][1 + port] == 0)
8426                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8427                 else
8428                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8429         }
8430
8431         return reset_code;
8432 }
8433
8434 /**
8435  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8436  *
8437  * @bp:         driver handle
8438  * @keep_link:          true iff link should be kept up
8439  */
8440 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8441 {
8442         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8443
8444         /* Report UNLOAD_DONE to MCP */
8445         if (!BP_NOMCP(bp))
8446                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8447 }
8448
8449 static int bnx2x_func_wait_started(struct bnx2x *bp)
8450 {
8451         int tout = 50;
8452         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8453
8454         if (!bp->port.pmf)
8455                 return 0;
8456
8457         /*
8458          * (assumption: No Attention from MCP at this stage)
8459          * PMF probably in the middle of TXdisable/enable transaction
8460          * 1. Sync IRS for default SB
8461          * 2. Sync SP queue - this guarantes us that attention handling started
8462          * 3. Wait, that TXdisable/enable transaction completes
8463          *
8464          * 1+2 guranty that if DCBx attention was scheduled it already changed
8465          * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8466          * received complettion for the transaction the state is TX_STOPPED.
8467          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8468          * transaction.
8469          */
8470
8471         /* make sure default SB ISR is done */
8472         if (msix)
8473                 synchronize_irq(bp->msix_table[0].vector);
8474         else
8475                 synchronize_irq(bp->pdev->irq);
8476
8477         flush_workqueue(bnx2x_wq);
8478
8479         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8480                                 BNX2X_F_STATE_STARTED && tout--)
8481                 msleep(20);
8482
8483         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8484                                                 BNX2X_F_STATE_STARTED) {
8485 #ifdef BNX2X_STOP_ON_ERROR
8486                 BNX2X_ERR("Wrong function state\n");
8487                 return -EBUSY;
8488 #else
8489                 /*
8490                  * Failed to complete the transaction in a "good way"
8491                  * Force both transactions with CLR bit
8492                  */
8493                 struct bnx2x_func_state_params func_params = {NULL};
8494
8495                 DP(NETIF_MSG_IFDOWN,
8496                    "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8497
8498                 func_params.f_obj = &bp->func_obj;
8499                 __set_bit(RAMROD_DRV_CLR_ONLY,
8500                                         &func_params.ramrod_flags);
8501
8502                 /* STARTED-->TX_ST0PPED */
8503                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8504                 bnx2x_func_state_change(bp, &func_params);
8505
8506                 /* TX_ST0PPED-->STARTED */
8507                 func_params.cmd = BNX2X_F_CMD_TX_START;
8508                 return bnx2x_func_state_change(bp, &func_params);
8509 #endif
8510         }
8511
8512         return 0;
8513 }
8514
8515 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8516 {
8517         int port = BP_PORT(bp);
8518         int i, rc = 0;
8519         u8 cos;
8520         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8521         u32 reset_code;
8522
8523         /* Wait until tx fastpath tasks complete */
8524         for_each_tx_queue(bp, i) {
8525                 struct bnx2x_fastpath *fp = &bp->fp[i];
8526
8527                 for_each_cos_in_tx_queue(fp, cos)
8528                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8529 #ifdef BNX2X_STOP_ON_ERROR
8530                 if (rc)
8531                         return;
8532 #endif
8533         }
8534
8535         /* Give HW time to discard old tx messages */
8536         usleep_range(1000, 1000);
8537
8538         /* Clean all ETH MACs */
8539         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8540                                 false);
8541         if (rc < 0)
8542                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8543
8544         /* Clean up UC list  */
8545         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8546                                 true);
8547         if (rc < 0)
8548                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8549                           rc);
8550
8551         /* Disable LLH */
8552         if (!CHIP_IS_E1(bp))
8553                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8554
8555         /* Set "drop all" (stop Rx).
8556          * We need to take a netif_addr_lock() here in order to prevent
8557          * a race between the completion code and this code.
8558          */
8559         netif_addr_lock_bh(bp->dev);
8560         /* Schedule the rx_mode command */
8561         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8562                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8563         else
8564                 bnx2x_set_storm_rx_mode(bp);
8565
8566         /* Cleanup multicast configuration */
8567         rparam.mcast_obj = &bp->mcast_obj;
8568         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8569         if (rc < 0)
8570                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8571
8572         netif_addr_unlock_bh(bp->dev);
8573
8574
8575
8576         /*
8577          * Send the UNLOAD_REQUEST to the MCP. This will return if
8578          * this function should perform FUNC, PORT or COMMON HW
8579          * reset.
8580          */
8581         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8582
8583         /*
8584          * (assumption: No Attention from MCP at this stage)
8585          * PMF probably in the middle of TXdisable/enable transaction
8586          */
8587         rc = bnx2x_func_wait_started(bp);
8588         if (rc) {
8589                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8590 #ifdef BNX2X_STOP_ON_ERROR
8591                 return;
8592 #endif
8593         }
8594
8595         /* Close multi and leading connections
8596          * Completions for ramrods are collected in a synchronous way
8597          */
8598         for_each_eth_queue(bp, i)
8599                 if (bnx2x_stop_queue(bp, i))
8600 #ifdef BNX2X_STOP_ON_ERROR
8601                         return;
8602 #else
8603                         goto unload_error;
8604 #endif
8605
8606         if (CNIC_LOADED(bp)) {
8607                 for_each_cnic_queue(bp, i)
8608                         if (bnx2x_stop_queue(bp, i))
8609 #ifdef BNX2X_STOP_ON_ERROR
8610                                 return;
8611 #else
8612                                 goto unload_error;
8613 #endif
8614         }
8615
8616         /* If SP settings didn't get completed so far - something
8617          * very wrong has happen.
8618          */
8619         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8620                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8621
8622 #ifndef BNX2X_STOP_ON_ERROR
8623 unload_error:
8624 #endif
8625         rc = bnx2x_func_stop(bp);
8626         if (rc) {
8627                 BNX2X_ERR("Function stop failed!\n");
8628 #ifdef BNX2X_STOP_ON_ERROR
8629                 return;
8630 #endif
8631         }
8632
8633         /* Disable HW interrupts, NAPI */
8634         bnx2x_netif_stop(bp, 1);
8635         /* Delete all NAPI objects */
8636         bnx2x_del_all_napi(bp);
8637         if (CNIC_LOADED(bp))
8638                 bnx2x_del_all_napi_cnic(bp);
8639
8640         /* Release IRQs */
8641         bnx2x_free_irq(bp);
8642
8643         /* Reset the chip */
8644         rc = bnx2x_reset_hw(bp, reset_code);
8645         if (rc)
8646                 BNX2X_ERR("HW_RESET failed\n");
8647
8648
8649         /* Report UNLOAD_DONE to MCP */
8650         bnx2x_send_unload_done(bp, keep_link);
8651 }
8652
8653 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8654 {
8655         u32 val;
8656
8657         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8658
8659         if (CHIP_IS_E1(bp)) {
8660                 int port = BP_PORT(bp);
8661                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8662                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8663
8664                 val = REG_RD(bp, addr);
8665                 val &= ~(0x300);
8666                 REG_WR(bp, addr, val);
8667         } else {
8668                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8669                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8670                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8671                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8672         }
8673 }
8674
8675 /* Close gates #2, #3 and #4: */
8676 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8677 {
8678         u32 val;
8679
8680         /* Gates #2 and #4a are closed/opened for "not E1" only */
8681         if (!CHIP_IS_E1(bp)) {
8682                 /* #4 */
8683                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8684                 /* #2 */
8685                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8686         }
8687
8688         /* #3 */
8689         if (CHIP_IS_E1x(bp)) {
8690                 /* Prevent interrupts from HC on both ports */
8691                 val = REG_RD(bp, HC_REG_CONFIG_1);
8692                 REG_WR(bp, HC_REG_CONFIG_1,
8693                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8694                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8695
8696                 val = REG_RD(bp, HC_REG_CONFIG_0);
8697                 REG_WR(bp, HC_REG_CONFIG_0,
8698                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8699                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8700         } else {
8701                 /* Prevent incomming interrupts in IGU */
8702                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8703
8704                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8705                        (!close) ?
8706                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8707                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8708         }
8709
8710         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8711                 close ? "closing" : "opening");
8712         mmiowb();
8713 }
8714
8715 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
8716
8717 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8718 {
8719         /* Do some magic... */
8720         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8721         *magic_val = val & SHARED_MF_CLP_MAGIC;
8722         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8723 }
8724
8725 /**
8726  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8727  *
8728  * @bp:         driver handle
8729  * @magic_val:  old value of the `magic' bit.
8730  */
8731 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8732 {
8733         /* Restore the `magic' bit value... */
8734         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8735         MF_CFG_WR(bp, shared_mf_config.clp_mb,
8736                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8737 }
8738
8739 /**
8740  * bnx2x_reset_mcp_prep - prepare for MCP reset.
8741  *
8742  * @bp:         driver handle
8743  * @magic_val:  old value of 'magic' bit.
8744  *
8745  * Takes care of CLP configurations.
8746  */
8747 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8748 {
8749         u32 shmem;
8750         u32 validity_offset;
8751
8752         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8753
8754         /* Set `magic' bit in order to save MF config */
8755         if (!CHIP_IS_E1(bp))
8756                 bnx2x_clp_reset_prep(bp, magic_val);
8757
8758         /* Get shmem offset */
8759         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8760         validity_offset =
8761                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8762
8763         /* Clear validity map flags */
8764         if (shmem > 0)
8765                 REG_WR(bp, shmem + validity_offset, 0);
8766 }
8767
8768 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
8769 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
8770
8771 /**
8772  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8773  *
8774  * @bp: driver handle
8775  */
8776 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8777 {
8778         /* special handling for emulation and FPGA,
8779            wait 10 times longer */
8780         if (CHIP_REV_IS_SLOW(bp))
8781                 msleep(MCP_ONE_TIMEOUT*10);
8782         else
8783                 msleep(MCP_ONE_TIMEOUT);
8784 }
8785
8786 /*
8787  * initializes bp->common.shmem_base and waits for validity signature to appear
8788  */
8789 static int bnx2x_init_shmem(struct bnx2x *bp)
8790 {
8791         int cnt = 0;
8792         u32 val = 0;
8793
8794         do {
8795                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8796                 if (bp->common.shmem_base) {
8797                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8798                         if (val & SHR_MEM_VALIDITY_MB)
8799                                 return 0;
8800                 }
8801
8802                 bnx2x_mcp_wait_one(bp);
8803
8804         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8805
8806         BNX2X_ERR("BAD MCP validity signature\n");
8807
8808         return -ENODEV;
8809 }
8810
8811 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8812 {
8813         int rc = bnx2x_init_shmem(bp);
8814
8815         /* Restore the `magic' bit value */
8816         if (!CHIP_IS_E1(bp))
8817                 bnx2x_clp_reset_done(bp, magic_val);
8818
8819         return rc;
8820 }
8821
8822 static void bnx2x_pxp_prep(struct bnx2x *bp)
8823 {
8824         if (!CHIP_IS_E1(bp)) {
8825                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8826                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8827                 mmiowb();
8828         }
8829 }
8830
8831 /*
8832  * Reset the whole chip except for:
8833  *      - PCIE core
8834  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8835  *              one reset bit)
8836  *      - IGU
8837  *      - MISC (including AEU)
8838  *      - GRC
8839  *      - RBCN, RBCP
8840  */
8841 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8842 {
8843         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8844         u32 global_bits2, stay_reset2;
8845
8846         /*
8847          * Bits that have to be set in reset_mask2 if we want to reset 'global'
8848          * (per chip) blocks.
8849          */
8850         global_bits2 =
8851                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8852                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8853
8854         /* Don't reset the following blocks.
8855          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
8856          *            reset, as in 4 port device they might still be owned
8857          *            by the MCP (there is only one leader per path).
8858          */
8859         not_reset_mask1 =
8860                 MISC_REGISTERS_RESET_REG_1_RST_HC |
8861                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8862                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8863
8864         not_reset_mask2 =
8865                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8866                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8867                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8868                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8869                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8870                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
8871                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8872                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8873                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8874                 MISC_REGISTERS_RESET_REG_2_PGLC |
8875                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8876                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8877                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8878                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8879                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8880                 MISC_REGISTERS_RESET_REG_2_UMAC1;
8881
8882         /*
8883          * Keep the following blocks in reset:
8884          *  - all xxMACs are handled by the bnx2x_link code.
8885          */
8886         stay_reset2 =
8887                 MISC_REGISTERS_RESET_REG_2_XMAC |
8888                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8889
8890         /* Full reset masks according to the chip */
8891         reset_mask1 = 0xffffffff;
8892
8893         if (CHIP_IS_E1(bp))
8894                 reset_mask2 = 0xffff;
8895         else if (CHIP_IS_E1H(bp))
8896                 reset_mask2 = 0x1ffff;
8897         else if (CHIP_IS_E2(bp))
8898                 reset_mask2 = 0xfffff;
8899         else /* CHIP_IS_E3 */
8900                 reset_mask2 = 0x3ffffff;
8901
8902         /* Don't reset global blocks unless we need to */
8903         if (!global)
8904                 reset_mask2 &= ~global_bits2;
8905
8906         /*
8907          * In case of attention in the QM, we need to reset PXP
8908          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8909          * because otherwise QM reset would release 'close the gates' shortly
8910          * before resetting the PXP, then the PSWRQ would send a write
8911          * request to PGLUE. Then when PXP is reset, PGLUE would try to
8912          * read the payload data from PSWWR, but PSWWR would not
8913          * respond. The write queue in PGLUE would stuck, dmae commands
8914          * would not return. Therefore it's important to reset the second
8915          * reset register (containing the
8916          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8917          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8918          * bit).
8919          */
8920         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8921                reset_mask2 & (~not_reset_mask2));
8922
8923         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8924                reset_mask1 & (~not_reset_mask1));
8925
8926         barrier();
8927         mmiowb();
8928
8929         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8930                reset_mask2 & (~stay_reset2));
8931
8932         barrier();
8933         mmiowb();
8934
8935         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8936         mmiowb();
8937 }
8938
8939 /**
8940  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8941  * It should get cleared in no more than 1s.
8942  *
8943  * @bp: driver handle
8944  *
8945  * It should get cleared in no more than 1s. Returns 0 if
8946  * pending writes bit gets cleared.
8947  */
8948 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8949 {
8950         u32 cnt = 1000;
8951         u32 pend_bits = 0;
8952
8953         do {
8954                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8955
8956                 if (pend_bits == 0)
8957                         break;
8958
8959                 usleep_range(1000, 1000);
8960         } while (cnt-- > 0);
8961
8962         if (cnt <= 0) {
8963                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8964                           pend_bits);
8965                 return -EBUSY;
8966         }
8967
8968         return 0;
8969 }
8970
8971 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8972 {
8973         int cnt = 1000;
8974         u32 val = 0;
8975         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8976                 u32 tags_63_32 = 0;
8977
8978
8979         /* Empty the Tetris buffer, wait for 1s */
8980         do {
8981                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8982                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8983                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8984                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8985                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8986                 if (CHIP_IS_E3(bp))
8987                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
8988
8989                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8990                     ((port_is_idle_0 & 0x1) == 0x1) &&
8991                     ((port_is_idle_1 & 0x1) == 0x1) &&
8992                     (pgl_exp_rom2 == 0xffffffff) &&
8993                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
8994                         break;
8995                 usleep_range(1000, 1000);
8996         } while (cnt-- > 0);
8997
8998         if (cnt <= 0) {
8999                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9000                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9001                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9002                           pgl_exp_rom2);
9003                 return -EAGAIN;
9004         }
9005
9006         barrier();
9007
9008         /* Close gates #2, #3 and #4 */
9009         bnx2x_set_234_gates(bp, true);
9010
9011         /* Poll for IGU VQs for 57712 and newer chips */
9012         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9013                 return -EAGAIN;
9014
9015
9016         /* TBD: Indicate that "process kill" is in progress to MCP */
9017
9018         /* Clear "unprepared" bit */
9019         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9020         barrier();
9021
9022         /* Make sure all is written to the chip before the reset */
9023         mmiowb();
9024
9025         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9026          * PSWHST, GRC and PSWRD Tetris buffer.
9027          */
9028         usleep_range(1000, 1000);
9029
9030         /* Prepare to chip reset: */
9031         /* MCP */
9032         if (global)
9033                 bnx2x_reset_mcp_prep(bp, &val);
9034
9035         /* PXP */
9036         bnx2x_pxp_prep(bp);
9037         barrier();
9038
9039         /* reset the chip */
9040         bnx2x_process_kill_chip_reset(bp, global);
9041         barrier();
9042
9043         /* Recover after reset: */
9044         /* MCP */
9045         if (global && bnx2x_reset_mcp_comp(bp, val))
9046                 return -EAGAIN;
9047
9048         /* TBD: Add resetting the NO_MCP mode DB here */
9049
9050         /* Open the gates #2, #3 and #4 */
9051         bnx2x_set_234_gates(bp, false);
9052
9053         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9054          * reset state, re-enable attentions. */
9055
9056         return 0;
9057 }
9058
9059 static int bnx2x_leader_reset(struct bnx2x *bp)
9060 {
9061         int rc = 0;
9062         bool global = bnx2x_reset_is_global(bp);
9063         u32 load_code;
9064
9065         /* if not going to reset MCP - load "fake" driver to reset HW while
9066          * driver is owner of the HW
9067          */
9068         if (!global && !BP_NOMCP(bp)) {
9069                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9070                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9071                 if (!load_code) {
9072                         BNX2X_ERR("MCP response failure, aborting\n");
9073                         rc = -EAGAIN;
9074                         goto exit_leader_reset;
9075                 }
9076                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9077                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9078                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9079                         rc = -EAGAIN;
9080                         goto exit_leader_reset2;
9081                 }
9082                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9083                 if (!load_code) {
9084                         BNX2X_ERR("MCP response failure, aborting\n");
9085                         rc = -EAGAIN;
9086                         goto exit_leader_reset2;
9087                 }
9088         }
9089
9090         /* Try to recover after the failure */
9091         if (bnx2x_process_kill(bp, global)) {
9092                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9093                           BP_PATH(bp));
9094                 rc = -EAGAIN;
9095                 goto exit_leader_reset2;
9096         }
9097
9098         /*
9099          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9100          * state.
9101          */
9102         bnx2x_set_reset_done(bp);
9103         if (global)
9104                 bnx2x_clear_reset_global(bp);
9105
9106 exit_leader_reset2:
9107         /* unload "fake driver" if it was loaded */
9108         if (!global && !BP_NOMCP(bp)) {
9109                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9110                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9111         }
9112 exit_leader_reset:
9113         bp->is_leader = 0;
9114         bnx2x_release_leader_lock(bp);
9115         smp_mb();
9116         return rc;
9117 }
9118
9119 static void bnx2x_recovery_failed(struct bnx2x *bp)
9120 {
9121         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9122
9123         /* Disconnect this device */
9124         netif_device_detach(bp->dev);
9125
9126         /*
9127          * Block ifup for all function on this engine until "process kill"
9128          * or power cycle.
9129          */
9130         bnx2x_set_reset_in_progress(bp);
9131
9132         /* Shut down the power */
9133         bnx2x_set_power_state(bp, PCI_D3hot);
9134
9135         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9136
9137         smp_mb();
9138 }
9139
9140 /*
9141  * Assumption: runs under rtnl lock. This together with the fact
9142  * that it's called only from bnx2x_sp_rtnl() ensure that it
9143  * will never be called when netif_running(bp->dev) is false.
9144  */
9145 static void bnx2x_parity_recover(struct bnx2x *bp)
9146 {
9147         bool global = false;
9148         u32 error_recovered, error_unrecovered;
9149         bool is_parity;
9150
9151         DP(NETIF_MSG_HW, "Handling parity\n");
9152         while (1) {
9153                 switch (bp->recovery_state) {
9154                 case BNX2X_RECOVERY_INIT:
9155                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9156                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9157                         WARN_ON(!is_parity);
9158
9159                         /* Try to get a LEADER_LOCK HW lock */
9160                         if (bnx2x_trylock_leader_lock(bp)) {
9161                                 bnx2x_set_reset_in_progress(bp);
9162                                 /*
9163                                  * Check if there is a global attention and if
9164                                  * there was a global attention, set the global
9165                                  * reset bit.
9166                                  */
9167
9168                                 if (global)
9169                                         bnx2x_set_reset_global(bp);
9170
9171                                 bp->is_leader = 1;
9172                         }
9173
9174                         /* Stop the driver */
9175                         /* If interface has been removed - break */
9176                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9177                                 return;
9178
9179                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9180
9181                         /* Ensure "is_leader", MCP command sequence and
9182                          * "recovery_state" update values are seen on other
9183                          * CPUs.
9184                          */
9185                         smp_mb();
9186                         break;
9187
9188                 case BNX2X_RECOVERY_WAIT:
9189                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9190                         if (bp->is_leader) {
9191                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9192                                 bool other_load_status =
9193                                         bnx2x_get_load_status(bp, other_engine);
9194                                 bool load_status =
9195                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9196                                 global = bnx2x_reset_is_global(bp);
9197
9198                                 /*
9199                                  * In case of a parity in a global block, let
9200                                  * the first leader that performs a
9201                                  * leader_reset() reset the global blocks in
9202                                  * order to clear global attentions. Otherwise
9203                                  * the the gates will remain closed for that
9204                                  * engine.
9205                                  */
9206                                 if (load_status ||
9207                                     (global && other_load_status)) {
9208                                         /* Wait until all other functions get
9209                                          * down.
9210                                          */
9211                                         schedule_delayed_work(&bp->sp_rtnl_task,
9212                                                                 HZ/10);
9213                                         return;
9214                                 } else {
9215                                         /* If all other functions got down -
9216                                          * try to bring the chip back to
9217                                          * normal. In any case it's an exit
9218                                          * point for a leader.
9219                                          */
9220                                         if (bnx2x_leader_reset(bp)) {
9221                                                 bnx2x_recovery_failed(bp);
9222                                                 return;
9223                                         }
9224
9225                                         /* If we are here, means that the
9226                                          * leader has succeeded and doesn't
9227                                          * want to be a leader any more. Try
9228                                          * to continue as a none-leader.
9229                                          */
9230                                         break;
9231                                 }
9232                         } else { /* non-leader */
9233                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9234                                         /* Try to get a LEADER_LOCK HW lock as
9235                                          * long as a former leader may have
9236                                          * been unloaded by the user or
9237                                          * released a leadership by another
9238                                          * reason.
9239                                          */
9240                                         if (bnx2x_trylock_leader_lock(bp)) {
9241                                                 /* I'm a leader now! Restart a
9242                                                  * switch case.
9243                                                  */
9244                                                 bp->is_leader = 1;
9245                                                 break;
9246                                         }
9247
9248                                         schedule_delayed_work(&bp->sp_rtnl_task,
9249                                                                 HZ/10);
9250                                         return;
9251
9252                                 } else {
9253                                         /*
9254                                          * If there was a global attention, wait
9255                                          * for it to be cleared.
9256                                          */
9257                                         if (bnx2x_reset_is_global(bp)) {
9258                                                 schedule_delayed_work(
9259                                                         &bp->sp_rtnl_task,
9260                                                         HZ/10);
9261                                                 return;
9262                                         }
9263
9264                                         error_recovered =
9265                                           bp->eth_stats.recoverable_error;
9266                                         error_unrecovered =
9267                                           bp->eth_stats.unrecoverable_error;
9268                                         bp->recovery_state =
9269                                                 BNX2X_RECOVERY_NIC_LOADING;
9270                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9271                                                 error_unrecovered++;
9272                                                 netdev_err(bp->dev,
9273                                                            "Recovery failed. Power cycle needed\n");
9274                                                 /* Disconnect this device */
9275                                                 netif_device_detach(bp->dev);
9276                                                 /* Shut down the power */
9277                                                 bnx2x_set_power_state(
9278                                                         bp, PCI_D3hot);
9279                                                 smp_mb();
9280                                         } else {
9281                                                 bp->recovery_state =
9282                                                         BNX2X_RECOVERY_DONE;
9283                                                 error_recovered++;
9284                                                 smp_mb();
9285                                         }
9286                                         bp->eth_stats.recoverable_error =
9287                                                 error_recovered;
9288                                         bp->eth_stats.unrecoverable_error =
9289                                                 error_unrecovered;
9290
9291                                         return;
9292                                 }
9293                         }
9294                 default:
9295                         return;
9296                 }
9297         }
9298 }
9299
9300 static int bnx2x_close(struct net_device *dev);
9301
9302 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9303  * scheduled on a general queue in order to prevent a dead lock.
9304  */
9305 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9306 {
9307         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9308
9309         rtnl_lock();
9310
9311         if (!netif_running(bp->dev))
9312                 goto sp_rtnl_exit;
9313
9314         /* if stop on error is defined no recovery flows should be executed */
9315 #ifdef BNX2X_STOP_ON_ERROR
9316         BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9317                   "you will need to reboot when done\n");
9318         goto sp_rtnl_not_reset;
9319 #endif
9320
9321         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9322                 /*
9323                  * Clear all pending SP commands as we are going to reset the
9324                  * function anyway.
9325                  */
9326                 bp->sp_rtnl_state = 0;
9327                 smp_mb();
9328
9329                 bnx2x_parity_recover(bp);
9330
9331                 goto sp_rtnl_exit;
9332         }
9333
9334         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9335                 /*
9336                  * Clear all pending SP commands as we are going to reset the
9337                  * function anyway.
9338                  */
9339                 bp->sp_rtnl_state = 0;
9340                 smp_mb();
9341
9342                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9343                 bnx2x_nic_load(bp, LOAD_NORMAL);
9344
9345                 goto sp_rtnl_exit;
9346         }
9347 #ifdef BNX2X_STOP_ON_ERROR
9348 sp_rtnl_not_reset:
9349 #endif
9350         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9351                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9352         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9353                 bnx2x_after_function_update(bp);
9354         /*
9355          * in case of fan failure we need to reset id if the "stop on error"
9356          * debug flag is set, since we trying to prevent permanent overheating
9357          * damage
9358          */
9359         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9360                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9361                 netif_device_detach(bp->dev);
9362                 bnx2x_close(bp->dev);
9363         }
9364
9365 sp_rtnl_exit:
9366         rtnl_unlock();
9367 }
9368
9369 /* end of nic load/unload */
9370
9371 static void bnx2x_period_task(struct work_struct *work)
9372 {
9373         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9374
9375         if (!netif_running(bp->dev))
9376                 goto period_task_exit;
9377
9378         if (CHIP_REV_IS_SLOW(bp)) {
9379                 BNX2X_ERR("period task called on emulation, ignoring\n");
9380                 goto period_task_exit;
9381         }
9382
9383         bnx2x_acquire_phy_lock(bp);
9384         /*
9385          * The barrier is needed to ensure the ordering between the writing to
9386          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9387          * the reading here.
9388          */
9389         smp_mb();
9390         if (bp->port.pmf) {
9391                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9392
9393                 /* Re-queue task in 1 sec */
9394                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9395         }
9396
9397         bnx2x_release_phy_lock(bp);
9398 period_task_exit:
9399         return;
9400 }
9401
9402 /*
9403  * Init service functions
9404  */
9405
9406 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9407 {
9408         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9409         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9410         return base + (BP_ABS_FUNC(bp)) * stride;
9411 }
9412
9413 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9414 {
9415         u32 reg = bnx2x_get_pretend_reg(bp);
9416
9417         /* Flush all outstanding writes */
9418         mmiowb();
9419
9420         /* Pretend to be function 0 */
9421         REG_WR(bp, reg, 0);
9422         REG_RD(bp, reg);        /* Flush the GRC transaction (in the chip) */
9423
9424         /* From now we are in the "like-E1" mode */
9425         bnx2x_int_disable(bp);
9426
9427         /* Flush all outstanding writes */
9428         mmiowb();
9429
9430         /* Restore the original function */
9431         REG_WR(bp, reg, BP_ABS_FUNC(bp));
9432         REG_RD(bp, reg);
9433 }
9434
9435 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9436 {
9437         if (CHIP_IS_E1(bp))
9438                 bnx2x_int_disable(bp);
9439         else
9440                 bnx2x_undi_int_disable_e1h(bp);
9441 }
9442
9443 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9444 {
9445         u32 val, base_addr, offset, mask, reset_reg;
9446         bool mac_stopped = false;
9447         u8 port = BP_PORT(bp);
9448
9449         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9450
9451         if (!CHIP_IS_E3(bp)) {
9452                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9453                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9454                 if ((mask & reset_reg) && val) {
9455                         u32 wb_data[2];
9456                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9457                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9458                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9459                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9460                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9461
9462                         /*
9463                          * use rd/wr since we cannot use dmae. This is safe
9464                          * since MCP won't access the bus due to the request
9465                          * to unload, and no function on the path can be
9466                          * loaded at this time.
9467                          */
9468                         wb_data[0] = REG_RD(bp, base_addr + offset);
9469                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9470                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9471                         REG_WR(bp, base_addr + offset, wb_data[0]);
9472                         REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9473
9474                 }
9475                 BNX2X_DEV_INFO("Disable emac Rx\n");
9476                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9477
9478                 mac_stopped = true;
9479         } else {
9480                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9481                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9482                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9483                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9484                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9485                                val & ~(1 << 1));
9486                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9487                                val | (1 << 1));
9488                         REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9489                         mac_stopped = true;
9490                 }
9491                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9492                 if (mask & reset_reg) {
9493                         BNX2X_DEV_INFO("Disable umac Rx\n");
9494                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9495                         REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9496                         mac_stopped = true;
9497                 }
9498         }
9499
9500         if (mac_stopped)
9501                 msleep(20);
9502
9503 }
9504
9505 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9506 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9507 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9508 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9509
9510 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9511 {
9512         u16 rcq, bd;
9513         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9514
9515         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9516         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9517
9518         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9519         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9520
9521         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9522                        port, bd, rcq);
9523 }
9524
9525 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9526 {
9527         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9528                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9529         if (!rc) {
9530                 BNX2X_ERR("MCP response failure, aborting\n");
9531                 return -EBUSY;
9532         }
9533
9534         return 0;
9535 }
9536
9537 static struct bnx2x_prev_path_list *
9538                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9539 {
9540         struct bnx2x_prev_path_list *tmp_list;
9541
9542         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9543                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9544                     bp->pdev->bus->number == tmp_list->bus &&
9545                     BP_PATH(bp) == tmp_list->path)
9546                         return tmp_list;
9547
9548         return NULL;
9549 }
9550
9551 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9552 {
9553         struct bnx2x_prev_path_list *tmp_list;
9554         int rc = false;
9555
9556         if (down_trylock(&bnx2x_prev_sem))
9557                 return false;
9558
9559         list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9560                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9561                     bp->pdev->bus->number == tmp_list->bus &&
9562                     BP_PATH(bp) == tmp_list->path) {
9563                         rc = true;
9564                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9565                                        BP_PATH(bp));
9566                         break;
9567                 }
9568         }
9569
9570         up(&bnx2x_prev_sem);
9571
9572         return rc;
9573 }
9574
9575 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9576 {
9577         struct bnx2x_prev_path_list *tmp_list;
9578         int rc;
9579
9580         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9581         if (!tmp_list) {
9582                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9583                 return -ENOMEM;
9584         }
9585
9586         tmp_list->bus = bp->pdev->bus->number;
9587         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9588         tmp_list->path = BP_PATH(bp);
9589         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9590
9591         rc = down_interruptible(&bnx2x_prev_sem);
9592         if (rc) {
9593                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9594                 kfree(tmp_list);
9595         } else {
9596                 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9597                                 BP_PATH(bp));
9598                 list_add(&tmp_list->list, &bnx2x_prev_list);
9599                 up(&bnx2x_prev_sem);
9600         }
9601
9602         return rc;
9603 }
9604
9605 static int bnx2x_do_flr(struct bnx2x *bp)
9606 {
9607         int i;
9608         u16 status;
9609         struct pci_dev *dev = bp->pdev;
9610
9611
9612         if (CHIP_IS_E1x(bp)) {
9613                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9614                 return -EINVAL;
9615         }
9616
9617         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9618         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9619                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9620                           bp->common.bc_ver);
9621                 return -EINVAL;
9622         }
9623
9624         /* Wait for Transaction Pending bit clean */
9625         for (i = 0; i < 4; i++) {
9626                 if (i)
9627                         msleep((1 << (i - 1)) * 100);
9628
9629                 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9630                 if (!(status & PCI_EXP_DEVSTA_TRPND))
9631                         goto clear;
9632         }
9633
9634         dev_err(&dev->dev,
9635                 "transaction is not cleared; proceeding with reset anyway\n");
9636
9637 clear:
9638
9639         BNX2X_DEV_INFO("Initiating FLR\n");
9640         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9641
9642         return 0;
9643 }
9644
9645 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9646 {
9647         int rc;
9648
9649         BNX2X_DEV_INFO("Uncommon unload Flow\n");
9650
9651         /* Test if previous unload process was already finished for this path */
9652         if (bnx2x_prev_is_path_marked(bp))
9653                 return bnx2x_prev_mcp_done(bp);
9654
9655         /* If function has FLR capabilities, and existing FW version matches
9656          * the one required, then FLR will be sufficient to clean any residue
9657          * left by previous driver
9658          */
9659         rc = bnx2x_test_firmware_version(bp, false);
9660
9661         if (!rc) {
9662                 /* fw version is good */
9663                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9664                 rc = bnx2x_do_flr(bp);
9665         }
9666
9667         if (!rc) {
9668                 /* FLR was performed */
9669                 BNX2X_DEV_INFO("FLR successful\n");
9670                 return 0;
9671         }
9672
9673         BNX2X_DEV_INFO("Could not FLR\n");
9674
9675         /* Close the MCP request, return failure*/
9676         rc = bnx2x_prev_mcp_done(bp);
9677         if (!rc)
9678                 rc = BNX2X_PREV_WAIT_NEEDED;
9679
9680         return rc;
9681 }
9682
9683 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9684 {
9685         u32 reset_reg, tmp_reg = 0, rc;
9686         bool prev_undi = false;
9687         /* It is possible a previous function received 'common' answer,
9688          * but hasn't loaded yet, therefore creating a scenario of
9689          * multiple functions receiving 'common' on the same path.
9690          */
9691         BNX2X_DEV_INFO("Common unload Flow\n");
9692
9693         if (bnx2x_prev_is_path_marked(bp))
9694                 return bnx2x_prev_mcp_done(bp);
9695
9696         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9697
9698         /* Reset should be performed after BRB is emptied */
9699         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9700                 u32 timer_count = 1000;
9701
9702                 /* Close the MAC Rx to prevent BRB from filling up */
9703                 bnx2x_prev_unload_close_mac(bp);
9704
9705                 /* Check if the UNDI driver was previously loaded
9706                  * UNDI driver initializes CID offset for normal bell to 0x7
9707                  */
9708                 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9709                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9710                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9711                         if (tmp_reg == 0x7) {
9712                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
9713                                 prev_undi = true;
9714                                 /* clear the UNDI indication */
9715                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9716                         }
9717                 }
9718                 /* wait until BRB is empty */
9719                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9720                 while (timer_count) {
9721                         u32 prev_brb = tmp_reg;
9722
9723                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9724                         if (!tmp_reg)
9725                                 break;
9726
9727                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9728
9729                         /* reset timer as long as BRB actually gets emptied */
9730                         if (prev_brb > tmp_reg)
9731                                 timer_count = 1000;
9732                         else
9733                                 timer_count--;
9734
9735                         /* If UNDI resides in memory, manually increment it */
9736                         if (prev_undi)
9737                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9738
9739                         udelay(10);
9740                 }
9741
9742                 if (!timer_count)
9743                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9744
9745         }
9746
9747         /* No packets are in the pipeline, path is ready for reset */
9748         bnx2x_reset_common(bp);
9749
9750         rc = bnx2x_prev_mark_path(bp, prev_undi);
9751         if (rc) {
9752                 bnx2x_prev_mcp_done(bp);
9753                 return rc;
9754         }
9755
9756         return bnx2x_prev_mcp_done(bp);
9757 }
9758
9759 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9760  * and boot began, or when kdump kernel was loaded. Either case would invalidate
9761  * the addresses of the transaction, resulting in was-error bit set in the pci
9762  * causing all hw-to-host pcie transactions to timeout. If this happened we want
9763  * to clear the interrupt which detected this from the pglueb and the was done
9764  * bit
9765  */
9766 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9767 {
9768         if (!CHIP_IS_E1x(bp)) {
9769                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9770                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9771                         BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9772                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9773                                1 << BP_FUNC(bp));
9774                 }
9775         }
9776 }
9777
9778 static int bnx2x_prev_unload(struct bnx2x *bp)
9779 {
9780         int time_counter = 10;
9781         u32 rc, fw, hw_lock_reg, hw_lock_val;
9782         struct bnx2x_prev_path_list *prev_list;
9783         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9784
9785         /* clear hw from errors which may have resulted from an interrupted
9786          * dmae transaction.
9787          */
9788         bnx2x_prev_interrupted_dmae(bp);
9789
9790         /* Release previously held locks */
9791         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9792                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9793                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9794
9795         hw_lock_val = (REG_RD(bp, hw_lock_reg));
9796         if (hw_lock_val) {
9797                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9798                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9799                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9800                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9801                 }
9802
9803                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9804                 REG_WR(bp, hw_lock_reg, 0xffffffff);
9805         } else
9806                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9807
9808         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9809                 BNX2X_DEV_INFO("Release previously held alr\n");
9810                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9811         }
9812
9813
9814         do {
9815                 /* Lock MCP using an unload request */
9816                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9817                 if (!fw) {
9818                         BNX2X_ERR("MCP response failure, aborting\n");
9819                         rc = -EBUSY;
9820                         break;
9821                 }
9822
9823                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9824                         rc = bnx2x_prev_unload_common(bp);
9825                         break;
9826                 }
9827
9828                 /* non-common reply from MCP night require looping */
9829                 rc = bnx2x_prev_unload_uncommon(bp);
9830                 if (rc != BNX2X_PREV_WAIT_NEEDED)
9831                         break;
9832
9833                 msleep(20);
9834         } while (--time_counter);
9835
9836         if (!time_counter || rc) {
9837                 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9838                 rc = -EBUSY;
9839         }
9840
9841         /* Mark function if its port was used to boot from SAN */
9842         prev_list = bnx2x_prev_path_get_entry(bp);
9843         if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
9844                 bp->link_params.feature_config_flags |=
9845                         FEATURE_CONFIG_BOOT_FROM_SAN;
9846
9847         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9848
9849         return rc;
9850 }
9851
9852 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
9853 {
9854         u32 val, val2, val3, val4, id, boot_mode;
9855         u16 pmc;
9856
9857         /* Get the chip revision id and number. */
9858         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9859         val = REG_RD(bp, MISC_REG_CHIP_NUM);
9860         id = ((val & 0xffff) << 16);
9861         val = REG_RD(bp, MISC_REG_CHIP_REV);
9862         id |= ((val & 0xf) << 12);
9863         val = REG_RD(bp, MISC_REG_CHIP_METAL);
9864         id |= ((val & 0xff) << 4);
9865         val = REG_RD(bp, MISC_REG_BOND_ID);
9866         id |= (val & 0xf);
9867         bp->common.chip_id = id;
9868
9869         /* force 57811 according to MISC register */
9870         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9871                 if (CHIP_IS_57810(bp))
9872                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9873                                 (bp->common.chip_id & 0x0000FFFF);
9874                 else if (CHIP_IS_57810_MF(bp))
9875                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9876                                 (bp->common.chip_id & 0x0000FFFF);
9877                 bp->common.chip_id |= 0x1;
9878         }
9879
9880         /* Set doorbell size */
9881         bp->db_size = (1 << BNX2X_DB_SHIFT);
9882
9883         if (!CHIP_IS_E1x(bp)) {
9884                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9885                 if ((val & 1) == 0)
9886                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9887                 else
9888                         val = (val >> 1) & 1;
9889                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9890                                                        "2_PORT_MODE");
9891                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9892                                                  CHIP_2_PORT_MODE;
9893
9894                 if (CHIP_MODE_IS_4_PORT(bp))
9895                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
9896                 else
9897                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
9898         } else {
9899                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9900                 bp->pfid = bp->pf_num;                  /* 0..7 */
9901         }
9902
9903         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9904
9905         bp->link_params.chip_id = bp->common.chip_id;
9906         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9907
9908         val = (REG_RD(bp, 0x2874) & 0x55);
9909         if ((bp->common.chip_id & 0x1) ||
9910             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9911                 bp->flags |= ONE_PORT_FLAG;
9912                 BNX2X_DEV_INFO("single port device\n");
9913         }
9914
9915         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9916         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9917                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
9918         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9919                        bp->common.flash_size, bp->common.flash_size);
9920
9921         bnx2x_init_shmem(bp);
9922
9923
9924
9925         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9926                                         MISC_REG_GENERIC_CR_1 :
9927                                         MISC_REG_GENERIC_CR_0));
9928
9929         bp->link_params.shmem_base = bp->common.shmem_base;
9930         bp->link_params.shmem2_base = bp->common.shmem2_base;
9931         if (SHMEM2_RD(bp, size) >
9932             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
9933                 bp->link_params.lfa_base =
9934                 REG_RD(bp, bp->common.shmem2_base +
9935                        (u32)offsetof(struct shmem2_region,
9936                                      lfa_host_addr[BP_PORT(bp)]));
9937         else
9938                 bp->link_params.lfa_base = 0;
9939         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
9940                        bp->common.shmem_base, bp->common.shmem2_base);
9941
9942         if (!bp->common.shmem_base) {
9943                 BNX2X_DEV_INFO("MCP not active\n");
9944                 bp->flags |= NO_MCP_FLAG;
9945                 return;
9946         }
9947
9948         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9949         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9950
9951         bp->link_params.hw_led_mode = ((bp->common.hw_config &
9952                                         SHARED_HW_CFG_LED_MODE_MASK) >>
9953                                        SHARED_HW_CFG_LED_MODE_SHIFT);
9954
9955         bp->link_params.feature_config_flags = 0;
9956         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9957         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9958                 bp->link_params.feature_config_flags |=
9959                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9960         else
9961                 bp->link_params.feature_config_flags &=
9962                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9963
9964         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9965         bp->common.bc_ver = val;
9966         BNX2X_DEV_INFO("bc_ver %X\n", val);
9967         if (val < BNX2X_BC_VER) {
9968                 /* for now only warn
9969                  * later we might need to enforce this */
9970                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9971                           BNX2X_BC_VER, val);
9972         }
9973         bp->link_params.feature_config_flags |=
9974                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9975                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9976
9977         bp->link_params.feature_config_flags |=
9978                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9979                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9980         bp->link_params.feature_config_flags |=
9981                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9982                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9983         bp->link_params.feature_config_flags |=
9984                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9985                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9986
9987         bp->link_params.feature_config_flags |=
9988                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
9989                 FEATURE_CONFIG_MT_SUPPORT : 0;
9990
9991         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9992                         BC_SUPPORTS_PFC_STATS : 0;
9993
9994         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9995                         BC_SUPPORTS_FCOE_FEATURES : 0;
9996
9997         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9998                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9999         boot_mode = SHMEM_RD(bp,
10000                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10001                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10002         switch (boot_mode) {
10003         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10004                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10005                 break;
10006         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10007                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10008                 break;
10009         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10010                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10011                 break;
10012         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10013                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10014                 break;
10015         }
10016
10017         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10018         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10019
10020         BNX2X_DEV_INFO("%sWoL capable\n",
10021                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10022
10023         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10024         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10025         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10026         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10027
10028         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10029                  val, val2, val3, val4);
10030 }
10031
10032 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10033 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10034
10035 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10036 {
10037         int pfid = BP_FUNC(bp);
10038         int igu_sb_id;
10039         u32 val;
10040         u8 fid, igu_sb_cnt = 0;
10041
10042         bp->igu_base_sb = 0xff;
10043         if (CHIP_INT_MODE_IS_BC(bp)) {
10044                 int vn = BP_VN(bp);
10045                 igu_sb_cnt = bp->igu_sb_cnt;
10046                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10047                         FP_SB_MAX_E1x;
10048
10049                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10050                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10051
10052                 return 0;
10053         }
10054
10055         /* IGU in normal mode - read CAM */
10056         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10057              igu_sb_id++) {
10058                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10059                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10060                         continue;
10061                 fid = IGU_FID(val);
10062                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10063                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10064                                 continue;
10065                         if (IGU_VEC(val) == 0)
10066                                 /* default status block */
10067                                 bp->igu_dsb_id = igu_sb_id;
10068                         else {
10069                                 if (bp->igu_base_sb == 0xff)
10070                                         bp->igu_base_sb = igu_sb_id;
10071                                 igu_sb_cnt++;
10072                         }
10073                 }
10074         }
10075
10076 #ifdef CONFIG_PCI_MSI
10077         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10078          * optional that number of CAM entries will not be equal to the value
10079          * advertised in PCI.
10080          * Driver should use the minimal value of both as the actual status
10081          * block count
10082          */
10083         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10084 #endif
10085
10086         if (igu_sb_cnt == 0) {
10087                 BNX2X_ERR("CAM configuration error\n");
10088                 return -EINVAL;
10089         }
10090
10091         return 0;
10092 }
10093
10094 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10095 {
10096         int cfg_size = 0, idx, port = BP_PORT(bp);
10097
10098         /* Aggregation of supported attributes of all external phys */
10099         bp->port.supported[0] = 0;
10100         bp->port.supported[1] = 0;
10101         switch (bp->link_params.num_phys) {
10102         case 1:
10103                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10104                 cfg_size = 1;
10105                 break;
10106         case 2:
10107                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10108                 cfg_size = 1;
10109                 break;
10110         case 3:
10111                 if (bp->link_params.multi_phy_config &
10112                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10113                         bp->port.supported[1] =
10114                                 bp->link_params.phy[EXT_PHY1].supported;
10115                         bp->port.supported[0] =
10116                                 bp->link_params.phy[EXT_PHY2].supported;
10117                 } else {
10118                         bp->port.supported[0] =
10119                                 bp->link_params.phy[EXT_PHY1].supported;
10120                         bp->port.supported[1] =
10121                                 bp->link_params.phy[EXT_PHY2].supported;
10122                 }
10123                 cfg_size = 2;
10124                 break;
10125         }
10126
10127         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10128                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10129                            SHMEM_RD(bp,
10130                            dev_info.port_hw_config[port].external_phy_config),
10131                            SHMEM_RD(bp,
10132                            dev_info.port_hw_config[port].external_phy_config2));
10133                         return;
10134         }
10135
10136         if (CHIP_IS_E3(bp))
10137                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10138         else {
10139                 switch (switch_cfg) {
10140                 case SWITCH_CFG_1G:
10141                         bp->port.phy_addr = REG_RD(
10142                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10143                         break;
10144                 case SWITCH_CFG_10G:
10145                         bp->port.phy_addr = REG_RD(
10146                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10147                         break;
10148                 default:
10149                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10150                                   bp->port.link_config[0]);
10151                         return;
10152                 }
10153         }
10154         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10155         /* mask what we support according to speed_cap_mask per configuration */
10156         for (idx = 0; idx < cfg_size; idx++) {
10157                 if (!(bp->link_params.speed_cap_mask[idx] &
10158                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10159                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10160
10161                 if (!(bp->link_params.speed_cap_mask[idx] &
10162                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10163                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10164
10165                 if (!(bp->link_params.speed_cap_mask[idx] &
10166                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10167                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10168
10169                 if (!(bp->link_params.speed_cap_mask[idx] &
10170                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10171                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10172
10173                 if (!(bp->link_params.speed_cap_mask[idx] &
10174                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10175                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10176                                                      SUPPORTED_1000baseT_Full);
10177
10178                 if (!(bp->link_params.speed_cap_mask[idx] &
10179                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10180                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10181
10182                 if (!(bp->link_params.speed_cap_mask[idx] &
10183                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10184                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10185
10186         }
10187
10188         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10189                        bp->port.supported[1]);
10190 }
10191
10192 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10193 {
10194         u32 link_config, idx, cfg_size = 0;
10195         bp->port.advertising[0] = 0;
10196         bp->port.advertising[1] = 0;
10197         switch (bp->link_params.num_phys) {
10198         case 1:
10199         case 2:
10200                 cfg_size = 1;
10201                 break;
10202         case 3:
10203                 cfg_size = 2;
10204                 break;
10205         }
10206         for (idx = 0; idx < cfg_size; idx++) {
10207                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10208                 link_config = bp->port.link_config[idx];
10209                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10210                 case PORT_FEATURE_LINK_SPEED_AUTO:
10211                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10212                                 bp->link_params.req_line_speed[idx] =
10213                                         SPEED_AUTO_NEG;
10214                                 bp->port.advertising[idx] |=
10215                                         bp->port.supported[idx];
10216                                 if (bp->link_params.phy[EXT_PHY1].type ==
10217                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10218                                         bp->port.advertising[idx] |=
10219                                         (SUPPORTED_100baseT_Half |
10220                                          SUPPORTED_100baseT_Full);
10221                         } else {
10222                                 /* force 10G, no AN */
10223                                 bp->link_params.req_line_speed[idx] =
10224                                         SPEED_10000;
10225                                 bp->port.advertising[idx] |=
10226                                         (ADVERTISED_10000baseT_Full |
10227                                          ADVERTISED_FIBRE);
10228                                 continue;
10229                         }
10230                         break;
10231
10232                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10233                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10234                                 bp->link_params.req_line_speed[idx] =
10235                                         SPEED_10;
10236                                 bp->port.advertising[idx] |=
10237                                         (ADVERTISED_10baseT_Full |
10238                                          ADVERTISED_TP);
10239                         } else {
10240                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10241                                             link_config,
10242                                     bp->link_params.speed_cap_mask[idx]);
10243                                 return;
10244                         }
10245                         break;
10246
10247                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10248                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10249                                 bp->link_params.req_line_speed[idx] =
10250                                         SPEED_10;
10251                                 bp->link_params.req_duplex[idx] =
10252                                         DUPLEX_HALF;
10253                                 bp->port.advertising[idx] |=
10254                                         (ADVERTISED_10baseT_Half |
10255                                          ADVERTISED_TP);
10256                         } else {
10257                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10258                                             link_config,
10259                                           bp->link_params.speed_cap_mask[idx]);
10260                                 return;
10261                         }
10262                         break;
10263
10264                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10265                         if (bp->port.supported[idx] &
10266                             SUPPORTED_100baseT_Full) {
10267                                 bp->link_params.req_line_speed[idx] =
10268                                         SPEED_100;
10269                                 bp->port.advertising[idx] |=
10270                                         (ADVERTISED_100baseT_Full |
10271                                          ADVERTISED_TP);
10272                         } else {
10273                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10274                                             link_config,
10275                                           bp->link_params.speed_cap_mask[idx]);
10276                                 return;
10277                         }
10278                         break;
10279
10280                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10281                         if (bp->port.supported[idx] &
10282                             SUPPORTED_100baseT_Half) {
10283                                 bp->link_params.req_line_speed[idx] =
10284                                                                 SPEED_100;
10285                                 bp->link_params.req_duplex[idx] =
10286                                                                 DUPLEX_HALF;
10287                                 bp->port.advertising[idx] |=
10288                                         (ADVERTISED_100baseT_Half |
10289                                          ADVERTISED_TP);
10290                         } else {
10291                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10292                                     link_config,
10293                                     bp->link_params.speed_cap_mask[idx]);
10294                                 return;
10295                         }
10296                         break;
10297
10298                 case PORT_FEATURE_LINK_SPEED_1G:
10299                         if (bp->port.supported[idx] &
10300                             SUPPORTED_1000baseT_Full) {
10301                                 bp->link_params.req_line_speed[idx] =
10302                                         SPEED_1000;
10303                                 bp->port.advertising[idx] |=
10304                                         (ADVERTISED_1000baseT_Full |
10305                                          ADVERTISED_TP);
10306                         } else {
10307                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10308                                     link_config,
10309                                     bp->link_params.speed_cap_mask[idx]);
10310                                 return;
10311                         }
10312                         break;
10313
10314                 case PORT_FEATURE_LINK_SPEED_2_5G:
10315                         if (bp->port.supported[idx] &
10316                             SUPPORTED_2500baseX_Full) {
10317                                 bp->link_params.req_line_speed[idx] =
10318                                         SPEED_2500;
10319                                 bp->port.advertising[idx] |=
10320                                         (ADVERTISED_2500baseX_Full |
10321                                                 ADVERTISED_TP);
10322                         } else {
10323                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10324                                     link_config,
10325                                     bp->link_params.speed_cap_mask[idx]);
10326                                 return;
10327                         }
10328                         break;
10329
10330                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10331                         if (bp->port.supported[idx] &
10332                             SUPPORTED_10000baseT_Full) {
10333                                 bp->link_params.req_line_speed[idx] =
10334                                         SPEED_10000;
10335                                 bp->port.advertising[idx] |=
10336                                         (ADVERTISED_10000baseT_Full |
10337                                                 ADVERTISED_FIBRE);
10338                         } else {
10339                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10340                                     link_config,
10341                                     bp->link_params.speed_cap_mask[idx]);
10342                                 return;
10343                         }
10344                         break;
10345                 case PORT_FEATURE_LINK_SPEED_20G:
10346                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10347
10348                         break;
10349                 default:
10350                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10351                                   link_config);
10352                                 bp->link_params.req_line_speed[idx] =
10353                                                         SPEED_AUTO_NEG;
10354                                 bp->port.advertising[idx] =
10355                                                 bp->port.supported[idx];
10356                         break;
10357                 }
10358
10359                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10360                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10361                 if (bp->link_params.req_flow_ctrl[idx] ==
10362                     BNX2X_FLOW_CTRL_AUTO) {
10363                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10364                                 bp->link_params.req_flow_ctrl[idx] =
10365                                                         BNX2X_FLOW_CTRL_NONE;
10366                         else
10367                                 bnx2x_set_requested_fc(bp);
10368                 }
10369
10370                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10371                                bp->link_params.req_line_speed[idx],
10372                                bp->link_params.req_duplex[idx],
10373                                bp->link_params.req_flow_ctrl[idx],
10374                                bp->port.advertising[idx]);
10375         }
10376 }
10377
10378 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10379 {
10380         mac_hi = cpu_to_be16(mac_hi);
10381         mac_lo = cpu_to_be32(mac_lo);
10382         memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10383         memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10384 }
10385
10386 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10387 {
10388         int port = BP_PORT(bp);
10389         u32 config;
10390         u32 ext_phy_type, ext_phy_config, eee_mode;
10391
10392         bp->link_params.bp = bp;
10393         bp->link_params.port = port;
10394
10395         bp->link_params.lane_config =
10396                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10397
10398         bp->link_params.speed_cap_mask[0] =
10399                 SHMEM_RD(bp,
10400                          dev_info.port_hw_config[port].speed_capability_mask);
10401         bp->link_params.speed_cap_mask[1] =
10402                 SHMEM_RD(bp,
10403                          dev_info.port_hw_config[port].speed_capability_mask2);
10404         bp->port.link_config[0] =
10405                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10406
10407         bp->port.link_config[1] =
10408                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10409
10410         bp->link_params.multi_phy_config =
10411                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10412         /* If the device is capable of WoL, set the default state according
10413          * to the HW
10414          */
10415         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10416         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10417                    (config & PORT_FEATURE_WOL_ENABLED));
10418
10419         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10420                        bp->link_params.lane_config,
10421                        bp->link_params.speed_cap_mask[0],
10422                        bp->port.link_config[0]);
10423
10424         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10425                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10426         bnx2x_phy_probe(&bp->link_params);
10427         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10428
10429         bnx2x_link_settings_requested(bp);
10430
10431         /*
10432          * If connected directly, work with the internal PHY, otherwise, work
10433          * with the external PHY
10434          */
10435         ext_phy_config =
10436                 SHMEM_RD(bp,
10437                          dev_info.port_hw_config[port].external_phy_config);
10438         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10439         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10440                 bp->mdio.prtad = bp->port.phy_addr;
10441
10442         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10443                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10444                 bp->mdio.prtad =
10445                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10446
10447         /* Configure link feature according to nvram value */
10448         eee_mode = (((SHMEM_RD(bp, dev_info.
10449                       port_feature_config[port].eee_power_mode)) &
10450                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10451                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10452         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10453                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10454                                            EEE_MODE_ENABLE_LPI |
10455                                            EEE_MODE_OUTPUT_TIME;
10456         } else {
10457                 bp->link_params.eee_mode = 0;
10458         }
10459 }
10460
10461 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10462 {
10463         u32 no_flags = NO_ISCSI_FLAG;
10464         int port = BP_PORT(bp);
10465         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10466                                 drv_lic_key[port].max_iscsi_conn);
10467
10468         if (!CNIC_SUPPORT(bp)) {
10469                 bp->flags |= no_flags;
10470                 return;
10471         }
10472
10473         /* Get the number of maximum allowed iSCSI connections */
10474         bp->cnic_eth_dev.max_iscsi_conn =
10475                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10476                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10477
10478         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10479                        bp->cnic_eth_dev.max_iscsi_conn);
10480
10481         /*
10482          * If maximum allowed number of connections is zero -
10483          * disable the feature.
10484          */
10485         if (!bp->cnic_eth_dev.max_iscsi_conn)
10486                 bp->flags |= no_flags;
10487
10488 }
10489
10490 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10491 {
10492         /* Port info */
10493         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10494                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10495         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10496                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10497
10498         /* Node info */
10499         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10500                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10501         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10502                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10503 }
10504 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10505 {
10506         int port = BP_PORT(bp);
10507         int func = BP_ABS_FUNC(bp);
10508         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10509                                 drv_lic_key[port].max_fcoe_conn);
10510
10511         if (!CNIC_SUPPORT(bp)) {
10512                 bp->flags |= NO_FCOE_FLAG;
10513                 return;
10514         }
10515
10516         /* Get the number of maximum allowed FCoE connections */
10517         bp->cnic_eth_dev.max_fcoe_conn =
10518                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10519                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10520
10521         /* Read the WWN: */
10522         if (!IS_MF(bp)) {
10523                 /* Port info */
10524                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10525                         SHMEM_RD(bp,
10526                                 dev_info.port_hw_config[port].
10527                                  fcoe_wwn_port_name_upper);
10528                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10529                         SHMEM_RD(bp,
10530                                 dev_info.port_hw_config[port].
10531                                  fcoe_wwn_port_name_lower);
10532
10533                 /* Node info */
10534                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10535                         SHMEM_RD(bp,
10536                                 dev_info.port_hw_config[port].
10537                                  fcoe_wwn_node_name_upper);
10538                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10539                         SHMEM_RD(bp,
10540                                 dev_info.port_hw_config[port].
10541                                  fcoe_wwn_node_name_lower);
10542         } else if (!IS_MF_SD(bp)) {
10543                 /*
10544                  * Read the WWN info only if the FCoE feature is enabled for
10545                  * this function.
10546                  */
10547                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10548                         bnx2x_get_ext_wwn_info(bp, func);
10549
10550         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10551                 bnx2x_get_ext_wwn_info(bp, func);
10552         }
10553
10554         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10555
10556         /*
10557          * If maximum allowed number of connections is zero -
10558          * disable the feature.
10559          */
10560         if (!bp->cnic_eth_dev.max_fcoe_conn)
10561                 bp->flags |= NO_FCOE_FLAG;
10562 }
10563
10564 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10565 {
10566         /*
10567          * iSCSI may be dynamically disabled but reading
10568          * info here we will decrease memory usage by driver
10569          * if the feature is disabled for good
10570          */
10571         bnx2x_get_iscsi_info(bp);
10572         bnx2x_get_fcoe_info(bp);
10573 }
10574
10575 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10576 {
10577         u32 val, val2;
10578         int func = BP_ABS_FUNC(bp);
10579         int port = BP_PORT(bp);
10580         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10581         u8 *fip_mac = bp->fip_mac;
10582
10583         if (IS_MF(bp)) {
10584                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10585                  * FCoE MAC then the appropriate feature should be disabled.
10586                  * In non SD mode features configuration comes from struct
10587                  * func_ext_config.
10588                  */
10589                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10590                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10591                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10592                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10593                                                  iscsi_mac_addr_upper);
10594                                 val = MF_CFG_RD(bp, func_ext_config[func].
10595                                                 iscsi_mac_addr_lower);
10596                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10597                                 BNX2X_DEV_INFO
10598                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10599                         } else {
10600                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10601                         }
10602
10603                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10604                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
10605                                                  fcoe_mac_addr_upper);
10606                                 val = MF_CFG_RD(bp, func_ext_config[func].
10607                                                 fcoe_mac_addr_lower);
10608                                 bnx2x_set_mac_buf(fip_mac, val, val2);
10609                                 BNX2X_DEV_INFO
10610                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
10611                         } else {
10612                                 bp->flags |= NO_FCOE_FLAG;
10613                         }
10614
10615                         bp->mf_ext_config = cfg;
10616
10617                 } else { /* SD MODE */
10618                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10619                                 /* use primary mac as iscsi mac */
10620                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10621
10622                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10623                                 BNX2X_DEV_INFO
10624                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
10625                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10626                                 /* use primary mac as fip mac */
10627                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10628                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
10629                                 BNX2X_DEV_INFO
10630                                         ("Read FIP MAC: %pM\n", fip_mac);
10631                         }
10632                 }
10633
10634                 if (IS_MF_STORAGE_SD(bp))
10635                         /* Zero primary MAC configuration */
10636                         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10637
10638                 if (IS_MF_FCOE_AFEX(bp))
10639                         /* use FIP MAC as primary MAC */
10640                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10641
10642         } else {
10643                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10644                                 iscsi_mac_upper);
10645                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10646                                iscsi_mac_lower);
10647                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10648
10649                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10650                                 fcoe_fip_mac_upper);
10651                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10652                                fcoe_fip_mac_lower);
10653                 bnx2x_set_mac_buf(fip_mac, val, val2);
10654         }
10655
10656         /* Disable iSCSI OOO if MAC configuration is invalid. */
10657         if (!is_valid_ether_addr(iscsi_mac)) {
10658                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10659                 memset(iscsi_mac, 0, ETH_ALEN);
10660         }
10661
10662         /* Disable FCoE if MAC configuration is invalid. */
10663         if (!is_valid_ether_addr(fip_mac)) {
10664                 bp->flags |= NO_FCOE_FLAG;
10665                 memset(bp->fip_mac, 0, ETH_ALEN);
10666         }
10667 }
10668
10669 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10670 {
10671         u32 val, val2;
10672         int func = BP_ABS_FUNC(bp);
10673         int port = BP_PORT(bp);
10674
10675         /* Zero primary MAC configuration */
10676         memset(bp->dev->dev_addr, 0, ETH_ALEN);
10677
10678         if (BP_NOMCP(bp)) {
10679                 BNX2X_ERROR("warning: random MAC workaround active\n");
10680                 eth_hw_addr_random(bp->dev);
10681         } else if (IS_MF(bp)) {
10682                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10683                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10684                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10685                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10686                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10687
10688                 if (CNIC_SUPPORT(bp))
10689                         bnx2x_get_cnic_mac_hwinfo(bp);
10690         } else {
10691                 /* in SF read MACs from port configuration */
10692                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10693                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10694                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10695
10696                 if (CNIC_SUPPORT(bp))
10697                         bnx2x_get_cnic_mac_hwinfo(bp);
10698         }
10699
10700         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10701         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10702
10703         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10704                 dev_err(&bp->pdev->dev,
10705                         "bad Ethernet MAC address configuration: %pM\n"
10706                         "change it manually before bringing up the appropriate network interface\n",
10707                         bp->dev->dev_addr);
10708 }
10709
10710 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10711 {
10712         int tmp;
10713         u32 cfg;
10714
10715         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10716                 /* Take function: tmp = func */
10717                 tmp = BP_ABS_FUNC(bp);
10718                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10719                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10720         } else {
10721                 /* Take port: tmp = port */
10722                 tmp = BP_PORT(bp);
10723                 cfg = SHMEM_RD(bp,
10724                                dev_info.port_hw_config[tmp].generic_features);
10725                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10726         }
10727         return cfg;
10728 }
10729
10730 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10731 {
10732         int /*abs*/func = BP_ABS_FUNC(bp);
10733         int vn;
10734         u32 val = 0;
10735         int rc = 0;
10736
10737         bnx2x_get_common_hwinfo(bp);
10738
10739         /*
10740          * initialize IGU parameters
10741          */
10742         if (CHIP_IS_E1x(bp)) {
10743                 bp->common.int_block = INT_BLOCK_HC;
10744
10745                 bp->igu_dsb_id = DEF_SB_IGU_ID;
10746                 bp->igu_base_sb = 0;
10747         } else {
10748                 bp->common.int_block = INT_BLOCK_IGU;
10749
10750                 /* do not allow device reset during IGU info preocessing */
10751                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10752
10753                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10754
10755                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10756                         int tout = 5000;
10757
10758                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
10759
10760                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10761                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10762                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10763
10764                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10765                                 tout--;
10766                                 usleep_range(1000, 1000);
10767                         }
10768
10769                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10770                                 dev_err(&bp->pdev->dev,
10771                                         "FORCING Normal Mode failed!!!\n");
10772                                 bnx2x_release_hw_lock(bp,
10773                                                       HW_LOCK_RESOURCE_RESET);
10774                                 return -EPERM;
10775                         }
10776                 }
10777
10778                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10779                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10780                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10781                 } else
10782                         BNX2X_DEV_INFO("IGU Normal Mode\n");
10783
10784                 rc = bnx2x_get_igu_cam_info(bp);
10785                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10786                 if (rc)
10787                         return rc;
10788         }
10789
10790         /*
10791          * set base FW non-default (fast path) status block id, this value is
10792          * used to initialize the fw_sb_id saved on the fp/queue structure to
10793          * determine the id used by the FW.
10794          */
10795         if (CHIP_IS_E1x(bp))
10796                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10797         else /*
10798               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10799               * the same queue are indicated on the same IGU SB). So we prefer
10800               * FW and IGU SBs to be the same value.
10801               */
10802                 bp->base_fw_ndsb = bp->igu_base_sb;
10803
10804         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
10805                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10806                        bp->igu_sb_cnt, bp->base_fw_ndsb);
10807
10808         /*
10809          * Initialize MF configuration
10810          */
10811
10812         bp->mf_ov = 0;
10813         bp->mf_mode = 0;
10814         vn = BP_VN(bp);
10815
10816         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10817                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10818                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
10819                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10820
10821                 if (SHMEM2_HAS(bp, mf_cfg_addr))
10822                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10823                 else
10824                         bp->common.mf_cfg_base = bp->common.shmem_base +
10825                                 offsetof(struct shmem_region, func_mb) +
10826                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10827                 /*
10828                  * get mf configuration:
10829                  * 1. existence of MF configuration
10830                  * 2. MAC address must be legal (check only upper bytes)
10831                  *    for  Switch-Independent mode;
10832                  *    OVLAN must be legal for Switch-Dependent mode
10833                  * 3. SF_MODE configures specific MF mode
10834                  */
10835                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10836                         /* get mf configuration */
10837                         val = SHMEM_RD(bp,
10838                                        dev_info.shared_feature_config.config);
10839                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10840
10841                         switch (val) {
10842                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10843                                 val = MF_CFG_RD(bp, func_mf_config[func].
10844                                                 mac_upper);
10845                                 /* check for legal mac (upper bytes)*/
10846                                 if (val != 0xffff) {
10847                                         bp->mf_mode = MULTI_FUNCTION_SI;
10848                                         bp->mf_config[vn] = MF_CFG_RD(bp,
10849                                                    func_mf_config[func].config);
10850                                 } else
10851                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
10852                                 break;
10853                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10854                                 if ((!CHIP_IS_E1x(bp)) &&
10855                                     (MF_CFG_RD(bp, func_mf_config[func].
10856                                                mac_upper) != 0xffff) &&
10857                                     (SHMEM2_HAS(bp,
10858                                                 afex_driver_support))) {
10859                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
10860                                         bp->mf_config[vn] = MF_CFG_RD(bp,
10861                                                 func_mf_config[func].config);
10862                                 } else {
10863                                         BNX2X_DEV_INFO("can not configure afex mode\n");
10864                                 }
10865                                 break;
10866                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10867                                 /* get OV configuration */
10868                                 val = MF_CFG_RD(bp,
10869                                         func_mf_config[FUNC_0].e1hov_tag);
10870                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10871
10872                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10873                                         bp->mf_mode = MULTI_FUNCTION_SD;
10874                                         bp->mf_config[vn] = MF_CFG_RD(bp,
10875                                                 func_mf_config[func].config);
10876                                 } else
10877                                         BNX2X_DEV_INFO("illegal OV for SD\n");
10878                                 break;
10879                         default:
10880                                 /* Unknown configuration: reset mf_config */
10881                                 bp->mf_config[vn] = 0;
10882                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10883                         }
10884                 }
10885
10886                 BNX2X_DEV_INFO("%s function mode\n",
10887                                IS_MF(bp) ? "multi" : "single");
10888
10889                 switch (bp->mf_mode) {
10890                 case MULTI_FUNCTION_SD:
10891                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10892                               FUNC_MF_CFG_E1HOV_TAG_MASK;
10893                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10894                                 bp->mf_ov = val;
10895                                 bp->path_has_ovlan = true;
10896
10897                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10898                                                func, bp->mf_ov, bp->mf_ov);
10899                         } else {
10900                                 dev_err(&bp->pdev->dev,
10901                                         "No valid MF OV for func %d, aborting\n",
10902                                         func);
10903                                 return -EPERM;
10904                         }
10905                         break;
10906                 case MULTI_FUNCTION_AFEX:
10907                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10908                         break;
10909                 case MULTI_FUNCTION_SI:
10910                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10911                                        func);
10912                         break;
10913                 default:
10914                         if (vn) {
10915                                 dev_err(&bp->pdev->dev,
10916                                         "VN %d is in a single function mode, aborting\n",
10917                                         vn);
10918                                 return -EPERM;
10919                         }
10920                         break;
10921                 }
10922
10923                 /* check if other port on the path needs ovlan:
10924                  * Since MF configuration is shared between ports
10925                  * Possible mixed modes are only
10926                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10927                  */
10928                 if (CHIP_MODE_IS_4_PORT(bp) &&
10929                     !bp->path_has_ovlan &&
10930                     !IS_MF(bp) &&
10931                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10932                         u8 other_port = !BP_PORT(bp);
10933                         u8 other_func = BP_PATH(bp) + 2*other_port;
10934                         val = MF_CFG_RD(bp,
10935                                         func_mf_config[other_func].e1hov_tag);
10936                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10937                                 bp->path_has_ovlan = true;
10938                 }
10939         }
10940
10941         /* adjust igu_sb_cnt to MF for E1x */
10942         if (CHIP_IS_E1x(bp) && IS_MF(bp))
10943                 bp->igu_sb_cnt /= E1HVN_MAX;
10944
10945         /* port info */
10946         bnx2x_get_port_hwinfo(bp);
10947
10948         /* Get MAC addresses */
10949         bnx2x_get_mac_hwinfo(bp);
10950
10951         bnx2x_get_cnic_info(bp);
10952
10953         return rc;
10954 }
10955
10956 static void bnx2x_read_fwinfo(struct bnx2x *bp)
10957 {
10958         int cnt, i, block_end, rodi;
10959         char vpd_start[BNX2X_VPD_LEN+1];
10960         char str_id_reg[VENDOR_ID_LEN+1];
10961         char str_id_cap[VENDOR_ID_LEN+1];
10962         char *vpd_data;
10963         char *vpd_extended_data = NULL;
10964         u8 len;
10965
10966         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10967         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10968
10969         if (cnt < BNX2X_VPD_LEN)
10970                 goto out_not_found;
10971
10972         /* VPD RO tag should be first tag after identifier string, hence
10973          * we should be able to find it in first BNX2X_VPD_LEN chars
10974          */
10975         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10976                              PCI_VPD_LRDT_RO_DATA);
10977         if (i < 0)
10978                 goto out_not_found;
10979
10980         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10981                     pci_vpd_lrdt_size(&vpd_start[i]);
10982
10983         i += PCI_VPD_LRDT_TAG_SIZE;
10984
10985         if (block_end > BNX2X_VPD_LEN) {
10986                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10987                 if (vpd_extended_data  == NULL)
10988                         goto out_not_found;
10989
10990                 /* read rest of vpd image into vpd_extended_data */
10991                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10992                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10993                                    block_end - BNX2X_VPD_LEN,
10994                                    vpd_extended_data + BNX2X_VPD_LEN);
10995                 if (cnt < (block_end - BNX2X_VPD_LEN))
10996                         goto out_not_found;
10997                 vpd_data = vpd_extended_data;
10998         } else
10999                 vpd_data = vpd_start;
11000
11001         /* now vpd_data holds full vpd content in both cases */
11002
11003         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11004                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11005         if (rodi < 0)
11006                 goto out_not_found;
11007
11008         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11009
11010         if (len != VENDOR_ID_LEN)
11011                 goto out_not_found;
11012
11013         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11014
11015         /* vendor specific info */
11016         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11017         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11018         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11019             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11020
11021                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11022                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11023                 if (rodi >= 0) {
11024                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11025
11026                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11027
11028                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11029                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11030                                 bp->fw_ver[len] = ' ';
11031                         }
11032                 }
11033                 kfree(vpd_extended_data);
11034                 return;
11035         }
11036 out_not_found:
11037         kfree(vpd_extended_data);
11038         return;
11039 }
11040
11041 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11042 {
11043         u32 flags = 0;
11044
11045         if (CHIP_REV_IS_FPGA(bp))
11046                 SET_FLAGS(flags, MODE_FPGA);
11047         else if (CHIP_REV_IS_EMUL(bp))
11048                 SET_FLAGS(flags, MODE_EMUL);
11049         else
11050                 SET_FLAGS(flags, MODE_ASIC);
11051
11052         if (CHIP_MODE_IS_4_PORT(bp))
11053                 SET_FLAGS(flags, MODE_PORT4);
11054         else
11055                 SET_FLAGS(flags, MODE_PORT2);
11056
11057         if (CHIP_IS_E2(bp))
11058                 SET_FLAGS(flags, MODE_E2);
11059         else if (CHIP_IS_E3(bp)) {
11060                 SET_FLAGS(flags, MODE_E3);
11061                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11062                         SET_FLAGS(flags, MODE_E3_A0);
11063                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11064                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11065         }
11066
11067         if (IS_MF(bp)) {
11068                 SET_FLAGS(flags, MODE_MF);
11069                 switch (bp->mf_mode) {
11070                 case MULTI_FUNCTION_SD:
11071                         SET_FLAGS(flags, MODE_MF_SD);
11072                         break;
11073                 case MULTI_FUNCTION_SI:
11074                         SET_FLAGS(flags, MODE_MF_SI);
11075                         break;
11076                 case MULTI_FUNCTION_AFEX:
11077                         SET_FLAGS(flags, MODE_MF_AFEX);
11078                         break;
11079                 }
11080         } else
11081                 SET_FLAGS(flags, MODE_SF);
11082
11083 #if defined(__LITTLE_ENDIAN)
11084         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11085 #else /*(__BIG_ENDIAN)*/
11086         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11087 #endif
11088         INIT_MODE_FLAGS(bp) = flags;
11089 }
11090
11091 static int bnx2x_init_bp(struct bnx2x *bp)
11092 {
11093         int func;
11094         int rc;
11095
11096         mutex_init(&bp->port.phy_mutex);
11097         mutex_init(&bp->fw_mb_mutex);
11098         spin_lock_init(&bp->stats_lock);
11099
11100
11101         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11102         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11103         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11104         if (IS_PF(bp)) {
11105                 rc = bnx2x_get_hwinfo(bp);
11106                 if (rc)
11107                         return rc;
11108         } else {
11109                 random_ether_addr(bp->dev->dev_addr);
11110         }
11111
11112         bnx2x_set_modes_bitmap(bp);
11113
11114         rc = bnx2x_alloc_mem_bp(bp);
11115         if (rc)
11116                 return rc;
11117
11118         bnx2x_read_fwinfo(bp);
11119
11120         func = BP_FUNC(bp);
11121
11122         /* need to reset chip if undi was active */
11123         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11124                 /* init fw_seq */
11125                 bp->fw_seq =
11126                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11127                                                         DRV_MSG_SEQ_NUMBER_MASK;
11128                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11129
11130                 bnx2x_prev_unload(bp);
11131         }
11132
11133
11134         if (CHIP_REV_IS_FPGA(bp))
11135                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11136
11137         if (BP_NOMCP(bp) && (func == 0))
11138                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11139
11140         bp->disable_tpa = disable_tpa;
11141         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11142
11143         /* Set TPA flags */
11144         if (bp->disable_tpa) {
11145                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11146                 bp->dev->features &= ~NETIF_F_LRO;
11147         } else {
11148                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11149                 bp->dev->features |= NETIF_F_LRO;
11150         }
11151
11152         if (CHIP_IS_E1(bp))
11153                 bp->dropless_fc = 0;
11154         else
11155                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11156
11157         bp->mrrs = mrrs;
11158
11159         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11160         if (IS_VF(bp))
11161                 bp->rx_ring_size = MAX_RX_AVAIL;
11162
11163         /* make sure that the numbers are in the right granularity */
11164         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11165         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11166
11167         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11168
11169         init_timer(&bp->timer);
11170         bp->timer.expires = jiffies + bp->current_interval;
11171         bp->timer.data = (unsigned long) bp;
11172         bp->timer.function = bnx2x_timer;
11173
11174         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11175             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11176             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11177             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11178                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11179                 bnx2x_dcbx_init_params(bp);
11180         } else {
11181                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11182         }
11183
11184         if (CHIP_IS_E1x(bp))
11185                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11186         else
11187                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11188
11189         /* multiple tx priority */
11190         if (IS_VF(bp))
11191                 bp->max_cos = 1;
11192         else if (CHIP_IS_E1x(bp))
11193                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11194         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11195                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11196         else if (CHIP_IS_E3B0(bp))
11197                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11198         else
11199                 BNX2X_ERR("unknown chip %x revision %x\n",
11200                           CHIP_NUM(bp), CHIP_REV(bp));
11201         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11202
11203         /* We need at least one default status block for slow-path events,
11204          * second status block for the L2 queue, and a third status block for
11205          * CNIC if supproted.
11206          */
11207         if (CNIC_SUPPORT(bp))
11208                 bp->min_msix_vec_cnt = 3;
11209         else
11210                 bp->min_msix_vec_cnt = 2;
11211         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11212
11213         return rc;
11214 }
11215
11216
11217 /****************************************************************************
11218 * General service functions
11219 ****************************************************************************/
11220
11221 /*
11222  * net_device service functions
11223  */
11224
11225 /* called with rtnl_lock */
11226 static int bnx2x_open(struct net_device *dev)
11227 {
11228         struct bnx2x *bp = netdev_priv(dev);
11229         bool global = false;
11230         int other_engine = BP_PATH(bp) ? 0 : 1;
11231         bool other_load_status, load_status;
11232
11233         bp->stats_init = true;
11234
11235         netif_carrier_off(dev);
11236
11237         bnx2x_set_power_state(bp, PCI_D0);
11238
11239         other_load_status = bnx2x_get_load_status(bp, other_engine);
11240         load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11241
11242         /*
11243          * If parity had happen during the unload, then attentions
11244          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11245          * want the first function loaded on the current engine to
11246          * complete the recovery.
11247          */
11248         if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11249             bnx2x_chk_parity_attn(bp, &global, true))
11250                 do {
11251                         /*
11252                          * If there are attentions and they are in a global
11253                          * blocks, set the GLOBAL_RESET bit regardless whether
11254                          * it will be this function that will complete the
11255                          * recovery or not.
11256                          */
11257                         if (global)
11258                                 bnx2x_set_reset_global(bp);
11259
11260                         /*
11261                          * Only the first function on the current engine should
11262                          * try to recover in open. In case of attentions in
11263                          * global blocks only the first in the chip should try
11264                          * to recover.
11265                          */
11266                         if ((!load_status &&
11267                              (!global || !other_load_status)) &&
11268                             bnx2x_trylock_leader_lock(bp) &&
11269                             !bnx2x_leader_reset(bp)) {
11270                                 netdev_info(bp->dev, "Recovered in open\n");
11271                                 break;
11272                         }
11273
11274                         /* recovery has failed... */
11275                         bnx2x_set_power_state(bp, PCI_D3hot);
11276                         bp->recovery_state = BNX2X_RECOVERY_FAILED;
11277
11278                         BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11279                                   "If you still see this message after a few retries then power cycle is required.\n");
11280
11281                         return -EAGAIN;
11282                 } while (0);
11283
11284         bp->recovery_state = BNX2X_RECOVERY_DONE;
11285         return bnx2x_nic_load(bp, LOAD_OPEN);
11286 }
11287
11288 /* called with rtnl_lock */
11289 static int bnx2x_close(struct net_device *dev)
11290 {
11291         struct bnx2x *bp = netdev_priv(dev);
11292
11293         /* Unload the driver, release IRQs */
11294         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11295
11296         /* Power off */
11297         bnx2x_set_power_state(bp, PCI_D3hot);
11298
11299         return 0;
11300 }
11301
11302 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11303                                       struct bnx2x_mcast_ramrod_params *p)
11304 {
11305         int mc_count = netdev_mc_count(bp->dev);
11306         struct bnx2x_mcast_list_elem *mc_mac =
11307                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11308         struct netdev_hw_addr *ha;
11309
11310         if (!mc_mac)
11311                 return -ENOMEM;
11312
11313         INIT_LIST_HEAD(&p->mcast_list);
11314
11315         netdev_for_each_mc_addr(ha, bp->dev) {
11316                 mc_mac->mac = bnx2x_mc_addr(ha);
11317                 list_add_tail(&mc_mac->link, &p->mcast_list);
11318                 mc_mac++;
11319         }
11320
11321         p->mcast_list_len = mc_count;
11322
11323         return 0;
11324 }
11325
11326 static void bnx2x_free_mcast_macs_list(
11327         struct bnx2x_mcast_ramrod_params *p)
11328 {
11329         struct bnx2x_mcast_list_elem *mc_mac =
11330                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11331                                  link);
11332
11333         WARN_ON(!mc_mac);
11334         kfree(mc_mac);
11335 }
11336
11337 /**
11338  * bnx2x_set_uc_list - configure a new unicast MACs list.
11339  *
11340  * @bp: driver handle
11341  *
11342  * We will use zero (0) as a MAC type for these MACs.
11343  */
11344 static int bnx2x_set_uc_list(struct bnx2x *bp)
11345 {
11346         int rc;
11347         struct net_device *dev = bp->dev;
11348         struct netdev_hw_addr *ha;
11349         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11350         unsigned long ramrod_flags = 0;
11351
11352         /* First schedule a cleanup up of old configuration */
11353         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11354         if (rc < 0) {
11355                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11356                 return rc;
11357         }
11358
11359         netdev_for_each_uc_addr(ha, dev) {
11360                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11361                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11362                 if (rc == -EEXIST) {
11363                         DP(BNX2X_MSG_SP,
11364                            "Failed to schedule ADD operations: %d\n", rc);
11365                         /* do not treat adding same MAC as error */
11366                         rc = 0;
11367
11368                 } else if (rc < 0) {
11369
11370                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11371                                   rc);
11372                         return rc;
11373                 }
11374         }
11375
11376         /* Execute the pending commands */
11377         __set_bit(RAMROD_CONT, &ramrod_flags);
11378         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11379                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11380 }
11381
11382 static int bnx2x_set_mc_list(struct bnx2x *bp)
11383 {
11384         struct net_device *dev = bp->dev;
11385         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11386         int rc = 0;
11387
11388         rparam.mcast_obj = &bp->mcast_obj;
11389
11390         /* first, clear all configured multicast MACs */
11391         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11392         if (rc < 0) {
11393                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11394                 return rc;
11395         }
11396
11397         /* then, configure a new MACs list */
11398         if (netdev_mc_count(dev)) {
11399                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11400                 if (rc) {
11401                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11402                                   rc);
11403                         return rc;
11404                 }
11405
11406                 /* Now add the new MACs */
11407                 rc = bnx2x_config_mcast(bp, &rparam,
11408                                         BNX2X_MCAST_CMD_ADD);
11409                 if (rc < 0)
11410                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11411                                   rc);
11412
11413                 bnx2x_free_mcast_macs_list(&rparam);
11414         }
11415
11416         return rc;
11417 }
11418
11419
11420 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11421 void bnx2x_set_rx_mode(struct net_device *dev)
11422 {
11423         struct bnx2x *bp = netdev_priv(dev);
11424         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11425
11426         if (bp->state != BNX2X_STATE_OPEN) {
11427                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11428                 return;
11429         }
11430
11431         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11432
11433         if (dev->flags & IFF_PROMISC)
11434                 rx_mode = BNX2X_RX_MODE_PROMISC;
11435         else if ((dev->flags & IFF_ALLMULTI) ||
11436                  ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11437                   CHIP_IS_E1(bp)))
11438                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11439         else {
11440                 /* some multicasts */
11441                 if (bnx2x_set_mc_list(bp) < 0)
11442                         rx_mode = BNX2X_RX_MODE_ALLMULTI;
11443
11444                 if (bnx2x_set_uc_list(bp) < 0)
11445                         rx_mode = BNX2X_RX_MODE_PROMISC;
11446         }
11447
11448         bp->rx_mode = rx_mode;
11449         /* handle ISCSI SD mode */
11450         if (IS_MF_ISCSI_SD(bp))
11451                 bp->rx_mode = BNX2X_RX_MODE_NONE;
11452
11453         /* Schedule the rx_mode command */
11454         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11455                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11456                 return;
11457         }
11458
11459         bnx2x_set_storm_rx_mode(bp);
11460 }
11461
11462 /* called with rtnl_lock */
11463 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11464                            int devad, u16 addr)
11465 {
11466         struct bnx2x *bp = netdev_priv(netdev);
11467         u16 value;
11468         int rc;
11469
11470         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11471            prtad, devad, addr);
11472
11473         /* The HW expects different devad if CL22 is used */
11474         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11475
11476         bnx2x_acquire_phy_lock(bp);
11477         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11478         bnx2x_release_phy_lock(bp);
11479         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11480
11481         if (!rc)
11482                 rc = value;
11483         return rc;
11484 }
11485
11486 /* called with rtnl_lock */
11487 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11488                             u16 addr, u16 value)
11489 {
11490         struct bnx2x *bp = netdev_priv(netdev);
11491         int rc;
11492
11493         DP(NETIF_MSG_LINK,
11494            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11495            prtad, devad, addr, value);
11496
11497         /* The HW expects different devad if CL22 is used */
11498         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11499
11500         bnx2x_acquire_phy_lock(bp);
11501         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11502         bnx2x_release_phy_lock(bp);
11503         return rc;
11504 }
11505
11506 /* called with rtnl_lock */
11507 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11508 {
11509         struct bnx2x *bp = netdev_priv(dev);
11510         struct mii_ioctl_data *mdio = if_mii(ifr);
11511
11512         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11513            mdio->phy_id, mdio->reg_num, mdio->val_in);
11514
11515         if (!netif_running(dev))
11516                 return -EAGAIN;
11517
11518         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11519 }
11520
11521 #ifdef CONFIG_NET_POLL_CONTROLLER
11522 static void poll_bnx2x(struct net_device *dev)
11523 {
11524         struct bnx2x *bp = netdev_priv(dev);
11525         int i;
11526
11527         for_each_eth_queue(bp, i) {
11528                 struct bnx2x_fastpath *fp = &bp->fp[i];
11529                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11530         }
11531 }
11532 #endif
11533
11534 static int bnx2x_validate_addr(struct net_device *dev)
11535 {
11536         struct bnx2x *bp = netdev_priv(dev);
11537
11538         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11539                 BNX2X_ERR("Non-valid Ethernet address\n");
11540                 return -EADDRNOTAVAIL;
11541         }
11542         return 0;
11543 }
11544
11545 static const struct net_device_ops bnx2x_netdev_ops = {
11546         .ndo_open               = bnx2x_open,
11547         .ndo_stop               = bnx2x_close,
11548         .ndo_start_xmit         = bnx2x_start_xmit,
11549         .ndo_select_queue       = bnx2x_select_queue,
11550         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
11551         .ndo_set_mac_address    = bnx2x_change_mac_addr,
11552         .ndo_validate_addr      = bnx2x_validate_addr,
11553         .ndo_do_ioctl           = bnx2x_ioctl,
11554         .ndo_change_mtu         = bnx2x_change_mtu,
11555         .ndo_fix_features       = bnx2x_fix_features,
11556         .ndo_set_features       = bnx2x_set_features,
11557         .ndo_tx_timeout         = bnx2x_tx_timeout,
11558 #ifdef CONFIG_NET_POLL_CONTROLLER
11559         .ndo_poll_controller    = poll_bnx2x,
11560 #endif
11561         .ndo_setup_tc           = bnx2x_setup_tc,
11562
11563 #ifdef NETDEV_FCOE_WWNN
11564         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
11565 #endif
11566 };
11567
11568 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11569 {
11570         struct device *dev = &bp->pdev->dev;
11571
11572         if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11573                 bp->flags |= USING_DAC_FLAG;
11574                 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11575                         dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11576                         return -EIO;
11577                 }
11578         } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11579                 dev_err(dev, "System does not support DMA, aborting\n");
11580                 return -EIO;
11581         }
11582
11583         return 0;
11584 }
11585
11586 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11587                           struct net_device *dev, unsigned long board_type)
11588 {
11589         int rc;
11590         u32 pci_cfg_dword;
11591         bool chip_is_e1x = (board_type == BCM57710 ||
11592                             board_type == BCM57711 ||
11593                             board_type == BCM57711E);
11594
11595         SET_NETDEV_DEV(dev, &pdev->dev);
11596
11597         bp->dev = dev;
11598         bp->pdev = pdev;
11599
11600         rc = pci_enable_device(pdev);
11601         if (rc) {
11602                 dev_err(&bp->pdev->dev,
11603                         "Cannot enable PCI device, aborting\n");
11604                 goto err_out;
11605         }
11606
11607         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11608                 dev_err(&bp->pdev->dev,
11609                         "Cannot find PCI device base address, aborting\n");
11610                 rc = -ENODEV;
11611                 goto err_out_disable;
11612         }
11613
11614         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11615                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11616                 rc = -ENODEV;
11617                 goto err_out_disable;
11618         }
11619
11620         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11621         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11622             PCICFG_REVESION_ID_ERROR_VAL) {
11623                 pr_err("PCI device error, probably due to fan failure, aborting\n");
11624                 rc = -ENODEV;
11625                 goto err_out_disable;
11626         }
11627
11628         if (atomic_read(&pdev->enable_cnt) == 1) {
11629                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11630                 if (rc) {
11631                         dev_err(&bp->pdev->dev,
11632                                 "Cannot obtain PCI resources, aborting\n");
11633                         goto err_out_disable;
11634                 }
11635
11636                 pci_set_master(pdev);
11637                 pci_save_state(pdev);
11638         }
11639
11640         if (IS_PF(bp)) {
11641                 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11642                 if (bp->pm_cap == 0) {
11643                         dev_err(&bp->pdev->dev,
11644                                 "Cannot find power management capability, aborting\n");
11645                         rc = -EIO;
11646                         goto err_out_release;
11647                 }
11648         }
11649
11650         if (!pci_is_pcie(pdev)) {
11651                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11652                 rc = -EIO;
11653                 goto err_out_release;
11654         }
11655
11656         rc = bnx2x_set_coherency_mask(bp);
11657         if (rc)
11658                 goto err_out_release;
11659
11660         dev->mem_start = pci_resource_start(pdev, 0);
11661         dev->base_addr = dev->mem_start;
11662         dev->mem_end = pci_resource_end(pdev, 0);
11663
11664         dev->irq = pdev->irq;
11665
11666         bp->regview = pci_ioremap_bar(pdev, 0);
11667         if (!bp->regview) {
11668                 dev_err(&bp->pdev->dev,
11669                         "Cannot map register space, aborting\n");
11670                 rc = -ENOMEM;
11671                 goto err_out_release;
11672         }
11673
11674         /* In E1/E1H use pci device function given by kernel.
11675          * In E2/E3 read physical function from ME register since these chips
11676          * support Physical Device Assignment where kernel BDF maybe arbitrary
11677          * (depending on hypervisor).
11678          */
11679         if (chip_is_e1x)
11680                 bp->pf_num = PCI_FUNC(pdev->devfn);
11681         else {/* chip is E2/3*/
11682                 pci_read_config_dword(bp->pdev,
11683                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
11684                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11685                     ME_REG_ABS_PF_NUM_SHIFT);
11686         }
11687         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11688
11689         bnx2x_set_power_state(bp, PCI_D0);
11690
11691         /* clean indirect addresses */
11692         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11693                                PCICFG_VENDOR_ID_OFFSET);
11694         /*
11695          * Clean the following indirect addresses for all functions since it
11696          * is not used by the driver.
11697          */
11698         if (IS_PF(bp)) {
11699                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11700                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11701                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11702                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11703
11704                 if (chip_is_e1x) {
11705                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11706                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11707                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11708                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11709                 }
11710
11711                 /* Enable internal target-read (in case we are probed after PF
11712                  * FLR). Must be done prior to any BAR read access. Only for
11713                  * 57712 and up
11714                  */
11715                 if (!chip_is_e1x)
11716                         REG_WR(bp,
11717                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11718         }
11719
11720         dev->watchdog_timeo = TX_TIMEOUT;
11721
11722         dev->netdev_ops = &bnx2x_netdev_ops;
11723         bnx2x_set_ethtool_ops(dev);
11724
11725         dev->priv_flags |= IFF_UNICAST_FLT;
11726
11727         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11728                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11729                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11730                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11731
11732         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11733                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11734
11735         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11736         if (bp->flags & USING_DAC_FLAG)
11737                 dev->features |= NETIF_F_HIGHDMA;
11738
11739         /* Add Loopback capability to the device */
11740         dev->hw_features |= NETIF_F_LOOPBACK;
11741
11742 #ifdef BCM_DCBNL
11743         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11744 #endif
11745
11746         /* get_port_hwinfo() will set prtad and mmds properly */
11747         bp->mdio.prtad = MDIO_PRTAD_NONE;
11748         bp->mdio.mmds = 0;
11749         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11750         bp->mdio.dev = dev;
11751         bp->mdio.mdio_read = bnx2x_mdio_read;
11752         bp->mdio.mdio_write = bnx2x_mdio_write;
11753
11754         return 0;
11755
11756 err_out_release:
11757         if (atomic_read(&pdev->enable_cnt) == 1)
11758                 pci_release_regions(pdev);
11759
11760 err_out_disable:
11761         pci_disable_device(pdev);
11762         pci_set_drvdata(pdev, NULL);
11763
11764 err_out:
11765         return rc;
11766 }
11767
11768 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
11769 {
11770         u32 val = 0;
11771
11772         pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
11773         *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11774
11775         /* return value of 1=2.5GHz 2=5GHz */
11776         *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11777 }
11778
11779 static int bnx2x_check_firmware(struct bnx2x *bp)
11780 {
11781         const struct firmware *firmware = bp->firmware;
11782         struct bnx2x_fw_file_hdr *fw_hdr;
11783         struct bnx2x_fw_file_section *sections;
11784         u32 offset, len, num_ops;
11785         u16 *ops_offsets;
11786         int i;
11787         const u8 *fw_ver;
11788
11789         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11790                 BNX2X_ERR("Wrong FW size\n");
11791                 return -EINVAL;
11792         }
11793
11794         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11795         sections = (struct bnx2x_fw_file_section *)fw_hdr;
11796
11797         /* Make sure none of the offsets and sizes make us read beyond
11798          * the end of the firmware data */
11799         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11800                 offset = be32_to_cpu(sections[i].offset);
11801                 len = be32_to_cpu(sections[i].len);
11802                 if (offset + len > firmware->size) {
11803                         BNX2X_ERR("Section %d length is out of bounds\n", i);
11804                         return -EINVAL;
11805                 }
11806         }
11807
11808         /* Likewise for the init_ops offsets */
11809         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11810         ops_offsets = (u16 *)(firmware->data + offset);
11811         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11812
11813         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11814                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11815                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
11816                         return -EINVAL;
11817                 }
11818         }
11819
11820         /* Check FW version */
11821         offset = be32_to_cpu(fw_hdr->fw_version.offset);
11822         fw_ver = firmware->data + offset;
11823         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11824             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11825             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11826             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11827                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11828                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11829                        BCM_5710_FW_MAJOR_VERSION,
11830                        BCM_5710_FW_MINOR_VERSION,
11831                        BCM_5710_FW_REVISION_VERSION,
11832                        BCM_5710_FW_ENGINEERING_VERSION);
11833                 return -EINVAL;
11834         }
11835
11836         return 0;
11837 }
11838
11839 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11840 {
11841         const __be32 *source = (const __be32 *)_source;
11842         u32 *target = (u32 *)_target;
11843         u32 i;
11844
11845         for (i = 0; i < n/4; i++)
11846                 target[i] = be32_to_cpu(source[i]);
11847 }
11848
11849 /*
11850    Ops array is stored in the following format:
11851    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11852  */
11853 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11854 {
11855         const __be32 *source = (const __be32 *)_source;
11856         struct raw_op *target = (struct raw_op *)_target;
11857         u32 i, j, tmp;
11858
11859         for (i = 0, j = 0; i < n/8; i++, j += 2) {
11860                 tmp = be32_to_cpu(source[j]);
11861                 target[i].op = (tmp >> 24) & 0xff;
11862                 target[i].offset = tmp & 0xffffff;
11863                 target[i].raw_data = be32_to_cpu(source[j + 1]);
11864         }
11865 }
11866
11867 /* IRO array is stored in the following format:
11868  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11869  */
11870 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11871 {
11872         const __be32 *source = (const __be32 *)_source;
11873         struct iro *target = (struct iro *)_target;
11874         u32 i, j, tmp;
11875
11876         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11877                 target[i].base = be32_to_cpu(source[j]);
11878                 j++;
11879                 tmp = be32_to_cpu(source[j]);
11880                 target[i].m1 = (tmp >> 16) & 0xffff;
11881                 target[i].m2 = tmp & 0xffff;
11882                 j++;
11883                 tmp = be32_to_cpu(source[j]);
11884                 target[i].m3 = (tmp >> 16) & 0xffff;
11885                 target[i].size = tmp & 0xffff;
11886                 j++;
11887         }
11888 }
11889
11890 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11891 {
11892         const __be16 *source = (const __be16 *)_source;
11893         u16 *target = (u16 *)_target;
11894         u32 i;
11895
11896         for (i = 0; i < n/2; i++)
11897                 target[i] = be16_to_cpu(source[i]);
11898 }
11899
11900 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
11901 do {                                                                    \
11902         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
11903         bp->arr = kmalloc(len, GFP_KERNEL);                             \
11904         if (!bp->arr)                                                   \
11905                 goto lbl;                                               \
11906         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
11907              (u8 *)bp->arr, len);                                       \
11908 } while (0)
11909
11910 static int bnx2x_init_firmware(struct bnx2x *bp)
11911 {
11912         const char *fw_file_name;
11913         struct bnx2x_fw_file_hdr *fw_hdr;
11914         int rc;
11915
11916         if (bp->firmware)
11917                 return 0;
11918
11919         if (CHIP_IS_E1(bp))
11920                 fw_file_name = FW_FILE_NAME_E1;
11921         else if (CHIP_IS_E1H(bp))
11922                 fw_file_name = FW_FILE_NAME_E1H;
11923         else if (!CHIP_IS_E1x(bp))
11924                 fw_file_name = FW_FILE_NAME_E2;
11925         else {
11926                 BNX2X_ERR("Unsupported chip revision\n");
11927                 return -EINVAL;
11928         }
11929         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11930
11931         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11932         if (rc) {
11933                 BNX2X_ERR("Can't load firmware file %s\n",
11934                           fw_file_name);
11935                 goto request_firmware_exit;
11936         }
11937
11938         rc = bnx2x_check_firmware(bp);
11939         if (rc) {
11940                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11941                 goto request_firmware_exit;
11942         }
11943
11944         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11945
11946         /* Initialize the pointers to the init arrays */
11947         /* Blob */
11948         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11949
11950         /* Opcodes */
11951         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11952
11953         /* Offsets */
11954         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11955                             be16_to_cpu_n);
11956
11957         /* STORMs firmware */
11958         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11959                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11960         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
11961                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11962         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11963                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11964         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
11965                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
11966         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11967                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11968         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
11969                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11970         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11971                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11972         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
11973                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
11974         /* IRO */
11975         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11976
11977         return 0;
11978
11979 iro_alloc_err:
11980         kfree(bp->init_ops_offsets);
11981 init_offsets_alloc_err:
11982         kfree(bp->init_ops);
11983 init_ops_alloc_err:
11984         kfree(bp->init_data);
11985 request_firmware_exit:
11986         release_firmware(bp->firmware);
11987         bp->firmware = NULL;
11988
11989         return rc;
11990 }
11991
11992 static void bnx2x_release_firmware(struct bnx2x *bp)
11993 {
11994         kfree(bp->init_ops_offsets);
11995         kfree(bp->init_ops);
11996         kfree(bp->init_data);
11997         release_firmware(bp->firmware);
11998         bp->firmware = NULL;
11999 }
12000
12001
12002 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12003         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12004         .init_hw_cmn      = bnx2x_init_hw_common,
12005         .init_hw_port     = bnx2x_init_hw_port,
12006         .init_hw_func     = bnx2x_init_hw_func,
12007
12008         .reset_hw_cmn     = bnx2x_reset_common,
12009         .reset_hw_port    = bnx2x_reset_port,
12010         .reset_hw_func    = bnx2x_reset_func,
12011
12012         .gunzip_init      = bnx2x_gunzip_init,
12013         .gunzip_end       = bnx2x_gunzip_end,
12014
12015         .init_fw          = bnx2x_init_firmware,
12016         .release_fw       = bnx2x_release_firmware,
12017 };
12018
12019 void bnx2x__init_func_obj(struct bnx2x *bp)
12020 {
12021         /* Prepare DMAE related driver resources */
12022         bnx2x_setup_dmae(bp);
12023
12024         bnx2x_init_func_obj(bp, &bp->func_obj,
12025                             bnx2x_sp(bp, func_rdata),
12026                             bnx2x_sp_mapping(bp, func_rdata),
12027                             bnx2x_sp(bp, func_afex_rdata),
12028                             bnx2x_sp_mapping(bp, func_afex_rdata),
12029                             &bnx2x_func_sp_drv);
12030 }
12031
12032 /* must be called after sriov-enable */
12033 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12034 {
12035         int cid_count = BNX2X_L2_MAX_CID(bp);
12036
12037         if (CNIC_SUPPORT(bp))
12038                 cid_count += CNIC_CID_MAX;
12039         return roundup(cid_count, QM_CID_ROUND);
12040 }
12041
12042 /**
12043  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12044  *
12045  * @dev:        pci device
12046  *
12047  */
12048 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12049                                      int cnic_cnt, bool is_vf)
12050 {
12051         int pos, index;
12052         u16 control = 0;
12053
12054         pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12055
12056         /*
12057          * If MSI-X is not supported - return number of SBs needed to support
12058          * one fast path queue: one FP queue + SB for CNIC
12059          */
12060         if (!pos) {
12061                 dev_info(&pdev->dev, "no msix capability found\n");
12062                 return 1 + cnic_cnt;
12063         }
12064         dev_info(&pdev->dev, "msix capability found\n");
12065
12066         /*
12067          * The value in the PCI configuration space is the index of the last
12068          * entry, namely one less than the actual size of the table, which is
12069          * exactly what we want to return from this function: number of all SBs
12070          * without the default SB.
12071          * For VFs there is no default SB, then we return (index+1).
12072          */
12073         pci_read_config_word(pdev, pos  + PCI_MSI_FLAGS, &control);
12074
12075         index = control & PCI_MSIX_FLAGS_QSIZE;
12076
12077         return is_vf ? index + 1 : index;
12078 }
12079
12080 static int set_max_cos_est(int chip_id)
12081 {
12082         switch (chip_id) {
12083         case BCM57710:
12084         case BCM57711:
12085         case BCM57711E:
12086                 return BNX2X_MULTI_TX_COS_E1X;
12087         case BCM57712:
12088         case BCM57712_MF:
12089         case BCM57712_VF:
12090                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12091         case BCM57800:
12092         case BCM57800_MF:
12093         case BCM57800_VF:
12094         case BCM57810:
12095         case BCM57810_MF:
12096         case BCM57840_4_10:
12097         case BCM57840_2_20:
12098         case BCM57840_O:
12099         case BCM57840_MFO:
12100         case BCM57810_VF:
12101         case BCM57840_MF:
12102         case BCM57840_VF:
12103         case BCM57811:
12104         case BCM57811_MF:
12105         case BCM57811_VF:
12106                 return BNX2X_MULTI_TX_COS_E3B0;
12107                 return 1;
12108         default:
12109                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12110                 return -ENODEV;
12111         }
12112 }
12113
12114 static int set_is_vf(int chip_id)
12115 {
12116         switch (chip_id) {
12117         case BCM57712_VF:
12118         case BCM57800_VF:
12119         case BCM57810_VF:
12120         case BCM57840_VF:
12121         case BCM57811_VF:
12122                 return true;
12123         default:
12124                 return false;
12125         }
12126 }
12127
12128 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12129
12130 static int bnx2x_init_one(struct pci_dev *pdev,
12131                                     const struct pci_device_id *ent)
12132 {
12133         struct net_device *dev = NULL;
12134         struct bnx2x *bp;
12135         int pcie_width, pcie_speed;
12136         int rc, max_non_def_sbs;
12137         int rx_count, tx_count, rss_count, doorbell_size;
12138         int max_cos_est;
12139         bool is_vf;
12140         int cnic_cnt;
12141
12142         /* An estimated maximum supported CoS number according to the chip
12143          * version.
12144          * We will try to roughly estimate the maximum number of CoSes this chip
12145          * may support in order to minimize the memory allocated for Tx
12146          * netdev_queue's. This number will be accurately calculated during the
12147          * initialization of bp->max_cos based on the chip versions AND chip
12148          * revision in the bnx2x_init_bp().
12149          */
12150         max_cos_est = set_max_cos_est(ent->driver_data);
12151         if (max_cos_est < 0)
12152                 return max_cos_est;
12153         is_vf = set_is_vf(ent->driver_data);
12154         cnic_cnt = is_vf ? 0 : 1;
12155
12156         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12157
12158         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12159         rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12160
12161         if (rss_count < 1)
12162                 return -EINVAL;
12163
12164         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12165         rx_count = rss_count + cnic_cnt;
12166
12167         /* Maximum number of netdev Tx queues:
12168          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12169          */
12170         tx_count = rss_count * max_cos_est + cnic_cnt;
12171
12172         /* dev zeroed in init_etherdev */
12173         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12174         if (!dev)
12175                 return -ENOMEM;
12176
12177         bp = netdev_priv(dev);
12178
12179         bp->flags = 0;
12180         if (is_vf)
12181                 bp->flags |= IS_VF_FLAG;
12182
12183         bp->igu_sb_cnt = max_non_def_sbs;
12184         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12185         bp->msg_enable = debug;
12186         bp->cnic_support = cnic_cnt;
12187         bp->cnic_probe = bnx2x_cnic_probe;
12188
12189         pci_set_drvdata(pdev, dev);
12190
12191         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12192         if (rc < 0) {
12193                 free_netdev(dev);
12194                 return rc;
12195         }
12196
12197         BNX2X_DEV_INFO("This is a %s function\n",
12198                        IS_PF(bp) ? "physical" : "virtual");
12199         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12200         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12201         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12202                           tx_count, rx_count);
12203
12204         rc = bnx2x_init_bp(bp);
12205         if (rc)
12206                 goto init_one_exit;
12207
12208         /* Map doorbells here as we need the real value of bp->max_cos which
12209          * is initialized in bnx2x_init_bp() to determine the number of
12210          * l2 connections.
12211          */
12212         if (IS_VF(bp)) {
12213                 /* vf doorbells are embedded within the regview */
12214                 bp->doorbells = bp->regview + PXP_VF_ADDR_DB_START;
12215
12216                 /* allocate vf2pf mailbox for vf to pf channel */
12217                 BNX2X_PCI_ALLOC(bp->vf2pf_mbox, &bp->vf2pf_mbox_mapping,
12218                                 sizeof(struct bnx2x_vf_mbx_msg));
12219         } else {
12220                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12221                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12222                         dev_err(&bp->pdev->dev,
12223                                 "Cannot map doorbells, bar size too small, aborting\n");
12224                         rc = -ENOMEM;
12225                         goto init_one_exit;
12226                 }
12227                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12228                                                 doorbell_size);
12229         }
12230         if (!bp->doorbells) {
12231                 dev_err(&bp->pdev->dev,
12232                         "Cannot map doorbell space, aborting\n");
12233                 rc = -ENOMEM;
12234                 goto init_one_exit;
12235         }
12236
12237         if (IS_VF(bp)) {
12238                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12239                 if (rc)
12240                         goto init_one_exit;
12241         }
12242
12243         /* calc qm_cid_count */
12244         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12245         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12246
12247         /* disable FCOE L2 queue for E1x*/
12248         if (CHIP_IS_E1x(bp))
12249                 bp->flags |= NO_FCOE_FLAG;
12250
12251         /* disable FCOE for 57840 device, until FW supports it */
12252         switch (ent->driver_data) {
12253         case BCM57840_O:
12254         case BCM57840_4_10:
12255         case BCM57840_2_20:
12256         case BCM57840_MFO:
12257         case BCM57840_MF:
12258                 bp->flags |= NO_FCOE_FLAG;
12259         }
12260
12261         /* Set bp->num_queues for MSI-X mode*/
12262         bnx2x_set_num_queues(bp);
12263
12264         /* Configure interrupt mode: try to enable MSI-X/MSI if
12265          * needed.
12266          */
12267         rc = bnx2x_set_int_mode(bp);
12268         if (rc) {
12269                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12270                 goto init_one_exit;
12271         }
12272
12273         /* register the net device */
12274         rc = register_netdev(dev);
12275         if (rc) {
12276                 dev_err(&pdev->dev, "Cannot register net device\n");
12277                 goto init_one_exit;
12278         }
12279         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12280
12281
12282         if (!NO_FCOE(bp)) {
12283                 /* Add storage MAC address */
12284                 rtnl_lock();
12285                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12286                 rtnl_unlock();
12287         }
12288
12289         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12290         BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12291                        pcie_width, pcie_speed);
12292
12293         BNX2X_DEV_INFO(
12294                 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12295                     board_info[ent->driver_data].name,
12296                     (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12297                     pcie_width,
12298                     ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12299                      (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12300                     "5GHz (Gen2)" : "2.5GHz",
12301                     dev->base_addr, bp->pdev->irq, dev->dev_addr);
12302
12303         return 0;
12304
12305 alloc_mem_err:
12306         BNX2X_PCI_FREE(bp->vf2pf_mbox, bp->vf2pf_mbox_mapping,
12307                        sizeof(struct bnx2x_vf_mbx_msg));
12308         rc = -ENOMEM;
12309
12310 init_one_exit:
12311         if (bp->regview)
12312                 iounmap(bp->regview);
12313
12314         if (IS_PF(bp) && bp->doorbells)
12315                 iounmap(bp->doorbells);
12316
12317         free_netdev(dev);
12318
12319         if (atomic_read(&pdev->enable_cnt) == 1)
12320                 pci_release_regions(pdev);
12321
12322         pci_disable_device(pdev);
12323         pci_set_drvdata(pdev, NULL);
12324
12325         return rc;
12326 }
12327
12328 static void bnx2x_remove_one(struct pci_dev *pdev)
12329 {
12330         struct net_device *dev = pci_get_drvdata(pdev);
12331         struct bnx2x *bp;
12332
12333         if (!dev) {
12334                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12335                 return;
12336         }
12337         bp = netdev_priv(dev);
12338
12339         /* Delete storage MAC address */
12340         if (!NO_FCOE(bp)) {
12341                 rtnl_lock();
12342                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12343                 rtnl_unlock();
12344         }
12345
12346 #ifdef BCM_DCBNL
12347         /* Delete app tlvs from dcbnl */
12348         bnx2x_dcbnl_update_applist(bp, true);
12349 #endif
12350
12351         unregister_netdev(dev);
12352
12353         /* Power on: we can't let PCI layer write to us while we are in D3 */
12354         if (IS_PF(bp))
12355                 bnx2x_set_power_state(bp, PCI_D0);
12356
12357         /* Disable MSI/MSI-X */
12358         bnx2x_disable_msi(bp);
12359
12360         /* Power off */
12361         if (IS_PF(bp))
12362                 bnx2x_set_power_state(bp, PCI_D3hot);
12363
12364         /* Make sure RESET task is not scheduled before continuing */
12365         cancel_delayed_work_sync(&bp->sp_rtnl_task);
12366         /* send message via vfpf channel to release the resources of this vf */
12367         if (IS_VF(bp))
12368                 bnx2x_vfpf_release(bp);
12369
12370         if (bp->regview)
12371                 iounmap(bp->regview);
12372
12373         /* for vf doorbells are part of the regview and were unmapped along with
12374          * it. FW is only loaded by PF.
12375          */
12376         if (IS_PF(bp)) {
12377                 if (bp->doorbells)
12378                         iounmap(bp->doorbells);
12379
12380                 bnx2x_release_firmware(bp);
12381         }
12382         bnx2x_free_mem_bp(bp);
12383
12384         free_netdev(dev);
12385
12386         if (atomic_read(&pdev->enable_cnt) == 1)
12387                 pci_release_regions(pdev);
12388
12389         pci_disable_device(pdev);
12390         pci_set_drvdata(pdev, NULL);
12391 }
12392
12393 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12394 {
12395         int i;
12396
12397         bp->state = BNX2X_STATE_ERROR;
12398
12399         bp->rx_mode = BNX2X_RX_MODE_NONE;
12400
12401         if (CNIC_LOADED(bp))
12402                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12403
12404         /* Stop Tx */
12405         bnx2x_tx_disable(bp);
12406
12407         bnx2x_netif_stop(bp, 0);
12408         /* Delete all NAPI objects */
12409         bnx2x_del_all_napi(bp);
12410         if (CNIC_LOADED(bp))
12411                 bnx2x_del_all_napi_cnic(bp);
12412
12413         del_timer_sync(&bp->timer);
12414
12415         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12416
12417         /* Release IRQs */
12418         bnx2x_free_irq(bp);
12419
12420         /* Free SKBs, SGEs, TPA pool and driver internals */
12421         bnx2x_free_skbs(bp);
12422
12423         for_each_rx_queue(bp, i)
12424                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12425
12426         bnx2x_free_mem(bp);
12427
12428         bp->state = BNX2X_STATE_CLOSED;
12429
12430         netif_carrier_off(bp->dev);
12431
12432         return 0;
12433 }
12434
12435 static void bnx2x_eeh_recover(struct bnx2x *bp)
12436 {
12437         u32 val;
12438
12439         mutex_init(&bp->port.phy_mutex);
12440
12441
12442         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12443         if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12444                 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12445                 BNX2X_ERR("BAD MCP validity signature\n");
12446 }
12447
12448 /**
12449  * bnx2x_io_error_detected - called when PCI error is detected
12450  * @pdev: Pointer to PCI device
12451  * @state: The current pci connection state
12452  *
12453  * This function is called after a PCI bus error affecting
12454  * this device has been detected.
12455  */
12456 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12457                                                 pci_channel_state_t state)
12458 {
12459         struct net_device *dev = pci_get_drvdata(pdev);
12460         struct bnx2x *bp = netdev_priv(dev);
12461
12462         rtnl_lock();
12463
12464         netif_device_detach(dev);
12465
12466         if (state == pci_channel_io_perm_failure) {
12467                 rtnl_unlock();
12468                 return PCI_ERS_RESULT_DISCONNECT;
12469         }
12470
12471         if (netif_running(dev))
12472                 bnx2x_eeh_nic_unload(bp);
12473
12474         pci_disable_device(pdev);
12475
12476         rtnl_unlock();
12477
12478         /* Request a slot reset */
12479         return PCI_ERS_RESULT_NEED_RESET;
12480 }
12481
12482 /**
12483  * bnx2x_io_slot_reset - called after the PCI bus has been reset
12484  * @pdev: Pointer to PCI device
12485  *
12486  * Restart the card from scratch, as if from a cold-boot.
12487  */
12488 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12489 {
12490         struct net_device *dev = pci_get_drvdata(pdev);
12491         struct bnx2x *bp = netdev_priv(dev);
12492
12493         rtnl_lock();
12494
12495         if (pci_enable_device(pdev)) {
12496                 dev_err(&pdev->dev,
12497                         "Cannot re-enable PCI device after reset\n");
12498                 rtnl_unlock();
12499                 return PCI_ERS_RESULT_DISCONNECT;
12500         }
12501
12502         pci_set_master(pdev);
12503         pci_restore_state(pdev);
12504
12505         if (netif_running(dev))
12506                 bnx2x_set_power_state(bp, PCI_D0);
12507
12508         rtnl_unlock();
12509
12510         return PCI_ERS_RESULT_RECOVERED;
12511 }
12512
12513 /**
12514  * bnx2x_io_resume - called when traffic can start flowing again
12515  * @pdev: Pointer to PCI device
12516  *
12517  * This callback is called when the error recovery driver tells us that
12518  * its OK to resume normal operation.
12519  */
12520 static void bnx2x_io_resume(struct pci_dev *pdev)
12521 {
12522         struct net_device *dev = pci_get_drvdata(pdev);
12523         struct bnx2x *bp = netdev_priv(dev);
12524
12525         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12526                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12527                 return;
12528         }
12529
12530         rtnl_lock();
12531
12532         bnx2x_eeh_recover(bp);
12533
12534         if (netif_running(dev))
12535                 bnx2x_nic_load(bp, LOAD_NORMAL);
12536
12537         netif_device_attach(dev);
12538
12539         rtnl_unlock();
12540 }
12541
12542 static const struct pci_error_handlers bnx2x_err_handler = {
12543         .error_detected = bnx2x_io_error_detected,
12544         .slot_reset     = bnx2x_io_slot_reset,
12545         .resume         = bnx2x_io_resume,
12546 };
12547
12548 static struct pci_driver bnx2x_pci_driver = {
12549         .name        = DRV_MODULE_NAME,
12550         .id_table    = bnx2x_pci_tbl,
12551         .probe       = bnx2x_init_one,
12552         .remove      = bnx2x_remove_one,
12553         .suspend     = bnx2x_suspend,
12554         .resume      = bnx2x_resume,
12555         .err_handler = &bnx2x_err_handler,
12556 };
12557
12558 static int __init bnx2x_init(void)
12559 {
12560         int ret;
12561
12562         pr_info("%s", version);
12563
12564         bnx2x_wq = create_singlethread_workqueue("bnx2x");
12565         if (bnx2x_wq == NULL) {
12566                 pr_err("Cannot create workqueue\n");
12567                 return -ENOMEM;
12568         }
12569
12570         ret = pci_register_driver(&bnx2x_pci_driver);
12571         if (ret) {
12572                 pr_err("Cannot register driver\n");
12573                 destroy_workqueue(bnx2x_wq);
12574         }
12575         return ret;
12576 }
12577
12578 static void __exit bnx2x_cleanup(void)
12579 {
12580         struct list_head *pos, *q;
12581         pci_unregister_driver(&bnx2x_pci_driver);
12582
12583         destroy_workqueue(bnx2x_wq);
12584
12585         /* Free globablly allocated resources */
12586         list_for_each_safe(pos, q, &bnx2x_prev_list) {
12587                 struct bnx2x_prev_path_list *tmp =
12588                         list_entry(pos, struct bnx2x_prev_path_list, list);
12589                 list_del(pos);
12590                 kfree(tmp);
12591         }
12592 }
12593
12594 void bnx2x_notify_link_changed(struct bnx2x *bp)
12595 {
12596         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12597 }
12598
12599 module_init(bnx2x_init);
12600 module_exit(bnx2x_cleanup);
12601
12602 /**
12603  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12604  *
12605  * @bp:         driver handle
12606  * @set:        set or clear the CAM entry
12607  *
12608  * This function will wait until the ramdord completion returns.
12609  * Return 0 if success, -ENODEV if ramrod doesn't return.
12610  */
12611 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12612 {
12613         unsigned long ramrod_flags = 0;
12614
12615         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12616         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12617                                  &bp->iscsi_l2_mac_obj, true,
12618                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12619 }
12620
12621 /* count denotes the number of new completions we have seen */
12622 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12623 {
12624         struct eth_spe *spe;
12625         int cxt_index, cxt_offset;
12626
12627 #ifdef BNX2X_STOP_ON_ERROR
12628         if (unlikely(bp->panic))
12629                 return;
12630 #endif
12631
12632         spin_lock_bh(&bp->spq_lock);
12633         BUG_ON(bp->cnic_spq_pending < count);
12634         bp->cnic_spq_pending -= count;
12635
12636
12637         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12638                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12639                                 & SPE_HDR_CONN_TYPE) >>
12640                                 SPE_HDR_CONN_TYPE_SHIFT;
12641                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12642                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12643
12644                 /* Set validation for iSCSI L2 client before sending SETUP
12645                  *  ramrod
12646                  */
12647                 if (type == ETH_CONNECTION_TYPE) {
12648                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12649                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12650                                         ILT_PAGE_CIDS;
12651                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12652                                         (cxt_index * ILT_PAGE_CIDS);
12653                                 bnx2x_set_ctx_validation(bp,
12654                                         &bp->context[cxt_index].
12655                                                          vcxt[cxt_offset].eth,
12656                                         BNX2X_ISCSI_ETH_CID(bp));
12657                         }
12658                 }
12659
12660                 /*
12661                  * There may be not more than 8 L2, not more than 8 L5 SPEs
12662                  * and in the air. We also check that number of outstanding
12663                  * COMMON ramrods is not more than the EQ and SPQ can
12664                  * accommodate.
12665                  */
12666                 if (type == ETH_CONNECTION_TYPE) {
12667                         if (!atomic_read(&bp->cq_spq_left))
12668                                 break;
12669                         else
12670                                 atomic_dec(&bp->cq_spq_left);
12671                 } else if (type == NONE_CONNECTION_TYPE) {
12672                         if (!atomic_read(&bp->eq_spq_left))
12673                                 break;
12674                         else
12675                                 atomic_dec(&bp->eq_spq_left);
12676                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12677                            (type == FCOE_CONNECTION_TYPE)) {
12678                         if (bp->cnic_spq_pending >=
12679                             bp->cnic_eth_dev.max_kwqe_pending)
12680                                 break;
12681                         else
12682                                 bp->cnic_spq_pending++;
12683                 } else {
12684                         BNX2X_ERR("Unknown SPE type: %d\n", type);
12685                         bnx2x_panic();
12686                         break;
12687                 }
12688
12689                 spe = bnx2x_sp_get_next(bp);
12690                 *spe = *bp->cnic_kwq_cons;
12691
12692                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12693                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12694
12695                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12696                         bp->cnic_kwq_cons = bp->cnic_kwq;
12697                 else
12698                         bp->cnic_kwq_cons++;
12699         }
12700         bnx2x_sp_prod_update(bp);
12701         spin_unlock_bh(&bp->spq_lock);
12702 }
12703
12704 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12705                                struct kwqe_16 *kwqes[], u32 count)
12706 {
12707         struct bnx2x *bp = netdev_priv(dev);
12708         int i;
12709
12710 #ifdef BNX2X_STOP_ON_ERROR
12711         if (unlikely(bp->panic)) {
12712                 BNX2X_ERR("Can't post to SP queue while panic\n");
12713                 return -EIO;
12714         }
12715 #endif
12716
12717         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12718             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12719                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12720                 return -EAGAIN;
12721         }
12722
12723         spin_lock_bh(&bp->spq_lock);
12724
12725         for (i = 0; i < count; i++) {
12726                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12727
12728                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12729                         break;
12730
12731                 *bp->cnic_kwq_prod = *spe;
12732
12733                 bp->cnic_kwq_pending++;
12734
12735                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12736                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
12737                    spe->data.update_data_addr.hi,
12738                    spe->data.update_data_addr.lo,
12739                    bp->cnic_kwq_pending);
12740
12741                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12742                         bp->cnic_kwq_prod = bp->cnic_kwq;
12743                 else
12744                         bp->cnic_kwq_prod++;
12745         }
12746
12747         spin_unlock_bh(&bp->spq_lock);
12748
12749         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12750                 bnx2x_cnic_sp_post(bp, 0);
12751
12752         return i;
12753 }
12754
12755 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12756 {
12757         struct cnic_ops *c_ops;
12758         int rc = 0;
12759
12760         mutex_lock(&bp->cnic_mutex);
12761         c_ops = rcu_dereference_protected(bp->cnic_ops,
12762                                           lockdep_is_held(&bp->cnic_mutex));
12763         if (c_ops)
12764                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12765         mutex_unlock(&bp->cnic_mutex);
12766
12767         return rc;
12768 }
12769
12770 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12771 {
12772         struct cnic_ops *c_ops;
12773         int rc = 0;
12774
12775         rcu_read_lock();
12776         c_ops = rcu_dereference(bp->cnic_ops);
12777         if (c_ops)
12778                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12779         rcu_read_unlock();
12780
12781         return rc;
12782 }
12783
12784 /*
12785  * for commands that have no data
12786  */
12787 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12788 {
12789         struct cnic_ctl_info ctl = {0};
12790
12791         ctl.cmd = cmd;
12792
12793         return bnx2x_cnic_ctl_send(bp, &ctl);
12794 }
12795
12796 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12797 {
12798         struct cnic_ctl_info ctl = {0};
12799
12800         /* first we tell CNIC and only then we count this as a completion */
12801         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12802         ctl.data.comp.cid = cid;
12803         ctl.data.comp.error = err;
12804
12805         bnx2x_cnic_ctl_send_bh(bp, &ctl);
12806         bnx2x_cnic_sp_post(bp, 0);
12807 }
12808
12809
12810 /* Called with netif_addr_lock_bh() taken.
12811  * Sets an rx_mode config for an iSCSI ETH client.
12812  * Doesn't block.
12813  * Completion should be checked outside.
12814  */
12815 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12816 {
12817         unsigned long accept_flags = 0, ramrod_flags = 0;
12818         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12819         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12820
12821         if (start) {
12822                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12823                  * because it's the only way for UIO Queue to accept
12824                  * multicasts (in non-promiscuous mode only one Queue per
12825                  * function will receive multicast packets (leading in our
12826                  * case).
12827                  */
12828                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12829                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12830                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12831                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12832
12833                 /* Clear STOP_PENDING bit if START is requested */
12834                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12835
12836                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12837         } else
12838                 /* Clear START_PENDING bit if STOP is requested */
12839                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12840
12841         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12842                 set_bit(sched_state, &bp->sp_state);
12843         else {
12844                 __set_bit(RAMROD_RX, &ramrod_flags);
12845                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12846                                     ramrod_flags);
12847         }
12848 }
12849
12850
12851 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12852 {
12853         struct bnx2x *bp = netdev_priv(dev);
12854         int rc = 0;
12855
12856         switch (ctl->cmd) {
12857         case DRV_CTL_CTXTBL_WR_CMD: {
12858                 u32 index = ctl->data.io.offset;
12859                 dma_addr_t addr = ctl->data.io.dma_addr;
12860
12861                 bnx2x_ilt_wr(bp, index, addr);
12862                 break;
12863         }
12864
12865         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12866                 int count = ctl->data.credit.credit_count;
12867
12868                 bnx2x_cnic_sp_post(bp, count);
12869                 break;
12870         }
12871
12872         /* rtnl_lock is held.  */
12873         case DRV_CTL_START_L2_CMD: {
12874                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12875                 unsigned long sp_bits = 0;
12876
12877                 /* Configure the iSCSI classification object */
12878                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12879                                    cp->iscsi_l2_client_id,
12880                                    cp->iscsi_l2_cid, BP_FUNC(bp),
12881                                    bnx2x_sp(bp, mac_rdata),
12882                                    bnx2x_sp_mapping(bp, mac_rdata),
12883                                    BNX2X_FILTER_MAC_PENDING,
12884                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12885                                    &bp->macs_pool);
12886
12887                 /* Set iSCSI MAC address */
12888                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12889                 if (rc)
12890                         break;
12891
12892                 mmiowb();
12893                 barrier();
12894
12895                 /* Start accepting on iSCSI L2 ring */
12896
12897                 netif_addr_lock_bh(dev);
12898                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12899                 netif_addr_unlock_bh(dev);
12900
12901                 /* bits to wait on */
12902                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12903                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12904
12905                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12906                         BNX2X_ERR("rx_mode completion timed out!\n");
12907
12908                 break;
12909         }
12910
12911         /* rtnl_lock is held.  */
12912         case DRV_CTL_STOP_L2_CMD: {
12913                 unsigned long sp_bits = 0;
12914
12915                 /* Stop accepting on iSCSI L2 ring */
12916                 netif_addr_lock_bh(dev);
12917                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12918                 netif_addr_unlock_bh(dev);
12919
12920                 /* bits to wait on */
12921                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12922                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12923
12924                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12925                         BNX2X_ERR("rx_mode completion timed out!\n");
12926
12927                 mmiowb();
12928                 barrier();
12929
12930                 /* Unset iSCSI L2 MAC */
12931                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12932                                         BNX2X_ISCSI_ETH_MAC, true);
12933                 break;
12934         }
12935         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12936                 int count = ctl->data.credit.credit_count;
12937
12938                 smp_mb__before_atomic_inc();
12939                 atomic_add(count, &bp->cq_spq_left);
12940                 smp_mb__after_atomic_inc();
12941                 break;
12942         }
12943         case DRV_CTL_ULP_REGISTER_CMD: {
12944                 int ulp_type = ctl->data.register_data.ulp_type;
12945
12946                 if (CHIP_IS_E3(bp)) {
12947                         int idx = BP_FW_MB_IDX(bp);
12948                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12949                         int path = BP_PATH(bp);
12950                         int port = BP_PORT(bp);
12951                         int i;
12952                         u32 scratch_offset;
12953                         u32 *host_addr;
12954
12955                         /* first write capability to shmem2 */
12956                         if (ulp_type == CNIC_ULP_ISCSI)
12957                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12958                         else if (ulp_type == CNIC_ULP_FCOE)
12959                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12960                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12961
12962                         if ((ulp_type != CNIC_ULP_FCOE) ||
12963                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12964                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
12965                                 break;
12966
12967                         /* if reached here - should write fcoe capabilities */
12968                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12969                         if (!scratch_offset)
12970                                 break;
12971                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
12972                                                    fcoe_features[path][port]);
12973                         host_addr = (u32 *) &(ctl->data.register_data.
12974                                               fcoe_features);
12975                         for (i = 0; i < sizeof(struct fcoe_capabilities);
12976                              i += 4)
12977                                 REG_WR(bp, scratch_offset + i,
12978                                        *(host_addr + i/4));
12979                 }
12980                 break;
12981         }
12982
12983         case DRV_CTL_ULP_UNREGISTER_CMD: {
12984                 int ulp_type = ctl->data.ulp_type;
12985
12986                 if (CHIP_IS_E3(bp)) {
12987                         int idx = BP_FW_MB_IDX(bp);
12988                         u32 cap;
12989
12990                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12991                         if (ulp_type == CNIC_ULP_ISCSI)
12992                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12993                         else if (ulp_type == CNIC_ULP_FCOE)
12994                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12995                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12996                 }
12997                 break;
12998         }
12999
13000         default:
13001                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13002                 rc = -EINVAL;
13003         }
13004
13005         return rc;
13006 }
13007
13008 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13009 {
13010         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13011
13012         if (bp->flags & USING_MSIX_FLAG) {
13013                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13014                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13015                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13016         } else {
13017                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13018                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13019         }
13020         if (!CHIP_IS_E1x(bp))
13021                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13022         else
13023                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13024
13025         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13026         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13027         cp->irq_arr[1].status_blk = bp->def_status_blk;
13028         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13029         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13030
13031         cp->num_irq = 2;
13032 }
13033
13034 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13035 {
13036         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13037
13038
13039         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13040                              bnx2x_cid_ilt_lines(bp);
13041         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13042         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13043         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13044
13045         if (NO_ISCSI_OOO(bp))
13046                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13047 }
13048
13049 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13050                                void *data)
13051 {
13052         struct bnx2x *bp = netdev_priv(dev);
13053         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13054         int rc;
13055
13056         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13057
13058         if (ops == NULL) {
13059                 BNX2X_ERR("NULL ops received\n");
13060                 return -EINVAL;
13061         }
13062
13063         if (!CNIC_SUPPORT(bp)) {
13064                 BNX2X_ERR("Can't register CNIC when not supported\n");
13065                 return -EOPNOTSUPP;
13066         }
13067
13068         if (!CNIC_LOADED(bp)) {
13069                 rc = bnx2x_load_cnic(bp);
13070                 if (rc) {
13071                         BNX2X_ERR("CNIC-related load failed\n");
13072                         return rc;
13073                 }
13074
13075         }
13076
13077         bp->cnic_enabled = true;
13078
13079         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13080         if (!bp->cnic_kwq)
13081                 return -ENOMEM;
13082
13083         bp->cnic_kwq_cons = bp->cnic_kwq;
13084         bp->cnic_kwq_prod = bp->cnic_kwq;
13085         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13086
13087         bp->cnic_spq_pending = 0;
13088         bp->cnic_kwq_pending = 0;
13089
13090         bp->cnic_data = data;
13091
13092         cp->num_irq = 0;
13093         cp->drv_state |= CNIC_DRV_STATE_REGD;
13094         cp->iro_arr = bp->iro_arr;
13095
13096         bnx2x_setup_cnic_irq_info(bp);
13097
13098         rcu_assign_pointer(bp->cnic_ops, ops);
13099
13100         return 0;
13101 }
13102
13103 static int bnx2x_unregister_cnic(struct net_device *dev)
13104 {
13105         struct bnx2x *bp = netdev_priv(dev);
13106         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13107
13108         mutex_lock(&bp->cnic_mutex);
13109         cp->drv_state = 0;
13110         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13111         mutex_unlock(&bp->cnic_mutex);
13112         synchronize_rcu();
13113         kfree(bp->cnic_kwq);
13114         bp->cnic_kwq = NULL;
13115
13116         return 0;
13117 }
13118
13119 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13120 {
13121         struct bnx2x *bp = netdev_priv(dev);
13122         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13123
13124         /* If both iSCSI and FCoE are disabled - return NULL in
13125          * order to indicate CNIC that it should not try to work
13126          * with this device.
13127          */
13128         if (NO_ISCSI(bp) && NO_FCOE(bp))
13129                 return NULL;
13130
13131         cp->drv_owner = THIS_MODULE;
13132         cp->chip_id = CHIP_ID(bp);
13133         cp->pdev = bp->pdev;
13134         cp->io_base = bp->regview;
13135         cp->io_base2 = bp->doorbells;
13136         cp->max_kwqe_pending = 8;
13137         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13138         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13139                              bnx2x_cid_ilt_lines(bp);
13140         cp->ctx_tbl_len = CNIC_ILT_LINES;
13141         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13142         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13143         cp->drv_ctl = bnx2x_drv_ctl;
13144         cp->drv_register_cnic = bnx2x_register_cnic;
13145         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13146         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13147         cp->iscsi_l2_client_id =
13148                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13149         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13150
13151         if (NO_ISCSI_OOO(bp))
13152                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13153
13154         if (NO_ISCSI(bp))
13155                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13156
13157         if (NO_FCOE(bp))
13158                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13159
13160         BNX2X_DEV_INFO(
13161                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13162            cp->ctx_blk_size,
13163            cp->ctx_tbl_offset,
13164            cp->ctx_tbl_len,
13165            cp->starting_cid);
13166         return cp;
13167 }
13168
13169 int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping)
13170 {
13171         struct cstorm_vf_zone_data __iomem *zone_data =
13172                 REG_ADDR(bp, PXP_VF_ADDR_CSDM_GLOBAL_START);
13173         int tout = 600, interval = 100; /* wait for 60 seconds */
13174
13175         if (*done) {
13176                 BNX2X_ERR("done was non zero before message to pf was sent\n");
13177                 WARN_ON(true);
13178                 return -EINVAL;
13179         }
13180
13181         /* Write message address */
13182         writel(U64_LO(msg_mapping),
13183                &zone_data->non_trigger.vf_pf_channel.msg_addr_lo);
13184         writel(U64_HI(msg_mapping),
13185                &zone_data->non_trigger.vf_pf_channel.msg_addr_hi);
13186
13187         /* make sure the address is written before FW accesses it */
13188         wmb();
13189
13190         /* Trigger the PF FW */
13191         writeb(1, &zone_data->trigger.vf_pf_channel.addr_valid);
13192
13193         /* Wait for PF to complete */
13194         while ((tout >= 0) && (!*done)) {
13195                 msleep(interval);
13196                 tout -= 1;
13197
13198                 /* progress indicator - HV can take its own sweet time in
13199                  * answering VFs...
13200                  */
13201                 DP_CONT(BNX2X_MSG_IOV, ".");
13202         }
13203
13204         if (!*done) {
13205                 BNX2X_ERR("PF response has timed out\n");
13206                 return -EAGAIN;
13207         }
13208         DP(BNX2X_MSG_SP, "Got a response from PF\n");
13209         return 0;
13210 }
13211
13212 int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id)
13213 {
13214         u32 me_reg;
13215         int tout = 10, interval = 100; /* Wait for 1 sec */
13216
13217         do {
13218                 /* pxp traps vf read of doorbells and returns me reg value */
13219                 me_reg = readl(bp->doorbells);
13220                 if (GOOD_ME_REG(me_reg))
13221                         break;
13222
13223                 msleep(interval);
13224
13225                 BNX2X_ERR("Invalid ME register value: 0x%08x\n. Is pf driver up?",
13226                           me_reg);
13227         } while (tout-- > 0);
13228
13229         if (!GOOD_ME_REG(me_reg)) {
13230                 BNX2X_ERR("Invalid ME register value: 0x%08x\n", me_reg);
13231                 return -EINVAL;
13232         }
13233
13234         BNX2X_ERR("valid ME register value: 0x%08x\n", me_reg);
13235
13236         *vf_id = (me_reg & ME_REG_VF_NUM_MASK) >> ME_REG_VF_NUM_SHIFT;
13237
13238         return 0;
13239 }
13240
13241 int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count)
13242 {
13243         int rc = 0, attempts = 0;
13244         struct vfpf_acquire_tlv *req = &bp->vf2pf_mbox->req.acquire;
13245         struct pfvf_acquire_resp_tlv *resp = &bp->vf2pf_mbox->resp.acquire_resp;
13246         u32 vf_id;
13247         bool resources_acquired = false;
13248
13249         /* clear mailbox and prep first tlv */
13250         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_ACQUIRE, sizeof(*req));
13251
13252         if (bnx2x_get_vf_id(bp, &vf_id))
13253                 return -EAGAIN;
13254
13255         req->vfdev_info.vf_id = vf_id;
13256         req->vfdev_info.vf_os = 0;
13257
13258         req->resc_request.num_rxqs = rx_count;
13259         req->resc_request.num_txqs = tx_count;
13260         req->resc_request.num_sbs = bp->igu_sb_cnt;
13261         req->resc_request.num_mac_filters = VF_ACQUIRE_MAC_FILTERS;
13262         req->resc_request.num_mc_filters = VF_ACQUIRE_MC_FILTERS;
13263
13264         /* add list termination tlv */
13265         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13266                       sizeof(struct channel_list_end_tlv));
13267
13268         /* output tlvs list */
13269         bnx2x_dp_tlv_list(bp, req);
13270
13271         while (!resources_acquired) {
13272                 DP(BNX2X_MSG_SP, "attempting to acquire resources\n");
13273
13274                 /* send acquire request */
13275                 rc = bnx2x_send_msg2pf(bp,
13276                                        &resp->hdr.status,
13277                                        bp->vf2pf_mbox_mapping);
13278
13279                 /* PF timeout */
13280                 if (rc)
13281                         return rc;
13282
13283                 /* copy acquire response from buffer to bp */
13284                 memcpy(&bp->acquire_resp, resp, sizeof(bp->acquire_resp));
13285
13286                 attempts++;
13287
13288                 /* test whether the PF accepted our request. If not, humble the
13289                  * the request and try again.
13290                  */
13291                 if (bp->acquire_resp.hdr.status == PFVF_STATUS_SUCCESS) {
13292                         DP(BNX2X_MSG_SP, "resources acquired\n");
13293                         resources_acquired = true;
13294                 } else if (bp->acquire_resp.hdr.status ==
13295                            PFVF_STATUS_NO_RESOURCE &&
13296                            attempts < VF_ACQUIRE_THRESH) {
13297                         DP(BNX2X_MSG_SP,
13298                            "PF unwilling to fulfill resource request. Try PF recommended amount\n");
13299
13300                         /* humble our request */
13301                         req->resc_request.num_txqs =
13302                                 bp->acquire_resp.resc.num_txqs;
13303                         req->resc_request.num_rxqs =
13304                                 bp->acquire_resp.resc.num_rxqs;
13305                         req->resc_request.num_sbs =
13306                                 bp->acquire_resp.resc.num_sbs;
13307                         req->resc_request.num_mac_filters =
13308                                 bp->acquire_resp.resc.num_mac_filters;
13309                         req->resc_request.num_vlan_filters =
13310                                 bp->acquire_resp.resc.num_vlan_filters;
13311                         req->resc_request.num_mc_filters =
13312                                 bp->acquire_resp.resc.num_mc_filters;
13313
13314                         /* Clear response buffer */
13315                         memset(&bp->vf2pf_mbox->resp, 0,
13316                                sizeof(union pfvf_tlvs));
13317                 } else {
13318                         /* PF reports error */
13319                         BNX2X_ERR("Failed to get the requested amount of resources: %d. Breaking...\n",
13320                                   bp->acquire_resp.hdr.status);
13321                         return -EAGAIN;
13322                 }
13323         }
13324
13325         /* get HW info */
13326         bp->common.chip_id |= (bp->acquire_resp.pfdev_info.chip_num & 0xffff);
13327         bp->link_params.chip_id = bp->common.chip_id;
13328         bp->db_size = bp->acquire_resp.pfdev_info.db_size;
13329         bp->common.int_block = INT_BLOCK_IGU;
13330         bp->common.chip_port_mode = CHIP_2_PORT_MODE;
13331         bp->igu_dsb_id = -1;
13332         bp->mf_ov = 0;
13333         bp->mf_mode = 0;
13334         bp->common.flash_size = 0;
13335         bp->flags |=
13336                 NO_WOL_FLAG | NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG | NO_FCOE_FLAG;
13337         bp->igu_sb_cnt = 1;
13338         bp->igu_base_sb = bp->acquire_resp.resc.hw_sbs[0].hw_sb_id;
13339         strlcpy(bp->fw_ver, bp->acquire_resp.pfdev_info.fw_ver,
13340                 sizeof(bp->fw_ver));
13341
13342         if (is_valid_ether_addr(bp->acquire_resp.resc.current_mac_addr))
13343                 memcpy(bp->dev->dev_addr,
13344                        bp->acquire_resp.resc.current_mac_addr,
13345                        ETH_ALEN);
13346
13347         return 0;
13348 }
13349
13350 int bnx2x_vfpf_release(struct bnx2x *bp)
13351 {
13352         struct vfpf_release_tlv *req = &bp->vf2pf_mbox->req.release;
13353         struct pfvf_general_resp_tlv *resp = &bp->vf2pf_mbox->resp.general_resp;
13354         u32 rc = 0, vf_id;
13355
13356         /* clear mailbox and prep first tlv */
13357         bnx2x_vfpf_prep(bp, &req->first_tlv, CHANNEL_TLV_RELEASE, sizeof(*req));
13358
13359         if (bnx2x_get_vf_id(bp, &vf_id))
13360                 return -EAGAIN;
13361
13362         req->vf_id = vf_id;
13363
13364         /* add list termination tlv */
13365         bnx2x_add_tlv(bp, req, req->first_tlv.tl.length, CHANNEL_TLV_LIST_END,
13366                       sizeof(struct channel_list_end_tlv));
13367
13368         /* output tlvs list */
13369         bnx2x_dp_tlv_list(bp, req);
13370
13371         /* send release request */
13372         rc = bnx2x_send_msg2pf(bp, &resp->hdr.status, bp->vf2pf_mbox_mapping);
13373
13374         if (rc)
13375                 /* PF timeout */
13376                 return rc;
13377         if (resp->hdr.status == PFVF_STATUS_SUCCESS) {
13378                 /* PF released us */
13379                 DP(BNX2X_MSG_SP, "vf released\n");
13380         } else {
13381                 /* PF reports error */
13382                 BNX2X_ERR("PF failed our release request - are we out of sync? response status: %d\n",
13383                           resp->hdr.status);
13384                 return -EAGAIN;
13385         }
13386
13387         return 0;
13388 }