1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
32 e1000_mng_mode_none = 0,
36 e1000_mng_mode_host_if_only
39 #define E1000_FACTPS_MNGCG 0x20000000
41 /* Intel(R) Active Management Technology signature */
42 #define E1000_IAMT_SIGNATURE 0x544D4149
45 * e1000e_get_bus_info_pcie - Get PCIe bus information
46 * @hw: pointer to the HW structure
48 * Determines and stores the system bus information for a particular
49 * network interface. The following bus information is determined and stored:
50 * bus speed, bus width, type (PCIe), and PCIe function.
52 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
54 struct e1000_mac_info *mac = &hw->mac;
55 struct e1000_bus_info *bus = &hw->bus;
56 struct e1000_adapter *adapter = hw->adapter;
57 u16 pcie_link_status, cap_offset;
59 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
61 bus->width = e1000_bus_width_unknown;
63 pci_read_config_word(adapter->pdev,
64 cap_offset + PCIE_LINK_STATUS,
66 bus->width = (enum e1000_bus_width)((pcie_link_status &
67 PCIE_LINK_WIDTH_MASK) >>
68 PCIE_LINK_WIDTH_SHIFT);
71 mac->ops.set_lan_id(hw);
77 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
79 * @hw: pointer to the HW structure
81 * Determines the LAN function id by reading memory-mapped registers
82 * and swaps the port value if requested.
84 void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
86 struct e1000_bus_info *bus = &hw->bus;
90 * The status register reports the correct function number
91 * for the device regardless of function swap state.
94 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
98 * e1000_set_lan_id_single_port - Set LAN id for a single port device
99 * @hw: pointer to the HW structure
101 * Sets the LAN function id to zero for a single port device.
103 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
105 struct e1000_bus_info *bus = &hw->bus;
111 * e1000_clear_vfta_generic - Clear VLAN filter table
112 * @hw: pointer to the HW structure
114 * Clears the register array which contains the VLAN filter table by
115 * setting all the values to 0.
117 void e1000_clear_vfta_generic(struct e1000_hw *hw)
121 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
122 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
128 * e1000_write_vfta_generic - Write value to VLAN filter table
129 * @hw: pointer to the HW structure
130 * @offset: register offset in VLAN filter table
131 * @value: register value written to VLAN filter table
133 * Writes value at the given offset in the register array which stores
134 * the VLAN filter table.
136 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
138 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
143 * e1000e_init_rx_addrs - Initialize receive address's
144 * @hw: pointer to the HW structure
145 * @rar_count: receive address registers
147 * Setups the receive address registers by setting the base receive address
148 * register to the devices MAC address and clearing all the other receive
149 * address registers to 0.
151 void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
154 u8 mac_addr[ETH_ALEN] = {0};
156 /* Setup the receive address */
157 e_dbg("Programming MAC Address into RAR[0]\n");
159 e1000e_rar_set(hw, hw->mac.addr, 0);
161 /* Zero out the other (rar_entry_count - 1) receive addresses */
162 e_dbg("Clearing RAR[1-%u]\n", rar_count-1);
163 for (i = 1; i < rar_count; i++)
164 e1000e_rar_set(hw, mac_addr, i);
168 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
169 * @hw: pointer to the HW structure
171 * Checks the nvm for an alternate MAC address. An alternate MAC address
172 * can be setup by pre-boot software and must be treated like a permanent
173 * address and must override the actual permanent MAC address. If an
174 * alternate MAC address is found it is programmed into RAR0, replacing
175 * the permanent address that was installed into RAR0 by the Si on reset.
176 * This function will return SUCCESS unless it encounters an error while
177 * reading the EEPROM.
179 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
183 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
184 u8 alt_mac_addr[ETH_ALEN];
186 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1,
187 &nvm_alt_mac_addr_offset);
189 e_dbg("NVM Read Error\n");
193 if (nvm_alt_mac_addr_offset == 0xFFFF) {
194 /* There is no Alternate MAC Address */
198 if (hw->bus.func == E1000_FUNC_1)
199 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
200 for (i = 0; i < ETH_ALEN; i += 2) {
201 offset = nvm_alt_mac_addr_offset + (i >> 1);
202 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
204 e_dbg("NVM Read Error\n");
208 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
209 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
212 /* if multicast bit is set, the alternate address will not be used */
213 if (alt_mac_addr[0] & 0x01) {
214 e_dbg("Ignoring Alternate Mac Address with MC bit set\n");
219 * We have a valid alternate MAC address, and we want to treat it the
220 * same as the normal permanent MAC address stored by the HW into the
221 * RAR. Do this by mapping this address into RAR0.
223 e1000e_rar_set(hw, alt_mac_addr, 0);
230 * e1000e_rar_set - Set receive address register
231 * @hw: pointer to the HW structure
232 * @addr: pointer to the receive address
233 * @index: receive address array register
235 * Sets the receive address array register at index to the address passed
238 void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
240 u32 rar_low, rar_high;
243 * HW expects these in little endian so we reverse the byte order
244 * from network order (big endian) to little endian
246 rar_low = ((u32) addr[0] |
247 ((u32) addr[1] << 8) |
248 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
250 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
252 /* If MAC address zero, no need to set the AV bit */
253 if (rar_low || rar_high)
254 rar_high |= E1000_RAH_AV;
257 * Some bridges will combine consecutive 32-bit writes into
258 * a single burst write, which will malfunction on some parts.
259 * The flushes avoid this.
261 ew32(RAL(index), rar_low);
263 ew32(RAH(index), rar_high);
268 * e1000_hash_mc_addr - Generate a multicast hash value
269 * @hw: pointer to the HW structure
270 * @mc_addr: pointer to a multicast address
272 * Generates a multicast address hash value which is used to determine
273 * the multicast filter table array address and new table value. See
274 * e1000_mta_set_generic()
276 static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
278 u32 hash_value, hash_mask;
281 /* Register count multiplied by bits per register */
282 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
285 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
286 * where 0xFF would still fall within the hash mask.
288 while (hash_mask >> bit_shift != 0xFF)
292 * The portion of the address that is used for the hash table
293 * is determined by the mc_filter_type setting.
294 * The algorithm is such that there is a total of 8 bits of shifting.
295 * The bit_shift for a mc_filter_type of 0 represents the number of
296 * left-shifts where the MSB of mc_addr[5] would still fall within
297 * the hash_mask. Case 0 does this exactly. Since there are a total
298 * of 8 bits of shifting, then mc_addr[4] will shift right the
299 * remaining number of bits. Thus 8 - bit_shift. The rest of the
300 * cases are a variation of this algorithm...essentially raising the
301 * number of bits to shift mc_addr[5] left, while still keeping the
302 * 8-bit shifting total.
304 * For example, given the following Destination MAC Address and an
305 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
306 * we can see that the bit_shift for case 0 is 4. These are the hash
307 * values resulting from each mc_filter_type...
308 * [0] [1] [2] [3] [4] [5]
312 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
313 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
314 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
315 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
317 switch (hw->mac.mc_filter_type) {
332 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
333 (((u16) mc_addr[5]) << bit_shift)));
339 * e1000e_update_mc_addr_list_generic - Update Multicast addresses
340 * @hw: pointer to the HW structure
341 * @mc_addr_list: array of multicast addresses to program
342 * @mc_addr_count: number of multicast addresses to program
343 * @rar_used_count: the first RAR register free to program
344 * @rar_count: total number of supported Receive Address Registers
346 * Updates the Receive Address Registers and Multicast Table Array.
347 * The caller must have a packed mc_addr_list of multicast addresses.
348 * The parameter rar_count will usually be hw->mac.rar_entry_count
349 * unless there are workarounds that change this.
351 void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
352 u8 *mc_addr_list, u32 mc_addr_count,
353 u32 rar_used_count, u32 rar_count)
356 u32 *mcarray = kzalloc(hw->mac.mta_reg_count * sizeof(u32), GFP_ATOMIC);
359 printk(KERN_ERR "multicast array memory allocation failed\n");
364 * Load the first set of multicast addresses into the exact
365 * filters (RAR). If there are not enough to fill the RAR
366 * array, clear the filters.
368 for (i = rar_used_count; i < rar_count; i++) {
370 e1000e_rar_set(hw, mc_addr_list, i);
372 mc_addr_list += ETH_ALEN;
374 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
376 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
381 /* Load any remaining multicast addresses into the hash table. */
382 for (; mc_addr_count > 0; mc_addr_count--) {
383 u32 hash_value, hash_reg, hash_bit, mta;
384 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
385 e_dbg("Hash value = 0x%03X\n", hash_value);
386 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
387 hash_bit = hash_value & 0x1F;
388 mta = (1 << hash_bit);
389 mcarray[hash_reg] |= mta;
390 mc_addr_list += ETH_ALEN;
393 /* write the hash table completely */
394 for (i = 0; i < hw->mac.mta_reg_count; i++)
395 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, mcarray[i]);
402 * e1000e_clear_hw_cntrs_base - Clear base hardware counters
403 * @hw: pointer to the HW structure
405 * Clears the base hardware counters by reading the counter registers.
407 void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw)
449 * e1000e_check_for_copper_link - Check for link (Copper)
450 * @hw: pointer to the HW structure
452 * Checks to see of the link status of the hardware has changed. If a
453 * change in link status has been detected, then we read the PHY registers
454 * to get the current speed/duplex if link exists.
456 s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
458 struct e1000_mac_info *mac = &hw->mac;
463 * We only want to go out to the PHY registers to see if Auto-Neg
464 * has completed and/or if our link status has changed. The
465 * get_link_status flag is set upon receiving a Link Status
466 * Change or Rx Sequence Error interrupt.
468 if (!mac->get_link_status)
472 * First we want to see if the MII Status Register reports
473 * link. If so, then we want to get the current speed/duplex
476 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
481 return ret_val; /* No link detected */
483 mac->get_link_status = false;
486 * Check if there was DownShift, must be checked
487 * immediately after link-up
489 e1000e_check_downshift(hw);
492 * If we are forcing speed/duplex, then we simply return since
493 * we have already determined whether we have link or not.
496 ret_val = -E1000_ERR_CONFIG;
501 * Auto-Neg is enabled. Auto Speed Detection takes care
502 * of MAC speed/duplex configuration. So we only need to
503 * configure Collision Distance in the MAC.
505 e1000e_config_collision_dist(hw);
508 * Configure Flow Control now that Auto-Neg has completed.
509 * First, we need to restore the desired flow control
510 * settings because we may have had to re-autoneg with a
511 * different link partner.
513 ret_val = e1000e_config_fc_after_link_up(hw);
515 e_dbg("Error configuring flow control\n");
522 * e1000e_check_for_fiber_link - Check for link (Fiber)
523 * @hw: pointer to the HW structure
525 * Checks for link up on the hardware. If link is not up and we have
526 * a signal, then we need to force link up.
528 s32 e1000e_check_for_fiber_link(struct e1000_hw *hw)
530 struct e1000_mac_info *mac = &hw->mac;
537 status = er32(STATUS);
541 * If we don't have link (auto-negotiation failed or link partner
542 * cannot auto-negotiate), the cable is plugged in (we have signal),
543 * and our link partner is not trying to auto-negotiate with us (we
544 * are receiving idles or data), we need to force link up. We also
545 * need to give auto-negotiation time to complete, in case the cable
546 * was just plugged in. The autoneg_failed flag does this.
548 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
549 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
550 (!(rxcw & E1000_RXCW_C))) {
551 if (mac->autoneg_failed == 0) {
552 mac->autoneg_failed = 1;
555 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
557 /* Disable auto-negotiation in the TXCW register */
558 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
560 /* Force link-up and also force full-duplex. */
562 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
565 /* Configure Flow Control after forcing link up. */
566 ret_val = e1000e_config_fc_after_link_up(hw);
568 e_dbg("Error configuring flow control\n");
571 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
573 * If we are forcing link and we are receiving /C/ ordered
574 * sets, re-enable auto-negotiation in the TXCW register
575 * and disable forced link in the Device Control register
576 * in an attempt to auto-negotiate with our link partner.
578 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
579 ew32(TXCW, mac->txcw);
580 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
582 mac->serdes_has_link = true;
589 * e1000e_check_for_serdes_link - Check for link (Serdes)
590 * @hw: pointer to the HW structure
592 * Checks for link up on the hardware. If link is not up and we have
593 * a signal, then we need to force link up.
595 s32 e1000e_check_for_serdes_link(struct e1000_hw *hw)
597 struct e1000_mac_info *mac = &hw->mac;
604 status = er32(STATUS);
608 * If we don't have link (auto-negotiation failed or link partner
609 * cannot auto-negotiate), and our link partner is not trying to
610 * auto-negotiate with us (we are receiving idles or data),
611 * we need to force link up. We also need to give auto-negotiation
614 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
615 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
616 if (mac->autoneg_failed == 0) {
617 mac->autoneg_failed = 1;
620 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
622 /* Disable auto-negotiation in the TXCW register */
623 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
625 /* Force link-up and also force full-duplex. */
627 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
630 /* Configure Flow Control after forcing link up. */
631 ret_val = e1000e_config_fc_after_link_up(hw);
633 e_dbg("Error configuring flow control\n");
636 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
638 * If we are forcing link and we are receiving /C/ ordered
639 * sets, re-enable auto-negotiation in the TXCW register
640 * and disable forced link in the Device Control register
641 * in an attempt to auto-negotiate with our link partner.
643 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
644 ew32(TXCW, mac->txcw);
645 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
647 mac->serdes_has_link = true;
648 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
650 * If we force link for non-auto-negotiation switch, check
651 * link status based on MAC synchronization for internal
654 /* SYNCH bit and IV bit are sticky. */
657 if (rxcw & E1000_RXCW_SYNCH) {
658 if (!(rxcw & E1000_RXCW_IV)) {
659 mac->serdes_has_link = true;
660 e_dbg("SERDES: Link up - forced.\n");
663 mac->serdes_has_link = false;
664 e_dbg("SERDES: Link down - force failed.\n");
668 if (E1000_TXCW_ANE & er32(TXCW)) {
669 status = er32(STATUS);
670 if (status & E1000_STATUS_LU) {
671 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
674 if (rxcw & E1000_RXCW_SYNCH) {
675 if (!(rxcw & E1000_RXCW_IV)) {
676 mac->serdes_has_link = true;
677 e_dbg("SERDES: Link up - autoneg "
678 "completed sucessfully.\n");
680 mac->serdes_has_link = false;
681 e_dbg("SERDES: Link down - invalid"
682 "codewords detected in autoneg.\n");
685 mac->serdes_has_link = false;
686 e_dbg("SERDES: Link down - no sync.\n");
689 mac->serdes_has_link = false;
690 e_dbg("SERDES: Link down - autoneg failed\n");
698 * e1000_set_default_fc_generic - Set flow control default values
699 * @hw: pointer to the HW structure
701 * Read the EEPROM for the default values for flow control and store the
704 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
710 * Read and store word 0x0F of the EEPROM. This word contains bits
711 * that determine the hardware's default PAUSE (flow control) mode,
712 * a bit that determines whether the HW defaults to enabling or
713 * disabling auto-negotiation, and the direction of the
714 * SW defined pins. If there is no SW over-ride of the flow
715 * control setting, then the variable hw->fc will
716 * be initialized based on a value in the EEPROM.
718 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
721 e_dbg("NVM Read Error\n");
725 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
726 hw->fc.requested_mode = e1000_fc_none;
727 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
729 hw->fc.requested_mode = e1000_fc_tx_pause;
731 hw->fc.requested_mode = e1000_fc_full;
737 * e1000e_setup_link - Setup flow control and link settings
738 * @hw: pointer to the HW structure
740 * Determines which flow control settings to use, then configures flow
741 * control. Calls the appropriate media-specific link configuration
742 * function. Assuming the adapter has a valid link partner, a valid link
743 * should be established. Assumes the hardware has previously been reset
744 * and the transmitter and receiver are not enabled.
746 s32 e1000e_setup_link(struct e1000_hw *hw)
748 struct e1000_mac_info *mac = &hw->mac;
752 * In the case of the phy reset being blocked, we already have a link.
753 * We do not need to set it up again.
755 if (e1000_check_reset_block(hw))
759 * If requested flow control is set to default, set flow control
760 * based on the EEPROM flow control settings.
762 if (hw->fc.requested_mode == e1000_fc_default) {
763 ret_val = e1000_set_default_fc_generic(hw);
769 * Save off the requested flow control mode for use later. Depending
770 * on the link partner's capabilities, we may or may not use this mode.
772 hw->fc.current_mode = hw->fc.requested_mode;
774 e_dbg("After fix-ups FlowControl is now = %x\n",
775 hw->fc.current_mode);
777 /* Call the necessary media_type subroutine to configure the link. */
778 ret_val = mac->ops.setup_physical_interface(hw);
783 * Initialize the flow control address, type, and PAUSE timer
784 * registers to their default values. This is done even if flow
785 * control is disabled, because it does not hurt anything to
786 * initialize these registers.
788 e_dbg("Initializing the Flow Control address, type and timer regs\n");
789 ew32(FCT, FLOW_CONTROL_TYPE);
790 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
791 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
793 ew32(FCTTV, hw->fc.pause_time);
795 return e1000e_set_fc_watermarks(hw);
799 * e1000_commit_fc_settings_generic - Configure flow control
800 * @hw: pointer to the HW structure
802 * Write the flow control settings to the Transmit Config Word Register (TXCW)
803 * base on the flow control settings in e1000_mac_info.
805 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
807 struct e1000_mac_info *mac = &hw->mac;
811 * Check for a software override of the flow control settings, and
812 * setup the device accordingly. If auto-negotiation is enabled, then
813 * software will have to set the "PAUSE" bits to the correct value in
814 * the Transmit Config Word Register (TXCW) and re-start auto-
815 * negotiation. However, if auto-negotiation is disabled, then
816 * software will have to manually configure the two flow control enable
817 * bits in the CTRL register.
819 * The possible values of the "fc" parameter are:
820 * 0: Flow control is completely disabled
821 * 1: Rx flow control is enabled (we can receive pause frames,
822 * but not send pause frames).
823 * 2: Tx flow control is enabled (we can send pause frames but we
824 * do not support receiving pause frames).
825 * 3: Both Rx and Tx flow control (symmetric) are enabled.
827 switch (hw->fc.current_mode) {
829 /* Flow control completely disabled by a software over-ride. */
830 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
832 case e1000_fc_rx_pause:
834 * Rx Flow control is enabled and Tx Flow control is disabled
835 * by a software over-ride. Since there really isn't a way to
836 * advertise that we are capable of Rx Pause ONLY, we will
837 * advertise that we support both symmetric and asymmetric Rx
838 * PAUSE. Later, we will disable the adapter's ability to send
841 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
843 case e1000_fc_tx_pause:
845 * Tx Flow control is enabled, and Rx Flow control is disabled,
846 * by a software over-ride.
848 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
852 * Flow control (both Rx and Tx) is enabled by a software
855 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
858 e_dbg("Flow control param set incorrectly\n");
859 return -E1000_ERR_CONFIG;
870 * e1000_poll_fiber_serdes_link_generic - Poll for link up
871 * @hw: pointer to the HW structure
873 * Polls for link up by reading the status register, if link fails to come
874 * up with auto-negotiation, then the link is forced if a signal is detected.
876 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
878 struct e1000_mac_info *mac = &hw->mac;
883 * If we have a signal (the cable is plugged in, or assumed true for
884 * serdes media) then poll for a "Link-Up" indication in the Device
885 * Status Register. Time-out if a link isn't seen in 500 milliseconds
886 * seconds (Auto-negotiation should complete in less than 500
887 * milliseconds even if the other end is doing it in SW).
889 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
891 status = er32(STATUS);
892 if (status & E1000_STATUS_LU)
895 if (i == FIBER_LINK_UP_LIMIT) {
896 e_dbg("Never got a valid link from auto-neg!!!\n");
897 mac->autoneg_failed = 1;
899 * AutoNeg failed to achieve a link, so we'll call
900 * mac->check_for_link. This routine will force the
901 * link up if we detect a signal. This will allow us to
902 * communicate with non-autonegotiating link partners.
904 ret_val = mac->ops.check_for_link(hw);
906 e_dbg("Error while checking for link\n");
909 mac->autoneg_failed = 0;
911 mac->autoneg_failed = 0;
912 e_dbg("Valid Link Found\n");
919 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes
920 * @hw: pointer to the HW structure
922 * Configures collision distance and flow control for fiber and serdes
923 * links. Upon successful setup, poll for link.
925 s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw)
932 /* Take the link out of reset */
933 ctrl &= ~E1000_CTRL_LRST;
935 e1000e_config_collision_dist(hw);
937 ret_val = e1000_commit_fc_settings_generic(hw);
942 * Since auto-negotiation is enabled, take the link out of reset (the
943 * link will be in reset, because we previously reset the chip). This
944 * will restart auto-negotiation. If auto-negotiation is successful
945 * then the link-up status bit will be set and the flow control enable
946 * bits (RFCE and TFCE) will be set according to their negotiated value.
948 e_dbg("Auto-negotiation enabled\n");
955 * For these adapters, the SW definable pin 1 is set when the optics
956 * detect a signal. If we have a signal, then poll for a "Link-Up"
959 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
960 (er32(CTRL) & E1000_CTRL_SWDPIN1)) {
961 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
963 e_dbg("No signal detected\n");
970 * e1000e_config_collision_dist - Configure collision distance
971 * @hw: pointer to the HW structure
973 * Configures the collision distance to the default value and is used
974 * during link setup. Currently no func pointer exists and all
975 * implementations are handled in the generic version of this function.
977 void e1000e_config_collision_dist(struct e1000_hw *hw)
983 tctl &= ~E1000_TCTL_COLD;
984 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
991 * e1000e_set_fc_watermarks - Set flow control high/low watermarks
992 * @hw: pointer to the HW structure
994 * Sets the flow control high/low threshold (watermark) registers. If
995 * flow control XON frame transmission is enabled, then set XON frame
996 * transmission as well.
998 s32 e1000e_set_fc_watermarks(struct e1000_hw *hw)
1000 u32 fcrtl = 0, fcrth = 0;
1003 * Set the flow control receive threshold registers. Normally,
1004 * these registers will be set to a default threshold that may be
1005 * adjusted later by the driver's runtime code. However, if the
1006 * ability to transmit pause frames is not enabled, then these
1007 * registers will be set to 0.
1009 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1011 * We need to set up the Receive Threshold high and low water
1012 * marks as well as (optionally) enabling the transmission of
1015 fcrtl = hw->fc.low_water;
1016 fcrtl |= E1000_FCRTL_XONE;
1017 fcrth = hw->fc.high_water;
1026 * e1000e_force_mac_fc - Force the MAC's flow control settings
1027 * @hw: pointer to the HW structure
1029 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1030 * device control register to reflect the adapter settings. TFCE and RFCE
1031 * need to be explicitly set by software when a copper PHY is used because
1032 * autonegotiation is managed by the PHY rather than the MAC. Software must
1033 * also configure these bits when link is forced on a fiber connection.
1035 s32 e1000e_force_mac_fc(struct e1000_hw *hw)
1042 * Because we didn't get link via the internal auto-negotiation
1043 * mechanism (we either forced link or we got link via PHY
1044 * auto-neg), we have to manually enable/disable transmit an
1045 * receive flow control.
1047 * The "Case" statement below enables/disable flow control
1048 * according to the "hw->fc.current_mode" parameter.
1050 * The possible values of the "fc" parameter are:
1051 * 0: Flow control is completely disabled
1052 * 1: Rx flow control is enabled (we can receive pause
1053 * frames but not send pause frames).
1054 * 2: Tx flow control is enabled (we can send pause frames
1055 * frames but we do not receive pause frames).
1056 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1057 * other: No other values should be possible at this point.
1059 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1061 switch (hw->fc.current_mode) {
1063 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1065 case e1000_fc_rx_pause:
1066 ctrl &= (~E1000_CTRL_TFCE);
1067 ctrl |= E1000_CTRL_RFCE;
1069 case e1000_fc_tx_pause:
1070 ctrl &= (~E1000_CTRL_RFCE);
1071 ctrl |= E1000_CTRL_TFCE;
1074 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1077 e_dbg("Flow control param set incorrectly\n");
1078 return -E1000_ERR_CONFIG;
1087 * e1000e_config_fc_after_link_up - Configures flow control after link
1088 * @hw: pointer to the HW structure
1090 * Checks the status of auto-negotiation after link up to ensure that the
1091 * speed and duplex were not forced. If the link needed to be forced, then
1092 * flow control needs to be forced also. If auto-negotiation is enabled
1093 * and did not fail, then we configure flow control based on our link
1096 s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
1098 struct e1000_mac_info *mac = &hw->mac;
1100 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1104 * Check for the case where we have fiber media and auto-neg failed
1105 * so we had to force link. In this case, we need to force the
1106 * configuration of the MAC to match the "fc" parameter.
1108 if (mac->autoneg_failed) {
1109 if (hw->phy.media_type == e1000_media_type_fiber ||
1110 hw->phy.media_type == e1000_media_type_internal_serdes)
1111 ret_val = e1000e_force_mac_fc(hw);
1113 if (hw->phy.media_type == e1000_media_type_copper)
1114 ret_val = e1000e_force_mac_fc(hw);
1118 e_dbg("Error forcing flow control settings\n");
1123 * Check for the case where we have copper media and auto-neg is
1124 * enabled. In this case, we need to check and see if Auto-Neg
1125 * has completed, and if so, how the PHY and link partner has
1126 * flow control configured.
1128 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1130 * Read the MII Status Register and check to see if AutoNeg
1131 * has completed. We read this twice because this reg has
1132 * some "sticky" (latched) bits.
1134 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1137 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg);
1141 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1142 e_dbg("Copper PHY and Auto Neg "
1143 "has not completed.\n");
1148 * The AutoNeg process has completed, so we now need to
1149 * read both the Auto Negotiation Advertisement
1150 * Register (Address 4) and the Auto_Negotiation Base
1151 * Page Ability Register (Address 5) to determine how
1152 * flow control was negotiated.
1154 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
1157 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
1162 * Two bits in the Auto Negotiation Advertisement Register
1163 * (Address 4) and two bits in the Auto Negotiation Base
1164 * Page Ability Register (Address 5) determine flow control
1165 * for both the PHY and the link partner. The following
1166 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1167 * 1999, describes these PAUSE resolution bits and how flow
1168 * control is determined based upon these settings.
1169 * NOTE: DC = Don't Care
1171 * LOCAL DEVICE | LINK PARTNER
1172 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1173 *-------|---------|-------|---------|--------------------
1174 * 0 | 0 | DC | DC | e1000_fc_none
1175 * 0 | 1 | 0 | DC | e1000_fc_none
1176 * 0 | 1 | 1 | 0 | e1000_fc_none
1177 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1178 * 1 | 0 | 0 | DC | e1000_fc_none
1179 * 1 | DC | 1 | DC | e1000_fc_full
1180 * 1 | 1 | 0 | 0 | e1000_fc_none
1181 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1183 * Are both PAUSE bits set to 1? If so, this implies
1184 * Symmetric Flow Control is enabled at both ends. The
1185 * ASM_DIR bits are irrelevant per the spec.
1187 * For Symmetric Flow Control:
1189 * LOCAL DEVICE | LINK PARTNER
1190 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1191 *-------|---------|-------|---------|--------------------
1192 * 1 | DC | 1 | DC | E1000_fc_full
1195 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1196 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1198 * Now we need to check if the user selected Rx ONLY
1199 * of pause frames. In this case, we had to advertise
1200 * FULL flow control because we could not advertise Rx
1201 * ONLY. Hence, we must now check to see if we need to
1202 * turn OFF the TRANSMISSION of PAUSE frames.
1204 if (hw->fc.requested_mode == e1000_fc_full) {
1205 hw->fc.current_mode = e1000_fc_full;
1206 e_dbg("Flow Control = FULL.\r\n");
1208 hw->fc.current_mode = e1000_fc_rx_pause;
1209 e_dbg("Flow Control = "
1210 "RX PAUSE frames only.\r\n");
1214 * For receiving PAUSE frames ONLY.
1216 * LOCAL DEVICE | LINK PARTNER
1217 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1218 *-------|---------|-------|---------|--------------------
1219 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1221 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1222 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1223 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1224 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1225 hw->fc.current_mode = e1000_fc_tx_pause;
1226 e_dbg("Flow Control = Tx PAUSE frames only.\r\n");
1229 * For transmitting PAUSE frames ONLY.
1231 * LOCAL DEVICE | LINK PARTNER
1232 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1233 *-------|---------|-------|---------|--------------------
1234 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1236 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1237 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1238 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1239 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1240 hw->fc.current_mode = e1000_fc_rx_pause;
1241 e_dbg("Flow Control = Rx PAUSE frames only.\r\n");
1244 * Per the IEEE spec, at this point flow control
1245 * should be disabled.
1247 hw->fc.current_mode = e1000_fc_none;
1248 e_dbg("Flow Control = NONE.\r\n");
1252 * Now we need to do one last check... If we auto-
1253 * negotiated to HALF DUPLEX, flow control should not be
1254 * enabled per IEEE 802.3 spec.
1256 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1258 e_dbg("Error getting link speed and duplex\n");
1262 if (duplex == HALF_DUPLEX)
1263 hw->fc.current_mode = e1000_fc_none;
1266 * Now we call a subroutine to actually force the MAC
1267 * controller to use the correct flow control settings.
1269 ret_val = e1000e_force_mac_fc(hw);
1271 e_dbg("Error forcing flow control settings\n");
1280 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex
1281 * @hw: pointer to the HW structure
1282 * @speed: stores the current speed
1283 * @duplex: stores the current duplex
1285 * Read the status register for the current speed/duplex and store the current
1286 * speed and duplex for copper connections.
1288 s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1292 status = er32(STATUS);
1293 if (status & E1000_STATUS_SPEED_1000) {
1294 *speed = SPEED_1000;
1295 e_dbg("1000 Mbs, ");
1296 } else if (status & E1000_STATUS_SPEED_100) {
1304 if (status & E1000_STATUS_FD) {
1305 *duplex = FULL_DUPLEX;
1306 e_dbg("Full Duplex\n");
1308 *duplex = HALF_DUPLEX;
1309 e_dbg("Half Duplex\n");
1316 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex
1317 * @hw: pointer to the HW structure
1318 * @speed: stores the current speed
1319 * @duplex: stores the current duplex
1321 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1322 * for fiber/serdes links.
1324 s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1326 *speed = SPEED_1000;
1327 *duplex = FULL_DUPLEX;
1333 * e1000e_get_hw_semaphore - Acquire hardware semaphore
1334 * @hw: pointer to the HW structure
1336 * Acquire the HW semaphore to access the PHY or NVM
1338 s32 e1000e_get_hw_semaphore(struct e1000_hw *hw)
1341 s32 timeout = hw->nvm.word_size + 1;
1344 /* Get the SW semaphore */
1345 while (i < timeout) {
1347 if (!(swsm & E1000_SWSM_SMBI))
1355 e_dbg("Driver can't access device - SMBI bit is set.\n");
1356 return -E1000_ERR_NVM;
1359 /* Get the FW semaphore. */
1360 for (i = 0; i < timeout; i++) {
1362 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
1364 /* Semaphore acquired if bit latched */
1365 if (er32(SWSM) & E1000_SWSM_SWESMBI)
1372 /* Release semaphores */
1373 e1000e_put_hw_semaphore(hw);
1374 e_dbg("Driver can't access the NVM\n");
1375 return -E1000_ERR_NVM;
1382 * e1000e_put_hw_semaphore - Release hardware semaphore
1383 * @hw: pointer to the HW structure
1385 * Release hardware semaphore used to access the PHY or NVM
1387 void e1000e_put_hw_semaphore(struct e1000_hw *hw)
1392 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1397 * e1000e_get_auto_rd_done - Check for auto read completion
1398 * @hw: pointer to the HW structure
1400 * Check EEPROM for Auto Read done bit.
1402 s32 e1000e_get_auto_rd_done(struct e1000_hw *hw)
1406 while (i < AUTO_READ_DONE_TIMEOUT) {
1407 if (er32(EECD) & E1000_EECD_AUTO_RD)
1413 if (i == AUTO_READ_DONE_TIMEOUT) {
1414 e_dbg("Auto read by HW from NVM has not completed.\n");
1415 return -E1000_ERR_RESET;
1422 * e1000e_valid_led_default - Verify a valid default LED config
1423 * @hw: pointer to the HW structure
1424 * @data: pointer to the NVM (EEPROM)
1426 * Read the EEPROM for the current default LED configuration. If the
1427 * LED configuration is not valid, set to a valid LED configuration.
1429 s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data)
1433 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1435 e_dbg("NVM Read Error\n");
1439 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1440 *data = ID_LED_DEFAULT;
1446 * e1000e_id_led_init -
1447 * @hw: pointer to the HW structure
1450 s32 e1000e_id_led_init(struct e1000_hw *hw)
1452 struct e1000_mac_info *mac = &hw->mac;
1454 const u32 ledctl_mask = 0x000000FF;
1455 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1456 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1458 const u16 led_mask = 0x0F;
1460 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1464 mac->ledctl_default = er32(LEDCTL);
1465 mac->ledctl_mode1 = mac->ledctl_default;
1466 mac->ledctl_mode2 = mac->ledctl_default;
1468 for (i = 0; i < 4; i++) {
1469 temp = (data >> (i << 2)) & led_mask;
1471 case ID_LED_ON1_DEF2:
1472 case ID_LED_ON1_ON2:
1473 case ID_LED_ON1_OFF2:
1474 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1475 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1477 case ID_LED_OFF1_DEF2:
1478 case ID_LED_OFF1_ON2:
1479 case ID_LED_OFF1_OFF2:
1480 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1481 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1488 case ID_LED_DEF1_ON2:
1489 case ID_LED_ON1_ON2:
1490 case ID_LED_OFF1_ON2:
1491 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1492 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1494 case ID_LED_DEF1_OFF2:
1495 case ID_LED_ON1_OFF2:
1496 case ID_LED_OFF1_OFF2:
1497 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1498 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1510 * e1000e_setup_led_generic - Configures SW controllable LED
1511 * @hw: pointer to the HW structure
1513 * This prepares the SW controllable LED for use and saves the current state
1514 * of the LED so it can be later restored.
1516 s32 e1000e_setup_led_generic(struct e1000_hw *hw)
1520 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
1521 return -E1000_ERR_CONFIG;
1524 if (hw->phy.media_type == e1000_media_type_fiber) {
1525 ledctl = er32(LEDCTL);
1526 hw->mac.ledctl_default = ledctl;
1528 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1529 E1000_LEDCTL_LED0_BLINK |
1530 E1000_LEDCTL_LED0_MODE_MASK);
1531 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1532 E1000_LEDCTL_LED0_MODE_SHIFT);
1533 ew32(LEDCTL, ledctl);
1534 } else if (hw->phy.media_type == e1000_media_type_copper) {
1535 ew32(LEDCTL, hw->mac.ledctl_mode1);
1542 * e1000e_cleanup_led_generic - Set LED config to default operation
1543 * @hw: pointer to the HW structure
1545 * Remove the current LED configuration and set the LED configuration
1546 * to the default value, saved from the EEPROM.
1548 s32 e1000e_cleanup_led_generic(struct e1000_hw *hw)
1550 ew32(LEDCTL, hw->mac.ledctl_default);
1555 * e1000e_blink_led - Blink LED
1556 * @hw: pointer to the HW structure
1558 * Blink the LEDs which are set to be on.
1560 s32 e1000e_blink_led(struct e1000_hw *hw)
1562 u32 ledctl_blink = 0;
1565 if (hw->phy.media_type == e1000_media_type_fiber) {
1566 /* always blink LED0 for PCI-E fiber */
1567 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1568 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1571 * set the blink bit for each LED that's "on" (0x0E)
1574 ledctl_blink = hw->mac.ledctl_mode2;
1575 for (i = 0; i < 4; i++)
1576 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1577 E1000_LEDCTL_MODE_LED_ON)
1578 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1582 ew32(LEDCTL, ledctl_blink);
1588 * e1000e_led_on_generic - Turn LED on
1589 * @hw: pointer to the HW structure
1593 s32 e1000e_led_on_generic(struct e1000_hw *hw)
1597 switch (hw->phy.media_type) {
1598 case e1000_media_type_fiber:
1600 ctrl &= ~E1000_CTRL_SWDPIN0;
1601 ctrl |= E1000_CTRL_SWDPIO0;
1604 case e1000_media_type_copper:
1605 ew32(LEDCTL, hw->mac.ledctl_mode2);
1615 * e1000e_led_off_generic - Turn LED off
1616 * @hw: pointer to the HW structure
1620 s32 e1000e_led_off_generic(struct e1000_hw *hw)
1624 switch (hw->phy.media_type) {
1625 case e1000_media_type_fiber:
1627 ctrl |= E1000_CTRL_SWDPIN0;
1628 ctrl |= E1000_CTRL_SWDPIO0;
1631 case e1000_media_type_copper:
1632 ew32(LEDCTL, hw->mac.ledctl_mode1);
1642 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities
1643 * @hw: pointer to the HW structure
1644 * @no_snoop: bitmap of snoop events
1646 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1648 void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop)
1654 gcr &= ~(PCIE_NO_SNOOP_ALL);
1661 * e1000e_disable_pcie_master - Disables PCI-express master access
1662 * @hw: pointer to the HW structure
1664 * Returns 0 if successful, else returns -10
1665 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1666 * the master requests to be disabled.
1668 * Disables PCI-Express master access and verifies there are no pending
1671 s32 e1000e_disable_pcie_master(struct e1000_hw *hw)
1674 s32 timeout = MASTER_DISABLE_TIMEOUT;
1677 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1681 if (!(er32(STATUS) &
1682 E1000_STATUS_GIO_MASTER_ENABLE))
1689 e_dbg("Master requests are pending.\n");
1690 return -E1000_ERR_MASTER_REQUESTS_PENDING;
1697 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing
1698 * @hw: pointer to the HW structure
1700 * Reset the Adaptive Interframe Spacing throttle to default values.
1702 void e1000e_reset_adaptive(struct e1000_hw *hw)
1704 struct e1000_mac_info *mac = &hw->mac;
1706 if (!mac->adaptive_ifs) {
1707 e_dbg("Not in Adaptive IFS mode!\n");
1711 mac->current_ifs_val = 0;
1712 mac->ifs_min_val = IFS_MIN;
1713 mac->ifs_max_val = IFS_MAX;
1714 mac->ifs_step_size = IFS_STEP;
1715 mac->ifs_ratio = IFS_RATIO;
1717 mac->in_ifs_mode = false;
1724 * e1000e_update_adaptive - Update Adaptive Interframe Spacing
1725 * @hw: pointer to the HW structure
1727 * Update the Adaptive Interframe Spacing Throttle value based on the
1728 * time between transmitted packets and time between collisions.
1730 void e1000e_update_adaptive(struct e1000_hw *hw)
1732 struct e1000_mac_info *mac = &hw->mac;
1734 if (!mac->adaptive_ifs) {
1735 e_dbg("Not in Adaptive IFS mode!\n");
1739 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1740 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1741 mac->in_ifs_mode = true;
1742 if (mac->current_ifs_val < mac->ifs_max_val) {
1743 if (!mac->current_ifs_val)
1744 mac->current_ifs_val = mac->ifs_min_val;
1746 mac->current_ifs_val +=
1748 ew32(AIT, mac->current_ifs_val);
1752 if (mac->in_ifs_mode &&
1753 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1754 mac->current_ifs_val = 0;
1755 mac->in_ifs_mode = false;
1764 * e1000_raise_eec_clk - Raise EEPROM clock
1765 * @hw: pointer to the HW structure
1766 * @eecd: pointer to the EEPROM
1768 * Enable/Raise the EEPROM clock bit.
1770 static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
1772 *eecd = *eecd | E1000_EECD_SK;
1775 udelay(hw->nvm.delay_usec);
1779 * e1000_lower_eec_clk - Lower EEPROM clock
1780 * @hw: pointer to the HW structure
1781 * @eecd: pointer to the EEPROM
1783 * Clear/Lower the EEPROM clock bit.
1785 static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
1787 *eecd = *eecd & ~E1000_EECD_SK;
1790 udelay(hw->nvm.delay_usec);
1794 * e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
1795 * @hw: pointer to the HW structure
1796 * @data: data to send to the EEPROM
1797 * @count: number of bits to shift out
1799 * We need to shift 'count' bits out to the EEPROM. So, the value in the
1800 * "data" parameter will be shifted out to the EEPROM one bit at a time.
1801 * In order to do this, "data" must be broken down into bits.
1803 static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
1805 struct e1000_nvm_info *nvm = &hw->nvm;
1806 u32 eecd = er32(EECD);
1809 mask = 0x01 << (count - 1);
1810 if (nvm->type == e1000_nvm_eeprom_spi)
1811 eecd |= E1000_EECD_DO;
1814 eecd &= ~E1000_EECD_DI;
1817 eecd |= E1000_EECD_DI;
1822 udelay(nvm->delay_usec);
1824 e1000_raise_eec_clk(hw, &eecd);
1825 e1000_lower_eec_clk(hw, &eecd);
1830 eecd &= ~E1000_EECD_DI;
1835 * e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
1836 * @hw: pointer to the HW structure
1837 * @count: number of bits to shift in
1839 * In order to read a register from the EEPROM, we need to shift 'count' bits
1840 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
1841 * the EEPROM (setting the SK bit), and then reading the value of the data out
1842 * "DO" bit. During this "shifting in" process the data in "DI" bit should
1845 static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
1853 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
1856 for (i = 0; i < count; i++) {
1858 e1000_raise_eec_clk(hw, &eecd);
1862 eecd &= ~E1000_EECD_DI;
1863 if (eecd & E1000_EECD_DO)
1866 e1000_lower_eec_clk(hw, &eecd);
1873 * e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
1874 * @hw: pointer to the HW structure
1875 * @ee_reg: EEPROM flag for polling
1877 * Polls the EEPROM status bit for either read or write completion based
1878 * upon the value of 'ee_reg'.
1880 s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
1882 u32 attempts = 100000;
1885 for (i = 0; i < attempts; i++) {
1886 if (ee_reg == E1000_NVM_POLL_READ)
1891 if (reg & E1000_NVM_RW_REG_DONE)
1897 return -E1000_ERR_NVM;
1901 * e1000e_acquire_nvm - Generic request for access to EEPROM
1902 * @hw: pointer to the HW structure
1904 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
1905 * Return successful if access grant bit set, else clear the request for
1906 * EEPROM access and return -E1000_ERR_NVM (-1).
1908 s32 e1000e_acquire_nvm(struct e1000_hw *hw)
1910 u32 eecd = er32(EECD);
1911 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
1913 ew32(EECD, eecd | E1000_EECD_REQ);
1917 if (eecd & E1000_EECD_GNT)
1925 eecd &= ~E1000_EECD_REQ;
1927 e_dbg("Could not acquire NVM grant\n");
1928 return -E1000_ERR_NVM;
1935 * e1000_standby_nvm - Return EEPROM to standby state
1936 * @hw: pointer to the HW structure
1938 * Return the EEPROM to a standby state.
1940 static void e1000_standby_nvm(struct e1000_hw *hw)
1942 struct e1000_nvm_info *nvm = &hw->nvm;
1943 u32 eecd = er32(EECD);
1945 if (nvm->type == e1000_nvm_eeprom_spi) {
1946 /* Toggle CS to flush commands */
1947 eecd |= E1000_EECD_CS;
1950 udelay(nvm->delay_usec);
1951 eecd &= ~E1000_EECD_CS;
1954 udelay(nvm->delay_usec);
1959 * e1000_stop_nvm - Terminate EEPROM command
1960 * @hw: pointer to the HW structure
1962 * Terminates the current command by inverting the EEPROM's chip select pin.
1964 static void e1000_stop_nvm(struct e1000_hw *hw)
1969 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
1971 eecd |= E1000_EECD_CS;
1972 e1000_lower_eec_clk(hw, &eecd);
1977 * e1000e_release_nvm - Release exclusive access to EEPROM
1978 * @hw: pointer to the HW structure
1980 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
1982 void e1000e_release_nvm(struct e1000_hw *hw)
1989 eecd &= ~E1000_EECD_REQ;
1994 * e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
1995 * @hw: pointer to the HW structure
1997 * Setups the EEPROM for reading and writing.
1999 static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
2001 struct e1000_nvm_info *nvm = &hw->nvm;
2002 u32 eecd = er32(EECD);
2006 if (nvm->type == e1000_nvm_eeprom_spi) {
2007 /* Clear SK and CS */
2008 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2011 timeout = NVM_MAX_RETRY_SPI;
2014 * Read "Status Register" repeatedly until the LSB is cleared.
2015 * The EEPROM will signal that the command has been completed
2016 * by clearing bit 0 of the internal status register. If it's
2017 * not cleared within 'timeout', then error out.
2020 e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
2021 hw->nvm.opcode_bits);
2022 spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
2023 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
2027 e1000_standby_nvm(hw);
2032 e_dbg("SPI NVM Status error\n");
2033 return -E1000_ERR_NVM;
2041 * e1000e_read_nvm_eerd - Reads EEPROM using EERD register
2042 * @hw: pointer to the HW structure
2043 * @offset: offset of word in the EEPROM to read
2044 * @words: number of words to read
2045 * @data: word read from the EEPROM
2047 * Reads a 16 bit word from the EEPROM using the EERD register.
2049 s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2051 struct e1000_nvm_info *nvm = &hw->nvm;
2056 * A check for invalid values: offset too large, too many words,
2057 * too many words for the offset, and not enough words.
2059 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2061 e_dbg("nvm parameter(s) out of bounds\n");
2062 return -E1000_ERR_NVM;
2065 for (i = 0; i < words; i++) {
2066 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
2067 E1000_NVM_RW_REG_START;
2070 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
2074 data[i] = (er32(EERD) >> E1000_NVM_RW_REG_DATA);
2081 * e1000e_write_nvm_spi - Write to EEPROM using SPI
2082 * @hw: pointer to the HW structure
2083 * @offset: offset within the EEPROM to be written to
2084 * @words: number of words to write
2085 * @data: 16 bit word(s) to be written to the EEPROM
2087 * Writes data to EEPROM at offset using SPI interface.
2089 * If e1000e_update_nvm_checksum is not called after this function , the
2090 * EEPROM will most likely contain an invalid checksum.
2092 s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
2094 struct e1000_nvm_info *nvm = &hw->nvm;
2099 * A check for invalid values: offset too large, too many words,
2100 * and not enough words.
2102 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
2104 e_dbg("nvm parameter(s) out of bounds\n");
2105 return -E1000_ERR_NVM;
2108 ret_val = nvm->ops.acquire(hw);
2114 while (widx < words) {
2115 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
2117 ret_val = e1000_ready_nvm_eeprom(hw);
2119 nvm->ops.release(hw);
2123 e1000_standby_nvm(hw);
2125 /* Send the WRITE ENABLE command (8 bit opcode) */
2126 e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
2129 e1000_standby_nvm(hw);
2132 * Some SPI eeproms use the 8th address bit embedded in the
2135 if ((nvm->address_bits == 8) && (offset >= 128))
2136 write_opcode |= NVM_A8_OPCODE_SPI;
2138 /* Send the Write command (8-bit opcode + addr) */
2139 e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
2140 e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
2143 /* Loop to allow for up to whole page write of eeprom */
2144 while (widx < words) {
2145 u16 word_out = data[widx];
2146 word_out = (word_out >> 8) | (word_out << 8);
2147 e1000_shift_out_eec_bits(hw, word_out, 16);
2150 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
2151 e1000_standby_nvm(hw);
2158 nvm->ops.release(hw);
2163 * e1000_read_mac_addr_generic - Read device MAC address
2164 * @hw: pointer to the HW structure
2166 * Reads the device MAC address from the EEPROM and stores the value.
2167 * Since devices with two ports use the same EEPROM, we increment the
2168 * last bit in the MAC address for the second port.
2170 s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
2176 rar_high = er32(RAH(0));
2177 rar_low = er32(RAL(0));
2179 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
2180 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
2182 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
2183 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
2185 for (i = 0; i < ETH_ALEN; i++)
2186 hw->mac.addr[i] = hw->mac.perm_addr[i];
2192 * e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
2193 * @hw: pointer to the HW structure
2195 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2196 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2198 s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
2204 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
2205 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2207 e_dbg("NVM Read Error\n");
2210 checksum += nvm_data;
2213 if (checksum != (u16) NVM_SUM) {
2214 e_dbg("NVM Checksum Invalid\n");
2215 return -E1000_ERR_NVM;
2222 * e1000e_update_nvm_checksum_generic - Update EEPROM checksum
2223 * @hw: pointer to the HW structure
2225 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2226 * up to the checksum. Then calculates the EEPROM checksum and writes the
2227 * value to the EEPROM.
2229 s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
2235 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
2236 ret_val = e1000_read_nvm(hw, i, 1, &nvm_data);
2238 e_dbg("NVM Read Error while updating checksum.\n");
2241 checksum += nvm_data;
2243 checksum = (u16) NVM_SUM - checksum;
2244 ret_val = e1000_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
2246 e_dbg("NVM Write Error while updating checksum.\n");
2252 * e1000e_reload_nvm - Reloads EEPROM
2253 * @hw: pointer to the HW structure
2255 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
2256 * extended control register.
2258 void e1000e_reload_nvm(struct e1000_hw *hw)
2263 ctrl_ext = er32(CTRL_EXT);
2264 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
2265 ew32(CTRL_EXT, ctrl_ext);
2270 * e1000_calculate_checksum - Calculate checksum for buffer
2271 * @buffer: pointer to EEPROM
2272 * @length: size of EEPROM to calculate a checksum for
2274 * Calculates the checksum for some buffer on a specified length. The
2275 * checksum calculated is returned.
2277 static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
2285 for (i = 0; i < length; i++)
2288 return (u8) (0 - sum);
2292 * e1000_mng_enable_host_if - Checks host interface is enabled
2293 * @hw: pointer to the HW structure
2295 * Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
2297 * This function checks whether the HOST IF is enabled for command operation
2298 * and also checks whether the previous command is completed. It busy waits
2299 * in case of previous command is not completed.
2301 static s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
2306 /* Check that the host interface is enabled. */
2308 if ((hicr & E1000_HICR_EN) == 0) {
2309 e_dbg("E1000_HOST_EN bit disabled.\n");
2310 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2312 /* check the previous command is completed */
2313 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
2315 if (!(hicr & E1000_HICR_C))
2320 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2321 e_dbg("Previous command timeout failed .\n");
2322 return -E1000_ERR_HOST_INTERFACE_COMMAND;
2329 * e1000e_check_mng_mode_generic - check management mode
2330 * @hw: pointer to the HW structure
2332 * Reads the firmware semaphore register and returns true (>0) if
2333 * manageability is enabled, else false (0).
2335 bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
2337 u32 fwsm = er32(FWSM);
2339 return (fwsm & E1000_FWSM_MODE_MASK) ==
2340 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
2344 * e1000e_enable_tx_pkt_filtering - Enable packet filtering on Tx
2345 * @hw: pointer to the HW structure
2347 * Enables packet filtering on transmit packets if manageability is enabled
2348 * and host interface is enabled.
2350 bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
2352 struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
2353 u32 *buffer = (u32 *)&hw->mng_cookie;
2355 s32 ret_val, hdr_csum, csum;
2358 hw->mac.tx_pkt_filtering = true;
2360 /* No manageability, no filtering */
2361 if (!e1000e_check_mng_mode(hw)) {
2362 hw->mac.tx_pkt_filtering = false;
2367 * If we can't read from the host interface for whatever
2368 * reason, disable filtering.
2370 ret_val = e1000_mng_enable_host_if(hw);
2372 hw->mac.tx_pkt_filtering = false;
2376 /* Read in the header. Length and offset are in dwords. */
2377 len = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
2378 offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
2379 for (i = 0; i < len; i++)
2380 *(buffer + i) = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset + i);
2381 hdr_csum = hdr->checksum;
2383 csum = e1000_calculate_checksum((u8 *)hdr,
2384 E1000_MNG_DHCP_COOKIE_LENGTH);
2386 * If either the checksums or signature don't match, then
2387 * the cookie area isn't considered valid, in which case we
2388 * take the safe route of assuming Tx filtering is enabled.
2390 if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
2391 hw->mac.tx_pkt_filtering = true;
2395 /* Cookie area is valid, make the final check for filtering. */
2396 if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING)) {
2397 hw->mac.tx_pkt_filtering = false;
2402 return hw->mac.tx_pkt_filtering;
2406 * e1000_mng_write_cmd_header - Writes manageability command header
2407 * @hw: pointer to the HW structure
2408 * @hdr: pointer to the host interface command header
2410 * Writes the command header after does the checksum calculation.
2412 static s32 e1000_mng_write_cmd_header(struct e1000_hw *hw,
2413 struct e1000_host_mng_command_header *hdr)
2415 u16 i, length = sizeof(struct e1000_host_mng_command_header);
2417 /* Write the whole command header structure with new checksum. */
2419 hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
2422 /* Write the relevant command block into the ram area. */
2423 for (i = 0; i < length; i++) {
2424 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, i,
2425 *((u32 *) hdr + i));
2433 * e1000_mng_host_if_write - Write to the manageability host interface
2434 * @hw: pointer to the HW structure
2435 * @buffer: pointer to the host interface buffer
2436 * @length: size of the buffer
2437 * @offset: location in the buffer to write to
2438 * @sum: sum of the data (not checksum)
2440 * This function writes the buffer content at the offset given on the host if.
2441 * It also does alignment considerations to do the writes in most efficient
2442 * way. Also fills up the sum of the buffer in *buffer parameter.
2444 static s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer,
2445 u16 length, u16 offset, u8 *sum)
2448 u8 *bufptr = buffer;
2450 u16 remaining, i, j, prev_bytes;
2452 /* sum = only sum of the data and it is not checksum */
2454 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
2455 return -E1000_ERR_PARAM;
2458 prev_bytes = offset & 0x3;
2462 data = E1000_READ_REG_ARRAY(hw, E1000_HOST_IF, offset);
2463 for (j = prev_bytes; j < sizeof(u32); j++) {
2464 *(tmp + j) = *bufptr++;
2467 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset, data);
2468 length -= j - prev_bytes;
2472 remaining = length & 0x3;
2473 length -= remaining;
2475 /* Calculate length in DWORDs */
2479 * The device driver writes the relevant command block into the
2482 for (i = 0; i < length; i++) {
2483 for (j = 0; j < sizeof(u32); j++) {
2484 *(tmp + j) = *bufptr++;
2488 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2491 for (j = 0; j < sizeof(u32); j++) {
2493 *(tmp + j) = *bufptr++;
2499 E1000_WRITE_REG_ARRAY(hw, E1000_HOST_IF, offset + i, data);
2506 * e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
2507 * @hw: pointer to the HW structure
2508 * @buffer: pointer to the host interface
2509 * @length: size of the buffer
2511 * Writes the DHCP information to the host interface.
2513 s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)
2515 struct e1000_host_mng_command_header hdr;
2519 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
2520 hdr.command_length = length;
2525 /* Enable the host interface */
2526 ret_val = e1000_mng_enable_host_if(hw);
2530 /* Populate the host interface with the contents of "buffer". */
2531 ret_val = e1000_mng_host_if_write(hw, buffer, length,
2532 sizeof(hdr), &(hdr.checksum));
2536 /* Write the manageability command header */
2537 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
2541 /* Tell the ARC a new command is pending. */
2543 ew32(HICR, hicr | E1000_HICR_C);
2549 * e1000e_enable_mng_pass_thru - Enable processing of ARP's
2550 * @hw: pointer to the HW structure
2552 * Verifies the hardware needs to allow ARPs to be processed by the host.
2554 bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
2558 bool ret_val = false;
2562 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
2563 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
2566 if (hw->mac.arc_subsystem_valid) {
2568 factps = er32(FACTPS);
2570 if (!(factps & E1000_FACTPS_MNGCG) &&
2571 ((fwsm & E1000_FWSM_MODE_MASK) ==
2572 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
2577 if ((manc & E1000_MANC_SMBUS_EN) &&
2578 !(manc & E1000_MANC_ASF_EN)) {
2587 s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
2592 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
2594 e_dbg("NVM Read Error\n");
2597 *pba_num = (u32)(nvm_data << 16);
2599 ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
2601 e_dbg("NVM Read Error\n");
2604 *pba_num |= nvm_data;