drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  */
  52
  53 #include <linux/netdevice.h>
  54 #include <linux/ethtool.h>
  55 #include <linux/delay.h>
  56 #include <linux/pci.h>
  57
  58 #include "e1000.h"
  59
  60 #define ICH_FLASH_GFPREG                0x0000
  61 #define ICH_FLASH_HSFSTS                0x0004
  62 #define ICH_FLASH_HSFCTL                0x0006
  63 #define ICH_FLASH_FADDR                 0x0008
  64 #define ICH_FLASH_FDATA0                0x0010
  65 #define ICH_FLASH_PR0                   0x0074
  66
  67 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  70 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  71 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  72
  73 #define ICH_CYCLE_READ                  0
  74 #define ICH_CYCLE_WRITE                 2
  75 #define ICH_CYCLE_ERASE                 3
  76
  77 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  78 #define FLASH_SECTOR_ADDR_SHIFT         12
  79
  80 #define ICH_FLASH_SEG_SIZE_256          256
  81 #define ICH_FLASH_SEG_SIZE_4K           4096
  82 #define ICH_FLASH_SEG_SIZE_8K           8192
  83 #define ICH_FLASH_SEG_SIZE_64K          65536
  84
  85
  86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  87
  88 #define E1000_ICH_MNG_IAMT_MODE         0x2
  89
  90 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  91                                  (ID_LED_DEF1_OFF2 <<  8) | \
  92                                  (ID_LED_DEF1_ON2  <<  4) | \
  93                                  (ID_LED_DEF1_DEF2))
  94
  95 #define E1000_ICH_NVM_SIG_WORD          0x13
  96 #define E1000_ICH_NVM_SIG_MASK          0xC000
  97
  98 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
  99
 100 #define E1000_FEXTNVM_SW_CONFIG         1
 101 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 102
 103 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 104
 105 #define E1000_ICH_RAR_ENTRIES           7
 106
 107 #define PHY_PAGE_SHIFT 5
 108 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 109                            ((reg) & MAX_PHY_REG_ADDRESS))
 110 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 111 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 112
 113 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 114 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 115 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 116
 117 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 118 /* Offset 04h HSFSTS */
 119 union ich8_hws_flash_status {
 120         struct ich8_hsfsts {
 121                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 122                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 123                 u16 dael       :1; /* bit 2 Direct Access error Log */
 124                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 125                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 126                 u16 reserved1  :2; /* bit 13:6 Reserved */
 127                 u16 reserved2  :6; /* bit 13:6 Reserved */
 128                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 129                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 130         } hsf_status;
 131         u16 regval;
 132 };
 133
 134 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 135 /* Offset 06h FLCTL */
 136 union ich8_hws_flash_ctrl {
 137         struct ich8_hsflctl {
 138                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 139                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 140                 u16 reserved   :5;   /* 7:3 Reserved  */
 141                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 142                 u16 flockdn    :6;   /* 15:10 Reserved */
 143         } hsf_ctrl;
 144         u16 regval;
 145 };
 146
 147 /* ICH Flash Region Access Permissions */
 148 union ich8_hws_flash_regacc {
 149         struct ich8_flracc {
 150                 u32 grra      :8; /* 0:7 GbE region Read Access */
 151                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 152                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 153                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 154         } hsf_flregacc;
 155         u16 regval;
 156 };
 157
 158 /* ICH Flash Protected Region */
 159 union ich8_flash_protected_range {
 160         struct ich8_pr {
 161                 u32 base:13;     /* 0:12 Protected Range Base */
 162                 u32 reserved1:2; /* 13:14 Reserved */
 163                 u32 rpe:1;       /* 15 Read Protection Enable */
 164                 u32 limit:13;    /* 16:28 Protected Range Limit */
 165                 u32 reserved2:2; /* 29:30 Reserved */
 166                 u32 wpe:1;       /* 31 Write Protection Enable */
 167         } range;
 168         u32 regval;
 169 };
 170
 171 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 172 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 173 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 174 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 175 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 176 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 177                                                 u32 offset, u8 byte);
 178 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 179                                          u8 *data);
 180 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 181                                          u16 *data);
 182 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 183                                          u8 size, u16 *data);
 184 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 185 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 186 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 187
 188 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 189 {
 190         return readw(hw->flash_address + reg);
 191 }
 192
 193 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 194 {
 195         return readl(hw->flash_address + reg);
 196 }
 197
 198 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 199 {
 200         writew(val, hw->flash_address + reg);
 201 }
 202
 203 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 204 {
 205         writel(val, hw->flash_address + reg);
 206 }
 207
 208 #define er16flash(reg)          __er16flash(hw, (reg))
 209 #define er32flash(reg)          __er32flash(hw, (reg))
 210 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 211 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 212
 213 /**
 214  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 215  *  @hw: pointer to the HW structure
 216  *
 217  *  Initialize family-specific PHY parameters and function pointers.
 218  **/
 219 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 220 {
 221         struct e1000_phy_info *phy = &hw->phy;
 222         s32 ret_val;
 223         u16 i = 0;
 224
 225         phy->addr                       = 1;
 226         phy->reset_delay_us             = 100;
 227
 228         /*
 229          * We may need to do this twice - once for IGP and if that fails,
 230          * we'll set BM func pointers and try again
 231          */
 232         ret_val = e1000e_determine_phy_address(hw);
 233         if (ret_val) {
 234                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 235                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 236                 ret_val = e1000e_determine_phy_address(hw);
 237                 if (ret_val)
 238                         return ret_val;
 239         }
 240
 241         phy->id = 0;
 242         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 243                (i++ < 100)) {
 244                 msleep(1);
 245                 ret_val = e1000e_get_phy_id(hw);
 246                 if (ret_val)
 247                         return ret_val;
 248         }
 249
 250         /* Verify phy id */
 251         switch (phy->id) {
 252         case IGP03E1000_E_PHY_ID:
 253                 phy->type = e1000_phy_igp_3;
 254                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 255                 break;
 256         case IFE_E_PHY_ID:
 257         case IFE_PLUS_E_PHY_ID:
 258         case IFE_C_E_PHY_ID:
 259                 phy->type = e1000_phy_ife;
 260                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 261                 break;
 262         case BME1000_E_PHY_ID:
 263                 phy->type = e1000_phy_bm;
 264                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 265                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 266                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 267                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 268                 break;
 269         default:
 270                 return -E1000_ERR_PHY;
 271                 break;
 272         }
 273
 274         return 0;
 275 }
 276
 277 /**
 278  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 279  *  @hw: pointer to the HW structure
 280  *
 281  *  Initialize family-specific NVM parameters and function
 282  *  pointers.
 283  **/
 284 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 285 {
 286         struct e1000_nvm_info *nvm = &hw->nvm;
 287         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 288         u32 gfpreg;
 289         u32 sector_base_addr;
 290         u32 sector_end_addr;
 291         u16 i;
 292
 293         /* Can't read flash registers if the register set isn't mapped. */
 294         if (!hw->flash_address) {
 295                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 296                 return -E1000_ERR_CONFIG;
 297         }
 298
 299         nvm->type = e1000_nvm_flash_sw;
 300
 301         gfpreg = er32flash(ICH_FLASH_GFPREG);
 302
 303         /*
 304          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 305          * Add 1 to sector_end_addr since this sector is included in
 306          * the overall size.
 307          */
 308         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 309         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 310
 311         /* flash_base_addr is byte-aligned */
 312         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 313
 314         /*
 315          * find total size of the NVM, then cut in half since the total
 316          * size represents two separate NVM banks.
 317          */
 318         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 319                                 << FLASH_SECTOR_ADDR_SHIFT;
 320         nvm->flash_bank_size /= 2;
 321         /* Adjust to word count */
 322         nvm->flash_bank_size /= sizeof(u16);
 323
 324         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 325
 326         /* Clear shadow ram */
 327         for (i = 0; i < nvm->word_size; i++) {
 328                 dev_spec->shadow_ram[i].modified = 0;
 329                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 330         }
 331
 332         return 0;
 333 }
 334
 335 /**
 336  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 337  *  @hw: pointer to the HW structure
 338  *
 339  *  Initialize family-specific MAC parameters and function
 340  *  pointers.
 341  **/
 342 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 343 {
 344         struct e1000_hw *hw = &adapter->hw;
 345         struct e1000_mac_info *mac = &hw->mac;
 346
 347         /* Set media type function pointer */
 348         hw->phy.media_type = e1000_media_type_copper;
 349
 350         /* Set mta register count */
 351         mac->mta_reg_count = 32;
 352         /* Set rar entry count */
 353         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 354         if (mac->type == e1000_ich8lan)
 355                 mac->rar_entry_count--;
 356         /* Set if manageability features are enabled. */
 357         mac->arc_subsystem_valid = 1;
 358
 359         /* Enable PCS Lock-loss workaround for ICH8 */
 360         if (mac->type == e1000_ich8lan)
 361                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 362
 363         return 0;
 364 }
 365
 366 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 367 {
 368         struct e1000_hw *hw = &adapter->hw;
 369         s32 rc;
 370
 371         rc = e1000_init_mac_params_ich8lan(adapter);
 372         if (rc)
 373                 return rc;
 374
 375         rc = e1000_init_nvm_params_ich8lan(hw);
 376         if (rc)
 377                 return rc;
 378
 379         rc = e1000_init_phy_params_ich8lan(hw);
 380         if (rc)
 381                 return rc;
 382
 383         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 384             (adapter->hw.phy.type == e1000_phy_igp_3))
 385                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 386
 387         return 0;
 388 }
 389
 390 static DEFINE_MUTEX(nvm_mutex);
 391 static pid_t nvm_owner = -1;
 392
 393 /**
 394  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 395  *  @hw: pointer to the HW structure
 396  *
 397  *  Acquires the software control flag for performing NVM and PHY
 398  *  operations.  This is a function pointer entry point only called by
 399  *  read/write routines for the PHY and NVM parts.
 400  **/
 401 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 402 {
 403         u32 extcnf_ctrl;
 404         u32 timeout = PHY_CFG_TIMEOUT;
 405
 406         might_sleep();
 407
 408         if (!mutex_trylock(&nvm_mutex)) {
 409                 WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n",
 410                      nvm_owner);
 411                 mutex_lock(&nvm_mutex);
 412         }
 413         nvm_owner = current->pid;
 414
 415         while (timeout) {
 416                 extcnf_ctrl = er32(EXTCNF_CTRL);
 417                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 418                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 419
 420                 extcnf_ctrl = er32(EXTCNF_CTRL);
 421                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 422                         break;
 423                 mdelay(1);
 424                 timeout--;
 425         }
 426
 427         if (!timeout) {
 428                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 429                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 430                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 431                 nvm_owner = -1;
 432                 mutex_unlock(&nvm_mutex);
 433                 return -E1000_ERR_CONFIG;
 434         }
 435
 436         return 0;
 437 }
 438
 439 /**
 440  *  e1000_release_swflag_ich8lan - Release software control flag
 441  *  @hw: pointer to the HW structure
 442  *
 443  *  Releases the software control flag for performing NVM and PHY operations.
 444  *  This is a function pointer entry point only called by read/write
 445  *  routines for the PHY and NVM parts.
 446  **/
 447 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 448 {
 449         u32 extcnf_ctrl;
 450
 451         extcnf_ctrl = er32(EXTCNF_CTRL);
 452         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 453         ew32(EXTCNF_CTRL, extcnf_ctrl);
 454
 455         nvm_owner = -1;
 456         mutex_unlock(&nvm_mutex);
 457 }
 458
 459 /**
 460  *  e1000_check_mng_mode_ich8lan - Checks management mode
 461  *  @hw: pointer to the HW structure
 462  *
 463  *  This checks if the adapter has manageability enabled.
 464  *  This is a function pointer entry point only called by read/write
 465  *  routines for the PHY and NVM parts.
 466  **/
 467 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 468 {
 469         u32 fwsm = er32(FWSM);
 470
 471         return (fwsm & E1000_FWSM_MODE_MASK) ==
 472                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
 473 }
 474
 475 /**
 476  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 477  *  @hw: pointer to the HW structure
 478  *
 479  *  Checks if firmware is blocking the reset of the PHY.
 480  *  This is a function pointer entry point only called by
 481  *  reset routines.
 482  **/
 483 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 484 {
 485         u32 fwsm;
 486
 487         fwsm = er32(FWSM);
 488
 489         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 490 }
 491
 492 /**
 493  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 494  *  @hw: pointer to the HW structure
 495  *
 496  *  Forces the speed and duplex settings of the PHY.
 497  *  This is a function pointer entry point only called by
 498  *  PHY setup routines.
 499  **/
 500 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 501 {
 502         struct e1000_phy_info *phy = &hw->phy;
 503         s32 ret_val;
 504         u16 data;
 505         bool link;
 506
 507         if (phy->type != e1000_phy_ife) {
 508                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 509                 return ret_val;
 510         }
 511
 512         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 513         if (ret_val)
 514                 return ret_val;
 515
 516         e1000e_phy_force_speed_duplex_setup(hw, &data);
 517
 518         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 519         if (ret_val)
 520                 return ret_val;
 521
 522         /* Disable MDI-X support for 10/100 */
 523         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 524         if (ret_val)
 525                 return ret_val;
 526
 527         data &= ~IFE_PMC_AUTO_MDIX;
 528         data &= ~IFE_PMC_FORCE_MDIX;
 529
 530         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 531         if (ret_val)
 532                 return ret_val;
 533
 534         hw_dbg(hw, "IFE PMC: %X\n", data);
 535
 536         udelay(1);
 537
 538         if (phy->autoneg_wait_to_complete) {
 539                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 540
 541                 ret_val = e1000e_phy_has_link_generic(hw,
 542                                                      PHY_FORCE_LIMIT,
 543                                                      100000,
 544                                                      &link);
 545                 if (ret_val)
 546                         return ret_val;
 547
 548                 if (!link)
 549                         hw_dbg(hw, "Link taking longer than expected.\n");
 550
 551                 /* Try once more */
 552                 ret_val = e1000e_phy_has_link_generic(hw,
 553                                                      PHY_FORCE_LIMIT,
 554                                                      100000,
 555                                                      &link);
 556                 if (ret_val)
 557                         return ret_val;
 558         }
 559
 560         return 0;
 561 }
 562
 563 /**
 564  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 565  *  @hw: pointer to the HW structure
 566  *
 567  *  Resets the PHY
 568  *  This is a function pointer entry point called by drivers
 569  *  or other shared routines.
 570  **/
 571 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 572 {
 573         struct e1000_phy_info *phy = &hw->phy;
 574         u32 i;
 575         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 576         s32 ret_val;
 577         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 578         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 579
 580         ret_val = e1000e_phy_hw_reset_generic(hw);
 581         if (ret_val)
 582                 return ret_val;
 583
 584         /*
 585          * Initialize the PHY from the NVM on ICH platforms.  This
 586          * is needed due to an issue where the NVM configuration is
 587          * not properly autoloaded after power transitions.
 588          * Therefore, after each PHY reset, we will load the
 589          * configuration data out of the NVM manually.
 590          */
 591         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 592                 struct e1000_adapter *adapter = hw->adapter;
 593
 594                 /* Check if SW needs configure the PHY */
 595                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 596                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 597                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 598                 else
 599                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 600
 601                 data = er32(FEXTNVM);
 602                 if (!(data & sw_cfg_mask))
 603                         return 0;
 604
 605                 /* Wait for basic configuration completes before proceeding*/
 606                 do {
 607                         data = er32(STATUS);
 608                         data &= E1000_STATUS_LAN_INIT_DONE;
 609                         udelay(100);
 610                 } while ((!data) && --loop);
 611
 612                 /*
 613                  * If basic configuration is incomplete before the above loop
 614                  * count reaches 0, loading the configuration from NVM will
 615                  * leave the PHY in a bad state possibly resulting in no link.
 616                  */
 617                 if (loop == 0) {
 618                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 619                 }
 620
 621                 /* Clear the Init Done bit for the next init event */
 622                 data = er32(STATUS);
 623                 data &= ~E1000_STATUS_LAN_INIT_DONE;
 624                 ew32(STATUS, data);
 625
 626                 /*
 627                  * Make sure HW does not configure LCD from PHY
 628                  * extended configuration before SW configuration
 629                  */
 630                 data = er32(EXTCNF_CTRL);
 631                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 632                         return 0;
 633
 634                 cnf_size = er32(EXTCNF_SIZE);
 635                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 636                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 637                 if (!cnf_size)
 638                         return 0;
 639
 640                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 641                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 642
 643                 /* Configure LCD from extended configuration region. */
 644
 645                 /* cnf_base_addr is in DWORD */
 646                 word_addr = (u16)(cnf_base_addr << 1);
 647
 648                 for (i = 0; i < cnf_size; i++) {
 649                         ret_val = e1000_read_nvm(hw,
 650                                                 (word_addr + i * 2),
 651                                                 1,
 652                                                 &reg_data);
 653                         if (ret_val)
 654                                 return ret_val;
 655
 656                         ret_val = e1000_read_nvm(hw,
 657                                                 (word_addr + i * 2 + 1),
 658                                                 1,
 659                                                 &reg_addr);
 660                         if (ret_val)
 661                                 return ret_val;
 662
 663                         /* Save off the PHY page for future writes. */
 664                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 665                                 phy_page = reg_data;
 666                                 continue;
 667                         }
 668
 669                         reg_addr |= phy_page;
 670
 671                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 672                         if (ret_val)
 673                                 return ret_val;
 674                 }
 675         }
 676
 677         return 0;
 678 }
 679
 680 /**
 681  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 682  *  @hw: pointer to the HW structure
 683  *
 684  *  Populates "phy" structure with various feature states.
 685  *  This function is only called by other family-specific
 686  *  routines.
 687  **/
 688 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 689 {
 690         struct e1000_phy_info *phy = &hw->phy;
 691         s32 ret_val;
 692         u16 data;
 693         bool link;
 694
 695         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         if (!link) {
 700                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 701                 return -E1000_ERR_CONFIG;
 702         }
 703
 704         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 705         if (ret_val)
 706                 return ret_val;
 707         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 708
 709         if (phy->polarity_correction) {
 710                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
 711                 if (ret_val)
 712                         return ret_val;
 713         } else {
 714                 /* Polarity is forced */
 715                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 716                                       ? e1000_rev_polarity_reversed
 717                                       : e1000_rev_polarity_normal;
 718         }
 719
 720         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 721         if (ret_val)
 722                 return ret_val;
 723
 724         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 725
 726         /* The following parameters are undefined for 10/100 operation. */
 727         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 728         phy->local_rx = e1000_1000t_rx_status_undefined;
 729         phy->remote_rx = e1000_1000t_rx_status_undefined;
 730
 731         return 0;
 732 }
 733
 734 /**
 735  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 736  *  @hw: pointer to the HW structure
 737  *
 738  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 739  *  This is a function pointer entry point called by drivers
 740  *  or other shared routines.
 741  **/
 742 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 743 {
 744         switch (hw->phy.type) {
 745         case e1000_phy_ife:
 746                 return e1000_get_phy_info_ife_ich8lan(hw);
 747                 break;
 748         case e1000_phy_igp_3:
 749         case e1000_phy_bm:
 750                 return e1000e_get_phy_info_igp(hw);
 751                 break;
 752         default:
 753                 break;
 754         }
 755
 756         return -E1000_ERR_PHY_TYPE;
 757 }
 758
 759 /**
 760  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 761  *  @hw: pointer to the HW structure
 762  *
 763  *  Polarity is determined on the polarity reversal feature being enabled.
 764  *  This function is only called by other family-specific
 765  *  routines.
 766  **/
 767 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 768 {
 769         struct e1000_phy_info *phy = &hw->phy;
 770         s32 ret_val;
 771         u16 phy_data, offset, mask;
 772
 773         /*
 774          * Polarity is determined based on the reversal feature being enabled.
 775          */
 776         if (phy->polarity_correction) {
 777                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 778                 mask    = IFE_PESC_POLARITY_REVERSED;
 779         } else {
 780                 offset  = IFE_PHY_SPECIAL_CONTROL;
 781                 mask    = IFE_PSC_FORCE_POLARITY;
 782         }
 783
 784         ret_val = e1e_rphy(hw, offset, &phy_data);
 785
 786         if (!ret_val)
 787                 phy->cable_polarity = (phy_data & mask)
 788                                       ? e1000_rev_polarity_reversed
 789                                       : e1000_rev_polarity_normal;
 790
 791         return ret_val;
 792 }
 793
 794 /**
 795  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 796  *  @hw: pointer to the HW structure
 797  *  @active: TRUE to enable LPLU, FALSE to disable
 798  *
 799  *  Sets the LPLU D0 state according to the active flag.  When
 800  *  activating LPLU this function also disables smart speed
 801  *  and vice versa.  LPLU will not be activated unless the
 802  *  device autonegotiation advertisement meets standards of
 803  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 804  *  This is a function pointer entry point only called by
 805  *  PHY setup routines.
 806  **/
 807 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 808 {
 809         struct e1000_phy_info *phy = &hw->phy;
 810         u32 phy_ctrl;
 811         s32 ret_val = 0;
 812         u16 data;
 813
 814         if (phy->type == e1000_phy_ife)
 815                 return ret_val;
 816
 817         phy_ctrl = er32(PHY_CTRL);
 818
 819         if (active) {
 820                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 821                 ew32(PHY_CTRL, phy_ctrl);
 822
 823                 /*
 824                  * Call gig speed drop workaround on LPLU before accessing
 825                  * any PHY registers
 826                  */
 827                 if ((hw->mac.type == e1000_ich8lan) &&
 828                     (hw->phy.type == e1000_phy_igp_3))
 829                         e1000e_gig_downshift_workaround_ich8lan(hw);
 830
 831                 /* When LPLU is enabled, we should disable SmartSpeed */
 832                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 833                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 834                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 835                 if (ret_val)
 836                         return ret_val;
 837         } else {
 838                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 839                 ew32(PHY_CTRL, phy_ctrl);
 840
 841                 /*
 842                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 843                  * during Dx states where the power conservation is most
 844                  * important.  During driver activity we should enable
 845                  * SmartSpeed, so performance is maintained.
 846                  */
 847                 if (phy->smart_speed == e1000_smart_speed_on) {
 848                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 849                                            &data);
 850                         if (ret_val)
 851                                 return ret_val;
 852
 853                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 854                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 855                                            data);
 856                         if (ret_val)
 857                                 return ret_val;
 858                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 859                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 860                                            &data);
 861                         if (ret_val)
 862                                 return ret_val;
 863
 864                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 865                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 866                                            data);
 867                         if (ret_val)
 868                                 return ret_val;
 869                 }
 870         }
 871
 872         return 0;
 873 }
 874
 875 /**
 876  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
 877  *  @hw: pointer to the HW structure
 878  *  @active: TRUE to enable LPLU, FALSE to disable
 879  *
 880  *  Sets the LPLU D3 state according to the active flag.  When
 881  *  activating LPLU this function also disables smart speed
 882  *  and vice versa.  LPLU will not be activated unless the
 883  *  device autonegotiation advertisement meets standards of
 884  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 885  *  This is a function pointer entry point only called by
 886  *  PHY setup routines.
 887  **/
 888 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 889 {
 890         struct e1000_phy_info *phy = &hw->phy;
 891         u32 phy_ctrl;
 892         s32 ret_val;
 893         u16 data;
 894
 895         phy_ctrl = er32(PHY_CTRL);
 896
 897         if (!active) {
 898                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 899                 ew32(PHY_CTRL, phy_ctrl);
 900                 /*
 901                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 902                  * during Dx states where the power conservation is most
 903                  * important.  During driver activity we should enable
 904                  * SmartSpeed, so performance is maintained.
 905                  */
 906                 if (phy->smart_speed == e1000_smart_speed_on) {
 907                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 908                                            &data);
 909                         if (ret_val)
 910                                 return ret_val;
 911
 912                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 913                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 914                                            data);
 915                         if (ret_val)
 916                                 return ret_val;
 917                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 918                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 919                                            &data);
 920                         if (ret_val)
 921                                 return ret_val;
 922
 923                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 924                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 925                                            data);
 926                         if (ret_val)
 927                                 return ret_val;
 928                 }
 929         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 930                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 931                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 932                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 933                 ew32(PHY_CTRL, phy_ctrl);
 934
 935                 /*
 936                  * Call gig speed drop workaround on LPLU before accessing
 937                  * any PHY registers
 938                  */
 939                 if ((hw->mac.type == e1000_ich8lan) &&
 940                     (hw->phy.type == e1000_phy_igp_3))
 941                         e1000e_gig_downshift_workaround_ich8lan(hw);
 942
 943                 /* When LPLU is enabled, we should disable SmartSpeed */
 944                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 945                 if (ret_val)
 946                         return ret_val;
 947
 948                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 949                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 950         }
 951
 952         return 0;
 953 }
 954
 955 /**
 956  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
 957  *  @hw: pointer to the HW structure
 958  *  @bank:  pointer to the variable that returns the active bank
 959  *
 960  *  Reads signature byte from the NVM using the flash access registers.
 961  **/
 962 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
 963 {
 964         struct e1000_nvm_info *nvm = &hw->nvm;
 965         /* flash bank size is in words */
 966         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
 967         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
 968         u8 bank_high_byte = 0;
 969
 970         if (hw->mac.type != e1000_ich10lan) {
 971                 if (er32(EECD) & E1000_EECD_SEC1VAL)
 972                         *bank = 1;
 973                 else
 974                         *bank = 0;
 975         } else {
 976                 /*
 977                  * Make sure the signature for bank 0 is valid,
 978                  * if not check for bank1
 979                  */
 980                 e1000_read_flash_byte_ich8lan(hw, act_offset, &bank_high_byte);
 981                 if ((bank_high_byte & 0xC0) == 0x80) {
 982                         *bank = 0;
 983                 } else {
 984                         /*
 985                          * find if segment 1 is valid by verifying
 986                          * bit 15:14 = 10b in word 0x13
 987                          */
 988                         e1000_read_flash_byte_ich8lan(hw,
 989                                                       act_offset + bank1_offset,
 990                                                       &bank_high_byte);
 991
 992                         /* bank1 has a valid signature equivalent to SEC1V */
 993                         if ((bank_high_byte & 0xC0) == 0x80) {
 994                                 *bank = 1;
 995                         } else {
 996                                 hw_dbg(hw, "ERROR: EEPROM not present\n");
 997                                 return -E1000_ERR_NVM;
 998                         }
 999                 }
1000         }
1001
1002         return 0;
1003 }
1004
1005 /**
1006  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1007  *  @hw: pointer to the HW structure
1008  *  @offset: The offset (in bytes) of the word(s) to read.
1009  *  @words: Size of data to read in words
1010  *  @data: Pointer to the word(s) to read at offset.
1011  *
1012  *  Reads a word(s) from the NVM using the flash access registers.
1013  **/
1014 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1015                                   u16 *data)
1016 {
1017         struct e1000_nvm_info *nvm = &hw->nvm;
1018         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1019         u32 act_offset;
1020         s32 ret_val;
1021         u32 bank = 0;
1022         u16 i, word;
1023
1024         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1025             (words == 0)) {
1026                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1027                 return -E1000_ERR_NVM;
1028         }
1029
1030         ret_val = e1000_acquire_swflag_ich8lan(hw);
1031         if (ret_val)
1032                 return ret_val;
1033
1034         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1035         if (ret_val)
1036                 return ret_val;
1037
1038         act_offset = (bank) ? nvm->flash_bank_size : 0;
1039         act_offset += offset;
1040
1041         for (i = 0; i < words; i++) {
1042                 if ((dev_spec->shadow_ram) &&
1043                     (dev_spec->shadow_ram[offset+i].modified)) {
1044                         data[i] = dev_spec->shadow_ram[offset+i].value;
1045                 } else {
1046                         ret_val = e1000_read_flash_word_ich8lan(hw,
1047                                                                 act_offset + i,
1048                                                                 &word);
1049                         if (ret_val)
1050                                 break;
1051                         data[i] = word;
1052                 }
1053         }
1054
1055         e1000_release_swflag_ich8lan(hw);
1056
1057         return ret_val;
1058 }
1059
1060 /**
1061  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1062  *  @hw: pointer to the HW structure
1063  *
1064  *  This function does initial flash setup so that a new read/write/erase cycle
1065  *  can be started.
1066  **/
1067 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1068 {
1069         union ich8_hws_flash_status hsfsts;
1070         s32 ret_val = -E1000_ERR_NVM;
1071         s32 i = 0;
1072
1073         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1074
1075         /* Check if the flash descriptor is valid */
1076         if (hsfsts.hsf_status.fldesvalid == 0) {
1077                 hw_dbg(hw, "Flash descriptor invalid.  "
1078                          "SW Sequencing must be used.");
1079                 return -E1000_ERR_NVM;
1080         }
1081
1082         /* Clear FCERR and DAEL in hw status by writing 1 */
1083         hsfsts.hsf_status.flcerr = 1;
1084         hsfsts.hsf_status.dael = 1;
1085
1086         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1087
1088         /*
1089          * Either we should have a hardware SPI cycle in progress
1090          * bit to check against, in order to start a new cycle or
1091          * FDONE bit should be changed in the hardware so that it
1092          * is 1 after hardware reset, which can then be used as an
1093          * indication whether a cycle is in progress or has been
1094          * completed.
1095          */
1096
1097         if (hsfsts.hsf_status.flcinprog == 0) {
1098                 /*
1099                  * There is no cycle running at present,
1100                  * so we can start a cycle
1101                  * Begin by setting Flash Cycle Done.
1102                  */
1103                 hsfsts.hsf_status.flcdone = 1;
1104                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1105                 ret_val = 0;
1106         } else {
1107                 /*
1108                  * otherwise poll for sometime so the current
1109                  * cycle has a chance to end before giving up.
1110                  */
1111                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1112                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1113                         if (hsfsts.hsf_status.flcinprog == 0) {
1114                                 ret_val = 0;
1115                                 break;
1116                         }
1117                         udelay(1);
1118                 }
1119                 if (ret_val == 0) {
1120                         /*
1121                          * Successful in waiting for previous cycle to timeout,
1122                          * now set the Flash Cycle Done.
1123                          */
1124                         hsfsts.hsf_status.flcdone = 1;
1125                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1126                 } else {
1127                         hw_dbg(hw, "Flash controller busy, cannot get access");
1128                 }
1129         }
1130
1131         return ret_val;
1132 }
1133
1134 /**
1135  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1136  *  @hw: pointer to the HW structure
1137  *  @timeout: maximum time to wait for completion
1138  *
1139  *  This function starts a flash cycle and waits for its completion.
1140  **/
1141 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1142 {
1143         union ich8_hws_flash_ctrl hsflctl;
1144         union ich8_hws_flash_status hsfsts;
1145         s32 ret_val = -E1000_ERR_NVM;
1146         u32 i = 0;
1147
1148         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1149         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1150         hsflctl.hsf_ctrl.flcgo = 1;
1151         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1152
1153         /* wait till FDONE bit is set to 1 */
1154         do {
1155                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1156                 if (hsfsts.hsf_status.flcdone == 1)
1157                         break;
1158                 udelay(1);
1159         } while (i++ < timeout);
1160
1161         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1162                 return 0;
1163
1164         return ret_val;
1165 }
1166
1167 /**
1168  *  e1000_read_flash_word_ich8lan - Read word from flash
1169  *  @hw: pointer to the HW structure
1170  *  @offset: offset to data location
1171  *  @data: pointer to the location for storing the data
1172  *
1173  *  Reads the flash word at offset into data.  Offset is converted
1174  *  to bytes before read.
1175  **/
1176 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1177                                          u16 *data)
1178 {
1179         /* Must convert offset into bytes. */
1180         offset <<= 1;
1181
1182         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1183 }
1184
1185 /**
1186  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1187  *  @hw: pointer to the HW structure
1188  *  @offset: The offset of the byte to read.
1189  *  @data: Pointer to a byte to store the value read.
1190  *
1191  *  Reads a single byte from the NVM using the flash access registers.
1192  **/
1193 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1194                                          u8 *data)
1195 {
1196         s32 ret_val;
1197         u16 word = 0;
1198
1199         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1200         if (ret_val)
1201                 return ret_val;
1202
1203         *data = (u8)word;
1204
1205         return 0;
1206 }
1207
1208 /**
1209  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1210  *  @hw: pointer to the HW structure
1211  *  @offset: The offset (in bytes) of the byte or word to read.
1212  *  @size: Size of data to read, 1=byte 2=word
1213  *  @data: Pointer to the word to store the value read.
1214  *
1215  *  Reads a byte or word from the NVM using the flash access registers.
1216  **/
1217 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1218                                          u8 size, u16 *data)
1219 {
1220         union ich8_hws_flash_status hsfsts;
1221         union ich8_hws_flash_ctrl hsflctl;
1222         u32 flash_linear_addr;
1223         u32 flash_data = 0;
1224         s32 ret_val = -E1000_ERR_NVM;
1225         u8 count = 0;
1226
1227         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1228                 return -E1000_ERR_NVM;
1229
1230         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1231                             hw->nvm.flash_base_addr;
1232
1233         do {
1234                 udelay(1);
1235                 /* Steps */
1236                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1237                 if (ret_val != 0)
1238                         break;
1239
1240                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1241                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1242                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1243                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1244                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1245
1246                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1247
1248                 ret_val = e1000_flash_cycle_ich8lan(hw,
1249                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1250
1251                 /*
1252                  * Check if FCERR is set to 1, if set to 1, clear it
1253                  * and try the whole sequence a few more times, else
1254                  * read in (shift in) the Flash Data0, the order is
1255                  * least significant byte first msb to lsb
1256                  */
1257                 if (ret_val == 0) {
1258                         flash_data = er32flash(ICH_FLASH_FDATA0);
1259                         if (size == 1) {
1260                                 *data = (u8)(flash_data & 0x000000FF);
1261                         } else if (size == 2) {
1262                                 *data = (u16)(flash_data & 0x0000FFFF);
1263                         }
1264                         break;
1265                 } else {
1266                         /*
1267                          * If we've gotten here, then things are probably
1268                          * completely hosed, but if the error condition is
1269                          * detected, it won't hurt to give it another try...
1270                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1271                          */
1272                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1273                         if (hsfsts.hsf_status.flcerr == 1) {
1274                                 /* Repeat for some time before giving up. */
1275                                 continue;
1276                         } else if (hsfsts.hsf_status.flcdone == 0) {
1277                                 hw_dbg(hw, "Timeout error - flash cycle "
1278                                          "did not complete.");
1279                                 break;
1280                         }
1281                 }
1282         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1283
1284         return ret_val;
1285 }
1286
1287 /**
1288  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1289  *  @hw: pointer to the HW structure
1290  *  @offset: The offset (in bytes) of the word(s) to write.
1291  *  @words: Size of data to write in words
1292  *  @data: Pointer to the word(s) to write at offset.
1293  *
1294  *  Writes a byte or word to the NVM using the flash access registers.
1295  **/
1296 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1297                                    u16 *data)
1298 {
1299         struct e1000_nvm_info *nvm = &hw->nvm;
1300         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1301         s32 ret_val;
1302         u16 i;
1303
1304         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1305             (words == 0)) {
1306                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1307                 return -E1000_ERR_NVM;
1308         }
1309
1310         ret_val = e1000_acquire_swflag_ich8lan(hw);
1311         if (ret_val)
1312                 return ret_val;
1313
1314         for (i = 0; i < words; i++) {
1315                 dev_spec->shadow_ram[offset+i].modified = 1;
1316                 dev_spec->shadow_ram[offset+i].value = data[i];
1317         }
1318
1319         e1000_release_swflag_ich8lan(hw);
1320
1321         return 0;
1322 }
1323
1324 /**
1325  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1326  *  @hw: pointer to the HW structure
1327  *
1328  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1329  *  which writes the checksum to the shadow ram.  The changes in the shadow
1330  *  ram are then committed to the EEPROM by processing each bank at a time
1331  *  checking for the modified bit and writing only the pending changes.
1332  *  After a successful commit, the shadow ram is cleared and is ready for
1333  *  future writes.
1334  **/
1335 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1336 {
1337         struct e1000_nvm_info *nvm = &hw->nvm;
1338         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1339         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1340         s32 ret_val;
1341         u16 data;
1342
1343         ret_val = e1000e_update_nvm_checksum_generic(hw);
1344         if (ret_val)
1345                 return ret_val;
1346
1347         if (nvm->type != e1000_nvm_flash_sw)
1348                 return ret_val;
1349
1350         ret_val = e1000_acquire_swflag_ich8lan(hw);
1351         if (ret_val)
1352                 return ret_val;
1353
1354         /*
1355          * We're writing to the opposite bank so if we're on bank 1,
1356          * write to bank 0 etc.  We also need to erase the segment that
1357          * is going to be written
1358          */
1359         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1360         if (ret_val)
1361                 return ret_val;
1362
1363         if (bank == 0) {
1364                 new_bank_offset = nvm->flash_bank_size;
1365                 old_bank_offset = 0;
1366                 e1000_erase_flash_bank_ich8lan(hw, 1);
1367         } else {
1368                 old_bank_offset = nvm->flash_bank_size;
1369                 new_bank_offset = 0;
1370                 e1000_erase_flash_bank_ich8lan(hw, 0);
1371         }
1372
1373         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1374                 /*
1375                  * Determine whether to write the value stored
1376                  * in the other NVM bank or a modified value stored
1377                  * in the shadow RAM
1378                  */
1379                 if (dev_spec->shadow_ram[i].modified) {
1380                         data = dev_spec->shadow_ram[i].value;
1381                 } else {
1382                         e1000_read_flash_word_ich8lan(hw,
1383                                                       i + old_bank_offset,
1384                                                       &data);
1385                 }
1386
1387                 /*
1388                  * If the word is 0x13, then make sure the signature bits
1389                  * (15:14) are 11b until the commit has completed.
1390                  * This will allow us to write 10b which indicates the
1391                  * signature is valid.  We want to do this after the write
1392                  * has completed so that we don't mark the segment valid
1393                  * while the write is still in progress
1394                  */
1395                 if (i == E1000_ICH_NVM_SIG_WORD)
1396                         data |= E1000_ICH_NVM_SIG_MASK;
1397
1398                 /* Convert offset to bytes. */
1399                 act_offset = (i + new_bank_offset) << 1;
1400
1401                 udelay(100);
1402                 /* Write the bytes to the new bank. */
1403                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1404                                                                act_offset,
1405                                                                (u8)data);
1406                 if (ret_val)
1407                         break;
1408
1409                 udelay(100);
1410                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1411                                                           act_offset + 1,
1412                                                           (u8)(data >> 8));
1413                 if (ret_val)
1414                         break;
1415         }
1416
1417         /*
1418          * Don't bother writing the segment valid bits if sector
1419          * programming failed.
1420          */
1421         if (ret_val) {
1422                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1423                 hw_dbg(hw, "Flash commit failed.\n");
1424                 e1000_release_swflag_ich8lan(hw);
1425                 return ret_val;
1426         }
1427
1428         /*
1429          * Finally validate the new segment by setting bit 15:14
1430          * to 10b in word 0x13 , this can be done without an
1431          * erase as well since these bits are 11 to start with
1432          * and we need to change bit 14 to 0b
1433          */
1434         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1435         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1436         data &= 0xBFFF;
1437         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1438                                                        act_offset * 2 + 1,
1439                                                        (u8)(data >> 8));
1440         if (ret_val) {
1441                 e1000_release_swflag_ich8lan(hw);
1442                 return ret_val;
1443         }
1444
1445         /*
1446          * And invalidate the previously valid segment by setting
1447          * its signature word (0x13) high_byte to 0b. This can be
1448          * done without an erase because flash erase sets all bits
1449          * to 1's. We can write 1's to 0's without an erase
1450          */
1451         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1452         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1453         if (ret_val) {
1454                 e1000_release_swflag_ich8lan(hw);
1455                 return ret_val;
1456         }
1457
1458         /* Great!  Everything worked, we can now clear the cached entries. */
1459         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1460                 dev_spec->shadow_ram[i].modified = 0;
1461                 dev_spec->shadow_ram[i].value = 0xFFFF;
1462         }
1463
1464         e1000_release_swflag_ich8lan(hw);
1465
1466         /*
1467          * Reload the EEPROM, or else modifications will not appear
1468          * until after the next adapter reset.
1469          */
1470         e1000e_reload_nvm(hw);
1471         msleep(10);
1472
1473         return ret_val;
1474 }
1475
1476 /**
1477  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1478  *  @hw: pointer to the HW structure
1479  *
1480  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1481  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1482  *  calculated, in which case we need to calculate the checksum and set bit 6.
1483  **/
1484 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1485 {
1486         s32 ret_val;
1487         u16 data;
1488
1489         /*
1490          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1491          * needs to be fixed.  This bit is an indication that the NVM
1492          * was prepared by OEM software and did not calculate the
1493          * checksum...a likely scenario.
1494          */
1495         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1496         if (ret_val)
1497                 return ret_val;
1498
1499         if ((data & 0x40) == 0) {
1500                 data |= 0x40;
1501                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1502                 if (ret_val)
1503                         return ret_val;
1504                 ret_val = e1000e_update_nvm_checksum(hw);
1505                 if (ret_val)
1506                         return ret_val;
1507         }
1508
1509         return e1000e_validate_nvm_checksum_generic(hw);
1510 }
1511
1512 /**
1513  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1514  *  @hw: pointer to the HW structure
1515  *
1516  *  To prevent malicious write/erase of the NVM, set it to be read-only
1517  *  so that the hardware ignores all write/erase cycles of the NVM via
1518  *  the flash control registers.  The shadow-ram copy of the NVM will
1519  *  still be updated, however any updates to this copy will not stick
1520  *  across driver reloads.
1521  **/
1522 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1523 {
1524         union ich8_flash_protected_range pr0;
1525         union ich8_hws_flash_status hsfsts;
1526         u32 gfpreg;
1527         s32 ret_val;
1528
1529         ret_val = e1000_acquire_swflag_ich8lan(hw);
1530         if (ret_val)
1531                 return;
1532
1533         gfpreg = er32flash(ICH_FLASH_GFPREG);
1534
1535         /* Write-protect GbE Sector of NVM */
1536         pr0.regval = er32flash(ICH_FLASH_PR0);
1537         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1538         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1539         pr0.range.wpe = true;
1540         ew32flash(ICH_FLASH_PR0, pr0.regval);
1541
1542         /*
1543          * Lock down a subset of GbE Flash Control Registers, e.g.
1544          * PR0 to prevent the write-protection from being lifted.
1545          * Once FLOCKDN is set, the registers protected by it cannot
1546          * be written until FLOCKDN is cleared by a hardware reset.
1547          */
1548         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1549         hsfsts.hsf_status.flockdn = true;
1550         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1551
1552         e1000_release_swflag_ich8lan(hw);
1553 }
1554
1555 /**
1556  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1557  *  @hw: pointer to the HW structure
1558  *  @offset: The offset (in bytes) of the byte/word to read.
1559  *  @size: Size of data to read, 1=byte 2=word
1560  *  @data: The byte(s) to write to the NVM.
1561  *
1562  *  Writes one/two bytes to the NVM using the flash access registers.
1563  **/
1564 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1565                                           u8 size, u16 data)
1566 {
1567         union ich8_hws_flash_status hsfsts;
1568         union ich8_hws_flash_ctrl hsflctl;
1569         u32 flash_linear_addr;
1570         u32 flash_data = 0;
1571         s32 ret_val;
1572         u8 count = 0;
1573
1574         if (size < 1 || size > 2 || data > size * 0xff ||
1575             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1576                 return -E1000_ERR_NVM;
1577
1578         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1579                             hw->nvm.flash_base_addr;
1580
1581         do {
1582                 udelay(1);
1583                 /* Steps */
1584                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1585                 if (ret_val)
1586                         break;
1587
1588                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1589                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1590                 hsflctl.hsf_ctrl.fldbcount = size -1;
1591                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1592                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1593
1594                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1595
1596                 if (size == 1)
1597                         flash_data = (u32)data & 0x00FF;
1598                 else
1599                         flash_data = (u32)data;
1600
1601                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1602
1603                 /*
1604                  * check if FCERR is set to 1 , if set to 1, clear it
1605                  * and try the whole sequence a few more times else done
1606                  */
1607                 ret_val = e1000_flash_cycle_ich8lan(hw,
1608                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1609                 if (!ret_val)
1610                         break;
1611
1612                 /*
1613                  * If we're here, then things are most likely
1614                  * completely hosed, but if the error condition
1615                  * is detected, it won't hurt to give it another
1616                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1617                  */
1618                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1619                 if (hsfsts.hsf_status.flcerr == 1)
1620                         /* Repeat for some time before giving up. */
1621                         continue;
1622                 if (hsfsts.hsf_status.flcdone == 0) {
1623                         hw_dbg(hw, "Timeout error - flash cycle "
1624                                  "did not complete.");
1625                         break;
1626                 }
1627         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1628
1629         return ret_val;
1630 }
1631
1632 /**
1633  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1634  *  @hw: pointer to the HW structure
1635  *  @offset: The index of the byte to read.
1636  *  @data: The byte to write to the NVM.
1637  *
1638  *  Writes a single byte to the NVM using the flash access registers.
1639  **/
1640 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1641                                           u8 data)
1642 {
1643         u16 word = (u16)data;
1644
1645         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1646 }
1647
1648 /**
1649  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1650  *  @hw: pointer to the HW structure
1651  *  @offset: The offset of the byte to write.
1652  *  @byte: The byte to write to the NVM.
1653  *
1654  *  Writes a single byte to the NVM using the flash access registers.
1655  *  Goes through a retry algorithm before giving up.
1656  **/
1657 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1658                                                 u32 offset, u8 byte)
1659 {
1660         s32 ret_val;
1661         u16 program_retries;
1662
1663         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1664         if (!ret_val)
1665                 return ret_val;
1666
1667         for (program_retries = 0; program_retries < 100; program_retries++) {
1668                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1669                 udelay(100);
1670                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1671                 if (!ret_val)
1672                         break;
1673         }
1674         if (program_retries == 100)
1675                 return -E1000_ERR_NVM;
1676
1677         return 0;
1678 }
1679
1680 /**
1681  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1682  *  @hw: pointer to the HW structure
1683  *  @bank: 0 for first bank, 1 for second bank, etc.
1684  *
1685  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1686  *  bank N is 4096 * N + flash_reg_addr.
1687  **/
1688 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1689 {
1690         struct e1000_nvm_info *nvm = &hw->nvm;
1691         union ich8_hws_flash_status hsfsts;
1692         union ich8_hws_flash_ctrl hsflctl;
1693         u32 flash_linear_addr;
1694         /* bank size is in 16bit words - adjust to bytes */
1695         u32 flash_bank_size = nvm->flash_bank_size * 2;
1696         s32 ret_val;
1697         s32 count = 0;
1698         s32 iteration;
1699         s32 sector_size;
1700         s32 j;
1701
1702         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1703
1704         /*
1705          * Determine HW Sector size: Read BERASE bits of hw flash status
1706          * register
1707          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1708          *     consecutive sectors.  The start index for the nth Hw sector
1709          *     can be calculated as = bank * 4096 + n * 256
1710          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1711          *     The start index for the nth Hw sector can be calculated
1712          *     as = bank * 4096
1713          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1714          *     (ich9 only, otherwise error condition)
1715          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1716          */
1717         switch (hsfsts.hsf_status.berasesz) {
1718         case 0:
1719                 /* Hw sector size 256 */
1720                 sector_size = ICH_FLASH_SEG_SIZE_256;
1721                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1722                 break;
1723         case 1:
1724                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1725                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1726                 break;
1727         case 2:
1728                 if (hw->mac.type == e1000_ich9lan) {
1729                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1730                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1731                 } else {
1732                         return -E1000_ERR_NVM;
1733                 }
1734                 break;
1735         case 3:
1736                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1737                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1738                 break;
1739         default:
1740                 return -E1000_ERR_NVM;
1741         }
1742
1743         /* Start with the base address, then add the sector offset. */
1744         flash_linear_addr = hw->nvm.flash_base_addr;
1745         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1746
1747         for (j = 0; j < iteration ; j++) {
1748                 do {
1749                         /* Steps */
1750                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1751                         if (ret_val)
1752                                 return ret_val;
1753
1754                         /*
1755                          * Write a value 11 (block Erase) in Flash
1756                          * Cycle field in hw flash control
1757                          */
1758                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1759                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1760                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1761
1762                         /*
1763                          * Write the last 24 bits of an index within the
1764                          * block into Flash Linear address field in Flash
1765                          * Address.
1766                          */
1767                         flash_linear_addr += (j * sector_size);
1768                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1769
1770                         ret_val = e1000_flash_cycle_ich8lan(hw,
1771                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1772                         if (ret_val == 0)
1773                                 break;
1774
1775                         /*
1776                          * Check if FCERR is set to 1.  If 1,
1777                          * clear it and try the whole sequence
1778                          * a few more times else Done
1779                          */
1780                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1781                         if (hsfsts.hsf_status.flcerr == 1)
1782                                 /* repeat for some time before giving up */
1783                                 continue;
1784                         else if (hsfsts.hsf_status.flcdone == 0)
1785                                 return ret_val;
1786                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1787         }
1788
1789         return 0;
1790 }
1791
1792 /**
1793  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1794  *  @hw: pointer to the HW structure
1795  *  @data: Pointer to the LED settings
1796  *
1797  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1798  *  settings is all 0's or F's, set the LED default to a valid LED default
1799  *  setting.
1800  **/
1801 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1802 {
1803         s32 ret_val;
1804
1805         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1806         if (ret_val) {
1807                 hw_dbg(hw, "NVM Read Error\n");
1808                 return ret_val;
1809         }
1810
1811         if (*data == ID_LED_RESERVED_0000 ||
1812             *data == ID_LED_RESERVED_FFFF)
1813                 *data = ID_LED_DEFAULT_ICH8LAN;
1814
1815         return 0;
1816 }
1817
1818 /**
1819  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1820  *  @hw: pointer to the HW structure
1821  *
1822  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1823  *  register, so the the bus width is hard coded.
1824  **/
1825 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1826 {
1827         struct e1000_bus_info *bus = &hw->bus;
1828         s32 ret_val;
1829
1830         ret_val = e1000e_get_bus_info_pcie(hw);
1831
1832         /*
1833          * ICH devices are "PCI Express"-ish.  They have
1834          * a configuration space, but do not contain
1835          * PCI Express Capability registers, so bus width
1836          * must be hardcoded.
1837          */
1838         if (bus->width == e1000_bus_width_unknown)
1839                 bus->width = e1000_bus_width_pcie_x1;
1840
1841         return ret_val;
1842 }
1843
1844 /**
1845  *  e1000_reset_hw_ich8lan - Reset the hardware
1846  *  @hw: pointer to the HW structure
1847  *
1848  *  Does a full reset of the hardware which includes a reset of the PHY and
1849  *  MAC.
1850  **/
1851 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1852 {
1853         u32 ctrl, icr, kab;
1854         s32 ret_val;
1855
1856         /*
1857          * Prevent the PCI-E bus from sticking if there is no TLP connection
1858          * on the last TLP read/write transaction when MAC is reset.
1859          */
1860         ret_val = e1000e_disable_pcie_master(hw);
1861         if (ret_val) {
1862                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1863         }
1864
1865         hw_dbg(hw, "Masking off all interrupts\n");
1866         ew32(IMC, 0xffffffff);
1867
1868         /*
1869          * Disable the Transmit and Receive units.  Then delay to allow
1870          * any pending transactions to complete before we hit the MAC
1871          * with the global reset.
1872          */
1873         ew32(RCTL, 0);
1874         ew32(TCTL, E1000_TCTL_PSP);
1875         e1e_flush();
1876
1877         msleep(10);
1878
1879         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1880         if (hw->mac.type == e1000_ich8lan) {
1881                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1882                 ew32(PBA, E1000_PBA_8K);
1883                 /* Set Packet Buffer Size to 16k. */
1884                 ew32(PBS, E1000_PBS_16K);
1885         }
1886
1887         ctrl = er32(CTRL);
1888
1889         if (!e1000_check_reset_block(hw)) {
1890                 /*
1891                  * PHY HW reset requires MAC CORE reset at the same
1892                  * time to make sure the interface between MAC and the
1893                  * external PHY is reset.
1894                  */
1895                 ctrl |= E1000_CTRL_PHY_RST;
1896         }
1897         ret_val = e1000_acquire_swflag_ich8lan(hw);
1898         hw_dbg(hw, "Issuing a global reset to ich8lan");
1899         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1900         msleep(20);
1901
1902         /* release the swflag because it is not reset by hardware reset */
1903         e1000_release_swflag_ich8lan(hw);
1904
1905         ret_val = e1000e_get_auto_rd_done(hw);
1906         if (ret_val) {
1907                 /*
1908                  * When auto config read does not complete, do not
1909                  * return with an error. This can happen in situations
1910                  * where there is no eeprom and prevents getting link.
1911                  */
1912                 hw_dbg(hw, "Auto Read Done did not complete\n");
1913         }
1914
1915         ew32(IMC, 0xffffffff);
1916         icr = er32(ICR);
1917
1918         kab = er32(KABGTXD);
1919         kab |= E1000_KABGTXD_BGSQLBIAS;
1920         ew32(KABGTXD, kab);
1921
1922         return ret_val;
1923 }
1924
1925 /**
1926  *  e1000_init_hw_ich8lan - Initialize the hardware
1927  *  @hw: pointer to the HW structure
1928  *
1929  *  Prepares the hardware for transmit and receive by doing the following:
1930  *   - initialize hardware bits
1931  *   - initialize LED identification
1932  *   - setup receive address registers
1933  *   - setup flow control
1934  *   - setup transmit descriptors
1935  *   - clear statistics
1936  **/
1937 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1938 {
1939         struct e1000_mac_info *mac = &hw->mac;
1940         u32 ctrl_ext, txdctl, snoop;
1941         s32 ret_val;
1942         u16 i;
1943
1944         e1000_initialize_hw_bits_ich8lan(hw);
1945
1946         /* Initialize identification LED */
1947         ret_val = e1000e_id_led_init(hw);
1948         if (ret_val) {
1949                 hw_dbg(hw, "Error initializing identification LED\n");
1950                 return ret_val;
1951         }
1952
1953         /* Setup the receive address. */
1954         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1955
1956         /* Zero out the Multicast HASH table */
1957         hw_dbg(hw, "Zeroing the MTA\n");
1958         for (i = 0; i < mac->mta_reg_count; i++)
1959                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1960
1961         /* Setup link and flow control */
1962         ret_val = e1000_setup_link_ich8lan(hw);
1963
1964         /* Set the transmit descriptor write-back policy for both queues */
1965         txdctl = er32(TXDCTL(0));
1966         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1967                  E1000_TXDCTL_FULL_TX_DESC_WB;
1968         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1969                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1970         ew32(TXDCTL(0), txdctl);
1971         txdctl = er32(TXDCTL(1));
1972         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1973                  E1000_TXDCTL_FULL_TX_DESC_WB;
1974         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1975                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1976         ew32(TXDCTL(1), txdctl);
1977
1978         /*
1979          * ICH8 has opposite polarity of no_snoop bits.
1980          * By default, we should use snoop behavior.
1981          */
1982         if (mac->type == e1000_ich8lan)
1983                 snoop = PCIE_ICH8_SNOOP_ALL;
1984         else
1985                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1986         e1000e_set_pcie_no_snoop(hw, snoop);
1987
1988         ctrl_ext = er32(CTRL_EXT);
1989         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1990         ew32(CTRL_EXT, ctrl_ext);
1991
1992         /*
1993          * Clear all of the statistics registers (clear on read).  It is
1994          * important that we do this after we have tried to establish link
1995          * because the symbol error count will increment wildly if there
1996          * is no link.
1997          */
1998         e1000_clear_hw_cntrs_ich8lan(hw);
1999
2000         return 0;
2001 }
2002 /**
2003  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2004  *  @hw: pointer to the HW structure
2005  *
2006  *  Sets/Clears required hardware bits necessary for correctly setting up the
2007  *  hardware for transmit and receive.
2008  **/
2009 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2010 {
2011         u32 reg;
2012
2013         /* Extended Device Control */
2014         reg = er32(CTRL_EXT);
2015         reg |= (1 << 22);
2016         ew32(CTRL_EXT, reg);
2017
2018         /* Transmit Descriptor Control 0 */
2019         reg = er32(TXDCTL(0));
2020         reg |= (1 << 22);
2021         ew32(TXDCTL(0), reg);
2022
2023         /* Transmit Descriptor Control 1 */
2024         reg = er32(TXDCTL(1));
2025         reg |= (1 << 22);
2026         ew32(TXDCTL(1), reg);
2027
2028         /* Transmit Arbitration Control 0 */
2029         reg = er32(TARC(0));
2030         if (hw->mac.type == e1000_ich8lan)
2031                 reg |= (1 << 28) | (1 << 29);
2032         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2033         ew32(TARC(0), reg);
2034
2035         /* Transmit Arbitration Control 1 */
2036         reg = er32(TARC(1));
2037         if (er32(TCTL) & E1000_TCTL_MULR)
2038                 reg &= ~(1 << 28);
2039         else
2040                 reg |= (1 << 28);
2041         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2042         ew32(TARC(1), reg);
2043
2044         /* Device Status */
2045         if (hw->mac.type == e1000_ich8lan) {
2046                 reg = er32(STATUS);
2047                 reg &= ~(1 << 31);
2048                 ew32(STATUS, reg);
2049         }
2050 }
2051
2052 /**
2053  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2054  *  @hw: pointer to the HW structure
2055  *
2056  *  Determines which flow control settings to use, then configures flow
2057  *  control.  Calls the appropriate media-specific link configuration
2058  *  function.  Assuming the adapter has a valid link partner, a valid link
2059  *  should be established.  Assumes the hardware has previously been reset
2060  *  and the transmitter and receiver are not enabled.
2061  **/
2062 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2063 {
2064         s32 ret_val;
2065
2066         if (e1000_check_reset_block(hw))
2067                 return 0;
2068
2069         /*
2070          * ICH parts do not have a word in the NVM to determine
2071          * the default flow control setting, so we explicitly
2072          * set it to full.
2073          */
2074         if (hw->fc.type == e1000_fc_default)
2075                 hw->fc.type = e1000_fc_full;
2076
2077         hw->fc.original_type = hw->fc.type;
2078
2079         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
2080
2081         /* Continue to configure the copper link. */
2082         ret_val = e1000_setup_copper_link_ich8lan(hw);
2083         if (ret_val)
2084                 return ret_val;
2085
2086         ew32(FCTTV, hw->fc.pause_time);
2087
2088         return e1000e_set_fc_watermarks(hw);
2089 }
2090
2091 /**
2092  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2093  *  @hw: pointer to the HW structure
2094  *
2095  *  Configures the kumeran interface to the PHY to wait the appropriate time
2096  *  when polling the PHY, then call the generic setup_copper_link to finish
2097  *  configuring the copper link.
2098  **/
2099 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2100 {
2101         u32 ctrl;
2102         s32 ret_val;
2103         u16 reg_data;
2104
2105         ctrl = er32(CTRL);
2106         ctrl |= E1000_CTRL_SLU;
2107         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2108         ew32(CTRL, ctrl);
2109
2110         /*
2111          * Set the mac to wait the maximum time between each iteration
2112          * and increase the max iterations when polling the phy;
2113          * this fixes erroneous timeouts at 10Mbps.
2114          */
2115         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2116         if (ret_val)
2117                 return ret_val;
2118         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2119         if (ret_val)
2120                 return ret_val;
2121         reg_data |= 0x3F;
2122         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2123         if (ret_val)
2124                 return ret_val;
2125
2126         if (hw->phy.type == e1000_phy_igp_3) {
2127                 ret_val = e1000e_copper_link_setup_igp(hw);
2128                 if (ret_val)
2129                         return ret_val;
2130         } else if (hw->phy.type == e1000_phy_bm) {
2131                 ret_val = e1000e_copper_link_setup_m88(hw);
2132                 if (ret_val)
2133                         return ret_val;
2134         }
2135
2136         if (hw->phy.type == e1000_phy_ife) {
2137                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2138                 if (ret_val)
2139                         return ret_val;
2140
2141                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2142
2143                 switch (hw->phy.mdix) {
2144                 case 1:
2145                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2146                         break;
2147                 case 2:
2148                         reg_data |= IFE_PMC_FORCE_MDIX;
2149                         break;
2150                 case 0:
2151                 default:
2152                         reg_data |= IFE_PMC_AUTO_MDIX;
2153                         break;
2154                 }
2155                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2156                 if (ret_val)
2157                         return ret_val;
2158         }
2159         return e1000e_setup_copper_link(hw);
2160 }
2161
2162 /**
2163  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2164  *  @hw: pointer to the HW structure
2165  *  @speed: pointer to store current link speed
2166  *  @duplex: pointer to store the current link duplex
2167  *
2168  *  Calls the generic get_speed_and_duplex to retrieve the current link
2169  *  information and then calls the Kumeran lock loss workaround for links at
2170  *  gigabit speeds.
2171  **/
2172 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2173                                           u16 *duplex)
2174 {
2175         s32 ret_val;
2176
2177         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2178         if (ret_val)
2179                 return ret_val;
2180
2181         if ((hw->mac.type == e1000_ich8lan) &&
2182             (hw->phy.type == e1000_phy_igp_3) &&
2183             (*speed == SPEED_1000)) {
2184                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2185         }
2186
2187         return ret_val;
2188 }
2189
2190 /**
2191  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2192  *  @hw: pointer to the HW structure
2193  *
2194  *  Work-around for 82566 Kumeran PCS lock loss:
2195  *  On link status change (i.e. PCI reset, speed change) and link is up and
2196  *  speed is gigabit-
2197  *    0) if workaround is optionally disabled do nothing
2198  *    1) wait 1ms for Kumeran link to come up
2199  *    2) check Kumeran Diagnostic register PCS lock loss bit
2200  *    3) if not set the link is locked (all is good), otherwise...
2201  *    4) reset the PHY
2202  *    5) repeat up to 10 times
2203  *  Note: this is only called for IGP3 copper when speed is 1gb.
2204  **/
2205 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2206 {
2207         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2208         u32 phy_ctrl;
2209         s32 ret_val;
2210         u16 i, data;
2211         bool link;
2212
2213         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2214                 return 0;
2215
2216         /*
2217          * Make sure link is up before proceeding.  If not just return.
2218          * Attempting this while link is negotiating fouled up link
2219          * stability
2220          */
2221         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2222         if (!link)
2223                 return 0;
2224
2225         for (i = 0; i < 10; i++) {
2226                 /* read once to clear */
2227                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2228                 if (ret_val)
2229                         return ret_val;
2230                 /* and again to get new status */
2231                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2232                 if (ret_val)
2233                         return ret_val;
2234
2235                 /* check for PCS lock */
2236                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2237                         return 0;
2238
2239                 /* Issue PHY reset */
2240                 e1000_phy_hw_reset(hw);
2241                 mdelay(5);
2242         }
2243         /* Disable GigE link negotiation */
2244         phy_ctrl = er32(PHY_CTRL);
2245         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2246                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2247         ew32(PHY_CTRL, phy_ctrl);
2248
2249         /*
2250          * Call gig speed drop workaround on Gig disable before accessing
2251          * any PHY registers
2252          */
2253         e1000e_gig_downshift_workaround_ich8lan(hw);
2254
2255         /* unable to acquire PCS lock */
2256         return -E1000_ERR_PHY;
2257 }
2258
2259 /**
2260  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2261  *  @hw: pointer to the HW structure
2262  *  @state: boolean value used to set the current Kumeran workaround state
2263  *
2264  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2265  *  /disabled - FALSE).
2266  **/
2267 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2268                                                  bool state)
2269 {
2270         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2271
2272         if (hw->mac.type != e1000_ich8lan) {
2273                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2274                 return;
2275         }
2276
2277         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2278 }
2279
2280 /**
2281  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2282  *  @hw: pointer to the HW structure
2283  *
2284  *  Workaround for 82566 power-down on D3 entry:
2285  *    1) disable gigabit link
2286  *    2) write VR power-down enable
2287  *    3) read it back
2288  *  Continue if successful, else issue LCD reset and repeat
2289  **/
2290 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2291 {
2292         u32 reg;
2293         u16 data;
2294         u8  retry = 0;
2295
2296         if (hw->phy.type != e1000_phy_igp_3)
2297                 return;
2298
2299         /* Try the workaround twice (if needed) */
2300         do {
2301                 /* Disable link */
2302                 reg = er32(PHY_CTRL);
2303                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2304                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2305                 ew32(PHY_CTRL, reg);
2306
2307                 /*
2308                  * Call gig speed drop workaround on Gig disable before
2309                  * accessing any PHY registers
2310                  */
2311                 if (hw->mac.type == e1000_ich8lan)
2312                         e1000e_gig_downshift_workaround_ich8lan(hw);
2313
2314                 /* Write VR power-down enable */
2315                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2316                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2317                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2318
2319                 /* Read it back and test */
2320                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2321                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2322                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2323                         break;
2324
2325                 /* Issue PHY reset and repeat at most one more time */
2326                 reg = er32(CTRL);
2327                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2328                 retry++;
2329         } while (retry);
2330 }
2331
2332 /**
2333  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2334  *  @hw: pointer to the HW structure
2335  *
2336  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2337  *  LPLU, Gig disable, MDIC PHY reset):
2338  *    1) Set Kumeran Near-end loopback
2339  *    2) Clear Kumeran Near-end loopback
2340  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2341  **/
2342 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2343 {
2344         s32 ret_val;
2345         u16 reg_data;
2346
2347         if ((hw->mac.type != e1000_ich8lan) ||
2348             (hw->phy.type != e1000_phy_igp_3))
2349                 return;
2350
2351         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2352                                       &reg_data);
2353         if (ret_val)
2354                 return;
2355         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2356         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2357                                        reg_data);
2358         if (ret_val)
2359                 return;
2360         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2361         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2362                                        reg_data);
2363 }
2364
2365 /**
2366  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2367  *  @hw: pointer to the HW structure
2368  *
2369  *  During S0 to Sx transition, it is possible the link remains at gig
2370  *  instead of negotiating to a lower speed.  Before going to Sx, set
2371  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2372  *  to a lower speed.
2373  *
2374  *  Should only be called for ICH9 and ICH10 devices.
2375  **/
2376 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2377 {
2378         u32 phy_ctrl;
2379
2380         if ((hw->mac.type == e1000_ich10lan) ||
2381             (hw->mac.type == e1000_ich9lan)) {
2382                 phy_ctrl = er32(PHY_CTRL);
2383                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2384                             E1000_PHY_CTRL_GBE_DISABLE;
2385                 ew32(PHY_CTRL, phy_ctrl);
2386         }
2387
2388         return;
2389 }
2390
2391 /**
2392  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2393  *  @hw: pointer to the HW structure
2394  *
2395  *  Return the LED back to the default configuration.
2396  **/
2397 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2398 {
2399         if (hw->phy.type == e1000_phy_ife)
2400                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2401
2402         ew32(LEDCTL, hw->mac.ledctl_default);
2403         return 0;
2404 }
2405
2406 /**
2407  *  e1000_led_on_ich8lan - Turn LEDs on
2408  *  @hw: pointer to the HW structure
2409  *
2410  *  Turn on the LEDs.
2411  **/
2412 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2413 {
2414         if (hw->phy.type == e1000_phy_ife)
2415                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2416                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2417
2418         ew32(LEDCTL, hw->mac.ledctl_mode2);
2419         return 0;
2420 }
2421
2422 /**
2423  *  e1000_led_off_ich8lan - Turn LEDs off
2424  *  @hw: pointer to the HW structure
2425  *
2426  *  Turn off the LEDs.
2427  **/
2428 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2429 {
2430         if (hw->phy.type == e1000_phy_ife)
2431                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2432                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2433
2434         ew32(LEDCTL, hw->mac.ledctl_mode1);
2435         return 0;
2436 }
2437
2438 /**
2439  *  e1000_get_cfg_done_ich8lan - Read config done bit
2440  *  @hw: pointer to the HW structure
2441  *
2442  *  Read the management control register for the config done bit for
2443  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2444  *  to read the config done bit, so an error is *ONLY* logged and returns
2445  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2446  *  would not be able to be reset or change link.
2447  **/
2448 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2449 {
2450         u32 bank = 0;
2451
2452         e1000e_get_cfg_done(hw);
2453
2454         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2455         if (hw->mac.type != e1000_ich10lan) {
2456                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2457                     (hw->phy.type == e1000_phy_igp_3)) {
2458                         e1000e_phy_init_script_igp3(hw);
2459                 }
2460         } else {
2461                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2462                         /* Maybe we should do a basic PHY config */
2463                         hw_dbg(hw, "EEPROM not present\n");
2464                         return -E1000_ERR_CONFIG;
2465                 }
2466         }
2467
2468         return 0;
2469 }
2470
2471 /**
2472  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2473  *  @hw: pointer to the HW structure
2474  *
2475  *  Clears hardware counters specific to the silicon family and calls
2476  *  clear_hw_cntrs_generic to clear all general purpose counters.
2477  **/
2478 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2479 {
2480         u32 temp;
2481
2482         e1000e_clear_hw_cntrs_base(hw);
2483
2484         temp = er32(ALGNERRC);
2485         temp = er32(RXERRC);
2486         temp = er32(TNCRS);
2487         temp = er32(CEXTERR);
2488         temp = er32(TSCTC);
2489         temp = er32(TSCTFC);
2490
2491         temp = er32(MGTPRC);
2492         temp = er32(MGTPDC);
2493         temp = er32(MGTPTC);
2494
2495         temp = er32(IAC);
2496         temp = er32(ICRXOC);
2497
2498 }
2499
2500 static struct e1000_mac_operations ich8_mac_ops = {
2501         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
2502         .check_for_link         = e1000e_check_for_copper_link,
2503         .cleanup_led            = e1000_cleanup_led_ich8lan,
2504         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2505         .get_bus_info           = e1000_get_bus_info_ich8lan,
2506         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2507         .led_on                 = e1000_led_on_ich8lan,
2508         .led_off                = e1000_led_off_ich8lan,
2509         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2510         .reset_hw               = e1000_reset_hw_ich8lan,
2511         .init_hw                = e1000_init_hw_ich8lan,
2512         .setup_link             = e1000_setup_link_ich8lan,
2513         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2514 };
2515
2516 static struct e1000_phy_operations ich8_phy_ops = {
2517         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2518         .check_reset_block      = e1000_check_reset_block_ich8lan,
2519         .commit_phy             = NULL,
2520         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2521         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2522         .get_cable_length       = e1000e_get_cable_length_igp_2,
2523         .get_phy_info           = e1000_get_phy_info_ich8lan,
2524         .read_phy_reg           = e1000e_read_phy_reg_igp,
2525         .release_phy            = e1000_release_swflag_ich8lan,
2526         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2527         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2528         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2529         .write_phy_reg          = e1000e_write_phy_reg_igp,
2530 };
2531
2532 static struct e1000_nvm_operations ich8_nvm_ops = {
2533         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2534         .read_nvm               = e1000_read_nvm_ich8lan,
2535         .release_nvm            = e1000_release_swflag_ich8lan,
2536         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2537         .valid_led_default      = e1000_valid_led_default_ich8lan,
2538         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2539         .write_nvm              = e1000_write_nvm_ich8lan,
2540 };
2541
2542 struct e1000_info e1000_ich8_info = {
2543         .mac                    = e1000_ich8lan,
2544         .flags                  = FLAG_HAS_WOL
2545                                   | FLAG_IS_ICH
2546                                   | FLAG_RX_CSUM_ENABLED
2547                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2548                                   | FLAG_HAS_AMT
2549                                   | FLAG_HAS_FLASH
2550                                   | FLAG_APME_IN_WUC,
2551         .pba                    = 8,
2552         .get_variants           = e1000_get_variants_ich8lan,
2553         .mac_ops                = &ich8_mac_ops,
2554         .phy_ops                = &ich8_phy_ops,
2555         .nvm_ops                = &ich8_nvm_ops,
2556 };
2557
2558 struct e1000_info e1000_ich9_info = {
2559         .mac                    = e1000_ich9lan,
2560         .flags                  = FLAG_HAS_JUMBO_FRAMES
2561                                   | FLAG_IS_ICH
2562                                   | FLAG_HAS_WOL
2563                                   | FLAG_RX_CSUM_ENABLED
2564                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2565                                   | FLAG_HAS_AMT
2566                                   | FLAG_HAS_ERT
2567                                   | FLAG_HAS_FLASH
2568                                   | FLAG_APME_IN_WUC,
2569         .pba                    = 10,
2570         .get_variants           = e1000_get_variants_ich8lan,
2571         .mac_ops                = &ich8_mac_ops,
2572         .phy_ops                = &ich8_phy_ops,
2573         .nvm_ops                = &ich8_nvm_ops,
2574 };
2575
2576 struct e1000_info e1000_ich10_info = {
2577         .mac                    = e1000_ich10lan,
2578         .flags                  = FLAG_HAS_JUMBO_FRAMES
2579                                   | FLAG_IS_ICH
2580                                   | FLAG_HAS_WOL
2581                                   | FLAG_RX_CSUM_ENABLED
2582                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2583                                   | FLAG_HAS_AMT
2584                                   | FLAG_HAS_ERT
2585                                   | FLAG_HAS_FLASH
2586                                   | FLAG_APME_IN_WUC,
2587         .pba                    = 10,
2588         .get_variants           = e1000_get_variants_ich8lan,
2589         .mac_ops                = &ich8_mac_ops,
2590         .phy_ops                = &ich8_phy_ops,
2591         .nvm_ops                = &ich8_nvm_ops,
2592 };