2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/if_bridge.h>
13 #include <linux/jiffies.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/netdevice.h>
17 #include <linux/phy.h>
19 #include "mv88e6xxx.h"
21 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
22 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
23 * will be directly accessible on some {device address,register address}
24 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
25 * will only respond to SMI transactions to that specific address, and
26 * an indirect addressing mechanism needs to be used to access its
29 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
34 for (i = 0; i < 16; i++) {
35 ret = mdiobus_read(bus, sw_addr, 0);
39 if ((ret & 0x8000) == 0)
46 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
51 return mdiobus_read(bus, addr, reg);
53 /* Wait for the bus to become free. */
54 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
58 /* Transmit the read command. */
59 ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
63 /* Wait for the read command to complete. */
64 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
69 ret = mdiobus_read(bus, sw_addr, 1);
76 /* Must be called with SMI mutex held */
77 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
79 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
85 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
89 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
95 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
100 mutex_lock(&ps->smi_mutex);
101 ret = _mv88e6xxx_reg_read(ds, addr, reg);
102 mutex_unlock(&ps->smi_mutex);
107 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
113 return mdiobus_write(bus, addr, reg, val);
115 /* Wait for the bus to become free. */
116 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
120 /* Transmit the data to write. */
121 ret = mdiobus_write(bus, sw_addr, 1, val);
125 /* Transmit the write command. */
126 ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
130 /* Wait for the write command to complete. */
131 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
138 /* Must be called with SMI mutex held */
139 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
142 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
147 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
150 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
153 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
155 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158 mutex_lock(&ps->smi_mutex);
159 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
160 mutex_unlock(&ps->smi_mutex);
165 int mv88e6xxx_config_prio(struct dsa_switch *ds)
167 /* Configure the IP ToS mapping registers. */
168 REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
169 REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
170 REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
171 REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
172 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
173 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
174 REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
175 REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
177 /* Configure the IEEE 802.1p priority mapping register. */
178 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
183 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
185 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
186 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
187 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
192 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
197 for (i = 0; i < 6; i++) {
200 /* Write the MAC address byte. */
201 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
203 /* Wait for the write to complete. */
204 for (j = 0; j < 16; j++) {
205 ret = REG_READ(REG_GLOBAL2, 0x0d);
206 if ((ret & 0x8000) == 0)
216 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
219 return mv88e6xxx_reg_read(ds, addr, regnum);
223 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
226 return mv88e6xxx_reg_write(ds, addr, regnum, val);
230 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
231 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
234 unsigned long timeout;
236 ret = REG_READ(REG_GLOBAL, 0x04);
237 REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
239 timeout = jiffies + 1 * HZ;
240 while (time_before(jiffies, timeout)) {
241 ret = REG_READ(REG_GLOBAL, 0x00);
242 usleep_range(1000, 2000);
243 if ((ret & 0xc000) != 0xc000)
250 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
253 unsigned long timeout;
255 ret = REG_READ(REG_GLOBAL, 0x04);
256 REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
258 timeout = jiffies + 1 * HZ;
259 while (time_before(jiffies, timeout)) {
260 ret = REG_READ(REG_GLOBAL, 0x00);
261 usleep_range(1000, 2000);
262 if ((ret & 0xc000) == 0xc000)
269 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
271 struct mv88e6xxx_priv_state *ps;
273 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
274 if (mutex_trylock(&ps->ppu_mutex)) {
275 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
277 if (mv88e6xxx_ppu_enable(ds) == 0)
278 ps->ppu_disabled = 0;
279 mutex_unlock(&ps->ppu_mutex);
283 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
285 struct mv88e6xxx_priv_state *ps = (void *)_ps;
287 schedule_work(&ps->ppu_work);
290 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
292 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
295 mutex_lock(&ps->ppu_mutex);
297 /* If the PHY polling unit is enabled, disable it so that
298 * we can access the PHY registers. If it was already
299 * disabled, cancel the timer that is going to re-enable
302 if (!ps->ppu_disabled) {
303 ret = mv88e6xxx_ppu_disable(ds);
305 mutex_unlock(&ps->ppu_mutex);
308 ps->ppu_disabled = 1;
310 del_timer(&ps->ppu_timer);
317 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
319 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
321 /* Schedule a timer to re-enable the PHY polling unit. */
322 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
323 mutex_unlock(&ps->ppu_mutex);
326 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
330 mutex_init(&ps->ppu_mutex);
331 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
332 init_timer(&ps->ppu_timer);
333 ps->ppu_timer.data = (unsigned long)ps;
334 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
337 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
341 ret = mv88e6xxx_ppu_access_get(ds);
343 ret = mv88e6xxx_reg_read(ds, addr, regnum);
344 mv88e6xxx_ppu_access_put(ds);
350 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
355 ret = mv88e6xxx_ppu_access_get(ds);
357 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
358 mv88e6xxx_ppu_access_put(ds);
365 void mv88e6xxx_poll_link(struct dsa_switch *ds)
369 for (i = 0; i < DSA_MAX_PORTS; i++) {
370 struct net_device *dev;
371 int uninitialized_var(port_status);
382 if (dev->flags & IFF_UP) {
383 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
387 link = !!(port_status & 0x0800);
391 if (netif_carrier_ok(dev)) {
392 netdev_info(dev, "link down\n");
393 netif_carrier_off(dev);
398 switch (port_status & 0x0300) {
412 duplex = (port_status & 0x0400) ? 1 : 0;
413 fc = (port_status & 0x8000) ? 1 : 0;
415 if (!netif_carrier_ok(dev)) {
417 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
419 duplex ? "full" : "half",
421 netif_carrier_on(dev);
426 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
431 for (i = 0; i < 10; i++) {
432 ret = REG_READ(REG_GLOBAL, 0x1d);
433 if ((ret & 0x8000) == 0)
440 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
444 /* Snapshot the hardware statistics counters for this port. */
445 REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
447 /* Wait for the snapshotting to complete. */
448 ret = mv88e6xxx_stats_wait(ds);
455 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
462 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
466 ret = mv88e6xxx_stats_wait(ds);
470 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
476 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
483 void mv88e6xxx_get_strings(struct dsa_switch *ds,
484 int nr_stats, struct mv88e6xxx_hw_stat *stats,
485 int port, uint8_t *data)
489 for (i = 0; i < nr_stats; i++) {
490 memcpy(data + i * ETH_GSTRING_LEN,
491 stats[i].string, ETH_GSTRING_LEN);
495 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
496 int nr_stats, struct mv88e6xxx_hw_stat *stats,
497 int port, uint64_t *data)
499 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
503 mutex_lock(&ps->stats_mutex);
505 ret = mv88e6xxx_stats_snapshot(ds, port);
507 mutex_unlock(&ps->stats_mutex);
511 /* Read each of the counters. */
512 for (i = 0; i < nr_stats; i++) {
513 struct mv88e6xxx_hw_stat *s = stats + i;
517 if (s->reg >= 0x100) {
520 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
525 if (s->sizeof_stat == 4) {
526 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
532 data[i] = (((u64)high) << 16) | low;
535 mv88e6xxx_stats_read(ds, s->reg, &low);
536 if (s->sizeof_stat == 8)
537 mv88e6xxx_stats_read(ds, s->reg + 1, &high);
539 data[i] = (((u64)high) << 32) | low;
542 mutex_unlock(&ps->stats_mutex);
545 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
547 return 32 * sizeof(u16);
550 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
551 struct ethtool_regs *regs, void *_p)
558 memset(p, 0xff, 32 * sizeof(u16));
560 for (i = 0; i < 32; i++) {
563 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
569 #ifdef CONFIG_NET_DSA_HWMON
571 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
573 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
579 mutex_lock(&ps->phy_mutex);
581 ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
585 /* Enable temperature sensor */
586 ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
590 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
594 /* Wait for temperature to stabilize */
595 usleep_range(10000, 12000);
597 val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
603 /* Disable temperature sensor */
604 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
608 *temp = ((val & 0x1f) - 5) * 5;
611 mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
612 mutex_unlock(&ps->phy_mutex);
615 #endif /* CONFIG_NET_DSA_HWMON */
617 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
619 unsigned long timeout = jiffies + HZ / 10;
621 while (time_before(jiffies, timeout)) {
624 ret = REG_READ(reg, offset);
628 usleep_range(1000, 2000);
633 int mv88e6xxx_phy_wait(struct dsa_switch *ds)
635 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x18, 0x8000);
638 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
640 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x0800);
643 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
645 return mv88e6xxx_wait(ds, REG_GLOBAL2, 0x14, 0x8000);
648 /* Must be called with SMI lock held */
649 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
651 unsigned long timeout = jiffies + HZ / 10;
653 while (time_before(jiffies, timeout)) {
656 ret = _mv88e6xxx_reg_read(ds, reg, offset);
662 usleep_range(1000, 2000);
667 /* Must be called with SMI lock held */
668 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
670 return _mv88e6xxx_wait(ds, REG_GLOBAL, 0x0b, ATU_BUSY);
673 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum)
677 REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
679 ret = mv88e6xxx_phy_wait(ds);
683 return REG_READ(REG_GLOBAL2, 0x19);
686 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
689 REG_WRITE(REG_GLOBAL2, 0x19, val);
690 REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
692 return mv88e6xxx_phy_wait(ds);
695 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
699 reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
703 e->eee_enabled = !!(reg & 0x0200);
704 e->tx_lpi_enabled = !!(reg & 0x0100);
706 reg = REG_READ(REG_PORT(port), 0);
707 e->eee_active = !!(reg & 0x0040);
712 static int mv88e6xxx_eee_enable_set(struct dsa_switch *ds, int port,
713 bool eee_enabled, bool tx_lpi_enabled)
717 reg = mv88e6xxx_phy_read_indirect(ds, port, 16);
721 nreg = reg & ~0x0300;
728 return mv88e6xxx_phy_write_indirect(ds, port, 16, nreg);
733 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
734 struct phy_device *phydev, struct ethtool_eee *e)
738 ret = mv88e6xxx_eee_enable_set(ds, port, e->eee_enabled,
746 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd)
750 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid);
754 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x0b, cmd);
758 return _mv88e6xxx_atu_wait(ds);
761 static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid)
765 ret = _mv88e6xxx_atu_wait(ds);
769 return _mv88e6xxx_atu_cmd(ds, fid, ATU_CMD_FLUSH_NONSTATIC_FID);
772 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
774 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
778 mutex_lock(&ps->smi_mutex);
780 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), 0x04);
784 oldstate = reg & PSTATE_MASK;
785 if (oldstate != state) {
786 /* Flush forwarding database if we're moving a port
787 * from Learning or Forwarding state to Disabled or
788 * Blocking or Listening state.
790 if (oldstate >= PSTATE_LEARNING && state <= PSTATE_BLOCKING) {
791 ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]);
795 reg = (reg & ~PSTATE_MASK) | state;
796 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x04, reg);
800 mutex_unlock(&ps->smi_mutex);
804 /* Must be called with smi lock held */
805 static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port)
807 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
808 u8 fid = ps->fid[port];
811 if (dsa_is_cpu_port(ds, port))
812 reg |= ds->phys_port_mask;
814 reg |= (ps->bridge_mask[fid] |
815 (1 << dsa_upstream_port(ds))) & ~(1 << port);
817 return _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x06, reg);
820 /* Must be called with smi lock held */
821 static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid)
823 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
828 mask = ds->phys_port_mask;
831 mask &= ~(1 << port);
832 if (ps->fid[port] != fid)
835 ret = _mv88e6xxx_update_port_config(ds, port);
840 return _mv88e6xxx_flush_fid(ds, fid);
843 /* Bridge handling functions */
845 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
847 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
852 /* If the bridge group is not empty, join that group.
853 * Otherwise create a new group.
856 nmask = br_port_mask & ~(1 << port);
858 fid = ps->fid[__ffs(nmask)];
860 nmask = ps->bridge_mask[fid] | (1 << port);
861 if (nmask != br_port_mask) {
862 netdev_err(ds->ports[port],
863 "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
864 fid, br_port_mask, nmask);
868 mutex_lock(&ps->smi_mutex);
870 ps->bridge_mask[fid] = br_port_mask;
872 if (fid != ps->fid[port]) {
873 ps->fid_mask |= 1 << ps->fid[port];
875 ret = _mv88e6xxx_update_bridge_config(ds, fid);
878 mutex_unlock(&ps->smi_mutex);
883 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask)
885 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
891 if (ps->bridge_mask[fid] != br_port_mask) {
892 netdev_err(ds->ports[port],
893 "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n",
894 fid, br_port_mask, ps->bridge_mask[fid]);
898 /* If the port was the last port of a bridge, we are done.
899 * Otherwise assign a new fid to the port, and fix up
900 * the bridge configuration.
902 if (br_port_mask == (1 << port))
905 mutex_lock(&ps->smi_mutex);
907 newfid = __ffs(ps->fid_mask);
908 ps->fid[port] = newfid;
909 ps->fid_mask &= (1 << newfid);
910 ps->bridge_mask[fid] &= ~(1 << port);
911 ps->bridge_mask[newfid] = 1 << port;
913 ret = _mv88e6xxx_update_bridge_config(ds, fid);
915 ret = _mv88e6xxx_update_bridge_config(ds, newfid);
917 mutex_unlock(&ps->smi_mutex);
922 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
924 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
928 case BR_STATE_DISABLED:
929 stp_state = PSTATE_DISABLED;
931 case BR_STATE_BLOCKING:
932 case BR_STATE_LISTENING:
933 stp_state = PSTATE_BLOCKING;
935 case BR_STATE_LEARNING:
936 stp_state = PSTATE_LEARNING;
938 case BR_STATE_FORWARDING:
940 stp_state = PSTATE_FORWARDING;
944 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
946 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
947 * so we can not update the port state directly but need to schedule it.
949 ps->port_state[port] = stp_state;
950 set_bit(port, &ps->port_state_update_mask);
951 schedule_work(&ps->bridge_work);
956 static void mv88e6xxx_bridge_work(struct work_struct *work)
958 struct mv88e6xxx_priv_state *ps;
959 struct dsa_switch *ds;
962 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
963 ds = ((struct dsa_switch *)ps) - 1;
965 while (ps->port_state_update_mask) {
966 port = __ffs(ps->port_state_update_mask);
967 clear_bit(port, &ps->port_state_update_mask);
968 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
972 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port)
974 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
977 mutex_lock(&ps->smi_mutex);
979 /* Port Control 1: disable trunking, disable sending
980 * learning messages to this port.
982 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x05, 0x0000);
986 /* Port based VLAN map: give each port its own address
987 * database, allow the CPU port to talk to each of the 'real'
988 * ports, and allow each of the 'real' ports to only talk to
991 fid = __ffs(ps->fid_mask);
993 ps->fid_mask &= ~(1 << fid);
995 if (!dsa_is_cpu_port(ds, port))
996 ps->bridge_mask[fid] = 1 << port;
998 ret = _mv88e6xxx_update_port_config(ds, port);
1002 /* Default VLAN ID and priority: don't set a default VLAN
1003 * ID, and set the default packet priority to zero.
1005 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000);
1007 mutex_unlock(&ps->smi_mutex);
1011 int mv88e6xxx_setup_common(struct dsa_switch *ds)
1013 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1015 mutex_init(&ps->smi_mutex);
1016 mutex_init(&ps->stats_mutex);
1017 mutex_init(&ps->phy_mutex);
1019 ps->fid_mask = (1 << DSA_MAX_PORTS) - 1;
1021 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
1026 static int __init mv88e6xxx_init(void)
1028 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1029 register_switch_driver(&mv88e6131_switch_driver);
1031 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1032 register_switch_driver(&mv88e6123_61_65_switch_driver);
1034 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
1035 register_switch_driver(&mv88e6352_switch_driver);
1037 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1038 register_switch_driver(&mv88e6171_switch_driver);
1042 module_init(mv88e6xxx_init);
1044 static void __exit mv88e6xxx_cleanup(void)
1046 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
1047 unregister_switch_driver(&mv88e6171_switch_driver);
1049 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
1050 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
1052 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
1053 unregister_switch_driver(&mv88e6131_switch_driver);
1056 module_exit(mv88e6xxx_cleanup);
1058 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
1059 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
1060 MODULE_LICENSE("GPL");