2 * This file is part of the Chelsio T3 Ethernet driver.
4 * Copyright (C) 2003-2006 Chelsio Communications. All rights reserved.
6 * This program is distributed in the hope that it will be useful, but WITHOUT
7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
9 * release for licensing terms and conditions.
20 /* DBGI command mode */
23 DBGI_MODE_IDT52100 = 5
26 /* IDT 75P52100 commands */
27 #define IDT_CMD_READ 0
28 #define IDT_CMD_WRITE 1
29 #define IDT_CMD_SEARCH 2
30 #define IDT_CMD_LEARN 3
32 /* IDT LAR register address and value for 144-bit mode (low 32 bits) */
33 #define IDT_LAR_ADR0 0x180006
34 #define IDT_LAR_MODE144 0xffff0000
36 /* IDT SCR and SSR addresses (low 32 bits) */
37 #define IDT_SCR_ADR0 0x180000
38 #define IDT_SSR0_ADR0 0x180002
39 #define IDT_SSR1_ADR0 0x180004
41 /* IDT GMR base address (low 32 bits) */
42 #define IDT_GMR_BASE_ADR0 0x180020
44 /* IDT data and mask array base addresses (low 32 bits) */
45 #define IDT_DATARY_BASE_ADR0 0
46 #define IDT_MSKARY_BASE_ADR0 0x80000
48 /* IDT 75N43102 commands */
49 #define IDT4_CMD_SEARCH144 3
50 #define IDT4_CMD_WRITE 4
51 #define IDT4_CMD_READ 5
53 /* IDT 75N43102 SCR address (low 32 bits) */
54 #define IDT4_SCR_ADR0 0x3
56 /* IDT 75N43102 GMR base addresses (low 32 bits) */
57 #define IDT4_GMR_BASE0 0x10
58 #define IDT4_GMR_BASE1 0x20
59 #define IDT4_GMR_BASE2 0x30
61 /* IDT 75N43102 data and mask array base addresses (low 32 bits) */
62 #define IDT4_DATARY_BASE_ADR0 0x1000000
63 #define IDT4_MSKARY_BASE_ADR0 0x2000000
65 #define MAX_WRITE_ATTEMPTS 5
67 #define MAX_ROUTES 2048
70 * Issue a command to the TCAM and wait for its completion. The address and
71 * any data required by the command must have been setup by the caller.
73 static int mc5_cmd_write(struct adapter *adapter, u32 cmd)
75 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd);
76 return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS,
77 F_DBGIRSPVALID, 1, MAX_WRITE_ATTEMPTS, 1);
80 static inline void dbgi_wr_addr3(struct adapter *adapter, u32 v1, u32 v2,
83 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1);
84 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2);
85 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3);
88 static inline void dbgi_wr_data3(struct adapter *adapter, u32 v1, u32 v2,
91 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1);
92 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2);
93 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3);
96 static inline void dbgi_rd_rsp3(struct adapter *adapter, u32 *v1, u32 *v2,
99 *v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0);
100 *v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1);
101 *v3 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA2);
105 * Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
106 * command cmd. The data to be written must have been set up by the caller.
107 * Returns -1 on failure, 0 on success.
109 static int mc5_write(struct adapter *adapter, u32 addr_lo, u32 cmd)
111 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo);
112 if (mc5_cmd_write(adapter, cmd) == 0)
114 CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n",
119 static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base,
120 u32 data_array_base, u32 write_cmd,
124 struct adapter *adap = mc5->adapter;
127 * We need the size of the TCAM data and mask arrays in terms of
130 unsigned int size72 = mc5->tcam_size;
131 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
133 if (mc5->mode == MC5_MODE_144_BIT) {
134 size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */
138 /* Clear the data array */
139 dbgi_wr_data3(adap, 0, 0, 0);
140 for (i = 0; i < size72; i++)
141 if (mc5_write(adap, data_array_base + (i << addr_shift),
145 /* Initialize the mask array. */
146 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
147 for (i = 0; i < size72; i++) {
148 if (i == server_base) /* entering server or routing region */
149 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0,
150 mc5->mode == MC5_MODE_144_BIT ?
151 0xfffffff9 : 0xfffffffd);
152 if (mc5_write(adap, mask_array_base + (i << addr_shift),
159 static int init_idt52100(struct mc5 *mc5)
162 struct adapter *adap = mc5->adapter;
164 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
165 V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15));
166 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2);
169 * Use GMRs 14-15 for ELOOKUP, GMRs 12-13 for SYN lookups, and
170 * GMRs 8-9 for ACK- and AOPEN searches.
172 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE);
173 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE);
174 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH);
175 t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN);
176 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);
177 t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN);
178 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH);
179 t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN);
180 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH);
181 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);
182 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE);
183 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ);
185 /* Set DBGI command mode for IDT TCAM. */
186 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
189 dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);
190 if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE))
194 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
195 if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) ||
196 mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE))
200 for (i = 0; i < 32; ++i) {
201 if (i >= 12 && i < 15)
202 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
204 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
206 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
208 if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE))
213 dbgi_wr_data3(adap, 1, 0, 0);
214 if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE))
217 return init_mask_data_array(mc5, IDT_MSKARY_BASE_ADR0,
218 IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0);
223 static int init_idt43102(struct mc5 *mc5)
226 struct adapter *adap = mc5->adapter;
228 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
229 adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :
230 V_RDLAT(0xd) | V_SRCHLAT(0x12));
233 * Use GMRs 24-25 for ELOOKUP, GMRs 20-21 for SYN lookups, and no mask
234 * for ACK- and AOPEN searches.
236 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE);
237 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE);
238 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD,
239 IDT4_CMD_SEARCH144 | 0x3800);
240 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144);
241 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);
242 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);
243 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);
244 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE);
245 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ);
247 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3);
249 /* Set DBGI command mode for IDT TCAM. */
250 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
253 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
254 for (i = 0; i < 7; ++i)
255 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE))
258 for (i = 0; i < 4; ++i)
259 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE))
262 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
263 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) ||
264 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) ||
265 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE))
268 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
269 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE))
273 dbgi_wr_data3(adap, 0xf0000000, 0, 0);
274 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE))
277 return init_mask_data_array(mc5, IDT4_MSKARY_BASE_ADR0,
278 IDT4_DATARY_BASE_ADR0, IDT4_CMD_WRITE, 1);
283 /* Put MC5 in DBGI mode. */
284 static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5)
286 t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
287 V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_DBGIEN);
290 /* Put MC5 in M-Bus mode. */
291 static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
293 t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
294 V_TMMODE(mc5->mode == MC5_MODE_72_BIT) |
295 V_COMPEN(mc5->mode == MC5_MODE_72_BIT) |
296 V_PRTYEN(mc5->parity_enabled) | F_MBUSEN);
300 * Initialization that requires the OS and protocol layers to already
301 * be intialized goes here.
303 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
304 unsigned int nroutes)
308 unsigned int tcam_size = mc5->tcam_size;
309 struct adapter *adap = mc5->adapter;
311 if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size)
315 cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
316 cfg |= V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_TMRST;
317 t3_write_reg(adap, A_MC5_DB_CONFIG, cfg);
318 if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
319 CH_ERR(adap, "TCAM reset timed out\n");
323 t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes);
324 t3_write_reg(adap, A_MC5_DB_FILTER_TABLE,
325 tcam_size - nroutes - nfilters);
326 t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
327 tcam_size - nroutes - nfilters - nservers);
329 mc5->parity_enabled = 1;
331 /* All the TCAM addresses we access have only the low 32 bits non 0 */
332 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
333 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
335 mc5_dbgi_mode_enable(mc5);
337 switch (mc5->part_type) {
339 err = init_idt52100(mc5);
342 err = init_idt43102(mc5);
345 CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type);
350 mc5_dbgi_mode_disable(mc5);
355 * read_mc5_range - dump a part of the memory managed by MC5
356 * @mc5: the MC5 handle
357 * @start: the start address for the dump
358 * @n: number of 72-bit words to read
359 * @buf: result buffer
361 * Read n 72-bit words from MC5 memory from the given start location.
363 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start,
364 unsigned int n, u32 *buf)
368 struct adapter *adap = mc5->adapter;
370 if (mc5->part_type == IDT75P52100)
371 read_cmd = IDT_CMD_READ;
372 else if (mc5->part_type == IDT75N43102)
373 read_cmd = IDT4_CMD_READ;
377 mc5_dbgi_mode_enable(mc5);
380 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR0, start++);
381 if (mc5_cmd_write(adap, read_cmd)) {
385 dbgi_rd_rsp3(adap, buf + 2, buf + 1, buf);
389 mc5_dbgi_mode_disable(mc5);
393 #define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR)
396 * MC5 interrupt handler
398 void t3_mc5_intr_handler(struct mc5 *mc5)
400 struct adapter *adap = mc5->adapter;
401 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
403 if ((cause & F_PARITYERR) && mc5->parity_enabled) {
404 CH_ALERT(adap, "MC5 parity error\n");
405 mc5->stats.parity_err++;
408 if (cause & F_REQQPARERR) {
409 CH_ALERT(adap, "MC5 request queue parity error\n");
410 mc5->stats.reqq_parity_err++;
413 if (cause & F_DISPQPARERR) {
414 CH_ALERT(adap, "MC5 dispatch queue parity error\n");
415 mc5->stats.dispq_parity_err++;
418 if (cause & F_ACTRGNFULL)
419 mc5->stats.active_rgn_full++;
420 if (cause & F_NFASRCHFAIL)
421 mc5->stats.nfa_srch_err++;
422 if (cause & F_UNKNOWNCMD)
423 mc5->stats.unknown_cmd++;
424 if (cause & F_DELACTEMPTY)
425 mc5->stats.del_act_empty++;
426 if (cause & MC5_INT_FATAL)
429 t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause);
432 void __devinit t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode)
436 static unsigned int tcam_part_size[] = { /* in K 72-bit entries */
437 64 K, 128 K, 256 K, 32 K
442 u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
444 mc5->adapter = adapter;
445 mc5->mode = (unsigned char)mode;
446 mc5->part_type = (unsigned char)G_TMTYPE(cfg);
447 if (cfg & F_TMTYPEHI)
450 mc5->tcam_size = tcam_part_size[G_TMPARTSIZE(cfg)];
451 if (mode == MC5_MODE_144_BIT)