1 /* Copyright 2008-2009 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/delay.h>
22 #include <linux/ethtool.h>
23 #include <linux/mutex.h>
27 /********************************************************/
29 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
30 #define ETH_MIN_PACKET_SIZE 60
31 #define ETH_MAX_PACKET_SIZE 1500
32 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
33 #define MDIO_ACCESS_TIMEOUT 1000
34 #define BMAC_CONTROL_RX_ENABLE 2
36 /***********************************************************/
37 /* Shortcut definitions */
38 /***********************************************************/
40 #define NIG_LATCH_BC_ENABLE_MI_INT 0
42 #define NIG_STATUS_EMAC0_MI_INT \
43 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
44 #define NIG_STATUS_XGXS0_LINK10G \
45 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
46 #define NIG_STATUS_XGXS0_LINK_STATUS \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
48 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
50 #define NIG_STATUS_SERDES0_LINK_STATUS \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
52 #define NIG_MASK_MI_INT \
53 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
54 #define NIG_MASK_XGXS0_LINK10G \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
56 #define NIG_MASK_XGXS0_LINK_STATUS \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
58 #define NIG_MASK_SERDES0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
61 #define MDIO_AN_CL73_OR_37_COMPLETE \
62 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
63 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
65 #define XGXS_RESET_BITS \
66 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
67 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
68 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
72 #define SERDES_RESET_BITS \
73 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
74 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
75 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
78 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
79 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
80 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
81 #define AUTONEG_PARALLEL \
82 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
83 #define AUTONEG_SGMII_FIBER_AUTODET \
84 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
85 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
87 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
88 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
89 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
91 #define GP_STATUS_SPEED_MASK \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
93 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
94 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
95 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
96 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
97 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
98 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
99 #define GP_STATUS_10G_HIG \
100 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
101 #define GP_STATUS_10G_CX4 \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
103 #define GP_STATUS_12G_HIG \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
105 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
106 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
107 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
108 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
109 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
110 #define GP_STATUS_10G_KX4 \
111 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
113 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
114 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
115 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
116 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
117 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
118 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
119 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
120 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
121 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
122 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
123 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
124 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
125 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
126 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
127 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
128 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
129 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
130 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
131 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
132 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
133 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
134 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
135 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
137 #define PHY_XGXS_FLAG 0x1
138 #define PHY_SGMII_FLAG 0x2
139 #define PHY_SERDES_FLAG 0x4
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
166 /**********************************************************/
168 /**********************************************************/
169 #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
170 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
171 DEFAULT_PHY_DEV_ADDR, \
172 (_bank + (_addr & 0xf)), \
175 #define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
176 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
177 DEFAULT_PHY_DEV_ADDR, \
178 (_bank + (_addr & 0xf)), \
181 static void bnx2x_set_serdes_access(struct link_params *params)
183 struct bnx2x *bp = params->bp;
184 u32 emac_base = (params->port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
186 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 1);
187 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
189 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
192 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + params->port*0x10, 0);
194 static void bnx2x_set_phy_mdio(struct link_params *params, u8 phy_flags)
196 struct bnx2x *bp = params->bp;
197 if (phy_flags & PHY_XGXS_FLAG) {
198 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
199 params->port*0x18, 0);
200 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
201 DEFAULT_PHY_DEV_ADDR);
203 bnx2x_set_serdes_access(params);
205 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
207 DEFAULT_PHY_DEV_ADDR);
211 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
213 u32 val = REG_RD(bp, reg);
216 REG_WR(bp, reg, val);
220 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
222 u32 val = REG_RD(bp, reg);
225 REG_WR(bp, reg, val);
229 static void bnx2x_emac_init(struct link_params *params,
230 struct link_vars *vars)
232 /* reset and unreset the emac core */
233 struct bnx2x *bp = params->bp;
234 u8 port = params->port;
235 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
239 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
240 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
242 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
243 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
245 /* init emac - use read-modify-write */
246 /* self clear reset */
247 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
248 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
252 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
253 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
255 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
259 } while (val & EMAC_MODE_RESET);
261 /* Set mac address */
262 val = ((params->mac_addr[0] << 8) |
263 params->mac_addr[1]);
264 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
266 val = ((params->mac_addr[2] << 24) |
267 (params->mac_addr[3] << 16) |
268 (params->mac_addr[4] << 8) |
269 params->mac_addr[5]);
270 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
273 static u8 bnx2x_emac_enable(struct link_params *params,
274 struct link_vars *vars, u8 lb)
276 struct bnx2x *bp = params->bp;
277 u8 port = params->port;
278 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
281 DP(NETIF_MSG_LINK, "enabling EMAC\n");
283 /* enable emac and not bmac */
284 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
287 if (CHIP_REV_IS_EMUL(bp)) {
288 /* Use lane 1 (of lanes 0-3) */
289 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
290 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
296 if (CHIP_REV_IS_FPGA(bp)) {
297 /* Use lane 1 (of lanes 0-3) */
298 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
300 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
301 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
305 if (vars->phy_flags & PHY_XGXS_FLAG) {
306 u32 ser_lane = ((params->lane_config &
307 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
308 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
310 DP(NETIF_MSG_LINK, "XGXS\n");
311 /* select the master lanes (out of 0-3) */
312 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
315 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
318 } else { /* SerDes */
319 DP(NETIF_MSG_LINK, "SerDes\n");
321 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
325 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
327 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
330 if (CHIP_REV_IS_SLOW(bp)) {
331 /* config GMII mode */
332 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
333 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
334 (val | EMAC_MODE_PORT_GMII));
336 /* pause enable/disable */
337 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
338 EMAC_RX_MODE_FLOW_EN);
339 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
340 bnx2x_bits_en(bp, emac_base +
341 EMAC_REG_EMAC_RX_MODE,
342 EMAC_RX_MODE_FLOW_EN);
344 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
345 (EMAC_TX_MODE_EXT_PAUSE_EN |
346 EMAC_TX_MODE_FLOW_EN));
347 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
348 bnx2x_bits_en(bp, emac_base +
349 EMAC_REG_EMAC_TX_MODE,
350 (EMAC_TX_MODE_EXT_PAUSE_EN |
351 EMAC_TX_MODE_FLOW_EN));
354 /* KEEP_VLAN_TAG, promiscuous */
355 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
356 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
357 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
360 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
365 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
368 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
370 /* enable emac for jumbo packets */
371 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
372 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
373 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
376 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
378 /* disable the NIG in/out to the bmac */
379 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
380 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
381 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
383 /* enable the NIG in/out to the emac */
384 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
386 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
389 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
390 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
392 if (CHIP_REV_IS_EMUL(bp)) {
393 /* take the BigMac out of reset */
395 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
396 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
398 /* enable access for bmac registers */
399 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
401 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
403 vars->mac_type = MAC_TYPE_EMAC;
409 static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
412 struct bnx2x *bp = params->bp;
413 u8 port = params->port;
414 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
415 NIG_REG_INGRESS_BMAC0_MEM;
419 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
420 /* reset and unreset the BigMac */
421 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
422 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
425 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
426 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
428 /* enable access for bmac registers */
429 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
434 REG_WR_DMAE(bp, bmac_addr +
435 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
439 wb_data[0] = ((params->mac_addr[2] << 24) |
440 (params->mac_addr[3] << 16) |
441 (params->mac_addr[4] << 8) |
442 params->mac_addr[5]);
443 wb_data[1] = ((params->mac_addr[0] << 8) |
444 params->mac_addr[1]);
445 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
450 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
454 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
461 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
465 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
470 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
472 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
475 /* rx control set to don't strip crc */
477 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
481 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
485 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
487 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
490 /* set cnt max size */
491 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
493 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
497 wb_data[0] = 0x1000200;
499 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
501 /* fix for emulation */
502 if (CHIP_REV_IS_EMUL(bp)) {
506 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
510 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
511 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
512 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
514 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
516 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
517 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
518 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
519 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
520 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
521 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
523 vars->mac_type = MAC_TYPE_BMAC;
527 static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
529 struct bnx2x *bp = params->bp;
532 if (phy_flags & PHY_XGXS_FLAG) {
533 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
534 val = XGXS_RESET_BITS;
536 } else { /* SerDes */
537 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
538 val = SERDES_RESET_BITS;
541 val = val << (params->port*16);
543 /* reset and unreset the SerDes/XGXS */
544 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
547 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
549 bnx2x_set_phy_mdio(params, phy_flags);
552 void bnx2x_link_status_update(struct link_params *params,
553 struct link_vars *vars)
555 struct bnx2x *bp = params->bp;
557 u8 port = params->port;
559 if (params->switch_cfg == SWITCH_CFG_1G)
560 vars->phy_flags = PHY_SERDES_FLAG;
562 vars->phy_flags = PHY_XGXS_FLAG;
563 vars->link_status = REG_RD(bp, params->shmem_base +
564 offsetof(struct shmem_region,
565 port_mb[port].link_status));
567 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
570 DP(NETIF_MSG_LINK, "phy link up\n");
572 vars->phy_link_up = 1;
573 vars->duplex = DUPLEX_FULL;
574 switch (vars->link_status &
575 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
577 vars->duplex = DUPLEX_HALF;
580 vars->line_speed = SPEED_10;
584 vars->duplex = DUPLEX_HALF;
588 vars->line_speed = SPEED_100;
592 vars->duplex = DUPLEX_HALF;
595 vars->line_speed = SPEED_1000;
599 vars->duplex = DUPLEX_HALF;
602 vars->line_speed = SPEED_2500;
606 vars->line_speed = SPEED_10000;
610 vars->line_speed = SPEED_12000;
614 vars->line_speed = SPEED_12500;
618 vars->line_speed = SPEED_13000;
622 vars->line_speed = SPEED_15000;
626 vars->line_speed = SPEED_16000;
633 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
634 vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
636 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_TX;
638 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
639 vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
641 vars->flow_ctrl &= ~BNX2X_FLOW_CTRL_RX;
643 if (vars->phy_flags & PHY_XGXS_FLAG) {
644 if (vars->line_speed &&
645 ((vars->line_speed == SPEED_10) ||
646 (vars->line_speed == SPEED_100))) {
647 vars->phy_flags |= PHY_SGMII_FLAG;
649 vars->phy_flags &= ~PHY_SGMII_FLAG;
653 /* anything 10 and over uses the bmac */
654 link_10g = ((vars->line_speed == SPEED_10000) ||
655 (vars->line_speed == SPEED_12000) ||
656 (vars->line_speed == SPEED_12500) ||
657 (vars->line_speed == SPEED_13000) ||
658 (vars->line_speed == SPEED_15000) ||
659 (vars->line_speed == SPEED_16000));
661 vars->mac_type = MAC_TYPE_BMAC;
663 vars->mac_type = MAC_TYPE_EMAC;
665 } else { /* link down */
666 DP(NETIF_MSG_LINK, "phy link down\n");
668 vars->phy_link_up = 0;
670 vars->line_speed = 0;
671 vars->duplex = DUPLEX_FULL;
672 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
674 /* indicate no mac active */
675 vars->mac_type = MAC_TYPE_NONE;
678 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
679 vars->link_status, vars->phy_link_up);
680 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
681 vars->line_speed, vars->duplex, vars->flow_ctrl);
684 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
686 struct bnx2x *bp = params->bp;
687 REG_WR(bp, params->shmem_base +
688 offsetof(struct shmem_region,
689 port_mb[params->port].link_status),
693 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
695 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
696 NIG_REG_INGRESS_BMAC0_MEM;
698 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
700 /* Only if the bmac is out of reset */
701 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
702 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
705 /* Clear Rx Enable bit in BMAC_CONTROL register */
706 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
708 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
709 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
716 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
719 struct bnx2x *bp = params->bp;
720 u8 port = params->port;
725 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
727 /* wait for init credit */
728 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
729 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
730 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
732 while ((init_crd != crd) && count) {
735 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
738 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
739 if (init_crd != crd) {
740 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
745 if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
746 line_speed == SPEED_10 ||
747 line_speed == SPEED_100 ||
748 line_speed == SPEED_1000 ||
749 line_speed == SPEED_2500) {
750 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
751 /* update threshold */
752 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
753 /* update init credit */
754 init_crd = 778; /* (800-18-4) */
757 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
759 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
760 /* update threshold */
761 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
762 /* update init credit */
763 switch (line_speed) {
765 init_crd = thresh + 553 - 22;
769 init_crd = thresh + 664 - 22;
773 init_crd = thresh + 742 - 22;
777 init_crd = thresh + 778 - 22;
780 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
786 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
787 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
788 line_speed, init_crd);
790 /* probe the credit changes */
791 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
793 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
796 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
800 static u32 bnx2x_get_emac_base(struct bnx2x *bp, u32 ext_phy_type, u8 port)
803 switch (ext_phy_type) {
804 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
805 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
806 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
807 /* All MDC/MDIO is directed through single EMAC */
808 if (REG_RD(bp, NIG_REG_PORT_SWAP))
809 emac_base = GRCBASE_EMAC0;
811 emac_base = GRCBASE_EMAC1;
813 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
814 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
817 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
824 u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
825 u8 phy_addr, u8 devad, u16 reg, u16 val)
829 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
831 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
832 * (a value of 49==0x31) and make sure that the AUTO poll is off
835 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
836 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
837 EMAC_MDIO_MODE_CLOCK_CNT);
838 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
839 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
840 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
841 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
846 tmp = ((phy_addr << 21) | (devad << 16) | reg |
847 EMAC_MDIO_COMM_COMMAND_ADDRESS |
848 EMAC_MDIO_COMM_START_BUSY);
849 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
851 for (i = 0; i < 50; i++) {
854 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
855 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
860 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
861 DP(NETIF_MSG_LINK, "write phy register failed\n");
865 tmp = ((phy_addr << 21) | (devad << 16) | val |
866 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
867 EMAC_MDIO_COMM_START_BUSY);
868 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
870 for (i = 0; i < 50; i++) {
873 tmp = REG_RD(bp, mdio_ctrl +
874 EMAC_REG_EMAC_MDIO_COMM);
875 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
880 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
881 DP(NETIF_MSG_LINK, "write phy register failed\n");
886 /* Restore the saved mode */
887 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
892 u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
893 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
899 u32 mdio_ctrl = bnx2x_get_emac_base(bp, ext_phy_type, port);
900 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
901 * (a value of 49==0x31) and make sure that the AUTO poll is off
904 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
905 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
906 EMAC_MDIO_MODE_CLOCK_CNT));
907 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
908 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
909 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
910 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
914 val = ((phy_addr << 21) | (devad << 16) | reg |
915 EMAC_MDIO_COMM_COMMAND_ADDRESS |
916 EMAC_MDIO_COMM_START_BUSY);
917 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
919 for (i = 0; i < 50; i++) {
922 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
923 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
928 if (val & EMAC_MDIO_COMM_START_BUSY) {
929 DP(NETIF_MSG_LINK, "read phy register failed\n");
936 val = ((phy_addr << 21) | (devad << 16) |
937 EMAC_MDIO_COMM_COMMAND_READ_45 |
938 EMAC_MDIO_COMM_START_BUSY);
939 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
941 for (i = 0; i < 50; i++) {
944 val = REG_RD(bp, mdio_ctrl +
945 EMAC_REG_EMAC_MDIO_COMM);
946 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
947 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
951 if (val & EMAC_MDIO_COMM_START_BUSY) {
952 DP(NETIF_MSG_LINK, "read phy register failed\n");
959 /* Restore the saved mode */
960 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
965 static void bnx2x_set_aer_mmd(struct link_params *params,
966 struct link_vars *vars)
968 struct bnx2x *bp = params->bp;
972 ser_lane = ((params->lane_config &
973 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
974 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
976 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
977 (params->phy_addr + ser_lane) : 0;
979 CL45_WR_OVER_CL22(bp, params->port,
981 MDIO_REG_BANK_AER_BLOCK,
982 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
985 static void bnx2x_set_master_ln(struct link_params *params)
987 struct bnx2x *bp = params->bp;
988 u16 new_master_ln, ser_lane;
989 ser_lane = ((params->lane_config &
990 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
991 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
993 /* set the master_ln for AN */
994 CL45_RD_OVER_CL22(bp, params->port,
996 MDIO_REG_BANK_XGXS_BLOCK2,
997 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1000 CL45_WR_OVER_CL22(bp, params->port,
1002 MDIO_REG_BANK_XGXS_BLOCK2 ,
1003 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1004 (new_master_ln | ser_lane));
1007 static u8 bnx2x_reset_unicore(struct link_params *params)
1009 struct bnx2x *bp = params->bp;
1013 CL45_RD_OVER_CL22(bp, params->port,
1015 MDIO_REG_BANK_COMBO_IEEE0,
1016 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1018 /* reset the unicore */
1019 CL45_WR_OVER_CL22(bp, params->port,
1021 MDIO_REG_BANK_COMBO_IEEE0,
1022 MDIO_COMBO_IEEE0_MII_CONTROL,
1024 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1025 if (params->switch_cfg == SWITCH_CFG_1G)
1026 bnx2x_set_serdes_access(params);
1028 /* wait for the reset to self clear */
1029 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1032 /* the reset erased the previous bank value */
1033 CL45_RD_OVER_CL22(bp, params->port,
1035 MDIO_REG_BANK_COMBO_IEEE0,
1036 MDIO_COMBO_IEEE0_MII_CONTROL,
1039 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1045 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1050 static void bnx2x_set_swap_lanes(struct link_params *params)
1052 struct bnx2x *bp = params->bp;
1053 /* Each two bits represents a lane number:
1054 No swap is 0123 => 0x1b no need to enable the swap */
1055 u16 ser_lane, rx_lane_swap, tx_lane_swap;
1057 ser_lane = ((params->lane_config &
1058 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1059 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1060 rx_lane_swap = ((params->lane_config &
1061 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1062 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1063 tx_lane_swap = ((params->lane_config &
1064 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1065 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1067 if (rx_lane_swap != 0x1b) {
1068 CL45_WR_OVER_CL22(bp, params->port,
1070 MDIO_REG_BANK_XGXS_BLOCK2,
1071 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1073 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1074 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1076 CL45_WR_OVER_CL22(bp, params->port,
1078 MDIO_REG_BANK_XGXS_BLOCK2,
1079 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1082 if (tx_lane_swap != 0x1b) {
1083 CL45_WR_OVER_CL22(bp, params->port,
1085 MDIO_REG_BANK_XGXS_BLOCK2,
1086 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1088 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1090 CL45_WR_OVER_CL22(bp, params->port,
1092 MDIO_REG_BANK_XGXS_BLOCK2,
1093 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1097 static void bnx2x_set_parallel_detection(struct link_params *params,
1100 struct bnx2x *bp = params->bp;
1103 CL45_RD_OVER_CL22(bp, params->port,
1105 MDIO_REG_BANK_SERDES_DIGITAL,
1106 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1110 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1113 CL45_WR_OVER_CL22(bp, params->port,
1115 MDIO_REG_BANK_SERDES_DIGITAL,
1116 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1119 if (phy_flags & PHY_XGXS_FLAG) {
1120 DP(NETIF_MSG_LINK, "XGXS\n");
1122 CL45_WR_OVER_CL22(bp, params->port,
1124 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1125 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1126 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1128 CL45_RD_OVER_CL22(bp, params->port,
1130 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1131 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1136 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1138 CL45_WR_OVER_CL22(bp, params->port,
1140 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1141 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1144 /* Disable parallel detection of HiG */
1145 CL45_WR_OVER_CL22(bp, params->port,
1147 MDIO_REG_BANK_XGXS_BLOCK2,
1148 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1149 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1150 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1154 static void bnx2x_set_autoneg(struct link_params *params,
1155 struct link_vars *vars,
1158 struct bnx2x *bp = params->bp;
1163 CL45_RD_OVER_CL22(bp, params->port,
1165 MDIO_REG_BANK_COMBO_IEEE0,
1166 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1168 /* CL37 Autoneg Enabled */
1169 if (vars->line_speed == SPEED_AUTO_NEG)
1170 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1171 else /* CL37 Autoneg Disabled */
1172 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1173 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1175 CL45_WR_OVER_CL22(bp, params->port,
1177 MDIO_REG_BANK_COMBO_IEEE0,
1178 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1180 /* Enable/Disable Autodetection */
1182 CL45_RD_OVER_CL22(bp, params->port,
1184 MDIO_REG_BANK_SERDES_DIGITAL,
1185 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
1186 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1187 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1188 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1189 if (vars->line_speed == SPEED_AUTO_NEG)
1190 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1192 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1194 CL45_WR_OVER_CL22(bp, params->port,
1196 MDIO_REG_BANK_SERDES_DIGITAL,
1197 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1199 /* Enable TetonII and BAM autoneg */
1200 CL45_RD_OVER_CL22(bp, params->port,
1202 MDIO_REG_BANK_BAM_NEXT_PAGE,
1203 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1205 if (vars->line_speed == SPEED_AUTO_NEG) {
1206 /* Enable BAM aneg Mode and TetonII aneg Mode */
1207 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1208 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1210 /* TetonII and BAM Autoneg Disabled */
1211 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1212 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1214 CL45_WR_OVER_CL22(bp, params->port,
1216 MDIO_REG_BANK_BAM_NEXT_PAGE,
1217 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1221 /* Enable Cl73 FSM status bits */
1222 CL45_WR_OVER_CL22(bp, params->port,
1224 MDIO_REG_BANK_CL73_USERB0,
1225 MDIO_CL73_USERB0_CL73_UCTRL,
1226 MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL);
1228 /* Enable BAM Station Manager*/
1229 CL45_WR_OVER_CL22(bp, params->port,
1231 MDIO_REG_BANK_CL73_USERB0,
1232 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1233 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1234 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1235 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
1237 /* Merge CL73 and CL37 aneg resolution */
1238 CL45_RD_OVER_CL22(bp, params->port,
1240 MDIO_REG_BANK_CL73_USERB0,
1241 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1244 if (params->speed_cap_mask &
1245 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
1246 /* Set the CL73 AN speed */
1247 CL45_RD_OVER_CL22(bp, params->port,
1249 MDIO_REG_BANK_CL73_IEEEB1,
1250 MDIO_CL73_IEEEB1_AN_ADV2,
1253 CL45_WR_OVER_CL22(bp, params->port,
1255 MDIO_REG_BANK_CL73_IEEEB1,
1256 MDIO_CL73_IEEEB1_AN_ADV2,
1257 reg_val | MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4);
1260 /* CL73 Autoneg Enabled */
1261 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1263 } else /* CL73 Autoneg Disabled */
1266 CL45_WR_OVER_CL22(bp, params->port,
1268 MDIO_REG_BANK_CL73_IEEEB0,
1269 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1272 /* program SerDes, forced speed */
1273 static void bnx2x_program_serdes(struct link_params *params,
1274 struct link_vars *vars)
1276 struct bnx2x *bp = params->bp;
1279 /* program duplex, disable autoneg */
1281 CL45_RD_OVER_CL22(bp, params->port,
1283 MDIO_REG_BANK_COMBO_IEEE0,
1284 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1285 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1286 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
1287 if (params->req_duplex == DUPLEX_FULL)
1288 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1289 CL45_WR_OVER_CL22(bp, params->port,
1291 MDIO_REG_BANK_COMBO_IEEE0,
1292 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1295 - needed only if the speed is greater than 1G (2.5G or 10G) */
1296 CL45_RD_OVER_CL22(bp, params->port,
1298 MDIO_REG_BANK_SERDES_DIGITAL,
1299 MDIO_SERDES_DIGITAL_MISC1, ®_val);
1300 /* clearing the speed value before setting the right speed */
1301 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1303 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1304 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1306 if (!((vars->line_speed == SPEED_1000) ||
1307 (vars->line_speed == SPEED_100) ||
1308 (vars->line_speed == SPEED_10))) {
1310 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1311 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1312 if (vars->line_speed == SPEED_10000)
1314 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1315 if (vars->line_speed == SPEED_13000)
1317 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1320 CL45_WR_OVER_CL22(bp, params->port,
1322 MDIO_REG_BANK_SERDES_DIGITAL,
1323 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1327 static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1329 struct bnx2x *bp = params->bp;
1332 /* configure the 48 bits for BAM AN */
1334 /* set extended capabilities */
1335 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1336 val |= MDIO_OVER_1G_UP1_2_5G;
1337 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1338 val |= MDIO_OVER_1G_UP1_10G;
1339 CL45_WR_OVER_CL22(bp, params->port,
1341 MDIO_REG_BANK_OVER_1G,
1342 MDIO_OVER_1G_UP1, val);
1344 CL45_WR_OVER_CL22(bp, params->port,
1346 MDIO_REG_BANK_OVER_1G,
1347 MDIO_OVER_1G_UP3, 0x400);
1350 static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
1352 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1353 /* resolve pause mode and advertisement
1354 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1356 switch (params->req_flow_ctrl) {
1357 case BNX2X_FLOW_CTRL_AUTO:
1358 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
1360 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1363 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1366 case BNX2X_FLOW_CTRL_TX:
1368 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1371 case BNX2X_FLOW_CTRL_RX:
1372 case BNX2X_FLOW_CTRL_BOTH:
1373 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1376 case BNX2X_FLOW_CTRL_NONE:
1378 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1383 static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1386 struct bnx2x *bp = params->bp;
1387 /* for AN, we are always publishing full duplex */
1389 CL45_WR_OVER_CL22(bp, params->port,
1391 MDIO_REG_BANK_COMBO_IEEE0,
1392 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
1395 static void bnx2x_restart_autoneg(struct link_params *params, u8 enable_cl73)
1397 struct bnx2x *bp = params->bp;
1400 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1401 /* Enable and restart BAM/CL37 aneg */
1404 CL45_RD_OVER_CL22(bp, params->port,
1406 MDIO_REG_BANK_CL73_IEEEB0,
1407 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1410 CL45_WR_OVER_CL22(bp, params->port,
1412 MDIO_REG_BANK_CL73_IEEEB0,
1413 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1415 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1416 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1419 CL45_RD_OVER_CL22(bp, params->port,
1421 MDIO_REG_BANK_COMBO_IEEE0,
1422 MDIO_COMBO_IEEE0_MII_CONTROL,
1425 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1427 CL45_WR_OVER_CL22(bp, params->port,
1429 MDIO_REG_BANK_COMBO_IEEE0,
1430 MDIO_COMBO_IEEE0_MII_CONTROL,
1432 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1433 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1437 static void bnx2x_initialize_sgmii_process(struct link_params *params,
1438 struct link_vars *vars)
1440 struct bnx2x *bp = params->bp;
1443 /* in SGMII mode, the unicore is always slave */
1445 CL45_RD_OVER_CL22(bp, params->port,
1447 MDIO_REG_BANK_SERDES_DIGITAL,
1448 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1450 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1451 /* set sgmii mode (and not fiber) */
1452 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1453 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1454 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1455 CL45_WR_OVER_CL22(bp, params->port,
1457 MDIO_REG_BANK_SERDES_DIGITAL,
1458 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1461 /* if forced speed */
1462 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1463 /* set speed, disable autoneg */
1466 CL45_RD_OVER_CL22(bp, params->port,
1468 MDIO_REG_BANK_COMBO_IEEE0,
1469 MDIO_COMBO_IEEE0_MII_CONTROL,
1471 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1472 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1473 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1475 switch (vars->line_speed) {
1478 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1482 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1485 /* there is nothing to set for 10M */
1488 /* invalid speed for SGMII */
1489 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1494 /* setting the full duplex */
1495 if (params->req_duplex == DUPLEX_FULL)
1497 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1498 CL45_WR_OVER_CL22(bp, params->port,
1500 MDIO_REG_BANK_COMBO_IEEE0,
1501 MDIO_COMBO_IEEE0_MII_CONTROL,
1504 } else { /* AN mode */
1505 /* enable and restart AN */
1506 bnx2x_restart_autoneg(params, 0);
1515 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1517 switch (pause_result) { /* ASYM P ASYM P */
1518 case 0xb: /* 1 0 1 1 */
1519 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
1522 case 0xe: /* 1 1 1 0 */
1523 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
1526 case 0x5: /* 0 1 0 1 */
1527 case 0x7: /* 0 1 1 1 */
1528 case 0xd: /* 1 1 0 1 */
1529 case 0xf: /* 1 1 1 1 */
1530 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
1538 static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1539 struct link_vars *vars)
1541 struct bnx2x *bp = params->bp;
1543 u16 ld_pause; /* local */
1544 u16 lp_pause; /* link partner */
1545 u16 an_complete; /* AN complete */
1549 u8 port = params->port;
1550 ext_phy_addr = ((params->ext_phy_config &
1551 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1552 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1554 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1557 bnx2x_cl45_read(bp, port,
1561 MDIO_AN_REG_STATUS, &an_complete);
1562 bnx2x_cl45_read(bp, port,
1566 MDIO_AN_REG_STATUS, &an_complete);
1568 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1570 bnx2x_cl45_read(bp, port,
1574 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1575 bnx2x_cl45_read(bp, port,
1579 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1580 pause_result = (ld_pause &
1581 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1582 pause_result |= (lp_pause &
1583 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1584 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1586 bnx2x_pause_resolve(vars, pause_result);
1587 if (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE &&
1588 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1589 bnx2x_cl45_read(bp, port,
1593 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1595 bnx2x_cl45_read(bp, port,
1599 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1600 pause_result = (ld_pause &
1601 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1602 pause_result |= (lp_pause &
1603 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1605 bnx2x_pause_resolve(vars, pause_result);
1606 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1614 static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1615 struct link_vars *vars,
1618 struct bnx2x *bp = params->bp;
1619 u16 ld_pause; /* local driver */
1620 u16 lp_pause; /* link partner */
1623 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1625 /* resolve from gp_status in case of AN complete and not sgmii */
1626 if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1627 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1628 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1629 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1630 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1631 CL45_RD_OVER_CL22(bp, params->port,
1633 MDIO_REG_BANK_COMBO_IEEE0,
1634 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1636 CL45_RD_OVER_CL22(bp, params->port,
1638 MDIO_REG_BANK_COMBO_IEEE0,
1639 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1641 pause_result = (ld_pause &
1642 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1643 pause_result |= (lp_pause &
1644 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1645 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1646 bnx2x_pause_resolve(vars, pause_result);
1647 } else if ((params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO) &&
1648 (bnx2x_ext_phy_resove_fc(params, vars))) {
1651 if (params->req_flow_ctrl == BNX2X_FLOW_CTRL_AUTO)
1652 vars->flow_ctrl = params->req_fc_auto_adv;
1654 vars->flow_ctrl = params->req_flow_ctrl;
1656 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1659 static void bnx2x_check_fallback_to_cl37(struct link_params *params)
1661 struct bnx2x *bp = params->bp;
1662 u16 rx_status, ustat_val, cl37_fsm_recieved;
1663 DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
1664 /* Step 1: Make sure signal is detected */
1665 CL45_RD_OVER_CL22(bp, params->port,
1670 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
1671 (MDIO_RX0_RX_STATUS_SIGDET)) {
1672 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
1673 "rx_status(0x80b0) = 0x%x\n", rx_status);
1674 CL45_WR_OVER_CL22(bp, params->port,
1676 MDIO_REG_BANK_CL73_IEEEB0,
1677 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1678 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
1681 /* Step 2: Check CL73 state machine */
1682 CL45_RD_OVER_CL22(bp, params->port,
1684 MDIO_REG_BANK_CL73_USERB0,
1685 MDIO_CL73_USERB0_CL73_USTAT1,
1688 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1689 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
1690 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
1691 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
1692 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
1693 "ustat_val(0x8371) = 0x%x\n", ustat_val);
1696 /* Step 3: Check CL37 Message Pages received to indicate LP
1697 supports only CL37 */
1698 CL45_RD_OVER_CL22(bp, params->port,
1700 MDIO_REG_BANK_REMOTE_PHY,
1701 MDIO_REMOTE_PHY_MISC_RX_STATUS,
1702 &cl37_fsm_recieved);
1703 if ((cl37_fsm_recieved &
1704 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1705 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
1706 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
1707 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
1708 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
1709 "misc_rx_status(0x8330) = 0x%x\n",
1713 /* The combined cl37/cl73 fsm state information indicating that we are
1714 connected to a device which does not support cl73, but does support
1715 cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
1717 CL45_WR_OVER_CL22(bp, params->port,
1719 MDIO_REG_BANK_CL73_IEEEB0,
1720 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1722 /* Restart CL37 autoneg */
1723 bnx2x_restart_autoneg(params, 0);
1724 DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
1726 static u8 bnx2x_link_settings_status(struct link_params *params,
1727 struct link_vars *vars,
1731 struct bnx2x *bp = params->bp;
1734 vars->link_status = 0;
1736 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1737 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1740 vars->phy_link_up = 1;
1741 vars->link_status |= LINK_STATUS_LINK_UP;
1743 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1744 vars->duplex = DUPLEX_FULL;
1746 vars->duplex = DUPLEX_HALF;
1748 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1750 switch (gp_status & GP_STATUS_SPEED_MASK) {
1752 new_line_speed = SPEED_10;
1753 if (vars->duplex == DUPLEX_FULL)
1754 vars->link_status |= LINK_10TFD;
1756 vars->link_status |= LINK_10THD;
1759 case GP_STATUS_100M:
1760 new_line_speed = SPEED_100;
1761 if (vars->duplex == DUPLEX_FULL)
1762 vars->link_status |= LINK_100TXFD;
1764 vars->link_status |= LINK_100TXHD;
1768 case GP_STATUS_1G_KX:
1769 new_line_speed = SPEED_1000;
1770 if (vars->duplex == DUPLEX_FULL)
1771 vars->link_status |= LINK_1000TFD;
1773 vars->link_status |= LINK_1000THD;
1776 case GP_STATUS_2_5G:
1777 new_line_speed = SPEED_2500;
1778 if (vars->duplex == DUPLEX_FULL)
1779 vars->link_status |= LINK_2500TFD;
1781 vars->link_status |= LINK_2500THD;
1787 "link speed unsupported gp_status 0x%x\n",
1791 case GP_STATUS_10G_KX4:
1792 case GP_STATUS_10G_HIG:
1793 case GP_STATUS_10G_CX4:
1794 new_line_speed = SPEED_10000;
1795 vars->link_status |= LINK_10GTFD;
1798 case GP_STATUS_12G_HIG:
1799 new_line_speed = SPEED_12000;
1800 vars->link_status |= LINK_12GTFD;
1803 case GP_STATUS_12_5G:
1804 new_line_speed = SPEED_12500;
1805 vars->link_status |= LINK_12_5GTFD;
1809 new_line_speed = SPEED_13000;
1810 vars->link_status |= LINK_13GTFD;
1814 new_line_speed = SPEED_15000;
1815 vars->link_status |= LINK_15GTFD;
1819 new_line_speed = SPEED_16000;
1820 vars->link_status |= LINK_16GTFD;
1825 "link speed unsupported gp_status 0x%x\n",
1831 /* Upon link speed change set the NIG into drain mode.
1832 Comes to deals with possible FIFO glitch due to clk change
1833 when speed is decreased without link down indicator */
1834 if (new_line_speed != vars->line_speed) {
1835 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config) !=
1836 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT &&
1838 DP(NETIF_MSG_LINK, "Internal link speed %d is"
1839 " different than the external"
1840 " link speed %d\n", new_line_speed,
1842 vars->phy_link_up = 0;
1845 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
1846 + params->port*4, 0);
1849 vars->line_speed = new_line_speed;
1850 vars->link_status |= LINK_STATUS_SERDES_LINK;
1852 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1853 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1854 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1855 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1856 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
1857 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1858 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726))) {
1859 vars->autoneg = AUTO_NEG_ENABLED;
1861 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1862 vars->autoneg |= AUTO_NEG_COMPLETE;
1863 vars->link_status |=
1864 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1867 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1868 vars->link_status |=
1869 LINK_STATUS_PARALLEL_DETECTION_USED;
1872 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1873 vars->link_status |=
1874 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1876 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1877 vars->link_status |=
1878 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1880 } else { /* link_down */
1881 DP(NETIF_MSG_LINK, "phy link down\n");
1883 vars->phy_link_up = 0;
1885 vars->duplex = DUPLEX_FULL;
1886 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1887 vars->autoneg = AUTO_NEG_DISABLED;
1888 vars->mac_type = MAC_TYPE_NONE;
1890 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1891 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1892 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT))) {
1893 /* Check signal is detected */
1894 bnx2x_check_fallback_to_cl37(params);
1898 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1899 gp_status, vars->phy_link_up, vars->line_speed);
1900 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1903 vars->flow_ctrl, vars->autoneg);
1904 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1909 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
1911 struct bnx2x *bp = params->bp;
1917 CL45_RD_OVER_CL22(bp, params->port,
1919 MDIO_REG_BANK_OVER_1G,
1920 MDIO_OVER_1G_LP_UP2, &lp_up2);
1922 /* bits [10:7] at lp_up2, positioned at [15:12] */
1923 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1924 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1925 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1930 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
1931 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
1932 CL45_RD_OVER_CL22(bp, params->port,
1935 MDIO_TX0_TX_DRIVER, &tx_driver);
1937 /* replace tx_driver bits [15:12] */
1939 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
1940 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1941 tx_driver |= lp_up2;
1942 CL45_WR_OVER_CL22(bp, params->port,
1945 MDIO_TX0_TX_DRIVER, tx_driver);
1950 static u8 bnx2x_emac_program(struct link_params *params,
1951 u32 line_speed, u32 duplex)
1953 struct bnx2x *bp = params->bp;
1954 u8 port = params->port;
1957 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1958 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1960 (EMAC_MODE_25G_MODE |
1961 EMAC_MODE_PORT_MII_10M |
1962 EMAC_MODE_HALF_DUPLEX));
1963 switch (line_speed) {
1965 mode |= EMAC_MODE_PORT_MII_10M;
1969 mode |= EMAC_MODE_PORT_MII;
1973 mode |= EMAC_MODE_PORT_GMII;
1977 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1981 /* 10G not valid for EMAC */
1982 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
1986 if (duplex == DUPLEX_HALF)
1987 mode |= EMAC_MODE_HALF_DUPLEX;
1989 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1992 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
1993 line_speed, params->hw_led_mode, params->chip_id);
1997 /*****************************************************************************/
1998 /* External Phy section */
1999 /*****************************************************************************/
2000 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
2002 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2003 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
2005 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2006 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
2009 static void bnx2x_ext_phy_reset(struct link_params *params,
2010 struct link_vars *vars)
2012 struct bnx2x *bp = params->bp;
2014 u8 ext_phy_addr = ((params->ext_phy_config &
2015 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2016 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2017 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
2018 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2019 /* The PHY reset is controled by GPIO 1
2020 * Give it 1ms of reset pulse
2022 if (vars->phy_flags & PHY_XGXS_FLAG) {
2024 switch (ext_phy_type) {
2025 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2026 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2029 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2030 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2031 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
2033 /* Restore normal power mode*/
2034 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2035 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2039 bnx2x_ext_phy_hw_reset(bp, params->port);
2041 bnx2x_cl45_write(bp, params->port,
2045 MDIO_PMA_REG_CTRL, 0xa040);
2048 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2051 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2053 /* Restore normal power mode*/
2054 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2055 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2058 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2059 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2062 bnx2x_cl45_write(bp, params->port,
2070 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2071 /* Unset Low Power Mode and SW reset */
2072 /* Restore normal power mode*/
2073 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2074 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2077 DP(NETIF_MSG_LINK, "XGXS 8072\n");
2078 bnx2x_cl45_write(bp, params->port,
2085 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2088 /* Restore normal power mode*/
2089 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2090 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2093 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
2094 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2097 DP(NETIF_MSG_LINK, "XGXS 8073\n");
2101 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2102 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
2104 /* Restore normal power mode*/
2105 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2106 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2110 bnx2x_ext_phy_hw_reset(bp, params->port);
2113 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2115 /* Restore normal power mode*/
2116 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
2117 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
2121 bnx2x_ext_phy_hw_reset(bp, params->port);
2123 bnx2x_cl45_write(bp, params->port,
2130 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2131 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
2135 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2136 params->ext_phy_config);
2140 } else { /* SerDes */
2141 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2142 switch (ext_phy_type) {
2143 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2144 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2147 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2148 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2149 bnx2x_ext_phy_hw_reset(bp, params->port);
2154 "BAD SerDes ext_phy_config 0x%x\n",
2155 params->ext_phy_config);
2162 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
2163 u32 shmem_base, u32 spirom_ver)
2165 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x\n",
2166 (u16)(spirom_ver>>16), (u16)spirom_ver);
2167 REG_WR(bp, shmem_base +
2168 offsetof(struct shmem_region,
2169 port_mb[port].ext_phy_fw_version),
2173 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, u8 port,
2174 u32 ext_phy_type, u8 ext_phy_addr,
2177 u16 fw_ver1, fw_ver2;
2178 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2179 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2180 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr, MDIO_PMA_DEVAD,
2181 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2182 bnx2x_save_spirom_version(bp, port, shmem_base,
2183 (u32)(fw_ver1<<16 | fw_ver2));
2187 static void bnx2x_save_8481_spirom_version(struct bnx2x *bp, u8 port,
2188 u8 ext_phy_addr, u32 shmem_base)
2190 u16 val, fw_ver1, fw_ver2, cnt;
2191 /* For the 32 bits registers in 8481, access via MDIO2ARM interface.*/
2192 /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
2193 bnx2x_cl45_write(bp, port,
2194 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2195 ext_phy_addr, MDIO_PMA_DEVAD,
2197 bnx2x_cl45_write(bp, port,
2198 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2203 bnx2x_cl45_write(bp, port,
2204 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2209 bnx2x_cl45_write(bp, port,
2210 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2215 bnx2x_cl45_write(bp, port,
2216 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2222 for (cnt = 0; cnt < 100; cnt++) {
2223 bnx2x_cl45_read(bp, port,
2224 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2234 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(1)\n");
2235 bnx2x_save_spirom_version(bp, port,
2241 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
2242 bnx2x_cl45_write(bp, port,
2243 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2244 ext_phy_addr, MDIO_PMA_DEVAD,
2246 bnx2x_cl45_write(bp, port,
2247 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2248 ext_phy_addr, MDIO_PMA_DEVAD,
2250 bnx2x_cl45_write(bp, port,
2251 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2252 ext_phy_addr, MDIO_PMA_DEVAD,
2254 for (cnt = 0; cnt < 100; cnt++) {
2255 bnx2x_cl45_read(bp, port,
2256 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2266 DP(NETIF_MSG_LINK, "Unable to read 8481 phy fw version(2)\n");
2267 bnx2x_save_spirom_version(bp, port,
2272 /* lower 16 bits of the register SPI_FW_STATUS */
2273 bnx2x_cl45_read(bp, port,
2274 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2279 /* upper 16 bits of register SPI_FW_STATUS */
2280 bnx2x_cl45_read(bp, port,
2281 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
2287 bnx2x_save_spirom_version(bp, port,
2288 shmem_base, (fw_ver2<<16) | fw_ver1);
2291 static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
2293 struct bnx2x *bp = params->bp;
2294 u8 port = params->port;
2295 u8 ext_phy_addr = ((params->ext_phy_config &
2296 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2297 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2298 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2300 /* Need to wait 200ms after reset */
2302 /* Boot port from external ROM
2303 * Set ser_boot_ctl bit in the MISC_CTRL1 register
2305 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2307 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2309 /* Reset internal microprocessor */
2310 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2312 MDIO_PMA_REG_GEN_CTRL,
2313 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2314 /* set micro reset = 0 */
2315 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2317 MDIO_PMA_REG_GEN_CTRL,
2318 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2319 /* Reset internal microprocessor */
2320 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2322 MDIO_PMA_REG_GEN_CTRL,
2323 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2324 /* wait for 100ms for code download via SPI port */
2327 /* Clear ser_boot_ctl bit */
2328 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2330 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2334 bnx2x_save_bcm_spirom_ver(bp, port,
2337 params->shmem_base);
2340 static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2342 /* This is only required for 8073A1, version 102 only */
2344 struct bnx2x *bp = params->bp;
2345 u8 ext_phy_addr = ((params->ext_phy_config &
2346 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2347 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2350 /* Read 8073 HW revision*/
2351 bnx2x_cl45_read(bp, params->port,
2352 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2355 MDIO_PMA_REG_8073_CHIP_REV, &val);
2358 /* No need to workaround in 8073 A1 */
2362 bnx2x_cl45_read(bp, params->port,
2363 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2366 MDIO_PMA_REG_ROM_VER2, &val);
2368 /* SNR should be applied only for version 0x102 */
2375 static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2377 struct bnx2x *bp = params->bp;
2378 u8 ext_phy_addr = ((params->ext_phy_config &
2379 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2380 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2381 u16 val, cnt, cnt1 ;
2383 bnx2x_cl45_read(bp, params->port,
2384 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2387 MDIO_PMA_REG_8073_CHIP_REV, &val);
2390 /* No need to workaround in 8073 A1 */
2393 /* XAUI workaround in 8073 A0: */
2395 /* After loading the boot ROM and restarting Autoneg,
2396 poll Dev1, Reg $C820: */
2398 for (cnt = 0; cnt < 1000; cnt++) {
2399 bnx2x_cl45_read(bp, params->port,
2400 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2403 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
2405 /* If bit [14] = 0 or bit [13] = 0, continue on with
2406 system initialization (XAUI work-around not required,
2407 as these bits indicate 2.5G or 1G link up). */
2408 if (!(val & (1<<14)) || !(val & (1<<13))) {
2409 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2411 } else if (!(val & (1<<15))) {
2412 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2413 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2414 it's MSB (bit 15) goes to 1 (indicating that the
2415 XAUI workaround has completed),
2416 then continue on with system initialization.*/
2417 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2418 bnx2x_cl45_read(bp, params->port,
2419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2422 MDIO_PMA_REG_8073_XAUI_WA, &val);
2423 if (val & (1<<15)) {
2425 "XAUI workaround has completed\n");
2434 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2439 static void bnx2x_bcm8073_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2444 /* Boot port from external ROM */
2446 bnx2x_cl45_write(bp, port,
2450 MDIO_PMA_REG_GEN_CTRL,
2453 /* ucode reboot and rst */
2454 bnx2x_cl45_write(bp, port,
2458 MDIO_PMA_REG_GEN_CTRL,
2461 bnx2x_cl45_write(bp, port,
2465 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2467 /* Reset internal microprocessor */
2468 bnx2x_cl45_write(bp, port,
2472 MDIO_PMA_REG_GEN_CTRL,
2473 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2475 /* Release srst bit */
2476 bnx2x_cl45_write(bp, port,
2480 MDIO_PMA_REG_GEN_CTRL,
2481 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2483 /* wait for 100ms for code download via SPI port */
2486 /* Clear ser_boot_ctl bit */
2487 bnx2x_cl45_write(bp, port,
2491 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2493 bnx2x_save_bcm_spirom_ver(bp, port,
2499 static void bnx2x_bcm8073_external_rom_boot(struct bnx2x *bp, u8 port,
2503 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2504 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2508 static void bnx2x_bcm8727_external_rom_boot(struct bnx2x *bp, u8 port,
2512 bnx2x_bcm8073_bcm8727_external_rom_boot(bp, port, ext_phy_addr,
2513 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2518 static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
2520 struct bnx2x *bp = params->bp;
2521 u8 port = params->port;
2522 u8 ext_phy_addr = ((params->ext_phy_config &
2523 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2524 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2525 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2527 /* Need to wait 100ms after reset */
2530 /* Set serial boot control for external load */
2531 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2533 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2535 /* Micro controller re-boot */
2536 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2538 MDIO_PMA_REG_GEN_CTRL,
2539 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2541 /* Set soft reset */
2542 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2544 MDIO_PMA_REG_GEN_CTRL,
2545 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2547 /* Set PLL register value to be same like in P13 ver */
2548 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2550 MDIO_PMA_REG_PLL_CTRL,
2553 /* Clear soft reset.
2554 Will automatically reset micro-controller re-boot */
2555 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2557 MDIO_PMA_REG_GEN_CTRL,
2558 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2560 /* wait for 150ms for microcode load */
2563 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
2564 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2566 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2569 bnx2x_save_bcm_spirom_ver(bp, port,
2572 params->shmem_base);
2575 static void bnx2x_sfp_set_transmitter(struct bnx2x *bp, u8 port,
2576 u32 ext_phy_type, u8 ext_phy_addr,
2580 DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
2582 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
2583 bnx2x_cl45_read(bp, port,
2587 MDIO_PMA_REG_PHY_IDENTIFIER,
2595 bnx2x_cl45_write(bp, port,
2599 MDIO_PMA_REG_PHY_IDENTIFIER,
2603 static u8 bnx2x_8726_read_sfp_module_eeprom(struct link_params *params,
2604 u16 addr, u8 byte_cnt, u8 *o_buf)
2606 struct bnx2x *bp = params->bp;
2609 u8 port = params->port;
2610 u8 ext_phy_addr = ((params->ext_phy_config &
2611 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2612 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2613 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2614 if (byte_cnt > 16) {
2615 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2616 " is limited to 0xf\n");
2619 /* Set the read command byte count */
2620 bnx2x_cl45_write(bp, port,
2624 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2625 (byte_cnt | 0xa000));
2627 /* Set the read command address */
2628 bnx2x_cl45_write(bp, port,
2632 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2635 /* Activate read command */
2636 bnx2x_cl45_write(bp, port,
2640 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2643 /* Wait up to 500us for command complete status */
2644 for (i = 0; i < 100; i++) {
2645 bnx2x_cl45_read(bp, port,
2649 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2650 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2651 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2656 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2657 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2659 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2660 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2664 /* Read the buffer */
2665 for (i = 0; i < byte_cnt; i++) {
2666 bnx2x_cl45_read(bp, port,
2670 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
2671 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
2674 for (i = 0; i < 100; i++) {
2675 bnx2x_cl45_read(bp, port,
2679 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2680 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2681 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2688 static u8 bnx2x_8727_read_sfp_module_eeprom(struct link_params *params,
2689 u16 addr, u8 byte_cnt, u8 *o_buf)
2691 struct bnx2x *bp = params->bp;
2693 u8 port = params->port;
2694 u8 ext_phy_addr = ((params->ext_phy_config &
2695 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2696 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2697 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2699 if (byte_cnt > 16) {
2700 DP(NETIF_MSG_LINK, "Reading from eeprom is"
2701 " is limited to 0xf\n");
2705 /* Need to read from 1.8000 to clear it */
2706 bnx2x_cl45_read(bp, port,
2707 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
2710 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2713 /* Set the read command byte count */
2714 bnx2x_cl45_write(bp, port,
2718 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
2719 ((byte_cnt < 2) ? 2 : byte_cnt));
2721 /* Set the read command address */
2722 bnx2x_cl45_write(bp, port,
2726 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
2728 /* Set the destination address */
2729 bnx2x_cl45_write(bp, port,
2734 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
2736 /* Activate read command */
2737 bnx2x_cl45_write(bp, port,
2741 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
2743 /* Wait appropriate time for two-wire command to finish before
2744 polling the status register */
2747 /* Wait up to 500us for command complete status */
2748 for (i = 0; i < 100; i++) {
2749 bnx2x_cl45_read(bp, port,
2753 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2754 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2755 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
2760 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
2761 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
2763 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
2764 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
2768 /* Read the buffer */
2769 for (i = 0; i < byte_cnt; i++) {
2770 bnx2x_cl45_read(bp, port,
2774 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
2775 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
2778 for (i = 0; i < 100; i++) {
2779 bnx2x_cl45_read(bp, port,
2783 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
2784 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
2785 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
2793 u8 bnx2x_read_sfp_module_eeprom(struct link_params *params, u16 addr,
2794 u8 byte_cnt, u8 *o_buf)
2796 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2798 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
2799 return bnx2x_8726_read_sfp_module_eeprom(params, addr,
2801 else if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
2802 return bnx2x_8727_read_sfp_module_eeprom(params, addr,
2807 static u8 bnx2x_get_edc_mode(struct link_params *params,
2810 struct bnx2x *bp = params->bp;
2811 u8 val, check_limiting_mode = 0;
2812 *edc_mode = EDC_MODE_LIMITING;
2814 /* First check for copper cable */
2815 if (bnx2x_read_sfp_module_eeprom(params,
2816 SFP_EEPROM_CON_TYPE_ADDR,
2819 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
2824 case SFP_EEPROM_CON_TYPE_VAL_COPPER:
2826 u8 copper_module_type;
2827 /* Check if its active cable( includes SFP+ module)
2829 if (bnx2x_read_sfp_module_eeprom(params,
2830 SFP_EEPROM_FC_TX_TECH_ADDR,
2832 &copper_module_type) !=
2835 "Failed to read copper-cable-type"
2836 " from SFP+ EEPROM\n");
2840 if (copper_module_type &
2841 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
2842 DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
2843 check_limiting_mode = 1;
2844 } else if (copper_module_type &
2845 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
2846 DP(NETIF_MSG_LINK, "Passive Copper"
2847 " cable detected\n");
2849 EDC_MODE_PASSIVE_DAC;
2851 DP(NETIF_MSG_LINK, "Unknown copper-cable-"
2852 "type 0x%x !!!\n", copper_module_type);
2857 case SFP_EEPROM_CON_TYPE_VAL_LC:
2858 DP(NETIF_MSG_LINK, "Optic module detected\n");
2859 check_limiting_mode = 1;
2863 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
2868 if (check_limiting_mode) {
2869 u8 options[SFP_EEPROM_OPTIONS_SIZE];
2870 if (bnx2x_read_sfp_module_eeprom(params,
2871 SFP_EEPROM_OPTIONS_ADDR,
2872 SFP_EEPROM_OPTIONS_SIZE,
2874 DP(NETIF_MSG_LINK, "Failed to read Option"
2875 " field from module EEPROM\n");
2878 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
2879 *edc_mode = EDC_MODE_LINEAR;
2881 *edc_mode = EDC_MODE_LIMITING;
2883 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
2887 /* This function read the relevant field from the module ( SFP+ ),
2888 and verify it is compliant with this board */
2889 static u8 bnx2x_verify_sfp_module(struct link_params *params)
2891 struct bnx2x *bp = params->bp;
2894 char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
2895 char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
2897 val = REG_RD(bp, params->shmem_base +
2898 offsetof(struct shmem_region, dev_info.
2899 port_feature_config[params->port].config));
2900 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
2901 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
2902 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
2906 /* Ask the FW to validate the module */
2907 if (!(params->feature_config_flags &
2908 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY)) {
2909 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
2914 fw_resp = bnx2x_fw_command(bp, DRV_MSG_CODE_VRFY_OPT_MDL);
2915 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
2916 DP(NETIF_MSG_LINK, "Approved module\n");
2920 /* format the warning message */
2921 if (bnx2x_read_sfp_module_eeprom(params,
2922 SFP_EEPROM_VENDOR_NAME_ADDR,
2923 SFP_EEPROM_VENDOR_NAME_SIZE,
2925 vendor_name[0] = '\0';
2927 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
2928 if (bnx2x_read_sfp_module_eeprom(params,
2929 SFP_EEPROM_PART_NO_ADDR,
2930 SFP_EEPROM_PART_NO_SIZE,
2932 vendor_pn[0] = '\0';
2934 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
2936 printk(KERN_INFO PFX "Warning: "
2937 "Unqualified SFP+ module "
2938 "detected on %s, Port %d from %s part number %s\n"
2939 , bp->dev->name, params->port,
2940 vendor_name, vendor_pn);
2944 static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
2947 struct bnx2x *bp = params->bp;
2948 u8 port = params->port;
2949 u8 ext_phy_addr = ((params->ext_phy_config &
2950 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2951 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2952 u16 cur_limiting_mode;
2954 bnx2x_cl45_read(bp, port,
2955 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2958 MDIO_PMA_REG_ROM_VER2,
2959 &cur_limiting_mode);
2960 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
2963 if (edc_mode == EDC_MODE_LIMITING) {
2965 "Setting LIMITING MODE\n");
2966 bnx2x_cl45_write(bp, port,
2967 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2970 MDIO_PMA_REG_ROM_VER2,
2972 } else { /* LRM mode ( default )*/
2974 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
2976 /* Changing to LRM mode takes quite few seconds.
2977 So do it only if current mode is limiting
2978 ( default is LRM )*/
2979 if (cur_limiting_mode != EDC_MODE_LIMITING)
2982 bnx2x_cl45_write(bp, port,
2983 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2986 MDIO_PMA_REG_LRM_MODE,
2988 bnx2x_cl45_write(bp, port,
2989 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2992 MDIO_PMA_REG_ROM_VER2,
2994 bnx2x_cl45_write(bp, port,
2995 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
2998 MDIO_PMA_REG_MISC_CTRL0,
3000 bnx2x_cl45_write(bp, port,
3001 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
3004 MDIO_PMA_REG_LRM_MODE,
3010 static u8 bnx2x_bcm8727_set_limiting_mode(struct link_params *params,
3013 struct bnx2x *bp = params->bp;
3014 u8 port = params->port;
3017 u8 ext_phy_addr = ((params->ext_phy_config &
3018 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3019 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3021 bnx2x_cl45_read(bp, port,
3022 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3025 MDIO_PMA_REG_PHY_IDENTIFIER,
3028 bnx2x_cl45_write(bp, port,
3029 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3032 MDIO_PMA_REG_PHY_IDENTIFIER,
3033 (phy_identifier & ~(1<<9)));
3035 bnx2x_cl45_read(bp, port,
3036 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3039 MDIO_PMA_REG_ROM_VER2,
3041 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
3042 bnx2x_cl45_write(bp, port,
3043 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3046 MDIO_PMA_REG_ROM_VER2,
3047 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
3049 bnx2x_cl45_write(bp, port,
3050 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3053 MDIO_PMA_REG_PHY_IDENTIFIER,
3054 (phy_identifier | (1<<9)));
3060 static u8 bnx2x_wait_for_sfp_module_initialized(struct link_params *params)
3063 struct bnx2x *bp = params->bp;
3065 /* Initialization time after hot-plug may take up to 300ms for some
3066 phys type ( e.g. JDSU ) */
3067 for (timeout = 0; timeout < 60; timeout++) {
3068 if (bnx2x_read_sfp_module_eeprom(params, 1, 1, &val)
3070 DP(NETIF_MSG_LINK, "SFP+ module initialization "
3071 "took %d ms\n", timeout * 5);
3079 static void bnx2x_8727_power_module(struct bnx2x *bp,
3080 struct link_params *params,
3081 u8 ext_phy_addr, u8 is_power_up) {
3082 /* Make sure GPIOs are not using for LED mode */
3084 u8 port = params->port;
3086 * In the GPIO register, bit 4 is use to detemine if the GPIOs are
3087 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
3089 * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
3090 * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
3091 * where the 1st bit is the over-current(only input), and 2nd bit is
3092 * for power( only output )
3096 * In case of NOC feature is disabled and power is up, set GPIO control
3097 * as input to enable listening of over-current indication
3100 if (!(params->feature_config_flags &
3101 FEATURE_CONFIG_BCM8727_NOC) && is_power_up)
3105 * Set GPIO control to OUTPUT, and set the power bit
3106 * to according to the is_power_up
3108 val = ((!(is_power_up)) << 1);
3110 bnx2x_cl45_write(bp, port,
3111 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
3114 MDIO_PMA_REG_8727_GPIO_CTRL,
3118 static u8 bnx2x_sfp_module_detection(struct link_params *params)
3120 struct bnx2x *bp = params->bp;
3123 u8 ext_phy_addr = ((params->ext_phy_config &
3124 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3125 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3126 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3127 u32 val = REG_RD(bp, params->shmem_base +
3128 offsetof(struct shmem_region, dev_info.
3129 port_feature_config[params->port].config));
3131 DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
3134 if (bnx2x_get_edc_mode(params, &edc_mode) != 0) {
3135 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
3137 } else if (bnx2x_verify_sfp_module(params) !=
3139 /* check SFP+ module compatibility */
3140 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
3142 /* Turn on fault module-detected led */
3143 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3144 MISC_REGISTERS_GPIO_HIGH,
3146 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
3147 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3148 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
3149 /* Shutdown SFP+ module */
3150 DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
3151 bnx2x_8727_power_module(bp, params,
3156 /* Turn off fault module-detected led */
3157 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
3158 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3159 MISC_REGISTERS_GPIO_LOW,
3163 /* power up the SFP module */
3164 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
3165 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
3167 /* Check and set limiting mode / LRM mode on 8726.
3168 On 8727 it is done automatically */
3169 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
3170 bnx2x_bcm8726_set_limiting_mode(params, edc_mode);
3172 bnx2x_bcm8727_set_limiting_mode(params, edc_mode);
3174 * Enable transmit for this module if the module is approved, or
3175 * if unapproved modules should also enable the Tx laser
3178 (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
3179 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3180 bnx2x_sfp_set_transmitter(bp, params->port,
3181 ext_phy_type, ext_phy_addr, 1);
3183 bnx2x_sfp_set_transmitter(bp, params->port,
3184 ext_phy_type, ext_phy_addr, 0);
3189 void bnx2x_handle_module_detect_int(struct link_params *params)
3191 struct bnx2x *bp = params->bp;
3193 u8 port = params->port;
3194 /* Set valid module led off */
3195 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
3196 MISC_REGISTERS_GPIO_HIGH,
3199 /* Get current gpio val refelecting module plugged in / out*/
3200 gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
3202 /* Call the handling function in case module is detected */
3203 if (gpio_val == 0) {
3205 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3206 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
3209 if (bnx2x_wait_for_sfp_module_initialized(params) ==
3211 bnx2x_sfp_module_detection(params);
3213 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
3215 u8 ext_phy_addr = ((params->ext_phy_config &
3216 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3217 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3219 XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3220 u32 val = REG_RD(bp, params->shmem_base +
3221 offsetof(struct shmem_region, dev_info.
3222 port_feature_config[params->port].
3225 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
3226 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
3228 /* Module was plugged out. */
3229 /* Disable transmit for this module */
3230 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
3231 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
3232 bnx2x_sfp_set_transmitter(bp, params->port,
3233 ext_phy_type, ext_phy_addr, 0);
3237 static void bnx2x_bcm807x_force_10G(struct link_params *params)
3239 struct bnx2x *bp = params->bp;
3240 u8 port = params->port;
3241 u8 ext_phy_addr = ((params->ext_phy_config &
3242 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3243 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3244 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3246 /* Force KR or KX */
3247 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3251 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3253 MDIO_PMA_REG_10G_CTRL2,
3255 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3257 MDIO_PMA_REG_BCM_CTRL,
3259 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3264 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
3266 struct bnx2x *bp = params->bp;
3267 u8 port = params->port;
3269 u8 ext_phy_addr = ((params->ext_phy_config &
3270 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3271 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3272 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3274 bnx2x_cl45_read(bp, params->port,
3275 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
3278 MDIO_PMA_REG_8073_CHIP_REV, &val);
3281 /* Mustn't set low power mode in 8073 A0 */
3285 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3286 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3288 MDIO_XS_PLL_SEQUENCER, &val);
3290 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3291 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3294 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3295 MDIO_XS_DEVAD, 0x805E, 0x1077);
3296 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3297 MDIO_XS_DEVAD, 0x805D, 0x0000);
3298 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3299 MDIO_XS_DEVAD, 0x805C, 0x030B);
3300 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3301 MDIO_XS_DEVAD, 0x805B, 0x1240);
3302 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3303 MDIO_XS_DEVAD, 0x805A, 0x2490);
3306 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3307 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3308 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3309 MDIO_XS_DEVAD, 0x80A6, 0x9041);
3310 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3311 MDIO_XS_DEVAD, 0x80A5, 0x4640);
3314 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3315 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3316 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3317 MDIO_XS_DEVAD, 0x80FD, 0x9249);
3318 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3319 MDIO_XS_DEVAD, 0x80FC, 0x2015);
3321 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
3322 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
3324 MDIO_XS_PLL_SEQUENCER, &val);
3326 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
3327 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3330 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
3331 struct link_vars *vars)
3334 struct bnx2x *bp = params->bp;
3336 u8 ext_phy_addr = ((params->ext_phy_config &
3337 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3338 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3339 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3341 bnx2x_cl45_read(bp, params->port,
3345 MDIO_AN_REG_CL37_FC_LD, &cl37_val);
3347 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3348 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3350 if ((vars->ieee_fc &
3351 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
3352 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
3353 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
3355 if ((vars->ieee_fc &
3356 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3358 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3360 if ((vars->ieee_fc &
3361 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3362 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3363 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3366 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
3368 bnx2x_cl45_write(bp, params->port,
3372 MDIO_AN_REG_CL37_FC_LD, cl37_val);
3376 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3377 struct link_vars *vars)
3379 struct bnx2x *bp = params->bp;
3381 u8 ext_phy_addr = ((params->ext_phy_config &
3382 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3383 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3384 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3386 /* read modify write pause advertizing */
3387 bnx2x_cl45_read(bp, params->port,
3391 MDIO_AN_REG_ADV_PAUSE, &val);
3393 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3395 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3397 if ((vars->ieee_fc &
3398 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3399 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3400 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3402 if ((vars->ieee_fc &
3403 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3404 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3406 MDIO_AN_REG_ADV_PAUSE_PAUSE;
3409 "Ext phy AN advertize 0x%x\n", val);
3410 bnx2x_cl45_write(bp, params->port,
3414 MDIO_AN_REG_ADV_PAUSE, val);
3416 static void bnx2x_set_preemphasis(struct link_params *params)
3419 struct bnx2x *bp = params->bp;
3421 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
3422 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
3423 CL45_WR_OVER_CL22(bp, params->port,
3426 MDIO_RX0_RX_EQ_BOOST,
3427 params->xgxs_config_rx[i]);
3430 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
3431 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
3432 CL45_WR_OVER_CL22(bp, params->port,
3436 params->xgxs_config_tx[i]);
3441 static void bnx2x_8481_set_led4(struct link_params *params,
3442 u32 ext_phy_type, u8 ext_phy_addr)
3444 struct bnx2x *bp = params->bp;
3446 /* PHYC_CTL_LED_CTL */
3447 bnx2x_cl45_write(bp, params->port,
3451 MDIO_PMA_REG_8481_LINK_SIGNAL, 0xa482);
3453 /* Unmask LED4 for 10G link */
3454 bnx2x_cl45_write(bp, params->port,
3458 MDIO_PMA_REG_8481_SIGNAL_MASK, (1<<6));
3459 /* 'Interrupt Mask' */
3460 bnx2x_cl45_write(bp, params->port,
3466 static void bnx2x_8481_set_legacy_led_mode(struct link_params *params,
3467 u32 ext_phy_type, u8 ext_phy_addr)
3469 struct bnx2x *bp = params->bp;
3471 /* LED1 (10G Link): Disable LED1 when 10/100/1000 link */
3472 /* LED2 (1G/100/10 Link): Enable LED2 when 10/100/1000 link) */
3473 bnx2x_cl45_write(bp, params->port,
3477 MDIO_AN_REG_8481_LEGACY_SHADOW,
3478 (1<<15) | (0xd << 10) | (0xc<<4) | 0xe);
3481 static void bnx2x_8481_set_10G_led_mode(struct link_params *params,
3482 u32 ext_phy_type, u8 ext_phy_addr)
3484 struct bnx2x *bp = params->bp;
3487 /* LED1 (10G Link) */
3488 /* Enable continuse based on source 7(10G-link) */
3489 bnx2x_cl45_read(bp, params->port,
3493 MDIO_PMA_REG_8481_LINK_SIGNAL,
3495 /* Set bit 2 to 0, and bits [1:0] to 10 */
3496 val1 &= ~((1<<0) | (1<<2)); /* Clear bits 0,2*/
3497 val1 |= (1<<1); /* Set bit 1 */
3499 bnx2x_cl45_write(bp, params->port,
3503 MDIO_PMA_REG_8481_LINK_SIGNAL,
3506 /* Unmask LED1 for 10G link */
3507 bnx2x_cl45_read(bp, params->port,
3511 MDIO_PMA_REG_8481_LED1_MASK,
3513 /* Set bit 2 to 0, and bits [1:0] to 10 */
3515 bnx2x_cl45_write(bp, params->port,
3519 MDIO_PMA_REG_8481_LED1_MASK,
3522 /* LED2 (1G/100/10G Link) */
3523 /* Mask LED2 for 10G link */
3524 bnx2x_cl45_write(bp, params->port,
3528 MDIO_PMA_REG_8481_LED2_MASK,
3531 /* LED3 (10G/1G/100/10G Activity) */
3532 bnx2x_cl45_read(bp, params->port,
3536 MDIO_PMA_REG_8481_LINK_SIGNAL,
3538 /* Enable blink based on source 4(Activity) */
3539 val1 &= ~((1<<7) | (1<<8)); /* Clear bits 7,8 */
3540 val1 |= (1<<6); /* Set only bit 6 */
3541 bnx2x_cl45_write(bp, params->port,
3545 MDIO_PMA_REG_8481_LINK_SIGNAL,
3548 bnx2x_cl45_read(bp, params->port,
3552 MDIO_PMA_REG_8481_LED3_MASK,
3554 val1 |= (1<<4); /* Unmask LED3 for 10G link */
3555 bnx2x_cl45_write(bp, params->port,
3559 MDIO_PMA_REG_8481_LED3_MASK,
3564 static void bnx2x_init_internal_phy(struct link_params *params,
3565 struct link_vars *vars,
3568 struct bnx2x *bp = params->bp;
3569 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
3570 if ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
3571 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3572 (params->feature_config_flags &
3573 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
3574 bnx2x_set_preemphasis(params);
3576 /* forced speed requested? */
3577 if (vars->line_speed != SPEED_AUTO_NEG) {
3578 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
3580 /* disable autoneg */
3581 bnx2x_set_autoneg(params, vars, 0);
3583 /* program speed and duplex */
3584 bnx2x_program_serdes(params, vars);
3586 } else { /* AN_mode */
3587 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
3590 bnx2x_set_brcm_cl37_advertisment(params);
3592 /* program duplex & pause advertisement (for aneg) */
3593 bnx2x_set_ieee_aneg_advertisment(params,
3596 /* enable autoneg */
3597 bnx2x_set_autoneg(params, vars, enable_cl73);
3599 /* enable and restart AN */
3600 bnx2x_restart_autoneg(params, enable_cl73);
3603 } else { /* SGMII mode */
3604 DP(NETIF_MSG_LINK, "SGMII\n");
3606 bnx2x_initialize_sgmii_process(params, vars);
3610 static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
3612 struct bnx2x *bp = params->bp;
3619 if (vars->phy_flags & PHY_XGXS_FLAG) {
3620 ext_phy_addr = ((params->ext_phy_config &
3621 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3622 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3624 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3625 /* Make sure that the soft reset is off (expect for the 8072:
3626 * due to the lock, it will be done inside the specific
3629 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3630 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3631 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
3632 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
3633 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
3634 /* Wait for soft reset to get cleared upto 1 sec */
3635 for (cnt = 0; cnt < 1000; cnt++) {
3636 bnx2x_cl45_read(bp, params->port,
3640 MDIO_PMA_REG_CTRL, &ctrl);
3641 if (!(ctrl & (1<<15)))
3645 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
3649 switch (ext_phy_type) {
3650 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3653 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3654 DP(NETIF_MSG_LINK, "XGXS 8705\n");
3656 bnx2x_cl45_write(bp, params->port,
3660 MDIO_PMA_REG_MISC_CTRL,
3662 bnx2x_cl45_write(bp, params->port,
3666 MDIO_PMA_REG_PHY_IDENTIFIER,
3668 bnx2x_cl45_write(bp, params->port,
3672 MDIO_PMA_REG_CMU_PLL_BYPASS,
3674 bnx2x_cl45_write(bp, params->port,
3678 MDIO_WIS_REG_LASI_CNTL, 0x1);
3680 /* BCM8705 doesn't have microcode, hence the 0 */
3681 bnx2x_save_spirom_version(bp, params->port,
3682 params->shmem_base, 0);
3685 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3686 /* Wait until fw is loaded */
3687 for (cnt = 0; cnt < 100; cnt++) {
3688 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3689 ext_phy_addr, MDIO_PMA_DEVAD,
3690 MDIO_PMA_REG_ROM_VER1, &val);
3695 DP(NETIF_MSG_LINK, "XGXS 8706 is initialized "
3696 "after %d ms\n", cnt);
3697 if ((params->feature_config_flags &
3698 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3701 for (i = 0; i < 4; i++) {
3702 reg = MDIO_XS_8706_REG_BANK_RX0 +
3703 i*(MDIO_XS_8706_REG_BANK_RX1 -
3704 MDIO_XS_8706_REG_BANK_RX0);
3705 bnx2x_cl45_read(bp, params->port,
3710 /* Clear first 3 bits of the control */
3712 /* Set control bits according to
3714 val |= (params->xgxs_config_rx[i] &
3716 DP(NETIF_MSG_LINK, "Setting RX"
3717 "Equalizer to BCM8706 reg 0x%x"
3718 " <-- val 0x%x\n", reg, val);
3719 bnx2x_cl45_write(bp, params->port,
3727 /* First enable LASI */
3728 bnx2x_cl45_write(bp, params->port,
3732 MDIO_PMA_REG_RX_ALARM_CTRL,
3734 bnx2x_cl45_write(bp, params->port,
3738 MDIO_PMA_REG_LASI_CTRL, 0x0004);
3740 if (params->req_line_speed == SPEED_10000) {
3741 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
3743 bnx2x_cl45_write(bp, params->port,
3747 MDIO_PMA_REG_DIGITAL_CTRL,
3750 /* Force 1Gbps using autoneg with 1G
3753 /* Allow CL37 through CL73 */
3754 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
3755 bnx2x_cl45_write(bp, params->port,
3759 MDIO_AN_REG_CL37_CL73,
3762 /* Enable Full-Duplex advertisment on CL37 */
3763 bnx2x_cl45_write(bp, params->port,
3767 MDIO_AN_REG_CL37_FC_LP,
3769 /* Enable CL37 AN */
3770 bnx2x_cl45_write(bp, params->port,
3774 MDIO_AN_REG_CL37_AN,
3777 bnx2x_cl45_write(bp, params->port,
3781 MDIO_AN_REG_ADV, (1<<5));
3783 /* Enable clause 73 AN */
3784 bnx2x_cl45_write(bp, params->port,
3792 bnx2x_save_bcm_spirom_ver(bp, params->port,
3795 params->shmem_base);
3797 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3798 DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
3799 bnx2x_bcm8726_external_rom_boot(params);
3801 /* Need to call module detected on initialization since
3802 the module detection triggered by actual module
3803 insertion might occur before driver is loaded, and when
3804 driver is loaded, it reset all registers, including the
3806 bnx2x_sfp_module_detection(params);
3808 /* Set Flow control */
3809 bnx2x_ext_phy_set_pause(params, vars);
3810 if (params->req_line_speed == SPEED_1000) {
3811 DP(NETIF_MSG_LINK, "Setting 1G force\n");
3812 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3813 ext_phy_addr, MDIO_PMA_DEVAD,
3814 MDIO_PMA_REG_CTRL, 0x40);
3815 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3816 ext_phy_addr, MDIO_PMA_DEVAD,
3817 MDIO_PMA_REG_10G_CTRL2, 0xD);
3818 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3819 ext_phy_addr, MDIO_PMA_DEVAD,
3820 MDIO_PMA_REG_LASI_CTRL, 0x5);
3821 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3822 ext_phy_addr, MDIO_PMA_DEVAD,
3823 MDIO_PMA_REG_RX_ALARM_CTRL,
3825 } else if ((params->req_line_speed ==
3827 ((params->speed_cap_mask &
3828 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
3829 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
3830 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3831 ext_phy_addr, MDIO_AN_DEVAD,
3832 MDIO_AN_REG_ADV, 0x20);
3833 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3834 ext_phy_addr, MDIO_AN_DEVAD,
3835 MDIO_AN_REG_CL37_CL73, 0x040c);
3836 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3837 ext_phy_addr, MDIO_AN_DEVAD,
3838 MDIO_AN_REG_CL37_FC_LD, 0x0020);
3839 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3840 ext_phy_addr, MDIO_AN_DEVAD,
3841 MDIO_AN_REG_CL37_AN, 0x1000);
3842 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3843 ext_phy_addr, MDIO_AN_DEVAD,
3844 MDIO_AN_REG_CTRL, 0x1200);
3846 /* Enable RX-ALARM control to receive
3847 interrupt for 1G speed change */
3848 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3849 ext_phy_addr, MDIO_PMA_DEVAD,
3850 MDIO_PMA_REG_LASI_CTRL, 0x4);
3851 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3852 ext_phy_addr, MDIO_PMA_DEVAD,
3853 MDIO_PMA_REG_RX_ALARM_CTRL,
3856 } else { /* Default 10G. Set only LASI control */
3857 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3858 ext_phy_addr, MDIO_PMA_DEVAD,
3859 MDIO_PMA_REG_LASI_CTRL, 1);
3862 /* Set TX PreEmphasis if needed */
3863 if ((params->feature_config_flags &
3864 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
3865 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
3867 params->xgxs_config_tx[0],
3868 params->xgxs_config_tx[1]);
3869 bnx2x_cl45_write(bp, params->port,
3873 MDIO_PMA_REG_8726_TX_CTRL1,
3874 params->xgxs_config_tx[0]);
3876 bnx2x_cl45_write(bp, params->port,
3880 MDIO_PMA_REG_8726_TX_CTRL2,
3881 params->xgxs_config_tx[1]);
3884 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3885 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3888 u16 rx_alarm_ctrl_val;
3891 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
3892 rx_alarm_ctrl_val = 0x400;
3893 lasi_ctrl_val = 0x0004;
3895 rx_alarm_ctrl_val = (1<<2);
3896 lasi_ctrl_val = 0x0004;
3900 bnx2x_cl45_write(bp, params->port,
3904 MDIO_PMA_REG_RX_ALARM_CTRL,
3907 bnx2x_cl45_write(bp, params->port,
3911 MDIO_PMA_REG_LASI_CTRL,
3914 bnx2x_8073_set_pause_cl37(params, vars);
3917 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
3918 bnx2x_bcm8072_external_rom_boot(params);
3921 /* In case of 8073 with long xaui lines,
3922 don't set the 8073 xaui low power*/
3923 bnx2x_bcm8073_set_xaui_low_power_mode(params);
3926 bnx2x_cl45_read(bp, params->port,
3930 MDIO_PMA_REG_M8051_MSGOUT_REG,
3933 bnx2x_cl45_read(bp, params->port,
3937 MDIO_PMA_REG_RX_ALARM, &tmp1);
3939 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
3942 /* If this is forced speed, set to KR or KX
3943 * (all other are not supported)
3945 if (params->loopback_mode == LOOPBACK_EXT) {
3946 bnx2x_bcm807x_force_10G(params);
3948 "Forced speed 10G on 807X\n");
3951 bnx2x_cl45_write(bp, params->port,
3952 ext_phy_type, ext_phy_addr,
3954 MDIO_PMA_REG_BCM_CTRL,
3957 if (params->req_line_speed != SPEED_AUTO_NEG) {
3958 if (params->req_line_speed == SPEED_10000) {
3960 } else if (params->req_line_speed ==
3963 /* Note that 2.5G works only
3964 when used with 1G advertisment */
3970 if (params->speed_cap_mask &
3971 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
3974 /* Note that 2.5G works only when
3975 used with 1G advertisment */
3976 if (params->speed_cap_mask &
3977 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
3978 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
3981 "807x autoneg val = 0x%x\n", val);
3984 bnx2x_cl45_write(bp, params->port,
3988 MDIO_AN_REG_ADV, val);
3991 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3993 bnx2x_cl45_read(bp, params->port,
3997 MDIO_AN_REG_8073_2_5G, &tmp1);
3999 if (((params->speed_cap_mask &
4000 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4001 (params->req_line_speed ==
4003 (params->req_line_speed ==
4006 /* Allow 2.5G for A1 and above */
4007 bnx2x_cl45_read(bp, params->port,
4008 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
4011 MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
4012 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4018 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4022 bnx2x_cl45_write(bp, params->port,
4026 MDIO_AN_REG_8073_2_5G, tmp1);
4029 /* Add support for CL37 (passive mode) II */
4031 bnx2x_cl45_read(bp, params->port,
4035 MDIO_AN_REG_CL37_FC_LD,
4038 bnx2x_cl45_write(bp, params->port,
4042 MDIO_AN_REG_CL37_FC_LD, (tmp1 |
4043 ((params->req_duplex == DUPLEX_FULL) ?
4046 /* Add support for CL37 (passive mode) III */
4047 bnx2x_cl45_write(bp, params->port,
4051 MDIO_AN_REG_CL37_AN, 0x1000);
4054 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4055 /* The SNR will improve about 2db by changing
4056 BW and FEE main tap. Rest commands are executed
4058 /*Change FFE main cursor to 5 in EDC register*/
4059 if (bnx2x_8073_is_snr_needed(params))
4060 bnx2x_cl45_write(bp, params->port,
4064 MDIO_PMA_REG_EDC_FFE_MAIN,
4067 /* Enable FEC (Forware Error Correction)
4068 Request in the AN */
4069 bnx2x_cl45_read(bp, params->port,
4073 MDIO_AN_REG_ADV2, &tmp1);
4077 bnx2x_cl45_write(bp, params->port,
4081 MDIO_AN_REG_ADV2, tmp1);
4085 bnx2x_ext_phy_set_pause(params, vars);
4087 /* Restart autoneg */
4089 bnx2x_cl45_write(bp, params->port,
4093 MDIO_AN_REG_CTRL, 0x1200);
4094 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
4095 "Advertise 1G=%x, 10G=%x\n",
4096 ((val & (1<<5)) > 0),
4097 ((val & (1<<7)) > 0));
4101 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4104 u16 rx_alarm_ctrl_val;
4107 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
4110 rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
4111 lasi_ctrl_val = 0x0004;
4113 DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
4115 bnx2x_cl45_write(bp, params->port,
4119 MDIO_PMA_REG_RX_ALARM_CTRL,
4122 bnx2x_cl45_write(bp, params->port,
4126 MDIO_PMA_REG_LASI_CTRL,
4129 /* Initially configure MOD_ABS to interrupt when
4130 module is presence( bit 8) */
4131 bnx2x_cl45_read(bp, params->port,
4135 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4136 /* Set EDC off by setting OPTXLOS signal input to low
4138 When the EDC is off it locks onto a reference clock and
4139 avoids becoming 'lost'.*/
4140 mod_abs &= ~((1<<8) | (1<<9));
4141 bnx2x_cl45_write(bp, params->port,
4145 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4147 /* Make MOD_ABS give interrupt on change */
4148 bnx2x_cl45_read(bp, params->port,
4152 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4155 bnx2x_cl45_write(bp, params->port,
4159 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4162 /* Set 8727 GPIOs to input to allow reading from the
4163 8727 GPIO0 status which reflect SFP+ module
4166 bnx2x_cl45_read(bp, params->port,
4167 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4170 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4172 val &= 0xff8f; /* Reset bits 4-6 */
4173 bnx2x_cl45_write(bp, params->port,
4174 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4177 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
4180 bnx2x_8727_power_module(bp, params, ext_phy_addr, 1);
4181 bnx2x_bcm8073_set_xaui_low_power_mode(params);
4183 bnx2x_cl45_read(bp, params->port,
4187 MDIO_PMA_REG_M8051_MSGOUT_REG,
4190 bnx2x_cl45_read(bp, params->port,
4194 MDIO_PMA_REG_RX_ALARM, &tmp1);
4196 /* Set option 1G speed */
4197 if (params->req_line_speed == SPEED_1000) {
4199 DP(NETIF_MSG_LINK, "Setting 1G force\n");
4200 bnx2x_cl45_write(bp, params->port,
4204 MDIO_PMA_REG_CTRL, 0x40);
4205 bnx2x_cl45_write(bp, params->port,
4209 MDIO_PMA_REG_10G_CTRL2, 0xD);
4210 bnx2x_cl45_read(bp, params->port,
4214 MDIO_PMA_REG_10G_CTRL2, &tmp1);
4215 DP(NETIF_MSG_LINK, "1.7 = 0x%x \n", tmp1);
4217 } else if ((params->req_line_speed ==
4219 ((params->speed_cap_mask &
4220 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))) {
4222 DP(NETIF_MSG_LINK, "Setting 1G clause37 \n");
4223 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4224 ext_phy_addr, MDIO_AN_DEVAD,
4225 MDIO_PMA_REG_8727_MISC_CTRL, 0);
4226 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4227 ext_phy_addr, MDIO_AN_DEVAD,
4228 MDIO_AN_REG_CL37_AN, 0x1300);
4230 /* Since the 8727 has only single reset pin,
4231 need to set the 10G registers although it is
4233 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4234 ext_phy_addr, MDIO_AN_DEVAD,
4235 MDIO_AN_REG_CTRL, 0x0020);
4236 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4237 ext_phy_addr, MDIO_AN_DEVAD,
4239 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4240 ext_phy_addr, MDIO_PMA_DEVAD,
4241 MDIO_PMA_REG_CTRL, 0x2040);
4242 bnx2x_cl45_write(bp, params->port, ext_phy_type,
4243 ext_phy_addr, MDIO_PMA_DEVAD,
4244 MDIO_PMA_REG_10G_CTRL2, 0x0008);
4247 /* Set 2-wire transfer rate to 400Khz since 100Khz
4248 is not operational */
4249 bnx2x_cl45_write(bp, params->port,
4253 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
4256 /* Set TX PreEmphasis if needed */
4257 if ((params->feature_config_flags &
4258 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
4259 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
4261 params->xgxs_config_tx[0],
4262 params->xgxs_config_tx[1]);
4263 bnx2x_cl45_write(bp, params->port,
4267 MDIO_PMA_REG_8727_TX_CTRL1,
4268 params->xgxs_config_tx[0]);
4270 bnx2x_cl45_write(bp, params->port,
4274 MDIO_PMA_REG_8727_TX_CTRL2,
4275 params->xgxs_config_tx[1]);
4281 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4283 u16 fw_ver1, fw_ver2;
4285 "Setting the SFX7101 LASI indication\n");
4287 bnx2x_cl45_write(bp, params->port,
4291 MDIO_PMA_REG_LASI_CTRL, 0x1);
4293 "Setting the SFX7101 LED to blink on traffic\n");
4294 bnx2x_cl45_write(bp, params->port,
4298 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
4300 bnx2x_ext_phy_set_pause(params, vars);
4301 /* Restart autoneg */
4302 bnx2x_cl45_read(bp, params->port,
4306 MDIO_AN_REG_CTRL, &val);
4308 bnx2x_cl45_write(bp, params->port,
4312 MDIO_AN_REG_CTRL, val);
4314 /* Save spirom version */
4315 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4316 ext_phy_addr, MDIO_PMA_DEVAD,
4317 MDIO_PMA_REG_7101_VER1, &fw_ver1);
4319 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4320 ext_phy_addr, MDIO_PMA_DEVAD,
4321 MDIO_PMA_REG_7101_VER2, &fw_ver2);
4323 bnx2x_save_spirom_version(params->bp, params->port,
4325 (u32)(fw_ver1<<16 | fw_ver2));
4329 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
4330 /* This phy uses the NIG latch mechanism since link
4331 indication arrives through its LED4 and not via
4332 its LASI signal, so we get steady signal
4333 instead of clear on read */
4334 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
4335 1 << NIG_LATCH_BC_ENABLE_MI_INT);
4337 bnx2x_8481_set_led4(params, ext_phy_type, ext_phy_addr);
4338 if (params->req_line_speed == SPEED_AUTO_NEG) {
4340 u16 autoneg_val, an_1000_val, an_10_100_val;
4341 /* set 1000 speed advertisement */
4342 bnx2x_cl45_read(bp, params->port,
4346 MDIO_AN_REG_8481_1000T_CTRL,
4349 if (params->speed_cap_mask &
4350 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) {
4351 an_1000_val |= (1<<8);
4352 if (params->req_duplex == DUPLEX_FULL)
4353 an_1000_val |= (1<<9);
4354 DP(NETIF_MSG_LINK, "Advertising 1G\n");
4356 an_1000_val &= ~((1<<8) | (1<<9));
4358 bnx2x_cl45_write(bp, params->port,
4362 MDIO_AN_REG_8481_1000T_CTRL,
4365 /* set 100 speed advertisement */
4366 bnx2x_cl45_read(bp, params->port,
4370 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4373 if (params->speed_cap_mask &
4374 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
4375 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) {
4376 an_10_100_val |= (1<<7);
4377 if (params->req_duplex == DUPLEX_FULL)
4378 an_10_100_val |= (1<<8);
4380 "Advertising 100M\n");
4382 an_10_100_val &= ~((1<<7) | (1<<8));
4384 /* set 10 speed advertisement */
4385 if (params->speed_cap_mask &
4386 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
4387 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) {
4388 an_10_100_val |= (1<<5);
4389 if (params->req_duplex == DUPLEX_FULL)
4390 an_10_100_val |= (1<<6);
4391 DP(NETIF_MSG_LINK, "Advertising 10M\n");
4394 an_10_100_val &= ~((1<<5) | (1<<6));
4396 bnx2x_cl45_write(bp, params->port,
4400 MDIO_AN_REG_8481_LEGACY_AN_ADV,
4403 bnx2x_cl45_read(bp, params->port,
4407 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4410 /* Disable forced speed */
4411 autoneg_val &= ~(1<<6|1<<13);
4413 /* Enable autoneg and restart autoneg
4414 for legacy speeds */
4415 autoneg_val |= (1<<9|1<<12);
4417 if (params->req_duplex == DUPLEX_FULL)
4418 autoneg_val |= (1<<8);
4420 autoneg_val &= ~(1<<8);
4422 bnx2x_cl45_write(bp, params->port,
4426 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4429 if (params->speed_cap_mask &
4430 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) {
4431 DP(NETIF_MSG_LINK, "Advertising 10G\n");
4432 /* Restart autoneg for 10G*/
4433 bnx2x_cl45_read(bp, params->port,
4437 MDIO_AN_REG_CTRL, &val);
4439 bnx2x_cl45_write(bp, params->port,
4443 MDIO_AN_REG_CTRL, val);
4447 u16 autoneg_ctrl, pma_ctrl;
4448 bnx2x_cl45_read(bp, params->port,
4452 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4455 /* Disable autoneg */
4456 autoneg_ctrl &= ~(1<<12);
4458 /* Set 1000 force */
4459 switch (params->req_line_speed) {
4462 "Unable to set 10G force !\n");
4465 bnx2x_cl45_read(bp, params->port,
4471 autoneg_ctrl &= ~(1<<13);
4472 autoneg_ctrl |= (1<<6);
4473 pma_ctrl &= ~(1<<13);
4476 "Setting 1000M force\n");
4477 bnx2x_cl45_write(bp, params->port,
4485 autoneg_ctrl |= (1<<13);
4486 autoneg_ctrl &= ~(1<<6);
4488 "Setting 100M force\n");
4491 autoneg_ctrl &= ~(1<<13);
4492 autoneg_ctrl &= ~(1<<6);
4494 "Setting 10M force\n");
4499 if (params->req_duplex == DUPLEX_FULL) {
4500 autoneg_ctrl |= (1<<8);
4502 "Setting full duplex\n");
4504 autoneg_ctrl &= ~(1<<8);
4506 /* Update autoneg ctrl and pma ctrl */
4507 bnx2x_cl45_write(bp, params->port,
4511 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
4515 /* Save spirom version */
4516 bnx2x_save_8481_spirom_version(bp, params->port,
4518 params->shmem_base);
4520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4522 "XGXS PHY Failure detected 0x%x\n",
4523 params->ext_phy_config);
4527 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
4528 params->ext_phy_config);
4533 } else { /* SerDes */
4535 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
4536 switch (ext_phy_type) {
4537 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
4538 DP(NETIF_MSG_LINK, "SerDes Direct\n");
4541 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
4542 DP(NETIF_MSG_LINK, "SerDes 5482\n");
4546 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
4547 params->ext_phy_config);
4554 static void bnx2x_8727_handle_mod_abs(struct link_params *params)
4556 struct bnx2x *bp = params->bp;
4557 u16 mod_abs, rx_alarm_status;
4558 u8 ext_phy_addr = ((params->ext_phy_config &
4559 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4560 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4561 u32 val = REG_RD(bp, params->shmem_base +
4562 offsetof(struct shmem_region, dev_info.
4563 port_feature_config[params->port].
4565 bnx2x_cl45_read(bp, params->port,
4566 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4569 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
4570 if (mod_abs & (1<<8)) {
4572 /* Module is absent */
4573 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4574 "show module is absent\n");
4576 /* 1. Set mod_abs to detect next module
4578 2. Set EDC off by setting OPTXLOS signal input to low
4580 When the EDC is off it locks onto a reference clock and
4581 avoids becoming 'lost'.*/
4582 mod_abs &= ~((1<<8)|(1<<9));
4583 bnx2x_cl45_write(bp, params->port,
4584 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4587 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4589 /* Clear RX alarm since it stays up as long as
4590 the mod_abs wasn't changed */
4591 bnx2x_cl45_read(bp, params->port,
4592 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4595 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4598 /* Module is present */
4599 DP(NETIF_MSG_LINK, "MOD_ABS indication "
4600 "show module is present\n");
4601 /* First thing, disable transmitter,
4602 and if the module is ok, the
4603 module_detection will enable it*/
4605 /* 1. Set mod_abs to detect next module
4606 absent event ( bit 8)
4607 2. Restore the default polarity of the OPRXLOS signal and
4608 this signal will then correctly indicate the presence or
4609 absence of the Rx signal. (bit 9) */
4610 mod_abs |= ((1<<8)|(1<<9));
4611 bnx2x_cl45_write(bp, params->port,
4612 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4615 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
4617 /* Clear RX alarm since it stays up as long as
4618 the mod_abs wasn't changed. This is need to be done
4619 before calling the module detection, otherwise it will clear
4620 the link update alarm */
4621 bnx2x_cl45_read(bp, params->port,
4622 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4625 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4628 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4629 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4630 bnx2x_sfp_set_transmitter(bp, params->port,
4631 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
4634 if (bnx2x_wait_for_sfp_module_initialized(params)
4636 bnx2x_sfp_module_detection(params);
4638 DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
4641 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4643 /* No need to check link status in case of
4644 module plugged in/out */
4648 static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
4649 struct link_vars *vars,
4652 struct bnx2x *bp = params->bp;
4656 u16 rx_sd, pcs_status;
4657 u8 ext_phy_link_up = 0;
4658 u8 port = params->port;
4659 if (vars->phy_flags & PHY_XGXS_FLAG) {
4660 ext_phy_addr = ((params->ext_phy_config &
4661 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4662 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4664 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4665 switch (ext_phy_type) {
4666 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4667 DP(NETIF_MSG_LINK, "XGXS Direct\n");
4668 ext_phy_link_up = 1;
4671 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4672 DP(NETIF_MSG_LINK, "XGXS 8705\n");
4673 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4676 MDIO_WIS_REG_LASI_STATUS, &val1);
4677 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4679 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4682 MDIO_WIS_REG_LASI_STATUS, &val1);
4683 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4685 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4688 MDIO_PMA_REG_RX_SD, &rx_sd);
4690 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4694 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4699 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4700 ext_phy_link_up = ((rx_sd & 0x1) && (val1 & (1<<9))
4701 && ((val1 & (1<<8)) == 0));
4702 if (ext_phy_link_up)
4703 vars->line_speed = SPEED_10000;
4706 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
4707 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
4708 DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
4710 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4712 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
4714 /* clear LASI indication*/
4715 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4717 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4719 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4721 MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS,
4723 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x-->"
4724 "0x%x\n", val1, val2);
4726 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4728 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD,
4730 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4732 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS,
4734 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4736 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4738 bnx2x_cl45_read(bp, params->port, ext_phy_type,
4740 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS,
4743 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x"
4744 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
4745 rx_sd, pcs_status, val2);
4746 /* link is up if both bit 0 of pmd_rx_sd and
4747 * bit 0 of pcs_status are set, or if the autoneg bit
4750 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
4752 if (ext_phy_link_up) {
4754 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
4755 /* If transmitter is disabled,
4756 ignore false link up indication */
4757 bnx2x_cl45_read(bp, params->port,
4761 MDIO_PMA_REG_PHY_IDENTIFIER,
4763 if (val1 & (1<<15)) {
4764 DP(NETIF_MSG_LINK, "Tx is "
4766 ext_phy_link_up = 0;
4772 vars->line_speed = SPEED_1000;
4774 vars->line_speed = SPEED_10000;
4778 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
4780 u16 link_status = 0;
4781 u16 rx_alarm_status;
4782 /* Check the LASI */
4783 bnx2x_cl45_read(bp, params->port,
4787 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
4789 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
4792 bnx2x_cl45_read(bp, params->port,
4796 MDIO_PMA_REG_LASI_STATUS, &val1);
4799 "8727 LASI status 0x%x\n",
4803 bnx2x_cl45_read(bp, params->port,
4807 MDIO_PMA_REG_M8051_MSGOUT_REG,
4811 * If a module is present and there is need to check
4814 if (!(params->feature_config_flags &
4815 FEATURE_CONFIG_BCM8727_NOC) &&
4816 !(rx_alarm_status & (1<<5))) {
4817 /* Check over-current using 8727 GPIO0 input*/
4818 bnx2x_cl45_read(bp, params->port,
4822 MDIO_PMA_REG_8727_GPIO_CTRL,
4825 if ((val1 & (1<<8)) == 0) {
4826 DP(NETIF_MSG_LINK, "8727 Power fault"
4827 " has been detected on port"
4828 " %d\n", params->port);
4829 printk(KERN_ERR PFX "Error: Power"
4830 " fault on %s Port %d has"
4831 " been detected and the"
4832 " power to that SFP+ module"
4833 " has been removed to prevent"
4834 " failure of the card. Please"
4835 " remove the SFP+ module and"
4836 " restart the system to clear"
4838 , bp->dev->name, params->port);
4840 * Disable all RX_ALARMs except for
4843 bnx2x_cl45_write(bp, params->port,
4847 MDIO_PMA_REG_RX_ALARM_CTRL,
4850 bnx2x_cl45_read(bp, params->port,
4854 MDIO_PMA_REG_PHY_IDENTIFIER,
4856 /* Wait for module_absent_event */
4858 bnx2x_cl45_write(bp, params->port,
4862 MDIO_PMA_REG_PHY_IDENTIFIER,
4864 /* Clear RX alarm */
4865 bnx2x_cl45_read(bp, params->port,
4869 MDIO_PMA_REG_RX_ALARM,
4873 } /* Over current check */
4875 /* When module absent bit is set, check module */
4876 if (rx_alarm_status & (1<<5)) {
4877 bnx2x_8727_handle_mod_abs(params);
4878 /* Enable all mod_abs and link detection bits */
4879 bnx2x_cl45_write(bp, params->port,
4883 MDIO_PMA_REG_RX_ALARM_CTRL,
4887 /* If transmitter is disabled,
4888 ignore false link up indication */
4889 bnx2x_cl45_read(bp, params->port,
4893 MDIO_PMA_REG_PHY_IDENTIFIER,
4895 if (val1 & (1<<15)) {
4896 DP(NETIF_MSG_LINK, "Tx is disabled\n");
4897 ext_phy_link_up = 0;
4901 bnx2x_cl45_read(bp, params->port,
4905 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4908 /* Bits 0..2 --> speed detected,
4909 bits 13..15--> link is down */
4910 if ((link_status & (1<<2)) &&
4911 (!(link_status & (1<<15)))) {
4912 ext_phy_link_up = 1;
4913 vars->line_speed = SPEED_10000;
4914 } else if ((link_status & (1<<0)) &&
4915 (!(link_status & (1<<13)))) {
4916 ext_phy_link_up = 1;
4917 vars->line_speed = SPEED_1000;
4919 "port %x: External link"
4920 " up in 1G\n", params->port);
4922 ext_phy_link_up = 0;
4924 "port %x: External link"
4925 " is down\n", params->port);
4930 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4931 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4933 u16 link_status = 0;
4934 u16 an1000_status = 0;
4936 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
4937 bnx2x_cl45_read(bp, params->port,
4941 MDIO_PCS_REG_LASI_STATUS, &val1);
4942 bnx2x_cl45_read(bp, params->port,
4946 MDIO_PCS_REG_LASI_STATUS, &val2);
4948 "870x LASI status 0x%x->0x%x\n",
4952 /* In 8073, port1 is directed through emac0 and
4953 * port0 is directed through emac1
4955 bnx2x_cl45_read(bp, params->port,
4959 MDIO_PMA_REG_LASI_STATUS, &val1);
4962 "8703 LASI status 0x%x\n",
4966 /* clear the interrupt LASI status register */
4967 bnx2x_cl45_read(bp, params->port,
4971 MDIO_PCS_REG_STATUS, &val2);
4972 bnx2x_cl45_read(bp, params->port,
4976 MDIO_PCS_REG_STATUS, &val1);
4977 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
4980 bnx2x_cl45_read(bp, params->port,
4984 MDIO_PMA_REG_M8051_MSGOUT_REG,
4987 /* Check the LASI */
4988 bnx2x_cl45_read(bp, params->port,
4992 MDIO_PMA_REG_RX_ALARM, &val2);
4994 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4996 /* Check the link status */
4997 bnx2x_cl45_read(bp, params->port,
5001 MDIO_PCS_REG_STATUS, &val2);
5002 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
5004 bnx2x_cl45_read(bp, params->port,
5008 MDIO_PMA_REG_STATUS, &val2);
5009 bnx2x_cl45_read(bp, params->port,
5013 MDIO_PMA_REG_STATUS, &val1);
5014 ext_phy_link_up = ((val1 & 4) == 4);
5015 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
5017 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
5019 if (ext_phy_link_up &&
5020 ((params->req_line_speed !=
5022 if (bnx2x_bcm8073_xaui_wa(params)
5024 ext_phy_link_up = 0;
5028 bnx2x_cl45_read(bp, params->port,
5032 MDIO_AN_REG_LINK_STATUS,
5034 bnx2x_cl45_read(bp, params->port,
5038 MDIO_AN_REG_LINK_STATUS,
5041 /* Check the link status on 1.1.2 */
5042 bnx2x_cl45_read(bp, params->port,
5046 MDIO_PMA_REG_STATUS, &val2);
5047 bnx2x_cl45_read(bp, params->port,
5051 MDIO_PMA_REG_STATUS, &val1);
5052 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
5053 "an_link_status=0x%x\n",
5054 val2, val1, an1000_status);
5056 ext_phy_link_up = (((val1 & 4) == 4) ||
5057 (an1000_status & (1<<1)));
5058 if (ext_phy_link_up &&
5059 bnx2x_8073_is_snr_needed(params)) {
5060 /* The SNR will improve about 2dbby
5061 changing the BW and FEE main tap.*/
5063 /* The 1st write to change FFE main
5064 tap is set before restart AN */
5065 /* Change PLL Bandwidth in EDC
5067 bnx2x_cl45_write(bp, port, ext_phy_type,
5070 MDIO_PMA_REG_PLL_BANDWIDTH,
5073 /* Change CDR Bandwidth in EDC
5075 bnx2x_cl45_write(bp, port, ext_phy_type,
5078 MDIO_PMA_REG_CDR_BANDWIDTH,
5083 bnx2x_cl45_read(bp, params->port,
5087 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
5090 /* Bits 0..2 --> speed detected,
5091 bits 13..15--> link is down */
5092 if ((link_status & (1<<2)) &&
5093 (!(link_status & (1<<15)))) {
5094 ext_phy_link_up = 1;
5095 vars->line_speed = SPEED_10000;
5097 "port %x: External link"
5098 " up in 10G\n", params->port);
5099 } else if ((link_status & (1<<1)) &&
5100 (!(link_status & (1<<14)))) {
5101 ext_phy_link_up = 1;
5102 vars->line_speed = SPEED_2500;
5104 "port %x: External link"
5105 " up in 2.5G\n", params->port);
5106 } else if ((link_status & (1<<0)) &&
5107 (!(link_status & (1<<13)))) {
5108 ext_phy_link_up = 1;
5109 vars->line_speed = SPEED_1000;
5111 "port %x: External link"
5112 " up in 1G\n", params->port);
5114 ext_phy_link_up = 0;
5116 "port %x: External link"
5117 " is down\n", params->port);
5120 /* See if 1G link is up for the 8072 */
5121 bnx2x_cl45_read(bp, params->port,
5125 MDIO_AN_REG_LINK_STATUS,
5127 bnx2x_cl45_read(bp, params->port,
5131 MDIO_AN_REG_LINK_STATUS,
5133 if (an1000_status & (1<<1)) {
5134 ext_phy_link_up = 1;
5135 vars->line_speed = SPEED_1000;
5137 "port %x: External link"
5138 " up in 1G\n", params->port);
5139 } else if (ext_phy_link_up) {
5140 ext_phy_link_up = 1;
5141 vars->line_speed = SPEED_10000;
5143 "port %x: External link"
5144 " up in 10G\n", params->port);
5151 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5152 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5155 MDIO_PMA_REG_LASI_STATUS, &val2);
5156 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5159 MDIO_PMA_REG_LASI_STATUS, &val1);
5161 "10G-base-T LASI status 0x%x->0x%x\n",
5163 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5166 MDIO_PMA_REG_STATUS, &val2);
5167 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5170 MDIO_PMA_REG_STATUS, &val1);
5172 "10G-base-T PMA status 0x%x->0x%x\n",
5174 ext_phy_link_up = ((val1 & 4) == 4);
5176 * print the AN outcome of the SFX7101 PHY
5178 if (ext_phy_link_up) {
5179 bnx2x_cl45_read(bp, params->port,
5183 MDIO_AN_REG_MASTER_STATUS,
5185 vars->line_speed = SPEED_10000;
5187 "SFX7101 AN status 0x%x->Master=%x\n",
5192 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5193 /* Check 10G-BaseT link status */
5194 /* Check PMD signal ok */
5195 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5200 bnx2x_cl45_read(bp, params->port, ext_phy_type,
5203 MDIO_PMA_REG_8481_PMD_SIGNAL,
5205 DP(NETIF_MSG_LINK, "PMD_SIGNAL 1.a811 = 0x%x\n", val2);
5207 /* Check link 10G */
5208 if (val2 & (1<<11)) {
5209 vars->line_speed = SPEED_10000;
5210 ext_phy_link_up = 1;
5211 bnx2x_8481_set_10G_led_mode(params,
5214 } else { /* Check Legacy speed link */
5215 u16 legacy_status, legacy_speed;
5217 /* Enable expansion register 0x42
5218 (Operation mode status) */
5219 bnx2x_cl45_write(bp, params->port,
5223 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS,
5226 /* Get legacy speed operation status */
5227 bnx2x_cl45_read(bp, params->port,
5231 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
5234 DP(NETIF_MSG_LINK, "Legacy speed status"
5235 " = 0x%x\n", legacy_status);
5236 ext_phy_link_up = ((legacy_status & (1<<11))
5238 if (ext_phy_link_up) {
5239 legacy_speed = (legacy_status & (3<<9));
5240 if (legacy_speed == (0<<9))
5241 vars->line_speed = SPEED_10;
5242 else if (legacy_speed == (1<<9))
5245 else if (legacy_speed == (2<<9))
5248 else /* Should not happen */
5249 vars->line_speed = 0;
5251 if (legacy_status & (1<<8))
5252 vars->duplex = DUPLEX_FULL;
5254 vars->duplex = DUPLEX_HALF;
5256 DP(NETIF_MSG_LINK, "Link is up "
5257 "in %dMbps, is_duplex_full"
5260 (vars->duplex == DUPLEX_FULL));
5261 bnx2x_8481_set_legacy_led_mode(params,
5269 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
5270 params->ext_phy_config);
5271 ext_phy_link_up = 0;
5275 } else { /* SerDes */
5276 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5277 switch (ext_phy_type) {
5278 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
5279 DP(NETIF_MSG_LINK, "SerDes Direct\n");
5280 ext_phy_link_up = 1;
5283 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
5284 DP(NETIF_MSG_LINK, "SerDes 5482\n");
5285 ext_phy_link_up = 1;
5290 "BAD SerDes ext_phy_config 0x%x\n",
5291 params->ext_phy_config);
5292 ext_phy_link_up = 0;
5297 return ext_phy_link_up;
5300 static void bnx2x_link_int_enable(struct link_params *params)
5302 u8 port = params->port;
5305 struct bnx2x *bp = params->bp;
5306 /* setting the status to report on link up
5307 for either XGXS or SerDes */
5309 if (params->switch_cfg == SWITCH_CFG_10G) {
5310 mask = (NIG_MASK_XGXS0_LINK10G |
5311 NIG_MASK_XGXS0_LINK_STATUS);
5312 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5313 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5314 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5315 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
5317 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
5318 mask |= NIG_MASK_MI_INT;
5319 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5322 } else { /* SerDes */
5323 mask = NIG_MASK_SERDES0_LINK_STATUS;
5324 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5325 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5326 if ((ext_phy_type !=
5327 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
5329 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
5330 mask |= NIG_MASK_MI_INT;
5331 DP(NETIF_MSG_LINK, "enabled external phy int\n");
5335 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5337 DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
5338 (params->switch_cfg == SWITCH_CFG_10G),
5339 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5341 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5342 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5343 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5344 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5345 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5346 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5347 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5350 static void bnx2x_8481_rearm_latch_signal(struct bnx2x *bp, u8 port,
5353 u32 latch_status = 0, is_mi_int_status;
5354 /* Disable the MI INT ( external phy int )
5355 * by writing 1 to the status register. Link down indication
5356 * is high-active-signal, so in this case we need to write the
5357 * status to clear the XOR
5359 /* Read Latched signals */
5360 latch_status = REG_RD(bp,
5361 NIG_REG_LATCH_STATUS_0 + port*8);
5362 is_mi_int_status = REG_RD(bp,
5363 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4);
5364 DP(NETIF_MSG_LINK, "original_signal = 0x%x, nig_status = 0x%x,"
5365 "latch_status = 0x%x\n",
5366 is_mi_int, is_mi_int_status, latch_status);
5367 /* Handle only those with latched-signal=up.*/
5368 if (latch_status & 1) {
5369 /* For all latched-signal=up,Write original_signal to status */
5372 NIG_REG_STATUS_INTERRUPT_PORT0
5374 NIG_STATUS_EMAC0_MI_INT);
5377 NIG_REG_STATUS_INTERRUPT_PORT0
5379 NIG_STATUS_EMAC0_MI_INT);
5380 /* For all latched-signal=up : Re-Arm Latch signals */
5381 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5382 (latch_status & 0xfffe) | (latch_status & 1));
5388 static void bnx2x_link_int_ack(struct link_params *params,
5389 struct link_vars *vars, u8 is_10g,
5392 struct bnx2x *bp = params->bp;
5393 u8 port = params->port;
5395 /* first reset all status
5396 * we assume only one line will be change at a time */
5397 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5398 (NIG_STATUS_XGXS0_LINK10G |
5399 NIG_STATUS_XGXS0_LINK_STATUS |
5400 NIG_STATUS_SERDES0_LINK_STATUS));
5401 if (XGXS_EXT_PHY_TYPE(params->ext_phy_config)
5402 == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481) {
5403 bnx2x_8481_rearm_latch_signal(bp, port, is_mi_int);
5405 if (vars->phy_link_up) {
5407 /* Disable the 10G link interrupt
5408 * by writing 1 to the status register
5410 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
5412 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5413 NIG_STATUS_XGXS0_LINK10G);
5415 } else if (params->switch_cfg == SWITCH_CFG_10G) {
5416 /* Disable the link interrupt
5417 * by writing 1 to the relevant lane
5418 * in the status register
5420 u32 ser_lane = ((params->lane_config &
5421 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5422 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5424 DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
5427 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5429 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
5431 } else { /* SerDes */
5432 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
5433 /* Disable the link interrupt
5434 * by writing 1 to the status register
5437 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5438 NIG_STATUS_SERDES0_LINK_STATUS);
5441 } else { /* link_down */
5445 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
5448 u32 mask = 0xf0000000;
5452 /* Need more than 10chars for this format */
5459 digit = ((num & mask) >> shift);
5461 *str_ptr = digit + '0';
5463 *str_ptr = digit - 0xa + 'a';
5475 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5476 u8 *version, u16 len)
5479 u32 ext_phy_type = 0;
5483 if (version == NULL || params == NULL)
5487 spirom_ver = REG_RD(bp, params->shmem_base +
5488 offsetof(struct shmem_region,
5489 port_mb[params->port].ext_phy_fw_version));
5492 /* reset the returned value to zero */
5493 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5494 switch (ext_phy_type) {
5495 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5500 version[0] = (spirom_ver & 0xFF);
5501 version[1] = (spirom_ver & 0xFF00) >> 8;
5502 version[2] = (spirom_ver & 0xFF0000) >> 16;
5503 version[3] = (spirom_ver & 0xFF000000) >> 24;
5507 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5508 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
5509 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
5510 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5511 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5512 status = bnx2x_format_ver(spirom_ver, version, len);
5514 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
5515 spirom_ver = ((spirom_ver & 0xF80) >> 7) << 16 |
5516 (spirom_ver & 0x7F);
5517 status = bnx2x_format_ver(spirom_ver, version, len);
5519 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5524 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
5525 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
5526 " type is FAILURE!\n");
5536 static void bnx2x_set_xgxs_loopback(struct link_params *params,
5537 struct link_vars *vars,
5540 u8 port = params->port;
5541 struct bnx2x *bp = params->bp;
5546 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5548 /* change the uni_phy_addr in the nig */
5549 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5552 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
5554 bnx2x_cl45_write(bp, port, 0,
5557 (MDIO_REG_BANK_AER_BLOCK +
5558 (MDIO_AER_BLOCK_AER_REG & 0xf)),
5561 bnx2x_cl45_write(bp, port, 0,
5564 (MDIO_REG_BANK_CL73_IEEEB0 +
5565 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5568 /* set aer mmd back */
5569 bnx2x_set_aer_mmd(params, vars);
5572 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5578 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5580 CL45_RD_OVER_CL22(bp, port,
5582 MDIO_REG_BANK_COMBO_IEEE0,
5583 MDIO_COMBO_IEEE0_MII_CONTROL,
5586 CL45_WR_OVER_CL22(bp, port,
5588 MDIO_REG_BANK_COMBO_IEEE0,
5589 MDIO_COMBO_IEEE0_MII_CONTROL,
5591 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
5596 static void bnx2x_ext_phy_loopback(struct link_params *params)
5598 struct bnx2x *bp = params->bp;
5602 if (params->switch_cfg == SWITCH_CFG_10G) {
5603 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5604 /* CL37 Autoneg Enabled */
5605 ext_phy_addr = ((params->ext_phy_config &
5606 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
5607 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
5608 switch (ext_phy_type) {
5609 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
5610 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
5612 "ext_phy_loopback: We should not get here\n");
5614 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
5615 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
5617 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
5618 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
5620 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
5621 DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5622 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5628 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
5629 /* SFX7101_XGXS_TEST1 */
5630 bnx2x_cl45_write(bp, params->port, ext_phy_type,
5633 MDIO_XS_SFX7101_XGXS_TEST1,
5636 "ext_phy_loopback: set ext phy loopback\n");
5638 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
5641 } /* switch external PHY type */
5644 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
5645 ext_phy_addr = (params->ext_phy_config &
5646 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
5647 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
5653 *------------------------------------------------------------------------
5654 * bnx2x_override_led_value -
5656 * Override the led value of the requsted led
5658 *------------------------------------------------------------------------
5660 u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
5661 u32 led_idx, u32 value)
5665 /* If port 0 then use EMAC0, else use EMAC1*/
5666 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5669 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
5670 port, led_idx, value);
5673 case 0: /* 10MB led */
5674 /* Read the current value of the LED register in
5676 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5677 /* Set the OVERRIDE bit to 1 */
5678 reg_val |= EMAC_LED_OVERRIDE;
5679 /* If value is 1, set the 10M_OVERRIDE bit,
5680 otherwise reset it.*/
5681 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
5682 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
5683 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5685 case 1: /*100MB led */
5686 /*Read the current value of the LED register in
5688 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5689 /* Set the OVERRIDE bit to 1 */
5690 reg_val |= EMAC_LED_OVERRIDE;
5691 /* If value is 1, set the 100M_OVERRIDE bit,
5692 otherwise reset it.*/
5693 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
5694 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
5695 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5697 case 2: /* 1000MB led */
5698 /* Read the current value of the LED register in the
5700 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5701 /* Set the OVERRIDE bit to 1 */
5702 reg_val |= EMAC_LED_OVERRIDE;
5703 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
5705 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
5706 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
5707 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5709 case 3: /* 2500MB led */
5710 /* Read the current value of the LED register in the
5712 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
5713 /* Set the OVERRIDE bit to 1 */
5714 reg_val |= EMAC_LED_OVERRIDE;
5715 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
5717 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
5718 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
5719 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5721 case 4: /*10G led */
5723 REG_WR(bp, NIG_REG_LED_10G_P0,
5726 REG_WR(bp, NIG_REG_LED_10G_P1,
5730 case 5: /* TRAFFIC led */
5731 /* Find if the traffic control is via BMAC or EMAC */
5733 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
5735 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
5737 /* Override the traffic led in the EMAC:*/
5739 /* Read the current value of the LED register in
5741 reg_val = REG_RD(bp, emac_base +
5743 /* Set the TRAFFIC_OVERRIDE bit to 1 */
5744 reg_val |= EMAC_LED_OVERRIDE;
5745 /* If value is 1, set the TRAFFIC bit, otherwise
5747 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
5748 (reg_val & ~EMAC_LED_TRAFFIC);
5749 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
5750 } else { /* Override the traffic led in the BMAC: */
5751 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5753 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
5759 "bnx2x_override_led_value() unknown led index %d "
5760 "(should be 0-5)\n", led_idx);
5768 u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
5769 u16 hw_led_mode, u32 chip_id)
5773 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5774 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5775 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5776 speed, hw_led_mode);
5779 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5780 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5781 SHARED_HW_CFG_LED_MAC1);
5783 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5784 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5788 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5789 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
5791 /* Set blinking rate to ~15.9Hz */
5792 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5793 LED_BLINK_RATE_VAL);
5794 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5796 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5797 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5798 (tmp & (~EMAC_LED_OVERRIDE)));
5800 if (!CHIP_IS_E1H(bp) &&
5801 ((speed == SPEED_2500) ||
5802 (speed == SPEED_1000) ||
5803 (speed == SPEED_100) ||
5804 (speed == SPEED_10))) {
5805 /* On Everest 1 Ax chip versions for speeds less than
5806 10G LED scheme is different */
5807 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5809 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5811 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5818 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5826 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
5828 struct bnx2x *bp = params->bp;
5831 CL45_RD_OVER_CL22(bp, params->port,
5833 MDIO_REG_BANK_GP_STATUS,
5834 MDIO_GP_STATUS_TOP_AN_STATUS1,
5836 /* link is up only if both local phy and external phy are up */
5837 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
5838 bnx2x_ext_phy_is_link_up(params, vars, 1))
5844 static u8 bnx2x_link_initialize(struct link_params *params,
5845 struct link_vars *vars)
5847 struct bnx2x *bp = params->bp;
5848 u8 port = params->port;
5851 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
5852 /* Activate the external PHY */
5853 bnx2x_ext_phy_reset(params, vars);
5855 bnx2x_set_aer_mmd(params, vars);
5857 if (vars->phy_flags & PHY_XGXS_FLAG)
5858 bnx2x_set_master_ln(params);
5860 rc = bnx2x_reset_unicore(params);
5861 /* reset the SerDes and wait for reset bit return low */
5865 bnx2x_set_aer_mmd(params, vars);
5867 /* setting the masterLn_def again after the reset */
5868 if (vars->phy_flags & PHY_XGXS_FLAG) {
5869 bnx2x_set_master_ln(params);
5870 bnx2x_set_swap_lanes(params);
5873 if (vars->phy_flags & PHY_XGXS_FLAG) {
5874 if ((params->req_line_speed &&
5875 ((params->req_line_speed == SPEED_100) ||
5876 (params->req_line_speed == SPEED_10))) ||
5877 (!params->req_line_speed &&
5878 (params->speed_cap_mask >=
5879 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5880 (params->speed_cap_mask <
5881 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5883 vars->phy_flags |= PHY_SGMII_FLAG;
5885 vars->phy_flags &= ~PHY_SGMII_FLAG;
5888 /* In case of external phy existance, the line speed would be the
5889 line speed linked up by the external phy. In case it is direct only,
5890 then the line_speed during initialization will be equal to the
5892 vars->line_speed = params->req_line_speed;
5894 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
5896 /* init ext phy and enable link state int */
5897 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
5898 (params->loopback_mode == LOOPBACK_XGXS_10));
5901 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
5902 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) ||
5903 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
5904 if (params->req_line_speed == SPEED_AUTO_NEG)
5905 bnx2x_set_parallel_detection(params, vars->phy_flags);
5906 bnx2x_init_internal_phy(params, vars, non_ext_phy);
5910 rc |= bnx2x_ext_phy_init(params, vars);
5912 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5913 (NIG_STATUS_XGXS0_LINK10G |
5914 NIG_STATUS_XGXS0_LINK_STATUS |
5915 NIG_STATUS_SERDES0_LINK_STATUS));
5922 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
5924 struct bnx2x *bp = params->bp;
5927 DP(NETIF_MSG_LINK, "Phy Initialization started \n");
5928 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
5929 params->req_line_speed, params->req_flow_ctrl);
5930 vars->link_status = 0;
5931 vars->phy_link_up = 0;
5933 vars->line_speed = 0;
5934 vars->duplex = DUPLEX_FULL;
5935 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5936 vars->mac_type = MAC_TYPE_NONE;
5938 if (params->switch_cfg == SWITCH_CFG_1G)
5939 vars->phy_flags = PHY_SERDES_FLAG;
5941 vars->phy_flags = PHY_XGXS_FLAG;
5944 /* disable attentions */
5945 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
5946 (NIG_MASK_XGXS0_LINK_STATUS |
5947 NIG_MASK_XGXS0_LINK10G |
5948 NIG_MASK_SERDES0_LINK_STATUS |
5951 bnx2x_emac_init(params, vars);
5953 if (CHIP_REV_IS_FPGA(bp)) {
5955 vars->line_speed = SPEED_10000;
5956 vars->duplex = DUPLEX_FULL;
5957 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5958 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5959 /* enable on E1.5 FPGA */
5960 if (CHIP_IS_E1H(bp)) {
5962 (BNX2X_FLOW_CTRL_TX | BNX2X_FLOW_CTRL_RX);
5963 vars->link_status |=
5964 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
5965 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
5968 bnx2x_emac_enable(params, vars, 0);
5969 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5971 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5972 + params->port*4, 0);
5974 /* update shared memory */
5975 bnx2x_update_mng(params, vars->link_status);
5980 if (CHIP_REV_IS_EMUL(bp)) {
5983 vars->line_speed = SPEED_10000;
5984 vars->duplex = DUPLEX_FULL;
5985 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5986 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
5988 bnx2x_bmac_enable(params, vars, 0);
5990 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
5992 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
5993 + params->port*4, 0);
5995 /* update shared memory */
5996 bnx2x_update_mng(params, vars->link_status);
6001 if (params->loopback_mode == LOOPBACK_BMAC) {
6003 vars->line_speed = SPEED_10000;
6004 vars->duplex = DUPLEX_FULL;
6005 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6006 vars->mac_type = MAC_TYPE_BMAC;
6008 vars->phy_flags = PHY_XGXS_FLAG;
6010 bnx2x_phy_deassert(params, vars->phy_flags);
6011 /* set bmac loopback */
6012 bnx2x_bmac_enable(params, vars, 1);
6014 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6016 } else if (params->loopback_mode == LOOPBACK_EMAC) {
6018 vars->line_speed = SPEED_1000;
6019 vars->duplex = DUPLEX_FULL;
6020 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6021 vars->mac_type = MAC_TYPE_EMAC;
6023 vars->phy_flags = PHY_XGXS_FLAG;
6025 bnx2x_phy_deassert(params, vars->phy_flags);
6026 /* set bmac loopback */
6027 bnx2x_emac_enable(params, vars, 1);
6028 bnx2x_emac_program(params, vars->line_speed,
6030 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6032 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
6033 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6035 vars->line_speed = SPEED_10000;
6036 vars->duplex = DUPLEX_FULL;
6037 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
6039 vars->phy_flags = PHY_XGXS_FLAG;
6042 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6044 params->phy_addr = (u8)val;
6046 bnx2x_phy_deassert(params, vars->phy_flags);
6047 bnx2x_link_initialize(params, vars);
6049 vars->mac_type = MAC_TYPE_BMAC;
6051 bnx2x_bmac_enable(params, vars, 0);
6053 if (params->loopback_mode == LOOPBACK_XGXS_10) {
6054 /* set 10G XGXS loopback */
6055 bnx2x_set_xgxs_loopback(params, vars, 1);
6057 /* set external phy loopback */
6058 bnx2x_ext_phy_loopback(params);
6060 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
6063 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
6064 vars->line_speed, params->hw_led_mode,
6071 bnx2x_phy_deassert(params, vars->phy_flags);
6072 switch (params->switch_cfg) {
6074 vars->phy_flags |= PHY_SERDES_FLAG;
6075 if ((params->ext_phy_config &
6076 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
6077 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
6083 NIG_REG_SERDES0_CTRL_PHY_ADDR+
6086 params->phy_addr = (u8)val;
6089 case SWITCH_CFG_10G:
6090 vars->phy_flags |= PHY_XGXS_FLAG;
6092 NIG_REG_XGXS0_CTRL_PHY_ADDR+
6094 params->phy_addr = (u8)val;
6098 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
6102 DP(NETIF_MSG_LINK, "Phy address = 0x%x\n", params->phy_addr);
6104 bnx2x_link_initialize(params, vars);
6106 bnx2x_link_int_enable(params);
6111 static void bnx2x_8726_reset_phy(struct bnx2x *bp, u8 port, u8 ext_phy_addr)
6113 DP(NETIF_MSG_LINK, "bnx2x_8726_reset_phy port %d\n", port);
6115 /* Set serial boot control for external load */
6116 bnx2x_cl45_write(bp, port,
6117 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, ext_phy_addr,
6119 MDIO_PMA_REG_GEN_CTRL, 0x0001);
6122 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
6126 struct bnx2x *bp = params->bp;
6127 u32 ext_phy_config = params->ext_phy_config;
6128 u16 hw_led_mode = params->hw_led_mode;
6129 u32 chip_id = params->chip_id;
6130 u8 port = params->port;
6131 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
6132 u32 val = REG_RD(bp, params->shmem_base +
6133 offsetof(struct shmem_region, dev_info.
6134 port_feature_config[params->port].
6137 /* disable attentions */
6139 vars->link_status = 0;
6140 bnx2x_update_mng(params, vars->link_status);
6141 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6142 (NIG_MASK_XGXS0_LINK_STATUS |
6143 NIG_MASK_XGXS0_LINK10G |
6144 NIG_MASK_SERDES0_LINK_STATUS |
6147 /* activate nig drain */
6148 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6150 /* disable nig egress interface */
6151 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6152 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6154 /* Stop BigMac rx */
6155 bnx2x_bmac_rx_disable(bp, port);
6158 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6161 /* The PHY reset is controled by GPIO 1
6162 * Hold it as vars low
6164 /* clear link led */
6165 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
6166 if (reset_ext_phy) {
6167 switch (ext_phy_type) {
6168 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
6169 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
6172 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6175 /* Disable Transmitter */
6176 u8 ext_phy_addr = ((params->ext_phy_config &
6177 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6178 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6179 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
6180 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
6181 bnx2x_sfp_set_transmitter(bp, port,
6182 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6186 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6187 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
6190 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6191 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6194 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6196 u8 ext_phy_addr = ((params->ext_phy_config &
6197 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6198 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6199 /* Set soft reset */
6200 bnx2x_8726_reset_phy(bp, params->port, ext_phy_addr);
6205 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6206 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6208 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6209 MISC_REGISTERS_GPIO_OUTPUT_LOW,
6211 DP(NETIF_MSG_LINK, "reset external PHY\n");
6214 /* reset the SerDes/XGXS */
6215 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6216 (0x1ff << (port*16)));
6219 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
6220 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6222 /* disable nig ingress interface */
6223 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
6224 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
6225 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
6226 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
6231 static u8 bnx2x_update_link_down(struct link_params *params,
6232 struct link_vars *vars)
6234 struct bnx2x *bp = params->bp;
6235 u8 port = params->port;
6236 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6237 bnx2x_set_led(bp, port, LED_MODE_OFF,
6238 0, params->hw_led_mode,
6241 /* indicate no mac active */
6242 vars->mac_type = MAC_TYPE_NONE;
6244 /* update shared memory */
6245 vars->link_status = 0;
6246 vars->line_speed = 0;
6247 bnx2x_update_mng(params, vars->link_status);
6249 /* activate nig drain */
6250 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6253 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6258 bnx2x_bmac_rx_disable(bp, params->port);
6259 REG_WR(bp, GRCBASE_MISC +
6260 MISC_REGISTERS_RESET_REG_2_CLEAR,
6261 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6265 static u8 bnx2x_update_link_up(struct link_params *params,
6266 struct link_vars *vars,
6267 u8 link_10g, u32 gp_status)
6269 struct bnx2x *bp = params->bp;
6270 u8 port = params->port;
6272 vars->link_status |= LINK_STATUS_LINK_UP;
6274 bnx2x_bmac_enable(params, vars, 0);
6275 bnx2x_set_led(bp, port, LED_MODE_OPER,
6276 SPEED_10000, params->hw_led_mode,
6280 bnx2x_emac_enable(params, vars, 0);
6281 rc = bnx2x_emac_program(params, vars->line_speed,
6285 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
6286 if (!(vars->phy_flags &
6288 bnx2x_set_gmii_tx_driver(params);
6293 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6297 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6299 /* update shared memory */
6300 bnx2x_update_mng(params, vars->link_status);
6304 /* This function should called upon link interrupt */
6305 /* In case vars->link_up, driver needs to
6308 3. Update the shared memory
6312 1. Update shared memory
6317 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6319 struct bnx2x *bp = params->bp;
6320 u8 port = params->port;
6323 u8 ext_phy_link_up, rc = 0;
6327 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6328 port, (vars->phy_flags & PHY_XGXS_FLAG),
6329 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6331 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6333 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6334 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6337 NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6339 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6340 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6341 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6344 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6346 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
6348 /* Check external link change only for non-direct */
6349 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars, is_mi_int);
6351 /* Read gp_status */
6352 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
6353 MDIO_REG_BANK_GP_STATUS,
6354 MDIO_GP_STATUS_TOP_AN_STATUS1,
6357 rc = bnx2x_link_settings_status(params, vars, gp_status,
6362 /* anything 10 and over uses the bmac */
6363 link_10g = ((vars->line_speed == SPEED_10000) ||
6364 (vars->line_speed == SPEED_12000) ||
6365 (vars->line_speed == SPEED_12500) ||
6366 (vars->line_speed == SPEED_13000) ||
6367 (vars->line_speed == SPEED_15000) ||
6368 (vars->line_speed == SPEED_16000));
6370 bnx2x_link_int_ack(params, vars, link_10g, is_mi_int);
6372 /* In case external phy link is up, and internal link is down
6373 ( not initialized yet probably after link initialization, it needs
6375 Note that after link down-up as result of cable plug,
6376 the xgxs link would probably become up again without the need to
6379 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
6380 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
6381 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) &&
6382 (ext_phy_link_up && !vars->phy_link_up))
6383 bnx2x_init_internal_phy(params, vars, 0);
6385 /* link is up only if both local phy and external phy are up */
6386 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
6389 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
6391 rc = bnx2x_update_link_down(params, vars);
6396 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6398 u8 ext_phy_addr[PORT_MAX];
6402 /* PART1 - Reset both phys */
6403 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6404 /* Extract the ext phy address for the port */
6405 u32 ext_phy_config = REG_RD(bp, shmem_base +
6406 offsetof(struct shmem_region,
6407 dev_info.port_hw_config[port].external_phy_config));
6409 /* disable attentions */
6410 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6411 (NIG_MASK_XGXS0_LINK_STATUS |
6412 NIG_MASK_XGXS0_LINK10G |
6413 NIG_MASK_SERDES0_LINK_STATUS |
6416 ext_phy_addr[port] =
6418 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6419 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6421 /* Need to take the phy out of low power mode in order
6422 to write to access its registers */
6423 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6424 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6427 bnx2x_cl45_write(bp, port,
6428 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6435 /* Add delay of 150ms after reset */
6438 /* PART2 - Download firmware to both phys */
6439 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6442 bnx2x_bcm8073_external_rom_boot(bp, port,
6443 ext_phy_addr[port], shmem_base);
6445 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6448 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6449 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6451 "bnx2x_8073_common_init_phy port %x:"
6452 "Download failed. fw version = 0x%x\n",
6457 /* Only set bit 10 = 1 (Tx power down) */
6458 bnx2x_cl45_read(bp, port,
6459 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6462 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6464 /* Phase1 of TX_POWER_DOWN reset */
6465 bnx2x_cl45_write(bp, port,
6466 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6469 MDIO_PMA_REG_TX_POWER_DOWN,
6473 /* Toggle Transmitter: Power down and then up with 600ms
6477 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
6478 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
6479 /* Phase2 of POWER_DOWN_RESET */
6480 /* Release bit 10 (Release Tx power down) */
6481 bnx2x_cl45_read(bp, port,
6482 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6485 MDIO_PMA_REG_TX_POWER_DOWN, &val);
6487 bnx2x_cl45_write(bp, port,
6488 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6491 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
6494 /* Read modify write the SPI-ROM version select register */
6495 bnx2x_cl45_read(bp, port,
6496 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6499 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
6500 bnx2x_cl45_write(bp, port,
6501 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6504 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
6506 /* set GPIO2 back to LOW */
6507 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6508 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6514 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6516 u8 ext_phy_addr[PORT_MAX];
6517 s8 port, first_port, i;
6518 u32 swap_val, swap_override;
6519 DP(NETIF_MSG_LINK, "Executing BCM8727 common init\n");
6520 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
6521 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
6523 bnx2x_ext_phy_hw_reset(bp, 1 ^ (swap_val && swap_override));
6526 if (swap_val && swap_override)
6527 first_port = PORT_0;
6529 first_port = PORT_1;
6531 /* PART1 - Reset both phys */
6532 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6533 /* Extract the ext phy address for the port */
6534 u32 ext_phy_config = REG_RD(bp, shmem_base +
6535 offsetof(struct shmem_region,
6536 dev_info.port_hw_config[port].external_phy_config));
6538 /* disable attentions */
6539 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6540 (NIG_MASK_XGXS0_LINK_STATUS |
6541 NIG_MASK_XGXS0_LINK10G |
6542 NIG_MASK_SERDES0_LINK_STATUS |
6545 ext_phy_addr[port] = ((ext_phy_config &
6546 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6547 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6550 bnx2x_cl45_write(bp, port,
6551 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6558 /* Add delay of 150ms after reset */
6561 /* PART2 - Download firmware to both phys */
6562 for (i = 0, port = first_port; i < PORT_MAX; i++, port = !port) {
6565 bnx2x_bcm8727_external_rom_boot(bp, port,
6566 ext_phy_addr[port], shmem_base);
6568 bnx2x_cl45_read(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6571 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6572 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
6574 "bnx2x_8727_common_init_phy port %x:"
6575 "Download failed. fw version = 0x%x\n",
6585 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6590 /* Use port1 because of the static port-swap */
6591 /* Enable the module detection interrupt */
6592 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
6593 val |= ((1<<MISC_REGISTERS_GPIO_3)|
6594 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
6595 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
6597 bnx2x_ext_phy_hw_reset(bp, 1);
6599 for (port = 0; port < PORT_MAX; port++) {
6600 /* Extract the ext phy address for the port */
6601 u32 ext_phy_config = REG_RD(bp, shmem_base +
6602 offsetof(struct shmem_region,
6603 dev_info.port_hw_config[port].external_phy_config));
6607 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
6608 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
6609 DP(NETIF_MSG_LINK, "8726_common_init : ext_phy_addr = 0x%x\n",
6612 bnx2x_8726_reset_phy(bp, port, ext_phy_addr);
6614 /* Set fault module detected LED on */
6615 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
6616 MISC_REGISTERS_GPIO_HIGH,
6623 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base)
6628 DP(NETIF_MSG_LINK, "Begin common phy init\n");
6630 /* Read the ext_phy_type for arbitrary port(0) */
6631 ext_phy_type = XGXS_EXT_PHY_TYPE(
6632 REG_RD(bp, shmem_base +
6633 offsetof(struct shmem_region,
6634 dev_info.port_hw_config[0].external_phy_config)));
6636 switch (ext_phy_type) {
6637 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
6639 rc = bnx2x_8073_common_init_phy(bp, shmem_base);
6643 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6644 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
6645 rc = bnx2x_8727_common_init_phy(bp, shmem_base);
6648 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
6649 /* GPIO1 affects both ports, so there's need to pull
6650 it for single port alone */
6651 rc = bnx2x_8726_common_init_phy(bp, shmem_base);
6656 "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
6664 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
6668 bnx2x_cl45_read(bp, port,
6669 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6672 MDIO_PMA_REG_7101_RESET, &val);
6674 for (cnt = 0; cnt < 10; cnt++) {
6676 /* Writes a self-clearing reset */
6677 bnx2x_cl45_write(bp, port,
6678 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6681 MDIO_PMA_REG_7101_RESET,
6683 /* Wait for clear */
6684 bnx2x_cl45_read(bp, port,
6685 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6688 MDIO_PMA_REG_7101_RESET, &val);
6690 if ((val & (1<<15)) == 0)