1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 /* compilation time flags */
19 /* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21 /* #define BNX2X_STOP_ON_ERROR */
23 #define DRV_MODULE_VERSION "1.52.53-7"
24 #define DRV_MODULE_RELDATE "2010/09/12"
25 #define BNX2X_BC_VER 0x040200
27 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define BNX2X_MULTI_QUEUE
33 #define BNX2X_NEW_NAPI
36 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
38 #include "../cnic_if.h"
42 #define BNX2X_MIN_MSIX_VEC_CNT 3
43 #define BNX2X_MSIX_VEC_FP_START 2
45 #define BNX2X_MIN_MSIX_VEC_CNT 2
46 #define BNX2X_MSIX_VEC_FP_START 1
49 #include <linux/mdio.h>
50 #include <linux/pci.h>
51 #include "bnx2x_reg.h"
52 #include "bnx2x_fw_defs.h"
53 #include "bnx2x_hsi.h"
54 #include "bnx2x_link.h"
55 #include "bnx2x_stats.h"
57 /* error/debug prints */
59 #define DRV_MODULE_NAME "bnx2x"
61 /* for messages that are currently off */
62 #define BNX2X_MSG_OFF 0
63 #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
64 #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
65 #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
68 #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
70 #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
72 /* regular debug print */
73 #define DP(__mask, __fmt, __args...) \
75 if (bp->msg_enable & (__mask)) \
76 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
78 bp->dev ? (bp->dev->name) : "?", \
82 /* errors debug print */
83 #define BNX2X_DBG_ERR(__fmt, __args...) \
85 if (netif_msg_probe(bp)) \
86 pr_err("[%s:%d(%s)]" __fmt, \
88 bp->dev ? (bp->dev->name) : "?", \
92 /* for errors (never masked) */
93 #define BNX2X_ERR(__fmt, __args...) \
95 pr_err("[%s:%d(%s)]" __fmt, \
97 bp->dev ? (bp->dev->name) : "?", \
101 #define BNX2X_ERROR(__fmt, __args...) do { \
102 pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \
106 /* before we have a dev->name use dev_info() */
107 #define BNX2X_DEV_INFO(__fmt, __args...) \
109 if (netif_msg_probe(bp)) \
110 dev_info(&bp->pdev->dev, __fmt, ##__args); \
113 void bnx2x_panic_dump(struct bnx2x *bp);
115 #ifdef BNX2X_STOP_ON_ERROR
116 #define bnx2x_panic() do { \
118 BNX2X_ERR("driver assert\n"); \
119 bnx2x_int_disable(bp); \
120 bnx2x_panic_dump(bp); \
123 #define bnx2x_panic() do { \
125 BNX2X_ERR("driver assert\n"); \
126 bnx2x_panic_dump(bp); \
130 #define bnx2x_mc_addr(ha) ((ha)->addr)
132 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
133 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
134 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
137 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
139 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
140 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
141 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
143 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
144 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
145 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
147 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
148 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
150 #define REG_RD_DMAE(bp, offset, valp, len32) \
152 bnx2x_read_dmae(bp, offset, len32);\
153 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
156 #define REG_WR_DMAE(bp, offset, valp, len32) \
158 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
159 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
163 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
164 REG_WR_DMAE(bp, offset, valp, len32)
166 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
168 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
169 bnx2x_write_big_buf_wb(bp, addr, len32); \
172 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
173 offsetof(struct shmem_region, field))
174 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
175 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
177 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
178 offsetof(struct shmem2_region, field))
179 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
180 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
181 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
182 offsetof(struct mf_cfg, field))
184 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
185 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
186 MF_CFG_ADDR(bp, field), (val))
188 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
189 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
193 /* General SP events - stats query, cfc delete, etc */
194 #define HC_SP_INDEX_ETH_DEF_CONS 3
197 #define HC_SP_INDEX_EQ_CONS 7
200 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
201 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
205 * CLIDs below is a CLID for func 0, then the CLID for other
206 * functions will be calculated by the formula:
208 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
212 #define BNX2X_ISCSI_ETH_CL_ID 17
213 #define BNX2X_ISCSI_ETH_CID 17
215 /** Additional rings budgeting */
217 #define CNIC_CONTEXT_USE 1
219 #define CNIC_CONTEXT_USE 0
220 #endif /* BCM_CNIC */
222 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
223 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
232 DEFINE_DMA_UNMAP_ADDR(mapping);
239 /* Set on the first BD descriptor when there is a split BD */
240 #define BNX2X_TSO_SPLIT_BD (1<<0)
245 DEFINE_DMA_UNMAP_ADDR(mapping);
249 struct doorbell_set_prod data;
255 #define BCM_PAGE_SHIFT 12
256 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
257 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
258 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
260 #define PAGES_PER_SGE_SHIFT 0
261 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
262 #define SGE_PAGE_SIZE PAGE_SIZE
263 #define SGE_PAGE_SHIFT PAGE_SHIFT
264 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
266 /* SGE ring related macros */
267 #define NUM_RX_SGE_PAGES 2
268 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
269 #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
270 /* RX_SGE_CNT is promised to be a power of 2 */
271 #define RX_SGE_MASK (RX_SGE_CNT - 1)
272 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
273 #define MAX_RX_SGE (NUM_RX_SGE - 1)
274 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
275 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
276 #define RX_SGE(x) ((x) & MAX_RX_SGE)
278 /* SGE producer mask related macros */
279 /* Number of bits in one sge_mask array element */
280 #define RX_SGE_MASK_ELEM_SZ 64
281 #define RX_SGE_MASK_ELEM_SHIFT 6
282 #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
284 /* Creates a bitmask of all ones in less significant bits.
285 idx - index of the most significant bit in the created mask */
286 #define RX_SGE_ONES_MASK(idx) \
287 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
288 #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
290 /* Number of u64 elements in SGE mask array */
291 #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
293 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
294 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
296 union host_hc_status_block {
297 /* pointer to fp status block e1x */
298 struct host_hc_status_block_e1x *e1x_sb;
301 struct bnx2x_fastpath {
303 struct napi_struct napi;
304 union host_hc_status_block status_blk;
305 /* chip independed shortcuts into sb structure */
306 __le16 *sb_index_values;
307 __le16 *sb_running_index;
308 /* chip independed shortcut into rx_prods_offset memory */
309 u32 ustorm_rx_prods_offset;
311 dma_addr_t status_blk_mapping;
313 struct sw_tx_bd *tx_buf_ring;
315 union eth_tx_bd_types *tx_desc_ring;
316 dma_addr_t tx_desc_mapping;
318 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
319 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
321 struct eth_rx_bd *rx_desc_ring;
322 dma_addr_t rx_desc_mapping;
324 union eth_rx_cqe *rx_comp_ring;
325 dma_addr_t rx_comp_mapping;
328 struct eth_rx_sge *rx_sge_ring;
329 dma_addr_t rx_sge_mapping;
331 u64 sge_mask[RX_SGE_MASK_LEN];
334 #define BNX2X_FP_STATE_CLOSED 0
335 #define BNX2X_FP_STATE_IRQ 0x80000
336 #define BNX2X_FP_STATE_OPENING 0x90000
337 #define BNX2X_FP_STATE_OPEN 0xa0000
338 #define BNX2X_FP_STATE_HALTING 0xb0000
339 #define BNX2X_FP_STATE_HALTED 0xc0000
340 #define BNX2X_FP_STATE_TERMINATING 0xd0000
341 #define BNX2X_FP_STATE_TERMINATED 0xe0000
343 u8 index; /* number in fp array */
344 u8 cl_id; /* eth client id */
346 u8 fw_sb_id; /* status block number in FW */
347 u8 igu_sb_id; /* status block number in HW */
365 /* The last maximal completed SGE */
371 unsigned long tx_pkt,
376 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
377 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
378 #define BNX2X_TPA_START 1
379 #define BNX2X_TPA_STOP 2
381 #ifdef BNX2X_STOP_ON_ERROR
385 struct tstorm_per_client_stats old_tclient;
386 struct ustorm_per_client_stats old_uclient;
387 struct xstorm_per_client_stats old_xclient;
388 struct bnx2x_eth_q_stats eth_q_stats;
390 /* The size is calculated using the following:
391 sizeof name field from netdev structure +
393 4 (for the digits and to make it DWORD aligned) */
394 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
395 char name[FP_NAME_SIZE];
396 struct bnx2x *bp; /* parent */
399 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
403 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
404 #define RX_COPY_THRESH 92
406 #define NUM_TX_RINGS 16
407 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
408 #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
409 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
410 #define MAX_TX_BD (NUM_TX_BD - 1)
411 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
412 #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL
413 #define INIT_TX_RING_SIZE MAX_TX_AVAIL
414 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
415 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
416 #define TX_BD(x) ((x) & MAX_TX_BD)
417 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
419 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
420 #define NUM_RX_RINGS 8
421 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
422 #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
423 #define RX_DESC_MASK (RX_DESC_CNT - 1)
424 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
425 #define MAX_RX_BD (NUM_RX_BD - 1)
426 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
427 #define MIN_RX_AVAIL 128
428 #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL
429 #define INIT_RX_RING_SIZE MAX_RX_AVAIL
430 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
431 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
432 #define RX_BD(x) ((x) & MAX_RX_BD)
434 /* As long as CQE is 4 times bigger than BD entry we have to allocate
435 4 times more pages for CQ ring in order to keep it balanced with
437 #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
438 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
439 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
440 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
441 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
442 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
443 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
444 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
445 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
448 /* This is needed for determining of last_max */
449 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
451 #define __SGE_MASK_SET_BIT(el, bit) \
453 el = ((el) | ((u64)0x1 << (bit))); \
456 #define __SGE_MASK_CLEAR_BIT(el, bit) \
458 el = ((el) & (~((u64)0x1 << (bit)))); \
461 #define SGE_MASK_SET_BIT(fp, idx) \
462 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
463 ((idx) & RX_SGE_MASK_ELEM_MASK))
465 #define SGE_MASK_CLEAR_BIT(fp, idx) \
466 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
467 ((idx) & RX_SGE_MASK_ELEM_MASK))
470 /* used on a CID received from the HW */
471 #define SW_CID(x) (le32_to_cpu(x) & \
472 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
473 #define CQE_CMD(x) (le32_to_cpu(x) >> \
474 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
476 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
477 le32_to_cpu((bd)->addr_lo))
478 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
480 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
481 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
482 #define DPM_TRIGER_TYPE 0x40
483 #define DOORBELL(bp, cid, val) \
485 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
490 /* TX CSUM helpers */
491 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
493 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
496 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
499 #define XMIT_CSUM_V4 0x1
500 #define XMIT_CSUM_V6 0x2
501 #define XMIT_CSUM_TCP 0x4
502 #define XMIT_GSO_V4 0x8
503 #define XMIT_GSO_V6 0x10
505 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
506 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
509 /* stuff added to make the code fit 80Col */
511 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
513 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
514 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
515 #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
516 (TPA_TYPE_START | TPA_TYPE_END))
518 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
520 #define BNX2X_IP_CSUM_ERR(cqe) \
521 (!((cqe)->fast_path_cqe.status_flags & \
522 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
523 ((cqe)->fast_path_cqe.type_error_flags & \
524 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
526 #define BNX2X_L4_CSUM_ERR(cqe) \
527 (!((cqe)->fast_path_cqe.status_flags & \
528 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
529 ((cqe)->fast_path_cqe.type_error_flags & \
530 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
532 #define BNX2X_RX_CSUM_OK(cqe) \
533 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
535 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
536 (((le16_to_cpu(flags) & \
537 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
538 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
539 == PRS_FLAG_OVERETH_IPV4)
540 #define BNX2X_RX_SUM_FIX(cqe) \
541 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
543 #define U_SB_ETH_RX_CQ_INDEX 1
544 #define U_SB_ETH_RX_BD_INDEX 2
545 #define C_SB_ETH_TX_CQ_INDEX 5
547 #define BNX2X_RX_SB_INDEX \
548 (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX])
550 #define BNX2X_TX_SB_INDEX \
551 (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX])
553 /* end of fast path */
557 struct bnx2x_common {
560 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
561 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
563 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
564 #define CHIP_NUM_57710 0x164e
565 #define CHIP_NUM_57711 0x164f
566 #define CHIP_NUM_57711E 0x1650
567 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
568 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
569 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
570 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
572 #define IS_E1H_OFFSET CHIP_IS_E1H(bp)
574 #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
575 #define CHIP_REV_Ax 0x00000000
576 /* assume maximum 5 revisions */
577 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
578 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
579 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
580 !(CHIP_REV(bp) & 0x00001000))
581 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
582 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
583 (CHIP_REV(bp) & 0x00001000))
585 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
586 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
588 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
589 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
592 #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
593 #define NVRAM_TIMEOUT_COUNT 30000
594 #define NVRAM_PAGE_SIZE 256
605 #define INT_BLOCK_HC 0
607 #define CHIP_PORT_MODE_NONE 0x2
618 u32 link_config[LINK_CONFIG_SIZE];
620 u32 supported[LINK_CONFIG_SIZE];
621 /* link settings - missing defines */
622 #define SUPPORTED_2500baseX_Full (1 << 15)
624 u32 advertising[LINK_CONFIG_SIZE];
625 /* link settings - missing defines */
626 #define ADVERTISED_2500baseX_Full (1 << 15)
630 /* used to synchronize phy accesses */
631 struct mutex phy_mutex;
636 struct nig_stats old_nig_stats;
641 /* e1h Classification CAM line allocations */
645 CAM_MAX_PF_LINE = CAM_ISCSI_ETH_LINE
648 #define BNX2X_VF_ID_INVALID 0xFF
651 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
652 * control by the number of fast-path status blocks supported by the
653 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
654 * status block represents an independent interrupts context that can
655 * serve a regular L2 networking queue. However special L2 queues such
656 * as the FCoE queue do not require a FP-SB and other components like
657 * the CNIC may consume FP-SB reducing the number of possible L2 queues
659 * If the maximum number of FP-SB available is X then:
660 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
661 * regular L2 queues is Y=X-1
662 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
663 * c. If the FCoE L2 queue is supported the actual number of L2 queues
665 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
666 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
667 * FP interrupt context for the CNIC).
668 * e. The number of HW context (CID count) is always X or X+1 if FCoE
669 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
672 #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */
673 #define MAX_CONTEXT FP_SB_MAX_E1x
676 * cid_cnt paramter below refers to the value returned by
677 * 'bnx2x_get_l2_cid_count()' routine
681 * The number of FP context allocated by the driver == max number of regular
682 * L2 queues + 1 for the FCoE L2 queue
684 #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE)
687 struct eth_context eth;
691 /* CDU host DB constants */
692 #define CDU_ILT_PAGE_SZ_HW 3
693 #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */
694 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
697 #define CNIC_ISCSI_CID_MAX 256
698 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX)
699 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
702 #define QM_ILT_PAGE_SZ_HW 3
703 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */
704 #define QM_CID_ROUND 1024
707 /* TM (timers) host DB constants */
708 #define TM_ILT_PAGE_SZ_HW 2
709 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */
710 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
711 #define TM_CONN_NUM 1024
712 #define TM_ILT_SZ (8 * TM_CONN_NUM)
713 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
715 /* SRC (Searcher) host DB constants */
716 #define SRC_ILT_PAGE_SZ_HW 3
717 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */
718 #define SRC_HASH_BITS 10
719 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
720 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
721 #define SRC_T2_SZ SRC_ILT_SZ
722 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
727 /* DMA memory not used in fastpath */
728 struct bnx2x_slowpath {
729 struct eth_stats_query fw_stats;
730 struct mac_configuration_cmd mac_config;
731 struct mac_configuration_cmd mcast_config;
732 struct client_init_ramrod_data client_init_data;
734 /* used by dmae command executer */
735 struct dmae_command dmae[MAX_DMAE_C];
738 union mac_stats mac_stats;
739 struct nig_stats nig_stats;
740 struct host_port_stats port_stats;
741 struct host_func_stats func_stats;
742 struct host_func_stats func_stats_base;
748 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
749 #define bnx2x_sp_mapping(bp, var) \
750 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
753 /* attn group wiring */
754 #define MAX_DYNAMIC_ATTN_GRPS 8
769 union cdu_context *vcxt;
770 dma_addr_t cxt_mapping;
781 } bnx2x_recovery_state_t;
784 * Event queue (EQ or event ring) MC hsi
785 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
787 #define NUM_EQ_PAGES 1
788 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
789 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
790 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
791 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
792 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
794 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
795 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
796 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
798 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
799 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
801 #define BNX2X_EQ_INDEX \
802 (&bp->def_status_blk->sp_sb.\
803 index_values[HC_SP_INDEX_EQ_CONS])
806 /* Fields used in the tx and intr/napi performance paths
807 * are grouped together in the beginning of the structure
809 struct bnx2x_fastpath *fp;
810 void __iomem *regview;
811 void __iomem *doorbells;
814 struct net_device *dev;
815 struct pci_dev *pdev;
818 #define IRO (bp->iro_arr)
822 bnx2x_recovery_state_t recovery_state;
824 struct msix_entry *msix_table;
825 #define INT_MODE_INTx 1
826 #define INT_MODE_MSI 2
831 struct vlan_group *vlgrp;
836 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
837 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
838 #define ETH_MIN_PACKET_SIZE 60
839 #define ETH_MAX_PACKET_SIZE 1500
840 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
842 /* Max supported alignment is 256 (8 shift) */
843 #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
845 #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
846 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
848 struct host_sp_status_block *def_status_blk;
849 #define DEF_SB_IGU_ID 16
850 #define DEF_SB_ID HC_SP_SB_ID
854 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
858 dma_addr_t spq_mapping;
860 struct eth_spe *spq_prod_bd;
861 struct eth_spe *spq_last_bd;
863 atomic_t spq_left; /* serialize spq */
864 /* used to synchronize spq accesses */
868 union event_ring_elem *eq_ring;
869 dma_addr_t eq_mapping;
874 /* Flags for marking that there is a STAT_QUERY or
875 SET_MAC ramrod pending */
879 /* End of fields used in the performance code paths */
886 #define PCI_32BIT_FLAG 2
887 #define ONE_PORT_FLAG 4
888 #define NO_WOL_FLAG 8
889 #define USING_DAC_FLAG 0x10
890 #define USING_MSIX_FLAG 0x20
891 #define USING_MSI_FLAG 0x40
892 #define TPA_ENABLE_FLAG 0x80
893 #define NO_MCP_FLAG 0x100
894 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
895 #define HW_VLAN_TX_FLAG 0x400
896 #define HW_VLAN_RX_FLAG 0x800
897 #define MF_FUNC_DIS 0x1000
902 #define BP_PORT(bp) (bp->func % PORT_MAX)
903 #define BP_FUNC(bp) (bp->func)
904 #define BP_E1HVN(bp) (bp->func >> 1)
905 #define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
908 #define BCM_CNIC_CID_START 16
909 #define BCM_ISCSI_ETH_CL_ID 17
916 struct delayed_work sp_task;
917 struct delayed_work reset_task;
918 struct timer_list timer;
919 int current_interval;
922 u16 fw_drv_pulse_wr_seq;
925 struct link_params link_params;
926 struct link_vars link_vars;
927 struct mdio_if_info mdio;
929 struct bnx2x_common common;
930 struct bnx2x_port port;
932 struct cmng_struct_per_port cmng;
938 #define IS_MF(bp) (bp->mf_mode != 0)
944 u16 tx_quick_cons_trip_int;
945 u16 tx_quick_cons_trip;
949 u16 rx_quick_cons_trip_int;
950 u16 rx_quick_cons_trip;
953 /* Maximal coalescing timeout in us */
954 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
959 #define BNX2X_STATE_CLOSED 0
960 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
961 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
962 #define BNX2X_STATE_OPEN 0x3000
963 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
964 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
965 #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
966 #define BNX2X_STATE_FUNC_STARTED 0x7000
967 #define BNX2X_STATE_DIAG 0xe000
968 #define BNX2X_STATE_ERROR 0xf000
975 struct tstorm_eth_mac_filter_config mac_filters;
976 #define BNX2X_ACCEPT_NONE 0x0000
977 #define BNX2X_ACCEPT_UNICAST 0x0001
978 #define BNX2X_ACCEPT_MULTICAST 0x0002
979 #define BNX2X_ACCEPT_ALL_UNICAST 0x0004
980 #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008
981 #define BNX2X_ACCEPT_BROADCAST 0x0010
982 #define BNX2X_PROMISCUOUS_MODE 0x10000
985 #define BNX2X_RX_MODE_NONE 0
986 #define BNX2X_RX_MODE_NORMAL 1
987 #define BNX2X_RX_MODE_ALLMULTI 2
988 #define BNX2X_RX_MODE_PROMISC 3
989 #define BNX2X_MAX_MULTICAST 64
990 #define BNX2X_MAX_EMUL_MULTI 16
995 dma_addr_t def_status_blk_mapping;
997 struct bnx2x_slowpath *slowpath;
998 dma_addr_t slowpath_mapping;
999 struct hw_context context;
1001 struct bnx2x_ilt *ilt;
1002 #define BP_ILT(bp) ((bp)->ilt)
1003 #define ILT_MAX_LINES 128
1006 #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \
1008 #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT))
1016 #define BNX2X_CNIC_FLAG_MAC_SET 1
1019 dma_addr_t t1_mapping;
1021 dma_addr_t t2_mapping;
1023 dma_addr_t timers_mapping;
1025 dma_addr_t qm_mapping;
1026 struct cnic_ops *cnic_ops;
1029 struct cnic_eth_dev cnic_eth_dev;
1030 union host_hc_status_block cnic_sb;
1031 dma_addr_t cnic_sb_mapping;
1032 #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp))
1033 #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb)
1034 struct eth_spe *cnic_kwq;
1035 struct eth_spe *cnic_kwq_prod;
1036 struct eth_spe *cnic_kwq_cons;
1037 struct eth_spe *cnic_kwq_last;
1038 u16 cnic_kwq_pending;
1039 u16 cnic_spq_pending;
1040 struct mutex cnic_mutex;
1045 /* used to synchronize dmae accesses */
1046 struct mutex dmae_mutex;
1048 /* used to protect the FW mail box */
1049 struct mutex fw_mb_mutex;
1051 /* used to synchronize stats collecting */
1054 /* used for synchronization of concurrent threads statistics handling */
1055 spinlock_t stats_lock;
1057 /* used by dmae command loader */
1058 struct dmae_command stats_dmae;
1062 struct bnx2x_eth_stats eth_stats;
1064 struct z_stream_s *strm;
1066 dma_addr_t gunzip_mapping;
1068 #define FW_BUF_SIZE 0x8000
1069 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1070 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1071 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1073 struct raw_op *init_ops;
1074 /* Init blocks offsets inside init_ops */
1075 u16 *init_ops_offsets;
1076 /* Data blob - has 32 bit granularity */
1078 /* Zipped PRAM blobs - raw data */
1079 const u8 *tsem_int_table_data;
1080 const u8 *tsem_pram_data;
1081 const u8 *usem_int_table_data;
1082 const u8 *usem_pram_data;
1083 const u8 *xsem_int_table_data;
1084 const u8 *xsem_pram_data;
1085 const u8 *csem_int_table_data;
1086 const u8 *csem_pram_data;
1087 #define INIT_OPS(bp) (bp->init_ops)
1088 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1089 #define INIT_DATA(bp) (bp->init_data)
1090 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1091 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1092 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1093 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1094 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1095 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1096 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1097 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1100 const struct firmware *firmware;
1104 * Init queue/func interface
1106 /* queue init flags */
1107 #define QUEUE_FLG_TPA 0x0001
1108 #define QUEUE_FLG_CACHE_ALIGN 0x0002
1109 #define QUEUE_FLG_STATS 0x0004
1110 #define QUEUE_FLG_OV 0x0008
1111 #define QUEUE_FLG_VLAN 0x0010
1112 #define QUEUE_FLG_COS 0x0020
1113 #define QUEUE_FLG_HC 0x0040
1114 #define QUEUE_FLG_DHC 0x0080
1115 #define QUEUE_FLG_OOO 0x0100
1117 #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR
1118 #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR
1119 #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0
1120 #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR
1124 /* rss capabilities */
1125 #define RSS_IPV4_CAP 0x0001
1126 #define RSS_IPV4_TCP_CAP 0x0002
1127 #define RSS_IPV6_CAP 0x0004
1128 #define RSS_IPV6_TCP_CAP 0x0008
1130 #define BNX2X_MAX_QUEUES(bp) (IS_MF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \
1132 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1133 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1136 #define RSS_IPV4_CAP_MASK \
1137 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1139 #define RSS_IPV4_TCP_CAP_MASK \
1140 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1142 #define RSS_IPV6_CAP_MASK \
1143 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1145 #define RSS_IPV6_TCP_CAP_MASK \
1146 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1148 /* func init flags */
1149 #define FUNC_FLG_RSS 0x0001
1150 #define FUNC_FLG_STATS 0x0002
1151 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1152 #define FUNC_FLG_TPA 0x0008
1153 #define FUNC_FLG_SPQ 0x0010
1154 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1156 #define FUNC_CONFIG(flgs) ((flgs) & (FUNC_FLG_RSS | FUNC_FLG_TPA | \
1159 struct rxq_pause_params {
1164 u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */
1165 u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */
1169 struct bnx2x_rxq_init_params {
1171 struct eth_context *cxt;
1174 dma_addr_t dscr_map;
1177 dma_addr_t rcq_np_map;
1188 /* valid iff QUEUE_FLG_STATS */
1191 /* valid iff QUEUE_FLG_TPA */
1196 /* valid iff QUEUE_FLG_CACHE_ALIGN */
1202 /* desired interrupts per sec. valid iff QUEUE_FLG_HC */
1206 struct bnx2x_txq_init_params {
1208 struct eth_context *cxt;
1211 dma_addr_t dscr_map;
1216 u8 cos; /* valid iff QUEUE_FLG_COS */
1217 u16 stat_id; /* valid iff QUEUE_FLG_STATS */
1220 u16 hc_rate; /* desired interrupts per sec.*/
1221 /* valid iff QUEUE_FLG_HC */
1225 struct bnx2x_client_ramrod_params {
1232 #define CLIENT_IS_LEADING_RSS 0x02
1236 struct bnx2x_client_init_params {
1237 struct rxq_pause_params pause;
1238 struct bnx2x_rxq_init_params rxq_params;
1239 struct bnx2x_txq_init_params txq_params;
1240 struct bnx2x_client_ramrod_params ramrod_params;
1243 struct bnx2x_rss_params {
1249 struct bnx2x_func_init_params {
1252 struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */
1255 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1256 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1259 u16 func_id; /* abs fid */
1261 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1264 #define for_each_queue(bp, var) \
1265 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
1266 #define for_each_nondefault_queue(bp, var) \
1267 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
1270 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1271 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1273 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1274 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1275 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1276 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
1277 void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1278 void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1280 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1281 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1282 u32 data_hi, u32 data_lo, int common);
1283 void bnx2x_update_coalesce(struct bnx2x *bp);
1284 int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
1285 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1291 val = REG_RD(bp, reg);
1292 if (val == expected)
1301 #define BNX2X_ILT_ZALLOC(x, y, size) \
1303 x = pci_alloc_consistent(bp->pdev, size, y); \
1305 memset(x, 0, size); \
1308 #define BNX2X_ILT_FREE(x, y, size) \
1311 pci_free_consistent(bp->pdev, size, x, y); \
1317 #define ILOG2(x) (ilog2((x)))
1319 #define ILT_NUM_PAGE_ENTRIES (3072)
1320 /* In 57710/11 we use whole table since we have 8 func
1322 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1324 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1326 * the phys address is shifted right 12 bits and has an added
1327 * 1=valid bit added to the 53rd bit
1328 * then since this is a wide register(TM)
1329 * we split it into two 32 bit writes
1331 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1332 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1335 /* load/unload mode */
1336 #define LOAD_NORMAL 0
1339 #define UNLOAD_NORMAL 0
1340 #define UNLOAD_CLOSE 1
1341 #define UNLOAD_RECOVERY 2
1344 /* DMAE command defines */
1345 #define DMAE_CMD_SRC_PCI 0
1346 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1348 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1349 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1351 #define DMAE_CMD_C_DST_PCI 0
1352 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1354 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1356 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1357 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1358 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1359 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1361 #define DMAE_CMD_PORT_0 0
1362 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1364 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1365 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1366 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1368 #define DMAE_LEN32_RD_MAX 0x80
1369 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1371 #define DMAE_COMP_VAL 0xe0d0d0ae
1373 #define MAX_DMAE_C_PER_PORT 8
1374 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1376 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1380 /* PCIE link and speed */
1381 #define PCICFG_LINK_WIDTH 0x1f00000
1382 #define PCICFG_LINK_WIDTH_SHIFT 20
1383 #define PCICFG_LINK_SPEED 0xf0000
1384 #define PCICFG_LINK_SPEED_SHIFT 16
1387 #define BNX2X_NUM_TESTS 7
1389 #define BNX2X_PHY_LOOPBACK 0
1390 #define BNX2X_MAC_LOOPBACK 1
1391 #define BNX2X_PHY_LOOPBACK_FAILED 1
1392 #define BNX2X_MAC_LOOPBACK_FAILED 2
1393 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1394 BNX2X_PHY_LOOPBACK_FAILED)
1397 #define STROM_ASSERT_ARRAY_SIZE 50
1400 /* must be used on a CID before placing it on a HW ring */
1401 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1402 (BP_E1HVN(bp) << 17) | (x))
1404 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1405 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1409 #define MAX_SPQ_PENDING 8
1413 derived from lab experiments, and not from system spec calculations !!! */
1414 #define DEF_MIN_RATE 100
1415 /* resolution of the rate shaping timer - 100 usec */
1416 #define RS_PERIODIC_TIMEOUT_USEC 100
1417 /* resolution of fairness algorithm in usecs -
1418 coefficient for calculating the actual t fair */
1419 #define T_FAIR_COEF 10000000
1420 /* number of bytes in single QM arbitration cycle -
1421 coefficient for calculating the fairness timer */
1422 #define QM_ARB_BYTES 40000
1426 #define ATTN_NIG_FOR_FUNC (1L << 8)
1427 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1428 #define GPIO_2_FUNC (1L << 10)
1429 #define GPIO_3_FUNC (1L << 11)
1430 #define GPIO_4_FUNC (1L << 12)
1431 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1432 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1433 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1434 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1435 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1436 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1438 #define ATTN_HARD_WIRED_MASK 0xff00
1439 #define ATTENTION_ID 4
1442 /* stuff added to make the code fit 80Col */
1444 #define BNX2X_PMF_LINK_ASSERT \
1445 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1447 #define BNX2X_MC_ASSERT_BITS \
1448 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1449 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1450 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1451 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1453 #define BNX2X_MCP_ASSERT \
1454 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1456 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1457 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1458 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1459 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1460 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1461 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1462 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1464 #define HW_INTERRUT_ASSERT_SET_0 \
1465 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1466 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1467 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1468 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1469 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1470 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1471 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1472 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1473 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1474 #define HW_INTERRUT_ASSERT_SET_1 \
1475 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1476 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1477 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1478 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1479 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1480 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1481 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1482 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1483 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1484 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1485 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1486 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
1487 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1488 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1489 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1490 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1491 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
1492 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1493 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1494 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1495 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1496 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1497 #define HW_INTERRUT_ASSERT_SET_2 \
1498 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1499 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1500 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1501 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1502 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1503 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1504 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1505 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1506 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1507 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1508 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1509 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1511 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1512 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1513 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1514 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
1516 #define RSS_FLAGS(bp) \
1517 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1518 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1519 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1520 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1521 (bp->multi_mode << \
1522 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1523 #define MULTI_MASK 0x7f
1525 #define BNX2X_SP_DSB_INDEX \
1526 (&bp->def_status_blk->sp_sb.\
1527 index_values[HC_SP_INDEX_ETH_DEF_CONS])
1528 #define SET_FLAG(value, mask, flag) \
1530 (value) &= ~(mask);\
1531 (value) |= ((flag) << (mask##_SHIFT));\
1534 #define GET_FLAG(value, mask) \
1535 (((value) &= (mask)) >> (mask##_SHIFT))
1537 #define CAM_IS_INVALID(x) \
1538 (GET_FLAG(x.flags, \
1539 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
1540 (T_ETH_MAC_COMMAND_INVALIDATE))
1542 #define CAM_INVALIDATE(x) \
1543 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1546 /* Number of u32 elements in MC hash array */
1547 #define MC_HASH_SIZE 8
1548 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1549 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
1552 #ifndef PXP2_REG_PXP2_INT_STS
1553 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1556 #define BNX2X_VPD_LEN 128
1557 #define VENDOR_ID_LEN 4
1559 /* Congestion management fairness mode */
1560 #define CMNG_FNS_NONE 0
1561 #define CMNG_FNS_MINMAX 1
1563 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
1564 #define HC_SEG_ACCESS_ATTN 4
1565 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
1568 #define BNX2X_EXTERN
1570 #define BNX2X_EXTERN extern
1573 BNX2X_EXTERN int load_count[3]; /* 0-common, 1-port0, 2-port1 */
1575 /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1577 extern void bnx2x_set_ethtool_ops(struct net_device *netdev);
1579 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1581 #define WAIT_RAMROD_POLL 0x01
1582 #define WAIT_RAMROD_COMMON 0x02
1584 int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
1585 int *state_p, int flags);
1586 #endif /* bnx2x.h */