1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
7 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
9 * Add Programmable Multibit ECC support for various AT91 SoC
10 * (C) Copyright 2012 ATMEL, Hong Xu
16 #include <asm/arch/gpio.h>
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <linux/bug.h>
24 #include <linux/mtd/nand_ecc.h>
26 #ifdef CONFIG_ATMEL_NAND_HWECC
28 /* Register access macros */
29 #define ecc_readl(add, reg) \
30 readl(add + ATMEL_ECC_##reg)
31 #define ecc_writel(add, reg, value) \
32 writel((value), add + ATMEL_ECC_##reg)
34 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
36 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
38 #ifdef CONFIG_SPL_BUILD
39 #undef CONFIG_SYS_NAND_ONFI_DETECTION
42 struct atmel_nand_host {
43 struct pmecc_regs __iomem *pmecc;
44 struct pmecc_errloc_regs __iomem *pmerrloc;
45 void __iomem *pmecc_rom_base;
48 u16 pmecc_sector_size;
49 u32 pmecc_index_table_offset;
52 int pmecc_bytes_per_sector;
53 int pmecc_sector_number;
54 int pmecc_degree; /* Degree of remainders */
55 int pmecc_cw_len; /* Length of codeword */
57 /* lookup table for alpha_to and index_of */
58 void __iomem *pmecc_alpha_to;
59 void __iomem *pmecc_index_of;
61 /* data for pmecc computation */
63 int16_t *pmecc_partial_syn;
65 int16_t *pmecc_lmu; /* polynomal order */
71 static struct atmel_nand_host pmecc_host;
72 static struct nand_ecclayout atmel_pmecc_oobinfo;
75 * Return number of ecc bytes per sector according to sector size and
76 * correction capability
78 * Following table shows what at91 PMECC supported:
79 * Correction Capability Sector_512_bytes Sector_1024_bytes
80 * ===================== ================ =================
81 * 2-bits 4-bytes 4-bytes
82 * 4-bits 7-bytes 7-bytes
83 * 8-bits 13-bytes 14-bytes
84 * 12-bits 20-bytes 21-bytes
85 * 24-bits 39-bytes 42-bytes
86 * 32-bits 52-bytes 56-bytes
88 static int pmecc_get_ecc_bytes(int cap, int sector_size)
90 int m = 12 + sector_size / 512;
91 return (m * cap + 7) / 8;
94 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
95 int oobsize, int ecc_len)
99 layout->eccbytes = ecc_len;
101 /* ECC will occupy the last ecc_len bytes continuously */
102 for (i = 0; i < ecc_len; i++)
103 layout->eccpos[i] = oobsize - ecc_len + i;
105 layout->oobfree[0].offset = 2;
106 layout->oobfree[0].length =
107 oobsize - ecc_len - layout->oobfree[0].offset;
110 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
114 table_size = host->pmecc_sector_size == 512 ?
115 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
117 /* the ALPHA lookup table is right behind the INDEX lookup table. */
118 return host->pmecc_rom_base + host->pmecc_index_table_offset +
119 table_size * sizeof(int16_t);
122 static void pmecc_data_free(struct atmel_nand_host *host)
124 free(host->pmecc_partial_syn);
125 free(host->pmecc_si);
126 free(host->pmecc_lmu);
127 free(host->pmecc_smu);
128 free(host->pmecc_mu);
129 free(host->pmecc_dmu);
130 free(host->pmecc_delta);
133 static int pmecc_data_alloc(struct atmel_nand_host *host)
135 const int cap = host->pmecc_corr_cap;
138 size = (2 * cap + 1) * sizeof(int16_t);
139 host->pmecc_partial_syn = malloc(size);
140 host->pmecc_si = malloc(size);
141 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
142 host->pmecc_smu = malloc((cap + 2) * size);
144 size = (cap + 1) * sizeof(int);
145 host->pmecc_mu = malloc(size);
146 host->pmecc_dmu = malloc(size);
147 host->pmecc_delta = malloc(size);
149 if (host->pmecc_partial_syn &&
159 pmecc_data_free(host);
164 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
166 struct nand_chip *nand_chip = mtd_to_nand(mtd);
167 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
171 /* Fill odd syndromes */
172 for (i = 0; i < host->pmecc_corr_cap; i++) {
173 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
177 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
181 static void pmecc_substitute(struct mtd_info *mtd)
183 struct nand_chip *nand_chip = mtd_to_nand(mtd);
184 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
185 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
186 int16_t __iomem *index_of = host->pmecc_index_of;
187 int16_t *partial_syn = host->pmecc_partial_syn;
188 const int cap = host->pmecc_corr_cap;
192 /* si[] is a table that holds the current syndrome value,
193 * an element of that table belongs to the field
197 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
199 /* Computation 2t syndromes based on S(x) */
201 for (i = 1; i < 2 * cap; i += 2) {
202 for (j = 0; j < host->pmecc_degree; j++) {
203 if (partial_syn[i] & (0x1 << j))
204 si[i] = readw(alpha_to + i * j) ^ si[i];
207 /* Even syndrome = (Odd syndrome) ** 2 */
208 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
214 tmp = readw(index_of + si[j]);
215 tmp = (tmp * 2) % host->pmecc_cw_len;
216 si[i] = readw(alpha_to + tmp);
222 * This function defines a Berlekamp iterative procedure for
223 * finding the value of the error location polynomial.
224 * The input is si[], initialize by pmecc_substitute().
225 * The output is smu[][].
227 * This function is written according to chip datasheet Chapter:
228 * Find the Error Location Polynomial Sigma(x) of Section:
229 * Programmable Multibit ECC Control (PMECC).
231 static void pmecc_get_sigma(struct mtd_info *mtd)
233 struct nand_chip *nand_chip = mtd_to_nand(mtd);
234 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
236 int16_t *lmu = host->pmecc_lmu;
237 int16_t *si = host->pmecc_si;
238 int *mu = host->pmecc_mu;
239 int *dmu = host->pmecc_dmu; /* Discrepancy */
240 int *delta = host->pmecc_delta; /* Delta order */
241 int cw_len = host->pmecc_cw_len;
242 const int16_t cap = host->pmecc_corr_cap;
243 const int num = 2 * cap + 1;
244 int16_t __iomem *index_of = host->pmecc_index_of;
245 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
247 uint32_t dmu_0_count, tmp;
248 int16_t *smu = host->pmecc_smu;
250 /* index of largest delta */
255 /* Init the Sigma(x) */
256 memset(smu, 0, sizeof(int16_t) * num * (cap + 2));
267 /* discrepancy set to 1 */
269 /* polynom order set to 0 */
271 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
278 /* Sigma(x) set to 1 */
281 /* discrepancy set to S1 */
284 /* polynom order set to 0 */
287 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
290 for (i = 1; i <= cap; i++) {
292 /* Begin Computing Sigma (Mu+1) and L(mu) */
293 /* check if discrepancy is set to 0 */
297 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
298 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
303 if (dmu_0_count == tmp) {
304 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
305 smu[(cap + 1) * num + j] =
308 lmu[cap + 1] = lmu[i];
313 for (j = 0; j <= lmu[i] >> 1; j++)
314 smu[(i + 1) * num + j] = smu[i * num + j];
316 /* copy previous polynom order to the next */
321 /* find largest delta with dmu != 0 */
322 for (j = 0; j < i; j++) {
323 if ((dmu[j]) && (delta[j] > largest)) {
329 /* compute difference */
330 diff = (mu[i] - mu[ro]);
332 /* Compute degree of the new smu polynomial */
333 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
336 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
338 /* Init smu[i+1] with 0 */
339 for (k = 0; k < num; k++)
340 smu[(i + 1) * num + k] = 0;
342 /* Compute smu[i+1] */
343 for (k = 0; k <= lmu[ro] >> 1; k++) {
346 if (!(smu[ro * num + k] && dmu[i]))
348 a = readw(index_of + dmu[i]);
349 b = readw(index_of + dmu[ro]);
350 c = readw(index_of + smu[ro * num + k]);
351 tmp = a + (cw_len - b) + c;
352 a = readw(alpha_to + tmp % cw_len);
353 smu[(i + 1) * num + (k + diff)] = a;
356 for (k = 0; k <= lmu[i] >> 1; k++)
357 smu[(i + 1) * num + k] ^= smu[i * num + k];
360 /* End Computing Sigma (Mu+1) and L(mu) */
361 /* In either case compute delta */
362 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
364 /* Do not compute discrepancy for the last iteration */
368 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
371 dmu[i + 1] = si[tmp + 3];
372 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
375 smu[(i + 1) * num + k]);
376 b = si[2 * (i - 1) + 3 - k];
377 c = readw(index_of + b);
380 dmu[i + 1] = readw(alpha_to + tmp) ^
387 static int pmecc_err_location(struct mtd_info *mtd)
389 struct nand_chip *nand_chip = mtd_to_nand(mtd);
390 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
391 const int cap = host->pmecc_corr_cap;
392 const int num = 2 * cap + 1;
393 int sector_size = host->pmecc_sector_size;
394 int err_nbr = 0; /* number of error */
395 int roots_nbr; /* number of roots */
398 int16_t *smu = host->pmecc_smu;
399 int timeout = PMECC_MAX_TIMEOUT_US;
401 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
403 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
404 pmecc_writel(host->pmerrloc, sigma[i],
405 smu[(cap + 1) * num + i]);
409 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
410 if (sector_size == 1024)
411 val |= PMERRLOC_ELCFG_SECTOR_1024;
413 pmecc_writel(host->pmerrloc, elcfg, val);
414 pmecc_writel(host->pmerrloc, elen,
415 sector_size * 8 + host->pmecc_degree * cap);
418 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
425 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
429 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
431 /* Number of roots == degree of smu hence <= cap */
432 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
435 /* Number of roots does not match the degree of smu
436 * unable to correct error */
440 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
441 int sector_num, int extra_bytes, int err_nbr)
443 struct nand_chip *nand_chip = mtd_to_nand(mtd);
444 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
446 int byte_pos, bit_pos, sector_size, pos;
450 sector_size = host->pmecc_sector_size;
453 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
457 if (byte_pos >= (sector_size + extra_bytes))
458 BUG(); /* should never happen */
460 if (byte_pos < sector_size) {
461 err_byte = *(buf + byte_pos);
462 *(buf + byte_pos) ^= (1 << bit_pos);
464 pos = sector_num * host->pmecc_sector_size + byte_pos;
465 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
466 pos, bit_pos, err_byte, *(buf + byte_pos));
468 /* Bit flip in OOB area */
469 tmp = sector_num * host->pmecc_bytes_per_sector
470 + (byte_pos - sector_size);
472 ecc[tmp] ^= (1 << bit_pos);
474 pos = tmp + nand_chip->ecc.layout->eccpos[0];
475 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
476 pos, bit_pos, err_byte, ecc[tmp]);
486 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
489 struct nand_chip *nand_chip = mtd_to_nand(mtd);
490 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
491 int i, err_nbr, eccbytes;
494 /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
495 if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
498 eccbytes = nand_chip->ecc.bytes;
499 for (i = 0; i < eccbytes; i++)
502 /* Erased page, return OK */
506 for (i = 0; i < host->pmecc_sector_number; i++) {
508 if (pmecc_stat & 0x1) {
509 buf_pos = buf + i * host->pmecc_sector_size;
511 pmecc_gen_syndrome(mtd, i);
512 pmecc_substitute(mtd);
513 pmecc_get_sigma(mtd);
515 err_nbr = pmecc_err_location(mtd);
517 dev_err(host->dev, "PMECC: Too many errors\n");
518 mtd->ecc_stats.failed++;
521 pmecc_correct_data(mtd, buf_pos, ecc, i,
522 host->pmecc_bytes_per_sector, err_nbr);
523 mtd->ecc_stats.corrected += err_nbr;
532 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
533 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
535 struct atmel_nand_host *host = nand_get_controller_data(chip);
536 int eccsize = chip->ecc.size;
537 uint8_t *oob = chip->oob_poi;
538 uint32_t *eccpos = chip->ecc.layout->eccpos;
540 int timeout = PMECC_MAX_TIMEOUT_US;
542 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
543 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
544 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
545 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
547 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
548 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
550 chip->read_buf(mtd, buf, eccsize);
551 chip->read_buf(mtd, oob, mtd->oobsize);
554 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
561 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
565 stat = pmecc_readl(host->pmecc, isr);
567 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
573 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
574 struct nand_chip *chip, const uint8_t *buf,
575 int oob_required, int page)
577 struct atmel_nand_host *host = nand_get_controller_data(chip);
578 uint32_t *eccpos = chip->ecc.layout->eccpos;
580 int timeout = PMECC_MAX_TIMEOUT_US;
582 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
583 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
585 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
586 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
588 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
589 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
591 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
594 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
601 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
605 for (i = 0; i < host->pmecc_sector_number; i++) {
606 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
609 pos = i * host->pmecc_bytes_per_sector + j;
610 chip->oob_poi[eccpos[pos]] =
611 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
614 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
619 static void atmel_pmecc_core_init(struct mtd_info *mtd)
621 struct nand_chip *nand_chip = mtd_to_nand(mtd);
622 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
624 struct nand_ecclayout *ecc_layout;
626 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
627 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
629 switch (host->pmecc_corr_cap) {
631 val = PMECC_CFG_BCH_ERR2;
634 val = PMECC_CFG_BCH_ERR4;
637 val = PMECC_CFG_BCH_ERR8;
640 val = PMECC_CFG_BCH_ERR12;
643 val = PMECC_CFG_BCH_ERR24;
646 val = PMECC_CFG_BCH_ERR32;
650 if (host->pmecc_sector_size == 512)
651 val |= PMECC_CFG_SECTOR512;
652 else if (host->pmecc_sector_size == 1024)
653 val |= PMECC_CFG_SECTOR1024;
655 switch (host->pmecc_sector_number) {
657 val |= PMECC_CFG_PAGE_1SECTOR;
660 val |= PMECC_CFG_PAGE_2SECTORS;
663 val |= PMECC_CFG_PAGE_4SECTORS;
666 val |= PMECC_CFG_PAGE_8SECTORS;
670 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
671 | PMECC_CFG_AUTO_DISABLE);
672 pmecc_writel(host->pmecc, cfg, val);
674 ecc_layout = nand_chip->ecc.layout;
675 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
676 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
677 pmecc_writel(host->pmecc, eaddr,
678 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
679 /* See datasheet about PMECC Clock Control Register */
680 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
681 pmecc_writel(host->pmecc, idr, 0xff);
682 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
685 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
687 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
688 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
689 * ONFI ECC parameters.
690 * @host: point to an atmel_nand_host structure.
691 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
692 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
693 * @chip: point to an nand_chip structure.
694 * @cap: store the ONFI ECC correct bits capbility
695 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
697 * Return 0 if success. otherwise return the error code.
699 static int pmecc_choose_ecc(struct atmel_nand_host *host,
700 struct nand_chip *chip,
701 int *cap, int *sector_size)
703 /* Get ECC requirement from ONFI parameters */
704 *cap = *sector_size = 0;
705 if (chip->onfi_version) {
706 *cap = chip->ecc_strength_ds;
707 *sector_size = chip->ecc_step_ds;
708 pr_debug("ONFI params, minimum required ECC: %d bits in %d bytes\n",
712 if (*cap == 0 && *sector_size == 0) {
713 /* Non-ONFI compliant */
714 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
719 /* If head file doesn't specify then use the one in ONFI parameters */
720 if (host->pmecc_corr_cap == 0) {
721 /* use the most fitable ecc bits (the near bigger one ) */
723 host->pmecc_corr_cap = 2;
725 host->pmecc_corr_cap = 4;
727 host->pmecc_corr_cap = 8;
729 host->pmecc_corr_cap = 12;
731 host->pmecc_corr_cap = 24;
733 #ifdef CONFIG_SAMA5D2
734 host->pmecc_corr_cap = 32;
736 host->pmecc_corr_cap = 24;
739 if (host->pmecc_sector_size == 0) {
740 /* use the most fitable sector size (the near smaller one ) */
741 if (*sector_size >= 1024)
742 host->pmecc_sector_size = 1024;
743 else if (*sector_size >= 512)
744 host->pmecc_sector_size = 512;
752 #if defined(NO_GALOIS_TABLE_IN_ROM)
753 static uint16_t *pmecc_galois_table;
754 static inline int deg(unsigned int poly)
756 /* polynomial degree is the most-significant bit index */
757 return fls(poly) - 1;
760 static int build_gf_tables(int mm, unsigned int poly,
761 int16_t *index_of, int16_t *alpha_to)
763 unsigned int i, x = 1;
764 const unsigned int k = 1 << deg(poly);
765 unsigned int nn = (1 << mm) - 1;
767 /* primitive polynomial must be of degree m */
771 for (i = 0; i < nn; i++) {
775 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
788 static uint16_t *create_lookup_table(int sector_size)
790 int degree = (sector_size == 512) ?
791 PMECC_GF_DIMENSION_13 :
792 PMECC_GF_DIMENSION_14;
793 unsigned int poly = (sector_size == 512) ?
794 PMECC_GF_13_PRIMITIVE_POLY :
795 PMECC_GF_14_PRIMITIVE_POLY;
796 int table_size = (sector_size == 512) ?
797 PMECC_INDEX_TABLE_SIZE_512 :
798 PMECC_INDEX_TABLE_SIZE_1024;
800 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
801 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
804 return (uint16_t *)addr;
808 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
809 struct mtd_info *mtd)
811 struct atmel_nand_host *host;
812 int cap, sector_size;
815 nand_set_controller_data(nand, host);
817 nand->ecc.mode = NAND_ECC_HW;
818 nand->ecc.calculate = NULL;
819 nand->ecc.correct = NULL;
820 nand->ecc.hwctl = NULL;
822 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
823 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
825 #ifdef CONFIG_PMECC_CAP
826 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
828 #ifdef CONFIG_PMECC_SECTOR_SIZE
829 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
831 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
832 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
835 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
836 dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
841 if (cap > host->pmecc_corr_cap)
842 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
843 host->pmecc_corr_cap, cap);
844 if (sector_size < host->pmecc_sector_size)
845 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
846 host->pmecc_sector_size, sector_size);
847 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
848 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
849 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
852 cap = host->pmecc_corr_cap;
853 sector_size = host->pmecc_sector_size;
855 /* TODO: need check whether cap & sector_size is validate */
856 #if defined(NO_GALOIS_TABLE_IN_ROM)
858 * As pmecc_rom_base is the begin of the gallois field table, So the
859 * index offset just set as 0.
861 host->pmecc_index_table_offset = 0;
863 if (host->pmecc_sector_size == 512)
864 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
866 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
869 pr_debug("Initialize PMECC params, cap: %d, sector: %d\n",
872 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
873 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
875 #if defined(NO_GALOIS_TABLE_IN_ROM)
876 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
877 if (!pmecc_galois_table) {
878 dev_err(host->dev, "out of memory\n");
882 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
884 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
887 /* ECC is calculated for the whole page (1 step) */
888 nand->ecc.size = mtd->writesize;
890 /* set ECC page size and oob layout */
891 switch (mtd->writesize) {
895 host->pmecc_degree = (sector_size == 512) ?
896 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
897 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
898 host->pmecc_sector_number = mtd->writesize / sector_size;
899 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
901 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
902 host->pmecc_index_of = host->pmecc_rom_base +
903 host->pmecc_index_table_offset;
906 nand->ecc.bytes = host->pmecc_bytes_per_sector *
907 host->pmecc_sector_number;
909 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
910 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
911 MTD_MAX_ECCPOS_ENTRIES_LARGE);
915 if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
916 dev_err(host->dev, "No room for ECC bytes\n");
919 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
922 nand->ecc.layout = &atmel_pmecc_oobinfo;
927 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
929 /* page size not handled by HW ECC */
930 /* switching back to soft ECC */
931 nand->ecc.mode = NAND_ECC_SOFT;
932 nand->ecc.read_page = NULL;
933 nand->ecc.postpad = 0;
934 nand->ecc.prepad = 0;
939 /* Allocate data for PMECC computation */
940 if (pmecc_data_alloc(host)) {
941 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
945 nand->options |= NAND_NO_SUBPAGE_WRITE;
946 nand->ecc.read_page = atmel_nand_pmecc_read_page;
947 nand->ecc.write_page = atmel_nand_pmecc_write_page;
948 nand->ecc.strength = cap;
950 /* Check the PMECC ip version */
951 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
952 dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
954 atmel_pmecc_core_init(mtd);
961 /* oob layout for large page size
962 * bad block info is on bytes 0 and 1
963 * the bytes have to be consecutives to avoid
964 * several NAND_CMD_RNDOUT during read
966 static struct nand_ecclayout atmel_oobinfo_large = {
968 .eccpos = {60, 61, 62, 63},
974 /* oob layout for small page size
975 * bad block info is on bytes 4 and 5
976 * the bytes have to be consecutives to avoid
977 * several NAND_CMD_RNDOUT during read
979 static struct nand_ecclayout atmel_oobinfo_small = {
981 .eccpos = {0, 1, 2, 3},
990 * function called after a write
992 * mtd: MTD block structure
993 * dat: raw data (unused)
994 * ecc_code: buffer for ECC
996 static int atmel_nand_calculate(struct mtd_info *mtd,
997 const u_char *dat, unsigned char *ecc_code)
999 unsigned int ecc_value;
1001 /* get the first 2 ECC bytes */
1002 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1004 ecc_code[0] = ecc_value & 0xFF;
1005 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1007 /* get the last 2 ECC bytes */
1008 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1010 ecc_code[2] = ecc_value & 0xFF;
1011 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1017 * HW ECC read page function
1019 * mtd: mtd info structure
1020 * chip: nand chip info structure
1021 * buf: buffer to store read data
1022 * oob_required: caller expects OOB data read to chip->oob_poi
1024 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1025 uint8_t *buf, int oob_required, int page)
1027 int eccsize = chip->ecc.size;
1028 int eccbytes = chip->ecc.bytes;
1029 uint32_t *eccpos = chip->ecc.layout->eccpos;
1031 uint8_t *oob = chip->oob_poi;
1036 chip->read_buf(mtd, p, eccsize);
1038 /* move to ECC position if needed */
1039 if (eccpos[0] != 0) {
1040 /* This only works on large pages
1041 * because the ECC controller waits for
1042 * NAND_CMD_RNDOUTSTART after the
1044 * anyway, for small pages, the eccpos[0] == 0
1046 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1047 mtd->writesize + eccpos[0], -1);
1050 /* the ECC controller needs to read the ECC just after the data */
1051 ecc_pos = oob + eccpos[0];
1052 chip->read_buf(mtd, ecc_pos, eccbytes);
1054 /* check if there's an error */
1055 stat = chip->ecc.correct(mtd, p, oob, NULL);
1058 mtd->ecc_stats.failed++;
1060 mtd->ecc_stats.corrected += stat;
1062 /* get back to oob start (end of page) */
1063 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1066 chip->read_buf(mtd, oob, mtd->oobsize);
1074 * function called after a read
1076 * mtd: MTD block structure
1077 * dat: raw data read from the chip
1078 * read_ecc: ECC from the chip (unused)
1081 * Detect and correct a 1 bit error for a page
1083 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1084 u_char *read_ecc, u_char *isnull)
1086 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1087 unsigned int ecc_status;
1088 unsigned int ecc_word, ecc_bit;
1090 /* get the status from the Status Register */
1091 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1093 /* if there's no error */
1094 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1097 /* get error bit offset (4 bits) */
1098 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1099 /* get word address (12 bits) */
1100 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1103 /* if there are multiple errors */
1104 if (ecc_status & ATMEL_ECC_MULERR) {
1105 /* check if it is a freshly erased block
1106 * (filled with 0xff) */
1107 if ((ecc_bit == ATMEL_ECC_BITADDR)
1108 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1109 /* the block has just been erased, return OK */
1112 /* it doesn't seems to be a freshly
1114 * We can't correct so many errors */
1115 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1116 " Unable to correct.\n");
1120 /* if there's a single bit error : we can correct it */
1121 if (ecc_status & ATMEL_ECC_ECCERR) {
1122 /* there's nothing much to do here.
1123 * the bit error is on the ECC itself.
1125 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1126 " Nothing to correct\n");
1130 dev_warn(host->dev, "atmel_nand : one bit error on data."
1131 " (word offset in the page :"
1132 " 0x%x bit offset : 0x%x)\n",
1134 /* correct the error */
1135 if (nand_chip->options & NAND_BUSWIDTH_16) {
1137 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1140 dat[ecc_word] ^= (1 << ecc_bit);
1142 dev_warn(host->dev, "atmel_nand : error corrected\n");
1147 * Enable HW ECC : unused on most chips
1149 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1153 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1155 nand->ecc.mode = NAND_ECC_HW;
1156 nand->ecc.calculate = atmel_nand_calculate;
1157 nand->ecc.correct = atmel_nand_correct;
1158 nand->ecc.hwctl = atmel_nand_hwctl;
1159 nand->ecc.read_page = atmel_nand_read_page;
1160 nand->ecc.bytes = 4;
1161 nand->ecc.strength = 4;
1163 if (nand->ecc.mode == NAND_ECC_HW) {
1164 /* ECC is calculated for the whole page (1 step) */
1165 nand->ecc.size = mtd->writesize;
1167 /* set ECC page size and oob layout */
1168 switch (mtd->writesize) {
1170 nand->ecc.layout = &atmel_oobinfo_small;
1171 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1172 ATMEL_ECC_PAGESIZE_528);
1175 nand->ecc.layout = &atmel_oobinfo_large;
1176 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1177 ATMEL_ECC_PAGESIZE_1056);
1180 nand->ecc.layout = &atmel_oobinfo_large;
1181 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1182 ATMEL_ECC_PAGESIZE_2112);
1185 nand->ecc.layout = &atmel_oobinfo_large;
1186 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1187 ATMEL_ECC_PAGESIZE_4224);
1190 /* page size not handled by HW ECC */
1191 /* switching back to soft ECC */
1192 nand->ecc.mode = NAND_ECC_SOFT;
1193 nand->ecc.calculate = NULL;
1194 nand->ecc.correct = NULL;
1195 nand->ecc.hwctl = NULL;
1196 nand->ecc.read_page = NULL;
1197 nand->ecc.postpad = 0;
1198 nand->ecc.prepad = 0;
1199 nand->ecc.bytes = 0;
1207 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1209 #endif /* CONFIG_ATMEL_NAND_HWECC */
1211 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1212 int cmd, unsigned int ctrl)
1214 struct nand_chip *this = mtd_to_nand(mtd);
1216 if (ctrl & NAND_CTRL_CHANGE) {
1217 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1218 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1219 | CONFIG_SYS_NAND_MASK_CLE);
1221 if (ctrl & NAND_CLE)
1222 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1223 if (ctrl & NAND_ALE)
1224 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1226 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1227 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1228 !(ctrl & NAND_NCE));
1230 this->IO_ADDR_W = (void *) IO_ADDR_W;
1233 if (cmd != NAND_CMD_NONE)
1234 writeb(cmd, this->IO_ADDR_W);
1237 #ifdef CONFIG_SYS_NAND_READY_PIN
1238 static int at91_nand_ready(struct mtd_info *mtd)
1240 return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1244 #ifdef CONFIG_SPL_BUILD
1245 /* The following code is for SPL */
1246 static struct mtd_info *mtd;
1247 static struct nand_chip nand_chip;
1249 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1251 struct nand_chip *this = mtd_to_nand(mtd);
1252 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1253 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1254 unsigned int ctrl) = this->cmd_ctrl;
1256 while (!this->dev_ready(mtd))
1259 if (cmd == NAND_CMD_READOOB) {
1260 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1261 cmd = NAND_CMD_READ0;
1264 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1266 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1269 hwctrl(mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1270 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1271 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1272 hwctrl(mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1273 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1274 hwctrl(mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1276 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1278 hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1279 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1281 while (!this->dev_ready(mtd))
1287 static int nand_is_bad_block(int block)
1289 struct nand_chip *this = mtd_to_nand(mtd);
1291 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1293 if (this->options & NAND_BUSWIDTH_16) {
1294 if (readw(this->IO_ADDR_R) != 0xffff)
1297 if (readb(this->IO_ADDR_R) != 0xff)
1304 #ifdef CONFIG_SPL_NAND_ECC
1305 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1306 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1307 CONFIG_SYS_NAND_ECCSIZE)
1308 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1310 static int nand_read_page(int block, int page, void *dst)
1312 struct nand_chip *this = mtd_to_nand(mtd);
1313 u_char ecc_calc[ECCTOTAL];
1314 u_char ecc_code[ECCTOTAL];
1315 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1316 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1317 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1318 int eccsteps = ECCSTEPS;
1321 nand_command(block, page, 0, NAND_CMD_READ0);
1323 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1324 if (this->ecc.mode != NAND_ECC_SOFT)
1325 this->ecc.hwctl(mtd, NAND_ECC_READ);
1326 this->read_buf(mtd, p, eccsize);
1327 this->ecc.calculate(mtd, p, &ecc_calc[i]);
1329 this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1331 for (i = 0; i < ECCTOTAL; i++)
1332 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1334 eccsteps = ECCSTEPS;
1337 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1338 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1343 int spl_nand_erase_one(int block, int page)
1345 struct nand_chip *this = mtd_to_nand(mtd);
1346 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1347 unsigned int ctrl) = this->cmd_ctrl;
1350 if (nand_chip.select_chip)
1351 nand_chip.select_chip(mtd, 0);
1353 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1354 hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1356 hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1357 hwctrl(mtd, ((page_addr >> 8) & 0xff),
1358 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1359 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1360 /* One more address cycle for devices > 128MiB */
1361 hwctrl(mtd, (page_addr >> 16) & 0x0f,
1362 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1364 hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1366 while (!this->dev_ready(mtd))
1374 static int nand_read_page(int block, int page, void *dst)
1376 struct nand_chip *this = mtd_to_nand(mtd);
1378 nand_command(block, page, 0, NAND_CMD_READ0);
1379 atmel_nand_pmecc_read_page(mtd, this, dst, 0, page);
1383 #endif /* CONFIG_SPL_NAND_ECC */
1385 int at91_nand_wait_ready(struct mtd_info *mtd)
1387 struct nand_chip *this = mtd_to_nand(mtd);
1389 udelay(this->chip_delay);
1394 int board_nand_init(struct nand_chip *nand)
1398 nand->ecc.mode = NAND_ECC_SOFT;
1399 #ifdef CONFIG_SYS_NAND_DBW_16
1400 nand->options = NAND_BUSWIDTH_16;
1401 nand->read_buf = nand_read_buf16;
1403 nand->read_buf = nand_read_buf;
1405 nand->cmd_ctrl = at91_nand_hwcontrol;
1406 #ifdef CONFIG_SYS_NAND_READY_PIN
1407 nand->dev_ready = at91_nand_ready;
1409 nand->dev_ready = at91_nand_wait_ready;
1411 nand->chip_delay = 20;
1412 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1413 nand->bbt_options |= NAND_BBT_USE_FLASH;
1416 #ifdef CONFIG_ATMEL_NAND_HWECC
1417 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1418 ret = atmel_pmecc_nand_init_params(nand, mtd);
1425 void nand_init(void)
1427 mtd = nand_to_mtd(&nand_chip);
1428 mtd->writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1429 mtd->oobsize = CONFIG_SYS_NAND_OOBSIZE;
1430 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1431 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1432 board_nand_init(&nand_chip);
1434 #ifdef CONFIG_SPL_NAND_ECC
1435 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1436 nand_chip.ecc.calculate = nand_calculate_ecc;
1437 nand_chip.ecc.correct = nand_correct_data;
1441 if (nand_chip.select_chip)
1442 nand_chip.select_chip(mtd, 0);
1445 void nand_deselect(void)
1447 if (nand_chip.select_chip)
1448 nand_chip.select_chip(mtd, -1);
1451 #include "nand_spl_loaders.c"
1455 #ifndef CONFIG_SYS_NAND_BASE_LIST
1456 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1458 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1459 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1461 int atmel_nand_chip_init(int devnum, ulong base_addr)
1464 struct nand_chip *nand = &nand_chip[devnum];
1465 struct mtd_info *mtd = nand_to_mtd(nand);
1467 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1469 #ifdef CONFIG_NAND_ECC_BCH
1470 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1472 nand->ecc.mode = NAND_ECC_SOFT;
1474 #ifdef CONFIG_SYS_NAND_DBW_16
1475 nand->options = NAND_BUSWIDTH_16;
1477 nand->cmd_ctrl = at91_nand_hwcontrol;
1478 #ifdef CONFIG_SYS_NAND_READY_PIN
1479 nand->dev_ready = at91_nand_ready;
1481 nand->chip_delay = 75;
1482 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1483 nand->bbt_options |= NAND_BBT_USE_FLASH;
1486 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1490 #ifdef CONFIG_ATMEL_NAND_HWECC
1491 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1492 ret = atmel_pmecc_nand_init_params(nand, mtd);
1494 ret = atmel_hwecc_nand_init_param(nand, mtd);
1500 ret = nand_scan_tail(mtd);
1502 nand_register(devnum, mtd);
1507 void board_nand_init(void)
1510 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1511 if (atmel_nand_chip_init(i, base_addr[i]))
1512 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1515 #endif /* CONFIG_SPL_BUILD */