5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/compatmac.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_oobinfo nand_oob_8 = {
56 .useecc = MTD_NANDECC_AUTOPLACE,
59 .oobfree = {{3, 2}, {6, 2}}
62 static struct nand_oobinfo nand_oob_16 = {
63 .useecc = MTD_NANDECC_AUTOPLACE,
65 .eccpos = {0, 1, 2, 3, 6, 7},
69 static struct nand_oobinfo nand_oob_64 = {
70 .useecc = MTD_NANDECC_AUTOPLACE,
73 40, 41, 42, 43, 44, 45, 46, 47,
74 48, 49, 50, 51, 52, 53, 54, 55,
75 56, 57, 58, 59, 60, 61, 62, 63},
79 /* This is used for padding purposes in nand_write_oob */
80 static uint8_t ffchars[] = {
81 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
82 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
83 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
84 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
85 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
86 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
87 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
88 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
91 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
92 size_t *retlen, const uint8_t *buf);
93 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 * For devices which display every fart in the system on a seperate LED. Is
98 * compiled away when LED support is disabled.
100 DEFINE_LED_TRIGGER(nand_led_trigger);
103 * nand_release_device - [GENERIC] release chip
104 * @mtd: MTD device structure
106 * Deselect, release chip lock and wake up anyone waiting on the device
108 static void nand_release_device(struct mtd_info *mtd)
110 struct nand_chip *chip = mtd->priv;
112 /* De-select the NAND device */
113 chip->select_chip(mtd, -1);
115 /* Release the controller and the chip */
116 spin_lock(&chip->controller->lock);
117 chip->controller->active = NULL;
118 chip->state = FL_READY;
119 wake_up(&chip->controller->wq);
120 spin_unlock(&chip->controller->lock);
124 * nand_read_byte - [DEFAULT] read one byte from the chip
125 * @mtd: MTD device structure
127 * Default read function for 8bit buswith
129 static uint8_t nand_read_byte(struct mtd_info *mtd)
131 struct nand_chip *chip = mtd->priv;
132 return readb(chip->IO_ADDR_R);
136 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
137 * @mtd: MTD device structure
139 * Default read function for 16bit buswith with
140 * endianess conversion
142 static uint8_t nand_read_byte16(struct mtd_info *mtd)
144 struct nand_chip *chip = mtd->priv;
145 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
149 * nand_read_word - [DEFAULT] read one word from the chip
150 * @mtd: MTD device structure
152 * Default read function for 16bit buswith without
153 * endianess conversion
155 static u16 nand_read_word(struct mtd_info *mtd)
157 struct nand_chip *chip = mtd->priv;
158 return readw(chip->IO_ADDR_R);
162 * nand_select_chip - [DEFAULT] control CE line
163 * @mtd: MTD device structure
164 * @chip: chipnumber to select, -1 for deselect
166 * Default select function for 1 chip devices.
168 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
170 struct nand_chip *chip = mtd->priv;
174 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
177 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
178 NAND_NCE | NAND_CTRL_CHANGE);
187 * nand_write_buf - [DEFAULT] write buffer to chip
188 * @mtd: MTD device structure
190 * @len: number of bytes to write
192 * Default write function for 8bit buswith
194 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
197 struct nand_chip *chip = mtd->priv;
199 for (i = 0; i < len; i++)
200 writeb(buf[i], chip->IO_ADDR_W);
204 * nand_read_buf - [DEFAULT] read chip data into buffer
205 * @mtd: MTD device structure
206 * @buf: buffer to store date
207 * @len: number of bytes to read
209 * Default read function for 8bit buswith
211 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
214 struct nand_chip *chip = mtd->priv;
216 for (i = 0; i < len; i++)
217 buf[i] = readb(chip->IO_ADDR_R);
221 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
222 * @mtd: MTD device structure
223 * @buf: buffer containing the data to compare
224 * @len: number of bytes to compare
226 * Default verify function for 8bit buswith
228 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
231 struct nand_chip *chip = mtd->priv;
233 for (i = 0; i < len; i++)
234 if (buf[i] != readb(chip->IO_ADDR_R))
240 * nand_write_buf16 - [DEFAULT] write buffer to chip
241 * @mtd: MTD device structure
243 * @len: number of bytes to write
245 * Default write function for 16bit buswith
247 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
250 struct nand_chip *chip = mtd->priv;
251 u16 *p = (u16 *) buf;
254 for (i = 0; i < len; i++)
255 writew(p[i], chip->IO_ADDR_W);
260 * nand_read_buf16 - [DEFAULT] read chip data into buffer
261 * @mtd: MTD device structure
262 * @buf: buffer to store date
263 * @len: number of bytes to read
265 * Default read function for 16bit buswith
267 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
270 struct nand_chip *chip = mtd->priv;
271 u16 *p = (u16 *) buf;
274 for (i = 0; i < len; i++)
275 p[i] = readw(chip->IO_ADDR_R);
279 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
280 * @mtd: MTD device structure
281 * @buf: buffer containing the data to compare
282 * @len: number of bytes to compare
284 * Default verify function for 16bit buswith
286 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
289 struct nand_chip *chip = mtd->priv;
290 u16 *p = (u16 *) buf;
293 for (i = 0; i < len; i++)
294 if (p[i] != readw(chip->IO_ADDR_R))
301 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
302 * @mtd: MTD device structure
303 * @ofs: offset from device start
304 * @getchip: 0, if the chip is already selected
306 * Check, if the block is bad.
308 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
310 int page, chipnr, res = 0;
311 struct nand_chip *chip = mtd->priv;
315 page = (int)(ofs >> chip->page_shift);
316 chipnr = (int)(ofs >> chip->chip_shift);
318 nand_get_device(chip, mtd, FL_READING);
320 /* Select the NAND device */
321 chip->select_chip(mtd, chipnr);
325 if (chip->options & NAND_BUSWIDTH_16) {
326 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
327 page & chip->pagemask);
328 bad = cpu_to_le16(chip->read_word(mtd));
329 if (chip->badblockpos & 0x1)
331 if ((bad & 0xFF) != 0xff)
334 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
335 page & chip->pagemask);
336 if (chip->read_byte(mtd) != 0xff)
341 nand_release_device(mtd);
347 * nand_default_block_markbad - [DEFAULT] mark a block bad
348 * @mtd: MTD device structure
349 * @ofs: offset from device start
351 * This is the default implementation, which can be overridden by
352 * a hardware specific driver.
354 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
356 struct nand_chip *chip = mtd->priv;
357 uint8_t buf[2] = { 0, 0 };
361 /* Get block number */
362 block = ((int)ofs) >> chip->bbt_erase_shift;
364 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
366 /* Do we have a flash based bad block table ? */
367 if (chip->options & NAND_USE_FLASH_BBT)
368 return nand_update_bbt(mtd, ofs);
370 /* We write two bytes, so we dont have to mess with 16 bit access */
371 ofs += mtd->oobsize + (chip->badblockpos & ~0x01);
372 return nand_write_oob(mtd, ofs, 2, &retlen, buf);
376 * nand_check_wp - [GENERIC] check if the chip is write protected
377 * @mtd: MTD device structure
378 * Check, if the device is write protected
380 * The function expects, that the device is already selected
382 static int nand_check_wp(struct mtd_info *mtd)
384 struct nand_chip *chip = mtd->priv;
385 /* Check the WP bit */
386 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
387 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
391 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
392 * @mtd: MTD device structure
393 * @ofs: offset from device start
394 * @getchip: 0, if the chip is already selected
395 * @allowbbt: 1, if its allowed to access the bbt area
397 * Check, if the block is bad. Either by reading the bad block table or
398 * calling of the scan function.
400 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
403 struct nand_chip *chip = mtd->priv;
406 return chip->block_bad(mtd, ofs, getchip);
408 /* Return info from the table */
409 return nand_isbad_bbt(mtd, ofs, allowbbt);
413 * Wait for the ready pin, after a command
414 * The timeout is catched later.
416 static void nand_wait_ready(struct mtd_info *mtd)
418 struct nand_chip *chip = mtd->priv;
419 unsigned long timeo = jiffies + 2;
421 led_trigger_event(nand_led_trigger, LED_FULL);
422 /* wait until command is processed or timeout occures */
424 if (chip->dev_ready(mtd))
426 touch_softlockup_watchdog();
427 } while (time_before(jiffies, timeo));
428 led_trigger_event(nand_led_trigger, LED_OFF);
432 * nand_command - [DEFAULT] Send command to NAND device
433 * @mtd: MTD device structure
434 * @command: the command to be sent
435 * @column: the column address for this command, -1 if none
436 * @page_addr: the page address for this command, -1 if none
438 * Send command to NAND device. This function is used for small page
439 * devices (256/512 Bytes per page)
441 static void nand_command(struct mtd_info *mtd, unsigned int command,
442 int column, int page_addr)
444 register struct nand_chip *chip = mtd->priv;
445 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
448 * Write out the command to the device.
450 if (command == NAND_CMD_SEQIN) {
453 if (column >= mtd->writesize) {
455 column -= mtd->writesize;
456 readcmd = NAND_CMD_READOOB;
457 } else if (column < 256) {
458 /* First 256 bytes --> READ0 */
459 readcmd = NAND_CMD_READ0;
462 readcmd = NAND_CMD_READ1;
464 chip->cmd_ctrl(mtd, readcmd, ctrl);
465 ctrl &= ~NAND_CTRL_CHANGE;
467 chip->cmd_ctrl(mtd, command, ctrl);
470 * Address cycle, when necessary
472 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
473 /* Serially input address */
475 /* Adjust columns for 16 bit buswidth */
476 if (chip->options & NAND_BUSWIDTH_16)
478 chip->cmd_ctrl(mtd, column, ctrl);
479 ctrl &= ~NAND_CTRL_CHANGE;
481 if (page_addr != -1) {
482 chip->cmd_ctrl(mtd, page_addr, ctrl);
483 ctrl &= ~NAND_CTRL_CHANGE;
484 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
485 /* One more address cycle for devices > 32MiB */
486 if (chip->chipsize > (32 << 20))
487 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
489 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
492 * program and erase have their own busy handlers
493 * status and sequential in needs no delay
497 case NAND_CMD_PAGEPROG:
498 case NAND_CMD_ERASE1:
499 case NAND_CMD_ERASE2:
501 case NAND_CMD_STATUS:
502 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
508 udelay(chip->chip_delay);
509 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
510 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
512 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
513 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
516 /* This applies to read commands */
519 * If we don't have access to the busy pin, we apply the given
522 if (!chip->dev_ready) {
523 udelay(chip->chip_delay);
527 /* Apply this short delay always to ensure that we do wait tWB in
528 * any case on any machine. */
531 nand_wait_ready(mtd);
535 * nand_command_lp - [DEFAULT] Send command to NAND large page device
536 * @mtd: MTD device structure
537 * @command: the command to be sent
538 * @column: the column address for this command, -1 if none
539 * @page_addr: the page address for this command, -1 if none
541 * Send command to NAND device. This is the version for the new large page
542 * devices We dont have the separate regions as we have in the small page
543 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
546 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
547 int column, int page_addr)
549 register struct nand_chip *chip = mtd->priv;
551 /* Emulate NAND_CMD_READOOB */
552 if (command == NAND_CMD_READOOB) {
553 column += mtd->writesize;
554 command = NAND_CMD_READ0;
557 /* Command latch cycle */
558 chip->cmd_ctrl(mtd, command & 0xff,
559 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
561 if (column != -1 || page_addr != -1) {
562 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
564 /* Serially input address */
566 /* Adjust columns for 16 bit buswidth */
567 if (chip->options & NAND_BUSWIDTH_16)
569 chip->cmd_ctrl(mtd, column, ctrl);
570 ctrl &= ~NAND_CTRL_CHANGE;
571 chip->cmd_ctrl(mtd, column >> 8, ctrl);
573 if (page_addr != -1) {
574 chip->cmd_ctrl(mtd, page_addr, ctrl);
575 chip->cmd_ctrl(mtd, page_addr >> 8,
576 NAND_NCE | NAND_ALE);
577 /* One more address cycle for devices > 128MiB */
578 if (chip->chipsize > (128 << 20))
579 chip->cmd_ctrl(mtd, page_addr >> 16,
580 NAND_NCE | NAND_ALE);
583 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
586 * program and erase have their own busy handlers
587 * status, sequential in, and deplete1 need no delay
591 case NAND_CMD_CACHEDPROG:
592 case NAND_CMD_PAGEPROG:
593 case NAND_CMD_ERASE1:
594 case NAND_CMD_ERASE2:
596 case NAND_CMD_STATUS:
597 case NAND_CMD_DEPLETE1:
601 * read error status commands require only a short delay
603 case NAND_CMD_STATUS_ERROR:
604 case NAND_CMD_STATUS_ERROR0:
605 case NAND_CMD_STATUS_ERROR1:
606 case NAND_CMD_STATUS_ERROR2:
607 case NAND_CMD_STATUS_ERROR3:
608 udelay(chip->chip_delay);
614 udelay(chip->chip_delay);
615 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
616 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
617 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
618 NAND_NCE | NAND_CTRL_CHANGE);
619 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
623 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
624 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
625 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
626 NAND_NCE | NAND_CTRL_CHANGE);
628 /* This applies to read commands */
631 * If we don't have access to the busy pin, we apply the given
634 if (!chip->dev_ready) {
635 udelay(chip->chip_delay);
640 /* Apply this short delay always to ensure that we do wait tWB in
641 * any case on any machine. */
644 nand_wait_ready(mtd);
648 * nand_get_device - [GENERIC] Get chip for selected access
649 * @this: the nand chip descriptor
650 * @mtd: MTD device structure
651 * @new_state: the state which is requested
653 * Get the device and lock it for exclusive access
656 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
658 spinlock_t *lock = &chip->controller->lock;
659 wait_queue_head_t *wq = &chip->controller->wq;
660 DECLARE_WAITQUEUE(wait, current);
664 /* Hardware controller shared among independend devices */
665 /* Hardware controller shared among independend devices */
666 if (!chip->controller->active)
667 chip->controller->active = chip;
669 if (chip->controller->active == chip && chip->state == FL_READY) {
670 chip->state = new_state;
674 if (new_state == FL_PM_SUSPENDED) {
676 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
678 set_current_state(TASK_UNINTERRUPTIBLE);
679 add_wait_queue(wq, &wait);
682 remove_wait_queue(wq, &wait);
687 * nand_wait - [DEFAULT] wait until the command is done
688 * @mtd: MTD device structure
689 * @this: NAND chip structure
690 * @state: state to select the max. timeout value
692 * Wait for command done. This applies to erase and program only
693 * Erase can take up to 400ms and program up to 20ms according to
694 * general NAND and SmartMedia specs
697 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
700 unsigned long timeo = jiffies;
703 if (state == FL_ERASING)
704 timeo += (HZ * 400) / 1000;
706 timeo += (HZ * 20) / 1000;
708 led_trigger_event(nand_led_trigger, LED_FULL);
710 /* Apply this short delay always to ensure that we do wait tWB in
711 * any case on any machine. */
714 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
715 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
717 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
719 while (time_before(jiffies, timeo)) {
720 /* Check, if we were interrupted */
721 if (chip->state != state)
724 if (chip->dev_ready) {
725 if (chip->dev_ready(mtd))
728 if (chip->read_byte(mtd) & NAND_STATUS_READY)
733 led_trigger_event(nand_led_trigger, LED_OFF);
735 status = (int)chip->read_byte(mtd);
740 * nand_read_page_swecc - {REPLACABLE] software ecc based page read function
741 * @mtd: mtd info structure
742 * @chip: nand chip info structure
743 * @buf: buffer to store read data
745 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
748 int i, eccsize = chip->ecc.size;
749 int eccbytes = chip->ecc.bytes;
750 int eccsteps = chip->ecc.steps;
752 uint8_t *ecc_calc = chip->buffers.ecccalc;
753 uint8_t *ecc_code = chip->buffers.ecccode;
754 int *eccpos = chip->autooob->eccpos;
756 chip->read_buf(mtd, buf, mtd->writesize);
757 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
759 if (chip->ecc.mode == NAND_ECC_NONE)
762 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
763 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
765 for (i = 0; i < chip->ecc.total; i++)
766 ecc_code[i] = chip->oob_poi[eccpos[i]];
768 eccsteps = chip->ecc.steps;
771 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
774 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
776 mtd->ecc_stats.failed++;
778 mtd->ecc_stats.corrected += stat;
784 * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function
785 * @mtd: mtd info structure
786 * @chip: nand chip info structure
787 * @buf: buffer to store read data
789 * Not for syndrome calculating ecc controllers which need a special oob layout
791 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
794 int i, eccsize = chip->ecc.size;
795 int eccbytes = chip->ecc.bytes;
796 int eccsteps = chip->ecc.steps;
798 uint8_t *ecc_calc = chip->buffers.ecccalc;
799 uint8_t *ecc_code = chip->buffers.ecccode;
800 int *eccpos = chip->autooob->eccpos;
802 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
803 chip->ecc.hwctl(mtd, NAND_ECC_READ);
804 chip->read_buf(mtd, p, eccsize);
805 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
807 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
809 for (i = 0; i < chip->ecc.total; i++)
810 ecc_code[i] = chip->oob_poi[eccpos[i]];
812 eccsteps = chip->ecc.steps;
815 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
818 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
820 mtd->ecc_stats.failed++;
822 mtd->ecc_stats.corrected += stat;
828 * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
829 * @mtd: mtd info structure
830 * @chip: nand chip info structure
831 * @buf: buffer to store read data
833 * The hw generator calculates the error syndrome automatically. Therefor
834 * we need a special oob layout and handling.
836 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
839 int i, eccsize = chip->ecc.size;
840 int eccbytes = chip->ecc.bytes;
841 int eccsteps = chip->ecc.steps;
843 uint8_t *oob = chip->oob_poi;
845 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
848 chip->ecc.hwctl(mtd, NAND_ECC_READ);
849 chip->read_buf(mtd, p, eccsize);
851 if (chip->ecc.prepad) {
852 chip->read_buf(mtd, oob, chip->ecc.prepad);
853 oob += chip->ecc.prepad;
856 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
857 chip->read_buf(mtd, oob, eccbytes);
858 stat = chip->ecc.correct(mtd, p, oob, NULL);
861 mtd->ecc_stats.failed++;
863 mtd->ecc_stats.corrected += stat;
867 if (chip->ecc.postpad) {
868 chip->read_buf(mtd, oob, chip->ecc.postpad);
869 oob += chip->ecc.postpad;
873 /* Calculate remaining oob bytes */
874 i = oob - chip->oob_poi;
876 chip->read_buf(mtd, oob, i);
882 * nand_do_read - [Internal] Read data with ECC
884 * @mtd: MTD device structure
885 * @from: offset to read from
886 * @len: number of bytes to read
887 * @retlen: pointer to variable to store the number of read bytes
888 * @buf: the databuffer to put data
890 * Internal function. Called with chip held.
892 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
893 size_t *retlen, uint8_t *buf)
895 int chipnr, page, realpage, col, bytes, aligned;
896 struct nand_chip *chip = mtd->priv;
897 struct mtd_ecc_stats stats;
898 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
901 uint32_t readlen = len;
904 stats = mtd->ecc_stats;
906 chipnr = (int)(from >> chip->chip_shift);
907 chip->select_chip(mtd, chipnr);
909 realpage = (int)(from >> chip->page_shift);
910 page = realpage & chip->pagemask;
912 col = (int)(from & (mtd->writesize - 1));
913 chip->oob_poi = chip->buffers.oobrbuf;
916 bytes = min(mtd->writesize - col, readlen);
917 aligned = (bytes == mtd->writesize);
919 /* Is the current page in the buffer ? */
920 if (realpage != chip->pagebuf) {
921 bufpoi = aligned ? buf : chip->buffers.databuf;
923 if (likely(sndcmd)) {
924 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
928 /* Now read the page into the buffer */
929 ret = chip->ecc.read_page(mtd, chip, bufpoi);
933 /* Transfer not aligned data */
935 chip->pagebuf = realpage;
936 memcpy(buf, chip->buffers.databuf + col, bytes);
939 if (!(chip->options & NAND_NO_READRDY)) {
941 * Apply delay or wait for ready/busy pin. Do
942 * this before the AUTOINCR check, so no
943 * problems arise if a chip which does auto
944 * increment is marked as NOAUTOINCR by the
947 if (!chip->dev_ready)
948 udelay(chip->chip_delay);
950 nand_wait_ready(mtd);
953 memcpy(buf, chip->buffers.databuf + col, bytes);
961 /* For subsequent reads align to page boundary. */
963 /* Increment page address */
966 page = realpage & chip->pagemask;
967 /* Check, if we cross a chip boundary */
970 chip->select_chip(mtd, -1);
971 chip->select_chip(mtd, chipnr);
974 /* Check, if the chip supports auto page increment
975 * or if we have hit a block boundary.
977 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
981 *retlen = len - (size_t) readlen;
986 return mtd->ecc_stats.failed - stats.failed ? -EBADMSG : 0;
990 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
991 * @mtd: MTD device structure
992 * @from: offset to read from
993 * @len: number of bytes to read
994 * @retlen: pointer to variable to store the number of read bytes
995 * @buf: the databuffer to put data
997 * Get hold of the chip and call nand_do_read
999 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1000 size_t *retlen, uint8_t *buf)
1005 /* Do not allow reads past end of device */
1006 if ((from + len) > mtd->size)
1011 nand_get_device(mtd->priv, mtd, FL_READING);
1013 ret = nand_do_read(mtd, from, len, retlen, buf);
1015 nand_release_device(mtd);
1021 * nand_read_oob - [MTD Interface] NAND read out-of-band
1022 * @mtd: MTD device structure
1023 * @from: offset to read from
1024 * @len: number of bytes to read
1025 * @retlen: pointer to variable to store the number of read bytes
1026 * @buf: the databuffer to put data
1028 * NAND read out-of-band data from the spare area
1030 static int nand_read_oob(struct mtd_info *mtd, loff_t from, size_t len,
1031 size_t *retlen, uint8_t *buf)
1033 int col, page, realpage, chipnr, sndcmd = 1;
1034 struct nand_chip *chip = mtd->priv;
1035 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1038 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08x, len = %i\n",
1039 (unsigned int)from, (int)len);
1041 /* Initialize return length value */
1044 /* Do not allow reads past end of device */
1045 if ((from + len) > mtd->size) {
1046 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1047 "Attempt read beyond end of device\n");
1051 nand_get_device(chip, mtd, FL_READING);
1053 chipnr = (int)(from >> chip->chip_shift);
1054 chip->select_chip(mtd, chipnr);
1056 /* Shift to get page */
1057 realpage = (int)(from >> chip->page_shift);
1058 page = realpage & chip->pagemask;
1060 /* Mask to get column */
1061 col = from & (mtd->oobsize - 1);
1064 int bytes = min((int)(mtd->oobsize - col), readlen);
1066 if (likely(sndcmd)) {
1067 chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page);
1071 chip->read_buf(mtd, buf, bytes);
1077 if (!(chip->options & NAND_NO_READRDY)) {
1079 * Apply delay or wait for ready/busy pin. Do this
1080 * before the AUTOINCR check, so no problems arise if a
1081 * chip which does auto increment is marked as
1082 * NOAUTOINCR by the board driver.
1084 if (!chip->dev_ready)
1085 udelay(chip->chip_delay);
1087 nand_wait_ready(mtd);
1091 bytes = mtd->oobsize;
1094 /* Increment page address */
1097 page = realpage & chip->pagemask;
1098 /* Check, if we cross a chip boundary */
1101 chip->select_chip(mtd, -1);
1102 chip->select_chip(mtd, chipnr);
1105 /* Check, if the chip supports auto page increment
1106 * or if we have hit a block boundary.
1108 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1112 /* Deselect and wake up anyone waiting on the device */
1113 nand_release_device(mtd);
1120 * nand_read_raw - [GENERIC] Read raw data including oob into buffer
1121 * @mtd: MTD device structure
1122 * @buf: temporary buffer
1123 * @from: offset to read from
1124 * @len: number of bytes to read
1125 * @ooblen: number of oob data bytes to read
1127 * Read raw data including oob into buffer
1129 int nand_read_raw(struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len,
1132 struct nand_chip *chip = mtd->priv;
1133 int page = (int)(from >> chip->page_shift);
1134 int chipnr = (int)(from >> chip->chip_shift);
1137 int pagesize = mtd->writesize + mtd->oobsize;
1140 /* Do not allow reads past end of device */
1141 if ((from + len) > mtd->size) {
1142 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: "
1143 "Attempt read beyond end of device\n");
1147 /* Grab the lock and see if the device is available */
1148 nand_get_device(chip, mtd, FL_READING);
1150 chip->select_chip(mtd, chipnr);
1152 /* Add requested oob length */
1154 blockcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1157 if (likely(sndcmd)) {
1158 chip->cmdfunc(mtd, NAND_CMD_READ0, 0,
1159 page & chip->pagemask);
1163 chip->read_buf(mtd, &buf[cnt], pagesize);
1169 if (!(chip->options & NAND_NO_READRDY)) {
1170 if (!chip->dev_ready)
1171 udelay(chip->chip_delay);
1173 nand_wait_ready(mtd);
1177 * Check, if the chip supports auto page increment or if we
1178 * cross a block boundary.
1180 if (!NAND_CANAUTOINCR(chip) || !(page & blockcheck))
1184 /* Deselect and wake up anyone waiting on the device */
1185 nand_release_device(mtd);
1190 * nand_write_page_swecc - {REPLACABLE] software ecc based page write function
1191 * @mtd: mtd info structure
1192 * @chip: nand chip info structure
1195 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1198 int i, eccsize = chip->ecc.size;
1199 int eccbytes = chip->ecc.bytes;
1200 int eccsteps = chip->ecc.steps;
1201 uint8_t *ecc_calc = chip->buffers.ecccalc;
1202 const uint8_t *p = buf;
1203 int *eccpos = chip->autooob->eccpos;
1205 if (chip->ecc.mode != NAND_ECC_NONE) {
1206 /* Software ecc calculation */
1207 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1208 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1210 for (i = 0; i < chip->ecc.total; i++)
1211 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1214 chip->write_buf(mtd, buf, mtd->writesize);
1215 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1219 * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function
1220 * @mtd: mtd info structure
1221 * @chip: nand chip info structure
1224 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1227 int i, eccsize = chip->ecc.size;
1228 int eccbytes = chip->ecc.bytes;
1229 int eccsteps = chip->ecc.steps;
1230 uint8_t *ecc_calc = chip->buffers.ecccalc;
1231 const uint8_t *p = buf;
1232 int *eccpos = chip->autooob->eccpos;
1234 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1235 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1236 chip->write_buf(mtd, p, mtd->writesize);
1237 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1240 for (i = 0; i < chip->ecc.total; i++)
1241 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1243 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1247 * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write
1248 * @mtd: mtd info structure
1249 * @chip: nand chip info structure
1252 * The hw generator calculates the error syndrome automatically. Therefor
1253 * we need a special oob layout and handling.
1255 static void nand_write_page_syndrome(struct mtd_info *mtd,
1256 struct nand_chip *chip, const uint8_t *buf)
1258 int i, eccsize = chip->ecc.size;
1259 int eccbytes = chip->ecc.bytes;
1260 int eccsteps = chip->ecc.steps;
1261 const uint8_t *p = buf;
1262 uint8_t *oob = chip->oob_poi;
1264 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1266 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1267 chip->write_buf(mtd, p, eccsize);
1269 if (chip->ecc.prepad) {
1270 chip->write_buf(mtd, oob, chip->ecc.prepad);
1271 oob += chip->ecc.prepad;
1274 chip->ecc.calculate(mtd, p, oob);
1275 chip->write_buf(mtd, oob, eccbytes);
1278 if (chip->ecc.postpad) {
1279 chip->write_buf(mtd, oob, chip->ecc.postpad);
1280 oob += chip->ecc.postpad;
1284 /* Calculate remaining oob bytes */
1285 i = oob - chip->oob_poi;
1287 chip->write_buf(mtd, oob, i);
1291 * nand_write_page - [INTERNAL] write one page
1292 * @mtd: MTD device structure
1293 * @chip: NAND chip descriptor
1294 * @buf: the data to write
1295 * @page: page number to write
1296 * @cached: cached programming
1298 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1299 const uint8_t *buf, int page, int cached)
1303 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1305 chip->ecc.write_page(mtd, chip, buf);
1308 * Cached progamming disabled for now, Not sure if its worth the
1309 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1313 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1315 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1316 status = chip->waitfunc(mtd, chip, FL_WRITING);
1318 * See if operation failed and additional status checks are
1321 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1322 status = chip->errstat(mtd, chip, FL_WRITING, status,
1325 if (status & NAND_STATUS_FAIL)
1328 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1329 status = chip->waitfunc(mtd, chip, FL_WRITING);
1332 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1333 /* Send command to read back the data */
1334 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1336 if (chip->verify_buf(mtd, buf, mtd->writesize))
1342 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1345 * nand_write - [MTD Interface] NAND write with ECC
1346 * @mtd: MTD device structure
1347 * @to: offset to write to
1348 * @len: number of bytes to write
1349 * @retlen: pointer to variable to store the number of written bytes
1350 * @buf: the data to write
1352 * NAND write with ECC
1354 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1355 size_t *retlen, const uint8_t *buf)
1357 int chipnr, realpage, page, blockmask;
1358 struct nand_chip *chip = mtd->priv;
1359 uint32_t writelen = len;
1360 int bytes = mtd->writesize;
1365 /* Do not allow write past end of device */
1366 if ((to + len) > mtd->size) {
1367 DEBUG(MTD_DEBUG_LEVEL0, "nand_write: "
1368 "Attempt to write past end of page\n");
1372 /* reject writes, which are not page aligned */
1373 if (NOTALIGNED(to) || NOTALIGNED(len)) {
1374 printk(KERN_NOTICE "nand_write: "
1375 "Attempt to write not page aligned data\n");
1382 nand_get_device(chip, mtd, FL_WRITING);
1384 /* Check, if it is write protected */
1385 if (nand_check_wp(mtd))
1388 chipnr = (int)(to >> chip->chip_shift);
1389 chip->select_chip(mtd, chipnr);
1391 realpage = (int)(to >> chip->page_shift);
1392 page = realpage & chip->pagemask;
1393 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1395 /* Invalidate the page cache, when we write to the cached page */
1396 if (to <= (chip->pagebuf << chip->page_shift) &&
1397 (chip->pagebuf << chip->page_shift) < (to + len))
1400 chip->oob_poi = chip->buffers.oobwbuf;
1403 int cached = writelen > bytes && page != blockmask;
1405 ret = nand_write_page(mtd, chip, buf, page, cached);
1416 page = realpage & chip->pagemask;
1417 /* Check, if we cross a chip boundary */
1420 chip->select_chip(mtd, -1);
1421 chip->select_chip(mtd, chipnr);
1425 *retlen = len - writelen;
1426 nand_release_device(mtd);
1431 * nand_write_raw - [GENERIC] Write raw data including oob
1432 * @mtd: MTD device structure
1433 * @buf: source buffer
1434 * @to: offset to write to
1435 * @len: number of bytes to write
1436 * @buf: source buffer
1439 * Write raw data including oob
1441 int nand_write_raw(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
1442 const uint8_t *buf, uint8_t *oob)
1444 struct nand_chip *chip = mtd->priv;
1445 int page = (int)(to >> chip->page_shift);
1446 int chipnr = (int)(to >> chip->chip_shift);
1451 /* Do not allow writes past end of device */
1452 if ((to + len) > mtd->size) {
1453 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_raw: Attempt write "
1454 "beyond end of device\n");
1458 /* Grab the lock and see if the device is available */
1459 nand_get_device(chip, mtd, FL_WRITING);
1461 chip->select_chip(mtd, chipnr);
1462 chip->oob_poi = oob;
1464 while (len != *retlen) {
1465 ret = nand_write_page(mtd, chip, buf, page, 0);
1469 *retlen += mtd->writesize;
1470 buf += mtd->writesize;
1471 chip->oob_poi += mtd->oobsize;
1474 /* Deselect and wake up anyone waiting on the device */
1475 nand_release_device(mtd);
1478 EXPORT_SYMBOL_GPL(nand_write_raw);
1481 * nand_write_oob - [MTD Interface] NAND write out-of-band
1482 * @mtd: MTD device structure
1483 * @to: offset to write to
1484 * @len: number of bytes to write
1485 * @retlen: pointer to variable to store the number of written bytes
1486 * @buf: the data to write
1488 * NAND write out-of-band
1490 static int nand_write_oob(struct mtd_info *mtd, loff_t to, size_t len,
1491 size_t *retlen, const uint8_t *buf)
1493 int column, page, status, ret = -EIO, chipnr;
1494 struct nand_chip *chip = mtd->priv;
1496 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1497 (unsigned int)to, (int)len);
1499 /* Initialize return length value */
1502 /* Do not allow write past end of page */
1503 column = to & (mtd->oobsize - 1);
1504 if ((column + len) > mtd->oobsize) {
1505 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1506 "Attempt to write past end of page\n");
1510 nand_get_device(chip, mtd, FL_WRITING);
1512 chipnr = (int)(to >> chip->chip_shift);
1513 chip->select_chip(mtd, chipnr);
1515 /* Shift to get page */
1516 page = (int)(to >> chip->page_shift);
1519 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1520 * of my DiskOnChip 2000 test units) will clear the whole data page too
1521 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1522 * it in the doc2000 driver in August 1999. dwmw2.
1524 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1526 /* Check, if it is write protected */
1527 if (nand_check_wp(mtd))
1530 /* Invalidate the page cache, if we write to the cached page */
1531 if (page == chip->pagebuf)
1534 if (NAND_MUST_PAD(chip)) {
1535 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize,
1536 page & chip->pagemask);
1537 /* prepad 0xff for partial programming */
1538 chip->write_buf(mtd, ffchars, column);
1540 chip->write_buf(mtd, buf, len);
1541 /* postpad 0xff for partial programming */
1542 chip->write_buf(mtd, ffchars, mtd->oobsize - (len + column));
1544 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize + column,
1545 page & chip->pagemask);
1546 chip->write_buf(mtd, buf, len);
1548 /* Send command to program the OOB data */
1549 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1551 status = chip->waitfunc(mtd, chip, FL_WRITING);
1553 /* See if device thinks it succeeded */
1554 if (status & NAND_STATUS_FAIL) {
1555 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1556 "Failed write, page 0x%08x\n", page);
1562 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1563 /* Send command to read back the data */
1564 chip->cmdfunc(mtd, NAND_CMD_READOOB, column, page & chip->pagemask);
1566 if (chip->verify_buf(mtd, buf, len)) {
1567 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1568 "Failed write verify, page 0x%08x\n", page);
1575 /* Deselect and wake up anyone waiting on the device */
1576 nand_release_device(mtd);
1582 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1583 * @mtd: MTD device structure
1584 * @page: the page address of the block which will be erased
1586 * Standard erase command for NAND chips
1588 static void single_erase_cmd(struct mtd_info *mtd, int page)
1590 struct nand_chip *chip = mtd->priv;
1591 /* Send commands to erase a block */
1592 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1593 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1597 * multi_erease_cmd - [GENERIC] AND specific block erase command function
1598 * @mtd: MTD device structure
1599 * @page: the page address of the block which will be erased
1601 * AND multi block erase command function
1602 * Erase 4 consecutive blocks
1604 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1606 struct nand_chip *chip = mtd->priv;
1607 /* Send commands to erase a block */
1608 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1609 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1610 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1611 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1612 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1616 * nand_erase - [MTD Interface] erase block(s)
1617 * @mtd: MTD device structure
1618 * @instr: erase instruction
1620 * Erase one ore more blocks
1622 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1624 return nand_erase_nand(mtd, instr, 0);
1627 #define BBT_PAGE_MASK 0xffffff3f
1629 * nand_erase_nand - [Internal] erase block(s)
1630 * @mtd: MTD device structure
1631 * @instr: erase instruction
1632 * @allowbbt: allow erasing the bbt area
1634 * Erase one ore more blocks
1636 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1639 int page, len, status, pages_per_block, ret, chipnr;
1640 struct nand_chip *chip = mtd->priv;
1641 int rewrite_bbt[NAND_MAX_CHIPS]={0};
1642 unsigned int bbt_masked_page = 0xffffffff;
1644 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1645 (unsigned int)instr->addr, (unsigned int)instr->len);
1647 /* Start address must align on block boundary */
1648 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1649 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1653 /* Length must align on block boundary */
1654 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1655 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1656 "Length not block aligned\n");
1660 /* Do not allow erase past end of device */
1661 if ((instr->len + instr->addr) > mtd->size) {
1662 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1663 "Erase past end of device\n");
1667 instr->fail_addr = 0xffffffff;
1669 /* Grab the lock and see if the device is available */
1670 nand_get_device(chip, mtd, FL_ERASING);
1672 /* Shift to get first page */
1673 page = (int)(instr->addr >> chip->page_shift);
1674 chipnr = (int)(instr->addr >> chip->chip_shift);
1676 /* Calculate pages in each block */
1677 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1679 /* Select the NAND device */
1680 chip->select_chip(mtd, chipnr);
1682 /* Check, if it is write protected */
1683 if (nand_check_wp(mtd)) {
1684 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1685 "Device is write protected!!!\n");
1686 instr->state = MTD_ERASE_FAILED;
1691 * If BBT requires refresh, set the BBT page mask to see if the BBT
1692 * should be rewritten. Otherwise the mask is set to 0xffffffff which
1693 * can not be matched. This is also done when the bbt is actually
1694 * erased to avoid recusrsive updates
1696 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1697 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1699 /* Loop through the pages */
1702 instr->state = MTD_ERASING;
1706 * heck if we have a bad block, we do not erase bad blocks !
1708 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1709 chip->page_shift, 0, allowbbt)) {
1710 printk(KERN_WARNING "nand_erase: attempt to erase a "
1711 "bad block at page 0x%08x\n", page);
1712 instr->state = MTD_ERASE_FAILED;
1717 * Invalidate the page cache, if we erase the block which
1718 * contains the current cached page
1720 if (page <= chip->pagebuf && chip->pagebuf <
1721 (page + pages_per_block))
1724 chip->erase_cmd(mtd, page & chip->pagemask);
1726 status = chip->waitfunc(mtd, chip, FL_ERASING);
1729 * See if operation failed and additional status checks are
1732 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1733 status = chip->errstat(mtd, chip, FL_ERASING,
1736 /* See if block erase succeeded */
1737 if (status & NAND_STATUS_FAIL) {
1738 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1739 "Failed erase, page 0x%08x\n", page);
1740 instr->state = MTD_ERASE_FAILED;
1741 instr->fail_addr = (page << chip->page_shift);
1746 * If BBT requires refresh, set the BBT rewrite flag to the
1749 if (bbt_masked_page != 0xffffffff &&
1750 (page & BBT_PAGE_MASK) == bbt_masked_page)
1751 rewrite_bbt[chipnr] = (page << chip->page_shift);
1753 /* Increment page address and decrement length */
1754 len -= (1 << chip->phys_erase_shift);
1755 page += pages_per_block;
1757 /* Check, if we cross a chip boundary */
1758 if (len && !(page & chip->pagemask)) {
1760 chip->select_chip(mtd, -1);
1761 chip->select_chip(mtd, chipnr);
1764 * If BBT requires refresh and BBT-PERCHIP, set the BBT
1765 * page mask to see if this BBT should be rewritten
1767 if (bbt_masked_page != 0xffffffff &&
1768 (chip->bbt_td->options & NAND_BBT_PERCHIP))
1769 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1773 instr->state = MTD_ERASE_DONE;
1777 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1778 /* Do call back function */
1780 mtd_erase_callback(instr);
1782 /* Deselect and wake up anyone waiting on the device */
1783 nand_release_device(mtd);
1786 * If BBT requires refresh and erase was successful, rewrite any
1787 * selected bad block tables
1789 if (bbt_masked_page == 0xffffffff || ret)
1792 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
1793 if (!rewrite_bbt[chipnr])
1795 /* update the BBT for chip */
1796 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
1797 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
1798 chip->bbt_td->pages[chipnr]);
1799 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
1802 /* Return more or less happy */
1807 * nand_sync - [MTD Interface] sync
1808 * @mtd: MTD device structure
1810 * Sync is actually a wait for chip ready function
1812 static void nand_sync(struct mtd_info *mtd)
1814 struct nand_chip *chip = mtd->priv;
1816 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1818 /* Grab the lock and see if the device is available */
1819 nand_get_device(chip, mtd, FL_SYNCING);
1820 /* Release it and go back */
1821 nand_release_device(mtd);
1825 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1826 * @mtd: MTD device structure
1827 * @ofs: offset relative to mtd start
1829 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1831 /* Check for invalid offset */
1832 if (offs > mtd->size)
1835 return nand_block_checkbad(mtd, offs, 1, 0);
1839 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1840 * @mtd: MTD device structure
1841 * @ofs: offset relative to mtd start
1843 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1845 struct nand_chip *chip = mtd->priv;
1848 if ((ret = nand_block_isbad(mtd, ofs))) {
1849 /* If it was bad already, return success and do nothing. */
1855 return chip->block_markbad(mtd, ofs);
1859 * nand_suspend - [MTD Interface] Suspend the NAND flash
1860 * @mtd: MTD device structure
1862 static int nand_suspend(struct mtd_info *mtd)
1864 struct nand_chip *chip = mtd->priv;
1866 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
1870 * nand_resume - [MTD Interface] Resume the NAND flash
1871 * @mtd: MTD device structure
1873 static void nand_resume(struct mtd_info *mtd)
1875 struct nand_chip *chip = mtd->priv;
1877 if (chip->state == FL_PM_SUSPENDED)
1878 nand_release_device(mtd);
1880 printk(KERN_ERR "nand_resume() called for a chip which is not "
1881 "in suspended state\n");
1885 * Set default functions
1887 static void nand_set_defaults(struct nand_chip *chip, int busw)
1889 /* check for proper chip_delay setup, set 20us if not */
1890 if (!chip->chip_delay)
1891 chip->chip_delay = 20;
1893 /* check, if a user supplied command function given */
1894 if (chip->cmdfunc == NULL)
1895 chip->cmdfunc = nand_command;
1897 /* check, if a user supplied wait function given */
1898 if (chip->waitfunc == NULL)
1899 chip->waitfunc = nand_wait;
1901 if (!chip->select_chip)
1902 chip->select_chip = nand_select_chip;
1903 if (!chip->read_byte)
1904 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
1905 if (!chip->read_word)
1906 chip->read_word = nand_read_word;
1907 if (!chip->block_bad)
1908 chip->block_bad = nand_block_bad;
1909 if (!chip->block_markbad)
1910 chip->block_markbad = nand_default_block_markbad;
1911 if (!chip->write_buf)
1912 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
1913 if (!chip->read_buf)
1914 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
1915 if (!chip->verify_buf)
1916 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
1917 if (!chip->scan_bbt)
1918 chip->scan_bbt = nand_default_bbt;
1920 if (!chip->controller) {
1921 chip->controller = &chip->hwcontrol;
1922 spin_lock_init(&chip->controller->lock);
1923 init_waitqueue_head(&chip->controller->wq);
1929 * Get the flash and manufacturer id and lookup if the type is supported
1931 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
1932 struct nand_chip *chip,
1933 int busw, int *maf_id)
1935 struct nand_flash_dev *type = NULL;
1936 int i, dev_id, maf_idx;
1938 /* Select the device */
1939 chip->select_chip(mtd, 0);
1941 /* Send the command for reading device ID */
1942 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
1944 /* Read manufacturer and device IDs */
1945 *maf_id = chip->read_byte(mtd);
1946 dev_id = chip->read_byte(mtd);
1948 /* Lookup the flash id */
1949 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
1950 if (dev_id == nand_flash_ids[i].id) {
1951 type = &nand_flash_ids[i];
1957 return ERR_PTR(-ENODEV);
1959 chip->chipsize = nand_flash_ids[i].chipsize << 20;
1961 /* Newer devices have all the information in additional id bytes */
1962 if (!nand_flash_ids[i].pagesize) {
1964 /* The 3rd id byte contains non relevant data ATM */
1965 extid = chip->read_byte(mtd);
1966 /* The 4th id byte is the important one */
1967 extid = chip->read_byte(mtd);
1969 mtd->writesize = 1024 << (extid & 0x3);
1972 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
1974 /* Calc blocksize. Blocksize is multiples of 64KiB */
1975 mtd->erasesize = (64 * 1024) << (extid & 0x03);
1977 /* Get buswidth information */
1978 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
1982 * Old devices have chip data hardcoded in the device id table
1984 mtd->erasesize = nand_flash_ids[i].erasesize;
1985 mtd->writesize = nand_flash_ids[i].pagesize;
1986 mtd->oobsize = mtd->writesize / 32;
1987 busw = nand_flash_ids[i].options & NAND_BUSWIDTH_16;
1990 /* Try to identify manufacturer */
1991 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) {
1992 if (nand_manuf_ids[maf_idx].id == *maf_id)
1997 * Check, if buswidth is correct. Hardware drivers should set
2000 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2001 printk(KERN_INFO "NAND device: Manufacturer ID:"
2002 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2003 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2004 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2005 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2007 return ERR_PTR(-EINVAL);
2010 /* Calculate the address shift from the page size */
2011 chip->page_shift = ffs(mtd->writesize) - 1;
2012 /* Convert chipsize to number of pages per chip -1. */
2013 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2015 chip->bbt_erase_shift = chip->phys_erase_shift =
2016 ffs(mtd->erasesize) - 1;
2017 chip->chip_shift = ffs(chip->chipsize) - 1;
2019 /* Set the bad block position */
2020 chip->badblockpos = mtd->writesize > 512 ?
2021 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2023 /* Get chip options, preserve non chip based options */
2024 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2025 chip->options |= nand_flash_ids[i].options & NAND_CHIPOPTIONS_MSK;
2028 * Set chip as a default. Board drivers can override it, if necessary
2030 chip->options |= NAND_NO_AUTOINCR;
2032 /* Check if chip is a not a samsung device. Do not clear the
2033 * options for chips which are not having an extended id.
2035 if (*maf_id != NAND_MFR_SAMSUNG && !nand_flash_ids[i].pagesize)
2036 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2038 /* Check for AND chips with 4 page planes */
2039 if (chip->options & NAND_4PAGE_ARRAY)
2040 chip->erase_cmd = multi_erase_cmd;
2042 chip->erase_cmd = single_erase_cmd;
2044 /* Do not replace user supplied command function ! */
2045 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2046 chip->cmdfunc = nand_command_lp;
2048 printk(KERN_INFO "NAND device: Manufacturer ID:"
2049 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2050 nand_manuf_ids[maf_idx].name, type->name);
2055 /* module_text_address() isn't exported, and it's mostly a pointless
2056 test if this is a module _anyway_ -- they'd have to try _really_ hard
2057 to call us from in-kernel code if the core NAND support is modular. */
2059 #define caller_is_module() (1)
2061 #define caller_is_module() \
2062 module_text_address((unsigned long)__builtin_return_address(0))
2066 * nand_scan - [NAND Interface] Scan for the NAND device
2067 * @mtd: MTD device structure
2068 * @maxchips: Number of chips to scan for
2070 * This fills out all the uninitialized function pointers
2071 * with the defaults.
2072 * The flash ID is read and the mtd/chip structures are
2073 * filled with the appropriate values.
2074 * The mtd->owner field must be set to the module of the caller
2077 int nand_scan(struct mtd_info *mtd, int maxchips)
2079 int i, busw, nand_maf_id;
2080 struct nand_chip *chip = mtd->priv;
2081 struct nand_flash_dev *type;
2083 /* Many callers got this wrong, so check for it for a while... */
2084 if (!mtd->owner && caller_is_module()) {
2085 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2089 /* Get buswidth to select the correct functions */
2090 busw = chip->options & NAND_BUSWIDTH_16;
2091 /* Set the default functions */
2092 nand_set_defaults(chip, busw);
2094 /* Read the flash type */
2095 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2098 printk(KERN_WARNING "No NAND device found!!!\n");
2099 chip->select_chip(mtd, -1);
2100 return PTR_ERR(type);
2103 /* Check for a chip array */
2104 for (i = 1; i < maxchips; i++) {
2105 chip->select_chip(mtd, i);
2106 /* Send the command for reading device ID */
2107 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2108 /* Read manufacturer and device IDs */
2109 if (nand_maf_id != chip->read_byte(mtd) ||
2110 type->id != chip->read_byte(mtd))
2114 printk(KERN_INFO "%d NAND chips detected\n", i);
2116 /* Store the number of chips and calc total size for mtd */
2118 mtd->size = i * chip->chipsize;
2120 /* Preset the internal oob write buffer */
2121 memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize);
2124 * If no default placement scheme is given, select an appropriate one
2126 if (!chip->autooob) {
2127 switch (mtd->oobsize) {
2129 chip->autooob = &nand_oob_8;
2132 chip->autooob = &nand_oob_16;
2135 chip->autooob = &nand_oob_64;
2138 printk(KERN_WARNING "No oob scheme defined for "
2139 "oobsize %d\n", mtd->oobsize);
2145 * The number of bytes available for the filesystem to place fs
2146 * dependend oob data
2149 for (i = 0; chip->autooob->oobfree[i][1]; i++)
2150 mtd->oobavail += chip->autooob->oobfree[i][1];
2153 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2154 * selected and we have 256 byte pagesize fallback to software ECC
2156 switch (chip->ecc.mode) {
2158 /* Use standard hwecc read page function ? */
2159 if (!chip->ecc.read_page)
2160 chip->ecc.read_page = nand_read_page_hwecc;
2161 if (!chip->ecc.write_page)
2162 chip->ecc.write_page = nand_write_page_hwecc;
2164 case NAND_ECC_HW_SYNDROME:
2165 if (!chip->ecc.calculate || !chip->ecc.correct ||
2167 printk(KERN_WARNING "No ECC functions supplied, "
2168 "Hardware ECC not possible\n");
2171 /* Use standard syndrome read/write page function ? */
2172 if (!chip->ecc.read_page)
2173 chip->ecc.read_page = nand_read_page_syndrome;
2174 if (!chip->ecc.write_page)
2175 chip->ecc.write_page = nand_write_page_syndrome;
2177 if (mtd->writesize >= chip->ecc.size)
2179 printk(KERN_WARNING "%d byte HW ECC not possible on "
2180 "%d byte page size, fallback to SW ECC\n",
2181 chip->ecc.size, mtd->writesize);
2182 chip->ecc.mode = NAND_ECC_SOFT;
2185 chip->ecc.calculate = nand_calculate_ecc;
2186 chip->ecc.correct = nand_correct_data;
2187 chip->ecc.read_page = nand_read_page_swecc;
2188 chip->ecc.write_page = nand_write_page_swecc;
2189 chip->ecc.size = 256;
2190 chip->ecc.bytes = 3;
2194 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2195 "This is not recommended !!\n");
2196 chip->ecc.read_page = nand_read_page_swecc;
2197 chip->ecc.write_page = nand_write_page_swecc;
2198 chip->ecc.size = mtd->writesize;
2199 chip->ecc.bytes = 0;
2202 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2208 * Set the number of read / write steps for one page depending on ECC
2211 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2212 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2213 printk(KERN_WARNING "Invalid ecc parameters\n");
2216 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2218 /* Initialize state */
2219 chip->state = FL_READY;
2221 /* De-select the device */
2222 chip->select_chip(mtd, -1);
2224 /* Invalidate the pagebuffer reference */
2227 /* Fill in remaining MTD driver data */
2228 mtd->type = MTD_NANDFLASH;
2229 mtd->flags = MTD_CAP_NANDFLASH;
2230 mtd->ecctype = MTD_ECC_SW;
2231 mtd->erase = nand_erase;
2233 mtd->unpoint = NULL;
2234 mtd->read = nand_read;
2235 mtd->write = nand_write;
2236 mtd->read_oob = nand_read_oob;
2237 mtd->write_oob = nand_write_oob;
2238 mtd->sync = nand_sync;
2241 mtd->suspend = nand_suspend;
2242 mtd->resume = nand_resume;
2243 mtd->block_isbad = nand_block_isbad;
2244 mtd->block_markbad = nand_block_markbad;
2246 /* and make the autooob the default one */
2247 memcpy(&mtd->oobinfo, chip->autooob, sizeof(mtd->oobinfo));
2249 /* Check, if we should skip the bad block table scan */
2250 if (chip->options & NAND_SKIP_BBTSCAN)
2253 /* Build bad block table */
2254 return chip->scan_bbt(mtd);
2258 * nand_release - [NAND Interface] Free resources held by the NAND device
2259 * @mtd: MTD device structure
2261 void nand_release(struct mtd_info *mtd)
2263 struct nand_chip *chip = mtd->priv;
2265 #ifdef CONFIG_MTD_PARTITIONS
2266 /* Deregister partitions */
2267 del_mtd_partitions(mtd);
2269 /* Deregister the device */
2270 del_mtd_device(mtd);
2272 /* Free bad block table memory */
2276 EXPORT_SYMBOL_GPL(nand_scan);
2277 EXPORT_SYMBOL_GPL(nand_release);
2279 static int __init nand_base_init(void)
2281 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2285 static void __exit nand_base_exit(void)
2287 led_trigger_unregister_simple(nand_led_trigger);
2290 module_init(nand_base_init);
2291 module_exit(nand_base_exit);
2293 MODULE_LICENSE("GPL");
2294 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2295 MODULE_DESCRIPTION("Generic NAND flash driver code");