5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/tech/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
28 * This program is free software; you can redistribute it and/or modify
29 * it under the terms of the GNU General Public License version 2 as
30 * published by the Free Software Foundation.
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/err.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/types.h>
41 #include <linux/mtd/mtd.h>
42 #include <linux/mtd/nand.h>
43 #include <linux/mtd/nand_ecc.h>
44 #include <linux/mtd/compatmac.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_ecclayout nand_oob_8 = {
65 static struct nand_ecclayout nand_oob_16 = {
67 .eccpos = {0, 1, 2, 3, 6, 7},
73 static struct nand_ecclayout nand_oob_64 = {
76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
84 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
87 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
88 struct mtd_oob_ops *ops);
91 * For devices which display every fart in the system on a seperate LED. Is
92 * compiled away when LED support is disabled.
94 DEFINE_LED_TRIGGER(nand_led_trigger);
97 * nand_release_device - [GENERIC] release chip
98 * @mtd: MTD device structure
100 * Deselect, release chip lock and wake up anyone waiting on the device
102 static void nand_release_device(struct mtd_info *mtd)
104 struct nand_chip *chip = mtd->priv;
106 /* De-select the NAND device */
107 chip->select_chip(mtd, -1);
109 /* Release the controller and the chip */
110 spin_lock(&chip->controller->lock);
111 chip->controller->active = NULL;
112 chip->state = FL_READY;
113 wake_up(&chip->controller->wq);
114 spin_unlock(&chip->controller->lock);
118 * nand_read_byte - [DEFAULT] read one byte from the chip
119 * @mtd: MTD device structure
121 * Default read function for 8bit buswith
123 static uint8_t nand_read_byte(struct mtd_info *mtd)
125 struct nand_chip *chip = mtd->priv;
126 return readb(chip->IO_ADDR_R);
130 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
131 * @mtd: MTD device structure
133 * Default read function for 16bit buswith with
134 * endianess conversion
136 static uint8_t nand_read_byte16(struct mtd_info *mtd)
138 struct nand_chip *chip = mtd->priv;
139 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
143 * nand_read_word - [DEFAULT] read one word from the chip
144 * @mtd: MTD device structure
146 * Default read function for 16bit buswith without
147 * endianess conversion
149 static u16 nand_read_word(struct mtd_info *mtd)
151 struct nand_chip *chip = mtd->priv;
152 return readw(chip->IO_ADDR_R);
156 * nand_select_chip - [DEFAULT] control CE line
157 * @mtd: MTD device structure
158 * @chip: chipnumber to select, -1 for deselect
160 * Default select function for 1 chip devices.
162 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
164 struct nand_chip *chip = mtd->priv;
168 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
179 * nand_write_buf - [DEFAULT] write buffer to chip
180 * @mtd: MTD device structure
182 * @len: number of bytes to write
184 * Default write function for 8bit buswith
186 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
189 struct nand_chip *chip = mtd->priv;
191 for (i = 0; i < len; i++)
192 writeb(buf[i], chip->IO_ADDR_W);
196 * nand_read_buf - [DEFAULT] read chip data into buffer
197 * @mtd: MTD device structure
198 * @buf: buffer to store date
199 * @len: number of bytes to read
201 * Default read function for 8bit buswith
203 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
206 struct nand_chip *chip = mtd->priv;
208 for (i = 0; i < len; i++)
209 buf[i] = readb(chip->IO_ADDR_R);
213 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
214 * @mtd: MTD device structure
215 * @buf: buffer containing the data to compare
216 * @len: number of bytes to compare
218 * Default verify function for 8bit buswith
220 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
223 struct nand_chip *chip = mtd->priv;
225 for (i = 0; i < len; i++)
226 if (buf[i] != readb(chip->IO_ADDR_R))
232 * nand_write_buf16 - [DEFAULT] write buffer to chip
233 * @mtd: MTD device structure
235 * @len: number of bytes to write
237 * Default write function for 16bit buswith
239 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
242 struct nand_chip *chip = mtd->priv;
243 u16 *p = (u16 *) buf;
246 for (i = 0; i < len; i++)
247 writew(p[i], chip->IO_ADDR_W);
252 * nand_read_buf16 - [DEFAULT] read chip data into buffer
253 * @mtd: MTD device structure
254 * @buf: buffer to store date
255 * @len: number of bytes to read
257 * Default read function for 16bit buswith
259 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
262 struct nand_chip *chip = mtd->priv;
263 u16 *p = (u16 *) buf;
266 for (i = 0; i < len; i++)
267 p[i] = readw(chip->IO_ADDR_R);
271 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
272 * @mtd: MTD device structure
273 * @buf: buffer containing the data to compare
274 * @len: number of bytes to compare
276 * Default verify function for 16bit buswith
278 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
281 struct nand_chip *chip = mtd->priv;
282 u16 *p = (u16 *) buf;
285 for (i = 0; i < len; i++)
286 if (p[i] != readw(chip->IO_ADDR_R))
293 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
294 * @mtd: MTD device structure
295 * @ofs: offset from device start
296 * @getchip: 0, if the chip is already selected
298 * Check, if the block is bad.
300 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
302 int page, chipnr, res = 0;
303 struct nand_chip *chip = mtd->priv;
307 page = (int)(ofs >> chip->page_shift);
308 chipnr = (int)(ofs >> chip->chip_shift);
310 nand_get_device(chip, mtd, FL_READING);
312 /* Select the NAND device */
313 chip->select_chip(mtd, chipnr);
317 if (chip->options & NAND_BUSWIDTH_16) {
318 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
319 page & chip->pagemask);
320 bad = cpu_to_le16(chip->read_word(mtd));
321 if (chip->badblockpos & 0x1)
323 if ((bad & 0xFF) != 0xff)
326 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
327 page & chip->pagemask);
328 if (chip->read_byte(mtd) != 0xff)
333 nand_release_device(mtd);
339 * nand_default_block_markbad - [DEFAULT] mark a block bad
340 * @mtd: MTD device structure
341 * @ofs: offset from device start
343 * This is the default implementation, which can be overridden by
344 * a hardware specific driver.
346 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
348 struct nand_chip *chip = mtd->priv;
349 uint8_t buf[2] = { 0, 0 };
352 /* Get block number */
353 block = ((int)ofs) >> chip->bbt_erase_shift;
355 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
357 /* Do we have a flash based bad block table ? */
358 if (chip->options & NAND_USE_FLASH_BBT)
359 ret = nand_update_bbt(mtd, ofs);
361 /* We write two bytes, so we dont have to mess with 16 bit
366 chip->ops.datbuf = NULL;
367 chip->ops.oobbuf = buf;
368 chip->ops.ooboffs = chip->badblockpos & ~0x01;
370 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
373 mtd->ecc_stats.badblocks++;
378 * nand_check_wp - [GENERIC] check if the chip is write protected
379 * @mtd: MTD device structure
380 * Check, if the device is write protected
382 * The function expects, that the device is already selected
384 static int nand_check_wp(struct mtd_info *mtd)
386 struct nand_chip *chip = mtd->priv;
387 /* Check the WP bit */
388 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
389 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
393 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
394 * @mtd: MTD device structure
395 * @ofs: offset from device start
396 * @getchip: 0, if the chip is already selected
397 * @allowbbt: 1, if its allowed to access the bbt area
399 * Check, if the block is bad. Either by reading the bad block table or
400 * calling of the scan function.
402 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
405 struct nand_chip *chip = mtd->priv;
408 return chip->block_bad(mtd, ofs, getchip);
410 /* Return info from the table */
411 return nand_isbad_bbt(mtd, ofs, allowbbt);
415 * Wait for the ready pin, after a command
416 * The timeout is catched later.
418 static void nand_wait_ready(struct mtd_info *mtd)
420 struct nand_chip *chip = mtd->priv;
421 unsigned long timeo = jiffies + 2;
423 led_trigger_event(nand_led_trigger, LED_FULL);
424 /* wait until command is processed or timeout occures */
426 if (chip->dev_ready(mtd))
428 touch_softlockup_watchdog();
429 } while (time_before(jiffies, timeo));
430 led_trigger_event(nand_led_trigger, LED_OFF);
434 * nand_command - [DEFAULT] Send command to NAND device
435 * @mtd: MTD device structure
436 * @command: the command to be sent
437 * @column: the column address for this command, -1 if none
438 * @page_addr: the page address for this command, -1 if none
440 * Send command to NAND device. This function is used for small page
441 * devices (256/512 Bytes per page)
443 static void nand_command(struct mtd_info *mtd, unsigned int command,
444 int column, int page_addr)
446 register struct nand_chip *chip = mtd->priv;
447 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
450 * Write out the command to the device.
452 if (command == NAND_CMD_SEQIN) {
455 if (column >= mtd->writesize) {
457 column -= mtd->writesize;
458 readcmd = NAND_CMD_READOOB;
459 } else if (column < 256) {
460 /* First 256 bytes --> READ0 */
461 readcmd = NAND_CMD_READ0;
464 readcmd = NAND_CMD_READ1;
466 chip->cmd_ctrl(mtd, readcmd, ctrl);
467 ctrl &= ~NAND_CTRL_CHANGE;
469 chip->cmd_ctrl(mtd, command, ctrl);
472 * Address cycle, when necessary
474 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
475 /* Serially input address */
477 /* Adjust columns for 16 bit buswidth */
478 if (chip->options & NAND_BUSWIDTH_16)
480 chip->cmd_ctrl(mtd, column, ctrl);
481 ctrl &= ~NAND_CTRL_CHANGE;
483 if (page_addr != -1) {
484 chip->cmd_ctrl(mtd, page_addr, ctrl);
485 ctrl &= ~NAND_CTRL_CHANGE;
486 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
487 /* One more address cycle for devices > 32MiB */
488 if (chip->chipsize > (32 << 20))
489 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
491 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
494 * program and erase have their own busy handlers
495 * status and sequential in needs no delay
499 case NAND_CMD_PAGEPROG:
500 case NAND_CMD_ERASE1:
501 case NAND_CMD_ERASE2:
503 case NAND_CMD_STATUS:
504 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE);
510 udelay(chip->chip_delay);
511 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
512 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
514 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
515 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
518 /* This applies to read commands */
521 * If we don't have access to the busy pin, we apply the given
524 if (!chip->dev_ready) {
525 udelay(chip->chip_delay);
529 /* Apply this short delay always to ensure that we do wait tWB in
530 * any case on any machine. */
533 nand_wait_ready(mtd);
537 * nand_command_lp - [DEFAULT] Send command to NAND large page device
538 * @mtd: MTD device structure
539 * @command: the command to be sent
540 * @column: the column address for this command, -1 if none
541 * @page_addr: the page address for this command, -1 if none
543 * Send command to NAND device. This is the version for the new large page
544 * devices We dont have the separate regions as we have in the small page
545 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
548 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
549 int column, int page_addr)
551 register struct nand_chip *chip = mtd->priv;
553 /* Emulate NAND_CMD_READOOB */
554 if (command == NAND_CMD_READOOB) {
555 column += mtd->writesize;
556 command = NAND_CMD_READ0;
559 /* Command latch cycle */
560 chip->cmd_ctrl(mtd, command & 0xff,
561 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
563 if (column != -1 || page_addr != -1) {
564 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
566 /* Serially input address */
568 /* Adjust columns for 16 bit buswidth */
569 if (chip->options & NAND_BUSWIDTH_16)
571 chip->cmd_ctrl(mtd, column, ctrl);
572 ctrl &= ~NAND_CTRL_CHANGE;
573 chip->cmd_ctrl(mtd, column >> 8, ctrl);
575 if (page_addr != -1) {
576 chip->cmd_ctrl(mtd, page_addr, ctrl);
577 chip->cmd_ctrl(mtd, page_addr >> 8,
578 NAND_NCE | NAND_ALE);
579 /* One more address cycle for devices > 128MiB */
580 if (chip->chipsize > (128 << 20))
581 chip->cmd_ctrl(mtd, page_addr >> 16,
582 NAND_NCE | NAND_ALE);
585 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
588 * program and erase have their own busy handlers
589 * status, sequential in, and deplete1 need no delay
593 case NAND_CMD_CACHEDPROG:
594 case NAND_CMD_PAGEPROG:
595 case NAND_CMD_ERASE1:
596 case NAND_CMD_ERASE2:
598 case NAND_CMD_STATUS:
599 case NAND_CMD_DEPLETE1:
603 * read error status commands require only a short delay
605 case NAND_CMD_STATUS_ERROR:
606 case NAND_CMD_STATUS_ERROR0:
607 case NAND_CMD_STATUS_ERROR1:
608 case NAND_CMD_STATUS_ERROR2:
609 case NAND_CMD_STATUS_ERROR3:
610 udelay(chip->chip_delay);
616 udelay(chip->chip_delay);
617 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
618 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
619 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
620 NAND_NCE | NAND_CTRL_CHANGE);
621 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
625 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
626 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
627 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
628 NAND_NCE | NAND_CTRL_CHANGE);
630 /* This applies to read commands */
633 * If we don't have access to the busy pin, we apply the given
636 if (!chip->dev_ready) {
637 udelay(chip->chip_delay);
642 /* Apply this short delay always to ensure that we do wait tWB in
643 * any case on any machine. */
646 nand_wait_ready(mtd);
650 * nand_get_device - [GENERIC] Get chip for selected access
651 * @this: the nand chip descriptor
652 * @mtd: MTD device structure
653 * @new_state: the state which is requested
655 * Get the device and lock it for exclusive access
658 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
660 spinlock_t *lock = &chip->controller->lock;
661 wait_queue_head_t *wq = &chip->controller->wq;
662 DECLARE_WAITQUEUE(wait, current);
666 /* Hardware controller shared among independend devices */
667 /* Hardware controller shared among independend devices */
668 if (!chip->controller->active)
669 chip->controller->active = chip;
671 if (chip->controller->active == chip && chip->state == FL_READY) {
672 chip->state = new_state;
676 if (new_state == FL_PM_SUSPENDED) {
678 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
680 set_current_state(TASK_UNINTERRUPTIBLE);
681 add_wait_queue(wq, &wait);
684 remove_wait_queue(wq, &wait);
689 * nand_wait - [DEFAULT] wait until the command is done
690 * @mtd: MTD device structure
691 * @this: NAND chip structure
692 * @state: state to select the max. timeout value
694 * Wait for command done. This applies to erase and program only
695 * Erase can take up to 400ms and program up to 20ms according to
696 * general NAND and SmartMedia specs
699 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
702 unsigned long timeo = jiffies;
705 if (state == FL_ERASING)
706 timeo += (HZ * 400) / 1000;
708 timeo += (HZ * 20) / 1000;
710 led_trigger_event(nand_led_trigger, LED_FULL);
712 /* Apply this short delay always to ensure that we do wait tWB in
713 * any case on any machine. */
716 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
717 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
719 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
721 while (time_before(jiffies, timeo)) {
722 /* Check, if we were interrupted */
723 if (chip->state != state)
726 if (chip->dev_ready) {
727 if (chip->dev_ready(mtd))
730 if (chip->read_byte(mtd) & NAND_STATUS_READY)
735 led_trigger_event(nand_led_trigger, LED_OFF);
737 status = (int)chip->read_byte(mtd);
742 * nand_read_page_raw - [Intern] read raw page data without ecc
743 * @mtd: mtd info structure
744 * @chip: nand chip info structure
745 * @buf: buffer to store read data
747 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
750 chip->read_buf(mtd, buf, mtd->writesize);
751 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
756 * nand_read_page_swecc - {REPLACABLE] software ecc based page read function
757 * @mtd: mtd info structure
758 * @chip: nand chip info structure
759 * @buf: buffer to store read data
761 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
764 int i, eccsize = chip->ecc.size;
765 int eccbytes = chip->ecc.bytes;
766 int eccsteps = chip->ecc.steps;
768 uint8_t *ecc_calc = chip->buffers.ecccalc;
769 uint8_t *ecc_code = chip->buffers.ecccode;
770 int *eccpos = chip->ecc.layout->eccpos;
772 nand_read_page_raw(mtd, chip, buf);
774 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
775 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
777 for (i = 0; i < chip->ecc.total; i++)
778 ecc_code[i] = chip->oob_poi[eccpos[i]];
780 eccsteps = chip->ecc.steps;
783 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
786 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
788 mtd->ecc_stats.failed++;
790 mtd->ecc_stats.corrected += stat;
796 * nand_read_page_hwecc - {REPLACABLE] hardware ecc based page read function
797 * @mtd: mtd info structure
798 * @chip: nand chip info structure
799 * @buf: buffer to store read data
801 * Not for syndrome calculating ecc controllers which need a special oob layout
803 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
806 int i, eccsize = chip->ecc.size;
807 int eccbytes = chip->ecc.bytes;
808 int eccsteps = chip->ecc.steps;
810 uint8_t *ecc_calc = chip->buffers.ecccalc;
811 uint8_t *ecc_code = chip->buffers.ecccode;
812 int *eccpos = chip->ecc.layout->eccpos;
814 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
815 chip->ecc.hwctl(mtd, NAND_ECC_READ);
816 chip->read_buf(mtd, p, eccsize);
817 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
819 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
821 for (i = 0; i < chip->ecc.total; i++)
822 ecc_code[i] = chip->oob_poi[eccpos[i]];
824 eccsteps = chip->ecc.steps;
827 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
830 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
832 mtd->ecc_stats.failed++;
834 mtd->ecc_stats.corrected += stat;
840 * nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
841 * @mtd: mtd info structure
842 * @chip: nand chip info structure
843 * @buf: buffer to store read data
845 * The hw generator calculates the error syndrome automatically. Therefor
846 * we need a special oob layout and handling.
848 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
851 int i, eccsize = chip->ecc.size;
852 int eccbytes = chip->ecc.bytes;
853 int eccsteps = chip->ecc.steps;
855 uint8_t *oob = chip->oob_poi;
857 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
860 chip->ecc.hwctl(mtd, NAND_ECC_READ);
861 chip->read_buf(mtd, p, eccsize);
863 if (chip->ecc.prepad) {
864 chip->read_buf(mtd, oob, chip->ecc.prepad);
865 oob += chip->ecc.prepad;
868 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
869 chip->read_buf(mtd, oob, eccbytes);
870 stat = chip->ecc.correct(mtd, p, oob, NULL);
873 mtd->ecc_stats.failed++;
875 mtd->ecc_stats.corrected += stat;
879 if (chip->ecc.postpad) {
880 chip->read_buf(mtd, oob, chip->ecc.postpad);
881 oob += chip->ecc.postpad;
885 /* Calculate remaining oob bytes */
886 i = oob - chip->oob_poi;
888 chip->read_buf(mtd, oob, i);
894 * nand_transfer_oob - [Internal] Transfer oob to client buffer
895 * @chip: nand chip structure
896 * @ops: oob ops structure
898 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
899 struct mtd_oob_ops *ops)
901 size_t len = ops->ooblen;
907 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
911 struct nand_oobfree *free = chip->ecc.layout->oobfree;
914 for(; free->length && len; free++, len -= bytes) {
915 bytes = min_t(size_t, len, free->length);
917 memcpy(oob, chip->oob_poi + free->offset, bytes);
929 * nand_do_read_ops - [Internal] Read data with ECC
931 * @mtd: MTD device structure
932 * @from: offset to read from
934 * Internal function. Called with chip held.
936 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
937 struct mtd_oob_ops *ops)
939 int chipnr, page, realpage, col, bytes, aligned;
940 struct nand_chip *chip = mtd->priv;
941 struct mtd_ecc_stats stats;
942 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
945 uint32_t readlen = ops->len;
946 uint8_t *bufpoi, *oob, *buf;
948 stats = mtd->ecc_stats;
950 chipnr = (int)(from >> chip->chip_shift);
951 chip->select_chip(mtd, chipnr);
953 realpage = (int)(from >> chip->page_shift);
954 page = realpage & chip->pagemask;
956 col = (int)(from & (mtd->writesize - 1));
957 chip->oob_poi = chip->buffers.oobrbuf;
963 bytes = min(mtd->writesize - col, readlen);
964 aligned = (bytes == mtd->writesize);
966 /* Is the current page in the buffer ? */
967 if (realpage != chip->pagebuf || oob) {
968 bufpoi = aligned ? buf : chip->buffers.databuf;
970 if (likely(sndcmd)) {
971 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
975 /* Now read the page into the buffer */
976 ret = chip->ecc.read_page(mtd, chip, bufpoi);
980 /* Transfer not aligned data */
982 chip->pagebuf = realpage;
983 memcpy(buf, chip->buffers.databuf + col, bytes);
989 /* Raw mode does data:oob:data:oob */
990 if (ops->mode != MTD_OOB_RAW)
991 oob = nand_transfer_oob(chip, oob, ops);
993 buf = nand_transfer_oob(chip, buf, ops);
996 if (!(chip->options & NAND_NO_READRDY)) {
998 * Apply delay or wait for ready/busy pin. Do
999 * this before the AUTOINCR check, so no
1000 * problems arise if a chip which does auto
1001 * increment is marked as NOAUTOINCR by the
1004 if (!chip->dev_ready)
1005 udelay(chip->chip_delay);
1007 nand_wait_ready(mtd);
1010 memcpy(buf, chip->buffers.databuf + col, bytes);
1019 /* For subsequent reads align to page boundary. */
1021 /* Increment page address */
1024 page = realpage & chip->pagemask;
1025 /* Check, if we cross a chip boundary */
1028 chip->select_chip(mtd, -1);
1029 chip->select_chip(mtd, chipnr);
1032 /* Check, if the chip supports auto page increment
1033 * or if we have hit a block boundary.
1035 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1039 ops->retlen = ops->len - (size_t) readlen;
1044 if (mtd->ecc_stats.failed - stats.failed)
1047 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1051 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1052 * @mtd: MTD device structure
1053 * @from: offset to read from
1054 * @len: number of bytes to read
1055 * @retlen: pointer to variable to store the number of read bytes
1056 * @buf: the databuffer to put data
1058 * Get hold of the chip and call nand_do_read
1060 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1061 size_t *retlen, uint8_t *buf)
1063 struct nand_chip *chip = mtd->priv;
1066 /* Do not allow reads past end of device */
1067 if ((from + len) > mtd->size)
1072 nand_get_device(chip, mtd, FL_READING);
1074 chip->ops.len = len;
1075 chip->ops.datbuf = buf;
1076 chip->ops.oobbuf = NULL;
1078 ret = nand_do_read_ops(mtd, from, &chip->ops);
1080 nand_release_device(mtd);
1082 *retlen = chip->ops.retlen;
1087 * nand_do_read_oob - [Intern] NAND read out-of-band
1088 * @mtd: MTD device structure
1089 * @from: offset to read from
1090 * @ops: oob operations description structure
1092 * NAND read out-of-band data from the spare area
1094 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1095 struct mtd_oob_ops *ops)
1097 int col, page, realpage, chipnr, sndcmd = 1;
1098 struct nand_chip *chip = mtd->priv;
1099 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1100 int direct, bytes, readlen = ops->len;
1101 uint8_t *bufpoi, *buf = ops->oobbuf;
1103 DEBUG(MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1104 (unsigned long long)from, readlen);
1106 chipnr = (int)(from >> chip->chip_shift);
1107 chip->select_chip(mtd, chipnr);
1109 /* Shift to get page */
1110 realpage = (int)(from >> chip->page_shift);
1111 page = realpage & chip->pagemask;
1113 if (ops->mode != MTD_OOB_AUTO) {
1122 bytes = direct ? ops->ooblen : mtd->oobsize;
1123 bufpoi = direct ? buf : chip->buffers.oobrbuf;
1125 if (likely(sndcmd)) {
1126 chip->cmdfunc(mtd, NAND_CMD_READOOB, col, page);
1130 chip->read_buf(mtd, bufpoi, bytes);
1132 if (unlikely(!direct))
1133 buf = nand_transfer_oob(chip, buf, ops);
1137 readlen -= ops->ooblen;
1141 if (!(chip->options & NAND_NO_READRDY)) {
1143 * Apply delay or wait for ready/busy pin. Do this
1144 * before the AUTOINCR check, so no problems arise if a
1145 * chip which does auto increment is marked as
1146 * NOAUTOINCR by the board driver.
1148 if (!chip->dev_ready)
1149 udelay(chip->chip_delay);
1151 nand_wait_ready(mtd);
1154 /* Increment page address */
1157 page = realpage & chip->pagemask;
1158 /* Check, if we cross a chip boundary */
1161 chip->select_chip(mtd, -1);
1162 chip->select_chip(mtd, chipnr);
1165 /* Check, if the chip supports auto page increment
1166 * or if we have hit a block boundary.
1168 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1172 ops->retlen = ops->len;
1177 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1178 * @mtd: MTD device structure
1179 * @from: offset to read from
1180 * @ops: oob operation description structure
1182 * NAND read data and/or out-of-band data
1184 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1185 struct mtd_oob_ops *ops)
1187 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
1188 uint8_t *buf) = NULL;
1189 struct nand_chip *chip = mtd->priv;
1190 int ret = -ENOTSUPP;
1194 /* Do not allow reads past end of device */
1195 if ((from + ops->len) > mtd->size) {
1196 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1197 "Attempt read beyond end of device\n");
1201 nand_get_device(chip, mtd, FL_READING);
1209 /* Replace the read_page algorithm temporary */
1210 read_page = chip->ecc.read_page;
1211 chip->ecc.read_page = nand_read_page_raw;
1219 ret = nand_do_read_oob(mtd, from, ops);
1221 ret = nand_do_read_ops(mtd, from, ops);
1223 if (unlikely(ops->mode == MTD_OOB_RAW))
1224 chip->ecc.read_page = read_page;
1226 nand_release_device(mtd);
1232 * nand_write_page_raw - [Intern] raw page write function
1233 * @mtd: mtd info structure
1234 * @chip: nand chip info structure
1237 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1240 chip->write_buf(mtd, buf, mtd->writesize);
1241 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1245 * nand_write_page_swecc - {REPLACABLE] software ecc based page write function
1246 * @mtd: mtd info structure
1247 * @chip: nand chip info structure
1250 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1253 int i, eccsize = chip->ecc.size;
1254 int eccbytes = chip->ecc.bytes;
1255 int eccsteps = chip->ecc.steps;
1256 uint8_t *ecc_calc = chip->buffers.ecccalc;
1257 const uint8_t *p = buf;
1258 int *eccpos = chip->ecc.layout->eccpos;
1260 /* Software ecc calculation */
1261 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1262 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1264 for (i = 0; i < chip->ecc.total; i++)
1265 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1267 nand_write_page_raw(mtd, chip, buf);
1271 * nand_write_page_hwecc - {REPLACABLE] hardware ecc based page write function
1272 * @mtd: mtd info structure
1273 * @chip: nand chip info structure
1276 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1279 int i, eccsize = chip->ecc.size;
1280 int eccbytes = chip->ecc.bytes;
1281 int eccsteps = chip->ecc.steps;
1282 uint8_t *ecc_calc = chip->buffers.ecccalc;
1283 const uint8_t *p = buf;
1284 int *eccpos = chip->ecc.layout->eccpos;
1286 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1287 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1288 chip->write_buf(mtd, p, eccsize);
1289 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1292 for (i = 0; i < chip->ecc.total; i++)
1293 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1295 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1299 * nand_write_page_syndrome - {REPLACABLE] hardware ecc syndrom based page write
1300 * @mtd: mtd info structure
1301 * @chip: nand chip info structure
1304 * The hw generator calculates the error syndrome automatically. Therefor
1305 * we need a special oob layout and handling.
1307 static void nand_write_page_syndrome(struct mtd_info *mtd,
1308 struct nand_chip *chip, const uint8_t *buf)
1310 int i, eccsize = chip->ecc.size;
1311 int eccbytes = chip->ecc.bytes;
1312 int eccsteps = chip->ecc.steps;
1313 const uint8_t *p = buf;
1314 uint8_t *oob = chip->oob_poi;
1316 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1318 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1319 chip->write_buf(mtd, p, eccsize);
1321 if (chip->ecc.prepad) {
1322 chip->write_buf(mtd, oob, chip->ecc.prepad);
1323 oob += chip->ecc.prepad;
1326 chip->ecc.calculate(mtd, p, oob);
1327 chip->write_buf(mtd, oob, eccbytes);
1330 if (chip->ecc.postpad) {
1331 chip->write_buf(mtd, oob, chip->ecc.postpad);
1332 oob += chip->ecc.postpad;
1336 /* Calculate remaining oob bytes */
1337 i = oob - chip->oob_poi;
1339 chip->write_buf(mtd, oob, i);
1343 * nand_write_page - [INTERNAL] write one page
1344 * @mtd: MTD device structure
1345 * @chip: NAND chip descriptor
1346 * @buf: the data to write
1347 * @page: page number to write
1348 * @cached: cached programming
1350 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1351 const uint8_t *buf, int page, int cached)
1355 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1357 chip->ecc.write_page(mtd, chip, buf);
1360 * Cached progamming disabled for now, Not sure if its worth the
1361 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1365 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1367 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1368 status = chip->waitfunc(mtd, chip, FL_WRITING);
1370 * See if operation failed and additional status checks are
1373 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1374 status = chip->errstat(mtd, chip, FL_WRITING, status,
1377 if (status & NAND_STATUS_FAIL)
1380 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1381 status = chip->waitfunc(mtd, chip, FL_WRITING);
1384 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1385 /* Send command to read back the data */
1386 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1388 if (chip->verify_buf(mtd, buf, mtd->writesize))
1395 * nand_fill_oob - [Internal] Transfer client buffer to oob
1396 * @chip: nand chip structure
1397 * @oob: oob data buffer
1398 * @ops: oob ops structure
1400 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1401 struct mtd_oob_ops *ops)
1403 size_t len = ops->ooblen;
1409 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1412 case MTD_OOB_AUTO: {
1413 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1416 for(; free->length && len; free++, len -= bytes) {
1417 bytes = min_t(size_t, len, free->length);
1418 memcpy(chip->oob_poi + free->offset, oob, bytes);
1429 #define NOTALIGNED(x) (x & (mtd->writesize-1)) != 0
1432 * nand_do_write_ops - [Internal] NAND write with ECC
1433 * @mtd: MTD device structure
1434 * @to: offset to write to
1435 * @ops: oob operations description structure
1437 * NAND write with ECC
1439 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1440 struct mtd_oob_ops *ops)
1442 int chipnr, realpage, page, blockmask;
1443 struct nand_chip *chip = mtd->priv;
1444 uint32_t writelen = ops->len;
1445 uint8_t *oob = ops->oobbuf;
1446 uint8_t *buf = ops->datbuf;
1447 int bytes = mtd->writesize;
1452 /* reject writes, which are not page aligned */
1453 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1454 printk(KERN_NOTICE "nand_write: "
1455 "Attempt to write not page aligned data\n");
1462 /* Check, if it is write protected */
1463 if (nand_check_wp(mtd))
1466 chipnr = (int)(to >> chip->chip_shift);
1467 chip->select_chip(mtd, chipnr);
1469 realpage = (int)(to >> chip->page_shift);
1470 page = realpage & chip->pagemask;
1471 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1473 /* Invalidate the page cache, when we write to the cached page */
1474 if (to <= (chip->pagebuf << chip->page_shift) &&
1475 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1478 chip->oob_poi = chip->buffers.oobwbuf;
1481 int cached = writelen > bytes && page != blockmask;
1484 oob = nand_fill_oob(chip, oob, ops);
1486 ret = nand_write_page(mtd, chip, buf, page, cached);
1497 page = realpage & chip->pagemask;
1498 /* Check, if we cross a chip boundary */
1501 chip->select_chip(mtd, -1);
1502 chip->select_chip(mtd, chipnr);
1507 memset(chip->oob_poi, 0xff, mtd->oobsize);
1509 ops->retlen = ops->len - writelen;
1514 * nand_write - [MTD Interface] NAND write with ECC
1515 * @mtd: MTD device structure
1516 * @to: offset to write to
1517 * @len: number of bytes to write
1518 * @retlen: pointer to variable to store the number of written bytes
1519 * @buf: the data to write
1521 * NAND write with ECC
1523 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1524 size_t *retlen, const uint8_t *buf)
1526 struct nand_chip *chip = mtd->priv;
1529 /* Do not allow reads past end of device */
1530 if ((to + len) > mtd->size)
1535 nand_get_device(chip, mtd, FL_READING);
1537 chip->ops.len = len;
1538 chip->ops.datbuf = (uint8_t *)buf;
1539 chip->ops.oobbuf = NULL;
1541 ret = nand_do_write_ops(mtd, to, &chip->ops);
1543 nand_release_device(mtd);
1545 *retlen = chip->ops.retlen;
1550 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1551 * @mtd: MTD device structure
1552 * @to: offset to write to
1553 * @ops: oob operation description structure
1555 * NAND write out-of-band
1557 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1558 struct mtd_oob_ops *ops)
1560 int chipnr, page, status;
1561 struct nand_chip *chip = mtd->priv;
1563 DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1564 (unsigned int)to, (int)ops->len);
1566 /* Do not allow write past end of page */
1567 if ((ops->ooboffs + ops->len) > mtd->oobsize) {
1568 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1569 "Attempt to write past end of page\n");
1573 chipnr = (int)(to >> chip->chip_shift);
1574 chip->select_chip(mtd, chipnr);
1576 /* Shift to get page */
1577 page = (int)(to >> chip->page_shift);
1580 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1581 * of my DiskOnChip 2000 test units) will clear the whole data page too
1582 * if we don't do this. I have no clue why, but I seem to have 'fixed'
1583 * it in the doc2000 driver in August 1999. dwmw2.
1585 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1587 /* Check, if it is write protected */
1588 if (nand_check_wp(mtd))
1591 /* Invalidate the page cache, if we write to the cached page */
1592 if (page == chip->pagebuf)
1595 if (ops->mode == MTD_OOB_AUTO || NAND_MUST_PAD(chip)) {
1596 chip->oob_poi = chip->buffers.oobwbuf;
1597 memset(chip->oob_poi, 0xff, mtd->oobsize);
1598 nand_fill_oob(chip, ops->oobbuf, ops);
1599 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize,
1600 page & chip->pagemask);
1601 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1602 memset(chip->oob_poi, 0xff, mtd->oobsize);
1604 chip->cmdfunc(mtd, NAND_CMD_SEQIN,
1605 mtd->writesize + ops->ooboffs,
1606 page & chip->pagemask);
1607 chip->write_buf(mtd, ops->oobbuf, ops->len);
1610 /* Send command to program the OOB data */
1611 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1613 status = chip->waitfunc(mtd, chip, FL_WRITING);
1615 /* See if device thinks it succeeded */
1616 if (status & NAND_STATUS_FAIL) {
1617 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1618 "Failed write, page 0x%08x\n", page);
1621 ops->retlen = ops->len;
1623 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1624 if (ops->mode != MTD_OOB_AUTO) {
1625 /* Send command to read back the data */
1626 chip->cmdfunc(mtd, NAND_CMD_READOOB, ops->ooboffs,
1627 page & chip->pagemask);
1629 if (chip->verify_buf(mtd, ops->oobbuf, ops->len)) {
1630 DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
1631 "Failed write verify, page 0x%08x\n", page);
1640 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1641 * @mtd: MTD device structure
1642 * @from: offset to read from
1643 * @ops: oob operation description structure
1645 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1646 struct mtd_oob_ops *ops)
1648 void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
1649 const uint8_t *buf) = NULL;
1650 struct nand_chip *chip = mtd->priv;
1651 int ret = -ENOTSUPP;
1655 /* Do not allow writes past end of device */
1656 if ((to + ops->len) > mtd->size) {
1657 DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
1658 "Attempt read beyond end of device\n");
1662 nand_get_device(chip, mtd, FL_READING);
1670 /* Replace the write_page algorithm temporary */
1671 write_page = chip->ecc.write_page;
1672 chip->ecc.write_page = nand_write_page_raw;
1680 ret = nand_do_write_oob(mtd, to, ops);
1682 ret = nand_do_write_ops(mtd, to, ops);
1684 if (unlikely(ops->mode == MTD_OOB_RAW))
1685 chip->ecc.write_page = write_page;
1687 nand_release_device(mtd);
1692 * single_erease_cmd - [GENERIC] NAND standard block erase command function
1693 * @mtd: MTD device structure
1694 * @page: the page address of the block which will be erased
1696 * Standard erase command for NAND chips
1698 static void single_erase_cmd(struct mtd_info *mtd, int page)
1700 struct nand_chip *chip = mtd->priv;
1701 /* Send commands to erase a block */
1702 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1703 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1707 * multi_erease_cmd - [GENERIC] AND specific block erase command function
1708 * @mtd: MTD device structure
1709 * @page: the page address of the block which will be erased
1711 * AND multi block erase command function
1712 * Erase 4 consecutive blocks
1714 static void multi_erase_cmd(struct mtd_info *mtd, int page)
1716 struct nand_chip *chip = mtd->priv;
1717 /* Send commands to erase a block */
1718 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1719 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1720 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
1721 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
1722 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
1726 * nand_erase - [MTD Interface] erase block(s)
1727 * @mtd: MTD device structure
1728 * @instr: erase instruction
1730 * Erase one ore more blocks
1732 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1734 return nand_erase_nand(mtd, instr, 0);
1737 #define BBT_PAGE_MASK 0xffffff3f
1739 * nand_erase_nand - [Internal] erase block(s)
1740 * @mtd: MTD device structure
1741 * @instr: erase instruction
1742 * @allowbbt: allow erasing the bbt area
1744 * Erase one ore more blocks
1746 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1749 int page, len, status, pages_per_block, ret, chipnr;
1750 struct nand_chip *chip = mtd->priv;
1751 int rewrite_bbt[NAND_MAX_CHIPS]={0};
1752 unsigned int bbt_masked_page = 0xffffffff;
1754 DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
1755 (unsigned int)instr->addr, (unsigned int)instr->len);
1757 /* Start address must align on block boundary */
1758 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
1759 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
1763 /* Length must align on block boundary */
1764 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
1765 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1766 "Length not block aligned\n");
1770 /* Do not allow erase past end of device */
1771 if ((instr->len + instr->addr) > mtd->size) {
1772 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1773 "Erase past end of device\n");
1777 instr->fail_addr = 0xffffffff;
1779 /* Grab the lock and see if the device is available */
1780 nand_get_device(chip, mtd, FL_ERASING);
1782 /* Shift to get first page */
1783 page = (int)(instr->addr >> chip->page_shift);
1784 chipnr = (int)(instr->addr >> chip->chip_shift);
1786 /* Calculate pages in each block */
1787 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
1789 /* Select the NAND device */
1790 chip->select_chip(mtd, chipnr);
1792 /* Check, if it is write protected */
1793 if (nand_check_wp(mtd)) {
1794 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1795 "Device is write protected!!!\n");
1796 instr->state = MTD_ERASE_FAILED;
1801 * If BBT requires refresh, set the BBT page mask to see if the BBT
1802 * should be rewritten. Otherwise the mask is set to 0xffffffff which
1803 * can not be matched. This is also done when the bbt is actually
1804 * erased to avoid recusrsive updates
1806 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
1807 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
1809 /* Loop through the pages */
1812 instr->state = MTD_ERASING;
1816 * heck if we have a bad block, we do not erase bad blocks !
1818 if (nand_block_checkbad(mtd, ((loff_t) page) <<
1819 chip->page_shift, 0, allowbbt)) {
1820 printk(KERN_WARNING "nand_erase: attempt to erase a "
1821 "bad block at page 0x%08x\n", page);
1822 instr->state = MTD_ERASE_FAILED;
1827 * Invalidate the page cache, if we erase the block which
1828 * contains the current cached page
1830 if (page <= chip->pagebuf && chip->pagebuf <
1831 (page + pages_per_block))
1834 chip->erase_cmd(mtd, page & chip->pagemask);
1836 status = chip->waitfunc(mtd, chip, FL_ERASING);
1839 * See if operation failed and additional status checks are
1842 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1843 status = chip->errstat(mtd, chip, FL_ERASING,
1846 /* See if block erase succeeded */
1847 if (status & NAND_STATUS_FAIL) {
1848 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
1849 "Failed erase, page 0x%08x\n", page);
1850 instr->state = MTD_ERASE_FAILED;
1851 instr->fail_addr = (page << chip->page_shift);
1856 * If BBT requires refresh, set the BBT rewrite flag to the
1859 if (bbt_masked_page != 0xffffffff &&
1860 (page & BBT_PAGE_MASK) == bbt_masked_page)
1861 rewrite_bbt[chipnr] = (page << chip->page_shift);
1863 /* Increment page address and decrement length */
1864 len -= (1 << chip->phys_erase_shift);
1865 page += pages_per_block;
1867 /* Check, if we cross a chip boundary */
1868 if (len && !(page & chip->pagemask)) {
1870 chip->select_chip(mtd, -1);
1871 chip->select_chip(mtd, chipnr);
1874 * If BBT requires refresh and BBT-PERCHIP, set the BBT
1875 * page mask to see if this BBT should be rewritten
1877 if (bbt_masked_page != 0xffffffff &&
1878 (chip->bbt_td->options & NAND_BBT_PERCHIP))
1879 bbt_masked_page = chip->bbt_td->pages[chipnr] &
1883 instr->state = MTD_ERASE_DONE;
1887 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
1888 /* Do call back function */
1890 mtd_erase_callback(instr);
1892 /* Deselect and wake up anyone waiting on the device */
1893 nand_release_device(mtd);
1896 * If BBT requires refresh and erase was successful, rewrite any
1897 * selected bad block tables
1899 if (bbt_masked_page == 0xffffffff || ret)
1902 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
1903 if (!rewrite_bbt[chipnr])
1905 /* update the BBT for chip */
1906 DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
1907 "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
1908 chip->bbt_td->pages[chipnr]);
1909 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
1912 /* Return more or less happy */
1917 * nand_sync - [MTD Interface] sync
1918 * @mtd: MTD device structure
1920 * Sync is actually a wait for chip ready function
1922 static void nand_sync(struct mtd_info *mtd)
1924 struct nand_chip *chip = mtd->priv;
1926 DEBUG(MTD_DEBUG_LEVEL3, "nand_sync: called\n");
1928 /* Grab the lock and see if the device is available */
1929 nand_get_device(chip, mtd, FL_SYNCING);
1930 /* Release it and go back */
1931 nand_release_device(mtd);
1935 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
1936 * @mtd: MTD device structure
1937 * @ofs: offset relative to mtd start
1939 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1941 /* Check for invalid offset */
1942 if (offs > mtd->size)
1945 return nand_block_checkbad(mtd, offs, 1, 0);
1949 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
1950 * @mtd: MTD device structure
1951 * @ofs: offset relative to mtd start
1953 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1955 struct nand_chip *chip = mtd->priv;
1958 if ((ret = nand_block_isbad(mtd, ofs))) {
1959 /* If it was bad already, return success and do nothing. */
1965 return chip->block_markbad(mtd, ofs);
1969 * nand_suspend - [MTD Interface] Suspend the NAND flash
1970 * @mtd: MTD device structure
1972 static int nand_suspend(struct mtd_info *mtd)
1974 struct nand_chip *chip = mtd->priv;
1976 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
1980 * nand_resume - [MTD Interface] Resume the NAND flash
1981 * @mtd: MTD device structure
1983 static void nand_resume(struct mtd_info *mtd)
1985 struct nand_chip *chip = mtd->priv;
1987 if (chip->state == FL_PM_SUSPENDED)
1988 nand_release_device(mtd);
1990 printk(KERN_ERR "nand_resume() called for a chip which is not "
1991 "in suspended state\n");
1995 * Set default functions
1997 static void nand_set_defaults(struct nand_chip *chip, int busw)
1999 /* check for proper chip_delay setup, set 20us if not */
2000 if (!chip->chip_delay)
2001 chip->chip_delay = 20;
2003 /* check, if a user supplied command function given */
2004 if (chip->cmdfunc == NULL)
2005 chip->cmdfunc = nand_command;
2007 /* check, if a user supplied wait function given */
2008 if (chip->waitfunc == NULL)
2009 chip->waitfunc = nand_wait;
2011 if (!chip->select_chip)
2012 chip->select_chip = nand_select_chip;
2013 if (!chip->read_byte)
2014 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2015 if (!chip->read_word)
2016 chip->read_word = nand_read_word;
2017 if (!chip->block_bad)
2018 chip->block_bad = nand_block_bad;
2019 if (!chip->block_markbad)
2020 chip->block_markbad = nand_default_block_markbad;
2021 if (!chip->write_buf)
2022 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2023 if (!chip->read_buf)
2024 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2025 if (!chip->verify_buf)
2026 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2027 if (!chip->scan_bbt)
2028 chip->scan_bbt = nand_default_bbt;
2030 if (!chip->controller) {
2031 chip->controller = &chip->hwcontrol;
2032 spin_lock_init(&chip->controller->lock);
2033 init_waitqueue_head(&chip->controller->wq);
2039 * Get the flash and manufacturer id and lookup if the type is supported
2041 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2042 struct nand_chip *chip,
2043 int busw, int *maf_id)
2045 struct nand_flash_dev *type = NULL;
2046 int i, dev_id, maf_idx;
2048 /* Select the device */
2049 chip->select_chip(mtd, 0);
2051 /* Send the command for reading device ID */
2052 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2054 /* Read manufacturer and device IDs */
2055 *maf_id = chip->read_byte(mtd);
2056 dev_id = chip->read_byte(mtd);
2058 /* Lookup the flash id */
2059 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2060 if (dev_id == nand_flash_ids[i].id) {
2061 type = &nand_flash_ids[i];
2067 return ERR_PTR(-ENODEV);
2070 mtd->name = type->name;
2072 chip->chipsize = type->chipsize << 20;
2074 /* Newer devices have all the information in additional id bytes */
2075 if (!type->pagesize) {
2077 /* The 3rd id byte contains non relevant data ATM */
2078 extid = chip->read_byte(mtd);
2079 /* The 4th id byte is the important one */
2080 extid = chip->read_byte(mtd);
2082 mtd->writesize = 1024 << (extid & 0x3);
2085 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2087 /* Calc blocksize. Blocksize is multiples of 64KiB */
2088 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2090 /* Get buswidth information */
2091 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2095 * Old devices have chip data hardcoded in the device id table
2097 mtd->erasesize = type->erasesize;
2098 mtd->writesize = type->pagesize;
2099 mtd->oobsize = mtd->writesize / 32;
2100 busw = type->options & NAND_BUSWIDTH_16;
2103 /* Try to identify manufacturer */
2104 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_id++) {
2105 if (nand_manuf_ids[maf_idx].id == *maf_id)
2110 * Check, if buswidth is correct. Hardware drivers should set
2113 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2114 printk(KERN_INFO "NAND device: Manufacturer ID:"
2115 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2116 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2117 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2118 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2120 return ERR_PTR(-EINVAL);
2123 /* Calculate the address shift from the page size */
2124 chip->page_shift = ffs(mtd->writesize) - 1;
2125 /* Convert chipsize to number of pages per chip -1. */
2126 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2128 chip->bbt_erase_shift = chip->phys_erase_shift =
2129 ffs(mtd->erasesize) - 1;
2130 chip->chip_shift = ffs(chip->chipsize) - 1;
2132 /* Set the bad block position */
2133 chip->badblockpos = mtd->writesize > 512 ?
2134 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2136 /* Get chip options, preserve non chip based options */
2137 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2138 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2141 * Set chip as a default. Board drivers can override it, if necessary
2143 chip->options |= NAND_NO_AUTOINCR;
2145 /* Check if chip is a not a samsung device. Do not clear the
2146 * options for chips which are not having an extended id.
2148 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2149 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2151 /* Check for AND chips with 4 page planes */
2152 if (chip->options & NAND_4PAGE_ARRAY)
2153 chip->erase_cmd = multi_erase_cmd;
2155 chip->erase_cmd = single_erase_cmd;
2157 /* Do not replace user supplied command function ! */
2158 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2159 chip->cmdfunc = nand_command_lp;
2161 printk(KERN_INFO "NAND device: Manufacturer ID:"
2162 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2163 nand_manuf_ids[maf_idx].name, type->name);
2168 /* module_text_address() isn't exported, and it's mostly a pointless
2169 test if this is a module _anyway_ -- they'd have to try _really_ hard
2170 to call us from in-kernel code if the core NAND support is modular. */
2172 #define caller_is_module() (1)
2174 #define caller_is_module() \
2175 module_text_address((unsigned long)__builtin_return_address(0))
2179 * nand_scan - [NAND Interface] Scan for the NAND device
2180 * @mtd: MTD device structure
2181 * @maxchips: Number of chips to scan for
2183 * This fills out all the uninitialized function pointers
2184 * with the defaults.
2185 * The flash ID is read and the mtd/chip structures are
2186 * filled with the appropriate values.
2187 * The mtd->owner field must be set to the module of the caller
2190 int nand_scan(struct mtd_info *mtd, int maxchips)
2192 int i, busw, nand_maf_id;
2193 struct nand_chip *chip = mtd->priv;
2194 struct nand_flash_dev *type;
2196 /* Many callers got this wrong, so check for it for a while... */
2197 if (!mtd->owner && caller_is_module()) {
2198 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2202 /* Get buswidth to select the correct functions */
2203 busw = chip->options & NAND_BUSWIDTH_16;
2204 /* Set the default functions */
2205 nand_set_defaults(chip, busw);
2207 /* Read the flash type */
2208 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2211 printk(KERN_WARNING "No NAND device found!!!\n");
2212 chip->select_chip(mtd, -1);
2213 return PTR_ERR(type);
2216 /* Check for a chip array */
2217 for (i = 1; i < maxchips; i++) {
2218 chip->select_chip(mtd, i);
2219 /* Send the command for reading device ID */
2220 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2221 /* Read manufacturer and device IDs */
2222 if (nand_maf_id != chip->read_byte(mtd) ||
2223 type->id != chip->read_byte(mtd))
2227 printk(KERN_INFO "%d NAND chips detected\n", i);
2229 /* Store the number of chips and calc total size for mtd */
2231 mtd->size = i * chip->chipsize;
2233 /* Preset the internal oob write buffer */
2234 memset(chip->buffers.oobwbuf, 0xff, mtd->oobsize);
2237 * If no default placement scheme is given, select an appropriate one
2239 if (!chip->ecc.layout) {
2240 switch (mtd->oobsize) {
2242 chip->ecc.layout = &nand_oob_8;
2245 chip->ecc.layout = &nand_oob_16;
2248 chip->ecc.layout = &nand_oob_64;
2251 printk(KERN_WARNING "No oob scheme defined for "
2252 "oobsize %d\n", mtd->oobsize);
2258 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2259 * selected and we have 256 byte pagesize fallback to software ECC
2261 switch (chip->ecc.mode) {
2263 /* Use standard hwecc read page function ? */
2264 if (!chip->ecc.read_page)
2265 chip->ecc.read_page = nand_read_page_hwecc;
2266 if (!chip->ecc.write_page)
2267 chip->ecc.write_page = nand_write_page_hwecc;
2269 case NAND_ECC_HW_SYNDROME:
2270 if (!chip->ecc.calculate || !chip->ecc.correct ||
2272 printk(KERN_WARNING "No ECC functions supplied, "
2273 "Hardware ECC not possible\n");
2276 /* Use standard syndrome read/write page function ? */
2277 if (!chip->ecc.read_page)
2278 chip->ecc.read_page = nand_read_page_syndrome;
2279 if (!chip->ecc.write_page)
2280 chip->ecc.write_page = nand_write_page_syndrome;
2282 if (mtd->writesize >= chip->ecc.size)
2284 printk(KERN_WARNING "%d byte HW ECC not possible on "
2285 "%d byte page size, fallback to SW ECC\n",
2286 chip->ecc.size, mtd->writesize);
2287 chip->ecc.mode = NAND_ECC_SOFT;
2290 chip->ecc.calculate = nand_calculate_ecc;
2291 chip->ecc.correct = nand_correct_data;
2292 chip->ecc.read_page = nand_read_page_swecc;
2293 chip->ecc.write_page = nand_write_page_swecc;
2294 chip->ecc.size = 256;
2295 chip->ecc.bytes = 3;
2299 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2300 "This is not recommended !!\n");
2301 chip->ecc.read_page = nand_read_page_raw;
2302 chip->ecc.write_page = nand_write_page_raw;
2303 chip->ecc.size = mtd->writesize;
2304 chip->ecc.bytes = 0;
2307 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2313 * The number of bytes available for a client to place data into
2314 * the out of band area
2316 chip->ecc.layout->oobavail = 0;
2317 for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2318 chip->ecc.layout->oobavail +=
2319 chip->ecc.layout->oobfree[i].length;
2322 * Set the number of read / write steps for one page depending on ECC
2325 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2326 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2327 printk(KERN_WARNING "Invalid ecc parameters\n");
2330 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2332 /* Initialize state */
2333 chip->state = FL_READY;
2335 /* De-select the device */
2336 chip->select_chip(mtd, -1);
2338 /* Invalidate the pagebuffer reference */
2341 /* Fill in remaining MTD driver data */
2342 mtd->type = MTD_NANDFLASH;
2343 mtd->flags = MTD_CAP_NANDFLASH;
2344 mtd->ecctype = MTD_ECC_SW;
2345 mtd->erase = nand_erase;
2347 mtd->unpoint = NULL;
2348 mtd->read = nand_read;
2349 mtd->write = nand_write;
2350 mtd->read_oob = nand_read_oob;
2351 mtd->write_oob = nand_write_oob;
2352 mtd->sync = nand_sync;
2355 mtd->suspend = nand_suspend;
2356 mtd->resume = nand_resume;
2357 mtd->block_isbad = nand_block_isbad;
2358 mtd->block_markbad = nand_block_markbad;
2360 /* propagate ecc.layout to mtd_info */
2361 mtd->ecclayout = chip->ecc.layout;
2363 /* Check, if we should skip the bad block table scan */
2364 if (chip->options & NAND_SKIP_BBTSCAN)
2367 /* Build bad block table */
2368 return chip->scan_bbt(mtd);
2372 * nand_release - [NAND Interface] Free resources held by the NAND device
2373 * @mtd: MTD device structure
2375 void nand_release(struct mtd_info *mtd)
2377 struct nand_chip *chip = mtd->priv;
2379 #ifdef CONFIG_MTD_PARTITIONS
2380 /* Deregister partitions */
2381 del_mtd_partitions(mtd);
2383 /* Deregister the device */
2384 del_mtd_device(mtd);
2386 /* Free bad block table memory */
2390 EXPORT_SYMBOL_GPL(nand_scan);
2391 EXPORT_SYMBOL_GPL(nand_release);
2393 static int __init nand_base_init(void)
2395 led_trigger_register_simple("nand-disk", &nand_led_trigger);
2399 static void __exit nand_base_exit(void)
2401 led_trigger_unregister_simple(nand_led_trigger);
2404 module_init(nand_base_init);
2405 module_exit(nand_base_exit);
2407 MODULE_LICENSE("GPL");
2408 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2409 MODULE_DESCRIPTION("Generic NAND flash driver code");