2 * Copyright 2004-2008 Freescale Semiconductor, Inc.
3 * Copyright 2009 Semihalf.
5 * Approved as OSADL project by a majority of OSADL members and funded
6 * by OSADL membership fees in 2009; for details see www.osadl.org.
8 * Based on original driver from Freescale Semiconductor
9 * written by John Rigby <jrigby@freescale.com> on basis
10 * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
11 * Piotr Ziecik <kosmo@semihalf.com>.
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 #include <linux/module.h>
29 #include <linux/clk.h>
30 #include <linux/gfp.h>
31 #include <linux/delay.h>
32 #include <linux/err.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/partitions.h>
39 #include <linux/of_device.h>
40 #include <linux/of_platform.h>
42 #include <asm/mpc5121.h>
44 /* Addresses for NFC MAIN RAM BUFFER areas */
45 #define NFC_MAIN_AREA(n) ((n) * 0x200)
47 /* Addresses for NFC SPARE BUFFER areas */
48 #define NFC_SPARE_BUFFERS 8
49 #define NFC_SPARE_LEN 0x40
50 #define NFC_SPARE_AREA(n) (0x1000 + ((n) * NFC_SPARE_LEN))
52 /* MPC5121 NFC registers */
53 #define NFC_BUF_ADDR 0x1E04
54 #define NFC_FLASH_ADDR 0x1E06
55 #define NFC_FLASH_CMD 0x1E08
56 #define NFC_CONFIG 0x1E0A
57 #define NFC_ECC_STATUS1 0x1E0C
58 #define NFC_ECC_STATUS2 0x1E0E
59 #define NFC_SPAS 0x1E10
60 #define NFC_WRPROT 0x1E12
61 #define NFC_NF_WRPRST 0x1E18
62 #define NFC_CONFIG1 0x1E1A
63 #define NFC_CONFIG2 0x1E1C
64 #define NFC_UNLOCKSTART_BLK0 0x1E20
65 #define NFC_UNLOCKEND_BLK0 0x1E22
66 #define NFC_UNLOCKSTART_BLK1 0x1E24
67 #define NFC_UNLOCKEND_BLK1 0x1E26
68 #define NFC_UNLOCKSTART_BLK2 0x1E28
69 #define NFC_UNLOCKEND_BLK2 0x1E2A
70 #define NFC_UNLOCKSTART_BLK3 0x1E2C
71 #define NFC_UNLOCKEND_BLK3 0x1E2E
73 /* Bit Definitions: NFC_BUF_ADDR */
74 #define NFC_RBA_MASK (7 << 0)
75 #define NFC_ACTIVE_CS_SHIFT 5
76 #define NFC_ACTIVE_CS_MASK (3 << NFC_ACTIVE_CS_SHIFT)
78 /* Bit Definitions: NFC_CONFIG */
79 #define NFC_BLS_UNLOCKED (1 << 1)
81 /* Bit Definitions: NFC_CONFIG1 */
82 #define NFC_ECC_4BIT (1 << 0)
83 #define NFC_FULL_PAGE_DMA (1 << 1)
84 #define NFC_SPARE_ONLY (1 << 2)
85 #define NFC_ECC_ENABLE (1 << 3)
86 #define NFC_INT_MASK (1 << 4)
87 #define NFC_BIG_ENDIAN (1 << 5)
88 #define NFC_RESET (1 << 6)
89 #define NFC_CE (1 << 7)
90 #define NFC_ONE_CYCLE (1 << 8)
91 #define NFC_PPB_32 (0 << 9)
92 #define NFC_PPB_64 (1 << 9)
93 #define NFC_PPB_128 (2 << 9)
94 #define NFC_PPB_256 (3 << 9)
95 #define NFC_PPB_MASK (3 << 9)
96 #define NFC_FULL_PAGE_INT (1 << 11)
98 /* Bit Definitions: NFC_CONFIG2 */
99 #define NFC_COMMAND (1 << 0)
100 #define NFC_ADDRESS (1 << 1)
101 #define NFC_INPUT (1 << 2)
102 #define NFC_OUTPUT (1 << 3)
103 #define NFC_ID (1 << 4)
104 #define NFC_STATUS (1 << 5)
105 #define NFC_CMD_FAIL (1 << 15)
106 #define NFC_INT (1 << 15)
108 /* Bit Definitions: NFC_WRPROT */
109 #define NFC_WPC_LOCK_TIGHT (1 << 0)
110 #define NFC_WPC_LOCK (1 << 1)
111 #define NFC_WPC_UNLOCK (1 << 2)
113 #define DRV_NAME "mpc5121_nfc"
116 #define NFC_RESET_TIMEOUT 1000 /* 1 ms */
117 #define NFC_TIMEOUT (HZ / 10) /* 1/10 s */
119 struct mpc5121_nfc_prv {
121 struct nand_chip chip;
125 wait_queue_head_t irq_waitq;
132 static void mpc5121_nfc_done(struct mtd_info *mtd);
134 static const char *mpc5121_nfc_pprobes[] = { "cmdlinepart", NULL };
136 /* Read NFC register */
137 static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
139 struct nand_chip *chip = mtd->priv;
140 struct mpc5121_nfc_prv *prv = chip->priv;
142 return in_be16(prv->regs + reg);
145 /* Write NFC register */
146 static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
148 struct nand_chip *chip = mtd->priv;
149 struct mpc5121_nfc_prv *prv = chip->priv;
151 out_be16(prv->regs + reg, val);
154 /* Set bits in NFC register */
155 static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
157 nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
160 /* Clear bits in NFC register */
161 static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
163 nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
166 /* Invoke address cycle */
167 static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
169 nfc_write(mtd, NFC_FLASH_ADDR, addr);
170 nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
171 mpc5121_nfc_done(mtd);
174 /* Invoke command cycle */
175 static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
177 nfc_write(mtd, NFC_FLASH_CMD, cmd);
178 nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
179 mpc5121_nfc_done(mtd);
182 /* Send data from NFC buffers to NAND flash */
183 static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
185 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
186 nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
187 mpc5121_nfc_done(mtd);
190 /* Receive data from NAND flash */
191 static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
193 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
194 nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
195 mpc5121_nfc_done(mtd);
198 /* Receive ID from NAND flash */
199 static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
201 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
202 nfc_write(mtd, NFC_CONFIG2, NFC_ID);
203 mpc5121_nfc_done(mtd);
206 /* Receive status from NAND flash */
207 static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
209 nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
210 nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
211 mpc5121_nfc_done(mtd);
214 /* NFC interrupt handler */
215 static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
217 struct mtd_info *mtd = data;
218 struct nand_chip *chip = mtd->priv;
219 struct mpc5121_nfc_prv *prv = chip->priv;
221 nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
222 wake_up(&prv->irq_waitq);
227 /* Wait for operation complete */
228 static void mpc5121_nfc_done(struct mtd_info *mtd)
230 struct nand_chip *chip = mtd->priv;
231 struct mpc5121_nfc_prv *prv = chip->priv;
234 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
235 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
236 rv = wait_event_timeout(prv->irq_waitq,
237 (nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
241 "Timeout while waiting for interrupt.\n");
244 nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
247 /* Do address cycle(s) */
248 static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
250 struct nand_chip *chip = mtd->priv;
251 u32 pagemask = chip->pagemask;
254 mpc5121_nfc_send_addr(mtd, column);
255 if (mtd->writesize > 512)
256 mpc5121_nfc_send_addr(mtd, column >> 8);
261 mpc5121_nfc_send_addr(mtd, page & 0xFF);
268 /* Control chip select signals */
269 static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
272 nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
276 nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
277 nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
279 nfc_set(mtd, NFC_CONFIG1, NFC_CE);
282 /* Init external chip select logic on ADS5121 board */
283 static int ads5121_chipselect_init(struct mtd_info *mtd)
285 struct nand_chip *chip = mtd->priv;
286 struct mpc5121_nfc_prv *prv = chip->priv;
287 struct device_node *dn;
289 dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
291 prv->csreg = of_iomap(dn, 0);
296 /* CPLD Register 9 controls NAND /CE Lines */
304 /* Control chips select signal on ADS5121 board */
305 static void ads5121_select_chip(struct mtd_info *mtd, int chip)
307 struct nand_chip *nand = mtd->priv;
308 struct mpc5121_nfc_prv *prv = nand->priv;
311 v = in_8(prv->csreg);
315 mpc5121_nfc_select_chip(mtd, 0);
318 mpc5121_nfc_select_chip(mtd, -1);
320 out_8(prv->csreg, v);
323 /* Read NAND Ready/Busy signal */
324 static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
327 * NFC handles ready/busy signal internally. Therefore, this function
328 * always returns status as ready.
333 /* Write command to NAND flash */
334 static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
335 int column, int page)
337 struct nand_chip *chip = mtd->priv;
338 struct mpc5121_nfc_prv *prv = chip->priv;
340 prv->column = (column >= 0) ? column : 0;
344 case NAND_CMD_PAGEPROG:
345 mpc5121_nfc_send_prog_page(mtd);
348 * NFC does not support sub-page reads and writes,
349 * so emulate them using full page transfers.
357 command = NAND_CMD_READ0;
361 case NAND_CMD_READOOB:
363 command = NAND_CMD_READ0;
368 mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
372 case NAND_CMD_ERASE1:
373 case NAND_CMD_ERASE2:
374 case NAND_CMD_READID:
375 case NAND_CMD_STATUS:
382 mpc5121_nfc_send_cmd(mtd, command);
383 mpc5121_nfc_addr_cycle(mtd, column, page);
387 if (mtd->writesize > 512)
388 mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
389 mpc5121_nfc_send_read_page(mtd);
392 case NAND_CMD_READID:
393 mpc5121_nfc_send_read_id(mtd);
396 case NAND_CMD_STATUS:
397 mpc5121_nfc_send_read_status(mtd);
398 if (chip->options & NAND_BUSWIDTH_16)
406 /* Copy data from/to NFC spare buffers. */
407 static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
408 u8 *buffer, uint size, int wr)
410 struct nand_chip *nand = mtd->priv;
411 struct mpc5121_nfc_prv *prv = nand->priv;
412 uint o, s, sbsize, blksize;
415 * NAND spare area is available through NFC spare buffers.
416 * The NFC divides spare area into (page_size / 512) chunks.
417 * Each chunk is placed into separate spare memory area, using
418 * first (spare_size / num_of_chunks) bytes of the buffer.
420 * For NAND device in which the spare area is not divided fully
421 * by the number of chunks, number of used bytes in each spare
422 * buffer is rounded down to the nearest even number of bytes,
423 * and all remaining bytes are added to the last used spare area.
425 * For more information read section 26.6.10 of MPC5121e
426 * Microcontroller Reference Manual, Rev. 3.
429 /* Calculate number of valid bytes in each spare buffer */
430 sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
433 /* Calculate spare buffer number */
435 if (s > NFC_SPARE_BUFFERS - 1)
436 s = NFC_SPARE_BUFFERS - 1;
439 * Calculate offset to requested data block in selected spare
440 * buffer and its size.
442 o = offset - (s * sbsize);
443 blksize = min(sbsize - o, size);
446 memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
449 memcpy_fromio(buffer,
450 prv->regs + NFC_SPARE_AREA(s) + o, blksize);
458 /* Copy data from/to NFC main and spare buffers */
459 static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
462 struct nand_chip *chip = mtd->priv;
463 struct mpc5121_nfc_prv *prv = chip->priv;
464 uint c = prv->column;
467 /* Handle spare area access */
468 if (prv->spareonly || c >= mtd->writesize) {
469 /* Calculate offset from beginning of spare area */
470 if (c >= mtd->writesize)
474 mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
479 * Handle main area access - limit copy length to prevent
480 * crossing main/spare boundary.
482 l = min((uint)len, mtd->writesize - c);
486 memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
488 memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
490 /* Handle crossing main/spare boundary */
494 mpc5121_nfc_buf_copy(mtd, buf, len, wr);
498 /* Read data from NFC buffers */
499 static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
501 mpc5121_nfc_buf_copy(mtd, buf, len, 0);
504 /* Write data to NFC buffers */
505 static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
506 const u_char *buf, int len)
508 mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
511 /* Compare buffer with NAND flash */
512 static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
513 const u_char *buf, int len)
519 bsize = min(len, 256);
520 mpc5121_nfc_read_buf(mtd, tmp, bsize);
522 if (memcmp(buf, tmp, bsize))
532 /* Read byte from NFC buffers */
533 static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
537 mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
542 /* Read word from NFC buffers */
543 static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
547 mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
553 * Read NFC configuration from Reset Config Word
555 * NFC is configured during reset in basis of information stored
556 * in Reset Config Word. There is no other way to set NAND block
557 * size, spare size and bus width.
559 static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
561 struct nand_chip *chip = mtd->priv;
562 struct mpc5121_nfc_prv *prv = chip->priv;
563 struct mpc512x_reset_module *rm;
564 struct device_node *rmnode;
565 uint rcw_pagesize = 0;
566 uint rcw_sparesize = 0;
572 rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
574 dev_err(prv->dev, "Missing 'fsl,mpc5121-reset' "
575 "node in device tree!\n");
579 rm = of_iomap(rmnode, 0);
581 dev_err(prv->dev, "Error mapping reset module node!\n");
586 rcwh = in_be32(&rm->rcwhr);
588 /* Bit 6: NFC bus width */
589 rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
591 /* Bit 7: NFC Page/Spare size */
592 ps = (rcwh >> 7) & 0x1;
594 /* Bits [22:21]: ROM Location */
595 romloc = (rcwh >> 21) & 0x3;
597 /* Decode RCW bits */
598 switch ((ps << 2) | romloc) {
621 mtd->writesize = rcw_pagesize;
622 mtd->oobsize = rcw_sparesize;
624 chip->options |= NAND_BUSWIDTH_16;
626 dev_notice(prv->dev, "Configured for "
627 "%u-bit NAND, page size %u "
629 rcw_width * 8, rcw_pagesize,
637 /* Free driver resources */
638 static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
640 struct nand_chip *chip = mtd->priv;
641 struct mpc5121_nfc_prv *prv = chip->priv;
644 clk_disable(prv->clk);
652 static int __devinit mpc5121_nfc_probe(struct platform_device *op)
654 struct device_node *rootnode, *dn = op->dev.of_node;
655 struct device *dev = &op->dev;
656 struct mpc5121_nfc_prv *prv;
658 struct mtd_info *mtd;
659 struct mtd_partition *parts;
660 struct nand_chip *chip;
661 unsigned long regs_paddr, regs_size;
662 const __be32 *chips_no;
668 * Check SoC revision. This driver supports only NFC
669 * in MPC5121 revision 2 and MPC5123 revision 3.
671 rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
672 if ((rev != 2) && (rev != 3)) {
673 dev_err(dev, "SoC revision %u is not supported!\n", rev);
677 prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
679 dev_err(dev, "Memory exhausted!\n");
690 /* Read NFC configuration from Reset Config Word */
691 retval = mpc5121_nfc_read_hw_config(mtd);
693 dev_err(dev, "Unable to read NFC config!\n");
697 prv->irq = irq_of_parse_and_map(dn, 0);
698 if (prv->irq == NO_IRQ) {
699 dev_err(dev, "Error mapping IRQ!\n");
703 retval = of_address_to_resource(dn, 0, &res);
705 dev_err(dev, "Error parsing memory region!\n");
709 chips_no = of_get_property(dn, "chips", &len);
710 if (!chips_no || len != sizeof(*chips_no)) {
711 dev_err(dev, "Invalid/missing 'chips' property!\n");
715 regs_paddr = res.start;
716 regs_size = resource_size(&res);
718 if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
719 dev_err(dev, "Error requesting memory region!\n");
723 prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
725 dev_err(dev, "Error mapping memory region!\n");
729 mtd->name = "MPC5121 NAND";
730 chip->dev_ready = mpc5121_nfc_dev_ready;
731 chip->cmdfunc = mpc5121_nfc_command;
732 chip->read_byte = mpc5121_nfc_read_byte;
733 chip->read_word = mpc5121_nfc_read_word;
734 chip->read_buf = mpc5121_nfc_read_buf;
735 chip->write_buf = mpc5121_nfc_write_buf;
736 chip->verify_buf = mpc5121_nfc_verify_buf;
737 chip->select_chip = mpc5121_nfc_select_chip;
738 chip->options = NAND_NO_AUTOINCR;
739 chip->bbt_options = NAND_BBT_USE_FLASH;
740 chip->ecc.mode = NAND_ECC_SOFT;
742 /* Support external chip-select logic on ADS5121 board */
743 rootnode = of_find_node_by_path("/");
744 if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
745 retval = ads5121_chipselect_init(mtd);
747 dev_err(dev, "Chipselect init error!\n");
748 of_node_put(rootnode);
752 chip->select_chip = ads5121_select_chip;
754 of_node_put(rootnode);
756 /* Enable NFC clock */
757 prv->clk = clk_get(dev, "nfc_clk");
758 if (IS_ERR(prv->clk)) {
759 dev_err(dev, "Unable to acquire NFC clock!\n");
760 retval = PTR_ERR(prv->clk);
764 clk_enable(prv->clk);
766 /* Reset NAND Flash controller */
767 nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
768 while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
769 if (resettime++ >= NFC_RESET_TIMEOUT) {
770 dev_err(dev, "Timeout while resetting NFC!\n");
778 /* Enable write to NFC memory */
779 nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
781 /* Enable write to all NAND pages */
782 nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
783 nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
784 nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
788 * - Big Endian transfers,
789 * - Interrupt after full page read/write.
791 nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
794 /* Set spare area size */
795 nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
797 init_waitqueue_head(&prv->irq_waitq);
798 retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
801 dev_err(dev, "Error requesting IRQ!\n");
805 /* Detect NAND chips */
806 if (nand_scan(mtd, be32_to_cpup(chips_no))) {
807 dev_err(dev, "NAND Flash not found !\n");
808 devm_free_irq(dev, prv->irq, mtd);
813 /* Set erase block size */
814 switch (mtd->erasesize / mtd->writesize) {
816 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
820 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
824 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
828 nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
832 dev_err(dev, "Unsupported NAND flash!\n");
833 devm_free_irq(dev, prv->irq, mtd);
838 dev_set_drvdata(dev, mtd);
840 /* Register device in MTD */
841 retval = parse_mtd_partitions(mtd, mpc5121_nfc_pprobes, &parts, 0);
842 #ifdef CONFIG_MTD_OF_PARTS
844 retval = of_mtd_parse_partitions(dev, dn, &parts);
847 dev_err(dev, "Error parsing MTD partitions!\n");
848 devm_free_irq(dev, prv->irq, mtd);
853 retval = mtd_device_register(mtd, parts, retval);
855 dev_err(dev, "Error adding MTD device!\n");
856 devm_free_irq(dev, prv->irq, mtd);
862 mpc5121_nfc_free(dev, mtd);
866 static int __devexit mpc5121_nfc_remove(struct platform_device *op)
868 struct device *dev = &op->dev;
869 struct mtd_info *mtd = dev_get_drvdata(dev);
870 struct nand_chip *chip = mtd->priv;
871 struct mpc5121_nfc_prv *prv = chip->priv;
874 devm_free_irq(dev, prv->irq, mtd);
875 mpc5121_nfc_free(dev, mtd);
880 static struct of_device_id mpc5121_nfc_match[] __devinitdata = {
881 { .compatible = "fsl,mpc5121-nfc", },
885 static struct platform_driver mpc5121_nfc_driver = {
886 .probe = mpc5121_nfc_probe,
887 .remove = __devexit_p(mpc5121_nfc_remove),
890 .owner = THIS_MODULE,
891 .of_match_table = mpc5121_nfc_match,
895 static int __init mpc5121_nfc_init(void)
897 return platform_driver_register(&mpc5121_nfc_driver);
900 module_init(mpc5121_nfc_init);
902 static void __exit mpc5121_nfc_cleanup(void)
904 platform_driver_unregister(&mpc5121_nfc_driver);
907 module_exit(mpc5121_nfc_cleanup);
909 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
910 MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
911 MODULE_LICENSE("GPL");