2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/resource.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/partitions.h>
32 #include <linux/slab.h>
33 #include <linux/mtd/fsmc.h>
34 #include <linux/amba/bus.h>
35 #include <mtd/mtd-abi.h>
37 static struct nand_ecclayout fsmc_ecc1_layout = {
39 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
42 {.offset = 8, .length = 8},
43 {.offset = 24, .length = 8},
44 {.offset = 40, .length = 8},
45 {.offset = 56, .length = 8},
46 {.offset = 72, .length = 8},
47 {.offset = 88, .length = 8},
48 {.offset = 104, .length = 8},
49 {.offset = 120, .length = 8}
53 static struct nand_ecclayout fsmc_ecc4_lp_layout = {
55 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
56 9, 10, 11, 12, 13, 14,
57 18, 19, 20, 21, 22, 23, 24,
58 25, 26, 27, 28, 29, 30,
59 34, 35, 36, 37, 38, 39, 40,
60 41, 42, 43, 44, 45, 46,
61 50, 51, 52, 53, 54, 55, 56,
62 57, 58, 59, 60, 61, 62,
63 66, 67, 68, 69, 70, 71, 72,
64 73, 74, 75, 76, 77, 78,
65 82, 83, 84, 85, 86, 87, 88,
66 89, 90, 91, 92, 93, 94,
67 98, 99, 100, 101, 102, 103, 104,
68 105, 106, 107, 108, 109, 110,
69 114, 115, 116, 117, 118, 119, 120,
70 121, 122, 123, 124, 125, 126
73 {.offset = 15, .length = 3},
74 {.offset = 31, .length = 3},
75 {.offset = 47, .length = 3},
76 {.offset = 63, .length = 3},
77 {.offset = 79, .length = 3},
78 {.offset = 95, .length = 3},
79 {.offset = 111, .length = 3},
80 {.offset = 127, .length = 1}
85 * ECC placement definitions in oobfree type format.
86 * There are 13 bytes of ecc for every 512 byte block and it has to be read
87 * consecutively and immediately after the 512 byte data block for hardware to
88 * generate the error bit offsets in 512 byte data.
89 * Managing the ecc bytes in the following way makes it easier for software to
90 * read ecc bytes consecutive to data bytes. This way is similar to
91 * oobfree structure maintained already in generic nand driver
93 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
95 {.offset = 2, .length = 13},
96 {.offset = 18, .length = 13},
97 {.offset = 34, .length = 13},
98 {.offset = 50, .length = 13},
99 {.offset = 66, .length = 13},
100 {.offset = 82, .length = 13},
101 {.offset = 98, .length = 13},
102 {.offset = 114, .length = 13}
106 static struct nand_ecclayout fsmc_ecc4_sp_layout = {
108 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
109 9, 10, 11, 12, 13, 14
112 {.offset = 15, .length = 1},
116 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
118 {.offset = 0, .length = 4},
119 {.offset = 6, .length = 9}
124 * Default partition tables to be used if the partition information not
125 * provided through platform data.
127 * Default partition layout for small page(= 512 bytes) devices
128 * Size for "Root file system" is updated in driver based on actual device size
130 static struct mtd_partition partition_info_16KB_blk[] = {
147 .name = "Root File System",
154 * Default partition layout for large page(> 512 bytes) devices
155 * Size for "Root file system" is updated in driver based on actual device size
157 static struct mtd_partition partition_info_128KB_blk[] = {
174 .name = "Root File System",
182 * struct fsmc_nand_data - structure for FSMC NAND device state
184 * @pid: Part ID on the AMBA PrimeCell format
185 * @mtd: MTD info for a NAND flash.
186 * @nand: Chip related info for a NAND flash.
187 * @partitions: Partition info for a NAND Flash.
188 * @nr_partitions: Total number of partition of a NAND flash.
190 * @ecc_place: ECC placing locations in oobfree type format.
191 * @bank: Bank number for probed device.
192 * @clk: Clock structure for FSMC.
194 * @data_va: NAND port for Data.
195 * @cmd_va: NAND port for Command.
196 * @addr_va: NAND port for Address.
197 * @regs_va: FSMC regs base address.
199 struct fsmc_nand_data {
202 struct nand_chip nand;
203 struct mtd_partition *partitions;
204 unsigned int nr_partitions;
206 struct fsmc_eccplace *ecc_place;
210 struct resource *resregs;
211 struct resource *rescmd;
212 struct resource *resaddr;
213 struct resource *resdata;
215 void __iomem *data_va;
216 void __iomem *cmd_va;
217 void __iomem *addr_va;
218 void __iomem *regs_va;
220 void (*select_chip)(uint32_t bank, uint32_t busw);
223 /* Assert CS signal based on chipnr */
224 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
226 struct nand_chip *chip = mtd->priv;
227 struct fsmc_nand_data *host;
229 host = container_of(mtd, struct fsmc_nand_data, mtd);
233 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
239 if (host->select_chip)
240 host->select_chip(chipnr,
241 chip->options & NAND_BUSWIDTH_16);
250 * fsmc_cmd_ctrl - For facilitaing Hardware access
251 * This routine allows hardware specific access to control-lines(ALE,CLE)
253 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
255 struct nand_chip *this = mtd->priv;
256 struct fsmc_nand_data *host = container_of(mtd,
257 struct fsmc_nand_data, mtd);
258 struct fsmc_regs *regs = host->regs_va;
259 unsigned int bank = host->bank;
261 if (ctrl & NAND_CTRL_CHANGE) {
262 if (ctrl & NAND_CLE) {
263 this->IO_ADDR_R = (void __iomem *)host->cmd_va;
264 this->IO_ADDR_W = (void __iomem *)host->cmd_va;
265 } else if (ctrl & NAND_ALE) {
266 this->IO_ADDR_R = (void __iomem *)host->addr_va;
267 this->IO_ADDR_W = (void __iomem *)host->addr_va;
269 this->IO_ADDR_R = (void __iomem *)host->data_va;
270 this->IO_ADDR_W = (void __iomem *)host->data_va;
273 if (ctrl & NAND_NCE) {
274 writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE,
275 ®s->bank_regs[bank].pc);
277 writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE,
278 ®s->bank_regs[bank].pc);
284 if (cmd != NAND_CMD_NONE)
285 writeb(cmd, this->IO_ADDR_W);
289 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
291 * This routine initializes timing parameters related to NAND memory access in
294 static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
297 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
300 writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc);
302 writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc);
304 writel(readl(®s->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
305 ®s->bank_regs[bank].pc);
306 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
307 ®s->bank_regs[bank].comm);
308 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
309 ®s->bank_regs[bank].attrib);
313 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
315 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
317 struct fsmc_nand_data *host = container_of(mtd,
318 struct fsmc_nand_data, mtd);
319 struct fsmc_regs *regs = host->regs_va;
320 uint32_t bank = host->bank;
322 writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
323 ®s->bank_regs[bank].pc);
324 writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN,
325 ®s->bank_regs[bank].pc);
326 writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN,
327 ®s->bank_regs[bank].pc);
331 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
332 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
335 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
338 struct fsmc_nand_data *host = container_of(mtd,
339 struct fsmc_nand_data, mtd);
340 struct fsmc_regs *regs = host->regs_va;
341 uint32_t bank = host->bank;
343 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
346 if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY)
350 } while (!time_after_eq(jiffies, deadline));
352 ecc_tmp = readl(®s->bank_regs[bank].ecc1);
353 ecc[0] = (uint8_t) (ecc_tmp >> 0);
354 ecc[1] = (uint8_t) (ecc_tmp >> 8);
355 ecc[2] = (uint8_t) (ecc_tmp >> 16);
356 ecc[3] = (uint8_t) (ecc_tmp >> 24);
358 ecc_tmp = readl(®s->bank_regs[bank].ecc2);
359 ecc[4] = (uint8_t) (ecc_tmp >> 0);
360 ecc[5] = (uint8_t) (ecc_tmp >> 8);
361 ecc[6] = (uint8_t) (ecc_tmp >> 16);
362 ecc[7] = (uint8_t) (ecc_tmp >> 24);
364 ecc_tmp = readl(®s->bank_regs[bank].ecc3);
365 ecc[8] = (uint8_t) (ecc_tmp >> 0);
366 ecc[9] = (uint8_t) (ecc_tmp >> 8);
367 ecc[10] = (uint8_t) (ecc_tmp >> 16);
368 ecc[11] = (uint8_t) (ecc_tmp >> 24);
370 ecc_tmp = readl(®s->bank_regs[bank].sts);
371 ecc[12] = (uint8_t) (ecc_tmp >> 16);
377 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
378 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
381 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
384 struct fsmc_nand_data *host = container_of(mtd,
385 struct fsmc_nand_data, mtd);
386 struct fsmc_regs *regs = host->regs_va;
387 uint32_t bank = host->bank;
390 ecc_tmp = readl(®s->bank_regs[bank].ecc1);
391 ecc[0] = (uint8_t) (ecc_tmp >> 0);
392 ecc[1] = (uint8_t) (ecc_tmp >> 8);
393 ecc[2] = (uint8_t) (ecc_tmp >> 16);
399 * fsmc_read_page_hwecc
400 * @mtd: mtd info structure
401 * @chip: nand chip info structure
402 * @buf: buffer to store read data
403 * @page: page number to read
405 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
406 * performed in a strict sequence as follows:
407 * data(512 byte) -> ecc(13 byte)
408 * After this read, fsmc hardware generates and reports error data bits(up to a
411 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
412 uint8_t *buf, int page)
414 struct fsmc_nand_data *host = container_of(mtd,
415 struct fsmc_nand_data, mtd);
416 struct fsmc_eccplace *ecc_place = host->ecc_place;
417 int i, j, s, stat, eccsize = chip->ecc.size;
418 int eccbytes = chip->ecc.bytes;
419 int eccsteps = chip->ecc.steps;
421 uint8_t *ecc_calc = chip->buffers->ecccalc;
422 uint8_t *ecc_code = chip->buffers->ecccode;
423 int off, len, group = 0;
425 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
426 * end up reading 14 bytes (7 words) from oob. The local array is
427 * to maintain word alignment
430 uint8_t *oob = (uint8_t *)&ecc_oob[0];
432 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
434 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
435 chip->ecc.hwctl(mtd, NAND_ECC_READ);
436 chip->read_buf(mtd, p, eccsize);
438 for (j = 0; j < eccbytes;) {
439 off = ecc_place->eccplace[group].offset;
440 len = ecc_place->eccplace[group].length;
444 * length is intentionally kept a higher multiple of 2
445 * to read at least 13 bytes even in case of 16 bit NAND
448 len = roundup(len, 2);
449 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
450 chip->read_buf(mtd, oob + j, len);
454 memcpy(&ecc_code[i], oob, 13);
455 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
457 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
459 mtd->ecc_stats.failed++;
461 mtd->ecc_stats.corrected += stat;
469 * @mtd: mtd info structure
470 * @dat: buffer of read data
471 * @read_ecc: ecc read from device spare area
472 * @calc_ecc: ecc calculated from read data
474 * calc_ecc is a 104 bit information containing maximum of 8 error
475 * offset informations of 13 bits each in 512 bytes of read data.
477 static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
478 uint8_t *read_ecc, uint8_t *calc_ecc)
480 struct fsmc_nand_data *host = container_of(mtd,
481 struct fsmc_nand_data, mtd);
482 struct fsmc_regs *regs = host->regs_va;
483 unsigned int bank = host->bank;
485 uint64_t ecc_data[2];
488 /* The calculated ecc is actually the correction index in data */
489 memcpy(ecc_data, calc_ecc, 13);
492 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
493 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
495 * calc_ecc is a 104 bit information containing maximum of 8 error
496 * offset informations of 13 bits each. calc_ecc is copied into a
497 * uint64_t array and error offset indexes are populated in err_idx
500 for (i = 0; i < 8; i++) {
502 err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
506 err_idx[i] = (ecc_data[i/4] & 0x1FFF);
507 ecc_data[i/4] >>= 13;
510 num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF;
517 change_bit(0, (unsigned long *)&err_idx[i]);
518 change_bit(1, (unsigned long *)&err_idx[i]);
520 if (err_idx[i] <= 512 * 8) {
521 change_bit(err_idx[i], (unsigned long *)dat);
529 * fsmc_nand_probe - Probe function
530 * @pdev: platform device structure
532 static int __init fsmc_nand_probe(struct platform_device *pdev)
534 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
535 struct fsmc_nand_data *host;
536 struct mtd_info *mtd;
537 struct nand_chip *nand;
538 struct fsmc_regs *regs;
539 struct resource *res;
545 dev_err(&pdev->dev, "platform data is NULL\n");
549 /* Allocate memory for the device structure (and zero it) */
550 host = kzalloc(sizeof(*host), GFP_KERNEL);
552 dev_err(&pdev->dev, "failed to allocate device structure\n");
556 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
562 host->resdata = request_mem_region(res->start, resource_size(res),
564 if (!host->resdata) {
569 host->data_va = ioremap(res->start, resource_size(res));
570 if (!host->data_va) {
575 host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
576 resource_size(res), pdev->name);
577 if (!host->resaddr) {
582 host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
583 if (!host->addr_va) {
588 host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
589 resource_size(res), pdev->name);
595 host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
601 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
607 host->resregs = request_mem_region(res->start, resource_size(res),
609 if (!host->resregs) {
614 host->regs_va = ioremap(res->start, resource_size(res));
615 if (!host->regs_va) {
620 host->clk = clk_get(&pdev->dev, NULL);
621 if (IS_ERR(host->clk)) {
622 dev_err(&pdev->dev, "failed to fetch block clock\n");
623 ret = PTR_ERR(host->clk);
628 ret = clk_enable(host->clk);
633 * This device ID is actually a common AMBA ID as used on the
634 * AMBA PrimeCell bus. However it is not a PrimeCell.
636 for (pid = 0, i = 0; i < 4; i++)
637 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
639 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
640 "revision %02x, config %02x\n",
641 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
642 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
644 host->bank = pdata->bank;
645 host->select_chip = pdata->select_bank;
646 regs = host->regs_va;
648 /* Link all private pointers */
654 host->mtd.owner = THIS_MODULE;
655 nand->IO_ADDR_R = host->data_va;
656 nand->IO_ADDR_W = host->data_va;
657 nand->cmd_ctrl = fsmc_cmd_ctrl;
658 nand->chip_delay = 30;
660 nand->ecc.mode = NAND_ECC_HW;
661 nand->ecc.hwctl = fsmc_enable_hwecc;
662 nand->ecc.size = 512;
663 nand->options = pdata->options;
664 nand->select_chip = fsmc_select_chip;
666 if (pdata->width == FSMC_NAND_BW16)
667 nand->options |= NAND_BUSWIDTH_16;
669 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
671 if (AMBA_REV_BITS(host->pid) >= 8) {
672 nand->ecc.read_page = fsmc_read_page_hwecc;
673 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
674 nand->ecc.correct = fsmc_correct_data;
675 nand->ecc.bytes = 13;
677 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
678 nand->ecc.correct = nand_correct_data;
683 * Scan to find existence of the device
685 if (nand_scan_ident(&host->mtd, 1, NULL)) {
687 dev_err(&pdev->dev, "No NAND Device found!\n");
691 if (AMBA_REV_BITS(host->pid) >= 8) {
692 if (host->mtd.writesize == 512) {
693 nand->ecc.layout = &fsmc_ecc4_sp_layout;
694 host->ecc_place = &fsmc_ecc4_sp_place;
696 nand->ecc.layout = &fsmc_ecc4_lp_layout;
697 host->ecc_place = &fsmc_ecc4_lp_place;
700 nand->ecc.layout = &fsmc_ecc1_layout;
703 /* Second stage of scan to fill MTD data-structures */
704 if (nand_scan_tail(&host->mtd)) {
710 * The partition information can is accessed by (in the same precedence)
712 * command line through Bootloader,
714 * default partition information present in driver.
717 * Check for partition info passed
719 host->mtd.name = "nand";
720 host->nr_partitions = parse_mtd_partitions(&host->mtd, NULL,
721 &host->partitions, 0);
722 if (host->nr_partitions <= 0) {
724 * Check if partition info passed via command line
726 if (pdata->partitions) {
727 host->partitions = pdata->partitions;
728 host->nr_partitions = pdata->nr_partitions;
730 struct mtd_partition *partition;
733 /* Select the default partitions info */
734 switch (host->mtd.size) {
738 host->partitions = partition_info_16KB_blk;
739 host->nr_partitions =
740 sizeof(partition_info_16KB_blk) /
741 sizeof(struct mtd_partition);
747 host->partitions = partition_info_128KB_blk;
748 host->nr_partitions =
749 sizeof(partition_info_128KB_blk) /
750 sizeof(struct mtd_partition);
754 pr_err("Unsupported NAND size\n");
758 partition = host->partitions;
759 for (i = 0; i < host->nr_partitions; i++, partition++) {
760 if (partition->size == 0) {
761 partition->size = host->mtd.size -
769 ret = mtd_device_register(&host->mtd, host->partitions,
770 host->nr_partitions);
774 platform_set_drvdata(pdev, host);
775 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
779 clk_disable(host->clk);
784 iounmap(host->regs_va);
786 release_mem_region(host->resregs->start,
787 resource_size(host->resregs));
789 iounmap(host->cmd_va);
791 release_mem_region(host->rescmd->start,
792 resource_size(host->rescmd));
794 iounmap(host->addr_va);
796 release_mem_region(host->resaddr->start,
797 resource_size(host->resaddr));
799 iounmap(host->data_va);
801 release_mem_region(host->resdata->start,
802 resource_size(host->resdata));
811 static int fsmc_nand_remove(struct platform_device *pdev)
813 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
815 platform_set_drvdata(pdev, NULL);
818 nand_release(&host->mtd);
819 clk_disable(host->clk);
822 iounmap(host->regs_va);
823 release_mem_region(host->resregs->start,
824 resource_size(host->resregs));
825 iounmap(host->cmd_va);
826 release_mem_region(host->rescmd->start,
827 resource_size(host->rescmd));
828 iounmap(host->addr_va);
829 release_mem_region(host->resaddr->start,
830 resource_size(host->resaddr));
831 iounmap(host->data_va);
832 release_mem_region(host->resdata->start,
833 resource_size(host->resdata));
841 static int fsmc_nand_suspend(struct device *dev)
843 struct fsmc_nand_data *host = dev_get_drvdata(dev);
845 clk_disable(host->clk);
849 static int fsmc_nand_resume(struct device *dev)
851 struct fsmc_nand_data *host = dev_get_drvdata(dev);
853 clk_enable(host->clk);
857 static const struct dev_pm_ops fsmc_nand_pm_ops = {
858 .suspend = fsmc_nand_suspend,
859 .resume = fsmc_nand_resume,
863 static struct platform_driver fsmc_nand_driver = {
864 .remove = fsmc_nand_remove,
866 .owner = THIS_MODULE,
869 .pm = &fsmc_nand_pm_ops,
874 static int __init fsmc_nand_init(void)
876 return platform_driver_probe(&fsmc_nand_driver,
879 module_init(fsmc_nand_init);
881 static void __exit fsmc_nand_exit(void)
883 platform_driver_unregister(&fsmc_nand_driver);
885 module_exit(fsmc_nand_exit);
887 MODULE_LICENSE("GPL");
888 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
889 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");