3 * Texas Instruments, <www.ti.com>
4 * Sukumar Ghorai <s-ghorai@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation's version 2 of
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
37 #include <asm/cache.h>
39 #include <asm/arch/mmc_host_def.h>
40 #ifdef CONFIG_OMAP54XX
41 #include <asm/arch/mux_dra7xx.h>
42 #include <asm/arch/dra7xx_iodelay.h>
44 #if !defined(CONFIG_SOC_KEYSTONE)
46 #include <asm/arch/sys_proto.h>
48 #ifdef CONFIG_MMC_OMAP36XX_PINS
49 #include <asm/arch/mux.h>
52 #include <dm/devres.h>
53 #include <linux/err.h>
54 #include <power/regulator.h>
57 DECLARE_GLOBAL_DATA_PTR;
59 /* simplify defines to OMAP_HSMMC_USE_GPIO */
60 #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
61 (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT))
62 #define OMAP_HSMMC_USE_GPIO
64 #undef OMAP_HSMMC_USE_GPIO
67 /* common definitions for all OMAPs */
68 #define SYSCTL_SRC (1 << 25)
69 #define SYSCTL_SRD (1 << 26)
71 #ifdef CONFIG_IODELAY_RECALIBRATION
72 struct omap_hsmmc_pinctrl_state {
73 struct pad_conf_entry *padconf;
75 struct iodelay_cfg_entry *iodelay;
80 struct omap_hsmmc_data {
81 struct hsmmc *base_addr;
82 #if !CONFIG_IS_ENABLED(DM_MMC)
83 struct mmc_config cfg;
88 #ifdef OMAP_HSMMC_USE_GPIO
89 #if CONFIG_IS_ENABLED(DM_MMC)
90 struct gpio_desc cd_gpio; /* Change Detect GPIO */
91 struct gpio_desc wp_gpio; /* Write Protect GPIO */
97 #if CONFIG_IS_ENABLED(DM_MMC)
101 #ifdef CONFIG_MMC_OMAP_HS_ADMA
102 struct omap_hsmmc_adma_desc *adma_desc_table;
106 struct udevice *pbias_supply;
108 #ifdef CONFIG_IODELAY_RECALIBRATION
109 struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
110 struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
111 struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
112 struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
113 struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
114 struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
115 struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
116 struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
117 struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
121 struct omap_mmc_of_data {
125 #ifdef CONFIG_MMC_OMAP_HS_ADMA
126 struct omap_hsmmc_adma_desc {
133 #define ADMA_MAX_LEN 63488
135 /* Decriptor table defines */
136 #define ADMA_DESC_ATTR_VALID BIT(0)
137 #define ADMA_DESC_ATTR_END BIT(1)
138 #define ADMA_DESC_ATTR_INT BIT(2)
139 #define ADMA_DESC_ATTR_ACT1 BIT(4)
140 #define ADMA_DESC_ATTR_ACT2 BIT(5)
142 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
143 #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
146 /* If we fail after 1 second wait, something is really bad */
147 #define MAX_RETRY_MS 1000
148 #define MMC_TIMEOUT_MS 20
150 /* DMA transfers can take a long time if a lot a data is transferred.
151 * The timeout must take in account the amount of data. Let's assume
152 * that the time will never exceed 333 ms per MB (in other word we assume
153 * that the bandwidth is always above 3MB/s).
155 #define DMA_TIMEOUT_PER_MB 333
156 #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
157 #define OMAP_HSMMC_NO_1_8_V BIT(1)
158 #define OMAP_HSMMC_USE_ADMA BIT(2)
159 #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
161 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
162 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
164 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
165 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
166 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
168 static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
170 #if CONFIG_IS_ENABLED(DM_MMC)
171 return dev_get_priv(mmc->dev);
173 return (struct omap_hsmmc_data *)mmc->priv;
176 static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
178 #if CONFIG_IS_ENABLED(DM_MMC)
179 struct omap_hsmmc_plat *plat = dev_get_platdata(mmc->dev);
182 return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
186 #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
187 static int omap_mmc_setup_gpio_in(int gpio, const char *label)
191 #if !CONFIG_IS_ENABLED(DM_GPIO)
192 if (!gpio_is_valid(gpio))
195 ret = gpio_request(gpio, label);
199 ret = gpio_direction_input(gpio);
207 static unsigned char mmc_board_init(struct mmc *mmc)
209 #if defined(CONFIG_OMAP34XX)
210 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
211 t2_t *t2_base = (t2_t *)T2_BASE;
212 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
214 #ifdef CONFIG_MMC_OMAP36XX_PINS
215 u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
218 pbias_lite = readl(&t2_base->pbias_lite);
219 pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
220 #ifdef CONFIG_TARGET_OMAP3_CAIRO
221 /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
222 pbias_lite &= ~PBIASLITEVMODE0;
224 #ifdef CONFIG_TARGET_OMAP3_LOGIC
225 /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
226 pbias_lite &= ~PBIASLITEVMODE1;
228 #ifdef CONFIG_MMC_OMAP36XX_PINS
229 if (get_cpu_family() == CPU_OMAP36XX) {
230 /* Disable extended drain IO before changing PBIAS */
231 wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
232 writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
235 writel(pbias_lite, &t2_base->pbias_lite);
237 writel(pbias_lite | PBIASLITEPWRDNZ1 |
238 PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
239 &t2_base->pbias_lite);
241 #ifdef CONFIG_MMC_OMAP36XX_PINS
242 if (get_cpu_family() == CPU_OMAP36XX)
243 /* Enable extended drain IO after changing PBIAS */
245 OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
246 OMAP34XX_CTRL_WKUP_CTRL);
248 writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
251 writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
254 /* Change from default of 52MHz to 26MHz if necessary */
255 if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
256 writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
257 &t2_base->ctl_prog_io1);
259 writel(readl(&prcm_base->fclken1_core) |
260 EN_MMC1 | EN_MMC2 | EN_MMC3,
261 &prcm_base->fclken1_core);
263 writel(readl(&prcm_base->iclken1_core) |
264 EN_MMC1 | EN_MMC2 | EN_MMC3,
265 &prcm_base->iclken1_core);
268 #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
269 !CONFIG_IS_ENABLED(DM_REGULATOR)
270 /* PBIAS config needed for MMC1 only */
271 if (mmc_get_blk_desc(mmc)->devnum == 0)
272 vmmc_pbias_config(LDO_VOLT_3V3);
278 void mmc_init_stream(struct hsmmc *mmc_base)
282 writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
284 writel(MMC_CMD0, &mmc_base->cmd);
285 start = get_timer(0);
286 while (!(readl(&mmc_base->stat) & CC_MASK)) {
287 if (get_timer(0) - start > MAX_RETRY_MS) {
288 printf("%s: timedout waiting for cc!\n", __func__);
292 writel(CC_MASK, &mmc_base->stat)
294 writel(MMC_CMD0, &mmc_base->cmd)
296 start = get_timer(0);
297 while (!(readl(&mmc_base->stat) & CC_MASK)) {
298 if (get_timer(0) - start > MAX_RETRY_MS) {
299 printf("%s: timedout waiting for cc2!\n", __func__);
303 writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
306 #if CONFIG_IS_ENABLED(DM_MMC)
307 #ifdef CONFIG_IODELAY_RECALIBRATION
308 static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
310 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
311 struct omap_hsmmc_pinctrl_state *pinctrl_state;
313 switch (priv->mode) {
315 pinctrl_state = priv->hs200_1_8v_pinctrl_state;
318 pinctrl_state = priv->sdr104_pinctrl_state;
321 pinctrl_state = priv->sdr50_pinctrl_state;
324 pinctrl_state = priv->ddr50_pinctrl_state;
327 pinctrl_state = priv->sdr25_pinctrl_state;
330 pinctrl_state = priv->sdr12_pinctrl_state;
335 pinctrl_state = priv->hs_pinctrl_state;
338 pinctrl_state = priv->ddr_1_8v_pinctrl_state;
340 pinctrl_state = priv->default_pinctrl_state;
345 pinctrl_state = priv->default_pinctrl_state;
347 if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
348 if (pinctrl_state->iodelay)
349 late_recalibrate_iodelay(pinctrl_state->padconf,
350 pinctrl_state->npads,
351 pinctrl_state->iodelay,
352 pinctrl_state->niodelays);
354 do_set_mux32((*ctrl)->control_padconf_core_base,
355 pinctrl_state->padconf,
356 pinctrl_state->npads);
360 static void omap_hsmmc_set_timing(struct mmc *mmc)
363 struct hsmmc *mmc_base;
364 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
366 mmc_base = priv->base_addr;
368 omap_hsmmc_stop_clock(mmc_base);
369 val = readl(&mmc_base->ac12);
370 val &= ~AC12_UHSMC_MASK;
371 priv->mode = mmc->selected_mode;
373 if (mmc_is_mode_ddr(priv->mode))
374 writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
376 writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
378 switch (priv->mode) {
381 val |= AC12_UHSMC_SDR104;
384 val |= AC12_UHSMC_SDR50;
388 val |= AC12_UHSMC_DDR50;
393 val |= AC12_UHSMC_SDR25;
398 val |= AC12_UHSMC_SDR12;
401 val |= AC12_UHSMC_RES;
404 writel(val, &mmc_base->ac12);
406 #ifdef CONFIG_IODELAY_RECALIBRATION
407 omap_hsmmc_io_recalibrate(mmc);
409 omap_hsmmc_start_clock(mmc_base);
412 static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
414 struct hsmmc *mmc_base;
415 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
418 mmc_base = priv->base_addr;
420 hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
421 ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
423 switch (signal_voltage) {
424 case MMC_SIGNAL_VOLTAGE_330:
427 case MMC_SIGNAL_VOLTAGE_180:
429 ac12 |= AC12_V1V8_SIGEN;
433 writel(hctl, &mmc_base->hctl);
434 writel(ac12, &mmc_base->ac12);
437 static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
439 int ret = -ETIMEDOUT;
442 bool target_dat0_high = !!state;
443 struct omap_hsmmc_data *priv = dev_get_priv(dev);
444 struct hsmmc *mmc_base = priv->base_addr;
446 con = readl(&mmc_base->con);
447 writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
449 timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
450 while (timeout_us--) {
451 dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
452 if (dat0_high == target_dat0_high) {
458 writel(con, &mmc_base->con);
463 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
464 #if CONFIG_IS_ENABLED(DM_REGULATOR)
465 static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
470 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
472 if (!mmc->vqmmc_supply)
476 ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
480 /* Turn off IO voltage */
481 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
484 /* Program a new IO voltage value */
485 ret = regulator_set_value(mmc->vqmmc_supply, uV);
488 /* Turn on IO voltage */
489 ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
493 /* Program PBIAS voltage*/
494 ret = regulator_set_value(priv->pbias_supply, uV);
495 if (ret && ret != -ENOSYS)
498 ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
506 static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
508 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
509 struct hsmmc *mmc_base = priv->base_addr;
510 int mv = mmc_voltage_to_mv(mmc->signal_voltage);
512 __maybe_unused u8 palmas_ldo_volt;
518 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
520 capa_mask = VS33_3V3SUP;
521 palmas_ldo_volt = LDO_VOLT_3V3;
522 } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
523 capa_mask = VS18_1V8SUP;
524 palmas_ldo_volt = LDO_VOLT_1V8;
529 val = readl(&mmc_base->capa);
530 if (!(val & capa_mask))
533 priv->signal_voltage = mmc->signal_voltage;
535 omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
537 #if CONFIG_IS_ENABLED(DM_REGULATOR)
538 return omap_hsmmc_set_io_regulator(mmc, mv);
539 #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
540 defined(CONFIG_PALMAS_POWER)
541 if (mmc_get_blk_desc(mmc)->devnum == 0)
542 vmmc_pbias_config(palmas_ldo_volt);
550 static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
552 struct hsmmc *mmc_base;
553 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
556 mmc_base = priv->base_addr;
557 val = readl(&mmc_base->capa);
559 if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
560 val |= (VS33_3V3SUP | VS18_1V8SUP);
561 } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
569 writel(val, &mmc_base->capa);
574 #ifdef MMC_SUPPORTS_TUNING
575 static void omap_hsmmc_disable_tuning(struct mmc *mmc)
577 struct hsmmc *mmc_base;
578 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
581 mmc_base = priv->base_addr;
582 val = readl(&mmc_base->ac12);
583 val &= ~(AC12_SCLK_SEL);
584 writel(val, &mmc_base->ac12);
586 val = readl(&mmc_base->dll);
587 val &= ~(DLL_FORCE_VALUE | DLL_SWT);
588 writel(val, &mmc_base->dll);
591 static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
594 struct hsmmc *mmc_base;
595 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
598 mmc_base = priv->base_addr;
599 val = readl(&mmc_base->dll);
600 val |= DLL_FORCE_VALUE;
601 val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
602 val |= (count << DLL_FORCE_SR_C_SHIFT);
603 writel(val, &mmc_base->dll);
606 writel(val, &mmc_base->dll);
607 for (i = 0; i < 1000; i++) {
608 if (readl(&mmc_base->dll) & DLL_CALIB)
612 writel(val, &mmc_base->dll);
615 static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
617 struct omap_hsmmc_data *priv = dev_get_priv(dev);
618 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
619 struct mmc *mmc = upriv->mmc;
620 struct hsmmc *mmc_base;
622 u8 cur_match, prev_match = 0;
625 u32 start_window = 0, max_window = 0;
626 u32 length = 0, max_len = 0;
627 bool single_point_failure = false;
628 struct udevice *thermal_dev;
632 mmc_base = priv->base_addr;
633 val = readl(&mmc_base->capa2);
635 /* clock tuning is not needed for upto 52MHz */
636 if (!((mmc->selected_mode == MMC_HS_200) ||
637 (mmc->selected_mode == UHS_SDR104) ||
638 ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
641 ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
643 printf("Couldn't get thermal device for tuning\n");
646 ret = thermal_get_temp(thermal_dev, &temperature);
648 printf("Couldn't get temperature for tuning\n");
651 val = readl(&mmc_base->dll);
653 writel(val, &mmc_base->dll);
656 * Stage 1: Search for a maximum pass window ignoring any
657 * any single point failures. If the tuning value ends up
658 * near it, move away from it in stage 2 below
660 while (phase_delay <= MAX_PHASE_DELAY) {
661 omap_hsmmc_set_dll(mmc, phase_delay);
663 cur_match = !mmc_send_tuning(mmc, opcode, NULL);
668 } else if (single_point_failure) {
669 /* ignore single point failure */
671 single_point_failure = false;
673 start_window = phase_delay;
677 single_point_failure = prev_match;
680 if (length > max_len) {
681 max_window = start_window;
685 prev_match = cur_match;
694 val = readl(&mmc_base->ac12);
695 if (!(val & AC12_SCLK_SEL)) {
700 * Assign tuning value as a ratio of maximum pass window based
703 if (temperature < -20000)
704 phase_delay = min(max_window + 4 * max_len - 24,
706 DIV_ROUND_UP(13 * max_len, 16) * 4);
707 else if (temperature < 20000)
708 phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
709 else if (temperature < 40000)
710 phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
711 else if (temperature < 70000)
712 phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
713 else if (temperature < 90000)
714 phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
715 else if (temperature < 120000)
716 phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
718 phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
721 * Stage 2: Search for a single point failure near the chosen tuning
722 * value in two steps. First in the +3 to +10 range and then in the
723 * +2 to -10 range. If found, move away from it in the appropriate
724 * direction by the appropriate amount depending on the temperature.
726 for (i = 3; i <= 10; i++) {
727 omap_hsmmc_set_dll(mmc, phase_delay + i);
728 if (mmc_send_tuning(mmc, opcode, NULL)) {
729 if (temperature < 10000)
730 phase_delay += i + 6;
731 else if (temperature < 20000)
732 phase_delay += i - 12;
733 else if (temperature < 70000)
734 phase_delay += i - 8;
735 else if (temperature < 90000)
736 phase_delay += i - 6;
738 phase_delay += i - 6;
740 goto single_failure_found;
744 for (i = 2; i >= -10; i--) {
745 omap_hsmmc_set_dll(mmc, phase_delay + i);
746 if (mmc_send_tuning(mmc, opcode, NULL)) {
747 if (temperature < 10000)
748 phase_delay += i + 12;
749 else if (temperature < 20000)
750 phase_delay += i + 8;
751 else if (temperature < 70000)
752 phase_delay += i + 8;
753 else if (temperature < 90000)
754 phase_delay += i + 10;
756 phase_delay += i + 12;
758 goto single_failure_found;
762 single_failure_found:
764 omap_hsmmc_set_dll(mmc, phase_delay);
766 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
767 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
773 omap_hsmmc_disable_tuning(mmc);
774 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
775 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
782 static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
784 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
785 struct hsmmc *mmc_base = priv->base_addr;
786 u32 irq_mask = INT_EN_MASK;
789 * TODO: Errata i802 indicates only DCRC interrupts can occur during
790 * tuning procedure and DCRC should be disabled. But see occurences
791 * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
792 * interrupts occur along with BRR, so the data is actually in the
793 * buffer. It has to be debugged why these interrutps occur
795 if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
796 irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
798 writel(irq_mask, &mmc_base->ie);
801 static int omap_hsmmc_init_setup(struct mmc *mmc)
803 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
804 struct hsmmc *mmc_base;
805 unsigned int reg_val;
809 mmc_base = priv->base_addr;
812 writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
813 &mmc_base->sysconfig);
814 start = get_timer(0);
815 while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
816 if (get_timer(0) - start > MAX_RETRY_MS) {
817 printf("%s: timedout waiting for cc2!\n", __func__);
821 writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
822 start = get_timer(0);
823 while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
824 if (get_timer(0) - start > MAX_RETRY_MS) {
825 printf("%s: timedout waiting for softresetall!\n",
830 #ifdef CONFIG_MMC_OMAP_HS_ADMA
831 reg_val = readl(&mmc_base->hl_hwinfo);
832 if (reg_val & MADMA_EN)
833 priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
836 #if CONFIG_IS_ENABLED(DM_MMC)
837 reg_val = omap_hsmmc_set_capabilities(mmc);
838 omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
839 MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
841 writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
842 writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
846 reg_val = readl(&mmc_base->con) & RESERVED_MASK;
848 writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
849 MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
850 HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
853 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
854 (ICE_STOP | DTO_15THDTO));
855 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
856 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
857 start = get_timer(0);
858 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
859 if (get_timer(0) - start > MAX_RETRY_MS) {
860 printf("%s: timedout waiting for ics!\n", __func__);
864 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
866 writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
868 mmc_enable_irq(mmc, NULL);
870 #if !CONFIG_IS_ENABLED(DM_MMC)
871 mmc_init_stream(mmc_base);
878 * MMC controller internal finite state machine reset
880 * Used to reset command or data internal state machines, using respectively
881 * SRC or SRD bit of SYSCTL register
883 static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
887 mmc_reg_out(&mmc_base->sysctl, bit, bit);
890 * CMD(DAT) lines reset procedures are slightly different
891 * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
892 * According to OMAP3 TRM:
893 * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
895 * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
896 * procedure steps must be as follows:
897 * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
898 * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
899 * 2. Poll the SRC(SRD) bit until it is set to 0x1.
900 * 3. Wait until the SRC (SRD) bit returns to 0x0
901 * (reset procedure is completed).
903 #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
904 defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
905 if (!(readl(&mmc_base->sysctl) & bit)) {
906 start = get_timer(0);
907 while (!(readl(&mmc_base->sysctl) & bit)) {
908 if (get_timer(0) - start > MMC_TIMEOUT_MS)
913 start = get_timer(0);
914 while ((readl(&mmc_base->sysctl) & bit) != 0) {
915 if (get_timer(0) - start > MAX_RETRY_MS) {
916 printf("%s: timedout waiting for sysctl %x to clear\n",
923 #ifdef CONFIG_MMC_OMAP_HS_ADMA
924 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
926 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
927 struct omap_hsmmc_adma_desc *desc;
930 desc = &priv->adma_desc_table[priv->desc_slot];
932 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
936 attr |= ADMA_DESC_ATTR_END;
939 desc->addr = (u32)buf;
944 static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
945 struct mmc_data *data)
947 uint total_len = data->blocksize * data->blocks;
948 uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
949 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
954 priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
955 memalign(ARCH_DMA_MINALIGN, desc_count *
956 sizeof(struct omap_hsmmc_adma_desc));
958 if (data->flags & MMC_DATA_READ)
961 buf = (char *)data->src;
964 omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
966 total_len -= ADMA_MAX_LEN;
969 omap_hsmmc_adma_desc(mmc, buf, total_len, true);
971 flush_dcache_range((long)priv->adma_desc_table,
972 (long)priv->adma_desc_table +
974 sizeof(struct omap_hsmmc_adma_desc),
978 static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
980 struct hsmmc *mmc_base;
981 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
985 mmc_base = priv->base_addr;
986 omap_hsmmc_prepare_adma_table(mmc, data);
988 if (data->flags & MMC_DATA_READ)
991 buf = (char *)data->src;
993 val = readl(&mmc_base->hctl);
995 writel(val, &mmc_base->hctl);
997 val = readl(&mmc_base->con);
999 writel(val, &mmc_base->con);
1001 writel((u32)priv->adma_desc_table, &mmc_base->admasal);
1003 flush_dcache_range((u32)buf,
1005 ROUND(data->blocksize * data->blocks,
1006 ARCH_DMA_MINALIGN));
1009 static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
1011 struct hsmmc *mmc_base;
1012 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1015 mmc_base = priv->base_addr;
1017 val = readl(&mmc_base->con);
1019 writel(val, &mmc_base->con);
1021 val = readl(&mmc_base->hctl);
1023 writel(val, &mmc_base->hctl);
1025 kfree(priv->adma_desc_table);
1028 #define omap_hsmmc_adma_desc
1029 #define omap_hsmmc_prepare_adma_table
1030 #define omap_hsmmc_prepare_data
1031 #define omap_hsmmc_dma_cleanup
1034 #if !CONFIG_IS_ENABLED(DM_MMC)
1035 static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1036 struct mmc_data *data)
1038 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1040 static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1041 struct mmc_data *data)
1043 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1044 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1045 struct mmc *mmc = upriv->mmc;
1047 struct hsmmc *mmc_base;
1048 unsigned int flags, mmc_stat;
1050 priv->last_cmd = cmd->cmdidx;
1052 mmc_base = priv->base_addr;
1054 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
1057 start = get_timer(0);
1058 while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
1059 if (get_timer(0) - start > MAX_RETRY_MS) {
1060 printf("%s: timedout waiting on cmd inhibit to clear\n",
1062 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1063 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1067 writel(0xFFFFFFFF, &mmc_base->stat);
1068 if (readl(&mmc_base->stat)) {
1069 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1070 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1075 * CMDIDX[13:8] : Command index
1076 * DATAPRNT[5] : Data Present Select
1077 * ENCMDIDX[4] : Command Index Check Enable
1078 * ENCMDCRC[3] : Command CRC Check Enable
1083 * 11 = Length 48 Check busy after response
1085 /* Delay added before checking the status of frq change
1086 * retry not supported by mmc.c(core file)
1088 if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
1089 udelay(50000); /* wait 50 ms */
1091 if (!(cmd->resp_type & MMC_RSP_PRESENT))
1093 else if (cmd->resp_type & MMC_RSP_136)
1094 flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
1095 else if (cmd->resp_type & MMC_RSP_BUSY)
1096 flags = RSP_TYPE_LGHT48B;
1098 flags = RSP_TYPE_LGHT48;
1100 /* enable default flags */
1101 flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
1103 flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
1105 if (cmd->resp_type & MMC_RSP_CRC)
1106 flags |= CCCE_CHECK;
1107 if (cmd->resp_type & MMC_RSP_OPCODE)
1108 flags |= CICE_CHECK;
1111 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
1112 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
1113 flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
1114 data->blocksize = 512;
1115 writel(data->blocksize | (data->blocks << 16),
1118 writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
1120 if (data->flags & MMC_DATA_READ)
1121 flags |= (DP_DATA | DDIR_READ);
1123 flags |= (DP_DATA | DDIR_WRITE);
1125 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1126 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
1127 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1128 omap_hsmmc_prepare_data(mmc, data);
1134 mmc_enable_irq(mmc, cmd);
1136 writel(cmd->cmdarg, &mmc_base->arg);
1137 udelay(20); /* To fix "No status update" error on eMMC */
1138 writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
1140 start = get_timer(0);
1142 mmc_stat = readl(&mmc_base->stat);
1143 if (get_timer(start) > MAX_RETRY_MS) {
1144 printf("%s : timeout: No status update\n", __func__);
1147 } while (!mmc_stat);
1149 if ((mmc_stat & IE_CTO) != 0) {
1150 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
1152 } else if ((mmc_stat & ERRI_MASK) != 0)
1155 if (mmc_stat & CC_MASK) {
1156 writel(CC_MASK, &mmc_base->stat);
1157 if (cmd->resp_type & MMC_RSP_PRESENT) {
1158 if (cmd->resp_type & MMC_RSP_136) {
1159 /* response type 2 */
1160 cmd->response[3] = readl(&mmc_base->rsp10);
1161 cmd->response[2] = readl(&mmc_base->rsp32);
1162 cmd->response[1] = readl(&mmc_base->rsp54);
1163 cmd->response[0] = readl(&mmc_base->rsp76);
1165 /* response types 1, 1b, 3, 4, 5, 6 */
1166 cmd->response[0] = readl(&mmc_base->rsp10);
1170 #ifdef CONFIG_MMC_OMAP_HS_ADMA
1171 if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
1172 !mmc_is_tuning_cmd(cmd->cmdidx)) {
1175 if (mmc_stat & IE_ADMAE) {
1176 omap_hsmmc_dma_cleanup(mmc);
1180 sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
1181 timeout = sz_mb * DMA_TIMEOUT_PER_MB;
1182 if (timeout < MAX_RETRY_MS)
1183 timeout = MAX_RETRY_MS;
1185 start = get_timer(0);
1187 mmc_stat = readl(&mmc_base->stat);
1188 if (mmc_stat & TC_MASK) {
1189 writel(readl(&mmc_base->stat) | TC_MASK,
1193 if (get_timer(start) > timeout) {
1194 printf("%s : DMA timeout: No status update\n",
1200 omap_hsmmc_dma_cleanup(mmc);
1205 if (data && (data->flags & MMC_DATA_READ)) {
1206 mmc_read_data(mmc_base, data->dest,
1207 data->blocksize * data->blocks);
1208 } else if (data && (data->flags & MMC_DATA_WRITE)) {
1209 mmc_write_data(mmc_base, data->src,
1210 data->blocksize * data->blocks);
1215 static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
1217 unsigned int *output_buf = (unsigned int *)buf;
1218 unsigned int mmc_stat;
1224 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1228 ulong start = get_timer(0);
1230 mmc_stat = readl(&mmc_base->stat);
1231 if (get_timer(0) - start > MAX_RETRY_MS) {
1232 printf("%s: timedout waiting for status!\n",
1236 } while (mmc_stat == 0);
1238 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1239 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1241 if ((mmc_stat & ERRI_MASK) != 0)
1244 if (mmc_stat & BRR_MASK) {
1247 writel(readl(&mmc_base->stat) | BRR_MASK,
1249 for (k = 0; k < count; k++) {
1250 *output_buf = readl(&mmc_base->data);
1256 if (mmc_stat & BWR_MASK)
1257 writel(readl(&mmc_base->stat) | BWR_MASK,
1260 if (mmc_stat & TC_MASK) {
1261 writel(readl(&mmc_base->stat) | TC_MASK,
1269 #if CONFIG_IS_ENABLED(MMC_WRITE)
1270 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1273 unsigned int *input_buf = (unsigned int *)buf;
1274 unsigned int mmc_stat;
1278 * Start Polled Write
1280 count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
1284 ulong start = get_timer(0);
1286 mmc_stat = readl(&mmc_base->stat);
1287 if (get_timer(0) - start > MAX_RETRY_MS) {
1288 printf("%s: timedout waiting for status!\n",
1292 } while (mmc_stat == 0);
1294 if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
1295 mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
1297 if ((mmc_stat & ERRI_MASK) != 0)
1300 if (mmc_stat & BWR_MASK) {
1303 writel(readl(&mmc_base->stat) | BWR_MASK,
1305 for (k = 0; k < count; k++) {
1306 writel(*input_buf, &mmc_base->data);
1312 if (mmc_stat & BRR_MASK)
1313 writel(readl(&mmc_base->stat) | BRR_MASK,
1316 if (mmc_stat & TC_MASK) {
1317 writel(readl(&mmc_base->stat) | TC_MASK,
1325 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
1331 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
1333 writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
1336 static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
1338 writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
1341 static void omap_hsmmc_set_clock(struct mmc *mmc)
1343 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1344 struct hsmmc *mmc_base;
1345 unsigned int dsor = 0;
1348 mmc_base = priv->base_addr;
1349 omap_hsmmc_stop_clock(mmc_base);
1351 /* TODO: Is setting DTO required here? */
1352 mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
1353 (ICE_STOP | DTO_15THDTO));
1355 if (mmc->clock != 0) {
1356 dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
1357 if (dsor > CLKD_MAX)
1363 mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
1364 (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
1366 start = get_timer(0);
1367 while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
1368 if (get_timer(0) - start > MAX_RETRY_MS) {
1369 printf("%s: timedout waiting for ics!\n", __func__);
1374 priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
1375 mmc->clock = priv->clock;
1376 omap_hsmmc_start_clock(mmc_base);
1379 static void omap_hsmmc_set_bus_width(struct mmc *mmc)
1381 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1382 struct hsmmc *mmc_base;
1384 mmc_base = priv->base_addr;
1385 /* configue bus width */
1386 switch (mmc->bus_width) {
1388 writel(readl(&mmc_base->con) | DTW_8_BITMODE,
1393 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1395 writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
1401 writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
1403 writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
1408 priv->bus_width = mmc->bus_width;
1411 #if !CONFIG_IS_ENABLED(DM_MMC)
1412 static int omap_hsmmc_set_ios(struct mmc *mmc)
1414 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1416 static int omap_hsmmc_set_ios(struct udevice *dev)
1418 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1419 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1420 struct mmc *mmc = upriv->mmc;
1422 struct hsmmc *mmc_base = priv->base_addr;
1425 if (priv->bus_width != mmc->bus_width)
1426 omap_hsmmc_set_bus_width(mmc);
1428 if (priv->clock != mmc->clock)
1429 omap_hsmmc_set_clock(mmc);
1431 if (mmc->clk_disable)
1432 omap_hsmmc_stop_clock(mmc_base);
1434 omap_hsmmc_start_clock(mmc_base);
1436 #if CONFIG_IS_ENABLED(DM_MMC)
1437 if (priv->mode != mmc->selected_mode)
1438 omap_hsmmc_set_timing(mmc);
1440 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1441 if (priv->signal_voltage != mmc->signal_voltage)
1442 ret = omap_hsmmc_set_signal_voltage(mmc);
1448 #ifdef OMAP_HSMMC_USE_GPIO
1449 #if CONFIG_IS_ENABLED(DM_MMC)
1450 static int omap_hsmmc_getcd(struct udevice *dev)
1453 #if CONFIG_IS_ENABLED(DM_GPIO)
1454 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1455 value = dm_gpio_get_value(&priv->cd_gpio);
1457 /* if no CD return as 1 */
1464 static int omap_hsmmc_getwp(struct udevice *dev)
1467 #if CONFIG_IS_ENABLED(DM_GPIO)
1468 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1469 value = dm_gpio_get_value(&priv->wp_gpio);
1471 /* if no WP return as 0 */
1477 static int omap_hsmmc_getcd(struct mmc *mmc)
1479 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1482 /* if no CD return as 1 */
1483 cd_gpio = priv->cd_gpio;
1487 /* NOTE: assumes card detect signal is active-low */
1488 return !gpio_get_value(cd_gpio);
1491 static int omap_hsmmc_getwp(struct mmc *mmc)
1493 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1496 /* if no WP return as 0 */
1497 wp_gpio = priv->wp_gpio;
1501 /* NOTE: assumes write protect signal is active-high */
1502 return gpio_get_value(wp_gpio);
1507 #if CONFIG_IS_ENABLED(DM_MMC)
1508 static const struct dm_mmc_ops omap_hsmmc_ops = {
1509 .send_cmd = omap_hsmmc_send_cmd,
1510 .set_ios = omap_hsmmc_set_ios,
1511 #ifdef OMAP_HSMMC_USE_GPIO
1512 .get_cd = omap_hsmmc_getcd,
1513 .get_wp = omap_hsmmc_getwp,
1515 #ifdef MMC_SUPPORTS_TUNING
1516 .execute_tuning = omap_hsmmc_execute_tuning,
1518 .wait_dat0 = omap_hsmmc_wait_dat0,
1521 static const struct mmc_ops omap_hsmmc_ops = {
1522 .send_cmd = omap_hsmmc_send_cmd,
1523 .set_ios = omap_hsmmc_set_ios,
1524 .init = omap_hsmmc_init_setup,
1525 #ifdef OMAP_HSMMC_USE_GPIO
1526 .getcd = omap_hsmmc_getcd,
1527 .getwp = omap_hsmmc_getwp,
1532 #if !CONFIG_IS_ENABLED(DM_MMC)
1533 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
1537 struct omap_hsmmc_data *priv;
1538 struct mmc_config *cfg;
1541 priv = calloc(1, sizeof(*priv));
1545 host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
1547 switch (dev_index) {
1549 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1551 #ifdef OMAP_HSMMC2_BASE
1553 priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
1554 #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
1555 defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
1556 defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
1557 defined(CONFIG_HSMMC2_8BIT)
1558 /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
1559 host_caps_val |= MMC_MODE_8BIT;
1563 #ifdef OMAP_HSMMC3_BASE
1565 priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
1566 #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
1567 /* Enable 8-bit interface for eMMC on DRA7XX */
1568 host_caps_val |= MMC_MODE_8BIT;
1573 priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
1576 #ifdef OMAP_HSMMC_USE_GPIO
1577 /* on error gpio values are set to -1, which is what we want */
1578 priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
1579 priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
1584 cfg->name = "OMAP SD/MMC";
1585 cfg->ops = &omap_hsmmc_ops;
1587 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1588 cfg->host_caps = host_caps_val & ~host_caps_mask;
1590 cfg->f_min = 400000;
1595 if (cfg->host_caps & MMC_MODE_HS) {
1596 if (cfg->host_caps & MMC_MODE_HS_52MHz)
1597 cfg->f_max = 52000000;
1599 cfg->f_max = 26000000;
1601 cfg->f_max = 20000000;
1604 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1606 #if defined(CONFIG_OMAP34XX)
1608 * Silicon revs 2.1 and older do not support multiblock transfers.
1610 if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
1614 mmc = mmc_create(cfg, priv);
1622 #ifdef CONFIG_IODELAY_RECALIBRATION
1623 static struct pad_conf_entry *
1624 omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
1627 struct pad_conf_entry *padconf;
1629 padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
1631 debug("failed to allocate memory\n");
1635 while (index < count) {
1636 padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
1637 padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
1644 static struct iodelay_cfg_entry *
1645 omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
1648 struct iodelay_cfg_entry *iodelay;
1650 iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
1652 debug("failed to allocate memory\n");
1656 while (index < count) {
1657 iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
1658 iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
1659 iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
1666 static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
1667 const char *name, int *len)
1669 const void *fdt = gd->fdt_blob;
1671 const fdt32_t *pinctrl;
1673 offset = fdt_node_offset_by_phandle(fdt, phandle);
1675 debug("failed to get pinctrl node %s.\n",
1676 fdt_strerror(offset));
1680 pinctrl = fdt_getprop(fdt, offset, name, len);
1682 debug("failed to get property %s\n", name);
1689 static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
1692 const void *fdt = gd->fdt_blob;
1693 const __be32 *phandle;
1694 int node = dev_of_offset(mmc->dev);
1696 phandle = fdt_getprop(fdt, node, prop_name, NULL);
1698 debug("failed to get property %s\n", prop_name);
1702 return fdt32_to_cpu(*phandle);
1705 static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
1708 const void *fdt = gd->fdt_blob;
1709 const __be32 *phandle;
1712 int node = dev_of_offset(mmc->dev);
1714 phandle = fdt_getprop(fdt, node, prop_name, &len);
1716 debug("failed to get property %s\n", prop_name);
1720 /* No manual mode iodelay values if count < 2 */
1721 count = len / sizeof(*phandle);
1725 return fdt32_to_cpu(*(phandle + 1));
1728 static struct pad_conf_entry *
1729 omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
1733 struct pad_conf_entry *padconf;
1735 const fdt32_t *pinctrl;
1737 phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
1739 return ERR_PTR(-EINVAL);
1741 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
1744 return ERR_PTR(-EINVAL);
1746 count = (len / sizeof(*pinctrl)) / 2;
1747 padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
1749 return ERR_PTR(-EINVAL);
1756 static struct iodelay_cfg_entry *
1757 omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
1761 struct iodelay_cfg_entry *iodelay;
1763 const fdt32_t *pinctrl;
1765 phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
1766 /* Not all modes have manual mode iodelay values. So its not fatal */
1770 pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
1773 return ERR_PTR(-EINVAL);
1775 count = (len / sizeof(*pinctrl)) / 3;
1776 iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
1778 return ERR_PTR(-EINVAL);
1785 static struct omap_hsmmc_pinctrl_state *
1786 omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
1791 const void *fdt = gd->fdt_blob;
1792 int node = dev_of_offset(mmc->dev);
1794 struct omap_hsmmc_pinctrl_state *pinctrl_state;
1796 pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
1797 malloc(sizeof(*pinctrl_state));
1798 if (!pinctrl_state) {
1799 debug("failed to allocate memory\n");
1803 index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
1805 debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
1806 goto err_pinctrl_state;
1809 sprintf(prop_name, "pinctrl-%d", index);
1811 pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
1813 if (IS_ERR(pinctrl_state->padconf))
1814 goto err_pinctrl_state;
1815 pinctrl_state->npads = npads;
1817 pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
1819 if (IS_ERR(pinctrl_state->iodelay))
1821 pinctrl_state->niodelays = niodelays;
1823 return pinctrl_state;
1826 kfree(pinctrl_state->padconf);
1829 kfree(pinctrl_state);
1833 #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
1835 struct omap_hsmmc_pinctrl_state *s = NULL; \
1837 if (!(cfg->host_caps & capmask)) \
1840 if (priv->hw_rev) { \
1841 sprintf(str, "%s-%s", #mode, priv->hw_rev); \
1842 s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
1846 s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
1848 if (!s && !optional) { \
1849 debug("%s: no pinctrl for %s\n", \
1850 mmc->dev->name, #mode); \
1851 cfg->host_caps &= ~(capmask); \
1853 priv->mode##_pinctrl_state = s; \
1857 static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
1859 struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
1860 struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
1861 struct omap_hsmmc_pinctrl_state *default_pinctrl;
1863 if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
1866 default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
1867 if (!default_pinctrl) {
1868 printf("no pinctrl state for default mode\n");
1872 priv->default_pinctrl_state = default_pinctrl;
1874 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
1875 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
1876 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
1877 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
1878 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
1880 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
1881 OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
1882 OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
1888 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1889 #ifdef CONFIG_OMAP54XX
1890 __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
1896 static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
1898 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1899 struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
1901 struct mmc_config *cfg = &plat->cfg;
1902 #ifdef CONFIG_OMAP54XX
1903 const struct mmc_platform_fixups *fixups;
1905 const void *fdt = gd->fdt_blob;
1906 int node = dev_of_offset(dev);
1909 plat->base_addr = map_physmem(devfdt_get_addr(dev),
1910 sizeof(struct hsmmc *),
1913 ret = mmc_of_parse(dev, cfg);
1918 cfg->f_max = 52000000;
1919 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1920 cfg->f_min = 400000;
1921 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
1922 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1923 if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
1924 plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1925 if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
1926 plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
1928 plat->controller_flags |= of_data->controller_flags;
1930 #ifdef CONFIG_OMAP54XX
1931 fixups = platform_fixups_mmc(devfdt_get_addr(dev));
1933 plat->hw_rev = fixups->hw_rev;
1934 cfg->host_caps &= ~fixups->unsupported_caps;
1935 cfg->f_max = fixups->max_freq;
1945 static int omap_hsmmc_bind(struct udevice *dev)
1947 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1948 plat->mmc = calloc(1, sizeof(struct mmc));
1949 return mmc_bind(dev, plat->mmc, &plat->cfg);
1952 static int omap_hsmmc_probe(struct udevice *dev)
1954 struct omap_hsmmc_plat *plat = dev_get_platdata(dev);
1955 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1956 struct omap_hsmmc_data *priv = dev_get_priv(dev);
1957 struct mmc_config *cfg = &plat->cfg;
1959 #ifdef CONFIG_IODELAY_RECALIBRATION
1963 cfg->name = "OMAP SD/MMC";
1964 priv->base_addr = plat->base_addr;
1965 priv->controller_flags = plat->controller_flags;
1966 priv->hw_rev = plat->hw_rev;
1971 mmc = mmc_create(cfg, priv);
1975 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1976 device_get_supply_regulator(dev, "pbias-supply",
1977 &priv->pbias_supply);
1979 #if defined(OMAP_HSMMC_USE_GPIO)
1980 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
1981 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
1982 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
1989 #ifdef CONFIG_IODELAY_RECALIBRATION
1990 ret = omap_hsmmc_get_pinctrl_state(mmc);
1992 * disable high speed modes for the platforms that require IO delay
1993 * and for which we don't have this information
1996 (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
1997 priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
1998 cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
2003 return omap_hsmmc_init_setup(mmc);
2006 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2008 static const struct omap_mmc_of_data dra7_mmc_of_data = {
2009 .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
2012 static const struct udevice_id omap_hsmmc_ids[] = {
2013 { .compatible = "ti,omap3-hsmmc" },
2014 { .compatible = "ti,omap4-hsmmc" },
2015 { .compatible = "ti,am33xx-hsmmc" },
2016 { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
2021 U_BOOT_DRIVER(omap_hsmmc) = {
2022 .name = "omap_hsmmc",
2024 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
2025 .of_match = omap_hsmmc_ids,
2026 .ofdata_to_platdata = omap_hsmmc_ofdata_to_platdata,
2027 .platdata_auto_alloc_size = sizeof(struct omap_hsmmc_plat),
2030 .bind = omap_hsmmc_bind,
2032 .ops = &omap_hsmmc_ops,
2033 .probe = omap_hsmmc_probe,
2034 .priv_auto_alloc_size = sizeof(struct omap_hsmmc_data),
2035 #if !CONFIG_IS_ENABLED(OF_CONTROL)
2036 .flags = DM_FLAG_PRE_RELOC,