drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_finish_data(struct sdhci_host *);
  51
  52 static void sdhci_finish_command(struct sdhci_host *);
  53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  54 static void sdhci_tuning_timer(unsigned long data);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56
  57 #ifdef CONFIG_PM
  58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  62 #else
  63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  64 {
  65         return 0;
  66 }
  67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  68 {
  69         return 0;
  70 }
  71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  72 {
  73 }
  74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  75 {
  76 }
  77 #endif
  78
  79 static void sdhci_dumpregs(struct sdhci_host *host)
  80 {
  81         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  82                 mmc_hostname(host->mmc));
  83
  84         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  85                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  86                 sdhci_readw(host, SDHCI_HOST_VERSION));
  87         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  88                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  89                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  90         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  91                 sdhci_readl(host, SDHCI_ARGUMENT),
  92                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  93         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  95                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  96         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  97                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  98                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  99         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 100                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 101                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 102         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 103                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 104                 sdhci_readl(host, SDHCI_INT_STATUS));
 105         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 106                 sdhci_readl(host, SDHCI_INT_ENABLE),
 107                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 108         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 109                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 110                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 111         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 112                 sdhci_readl(host, SDHCI_CAPABILITIES),
 113                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 114         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 115                 sdhci_readw(host, SDHCI_COMMAND),
 116                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 117         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 119
 120         if (host->flags & SDHCI_USE_ADMA) {
 121                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 122                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 123                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 124                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 125                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 126                 else
 127                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 128                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 129                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 130         }
 131
 132         pr_debug(DRIVER_NAME ": ===========================================\n");
 133 }
 134
 135 /*****************************************************************************\
 136  *                                                                           *
 137  * Low level functions                                                       *
 138  *                                                                           *
 139 \*****************************************************************************/
 140
 141 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 142 {
 143         u32 present;
 144
 145         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 146             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 147                 return;
 148
 149         if (enable) {
 150                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 151                                       SDHCI_CARD_PRESENT;
 152
 153                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 154                                        SDHCI_INT_CARD_INSERT;
 155         } else {
 156                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 157         }
 158
 159         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 160         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 161 }
 162
 163 static void sdhci_enable_card_detection(struct sdhci_host *host)
 164 {
 165         sdhci_set_card_detection(host, true);
 166 }
 167
 168 static void sdhci_disable_card_detection(struct sdhci_host *host)
 169 {
 170         sdhci_set_card_detection(host, false);
 171 }
 172
 173 void sdhci_reset(struct sdhci_host *host, u8 mask)
 174 {
 175         unsigned long timeout;
 176
 177         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 178
 179         if (mask & SDHCI_RESET_ALL) {
 180                 host->clock = 0;
 181                 /* Reset-all turns off SD Bus Power */
 182                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 183                         sdhci_runtime_pm_bus_off(host);
 184         }
 185
 186         /* Wait max 100 ms */
 187         timeout = 100;
 188
 189         /* hw clears the bit when it's done */
 190         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 191                 if (timeout == 0) {
 192                         pr_err("%s: Reset 0x%x never completed.\n",
 193                                 mmc_hostname(host->mmc), (int)mask);
 194                         sdhci_dumpregs(host);
 195                         return;
 196                 }
 197                 timeout--;
 198                 mdelay(1);
 199         }
 200 }
 201 EXPORT_SYMBOL_GPL(sdhci_reset);
 202
 203 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 204 {
 205         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 206                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 207                         SDHCI_CARD_PRESENT))
 208                         return;
 209         }
 210
 211         host->ops->reset(host, mask);
 212
 213         if (mask & SDHCI_RESET_ALL) {
 214                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 215                         if (host->ops->enable_dma)
 216                                 host->ops->enable_dma(host);
 217                 }
 218
 219                 /* Resetting the controller clears many */
 220                 host->preset_enabled = false;
 221         }
 222 }
 223
 224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 225
 226 static void sdhci_init(struct sdhci_host *host, int soft)
 227 {
 228         if (soft)
 229                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 230         else
 231                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 232
 233         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 234                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 235                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 236                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 237                     SDHCI_INT_RESPONSE;
 238
 239         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 240         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 241
 242         if (soft) {
 243                 /* force clock reconfiguration */
 244                 host->clock = 0;
 245                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 246         }
 247 }
 248
 249 static void sdhci_reinit(struct sdhci_host *host)
 250 {
 251         sdhci_init(host, 0);
 252         /*
 253          * Retuning stuffs are affected by different cards inserted and only
 254          * applicable to UHS-I cards. So reset these fields to their initial
 255          * value when card is removed.
 256          */
 257         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 258                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 259
 260                 del_timer_sync(&host->tuning_timer);
 261                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 262         }
 263         sdhci_enable_card_detection(host);
 264 }
 265
 266 static void sdhci_activate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl |= SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 static void sdhci_deactivate_led(struct sdhci_host *host)
 276 {
 277         u8 ctrl;
 278
 279         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 280         ctrl &= ~SDHCI_CTRL_LED;
 281         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 282 }
 283
 284 #ifdef SDHCI_USE_LEDS_CLASS
 285 static void sdhci_led_control(struct led_classdev *led,
 286         enum led_brightness brightness)
 287 {
 288         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 289         unsigned long flags;
 290
 291         spin_lock_irqsave(&host->lock, flags);
 292
 293         if (host->runtime_suspended)
 294                 goto out;
 295
 296         if (brightness == LED_OFF)
 297                 sdhci_deactivate_led(host);
 298         else
 299                 sdhci_activate_led(host);
 300 out:
 301         spin_unlock_irqrestore(&host->lock, flags);
 302 }
 303 #endif
 304
 305 /*****************************************************************************\
 306  *                                                                           *
 307  * Core functions                                                            *
 308  *                                                                           *
 309 \*****************************************************************************/
 310
 311 static void sdhci_read_block_pio(struct sdhci_host *host)
 312 {
 313         unsigned long flags;
 314         size_t blksize, len, chunk;
 315         u32 uninitialized_var(scratch);
 316         u8 *buf;
 317
 318         DBG("PIO reading\n");
 319
 320         blksize = host->data->blksz;
 321         chunk = 0;
 322
 323         local_irq_save(flags);
 324
 325         while (blksize) {
 326                 if (!sg_miter_next(&host->sg_miter))
 327                         BUG();
 328
 329                 len = min(host->sg_miter.length, blksize);
 330
 331                 blksize -= len;
 332                 host->sg_miter.consumed = len;
 333
 334                 buf = host->sg_miter.addr;
 335
 336                 while (len) {
 337                         if (chunk == 0) {
 338                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 339                                 chunk = 4;
 340                         }
 341
 342                         *buf = scratch & 0xFF;
 343
 344                         buf++;
 345                         scratch >>= 8;
 346                         chunk--;
 347                         len--;
 348                 }
 349         }
 350
 351         sg_miter_stop(&host->sg_miter);
 352
 353         local_irq_restore(flags);
 354 }
 355
 356 static void sdhci_write_block_pio(struct sdhci_host *host)
 357 {
 358         unsigned long flags;
 359         size_t blksize, len, chunk;
 360         u32 scratch;
 361         u8 *buf;
 362
 363         DBG("PIO writing\n");
 364
 365         blksize = host->data->blksz;
 366         chunk = 0;
 367         scratch = 0;
 368
 369         local_irq_save(flags);
 370
 371         while (blksize) {
 372                 if (!sg_miter_next(&host->sg_miter))
 373                         BUG();
 374
 375                 len = min(host->sg_miter.length, blksize);
 376
 377                 blksize -= len;
 378                 host->sg_miter.consumed = len;
 379
 380                 buf = host->sg_miter.addr;
 381
 382                 while (len) {
 383                         scratch |= (u32)*buf << (chunk * 8);
 384
 385                         buf++;
 386                         chunk++;
 387                         len--;
 388
 389                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 390                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 391                                 chunk = 0;
 392                                 scratch = 0;
 393                         }
 394                 }
 395         }
 396
 397         sg_miter_stop(&host->sg_miter);
 398
 399         local_irq_restore(flags);
 400 }
 401
 402 static void sdhci_transfer_pio(struct sdhci_host *host)
 403 {
 404         u32 mask;
 405
 406         BUG_ON(!host->data);
 407
 408         if (host->blocks == 0)
 409                 return;
 410
 411         if (host->data->flags & MMC_DATA_READ)
 412                 mask = SDHCI_DATA_AVAILABLE;
 413         else
 414                 mask = SDHCI_SPACE_AVAILABLE;
 415
 416         /*
 417          * Some controllers (JMicron JMB38x) mess up the buffer bits
 418          * for transfers < 4 bytes. As long as it is just one block,
 419          * we can ignore the bits.
 420          */
 421         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 422                 (host->data->blocks == 1))
 423                 mask = ~0;
 424
 425         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 426                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 427                         udelay(100);
 428
 429                 if (host->data->flags & MMC_DATA_READ)
 430                         sdhci_read_block_pio(host);
 431                 else
 432                         sdhci_write_block_pio(host);
 433
 434                 host->blocks--;
 435                 if (host->blocks == 0)
 436                         break;
 437         }
 438
 439         DBG("PIO transfer complete.\n");
 440 }
 441
 442 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 443 {
 444         local_irq_save(*flags);
 445         return kmap_atomic(sg_page(sg)) + sg->offset;
 446 }
 447
 448 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 449 {
 450         kunmap_atomic(buffer);
 451         local_irq_restore(*flags);
 452 }
 453
 454 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 455                                   dma_addr_t addr, int len, unsigned cmd)
 456 {
 457         struct sdhci_adma2_64_desc *dma_desc = desc;
 458
 459         /* 32-bit and 64-bit descriptors have these members in same position */
 460         dma_desc->cmd = cpu_to_le16(cmd);
 461         dma_desc->len = cpu_to_le16(len);
 462         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 463
 464         if (host->flags & SDHCI_USE_64_BIT_DMA)
 465                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 466 }
 467
 468 static void sdhci_adma_mark_end(void *desc)
 469 {
 470         struct sdhci_adma2_64_desc *dma_desc = desc;
 471
 472         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 473         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 474 }
 475
 476 static int sdhci_adma_table_pre(struct sdhci_host *host,
 477         struct mmc_data *data)
 478 {
 479         int direction;
 480
 481         void *desc;
 482         void *align;
 483         dma_addr_t addr;
 484         dma_addr_t align_addr;
 485         int len, offset;
 486
 487         struct scatterlist *sg;
 488         int i;
 489         char *buffer;
 490         unsigned long flags;
 491
 492         /*
 493          * The spec does not specify endianness of descriptor table.
 494          * We currently guess that it is LE.
 495          */
 496
 497         if (data->flags & MMC_DATA_READ)
 498                 direction = DMA_FROM_DEVICE;
 499         else
 500                 direction = DMA_TO_DEVICE;
 501
 502         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 503                 host->align_buffer, host->align_buffer_sz, direction);
 504         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 505                 goto fail;
 506         BUG_ON(host->align_addr & host->align_mask);
 507
 508         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 509                 data->sg, data->sg_len, direction);
 510         if (host->sg_count == 0)
 511                 goto unmap_align;
 512
 513         desc = host->adma_table;
 514         align = host->align_buffer;
 515
 516         align_addr = host->align_addr;
 517
 518         for_each_sg(data->sg, sg, host->sg_count, i) {
 519                 addr = sg_dma_address(sg);
 520                 len = sg_dma_len(sg);
 521
 522                 /*
 523                  * The SDHCI specification states that ADMA
 524                  * addresses must be 32-bit aligned. If they
 525                  * aren't, then we use a bounce buffer for
 526                  * the (up to three) bytes that screw up the
 527                  * alignment.
 528                  */
 529                 offset = (host->align_sz - (addr & host->align_mask)) &
 530                          host->align_mask;
 531                 if (offset) {
 532                         if (data->flags & MMC_DATA_WRITE) {
 533                                 buffer = sdhci_kmap_atomic(sg, &flags);
 534                                 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
 535                                         (PAGE_SIZE - offset));
 536                                 memcpy(align, buffer, offset);
 537                                 sdhci_kunmap_atomic(buffer, &flags);
 538                         }
 539
 540                         /* tran, valid */
 541                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 542                                               ADMA2_TRAN_VALID);
 543
 544                         BUG_ON(offset > 65536);
 545
 546                         align += host->align_sz;
 547                         align_addr += host->align_sz;
 548
 549                         desc += host->desc_sz;
 550
 551                         addr += offset;
 552                         len -= offset;
 553                 }
 554
 555                 BUG_ON(len > 65536);
 556
 557                 /* tran, valid */
 558                 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
 559                 desc += host->desc_sz;
 560
 561                 /*
 562                  * If this triggers then we have a calculation bug
 563                  * somewhere. :/
 564                  */
 565                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 566         }
 567
 568         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 569                 /*
 570                 * Mark the last descriptor as the terminating descriptor
 571                 */
 572                 if (desc != host->adma_table) {
 573                         desc -= host->desc_sz;
 574                         sdhci_adma_mark_end(desc);
 575                 }
 576         } else {
 577                 /*
 578                 * Add a terminating entry.
 579                 */
 580
 581                 /* nop, end, valid */
 582                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 583         }
 584
 585         /*
 586          * Resync align buffer as we might have changed it.
 587          */
 588         if (data->flags & MMC_DATA_WRITE) {
 589                 dma_sync_single_for_device(mmc_dev(host->mmc),
 590                         host->align_addr, host->align_buffer_sz, direction);
 591         }
 592
 593         return 0;
 594
 595 unmap_align:
 596         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 597                 host->align_buffer_sz, direction);
 598 fail:
 599         return -EINVAL;
 600 }
 601
 602 static void sdhci_adma_table_post(struct sdhci_host *host,
 603         struct mmc_data *data)
 604 {
 605         int direction;
 606
 607         struct scatterlist *sg;
 608         int i, size;
 609         void *align;
 610         char *buffer;
 611         unsigned long flags;
 612         bool has_unaligned;
 613
 614         if (data->flags & MMC_DATA_READ)
 615                 direction = DMA_FROM_DEVICE;
 616         else
 617                 direction = DMA_TO_DEVICE;
 618
 619         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 620                 host->align_buffer_sz, direction);
 621
 622         /* Do a quick scan of the SG list for any unaligned mappings */
 623         has_unaligned = false;
 624         for_each_sg(data->sg, sg, host->sg_count, i)
 625                 if (sg_dma_address(sg) & host->align_mask) {
 626                         has_unaligned = true;
 627                         break;
 628                 }
 629
 630         if (has_unaligned && data->flags & MMC_DATA_READ) {
 631                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 632                         data->sg_len, direction);
 633
 634                 align = host->align_buffer;
 635
 636                 for_each_sg(data->sg, sg, host->sg_count, i) {
 637                         if (sg_dma_address(sg) & host->align_mask) {
 638                                 size = host->align_sz -
 639                                        (sg_dma_address(sg) & host->align_mask);
 640
 641                                 buffer = sdhci_kmap_atomic(sg, &flags);
 642                                 WARN_ON(((long)buffer & (PAGE_SIZE - 1)) >
 643                                         (PAGE_SIZE - size));
 644                                 memcpy(buffer, align, size);
 645                                 sdhci_kunmap_atomic(buffer, &flags);
 646
 647                                 align += host->align_sz;
 648                         }
 649                 }
 650         }
 651
 652         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 653                 data->sg_len, direction);
 654 }
 655
 656 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 657 {
 658         u8 count;
 659         struct mmc_data *data = cmd->data;
 660         unsigned target_timeout, current_timeout;
 661
 662         /*
 663          * If the host controller provides us with an incorrect timeout
 664          * value, just skip the check and use 0xE.  The hardware may take
 665          * longer to time out, but that's much better than having a too-short
 666          * timeout value.
 667          */
 668         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 669                 return 0xE;
 670
 671         /* Unspecified timeout, assume max */
 672         if (!data && !cmd->busy_timeout)
 673                 return 0xE;
 674
 675         /* timeout in us */
 676         if (!data)
 677                 target_timeout = cmd->busy_timeout * 1000;
 678         else {
 679                 target_timeout = data->timeout_ns / 1000;
 680                 if (host->clock)
 681                         target_timeout += data->timeout_clks / host->clock;
 682         }
 683
 684         /*
 685          * Figure out needed cycles.
 686          * We do this in steps in order to fit inside a 32 bit int.
 687          * The first step is the minimum timeout, which will have a
 688          * minimum resolution of 6 bits:
 689          * (1) 2^13*1000 > 2^22,
 690          * (2) host->timeout_clk < 2^16
 691          *     =>
 692          *     (1) / (2) > 2^6
 693          */
 694         count = 0;
 695         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 696         while (current_timeout < target_timeout) {
 697                 count++;
 698                 current_timeout <<= 1;
 699                 if (count >= 0xF)
 700                         break;
 701         }
 702
 703         if (count >= 0xF) {
 704                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 705                     mmc_hostname(host->mmc), count, cmd->opcode);
 706                 count = 0xE;
 707         }
 708
 709         return count;
 710 }
 711
 712 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 713 {
 714         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 715         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 716
 717         if (host->flags & SDHCI_REQ_USE_DMA)
 718                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 719         else
 720                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 721
 722         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 723         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 724 }
 725
 726 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 727 {
 728         u8 count;
 729
 730         if (host->ops->set_timeout) {
 731                 host->ops->set_timeout(host, cmd);
 732         } else {
 733                 count = sdhci_calc_timeout(host, cmd);
 734                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 735         }
 736 }
 737
 738 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 739 {
 740         u8 ctrl;
 741         struct mmc_data *data = cmd->data;
 742         int ret;
 743
 744         WARN_ON(host->data);
 745
 746         if (data || (cmd->flags & MMC_RSP_BUSY))
 747                 sdhci_set_timeout(host, cmd);
 748
 749         if (!data)
 750                 return;
 751
 752         /* Sanity checks */
 753         BUG_ON(data->blksz * data->blocks > 524288);
 754         BUG_ON(data->blksz > host->mmc->max_blk_size);
 755         BUG_ON(data->blocks > 65535);
 756
 757         host->data = data;
 758         host->data_early = 0;
 759         host->data->bytes_xfered = 0;
 760
 761         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 762                 host->flags |= SDHCI_REQ_USE_DMA;
 763
 764         /*
 765          * FIXME: This doesn't account for merging when mapping the
 766          * scatterlist.
 767          */
 768         if (host->flags & SDHCI_REQ_USE_DMA) {
 769                 int broken, i;
 770                 struct scatterlist *sg;
 771
 772                 broken = 0;
 773                 if (host->flags & SDHCI_USE_ADMA) {
 774                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 775                                 broken = 1;
 776                 } else {
 777                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 778                                 broken = 1;
 779                 }
 780
 781                 if (unlikely(broken)) {
 782                         for_each_sg(data->sg, sg, data->sg_len, i) {
 783                                 if (sg->length & 0x3) {
 784                                         DBG("Reverting to PIO because of "
 785                                                 "transfer size (%d)\n",
 786                                                 sg->length);
 787                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 788                                         break;
 789                                 }
 790                         }
 791                 }
 792         }
 793
 794         /*
 795          * The assumption here being that alignment is the same after
 796          * translation to device address space.
 797          */
 798         if (host->flags & SDHCI_REQ_USE_DMA) {
 799                 int broken, i;
 800                 struct scatterlist *sg;
 801
 802                 broken = 0;
 803                 if (host->flags & SDHCI_USE_ADMA) {
 804                         /*
 805                          * As we use 3 byte chunks to work around
 806                          * alignment problems, we need to check this
 807                          * quirk.
 808                          */
 809                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 810                                 broken = 1;
 811                 } else {
 812                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 813                                 broken = 1;
 814                 }
 815
 816                 if (unlikely(broken)) {
 817                         for_each_sg(data->sg, sg, data->sg_len, i) {
 818                                 if (sg->offset & 0x3) {
 819                                         DBG("Reverting to PIO because of "
 820                                                 "bad alignment\n");
 821                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 822                                         break;
 823                                 }
 824                         }
 825                 }
 826         }
 827
 828         if (host->flags & SDHCI_REQ_USE_DMA) {
 829                 if (host->flags & SDHCI_USE_ADMA) {
 830                         ret = sdhci_adma_table_pre(host, data);
 831                         if (ret) {
 832                                 /*
 833                                  * This only happens when someone fed
 834                                  * us an invalid request.
 835                                  */
 836                                 WARN_ON(1);
 837                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 838                         } else {
 839                                 sdhci_writel(host, host->adma_addr,
 840                                         SDHCI_ADMA_ADDRESS);
 841                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 842                                         sdhci_writel(host,
 843                                                      (u64)host->adma_addr >> 32,
 844                                                      SDHCI_ADMA_ADDRESS_HI);
 845                         }
 846                 } else {
 847                         int sg_cnt;
 848
 849                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 850                                         data->sg, data->sg_len,
 851                                         (data->flags & MMC_DATA_READ) ?
 852                                                 DMA_FROM_DEVICE :
 853                                                 DMA_TO_DEVICE);
 854                         if (sg_cnt == 0) {
 855                                 /*
 856                                  * This only happens when someone fed
 857                                  * us an invalid request.
 858                                  */
 859                                 WARN_ON(1);
 860                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 861                         } else {
 862                                 WARN_ON(sg_cnt != 1);
 863                                 sdhci_writel(host, sg_dma_address(data->sg),
 864                                         SDHCI_DMA_ADDRESS);
 865                         }
 866                 }
 867         }
 868
 869         /*
 870          * Always adjust the DMA selection as some controllers
 871          * (e.g. JMicron) can't do PIO properly when the selection
 872          * is ADMA.
 873          */
 874         if (host->version >= SDHCI_SPEC_200) {
 875                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 876                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 877                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 878                         (host->flags & SDHCI_USE_ADMA)) {
 879                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 880                                 ctrl |= SDHCI_CTRL_ADMA64;
 881                         else
 882                                 ctrl |= SDHCI_CTRL_ADMA32;
 883                 } else {
 884                         ctrl |= SDHCI_CTRL_SDMA;
 885                 }
 886                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 887         }
 888
 889         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 890                 int flags;
 891
 892                 flags = SG_MITER_ATOMIC;
 893                 if (host->data->flags & MMC_DATA_READ)
 894                         flags |= SG_MITER_TO_SG;
 895                 else
 896                         flags |= SG_MITER_FROM_SG;
 897                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 898                 host->blocks = data->blocks;
 899         }
 900
 901         sdhci_set_transfer_irqs(host);
 902
 903         /* Set the DMA boundary value and block size */
 904         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 905                 data->blksz), SDHCI_BLOCK_SIZE);
 906         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 907 }
 908
 909 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 910         struct mmc_command *cmd)
 911 {
 912         u16 mode;
 913         struct mmc_data *data = cmd->data;
 914
 915         if (data == NULL) {
 916                 if (host->quirks2 &
 917                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 918                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 919                 } else {
 920                 /* clear Auto CMD settings for no data CMDs */
 921                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 922                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 923                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 924                 }
 925                 return;
 926         }
 927
 928         WARN_ON(!host->data);
 929
 930         mode = SDHCI_TRNS_BLK_CNT_EN;
 931         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 932                 mode |= SDHCI_TRNS_MULTI;
 933                 /*
 934                  * If we are sending CMD23, CMD12 never gets sent
 935                  * on successful completion (so no Auto-CMD12).
 936                  */
 937                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 938                         mode |= SDHCI_TRNS_AUTO_CMD12;
 939                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 940                         mode |= SDHCI_TRNS_AUTO_CMD23;
 941                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 942                 }
 943         }
 944
 945         if (data->flags & MMC_DATA_READ)
 946                 mode |= SDHCI_TRNS_READ;
 947         if (host->flags & SDHCI_REQ_USE_DMA)
 948                 mode |= SDHCI_TRNS_DMA;
 949
 950         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 951 }
 952
 953 static void sdhci_finish_data(struct sdhci_host *host)
 954 {
 955         struct mmc_data *data;
 956
 957         BUG_ON(!host->data);
 958
 959         data = host->data;
 960         host->data = NULL;
 961
 962         if (host->flags & SDHCI_REQ_USE_DMA) {
 963                 if (host->flags & SDHCI_USE_ADMA)
 964                         sdhci_adma_table_post(host, data);
 965                 else {
 966                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 967                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 968                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 969                 }
 970         }
 971
 972         /*
 973          * The specification states that the block count register must
 974          * be updated, but it does not specify at what point in the
 975          * data flow. That makes the register entirely useless to read
 976          * back so we have to assume that nothing made it to the card
 977          * in the event of an error.
 978          */
 979         if (data->error)
 980                 data->bytes_xfered = 0;
 981         else
 982                 data->bytes_xfered = data->blksz * data->blocks;
 983
 984         /*
 985          * Need to send CMD12 if -
 986          * a) open-ended multiblock transfer (no CMD23)
 987          * b) error in multiblock transfer
 988          */
 989         if (data->stop &&
 990             (data->error ||
 991              !host->mrq->sbc)) {
 992
 993                 /*
 994                  * The controller needs a reset of internal state machines
 995                  * upon error conditions.
 996                  */
 997                 if (data->error) {
 998                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 999                         sdhci_do_reset(host, SDHCI_RESET_DATA);
1000                 }
1001
1002                 sdhci_send_command(host, data->stop);
1003         } else
1004                 tasklet_schedule(&host->finish_tasklet);
1005 }
1006
1007 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
1008 {
1009         int flags;
1010         u32 mask;
1011         unsigned long timeout;
1012
1013         WARN_ON(host->cmd);
1014
1015         /* Wait max 10 ms */
1016         timeout = 10;
1017
1018         mask = SDHCI_CMD_INHIBIT;
1019         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1020                 mask |= SDHCI_DATA_INHIBIT;
1021
1022         /* We shouldn't wait for data inihibit for stop commands, even
1023            though they might use busy signaling */
1024         if (host->mrq->data && (cmd == host->mrq->data->stop))
1025                 mask &= ~SDHCI_DATA_INHIBIT;
1026
1027         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1028                 if (timeout == 0) {
1029                         pr_err("%s: Controller never released "
1030                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1031                         sdhci_dumpregs(host);
1032                         cmd->error = -EIO;
1033                         tasklet_schedule(&host->finish_tasklet);
1034                         return;
1035                 }
1036                 timeout--;
1037                 mdelay(1);
1038         }
1039
1040         timeout = jiffies;
1041         if (!cmd->data && cmd->busy_timeout > 9000)
1042                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1043         else
1044                 timeout += 10 * HZ;
1045         mod_timer(&host->timer, timeout);
1046
1047         host->cmd = cmd;
1048         host->busy_handle = 0;
1049
1050         sdhci_prepare_data(host, cmd);
1051
1052         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1053
1054         sdhci_set_transfer_mode(host, cmd);
1055
1056         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1057                 pr_err("%s: Unsupported response type!\n",
1058                         mmc_hostname(host->mmc));
1059                 cmd->error = -EINVAL;
1060                 tasklet_schedule(&host->finish_tasklet);
1061                 return;
1062         }
1063
1064         if (!(cmd->flags & MMC_RSP_PRESENT))
1065                 flags = SDHCI_CMD_RESP_NONE;
1066         else if (cmd->flags & MMC_RSP_136)
1067                 flags = SDHCI_CMD_RESP_LONG;
1068         else if (cmd->flags & MMC_RSP_BUSY)
1069                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1070         else
1071                 flags = SDHCI_CMD_RESP_SHORT;
1072
1073         if (cmd->flags & MMC_RSP_CRC)
1074                 flags |= SDHCI_CMD_CRC;
1075         if (cmd->flags & MMC_RSP_OPCODE)
1076                 flags |= SDHCI_CMD_INDEX;
1077
1078         /* CMD19 is special in that the Data Present Select should be set */
1079         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1080             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1081                 flags |= SDHCI_CMD_DATA;
1082
1083         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1084 }
1085 EXPORT_SYMBOL_GPL(sdhci_send_command);
1086
1087 static void sdhci_finish_command(struct sdhci_host *host)
1088 {
1089         int i;
1090
1091         BUG_ON(host->cmd == NULL);
1092
1093         if (host->cmd->flags & MMC_RSP_PRESENT) {
1094                 if (host->cmd->flags & MMC_RSP_136) {
1095                         /* CRC is stripped so we need to do some shifting. */
1096                         for (i = 0;i < 4;i++) {
1097                                 host->cmd->resp[i] = sdhci_readl(host,
1098                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1099                                 if (i != 3)
1100                                         host->cmd->resp[i] |=
1101                                                 sdhci_readb(host,
1102                                                 SDHCI_RESPONSE + (3-i)*4-1);
1103                         }
1104                 } else {
1105                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1106                 }
1107         }
1108
1109         host->cmd->error = 0;
1110
1111         /* Finished CMD23, now send actual command. */
1112         if (host->cmd == host->mrq->sbc) {
1113                 host->cmd = NULL;
1114                 sdhci_send_command(host, host->mrq->cmd);
1115         } else {
1116
1117                 /* Processed actual command. */
1118                 if (host->data && host->data_early)
1119                         sdhci_finish_data(host);
1120
1121                 if (!host->cmd->data)
1122                         tasklet_schedule(&host->finish_tasklet);
1123
1124                 host->cmd = NULL;
1125         }
1126 }
1127
1128 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1129 {
1130         u16 preset = 0;
1131
1132         switch (host->timing) {
1133         case MMC_TIMING_UHS_SDR12:
1134                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1135                 break;
1136         case MMC_TIMING_UHS_SDR25:
1137                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1138                 break;
1139         case MMC_TIMING_UHS_SDR50:
1140                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1141                 break;
1142         case MMC_TIMING_UHS_SDR104:
1143         case MMC_TIMING_MMC_HS200:
1144                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1145                 break;
1146         case MMC_TIMING_UHS_DDR50:
1147                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1148                 break;
1149         case MMC_TIMING_MMC_HS400:
1150                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1151                 break;
1152         default:
1153                 pr_warn("%s: Invalid UHS-I mode selected\n",
1154                         mmc_hostname(host->mmc));
1155                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1156                 break;
1157         }
1158         return preset;
1159 }
1160
1161 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1162 {
1163         int div = 0; /* Initialized for compiler warning */
1164         int real_div = div, clk_mul = 1;
1165         u16 clk = 0;
1166         unsigned long timeout;
1167
1168         host->mmc->actual_clock = 0;
1169
1170         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1171
1172         if (clock == 0)
1173                 return;
1174
1175         if (host->version >= SDHCI_SPEC_300) {
1176                 if (host->preset_enabled) {
1177                         u16 pre_val;
1178
1179                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1180                         pre_val = sdhci_get_preset_value(host);
1181                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1182                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1183                         if (host->clk_mul &&
1184                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1185                                 clk = SDHCI_PROG_CLOCK_MODE;
1186                                 real_div = div + 1;
1187                                 clk_mul = host->clk_mul;
1188                         } else {
1189                                 real_div = max_t(int, 1, div << 1);
1190                         }
1191                         goto clock_set;
1192                 }
1193
1194                 /*
1195                  * Check if the Host Controller supports Programmable Clock
1196                  * Mode.
1197                  */
1198                 if (host->clk_mul) {
1199                         for (div = 1; div <= 1024; div++) {
1200                                 if ((host->max_clk * host->clk_mul / div)
1201                                         <= clock)
1202                                         break;
1203                         }
1204                         /*
1205                          * Set Programmable Clock Mode in the Clock
1206                          * Control register.
1207                          */
1208                         clk = SDHCI_PROG_CLOCK_MODE;
1209                         real_div = div;
1210                         clk_mul = host->clk_mul;
1211                         div--;
1212                 } else {
1213                         /* Version 3.00 divisors must be a multiple of 2. */
1214                         if (host->max_clk <= clock)
1215                                 div = 1;
1216                         else {
1217                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1218                                      div += 2) {
1219                                         if ((host->max_clk / div) <= clock)
1220                                                 break;
1221                                 }
1222                         }
1223                         real_div = div;
1224                         div >>= 1;
1225                 }
1226         } else {
1227                 /* Version 2.00 divisors must be a power of 2. */
1228                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1229                         if ((host->max_clk / div) <= clock)
1230                                 break;
1231                 }
1232                 real_div = div;
1233                 div >>= 1;
1234         }
1235
1236 clock_set:
1237         if (real_div)
1238                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1239         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1240         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1241                 << SDHCI_DIVIDER_HI_SHIFT;
1242         clk |= SDHCI_CLOCK_INT_EN;
1243         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1244
1245         /* Wait max 20 ms */
1246         timeout = 20;
1247         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1248                 & SDHCI_CLOCK_INT_STABLE)) {
1249                 if (timeout == 0) {
1250                         pr_err("%s: Internal clock never "
1251                                 "stabilised.\n", mmc_hostname(host->mmc));
1252                         sdhci_dumpregs(host);
1253                         return;
1254                 }
1255                 timeout--;
1256                 mdelay(1);
1257         }
1258
1259         clk |= SDHCI_CLOCK_CARD_EN;
1260         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1261 }
1262 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1263
1264 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1265                             unsigned short vdd)
1266 {
1267         struct mmc_host *mmc = host->mmc;
1268         u8 pwr = 0;
1269
1270         if (!IS_ERR(mmc->supply.vmmc)) {
1271                 spin_unlock_irq(&host->lock);
1272                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1273                 spin_lock_irq(&host->lock);
1274                 return;
1275         }
1276
1277         if (mode != MMC_POWER_OFF) {
1278                 switch (1 << vdd) {
1279                 case MMC_VDD_165_195:
1280                         pwr = SDHCI_POWER_180;
1281                         break;
1282                 case MMC_VDD_29_30:
1283                 case MMC_VDD_30_31:
1284                         pwr = SDHCI_POWER_300;
1285                         break;
1286                 case MMC_VDD_32_33:
1287                 case MMC_VDD_33_34:
1288                         pwr = SDHCI_POWER_330;
1289                         break;
1290                 default:
1291                         BUG();
1292                 }
1293         }
1294
1295         if (host->pwr == pwr)
1296                 return;
1297
1298         host->pwr = pwr;
1299
1300         if (pwr == 0) {
1301                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1302                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1303                         sdhci_runtime_pm_bus_off(host);
1304                 vdd = 0;
1305         } else {
1306                 /*
1307                  * Spec says that we should clear the power reg before setting
1308                  * a new value. Some controllers don't seem to like this though.
1309                  */
1310                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1311                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1312
1313                 /*
1314                  * At least the Marvell CaFe chip gets confused if we set the
1315                  * voltage and set turn on power at the same time, so set the
1316                  * voltage first.
1317                  */
1318                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1319                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1320
1321                 pwr |= SDHCI_POWER_ON;
1322
1323                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1324
1325                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1326                         sdhci_runtime_pm_bus_on(host);
1327
1328                 /*
1329                  * Some controllers need an extra 10ms delay of 10ms before
1330                  * they can apply clock after applying power
1331                  */
1332                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1333                         mdelay(10);
1334         }
1335 }
1336
1337 /*****************************************************************************\
1338  *                                                                           *
1339  * MMC callbacks                                                             *
1340  *                                                                           *
1341 \*****************************************************************************/
1342
1343 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1344 {
1345         struct sdhci_host *host;
1346         int present;
1347         unsigned long flags;
1348         u32 tuning_opcode;
1349
1350         host = mmc_priv(mmc);
1351
1352         sdhci_runtime_pm_get(host);
1353
1354         spin_lock_irqsave(&host->lock, flags);
1355
1356         WARN_ON(host->mrq != NULL);
1357
1358 #ifndef SDHCI_USE_LEDS_CLASS
1359         sdhci_activate_led(host);
1360 #endif
1361
1362         /*
1363          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1364          * requests if Auto-CMD12 is enabled.
1365          */
1366         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1367                 if (mrq->stop) {
1368                         mrq->data->stop = NULL;
1369                         mrq->stop = NULL;
1370                 }
1371         }
1372
1373         host->mrq = mrq;
1374
1375         /*
1376          * Firstly check card presence from cd-gpio.  The return could
1377          * be one of the following possibilities:
1378          *     negative: cd-gpio is not available
1379          *     zero: cd-gpio is used, and card is removed
1380          *     one: cd-gpio is used, and card is present
1381          */
1382         present = mmc_gpio_get_cd(host->mmc);
1383         if (present < 0) {
1384                 /* If polling, assume that the card is always present. */
1385                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1386                         present = 1;
1387                 else
1388                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1389                                         SDHCI_CARD_PRESENT;
1390         }
1391
1392         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1393                 host->mrq->cmd->error = -ENOMEDIUM;
1394                 tasklet_schedule(&host->finish_tasklet);
1395         } else {
1396                 u32 present_state;
1397
1398                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1399                 /*
1400                  * Check if the re-tuning timer has already expired and there
1401                  * is no on-going data transfer and DAT0 is not busy. If so,
1402                  * we need to execute tuning procedure before sending command.
1403                  */
1404                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1405                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ)) &&
1406                     (present_state & SDHCI_DATA_0_LVL_MASK)) {
1407                         if (mmc->card) {
1408                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1409                                 tuning_opcode =
1410                                         mmc->card->type == MMC_TYPE_MMC ?
1411                                         MMC_SEND_TUNING_BLOCK_HS200 :
1412                                         MMC_SEND_TUNING_BLOCK;
1413
1414                                 /* Here we need to set the host->mrq to NULL,
1415                                  * in case the pending finish_tasklet
1416                                  * finishes it incorrectly.
1417                                  */
1418                                 host->mrq = NULL;
1419
1420                                 spin_unlock_irqrestore(&host->lock, flags);
1421                                 sdhci_execute_tuning(mmc, tuning_opcode);
1422                                 spin_lock_irqsave(&host->lock, flags);
1423
1424                                 /* Restore original mmc_request structure */
1425                                 host->mrq = mrq;
1426                         }
1427                 }
1428
1429                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1430                         sdhci_send_command(host, mrq->sbc);
1431                 else
1432                         sdhci_send_command(host, mrq->cmd);
1433         }
1434
1435         mmiowb();
1436         spin_unlock_irqrestore(&host->lock, flags);
1437 }
1438
1439 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1440 {
1441         u8 ctrl;
1442
1443         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1444         if (width == MMC_BUS_WIDTH_8) {
1445                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1446                 if (host->version >= SDHCI_SPEC_300)
1447                         ctrl |= SDHCI_CTRL_8BITBUS;
1448         } else {
1449                 if (host->version >= SDHCI_SPEC_300)
1450                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1451                 if (width == MMC_BUS_WIDTH_4)
1452                         ctrl |= SDHCI_CTRL_4BITBUS;
1453                 else
1454                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1455         }
1456         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1457 }
1458 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1459
1460 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1461 {
1462         u16 ctrl_2;
1463
1464         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1465         /* Select Bus Speed Mode for host */
1466         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1467         if ((timing == MMC_TIMING_MMC_HS200) ||
1468             (timing == MMC_TIMING_UHS_SDR104))
1469                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1470         else if (timing == MMC_TIMING_UHS_SDR12)
1471                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1472         else if (timing == MMC_TIMING_UHS_SDR25)
1473                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1474         else if (timing == MMC_TIMING_UHS_SDR50)
1475                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1476         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1477                  (timing == MMC_TIMING_MMC_DDR52))
1478                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1479         else if (timing == MMC_TIMING_MMC_HS400)
1480                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1481         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1482 }
1483 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1484
1485 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1486 {
1487         unsigned long flags;
1488         u8 ctrl;
1489         struct mmc_host *mmc = host->mmc;
1490
1491         spin_lock_irqsave(&host->lock, flags);
1492
1493         if (host->flags & SDHCI_DEVICE_DEAD) {
1494                 spin_unlock_irqrestore(&host->lock, flags);
1495                 if (!IS_ERR(mmc->supply.vmmc) &&
1496                     ios->power_mode == MMC_POWER_OFF)
1497                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1498                 return;
1499         }
1500
1501         /*
1502          * Reset the chip on each power off.
1503          * Should clear out any weird states.
1504          */
1505         if (ios->power_mode == MMC_POWER_OFF) {
1506                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1507                 sdhci_reinit(host);
1508         }
1509
1510         if (host->version >= SDHCI_SPEC_300 &&
1511                 (ios->power_mode == MMC_POWER_UP) &&
1512                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1513                 sdhci_enable_preset_value(host, false);
1514
1515         if (!ios->clock || ios->clock != host->clock) {
1516                 host->ops->set_clock(host, ios->clock);
1517                 host->clock = ios->clock;
1518
1519                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1520                     host->clock) {
1521                         host->timeout_clk = host->mmc->actual_clock ?
1522                                                 host->mmc->actual_clock / 1000 :
1523                                                 host->clock / 1000;
1524                         host->mmc->max_busy_timeout =
1525                                 host->ops->get_max_timeout_count ?
1526                                 host->ops->get_max_timeout_count(host) :
1527                                 1 << 27;
1528                         host->mmc->max_busy_timeout /= host->timeout_clk;
1529                 }
1530         }
1531
1532         sdhci_set_power(host, ios->power_mode, ios->vdd);
1533
1534         if (host->ops->platform_send_init_74_clocks)
1535                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1536
1537         host->ops->set_bus_width(host, ios->bus_width);
1538
1539         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1540
1541         if ((ios->timing == MMC_TIMING_SD_HS ||
1542              ios->timing == MMC_TIMING_MMC_HS)
1543             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1544                 ctrl |= SDHCI_CTRL_HISPD;
1545         else
1546                 ctrl &= ~SDHCI_CTRL_HISPD;
1547
1548         if (host->version >= SDHCI_SPEC_300) {
1549                 u16 clk, ctrl_2;
1550
1551                 /* In case of UHS-I modes, set High Speed Enable */
1552                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1553                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1554                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1555                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1556                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1557                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1558                     (ios->timing == MMC_TIMING_UHS_SDR25))
1559                         ctrl |= SDHCI_CTRL_HISPD;
1560
1561                 if (!host->preset_enabled) {
1562                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1563                         /*
1564                          * We only need to set Driver Strength if the
1565                          * preset value enable is not set.
1566                          */
1567                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1568                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1569                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1570                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1571                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1572                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1573
1574                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1575                 } else {
1576                         /*
1577                          * According to SDHC Spec v3.00, if the Preset Value
1578                          * Enable in the Host Control 2 register is set, we
1579                          * need to reset SD Clock Enable before changing High
1580                          * Speed Enable to avoid generating clock gliches.
1581                          */
1582
1583                         /* Reset SD Clock Enable */
1584                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1585                         clk &= ~SDHCI_CLOCK_CARD_EN;
1586                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1587
1588                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1589
1590                         /* Re-enable SD Clock */
1591                         host->ops->set_clock(host, host->clock);
1592                 }
1593
1594                 /* Reset SD Clock Enable */
1595                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1596                 clk &= ~SDHCI_CLOCK_CARD_EN;
1597                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1598
1599                 host->ops->set_uhs_signaling(host, ios->timing);
1600                 host->timing = ios->timing;
1601
1602                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1603                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1604                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1605                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1606                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1607                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1608                         u16 preset;
1609
1610                         sdhci_enable_preset_value(host, true);
1611                         preset = sdhci_get_preset_value(host);
1612                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1613                                 >> SDHCI_PRESET_DRV_SHIFT;
1614                 }
1615
1616                 /* Re-enable SD Clock */
1617                 host->ops->set_clock(host, host->clock);
1618         } else
1619                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1620
1621         /*
1622          * Some (ENE) controllers go apeshit on some ios operation,
1623          * signalling timeout and CRC errors even on CMD0. Resetting
1624          * it on each ios seems to solve the problem.
1625          */
1626         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1627                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1628
1629         mmiowb();
1630         spin_unlock_irqrestore(&host->lock, flags);
1631 }
1632
1633 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1634 {
1635         struct sdhci_host *host = mmc_priv(mmc);
1636
1637         sdhci_runtime_pm_get(host);
1638         sdhci_do_set_ios(host, ios);
1639         sdhci_runtime_pm_put(host);
1640 }
1641
1642 static int sdhci_do_get_cd(struct sdhci_host *host)
1643 {
1644         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1645
1646         if (host->flags & SDHCI_DEVICE_DEAD)
1647                 return 0;
1648
1649         /* If polling/nonremovable, assume that the card is always present. */
1650         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1651             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1652                 return 1;
1653
1654         /* Try slot gpio detect */
1655         if (!IS_ERR_VALUE(gpio_cd))
1656                 return !!gpio_cd;
1657
1658         /* Host native card detect */
1659         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1660 }
1661
1662 static int sdhci_get_cd(struct mmc_host *mmc)
1663 {
1664         struct sdhci_host *host = mmc_priv(mmc);
1665         int ret;
1666
1667         sdhci_runtime_pm_get(host);
1668         ret = sdhci_do_get_cd(host);
1669         sdhci_runtime_pm_put(host);
1670         return ret;
1671 }
1672
1673 static int sdhci_check_ro(struct sdhci_host *host)
1674 {
1675         unsigned long flags;
1676         int is_readonly;
1677
1678         spin_lock_irqsave(&host->lock, flags);
1679
1680         if (host->flags & SDHCI_DEVICE_DEAD)
1681                 is_readonly = 0;
1682         else if (host->ops->get_ro)
1683                 is_readonly = host->ops->get_ro(host);
1684         else
1685                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1686                                 & SDHCI_WRITE_PROTECT);
1687
1688         spin_unlock_irqrestore(&host->lock, flags);
1689
1690         /* This quirk needs to be replaced by a callback-function later */
1691         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1692                 !is_readonly : is_readonly;
1693 }
1694
1695 #define SAMPLE_COUNT    5
1696
1697 static int sdhci_do_get_ro(struct sdhci_host *host)
1698 {
1699         int i, ro_count;
1700
1701         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1702                 return sdhci_check_ro(host);
1703
1704         ro_count = 0;
1705         for (i = 0; i < SAMPLE_COUNT; i++) {
1706                 if (sdhci_check_ro(host)) {
1707                         if (++ro_count > SAMPLE_COUNT / 2)
1708                                 return 1;
1709                 }
1710                 msleep(30);
1711         }
1712         return 0;
1713 }
1714
1715 static void sdhci_hw_reset(struct mmc_host *mmc)
1716 {
1717         struct sdhci_host *host = mmc_priv(mmc);
1718
1719         if (host->ops && host->ops->hw_reset)
1720                 host->ops->hw_reset(host);
1721 }
1722
1723 static int sdhci_get_ro(struct mmc_host *mmc)
1724 {
1725         struct sdhci_host *host = mmc_priv(mmc);
1726         int ret;
1727
1728         sdhci_runtime_pm_get(host);
1729         ret = sdhci_do_get_ro(host);
1730         sdhci_runtime_pm_put(host);
1731         return ret;
1732 }
1733
1734 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1735 {
1736         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1737                 if (enable)
1738                         host->ier |= SDHCI_INT_CARD_INT;
1739                 else
1740                         host->ier &= ~SDHCI_INT_CARD_INT;
1741
1742                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1743                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1744                 mmiowb();
1745         }
1746 }
1747
1748 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1749 {
1750         struct sdhci_host *host = mmc_priv(mmc);
1751         unsigned long flags;
1752
1753         sdhci_runtime_pm_get(host);
1754
1755         spin_lock_irqsave(&host->lock, flags);
1756         if (enable)
1757                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1758         else
1759                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1760
1761         sdhci_enable_sdio_irq_nolock(host, enable);
1762         spin_unlock_irqrestore(&host->lock, flags);
1763
1764         sdhci_runtime_pm_put(host);
1765 }
1766
1767 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1768                                                 struct mmc_ios *ios)
1769 {
1770         struct mmc_host *mmc = host->mmc;
1771         u16 ctrl;
1772         int ret;
1773
1774         /*
1775          * Signal Voltage Switching is only applicable for Host Controllers
1776          * v3.00 and above.
1777          */
1778         if (host->version < SDHCI_SPEC_300)
1779                 return 0;
1780
1781         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1782
1783         switch (ios->signal_voltage) {
1784         case MMC_SIGNAL_VOLTAGE_330:
1785                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1786                 ctrl &= ~SDHCI_CTRL_VDD_180;
1787                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1788
1789                 if (!IS_ERR(mmc->supply.vqmmc)) {
1790                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1791                                                     3600000);
1792                         if (ret) {
1793                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1794                                         mmc_hostname(mmc));
1795                                 return -EIO;
1796                         }
1797                 }
1798                 /* Wait for 5ms */
1799                 usleep_range(5000, 5500);
1800
1801                 /* 3.3V regulator output should be stable within 5 ms */
1802                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1803                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1804                         return 0;
1805
1806                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1807                         mmc_hostname(mmc));
1808
1809                 return -EAGAIN;
1810         case MMC_SIGNAL_VOLTAGE_180:
1811                 if (!IS_ERR(mmc->supply.vqmmc)) {
1812                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1813                                         1700000, 1950000);
1814                         if (ret) {
1815                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1816                                         mmc_hostname(mmc));
1817                                 return -EIO;
1818                         }
1819                 }
1820
1821                 /*
1822                  * Enable 1.8V Signal Enable in the Host Control2
1823                  * register
1824                  */
1825                 ctrl |= SDHCI_CTRL_VDD_180;
1826                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1827
1828                 /* 1.8V regulator output should be stable within 5 ms */
1829                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1830                 if (ctrl & SDHCI_CTRL_VDD_180)
1831                         return 0;
1832
1833                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1834                         mmc_hostname(mmc));
1835
1836                 return -EAGAIN;
1837         case MMC_SIGNAL_VOLTAGE_120:
1838                 if (!IS_ERR(mmc->supply.vqmmc)) {
1839                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1840                                                     1300000);
1841                         if (ret) {
1842                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1843                                         mmc_hostname(mmc));
1844                                 return -EIO;
1845                         }
1846                 }
1847                 return 0;
1848         default:
1849                 /* No signal voltage switch required */
1850                 return 0;
1851         }
1852 }
1853
1854 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1855         struct mmc_ios *ios)
1856 {
1857         struct sdhci_host *host = mmc_priv(mmc);
1858         int err;
1859
1860         if (host->version < SDHCI_SPEC_300)
1861                 return 0;
1862         sdhci_runtime_pm_get(host);
1863         err = sdhci_do_start_signal_voltage_switch(host, ios);
1864         sdhci_runtime_pm_put(host);
1865         return err;
1866 }
1867
1868 static int sdhci_card_busy(struct mmc_host *mmc)
1869 {
1870         struct sdhci_host *host = mmc_priv(mmc);
1871         u32 present_state;
1872
1873         sdhci_runtime_pm_get(host);
1874         /* Check whether DAT[3:0] is 0000 */
1875         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1876         sdhci_runtime_pm_put(host);
1877
1878         return !(present_state & SDHCI_DATA_LVL_MASK);
1879 }
1880
1881 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1882 {
1883         struct sdhci_host *host = mmc_priv(mmc);
1884         u16 ctrl;
1885         int tuning_loop_counter = MAX_TUNING_LOOP;
1886         int err = 0;
1887         unsigned long flags;
1888
1889         sdhci_runtime_pm_get(host);
1890         spin_lock_irqsave(&host->lock, flags);
1891
1892         /*
1893          * The Host Controller needs tuning only in case of SDR104 mode
1894          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1895          * Capabilities register.
1896          * If the Host Controller supports the HS200 mode then the
1897          * tuning function has to be executed.
1898          */
1899         switch (host->timing) {
1900         case MMC_TIMING_MMC_HS400:
1901         case MMC_TIMING_MMC_HS200:
1902         case MMC_TIMING_UHS_SDR104:
1903                 break;
1904
1905         case MMC_TIMING_UHS_SDR50:
1906                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1907                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1908                         break;
1909                 /* FALLTHROUGH */
1910
1911         default:
1912                 spin_unlock_irqrestore(&host->lock, flags);
1913                 sdhci_runtime_pm_put(host);
1914                 return 0;
1915         }
1916
1917         if (host->ops->platform_execute_tuning) {
1918                 spin_unlock_irqrestore(&host->lock, flags);
1919                 err = host->ops->platform_execute_tuning(host, opcode);
1920                 sdhci_runtime_pm_put(host);
1921                 return err;
1922         }
1923
1924         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1925         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1926         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1927
1928         /*
1929          * As per the Host Controller spec v3.00, tuning command
1930          * generates Buffer Read Ready interrupt, so enable that.
1931          *
1932          * Note: The spec clearly says that when tuning sequence
1933          * is being performed, the controller does not generate
1934          * interrupts other than Buffer Read Ready interrupt. But
1935          * to make sure we don't hit a controller bug, we _only_
1936          * enable Buffer Read Ready interrupt here.
1937          */
1938         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1939         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1940
1941         /*
1942          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1943          * of loops reaches 40 times or a timeout of 150ms occurs.
1944          */
1945         do {
1946                 struct mmc_command cmd = {0};
1947                 struct mmc_request mrq = {NULL};
1948
1949                 cmd.opcode = opcode;
1950                 cmd.arg = 0;
1951                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1952                 cmd.retries = 0;
1953                 cmd.data = NULL;
1954                 cmd.error = 0;
1955
1956                 if (tuning_loop_counter-- == 0)
1957                         break;
1958
1959                 mrq.cmd = &cmd;
1960                 host->mrq = &mrq;
1961
1962                 /*
1963                  * In response to CMD19, the card sends 64 bytes of tuning
1964                  * block to the Host Controller. So we set the block size
1965                  * to 64 here.
1966                  */
1967                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1968                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1969                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1970                                              SDHCI_BLOCK_SIZE);
1971                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1972                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1973                                              SDHCI_BLOCK_SIZE);
1974                 } else {
1975                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1976                                      SDHCI_BLOCK_SIZE);
1977                 }
1978
1979                 /*
1980                  * The tuning block is sent by the card to the host controller.
1981                  * So we set the TRNS_READ bit in the Transfer Mode register.
1982                  * This also takes care of setting DMA Enable and Multi Block
1983                  * Select in the same register to 0.
1984                  */
1985                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1986
1987                 sdhci_send_command(host, &cmd);
1988
1989                 host->cmd = NULL;
1990                 host->mrq = NULL;
1991
1992                 spin_unlock_irqrestore(&host->lock, flags);
1993                 /* Wait for Buffer Read Ready interrupt */
1994                 wait_event_interruptible_timeout(host->buf_ready_int,
1995                                         (host->tuning_done == 1),
1996                                         msecs_to_jiffies(50));
1997                 spin_lock_irqsave(&host->lock, flags);
1998
1999                 if (!host->tuning_done) {
2000                         pr_info(DRIVER_NAME ": Timeout waiting for "
2001                                 "Buffer Read Ready interrupt during tuning "
2002                                 "procedure, falling back to fixed sampling "
2003                                 "clock\n");
2004                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2005                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2006                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2007                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2008
2009                         err = -EIO;
2010                         goto out;
2011                 }
2012
2013                 host->tuning_done = 0;
2014
2015                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2016
2017                 /* eMMC spec does not require a delay between tuning cycles */
2018                 if (opcode == MMC_SEND_TUNING_BLOCK)
2019                         mdelay(1);
2020         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2021
2022         /*
2023          * The Host Driver has exhausted the maximum number of loops allowed,
2024          * so use fixed sampling frequency.
2025          */
2026         if (tuning_loop_counter < 0) {
2027                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2028                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2029         }
2030         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2031                 pr_info(DRIVER_NAME ": Tuning procedure"
2032                         " failed, falling back to fixed sampling"
2033                         " clock\n");
2034                 err = -EIO;
2035         }
2036
2037 out:
2038         /*
2039          * If this is the very first time we are here, we start the retuning
2040          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2041          * flag won't be set, we check this condition before actually starting
2042          * the timer.
2043          */
2044         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2045             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2046                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2047                 mod_timer(&host->tuning_timer, jiffies +
2048                         host->tuning_count * HZ);
2049         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2050                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2051                 /* Reload the new initial value for timer */
2052                 mod_timer(&host->tuning_timer, jiffies +
2053                           host->tuning_count * HZ);
2054         }
2055
2056         /*
2057          * In case tuning fails, host controllers which support re-tuning can
2058          * try tuning again at a later time, when the re-tuning timer expires.
2059          * So for these controllers, we return 0. Since there might be other
2060          * controllers who do not have this capability, we return error for
2061          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2062          * a retuning timer to do the retuning for the card.
2063          */
2064         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2065                 err = 0;
2066
2067         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2068         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2069         spin_unlock_irqrestore(&host->lock, flags);
2070         sdhci_runtime_pm_put(host);
2071
2072         return err;
2073 }
2074
2075
2076 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2077 {
2078         /* Host Controller v3.00 defines preset value registers */
2079         if (host->version < SDHCI_SPEC_300)
2080                 return;
2081
2082         /*
2083          * We only enable or disable Preset Value if they are not already
2084          * enabled or disabled respectively. Otherwise, we bail out.
2085          */
2086         if (host->preset_enabled != enable) {
2087                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2088
2089                 if (enable)
2090                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2091                 else
2092                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2093
2094                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2095
2096                 if (enable)
2097                         host->flags |= SDHCI_PV_ENABLED;
2098                 else
2099                         host->flags &= ~SDHCI_PV_ENABLED;
2100
2101                 host->preset_enabled = enable;
2102         }
2103 }
2104
2105 static void sdhci_card_event(struct mmc_host *mmc)
2106 {
2107         struct sdhci_host *host = mmc_priv(mmc);
2108         unsigned long flags;
2109
2110         /* First check if client has provided their own card event */
2111         if (host->ops->card_event)
2112                 host->ops->card_event(host);
2113
2114         spin_lock_irqsave(&host->lock, flags);
2115
2116         /* Check host->mrq first in case we are runtime suspended */
2117         if (host->mrq && !sdhci_do_get_cd(host)) {
2118                 pr_err("%s: Card removed during transfer!\n",
2119                         mmc_hostname(host->mmc));
2120                 pr_err("%s: Resetting controller.\n",
2121                         mmc_hostname(host->mmc));
2122
2123                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2124                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2125
2126                 host->mrq->cmd->error = -ENOMEDIUM;
2127                 tasklet_schedule(&host->finish_tasklet);
2128         }
2129
2130         spin_unlock_irqrestore(&host->lock, flags);
2131 }
2132
2133 static const struct mmc_host_ops sdhci_ops = {
2134         .request        = sdhci_request,
2135         .set_ios        = sdhci_set_ios,
2136         .get_cd         = sdhci_get_cd,
2137         .get_ro         = sdhci_get_ro,
2138         .hw_reset       = sdhci_hw_reset,
2139         .enable_sdio_irq = sdhci_enable_sdio_irq,
2140         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2141         .execute_tuning                 = sdhci_execute_tuning,
2142         .card_event                     = sdhci_card_event,
2143         .card_busy      = sdhci_card_busy,
2144 };
2145
2146 /*****************************************************************************\
2147  *                                                                           *
2148  * Tasklets                                                                  *
2149  *                                                                           *
2150 \*****************************************************************************/
2151
2152 static void sdhci_tasklet_finish(unsigned long param)
2153 {
2154         struct sdhci_host *host;
2155         unsigned long flags;
2156         struct mmc_request *mrq;
2157
2158         host = (struct sdhci_host*)param;
2159
2160         spin_lock_irqsave(&host->lock, flags);
2161
2162         /*
2163          * If this tasklet gets rescheduled while running, it will
2164          * be run again afterwards but without any active request.
2165          */
2166         if (!host->mrq) {
2167                 spin_unlock_irqrestore(&host->lock, flags);
2168                 return;
2169         }
2170
2171         del_timer(&host->timer);
2172
2173         mrq = host->mrq;
2174
2175         /*
2176          * The controller needs a reset of internal state machines
2177          * upon error conditions.
2178          */
2179         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2180             ((mrq->cmd && mrq->cmd->error) ||
2181              (mrq->sbc && mrq->sbc->error) ||
2182              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2183                             (mrq->data->stop && mrq->data->stop->error))) ||
2184              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2185
2186                 /* Some controllers need this kick or reset won't work here */
2187                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2188                         /* This is to force an update */
2189                         host->ops->set_clock(host, host->clock);
2190
2191                 /* Spec says we should do both at the same time, but Ricoh
2192                    controllers do not like that. */
2193                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2194                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2195         }
2196
2197         host->mrq = NULL;
2198         host->cmd = NULL;
2199         host->data = NULL;
2200
2201 #ifndef SDHCI_USE_LEDS_CLASS
2202         sdhci_deactivate_led(host);
2203 #endif
2204
2205         mmiowb();
2206         spin_unlock_irqrestore(&host->lock, flags);
2207
2208         mmc_request_done(host->mmc, mrq);
2209         sdhci_runtime_pm_put(host);
2210 }
2211
2212 static void sdhci_timeout_timer(unsigned long data)
2213 {
2214         struct sdhci_host *host;
2215         unsigned long flags;
2216
2217         host = (struct sdhci_host*)data;
2218
2219         spin_lock_irqsave(&host->lock, flags);
2220
2221         if (host->mrq) {
2222                 pr_err("%s: Timeout waiting for hardware "
2223                         "interrupt.\n", mmc_hostname(host->mmc));
2224                 sdhci_dumpregs(host);
2225
2226                 if (host->data) {
2227                         host->data->error = -ETIMEDOUT;
2228                         sdhci_finish_data(host);
2229                 } else {
2230                         if (host->cmd)
2231                                 host->cmd->error = -ETIMEDOUT;
2232                         else
2233                                 host->mrq->cmd->error = -ETIMEDOUT;
2234
2235                         tasklet_schedule(&host->finish_tasklet);
2236                 }
2237         }
2238
2239         mmiowb();
2240         spin_unlock_irqrestore(&host->lock, flags);
2241 }
2242
2243 static void sdhci_tuning_timer(unsigned long data)
2244 {
2245         struct sdhci_host *host;
2246         unsigned long flags;
2247
2248         host = (struct sdhci_host *)data;
2249
2250         spin_lock_irqsave(&host->lock, flags);
2251
2252         host->flags |= SDHCI_NEEDS_RETUNING;
2253
2254         spin_unlock_irqrestore(&host->lock, flags);
2255 }
2256
2257 /*****************************************************************************\
2258  *                                                                           *
2259  * Interrupt handling                                                        *
2260  *                                                                           *
2261 \*****************************************************************************/
2262
2263 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2264 {
2265         BUG_ON(intmask == 0);
2266
2267         if (!host->cmd) {
2268                 pr_err("%s: Got command interrupt 0x%08x even "
2269                         "though no command operation was in progress.\n",
2270                         mmc_hostname(host->mmc), (unsigned)intmask);
2271                 sdhci_dumpregs(host);
2272                 return;
2273         }
2274
2275         if (intmask & SDHCI_INT_TIMEOUT)
2276                 host->cmd->error = -ETIMEDOUT;
2277         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2278                         SDHCI_INT_INDEX))
2279                 host->cmd->error = -EILSEQ;
2280
2281         if (host->cmd->error) {
2282                 tasklet_schedule(&host->finish_tasklet);
2283                 return;
2284         }
2285
2286         /*
2287          * The host can send and interrupt when the busy state has
2288          * ended, allowing us to wait without wasting CPU cycles.
2289          * Unfortunately this is overloaded on the "data complete"
2290          * interrupt, so we need to take some care when handling
2291          * it.
2292          *
2293          * Note: The 1.0 specification is a bit ambiguous about this
2294          *       feature so there might be some problems with older
2295          *       controllers.
2296          */
2297         if (host->cmd->flags & MMC_RSP_BUSY) {
2298                 if (host->cmd->data)
2299                         DBG("Cannot wait for busy signal when also "
2300                                 "doing a data transfer");
2301                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2302                                 && !host->busy_handle) {
2303                         /* Mark that command complete before busy is ended */
2304                         host->busy_handle = 1;
2305                         return;
2306                 }
2307
2308                 /* The controller does not support the end-of-busy IRQ,
2309                  * fall through and take the SDHCI_INT_RESPONSE */
2310         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2311                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2312                 *mask &= ~SDHCI_INT_DATA_END;
2313         }
2314
2315         if (intmask & SDHCI_INT_RESPONSE)
2316                 sdhci_finish_command(host);
2317 }
2318
2319 #ifdef CONFIG_MMC_DEBUG
2320 static void sdhci_adma_show_error(struct sdhci_host *host)
2321 {
2322         const char *name = mmc_hostname(host->mmc);
2323         void *desc = host->adma_table;
2324
2325         sdhci_dumpregs(host);
2326
2327         while (true) {
2328                 struct sdhci_adma2_64_desc *dma_desc = desc;
2329
2330                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2331                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2332                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2333                             le32_to_cpu(dma_desc->addr_lo),
2334                             le16_to_cpu(dma_desc->len),
2335                             le16_to_cpu(dma_desc->cmd));
2336                 else
2337                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2338                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2339                             le16_to_cpu(dma_desc->len),
2340                             le16_to_cpu(dma_desc->cmd));
2341
2342                 desc += host->desc_sz;
2343
2344                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2345                         break;
2346         }
2347 }
2348 #else
2349 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2350 #endif
2351
2352 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2353 {
2354         u32 command;
2355         BUG_ON(intmask == 0);
2356
2357         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2358         if (intmask & SDHCI_INT_DATA_AVAIL) {
2359                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2360                 if (command == MMC_SEND_TUNING_BLOCK ||
2361                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2362                         host->tuning_done = 1;
2363                         wake_up(&host->buf_ready_int);
2364                         return;
2365                 }
2366         }
2367
2368         if (!host->data) {
2369                 /*
2370                  * The "data complete" interrupt is also used to
2371                  * indicate that a busy state has ended. See comment
2372                  * above in sdhci_cmd_irq().
2373                  */
2374                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2375                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2376                                 host->cmd->error = -ETIMEDOUT;
2377                                 tasklet_schedule(&host->finish_tasklet);
2378                                 return;
2379                         }
2380                         if (intmask & SDHCI_INT_DATA_END) {
2381                                 /*
2382                                  * Some cards handle busy-end interrupt
2383                                  * before the command completed, so make
2384                                  * sure we do things in the proper order.
2385                                  */
2386                                 if (host->busy_handle)
2387                                         sdhci_finish_command(host);
2388                                 else
2389                                         host->busy_handle = 1;
2390                                 return;
2391                         }
2392                 }
2393
2394                 pr_err("%s: Got data interrupt 0x%08x even "
2395                         "though no data operation was in progress.\n",
2396                         mmc_hostname(host->mmc), (unsigned)intmask);
2397                 sdhci_dumpregs(host);
2398
2399                 return;
2400         }
2401
2402         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2403                 host->data->error = -ETIMEDOUT;
2404         else if (intmask & SDHCI_INT_DATA_END_BIT)
2405                 host->data->error = -EILSEQ;
2406         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2407                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2408                         != MMC_BUS_TEST_R)
2409                 host->data->error = -EILSEQ;
2410         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2411                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2412                 sdhci_adma_show_error(host);
2413                 host->data->error = -EIO;
2414                 if (host->ops->adma_workaround)
2415                         host->ops->adma_workaround(host, intmask);
2416         }
2417
2418         if (host->data->error)
2419                 sdhci_finish_data(host);
2420         else {
2421                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2422                         sdhci_transfer_pio(host);
2423
2424                 /*
2425                  * We currently don't do anything fancy with DMA
2426                  * boundaries, but as we can't disable the feature
2427                  * we need to at least restart the transfer.
2428                  *
2429                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2430                  * should return a valid address to continue from, but as
2431                  * some controllers are faulty, don't trust them.
2432                  */
2433                 if (intmask & SDHCI_INT_DMA_END) {
2434                         u32 dmastart, dmanow;
2435                         dmastart = sg_dma_address(host->data->sg);
2436                         dmanow = dmastart + host->data->bytes_xfered;
2437                         /*
2438                          * Force update to the next DMA block boundary.
2439                          */
2440                         dmanow = (dmanow &
2441                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2442                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2443                         host->data->bytes_xfered = dmanow - dmastart;
2444                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2445                                 " next 0x%08x\n",
2446                                 mmc_hostname(host->mmc), dmastart,
2447                                 host->data->bytes_xfered, dmanow);
2448                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2449                 }
2450
2451                 if (intmask & SDHCI_INT_DATA_END) {
2452                         if (host->cmd) {
2453                                 /*
2454                                  * Data managed to finish before the
2455                                  * command completed. Make sure we do
2456                                  * things in the proper order.
2457                                  */
2458                                 host->data_early = 1;
2459                         } else {
2460                                 sdhci_finish_data(host);
2461                         }
2462                 }
2463         }
2464 }
2465
2466 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2467 {
2468         irqreturn_t result = IRQ_NONE;
2469         struct sdhci_host *host = dev_id;
2470         u32 intmask, mask, unexpected = 0;
2471         int max_loops = 16;
2472
2473         spin_lock(&host->lock);
2474
2475         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2476                 spin_unlock(&host->lock);
2477                 return IRQ_NONE;
2478         }
2479
2480         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2481         if (!intmask || intmask == 0xffffffff) {
2482                 result = IRQ_NONE;
2483                 goto out;
2484         }
2485
2486         do {
2487                 /* Clear selected interrupts. */
2488                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2489                                   SDHCI_INT_BUS_POWER);
2490                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2491
2492                 DBG("*** %s got interrupt: 0x%08x\n",
2493                         mmc_hostname(host->mmc), intmask);
2494
2495                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2496                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2497                                       SDHCI_CARD_PRESENT;
2498
2499                         /*
2500                          * There is a observation on i.mx esdhc.  INSERT
2501                          * bit will be immediately set again when it gets
2502                          * cleared, if a card is inserted.  We have to mask
2503                          * the irq to prevent interrupt storm which will
2504                          * freeze the system.  And the REMOVE gets the
2505                          * same situation.
2506                          *
2507                          * More testing are needed here to ensure it works
2508                          * for other platforms though.
2509                          */
2510                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2511                                        SDHCI_INT_CARD_REMOVE);
2512                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2513                                                SDHCI_INT_CARD_INSERT;
2514                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2515                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2516
2517                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2518                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2519
2520                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2521                                                        SDHCI_INT_CARD_REMOVE);
2522                         result = IRQ_WAKE_THREAD;
2523                 }
2524
2525                 if (intmask & SDHCI_INT_CMD_MASK)
2526                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2527                                       &intmask);
2528
2529                 if (intmask & SDHCI_INT_DATA_MASK)
2530                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2531
2532                 if (intmask & SDHCI_INT_BUS_POWER)
2533                         pr_err("%s: Card is consuming too much power!\n",
2534                                 mmc_hostname(host->mmc));
2535
2536                 if (intmask & SDHCI_INT_CARD_INT) {
2537                         sdhci_enable_sdio_irq_nolock(host, false);
2538                         host->thread_isr |= SDHCI_INT_CARD_INT;
2539                         result = IRQ_WAKE_THREAD;
2540                 }
2541
2542                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2543                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2544                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2545                              SDHCI_INT_CARD_INT);
2546
2547                 if (intmask) {
2548                         unexpected |= intmask;
2549                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2550                 }
2551
2552                 if (result == IRQ_NONE)
2553                         result = IRQ_HANDLED;
2554
2555                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2556         } while (intmask && --max_loops);
2557 out:
2558         spin_unlock(&host->lock);
2559
2560         if (unexpected) {
2561                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2562                            mmc_hostname(host->mmc), unexpected);
2563                 sdhci_dumpregs(host);
2564         }
2565
2566         return result;
2567 }
2568
2569 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2570 {
2571         struct sdhci_host *host = dev_id;
2572         unsigned long flags;
2573         u32 isr;
2574
2575         spin_lock_irqsave(&host->lock, flags);
2576         isr = host->thread_isr;
2577         host->thread_isr = 0;
2578         spin_unlock_irqrestore(&host->lock, flags);
2579
2580         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2581                 sdhci_card_event(host->mmc);
2582                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2583         }
2584
2585         if (isr & SDHCI_INT_CARD_INT) {
2586                 sdio_run_irqs(host->mmc);
2587
2588                 spin_lock_irqsave(&host->lock, flags);
2589                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2590                         sdhci_enable_sdio_irq_nolock(host, true);
2591                 spin_unlock_irqrestore(&host->lock, flags);
2592         }
2593
2594         return isr ? IRQ_HANDLED : IRQ_NONE;
2595 }
2596
2597 /*****************************************************************************\
2598  *                                                                           *
2599  * Suspend/resume                                                            *
2600  *                                                                           *
2601 \*****************************************************************************/
2602
2603 #ifdef CONFIG_PM
2604 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2605 {
2606         u8 val;
2607         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2608                         | SDHCI_WAKE_ON_INT;
2609
2610         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2611         val |= mask ;
2612         /* Avoid fake wake up */
2613         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2614                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2615         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2616 }
2617 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2618
2619 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2620 {
2621         u8 val;
2622         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2623                         | SDHCI_WAKE_ON_INT;
2624
2625         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2626         val &= ~mask;
2627         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2628 }
2629
2630 int sdhci_suspend_host(struct sdhci_host *host)
2631 {
2632         sdhci_disable_card_detection(host);
2633
2634         /* Disable tuning since we are suspending */
2635         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2636                 del_timer_sync(&host->tuning_timer);
2637                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2638         }
2639
2640         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2641                 host->ier = 0;
2642                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2643                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2644                 free_irq(host->irq, host);
2645         } else {
2646                 sdhci_enable_irq_wakeups(host);
2647                 enable_irq_wake(host->irq);
2648         }
2649         return 0;
2650 }
2651
2652 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2653
2654 int sdhci_resume_host(struct sdhci_host *host)
2655 {
2656         int ret = 0;
2657
2658         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2659                 if (host->ops->enable_dma)
2660                         host->ops->enable_dma(host);
2661         }
2662
2663         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2664                 ret = request_threaded_irq(host->irq, sdhci_irq,
2665                                            sdhci_thread_irq, IRQF_SHARED,
2666                                            mmc_hostname(host->mmc), host);
2667                 if (ret)
2668                         return ret;
2669         } else {
2670                 sdhci_disable_irq_wakeups(host);
2671                 disable_irq_wake(host->irq);
2672         }
2673
2674         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2675             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2676                 /* Card keeps power but host controller does not */
2677                 sdhci_init(host, 0);
2678                 host->pwr = 0;
2679                 host->clock = 0;
2680                 sdhci_do_set_ios(host, &host->mmc->ios);
2681         } else {
2682                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2683                 mmiowb();
2684         }
2685
2686         sdhci_enable_card_detection(host);
2687
2688         /* Set the re-tuning expiration flag */
2689         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2690                 host->flags |= SDHCI_NEEDS_RETUNING;
2691
2692         return ret;
2693 }
2694
2695 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2696
2697 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2698 {
2699         return pm_runtime_get_sync(host->mmc->parent);
2700 }
2701
2702 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2703 {
2704         pm_runtime_mark_last_busy(host->mmc->parent);
2705         return pm_runtime_put_autosuspend(host->mmc->parent);
2706 }
2707
2708 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2709 {
2710         if (host->runtime_suspended || host->bus_on)
2711                 return;
2712         host->bus_on = true;
2713         pm_runtime_get_noresume(host->mmc->parent);
2714 }
2715
2716 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2717 {
2718         if (host->runtime_suspended || !host->bus_on)
2719                 return;
2720         host->bus_on = false;
2721         pm_runtime_put_noidle(host->mmc->parent);
2722 }
2723
2724 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2725 {
2726         unsigned long flags;
2727
2728         /* Disable tuning since we are suspending */
2729         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2730                 del_timer_sync(&host->tuning_timer);
2731                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2732         }
2733
2734         spin_lock_irqsave(&host->lock, flags);
2735         host->ier &= SDHCI_INT_CARD_INT;
2736         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2737         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2738         spin_unlock_irqrestore(&host->lock, flags);
2739
2740         synchronize_hardirq(host->irq);
2741
2742         spin_lock_irqsave(&host->lock, flags);
2743         host->runtime_suspended = true;
2744         spin_unlock_irqrestore(&host->lock, flags);
2745
2746         return 0;
2747 }
2748 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2749
2750 int sdhci_runtime_resume_host(struct sdhci_host *host)
2751 {
2752         unsigned long flags;
2753         int host_flags = host->flags;
2754
2755         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2756                 if (host->ops->enable_dma)
2757                         host->ops->enable_dma(host);
2758         }
2759
2760         sdhci_init(host, 0);
2761
2762         /* Force clock and power re-program */
2763         host->pwr = 0;
2764         host->clock = 0;
2765         sdhci_do_set_ios(host, &host->mmc->ios);
2766
2767         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2768         if ((host_flags & SDHCI_PV_ENABLED) &&
2769                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2770                 spin_lock_irqsave(&host->lock, flags);
2771                 sdhci_enable_preset_value(host, true);
2772                 spin_unlock_irqrestore(&host->lock, flags);
2773         }
2774
2775         /* Set the re-tuning expiration flag */
2776         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2777                 host->flags |= SDHCI_NEEDS_RETUNING;
2778
2779         spin_lock_irqsave(&host->lock, flags);
2780
2781         host->runtime_suspended = false;
2782
2783         /* Enable SDIO IRQ */
2784         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2785                 sdhci_enable_sdio_irq_nolock(host, true);
2786
2787         /* Enable Card Detection */
2788         sdhci_enable_card_detection(host);
2789
2790         spin_unlock_irqrestore(&host->lock, flags);
2791
2792         return 0;
2793 }
2794 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2795
2796 #endif /* CONFIG_PM */
2797
2798 /*****************************************************************************\
2799  *                                                                           *
2800  * Device allocation/registration                                            *
2801  *                                                                           *
2802 \*****************************************************************************/
2803
2804 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2805         size_t priv_size)
2806 {
2807         struct mmc_host *mmc;
2808         struct sdhci_host *host;
2809
2810         WARN_ON(dev == NULL);
2811
2812         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2813         if (!mmc)
2814                 return ERR_PTR(-ENOMEM);
2815
2816         host = mmc_priv(mmc);
2817         host->mmc = mmc;
2818
2819         return host;
2820 }
2821
2822 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2823
2824 int sdhci_add_host(struct sdhci_host *host)
2825 {
2826         struct mmc_host *mmc;
2827         u32 caps[2] = {0, 0};
2828         u32 max_current_caps;
2829         unsigned int ocr_avail;
2830         unsigned int override_timeout_clk;
2831         int ret;
2832
2833         WARN_ON(host == NULL);
2834         if (host == NULL)
2835                 return -EINVAL;
2836
2837         mmc = host->mmc;
2838
2839         if (debug_quirks)
2840                 host->quirks = debug_quirks;
2841         if (debug_quirks2)
2842                 host->quirks2 = debug_quirks2;
2843
2844         override_timeout_clk = host->timeout_clk;
2845
2846         sdhci_do_reset(host, SDHCI_RESET_ALL);
2847
2848         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2849         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2850                                 >> SDHCI_SPEC_VER_SHIFT;
2851         if (host->version > SDHCI_SPEC_300) {
2852                 pr_err("%s: Unknown controller version (%d). "
2853                         "You may experience problems.\n", mmc_hostname(mmc),
2854                         host->version);
2855         }
2856
2857         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2858                 sdhci_readl(host, SDHCI_CAPABILITIES);
2859
2860         if (host->version >= SDHCI_SPEC_300)
2861                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2862                         host->caps1 :
2863                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2864
2865         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2866                 host->flags |= SDHCI_USE_SDMA;
2867         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2868                 DBG("Controller doesn't have SDMA capability\n");
2869         else
2870                 host->flags |= SDHCI_USE_SDMA;
2871
2872         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2873                 (host->flags & SDHCI_USE_SDMA)) {
2874                 DBG("Disabling DMA as it is marked broken\n");
2875                 host->flags &= ~SDHCI_USE_SDMA;
2876         }
2877
2878         if ((host->version >= SDHCI_SPEC_200) &&
2879                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2880                 host->flags |= SDHCI_USE_ADMA;
2881
2882         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2883                 (host->flags & SDHCI_USE_ADMA)) {
2884                 DBG("Disabling ADMA as it is marked broken\n");
2885                 host->flags &= ~SDHCI_USE_ADMA;
2886         }
2887
2888         /*
2889          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2890          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2891          * that during the first call to ->enable_dma().  Similarly
2892          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2893          * implement.
2894          */
2895         if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2896                 host->flags |= SDHCI_USE_64_BIT_DMA;
2897
2898         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2899                 if (host->ops->enable_dma) {
2900                         if (host->ops->enable_dma(host)) {
2901                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2902                                         mmc_hostname(mmc));
2903                                 host->flags &=
2904                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2905                         }
2906                 }
2907         }
2908
2909         /* SDMA does not support 64-bit DMA */
2910         if (host->flags & SDHCI_USE_64_BIT_DMA)
2911                 host->flags &= ~SDHCI_USE_SDMA;
2912
2913         if (host->flags & SDHCI_USE_ADMA) {
2914                 /*
2915                  * The DMA descriptor table size is calculated as the maximum
2916                  * number of segments times 2, to allow for an alignment
2917                  * descriptor for each segment, plus 1 for a nop end descriptor,
2918                  * all multipled by the descriptor size.
2919                  */
2920                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2921                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2922                                               SDHCI_ADMA2_64_DESC_SZ;
2923                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2924                                                 SDHCI_ADMA2_64_ALIGN;
2925                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2926                         host->align_sz = SDHCI_ADMA2_64_ALIGN;
2927                         host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2928                 } else {
2929                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2930                                               SDHCI_ADMA2_32_DESC_SZ;
2931                         host->align_buffer_sz = SDHCI_MAX_SEGS *
2932                                                 SDHCI_ADMA2_32_ALIGN;
2933                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2934                         host->align_sz = SDHCI_ADMA2_32_ALIGN;
2935                         host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2936                 }
2937                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2938                                                       host->adma_table_sz,
2939                                                       &host->adma_addr,
2940                                                       GFP_KERNEL);
2941                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2942                 if (!host->adma_table || !host->align_buffer) {
2943                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2944                                           host->adma_table, host->adma_addr);
2945                         kfree(host->align_buffer);
2946                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2947                                 mmc_hostname(mmc));
2948                         host->flags &= ~SDHCI_USE_ADMA;
2949                         host->adma_table = NULL;
2950                         host->align_buffer = NULL;
2951                 } else if (host->adma_addr & host->align_mask) {
2952                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2953                                 mmc_hostname(mmc));
2954                         host->flags &= ~SDHCI_USE_ADMA;
2955                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2956                                           host->adma_table, host->adma_addr);
2957                         kfree(host->align_buffer);
2958                         host->adma_table = NULL;
2959                         host->align_buffer = NULL;
2960                 }
2961         }
2962
2963         /*
2964          * If we use DMA, then it's up to the caller to set the DMA
2965          * mask, but PIO does not need the hw shim so we set a new
2966          * mask here in that case.
2967          */
2968         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2969                 host->dma_mask = DMA_BIT_MASK(64);
2970                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2971         }
2972
2973         if (host->version >= SDHCI_SPEC_300)
2974                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2975                         >> SDHCI_CLOCK_BASE_SHIFT;
2976         else
2977                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2978                         >> SDHCI_CLOCK_BASE_SHIFT;
2979
2980         host->max_clk *= 1000000;
2981         if (host->max_clk == 0 || host->quirks &
2982                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2983                 if (!host->ops->get_max_clock) {
2984                         pr_err("%s: Hardware doesn't specify base clock "
2985                                "frequency.\n", mmc_hostname(mmc));
2986                         return -ENODEV;
2987                 }
2988                 host->max_clk = host->ops->get_max_clock(host);
2989         }
2990
2991         /*
2992          * In case of Host Controller v3.00, find out whether clock
2993          * multiplier is supported.
2994          */
2995         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2996                         SDHCI_CLOCK_MUL_SHIFT;
2997
2998         /*
2999          * In case the value in Clock Multiplier is 0, then programmable
3000          * clock mode is not supported, otherwise the actual clock
3001          * multiplier is one more than the value of Clock Multiplier
3002          * in the Capabilities Register.
3003          */
3004         if (host->clk_mul)
3005                 host->clk_mul += 1;
3006
3007         /*
3008          * Set host parameters.
3009          */
3010         mmc->ops = &sdhci_ops;
3011         mmc->f_max = host->max_clk;
3012         if (host->ops->get_min_clock)
3013                 mmc->f_min = host->ops->get_min_clock(host);
3014         else if (host->version >= SDHCI_SPEC_300) {
3015                 if (host->clk_mul) {
3016                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3017                         mmc->f_max = host->max_clk * host->clk_mul;
3018                 } else
3019                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3020         } else
3021                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3022
3023         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3024                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3025                                         SDHCI_TIMEOUT_CLK_SHIFT;
3026                 if (host->timeout_clk == 0) {
3027                         if (host->ops->get_timeout_clock) {
3028                                 host->timeout_clk =
3029                                         host->ops->get_timeout_clock(host);
3030                         } else {
3031                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3032                                         mmc_hostname(mmc));
3033                                 return -ENODEV;
3034                         }
3035                 }
3036
3037                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3038                         host->timeout_clk *= 1000;
3039
3040                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3041                         host->ops->get_max_timeout_count(host) : 1 << 27;
3042                 mmc->max_busy_timeout /= host->timeout_clk;
3043         }
3044
3045         if (override_timeout_clk)
3046                 host->timeout_clk = override_timeout_clk;
3047
3048         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3049         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3050
3051         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3052                 host->flags |= SDHCI_AUTO_CMD12;
3053
3054         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3055         if ((host->version >= SDHCI_SPEC_300) &&
3056             ((host->flags & SDHCI_USE_ADMA) ||
3057              !(host->flags & SDHCI_USE_SDMA))) {
3058                 host->flags |= SDHCI_AUTO_CMD23;
3059                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3060         } else {
3061                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3062         }
3063
3064         /*
3065          * A controller may support 8-bit width, but the board itself
3066          * might not have the pins brought out.  Boards that support
3067          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3068          * their platform code before calling sdhci_add_host(), and we
3069          * won't assume 8-bit width for hosts without that CAP.
3070          */
3071         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3072                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3073
3074         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3075                 mmc->caps &= ~MMC_CAP_CMD23;
3076
3077         if (caps[0] & SDHCI_CAN_DO_HISPD)
3078                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3079
3080         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3081             !(mmc->caps & MMC_CAP_NONREMOVABLE))
3082                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3083
3084         /* If there are external regulators, get them */
3085         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3086                 return -EPROBE_DEFER;
3087
3088         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3089         if (!IS_ERR(mmc->supply.vqmmc)) {
3090                 ret = regulator_enable(mmc->supply.vqmmc);
3091                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3092                                                     1950000))
3093                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3094                                         SDHCI_SUPPORT_SDR50 |
3095                                         SDHCI_SUPPORT_DDR50);
3096                 if (ret) {
3097                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3098                                 mmc_hostname(mmc), ret);
3099                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3100                 }
3101         }
3102
3103         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3104                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3105                        SDHCI_SUPPORT_DDR50);
3106
3107         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3108         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3109                        SDHCI_SUPPORT_DDR50))
3110                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3111
3112         /* SDR104 supports also implies SDR50 support */
3113         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3114                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3115                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3116                  * field can be promoted to support HS200.
3117                  */
3118                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3119                         mmc->caps2 |= MMC_CAP2_HS200;
3120         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3121                 mmc->caps |= MMC_CAP_UHS_SDR50;
3122
3123         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3124             (caps[1] & SDHCI_SUPPORT_HS400))
3125                 mmc->caps2 |= MMC_CAP2_HS400;
3126
3127         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3128             (IS_ERR(mmc->supply.vqmmc) ||
3129              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3130                                              1300000)))
3131                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3132
3133         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3134                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3135                 mmc->caps |= MMC_CAP_UHS_DDR50;
3136
3137         /* Does the host need tuning for SDR50? */
3138         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3139                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3140
3141         /* Does the host need tuning for SDR104 / HS200? */
3142         if (mmc->caps2 & MMC_CAP2_HS200)
3143                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3144
3145         /* Driver Type(s) (A, C, D) supported by the host */
3146         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3147                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3148         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3149                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3150         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3151                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3152
3153         /* Initial value for re-tuning timer count */
3154         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3155                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3156
3157         /*
3158          * In case Re-tuning Timer is not disabled, the actual value of
3159          * re-tuning timer will be 2 ^ (n - 1).
3160          */
3161         if (host->tuning_count)
3162                 host->tuning_count = 1 << (host->tuning_count - 1);
3163
3164         /* Re-tuning mode supported by the Host Controller */
3165         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3166                              SDHCI_RETUNING_MODE_SHIFT;
3167
3168         ocr_avail = 0;
3169
3170         /*
3171          * According to SD Host Controller spec v3.00, if the Host System
3172          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3173          * the value is meaningful only if Voltage Support in the Capabilities
3174          * register is set. The actual current value is 4 times the register
3175          * value.
3176          */
3177         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3178         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3179                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3180                 if (curr > 0) {
3181
3182                         /* convert to SDHCI_MAX_CURRENT format */
3183                         curr = curr/1000;  /* convert to mA */
3184                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3185
3186                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3187                         max_current_caps =
3188                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3189                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3190                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3191                 }
3192         }
3193
3194         if (caps[0] & SDHCI_CAN_VDD_330) {
3195                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3196
3197                 mmc->max_current_330 = ((max_current_caps &
3198                                    SDHCI_MAX_CURRENT_330_MASK) >>
3199                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3200                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3201         }
3202         if (caps[0] & SDHCI_CAN_VDD_300) {
3203                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3204
3205                 mmc->max_current_300 = ((max_current_caps &
3206                                    SDHCI_MAX_CURRENT_300_MASK) >>
3207                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3208                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3209         }
3210         if (caps[0] & SDHCI_CAN_VDD_180) {
3211                 ocr_avail |= MMC_VDD_165_195;
3212
3213                 mmc->max_current_180 = ((max_current_caps &
3214                                    SDHCI_MAX_CURRENT_180_MASK) >>
3215                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3216                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3217         }
3218
3219         /* If OCR set by external regulators, use it instead */
3220         if (mmc->ocr_avail)
3221                 ocr_avail = mmc->ocr_avail;
3222
3223         if (host->ocr_mask)
3224                 ocr_avail &= host->ocr_mask;
3225
3226         mmc->ocr_avail = ocr_avail;
3227         mmc->ocr_avail_sdio = ocr_avail;
3228         if (host->ocr_avail_sdio)
3229                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3230         mmc->ocr_avail_sd = ocr_avail;
3231         if (host->ocr_avail_sd)
3232                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3233         else /* normal SD controllers don't support 1.8V */
3234                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3235         mmc->ocr_avail_mmc = ocr_avail;
3236         if (host->ocr_avail_mmc)
3237                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3238
3239         if (mmc->ocr_avail == 0) {
3240                 pr_err("%s: Hardware doesn't report any "
3241                         "support voltages.\n", mmc_hostname(mmc));
3242                 return -ENODEV;
3243         }
3244
3245         spin_lock_init(&host->lock);
3246
3247         /*
3248          * Maximum number of segments. Depends on if the hardware
3249          * can do scatter/gather or not.
3250          */
3251         if (host->flags & SDHCI_USE_ADMA)
3252                 mmc->max_segs = SDHCI_MAX_SEGS;
3253         else if (host->flags & SDHCI_USE_SDMA)
3254                 mmc->max_segs = 1;
3255         else /* PIO */
3256                 mmc->max_segs = SDHCI_MAX_SEGS;
3257
3258         /*
3259          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3260          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3261          * is less anyway.
3262          */
3263         mmc->max_req_size = 524288;
3264
3265         /*
3266          * Maximum segment size. Could be one segment with the maximum number
3267          * of bytes. When doing hardware scatter/gather, each entry cannot
3268          * be larger than 64 KiB though.
3269          */
3270         if (host->flags & SDHCI_USE_ADMA) {
3271                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3272                         mmc->max_seg_size = 65535;
3273                 else
3274                         mmc->max_seg_size = 65536;
3275         } else {
3276                 mmc->max_seg_size = mmc->max_req_size;
3277         }
3278
3279         /*
3280          * Maximum block size. This varies from controller to controller and
3281          * is specified in the capabilities register.
3282          */
3283         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3284                 mmc->max_blk_size = 2;
3285         } else {
3286                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3287                                 SDHCI_MAX_BLOCK_SHIFT;
3288                 if (mmc->max_blk_size >= 3) {
3289                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3290                                 mmc_hostname(mmc));
3291                         mmc->max_blk_size = 0;
3292                 }
3293         }
3294
3295         mmc->max_blk_size = 512 << mmc->max_blk_size;
3296
3297         /*
3298          * Maximum block count.
3299          */
3300         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3301
3302         /*
3303          * Init tasklets.
3304          */
3305         tasklet_init(&host->finish_tasklet,
3306                 sdhci_tasklet_finish, (unsigned long)host);
3307
3308         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3309
3310         if (host->version >= SDHCI_SPEC_300) {
3311                 init_waitqueue_head(&host->buf_ready_int);
3312
3313                 /* Initialize re-tuning timer */
3314                 init_timer(&host->tuning_timer);
3315                 host->tuning_timer.data = (unsigned long)host;
3316                 host->tuning_timer.function = sdhci_tuning_timer;
3317         }
3318
3319         sdhci_init(host, 0);
3320
3321         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3322                                    IRQF_SHARED, mmc_hostname(mmc), host);
3323         if (ret) {
3324                 pr_err("%s: Failed to request IRQ %d: %d\n",
3325                        mmc_hostname(mmc), host->irq, ret);
3326                 goto untasklet;
3327         }
3328
3329 #ifdef CONFIG_MMC_DEBUG
3330         sdhci_dumpregs(host);
3331 #endif
3332
3333 #ifdef SDHCI_USE_LEDS_CLASS
3334         snprintf(host->led_name, sizeof(host->led_name),
3335                 "%s::", mmc_hostname(mmc));
3336         host->led.name = host->led_name;
3337         host->led.brightness = LED_OFF;
3338         host->led.default_trigger = mmc_hostname(mmc);
3339         host->led.brightness_set = sdhci_led_control;
3340
3341         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3342         if (ret) {
3343                 pr_err("%s: Failed to register LED device: %d\n",
3344                        mmc_hostname(mmc), ret);
3345                 goto reset;
3346         }
3347 #endif
3348
3349         mmiowb();
3350
3351         mmc_add_host(mmc);
3352
3353         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3354                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3355                 (host->flags & SDHCI_USE_ADMA) ?
3356                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3357                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3358
3359         sdhci_enable_card_detection(host);
3360
3361         return 0;
3362
3363 #ifdef SDHCI_USE_LEDS_CLASS
3364 reset:
3365         sdhci_do_reset(host, SDHCI_RESET_ALL);
3366         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3367         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3368         free_irq(host->irq, host);
3369 #endif
3370 untasklet:
3371         tasklet_kill(&host->finish_tasklet);
3372
3373         return ret;
3374 }
3375
3376 EXPORT_SYMBOL_GPL(sdhci_add_host);
3377
3378 void sdhci_remove_host(struct sdhci_host *host, int dead)
3379 {
3380         struct mmc_host *mmc = host->mmc;
3381         unsigned long flags;
3382
3383         if (dead) {
3384                 spin_lock_irqsave(&host->lock, flags);
3385
3386                 host->flags |= SDHCI_DEVICE_DEAD;
3387
3388                 if (host->mrq) {
3389                         pr_err("%s: Controller removed during "
3390                                 " transfer!\n", mmc_hostname(mmc));
3391
3392                         host->mrq->cmd->error = -ENOMEDIUM;
3393                         tasklet_schedule(&host->finish_tasklet);
3394                 }
3395
3396                 spin_unlock_irqrestore(&host->lock, flags);
3397         }
3398
3399         sdhci_disable_card_detection(host);
3400
3401         mmc_remove_host(mmc);
3402
3403 #ifdef SDHCI_USE_LEDS_CLASS
3404         led_classdev_unregister(&host->led);
3405 #endif
3406
3407         if (!dead)
3408                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3409
3410         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3411         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3412         free_irq(host->irq, host);
3413
3414         del_timer_sync(&host->timer);
3415
3416         tasklet_kill(&host->finish_tasklet);
3417
3418         if (!IS_ERR(mmc->supply.vqmmc))
3419                 regulator_disable(mmc->supply.vqmmc);
3420
3421         if (host->adma_table)
3422                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3423                                   host->adma_table, host->adma_addr);
3424         kfree(host->align_buffer);
3425
3426         host->adma_table = NULL;
3427         host->align_buffer = NULL;
3428 }
3429
3430 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3431
3432 void sdhci_free_host(struct sdhci_host *host)
3433 {
3434         mmc_free_host(host->mmc);
3435 }
3436
3437 EXPORT_SYMBOL_GPL(sdhci_free_host);
3438
3439 /*****************************************************************************\
3440  *                                                                           *
3441  * Driver init/exit                                                          *
3442  *                                                                           *
3443 \*****************************************************************************/
3444
3445 static int __init sdhci_drv_init(void)
3446 {
3447         pr_info(DRIVER_NAME
3448                 ": Secure Digital Host Controller Interface driver\n");
3449         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3450
3451         return 0;
3452 }
3453
3454 static void __exit sdhci_drv_exit(void)
3455 {
3456 }
3457
3458 module_init(sdhci_drv_init);
3459 module_exit(sdhci_drv_exit);
3460
3461 module_param(debug_quirks, uint, 0444);
3462 module_param(debug_quirks2, uint, 0444);
3463
3464 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3465 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3466 MODULE_LICENSE("GPL");
3467
3468 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3469 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");