drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/firmware.h>
  25 #include <linux/videodev2.h>
  26 #include <media/v4l2-common.h>
  27 #include "pvrusb2.h"
  28 #include "pvrusb2-std.h"
  29 #include "pvrusb2-util.h"
  30 #include "pvrusb2-hdw.h"
  31 #include "pvrusb2-i2c-core.h"
  32 #include "pvrusb2-tuner.h"
  33 #include "pvrusb2-eeprom.h"
  34 #include "pvrusb2-hdw-internal.h"
  35 #include "pvrusb2-encoder.h"
  36 #include "pvrusb2-debug.h"
  37 #include "pvrusb2-fx2-cmd.h"
  38
  39 #define TV_MIN_FREQ     55250000L
  40 #define TV_MAX_FREQ    850000000L
  41
  42 /* This defines a minimum interval that the decoder must remain quiet
  43    before we are allowed to start it running. */
  44 #define TIME_MSEC_DECODER_WAIT 50
  45
  46 /* This defines a minimum interval that the encoder must remain quiet
  47    before we are allowed to configure it.  I had this originally set to
  48    50msec, but Martin Dauskardt <martin.dauskardt@gmx.de> reports that
  49    things work better when it's set to 100msec. */
  50 #define TIME_MSEC_ENCODER_WAIT 100
  51
  52 /* This defines the minimum interval that the encoder must successfully run
  53    before we consider that the encoder has run at least once since its
  54    firmware has been loaded.  This measurement is in important for cases
  55    where we can't do something until we know that the encoder has been run
  56    at least once. */
  57 #define TIME_MSEC_ENCODER_OK 250
  58
  59 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  60 static DEFINE_MUTEX(pvr2_unit_mtx);
  61
  62 static int ctlchg;
  63 static int initusbreset = 1;
  64 static int procreload;
  65 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  66 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  67 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  68 static int init_pause_msec;
  69
  70 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  71 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  72 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  73 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  74 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
  75 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
  76 module_param(procreload, int, S_IRUGO|S_IWUSR);
  77 MODULE_PARM_DESC(procreload,
  78                  "Attempt init failure recovery with firmware reload");
  79 module_param_array(tuner,    int, NULL, 0444);
  80 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  81 module_param_array(video_std,    int, NULL, 0444);
  82 MODULE_PARM_DESC(video_std,"specify initial video standard");
  83 module_param_array(tolerance,    int, NULL, 0444);
  84 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  85
  86 /* US Broadcast channel 7 (175.25 MHz) */
  87 static int default_tv_freq    = 175250000L;
  88 /* 104.3 MHz, a usable FM station for my area */
  89 static int default_radio_freq = 104300000L;
  90
  91 module_param_named(tv_freq, default_tv_freq, int, 0444);
  92 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  93 module_param_named(radio_freq, default_radio_freq, int, 0444);
  94 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  95
  96 #define PVR2_CTL_WRITE_ENDPOINT  0x01
  97 #define PVR2_CTL_READ_ENDPOINT   0x81
  98
  99 #define PVR2_GPIO_IN 0x9008
 100 #define PVR2_GPIO_OUT 0x900c
 101 #define PVR2_GPIO_DIR 0x9020
 102
 103 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 104
 105 #define PVR2_FIRMWARE_ENDPOINT   0x02
 106
 107 /* size of a firmware chunk */
 108 #define FIRMWARE_CHUNK_SIZE 0x2000
 109
 110 /* Define the list of additional controls we'll dynamically construct based
 111    on query of the cx2341x module. */
 112 struct pvr2_mpeg_ids {
 113         const char *strid;
 114         int id;
 115 };
 116 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 117         {
 118                 .strid = "audio_layer",
 119                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 120         },{
 121                 .strid = "audio_bitrate",
 122                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 123         },{
 124                 /* Already using audio_mode elsewhere :-( */
 125                 .strid = "mpeg_audio_mode",
 126                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 127         },{
 128                 .strid = "mpeg_audio_mode_extension",
 129                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 130         },{
 131                 .strid = "audio_emphasis",
 132                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 133         },{
 134                 .strid = "audio_crc",
 135                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 136         },{
 137                 .strid = "video_aspect",
 138                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 139         },{
 140                 .strid = "video_b_frames",
 141                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 142         },{
 143                 .strid = "video_gop_size",
 144                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 145         },{
 146                 .strid = "video_gop_closure",
 147                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 148         },{
 149                 .strid = "video_bitrate_mode",
 150                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 151         },{
 152                 .strid = "video_bitrate",
 153                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 154         },{
 155                 .strid = "video_bitrate_peak",
 156                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 157         },{
 158                 .strid = "video_temporal_decimation",
 159                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 160         },{
 161                 .strid = "stream_type",
 162                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 163         },{
 164                 .strid = "video_spatial_filter_mode",
 165                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 166         },{
 167                 .strid = "video_spatial_filter",
 168                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 169         },{
 170                 .strid = "video_luma_spatial_filter_type",
 171                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 172         },{
 173                 .strid = "video_chroma_spatial_filter_type",
 174                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 175         },{
 176                 .strid = "video_temporal_filter_mode",
 177                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 178         },{
 179                 .strid = "video_temporal_filter",
 180                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 181         },{
 182                 .strid = "video_median_filter_type",
 183                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 184         },{
 185                 .strid = "video_luma_median_filter_top",
 186                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 187         },{
 188                 .strid = "video_luma_median_filter_bottom",
 189                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 190         },{
 191                 .strid = "video_chroma_median_filter_top",
 192                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 193         },{
 194                 .strid = "video_chroma_median_filter_bottom",
 195                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 196         }
 197 };
 198 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 199
 200
 201 static const char *control_values_srate[] = {
 202         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 203         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 204         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 205 };
 206
 207
 208
 209 static const char *control_values_input[] = {
 210         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 211         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 212         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 213         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 214         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 215 };
 216
 217
 218 static const char *control_values_audiomode[] = {
 219         [V4L2_TUNER_MODE_MONO]   = "Mono",
 220         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 221         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 222         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 223         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 224 };
 225
 226
 227 static const char *control_values_hsm[] = {
 228         [PVR2_CVAL_HSM_FAIL] = "Fail",
 229         [PVR2_CVAL_HSM_HIGH] = "High",
 230         [PVR2_CVAL_HSM_FULL] = "Full",
 231 };
 232
 233
 234 static const char *pvr2_state_names[] = {
 235         [PVR2_STATE_NONE] =    "none",
 236         [PVR2_STATE_DEAD] =    "dead",
 237         [PVR2_STATE_COLD] =    "cold",
 238         [PVR2_STATE_WARM] =    "warm",
 239         [PVR2_STATE_ERROR] =   "error",
 240         [PVR2_STATE_READY] =   "ready",
 241         [PVR2_STATE_RUN] =     "run",
 242 };
 243
 244
 245 struct pvr2_fx2cmd_descdef {
 246         unsigned char id;
 247         unsigned char *desc;
 248 };
 249
 250 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 251         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 252         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 253         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 254         {FX2CMD_REG_WRITE, "write encoder register"},
 255         {FX2CMD_REG_READ, "read encoder register"},
 256         {FX2CMD_MEMSEL, "encoder memsel"},
 257         {FX2CMD_I2C_WRITE, "i2c write"},
 258         {FX2CMD_I2C_READ, "i2c read"},
 259         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 260         {FX2CMD_STREAMING_ON, "stream on"},
 261         {FX2CMD_STREAMING_OFF, "stream off"},
 262         {FX2CMD_FWPOST1, "fwpost1"},
 263         {FX2CMD_POWER_OFF, "power off"},
 264         {FX2CMD_POWER_ON, "power on"},
 265         {FX2CMD_DEEP_RESET, "deep reset"},
 266         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 267         {FX2CMD_GET_IR_CODE, "get IR code"},
 268         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 269         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 270         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 271         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 272         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 273         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 274         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 275 };
 276
 277
 278 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 279 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 280 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 281 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 282 static void pvr2_hdw_worker_i2c(struct work_struct *work);
 283 static void pvr2_hdw_worker_poll(struct work_struct *work);
 284 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 285 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 286 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 287 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 288 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 289 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 290 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 291 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 292 static void pvr2_hdw_quiescent_timeout(unsigned long);
 293 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 294 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 295 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 296 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 297                                 unsigned int timeout,int probe_fl,
 298                                 void *write_data,unsigned int write_len,
 299                                 void *read_data,unsigned int read_len);
 300
 301
 302 static void trace_stbit(const char *name,int val)
 303 {
 304         pvr2_trace(PVR2_TRACE_STBITS,
 305                    "State bit %s <-- %s",
 306                    name,(val ? "true" : "false"));
 307 }
 308
 309 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 310 {
 311         struct pvr2_hdw *hdw = cptr->hdw;
 312         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 313                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 314         } else {
 315                 *vp = 0;
 316         }
 317         return 0;
 318 }
 319
 320 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 321 {
 322         struct pvr2_hdw *hdw = cptr->hdw;
 323         unsigned int slotId = hdw->freqProgSlot;
 324         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 325                 hdw->freqTable[slotId-1] = v;
 326                 /* Handle side effects correctly - if we're tuned to this
 327                    slot, then forgot the slot id relation since the stored
 328                    frequency has been changed. */
 329                 if (hdw->freqSelector) {
 330                         if (hdw->freqSlotRadio == slotId) {
 331                                 hdw->freqSlotRadio = 0;
 332                         }
 333                 } else {
 334                         if (hdw->freqSlotTelevision == slotId) {
 335                                 hdw->freqSlotTelevision = 0;
 336                         }
 337                 }
 338         }
 339         return 0;
 340 }
 341
 342 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 343 {
 344         *vp = cptr->hdw->freqProgSlot;
 345         return 0;
 346 }
 347
 348 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 349 {
 350         struct pvr2_hdw *hdw = cptr->hdw;
 351         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 352                 hdw->freqProgSlot = v;
 353         }
 354         return 0;
 355 }
 356
 357 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 358 {
 359         struct pvr2_hdw *hdw = cptr->hdw;
 360         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 361         return 0;
 362 }
 363
 364 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 365 {
 366         unsigned freq = 0;
 367         struct pvr2_hdw *hdw = cptr->hdw;
 368         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 369         if (slotId > 0) {
 370                 freq = hdw->freqTable[slotId-1];
 371                 if (!freq) return 0;
 372                 pvr2_hdw_set_cur_freq(hdw,freq);
 373         }
 374         if (hdw->freqSelector) {
 375                 hdw->freqSlotRadio = slotId;
 376         } else {
 377                 hdw->freqSlotTelevision = slotId;
 378         }
 379         return 0;
 380 }
 381
 382 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 383 {
 384         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 385         return 0;
 386 }
 387
 388 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 389 {
 390         return cptr->hdw->freqDirty != 0;
 391 }
 392
 393 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 394 {
 395         cptr->hdw->freqDirty = 0;
 396 }
 397
 398 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 399 {
 400         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 401         return 0;
 402 }
 403
 404 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 405 {
 406         /* Actual maximum depends on the video standard in effect. */
 407         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 408                 *vp = 480;
 409         } else {
 410                 *vp = 576;
 411         }
 412         return 0;
 413 }
 414
 415 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 416 {
 417         /* Actual minimum depends on device digitizer type. */
 418         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 419                 *vp = 75;
 420         } else {
 421                 *vp = 17;
 422         }
 423         return 0;
 424 }
 425
 426 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 427 {
 428         *vp = cptr->hdw->input_val;
 429         return 0;
 430 }
 431
 432 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 433 {
 434         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 435 }
 436
 437 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 438 {
 439         return pvr2_hdw_set_input(cptr->hdw,v);
 440 }
 441
 442 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 443 {
 444         return cptr->hdw->input_dirty != 0;
 445 }
 446
 447 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 448 {
 449         cptr->hdw->input_dirty = 0;
 450 }
 451
 452
 453 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 454 {
 455         unsigned long fv;
 456         struct pvr2_hdw *hdw = cptr->hdw;
 457         if (hdw->tuner_signal_stale) {
 458                 pvr2_i2c_core_status_poll(hdw);
 459         }
 460         fv = hdw->tuner_signal_info.rangehigh;
 461         if (!fv) {
 462                 /* Safety fallback */
 463                 *vp = TV_MAX_FREQ;
 464                 return 0;
 465         }
 466         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 467                 fv = (fv * 125) / 2;
 468         } else {
 469                 fv = fv * 62500;
 470         }
 471         *vp = fv;
 472         return 0;
 473 }
 474
 475 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 476 {
 477         unsigned long fv;
 478         struct pvr2_hdw *hdw = cptr->hdw;
 479         if (hdw->tuner_signal_stale) {
 480                 pvr2_i2c_core_status_poll(hdw);
 481         }
 482         fv = hdw->tuner_signal_info.rangelow;
 483         if (!fv) {
 484                 /* Safety fallback */
 485                 *vp = TV_MIN_FREQ;
 486                 return 0;
 487         }
 488         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 489                 fv = (fv * 125) / 2;
 490         } else {
 491                 fv = fv * 62500;
 492         }
 493         *vp = fv;
 494         return 0;
 495 }
 496
 497 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 498 {
 499         return cptr->hdw->enc_stale != 0;
 500 }
 501
 502 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 503 {
 504         cptr->hdw->enc_stale = 0;
 505         cptr->hdw->enc_unsafe_stale = 0;
 506 }
 507
 508 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 509 {
 510         int ret;
 511         struct v4l2_ext_controls cs;
 512         struct v4l2_ext_control c1;
 513         memset(&cs,0,sizeof(cs));
 514         memset(&c1,0,sizeof(c1));
 515         cs.controls = &c1;
 516         cs.count = 1;
 517         c1.id = cptr->info->v4l_id;
 518         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 519                                 VIDIOC_G_EXT_CTRLS);
 520         if (ret) return ret;
 521         *vp = c1.value;
 522         return 0;
 523 }
 524
 525 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 526 {
 527         int ret;
 528         struct pvr2_hdw *hdw = cptr->hdw;
 529         struct v4l2_ext_controls cs;
 530         struct v4l2_ext_control c1;
 531         memset(&cs,0,sizeof(cs));
 532         memset(&c1,0,sizeof(c1));
 533         cs.controls = &c1;
 534         cs.count = 1;
 535         c1.id = cptr->info->v4l_id;
 536         c1.value = v;
 537         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 538                                 hdw->state_encoder_run, &cs,
 539                                 VIDIOC_S_EXT_CTRLS);
 540         if (ret == -EBUSY) {
 541                 /* Oops.  cx2341x is telling us it's not safe to change
 542                    this control while we're capturing.  Make a note of this
 543                    fact so that the pipeline will be stopped the next time
 544                    controls are committed.  Then go on ahead and store this
 545                    change anyway. */
 546                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 547                                         0, &cs,
 548                                         VIDIOC_S_EXT_CTRLS);
 549                 if (!ret) hdw->enc_unsafe_stale = !0;
 550         }
 551         if (ret) return ret;
 552         hdw->enc_stale = !0;
 553         return 0;
 554 }
 555
 556 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 557 {
 558         struct v4l2_queryctrl qctrl;
 559         struct pvr2_ctl_info *info;
 560         qctrl.id = cptr->info->v4l_id;
 561         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 562         /* Strip out the const so we can adjust a function pointer.  It's
 563            OK to do this here because we know this is a dynamically created
 564            control, so the underlying storage for the info pointer is (a)
 565            private to us, and (b) not in read-only storage.  Either we do
 566            this or we significantly complicate the underlying control
 567            implementation. */
 568         info = (struct pvr2_ctl_info *)(cptr->info);
 569         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 570                 if (info->set_value) {
 571                         info->set_value = NULL;
 572                 }
 573         } else {
 574                 if (!(info->set_value)) {
 575                         info->set_value = ctrl_cx2341x_set;
 576                 }
 577         }
 578         return qctrl.flags;
 579 }
 580
 581 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 582 {
 583         *vp = cptr->hdw->state_pipeline_req;
 584         return 0;
 585 }
 586
 587 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 588 {
 589         *vp = cptr->hdw->master_state;
 590         return 0;
 591 }
 592
 593 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 594 {
 595         int result = pvr2_hdw_is_hsm(cptr->hdw);
 596         *vp = PVR2_CVAL_HSM_FULL;
 597         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 598         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 599         return 0;
 600 }
 601
 602 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 603 {
 604         *vp = cptr->hdw->std_mask_avail;
 605         return 0;
 606 }
 607
 608 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 609 {
 610         struct pvr2_hdw *hdw = cptr->hdw;
 611         v4l2_std_id ns;
 612         ns = hdw->std_mask_avail;
 613         ns = (ns & ~m) | (v & m);
 614         if (ns == hdw->std_mask_avail) return 0;
 615         hdw->std_mask_avail = ns;
 616         pvr2_hdw_internal_set_std_avail(hdw);
 617         pvr2_hdw_internal_find_stdenum(hdw);
 618         return 0;
 619 }
 620
 621 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 622                                char *bufPtr,unsigned int bufSize,
 623                                unsigned int *len)
 624 {
 625         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 626         return 0;
 627 }
 628
 629 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 630                                const char *bufPtr,unsigned int bufSize,
 631                                int *mskp,int *valp)
 632 {
 633         int ret;
 634         v4l2_std_id id;
 635         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 636         if (ret < 0) return ret;
 637         if (mskp) *mskp = id;
 638         if (valp) *valp = id;
 639         return 0;
 640 }
 641
 642 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 643 {
 644         *vp = cptr->hdw->std_mask_cur;
 645         return 0;
 646 }
 647
 648 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 649 {
 650         struct pvr2_hdw *hdw = cptr->hdw;
 651         v4l2_std_id ns;
 652         ns = hdw->std_mask_cur;
 653         ns = (ns & ~m) | (v & m);
 654         if (ns == hdw->std_mask_cur) return 0;
 655         hdw->std_mask_cur = ns;
 656         hdw->std_dirty = !0;
 657         pvr2_hdw_internal_find_stdenum(hdw);
 658         return 0;
 659 }
 660
 661 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 662 {
 663         return cptr->hdw->std_dirty != 0;
 664 }
 665
 666 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 667 {
 668         cptr->hdw->std_dirty = 0;
 669 }
 670
 671 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 672 {
 673         struct pvr2_hdw *hdw = cptr->hdw;
 674         pvr2_i2c_core_status_poll(hdw);
 675         *vp = hdw->tuner_signal_info.signal;
 676         return 0;
 677 }
 678
 679 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 680 {
 681         int val = 0;
 682         unsigned int subchan;
 683         struct pvr2_hdw *hdw = cptr->hdw;
 684         pvr2_i2c_core_status_poll(hdw);
 685         subchan = hdw->tuner_signal_info.rxsubchans;
 686         if (subchan & V4L2_TUNER_SUB_MONO) {
 687                 val |= (1 << V4L2_TUNER_MODE_MONO);
 688         }
 689         if (subchan & V4L2_TUNER_SUB_STEREO) {
 690                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 691         }
 692         if (subchan & V4L2_TUNER_SUB_LANG1) {
 693                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 694         }
 695         if (subchan & V4L2_TUNER_SUB_LANG2) {
 696                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 697         }
 698         *vp = val;
 699         return 0;
 700 }
 701
 702
 703 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 704 {
 705         struct pvr2_hdw *hdw = cptr->hdw;
 706         if (v < 0) return -EINVAL;
 707         if (v > hdw->std_enum_cnt) return -EINVAL;
 708         hdw->std_enum_cur = v;
 709         if (!v) return 0;
 710         v--;
 711         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 712         hdw->std_mask_cur = hdw->std_defs[v].id;
 713         hdw->std_dirty = !0;
 714         return 0;
 715 }
 716
 717
 718 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 719 {
 720         *vp = cptr->hdw->std_enum_cur;
 721         return 0;
 722 }
 723
 724
 725 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 726 {
 727         return cptr->hdw->std_dirty != 0;
 728 }
 729
 730
 731 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 732 {
 733         cptr->hdw->std_dirty = 0;
 734 }
 735
 736
 737 #define DEFINT(vmin,vmax) \
 738         .type = pvr2_ctl_int, \
 739         .def.type_int.min_value = vmin, \
 740         .def.type_int.max_value = vmax
 741
 742 #define DEFENUM(tab) \
 743         .type = pvr2_ctl_enum, \
 744         .def.type_enum.count = ARRAY_SIZE(tab), \
 745         .def.type_enum.value_names = tab
 746
 747 #define DEFBOOL \
 748         .type = pvr2_ctl_bool
 749
 750 #define DEFMASK(msk,tab) \
 751         .type = pvr2_ctl_bitmask, \
 752         .def.type_bitmask.valid_bits = msk, \
 753         .def.type_bitmask.bit_names = tab
 754
 755 #define DEFREF(vname) \
 756         .set_value = ctrl_set_##vname, \
 757         .get_value = ctrl_get_##vname, \
 758         .is_dirty = ctrl_isdirty_##vname, \
 759         .clear_dirty = ctrl_cleardirty_##vname
 760
 761
 762 #define VCREATE_FUNCS(vname) \
 763 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 764 {*vp = cptr->hdw->vname##_val; return 0;} \
 765 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 766 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 767 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 768 {return cptr->hdw->vname##_dirty != 0;} \
 769 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 770 {cptr->hdw->vname##_dirty = 0;}
 771
 772 VCREATE_FUNCS(brightness)
 773 VCREATE_FUNCS(contrast)
 774 VCREATE_FUNCS(saturation)
 775 VCREATE_FUNCS(hue)
 776 VCREATE_FUNCS(volume)
 777 VCREATE_FUNCS(balance)
 778 VCREATE_FUNCS(bass)
 779 VCREATE_FUNCS(treble)
 780 VCREATE_FUNCS(mute)
 781 VCREATE_FUNCS(audiomode)
 782 VCREATE_FUNCS(res_hor)
 783 VCREATE_FUNCS(res_ver)
 784 VCREATE_FUNCS(srate)
 785
 786 /* Table definition of all controls which can be manipulated */
 787 static const struct pvr2_ctl_info control_defs[] = {
 788         {
 789                 .v4l_id = V4L2_CID_BRIGHTNESS,
 790                 .desc = "Brightness",
 791                 .name = "brightness",
 792                 .default_value = 128,
 793                 DEFREF(brightness),
 794                 DEFINT(0,255),
 795         },{
 796                 .v4l_id = V4L2_CID_CONTRAST,
 797                 .desc = "Contrast",
 798                 .name = "contrast",
 799                 .default_value = 68,
 800                 DEFREF(contrast),
 801                 DEFINT(0,127),
 802         },{
 803                 .v4l_id = V4L2_CID_SATURATION,
 804                 .desc = "Saturation",
 805                 .name = "saturation",
 806                 .default_value = 64,
 807                 DEFREF(saturation),
 808                 DEFINT(0,127),
 809         },{
 810                 .v4l_id = V4L2_CID_HUE,
 811                 .desc = "Hue",
 812                 .name = "hue",
 813                 .default_value = 0,
 814                 DEFREF(hue),
 815                 DEFINT(-128,127),
 816         },{
 817                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
 818                 .desc = "Volume",
 819                 .name = "volume",
 820                 .default_value = 62000,
 821                 DEFREF(volume),
 822                 DEFINT(0,65535),
 823         },{
 824                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
 825                 .desc = "Balance",
 826                 .name = "balance",
 827                 .default_value = 0,
 828                 DEFREF(balance),
 829                 DEFINT(-32768,32767),
 830         },{
 831                 .v4l_id = V4L2_CID_AUDIO_BASS,
 832                 .desc = "Bass",
 833                 .name = "bass",
 834                 .default_value = 0,
 835                 DEFREF(bass),
 836                 DEFINT(-32768,32767),
 837         },{
 838                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
 839                 .desc = "Treble",
 840                 .name = "treble",
 841                 .default_value = 0,
 842                 DEFREF(treble),
 843                 DEFINT(-32768,32767),
 844         },{
 845                 .v4l_id = V4L2_CID_AUDIO_MUTE,
 846                 .desc = "Mute",
 847                 .name = "mute",
 848                 .default_value = 0,
 849                 DEFREF(mute),
 850                 DEFBOOL,
 851         },{
 852                 .desc = "Video Source",
 853                 .name = "input",
 854                 .internal_id = PVR2_CID_INPUT,
 855                 .default_value = PVR2_CVAL_INPUT_TV,
 856                 .check_value = ctrl_check_input,
 857                 DEFREF(input),
 858                 DEFENUM(control_values_input),
 859         },{
 860                 .desc = "Audio Mode",
 861                 .name = "audio_mode",
 862                 .internal_id = PVR2_CID_AUDIOMODE,
 863                 .default_value = V4L2_TUNER_MODE_STEREO,
 864                 DEFREF(audiomode),
 865                 DEFENUM(control_values_audiomode),
 866         },{
 867                 .desc = "Horizontal capture resolution",
 868                 .name = "resolution_hor",
 869                 .internal_id = PVR2_CID_HRES,
 870                 .default_value = 720,
 871                 DEFREF(res_hor),
 872                 DEFINT(19,720),
 873         },{
 874                 .desc = "Vertical capture resolution",
 875                 .name = "resolution_ver",
 876                 .internal_id = PVR2_CID_VRES,
 877                 .default_value = 480,
 878                 DEFREF(res_ver),
 879                 DEFINT(17,576),
 880                 /* Hook in check for video standard and adjust maximum
 881                    depending on the standard. */
 882                 .get_max_value = ctrl_vres_max_get,
 883                 .get_min_value = ctrl_vres_min_get,
 884         },{
 885                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
 886                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
 887                 .desc = "Audio Sampling Frequency",
 888                 .name = "srate",
 889                 DEFREF(srate),
 890                 DEFENUM(control_values_srate),
 891         },{
 892                 .desc = "Tuner Frequency (Hz)",
 893                 .name = "frequency",
 894                 .internal_id = PVR2_CID_FREQUENCY,
 895                 .default_value = 0,
 896                 .set_value = ctrl_freq_set,
 897                 .get_value = ctrl_freq_get,
 898                 .is_dirty = ctrl_freq_is_dirty,
 899                 .clear_dirty = ctrl_freq_clear_dirty,
 900                 DEFINT(0,0),
 901                 /* Hook in check for input value (tv/radio) and adjust
 902                    max/min values accordingly */
 903                 .get_max_value = ctrl_freq_max_get,
 904                 .get_min_value = ctrl_freq_min_get,
 905         },{
 906                 .desc = "Channel",
 907                 .name = "channel",
 908                 .set_value = ctrl_channel_set,
 909                 .get_value = ctrl_channel_get,
 910                 DEFINT(0,FREQTABLE_SIZE),
 911         },{
 912                 .desc = "Channel Program Frequency",
 913                 .name = "freq_table_value",
 914                 .set_value = ctrl_channelfreq_set,
 915                 .get_value = ctrl_channelfreq_get,
 916                 DEFINT(0,0),
 917                 /* Hook in check for input value (tv/radio) and adjust
 918                    max/min values accordingly */
 919                 .get_max_value = ctrl_freq_max_get,
 920                 .get_min_value = ctrl_freq_min_get,
 921         },{
 922                 .desc = "Channel Program ID",
 923                 .name = "freq_table_channel",
 924                 .set_value = ctrl_channelprog_set,
 925                 .get_value = ctrl_channelprog_get,
 926                 DEFINT(0,FREQTABLE_SIZE),
 927         },{
 928                 .desc = "Streaming Enabled",
 929                 .name = "streaming_enabled",
 930                 .get_value = ctrl_streamingenabled_get,
 931                 DEFBOOL,
 932         },{
 933                 .desc = "USB Speed",
 934                 .name = "usb_speed",
 935                 .get_value = ctrl_hsm_get,
 936                 DEFENUM(control_values_hsm),
 937         },{
 938                 .desc = "Master State",
 939                 .name = "master_state",
 940                 .get_value = ctrl_masterstate_get,
 941                 DEFENUM(pvr2_state_names),
 942         },{
 943                 .desc = "Signal Present",
 944                 .name = "signal_present",
 945                 .get_value = ctrl_signal_get,
 946                 DEFINT(0,65535),
 947         },{
 948                 .desc = "Audio Modes Present",
 949                 .name = "audio_modes_present",
 950                 .get_value = ctrl_audio_modes_present_get,
 951                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
 952                    v4l.  Nothing outside of this module cares about this,
 953                    but I reuse it in order to also reuse the
 954                    control_values_audiomode string table. */
 955                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
 956                          (1 << V4L2_TUNER_MODE_STEREO)|
 957                          (1 << V4L2_TUNER_MODE_LANG1)|
 958                          (1 << V4L2_TUNER_MODE_LANG2)),
 959                         control_values_audiomode),
 960         },{
 961                 .desc = "Video Standards Available Mask",
 962                 .name = "video_standard_mask_available",
 963                 .internal_id = PVR2_CID_STDAVAIL,
 964                 .skip_init = !0,
 965                 .get_value = ctrl_stdavail_get,
 966                 .set_value = ctrl_stdavail_set,
 967                 .val_to_sym = ctrl_std_val_to_sym,
 968                 .sym_to_val = ctrl_std_sym_to_val,
 969                 .type = pvr2_ctl_bitmask,
 970         },{
 971                 .desc = "Video Standards In Use Mask",
 972                 .name = "video_standard_mask_active",
 973                 .internal_id = PVR2_CID_STDCUR,
 974                 .skip_init = !0,
 975                 .get_value = ctrl_stdcur_get,
 976                 .set_value = ctrl_stdcur_set,
 977                 .is_dirty = ctrl_stdcur_is_dirty,
 978                 .clear_dirty = ctrl_stdcur_clear_dirty,
 979                 .val_to_sym = ctrl_std_val_to_sym,
 980                 .sym_to_val = ctrl_std_sym_to_val,
 981                 .type = pvr2_ctl_bitmask,
 982         },{
 983                 .desc = "Video Standard Name",
 984                 .name = "video_standard",
 985                 .internal_id = PVR2_CID_STDENUM,
 986                 .skip_init = !0,
 987                 .get_value = ctrl_stdenumcur_get,
 988                 .set_value = ctrl_stdenumcur_set,
 989                 .is_dirty = ctrl_stdenumcur_is_dirty,
 990                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
 991                 .type = pvr2_ctl_enum,
 992         }
 993 };
 994
 995 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
 996
 997
 998 const char *pvr2_config_get_name(enum pvr2_config cfg)
 999 {
1000         switch (cfg) {
1001         case pvr2_config_empty: return "empty";
1002         case pvr2_config_mpeg: return "mpeg";
1003         case pvr2_config_vbi: return "vbi";
1004         case pvr2_config_pcm: return "pcm";
1005         case pvr2_config_rawvideo: return "raw video";
1006         }
1007         return "<unknown>";
1008 }
1009
1010
1011 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1012 {
1013         return hdw->usb_dev;
1014 }
1015
1016
1017 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1018 {
1019         return hdw->serial_number;
1020 }
1021
1022
1023 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1024 {
1025         return hdw->bus_info;
1026 }
1027
1028
1029 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1030 {
1031         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1032 }
1033
1034 /* Set the currently tuned frequency and account for all possible
1035    driver-core side effects of this action. */
1036 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1037 {
1038         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1039                 if (hdw->freqSelector) {
1040                         /* Swing over to radio frequency selection */
1041                         hdw->freqSelector = 0;
1042                         hdw->freqDirty = !0;
1043                 }
1044                 if (hdw->freqValRadio != val) {
1045                         hdw->freqValRadio = val;
1046                         hdw->freqSlotRadio = 0;
1047                         hdw->freqDirty = !0;
1048                 }
1049         } else {
1050                 if (!(hdw->freqSelector)) {
1051                         /* Swing over to television frequency selection */
1052                         hdw->freqSelector = 1;
1053                         hdw->freqDirty = !0;
1054                 }
1055                 if (hdw->freqValTelevision != val) {
1056                         hdw->freqValTelevision = val;
1057                         hdw->freqSlotTelevision = 0;
1058                         hdw->freqDirty = !0;
1059                 }
1060         }
1061 }
1062
1063 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1064 {
1065         return hdw->unit_number;
1066 }
1067
1068
1069 /* Attempt to locate one of the given set of files.  Messages are logged
1070    appropriate to what has been found.  The return value will be 0 or
1071    greater on success (it will be the index of the file name found) and
1072    fw_entry will be filled in.  Otherwise a negative error is returned on
1073    failure.  If the return value is -ENOENT then no viable firmware file
1074    could be located. */
1075 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1076                                 const struct firmware **fw_entry,
1077                                 const char *fwtypename,
1078                                 unsigned int fwcount,
1079                                 const char *fwnames[])
1080 {
1081         unsigned int idx;
1082         int ret = -EINVAL;
1083         for (idx = 0; idx < fwcount; idx++) {
1084                 ret = request_firmware(fw_entry,
1085                                        fwnames[idx],
1086                                        &hdw->usb_dev->dev);
1087                 if (!ret) {
1088                         trace_firmware("Located %s firmware: %s;"
1089                                        " uploading...",
1090                                        fwtypename,
1091                                        fwnames[idx]);
1092                         return idx;
1093                 }
1094                 if (ret == -ENOENT) continue;
1095                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1096                            "request_firmware fatal error with code=%d",ret);
1097                 return ret;
1098         }
1099         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1100                    "***WARNING***"
1101                    " Device %s firmware"
1102                    " seems to be missing.",
1103                    fwtypename);
1104         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1105                    "Did you install the pvrusb2 firmware files"
1106                    " in their proper location?");
1107         if (fwcount == 1) {
1108                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1109                            "request_firmware unable to locate %s file %s",
1110                            fwtypename,fwnames[0]);
1111         } else {
1112                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1113                            "request_firmware unable to locate"
1114                            " one of the following %s files:",
1115                            fwtypename);
1116                 for (idx = 0; idx < fwcount; idx++) {
1117                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1118                                    "request_firmware: Failed to find %s",
1119                                    fwnames[idx]);
1120                 }
1121         }
1122         return ret;
1123 }
1124
1125
1126 /*
1127  * pvr2_upload_firmware1().
1128  *
1129  * Send the 8051 firmware to the device.  After the upload, arrange for
1130  * device to re-enumerate.
1131  *
1132  * NOTE : the pointer to the firmware data given by request_firmware()
1133  * is not suitable for an usb transaction.
1134  *
1135  */
1136 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1137 {
1138         const struct firmware *fw_entry = NULL;
1139         void  *fw_ptr;
1140         unsigned int pipe;
1141         int ret;
1142         u16 address;
1143
1144         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1145                 hdw->fw1_state = FW1_STATE_OK;
1146                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1147                            "Connected device type defines"
1148                            " no firmware to upload; ignoring firmware");
1149                 return -ENOTTY;
1150         }
1151
1152         hdw->fw1_state = FW1_STATE_FAILED; // default result
1153
1154         trace_firmware("pvr2_upload_firmware1");
1155
1156         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1157                                    hdw->hdw_desc->fx2_firmware.cnt,
1158                                    hdw->hdw_desc->fx2_firmware.lst);
1159         if (ret < 0) {
1160                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1161                 return ret;
1162         }
1163
1164         usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1165         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1166
1167         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1168
1169         if (fw_entry->size != 0x2000){
1170                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1171                 release_firmware(fw_entry);
1172                 return -ENOMEM;
1173         }
1174
1175         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1176         if (fw_ptr == NULL){
1177                 release_firmware(fw_entry);
1178                 return -ENOMEM;
1179         }
1180
1181         /* We have to hold the CPU during firmware upload. */
1182         pvr2_hdw_cpureset_assert(hdw,1);
1183
1184         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1185            chunk. */
1186
1187         ret = 0;
1188         for(address = 0; address < fw_entry->size; address += 0x800) {
1189                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1190                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1191                                        0, fw_ptr, 0x800, HZ);
1192         }
1193
1194         trace_firmware("Upload done, releasing device's CPU");
1195
1196         /* Now release the CPU.  It will disconnect and reconnect later. */
1197         pvr2_hdw_cpureset_assert(hdw,0);
1198
1199         kfree(fw_ptr);
1200         release_firmware(fw_entry);
1201
1202         trace_firmware("Upload done (%d bytes sent)",ret);
1203
1204         /* We should have written 8192 bytes */
1205         if (ret == 8192) {
1206                 hdw->fw1_state = FW1_STATE_RELOAD;
1207                 return 0;
1208         }
1209
1210         return -EIO;
1211 }
1212
1213
1214 /*
1215  * pvr2_upload_firmware2()
1216  *
1217  * This uploads encoder firmware on endpoint 2.
1218  *
1219  */
1220
1221 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1222 {
1223         const struct firmware *fw_entry = NULL;
1224         void  *fw_ptr;
1225         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1226         int actual_length;
1227         int ret = 0;
1228         int fwidx;
1229         static const char *fw_files[] = {
1230                 CX2341X_FIRM_ENC_FILENAME,
1231         };
1232
1233         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1234                 return 0;
1235         }
1236
1237         trace_firmware("pvr2_upload_firmware2");
1238
1239         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1240                                    ARRAY_SIZE(fw_files), fw_files);
1241         if (ret < 0) return ret;
1242         fwidx = ret;
1243         ret = 0;
1244         /* Since we're about to completely reinitialize the encoder,
1245            invalidate our cached copy of its configuration state.  Next
1246            time we configure the encoder, then we'll fully configure it. */
1247         hdw->enc_cur_valid = 0;
1248
1249         /* Encoder is about to be reset so note that as far as we're
1250            concerned now, the encoder has never been run. */
1251         del_timer_sync(&hdw->encoder_run_timer);
1252         if (hdw->state_encoder_runok) {
1253                 hdw->state_encoder_runok = 0;
1254                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1255         }
1256
1257         /* First prepare firmware loading */
1258         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1259         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1260         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1261         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1262         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1263         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1264         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1265         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1266         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1267         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1268         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1269         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1270         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1271         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1272         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1273         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1274         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1275         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1276
1277         if (ret) {
1278                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1279                            "firmware2 upload prep failed, ret=%d",ret);
1280                 release_firmware(fw_entry);
1281                 goto done;
1282         }
1283
1284         /* Now send firmware */
1285
1286         fw_len = fw_entry->size;
1287
1288         if (fw_len % sizeof(u32)) {
1289                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1290                            "size of %s firmware"
1291                            " must be a multiple of %zu bytes",
1292                            fw_files[fwidx],sizeof(u32));
1293                 release_firmware(fw_entry);
1294                 ret = -EINVAL;
1295                 goto done;
1296         }
1297
1298         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1299         if (fw_ptr == NULL){
1300                 release_firmware(fw_entry);
1301                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1302                            "failed to allocate memory for firmware2 upload");
1303                 ret = -ENOMEM;
1304                 goto done;
1305         }
1306
1307         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1308
1309         fw_done = 0;
1310         for (fw_done = 0; fw_done < fw_len;) {
1311                 bcnt = fw_len - fw_done;
1312                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1313                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1314                 /* Usbsnoop log shows that we must swap bytes... */
1315                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1316                         ((u32 *)fw_ptr)[icnt] =
1317                                 ___swab32(((u32 *)fw_ptr)[icnt]);
1318
1319                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1320                                     &actual_length, HZ);
1321                 ret |= (actual_length != bcnt);
1322                 if (ret) break;
1323                 fw_done += bcnt;
1324         }
1325
1326         trace_firmware("upload of %s : %i / %i ",
1327                        fw_files[fwidx],fw_done,fw_len);
1328
1329         kfree(fw_ptr);
1330         release_firmware(fw_entry);
1331
1332         if (ret) {
1333                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1334                            "firmware2 upload transfer failure");
1335                 goto done;
1336         }
1337
1338         /* Finish upload */
1339
1340         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1341         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1342         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1343
1344         if (ret) {
1345                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1346                            "firmware2 upload post-proc failure");
1347         }
1348
1349  done:
1350         if (hdw->hdw_desc->signal_routing_scheme ==
1351             PVR2_ROUTING_SCHEME_GOTVIEW) {
1352                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1353                    hardware. */
1354                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1355         }
1356         return ret;
1357 }
1358
1359
1360 static const char *pvr2_get_state_name(unsigned int st)
1361 {
1362         if (st < ARRAY_SIZE(pvr2_state_names)) {
1363                 return pvr2_state_names[st];
1364         }
1365         return "???";
1366 }
1367
1368 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1369 {
1370         if (!hdw->decoder_ctrl) {
1371                 if (!hdw->flag_decoder_missed) {
1372                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1373                                    "WARNING: No decoder present");
1374                         hdw->flag_decoder_missed = !0;
1375                         trace_stbit("flag_decoder_missed",
1376                                     hdw->flag_decoder_missed);
1377                 }
1378                 return -EIO;
1379         }
1380         hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1381         return 0;
1382 }
1383
1384
1385 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1386 {
1387         if (hdw->decoder_ctrl == ptr) return;
1388         hdw->decoder_ctrl = ptr;
1389         if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1390                 hdw->flag_decoder_missed = 0;
1391                 trace_stbit("flag_decoder_missed",
1392                             hdw->flag_decoder_missed);
1393                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1394                            "Decoder has appeared");
1395                 pvr2_hdw_state_sched(hdw);
1396         }
1397 }
1398
1399
1400 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1401 {
1402         return hdw->master_state;
1403 }
1404
1405
1406 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1407 {
1408         if (!hdw->flag_tripped) return 0;
1409         hdw->flag_tripped = 0;
1410         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1411                    "Clearing driver error statuss");
1412         return !0;
1413 }
1414
1415
1416 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1417 {
1418         int fl;
1419         LOCK_TAKE(hdw->big_lock); do {
1420                 fl = pvr2_hdw_untrip_unlocked(hdw);
1421         } while (0); LOCK_GIVE(hdw->big_lock);
1422         if (fl) pvr2_hdw_state_sched(hdw);
1423         return 0;
1424 }
1425
1426
1427
1428
1429 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1430 {
1431         return hdw->state_pipeline_req != 0;
1432 }
1433
1434
1435 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1436 {
1437         int ret,st;
1438         LOCK_TAKE(hdw->big_lock); do {
1439                 pvr2_hdw_untrip_unlocked(hdw);
1440                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1441                         hdw->state_pipeline_req = enable_flag != 0;
1442                         pvr2_trace(PVR2_TRACE_START_STOP,
1443                                    "/*--TRACE_STREAM--*/ %s",
1444                                    enable_flag ? "enable" : "disable");
1445                 }
1446                 pvr2_hdw_state_sched(hdw);
1447         } while (0); LOCK_GIVE(hdw->big_lock);
1448         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1449         if (enable_flag) {
1450                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1451                         if (st != PVR2_STATE_READY) return -EIO;
1452                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1453                 }
1454         }
1455         return 0;
1456 }
1457
1458
1459 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1460 {
1461         int fl;
1462         LOCK_TAKE(hdw->big_lock);
1463         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1464                 hdw->desired_stream_type = config;
1465                 hdw->state_pipeline_config = 0;
1466                 trace_stbit("state_pipeline_config",
1467                             hdw->state_pipeline_config);
1468                 pvr2_hdw_state_sched(hdw);
1469         }
1470         LOCK_GIVE(hdw->big_lock);
1471         if (fl) return 0;
1472         return pvr2_hdw_wait(hdw,0);
1473 }
1474
1475
1476 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1477 {
1478         int unit_number = hdw->unit_number;
1479         int tp = -1;
1480         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1481                 tp = tuner[unit_number];
1482         }
1483         if (tp < 0) return -EINVAL;
1484         hdw->tuner_type = tp;
1485         hdw->tuner_updated = !0;
1486         return 0;
1487 }
1488
1489
1490 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1491 {
1492         int unit_number = hdw->unit_number;
1493         int tp = 0;
1494         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1495                 tp = video_std[unit_number];
1496                 if (tp) return tp;
1497         }
1498         return 0;
1499 }
1500
1501
1502 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1503 {
1504         int unit_number = hdw->unit_number;
1505         int tp = 0;
1506         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1507                 tp = tolerance[unit_number];
1508         }
1509         return tp;
1510 }
1511
1512
1513 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1514 {
1515         /* Try a harmless request to fetch the eeprom's address over
1516            endpoint 1.  See what happens.  Only the full FX2 image can
1517            respond to this.  If this probe fails then likely the FX2
1518            firmware needs be loaded. */
1519         int result;
1520         LOCK_TAKE(hdw->ctl_lock); do {
1521                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1522                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1523                                            hdw->cmd_buffer,1,
1524                                            hdw->cmd_buffer,1);
1525                 if (result < 0) break;
1526         } while(0); LOCK_GIVE(hdw->ctl_lock);
1527         if (result) {
1528                 pvr2_trace(PVR2_TRACE_INIT,
1529                            "Probe of device endpoint 1 result status %d",
1530                            result);
1531         } else {
1532                 pvr2_trace(PVR2_TRACE_INIT,
1533                            "Probe of device endpoint 1 succeeded");
1534         }
1535         return result == 0;
1536 }
1537
1538 struct pvr2_std_hack {
1539         v4l2_std_id pat;  /* Pattern to match */
1540         v4l2_std_id msk;  /* Which bits we care about */
1541         v4l2_std_id std;  /* What additional standards or default to set */
1542 };
1543
1544 /* This data structure labels specific combinations of standards from
1545    tveeprom that we'll try to recognize.  If we recognize one, then assume
1546    a specified default standard to use.  This is here because tveeprom only
1547    tells us about available standards not the intended default standard (if
1548    any) for the device in question.  We guess the default based on what has
1549    been reported as available.  Note that this is only for guessing a
1550    default - which can always be overridden explicitly - and if the user
1551    has otherwise named a default then that default will always be used in
1552    place of this table. */
1553 static const struct pvr2_std_hack std_eeprom_maps[] = {
1554         {       /* PAL(B/G) */
1555                 .pat = V4L2_STD_B|V4L2_STD_GH,
1556                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1557         },
1558         {       /* NTSC(M) */
1559                 .pat = V4L2_STD_MN,
1560                 .std = V4L2_STD_NTSC_M,
1561         },
1562         {       /* PAL(I) */
1563                 .pat = V4L2_STD_PAL_I,
1564                 .std = V4L2_STD_PAL_I,
1565         },
1566         {       /* SECAM(L/L') */
1567                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1568                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1569         },
1570         {       /* PAL(D/D1/K) */
1571                 .pat = V4L2_STD_DK,
1572                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1573         },
1574 };
1575
1576 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1577 {
1578         char buf[40];
1579         unsigned int bcnt;
1580         v4l2_std_id std1,std2,std3;
1581
1582         std1 = get_default_standard(hdw);
1583         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1584
1585         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1586         pvr2_trace(PVR2_TRACE_STD,
1587                    "Supported video standard(s) reported available"
1588                    " in hardware: %.*s",
1589                    bcnt,buf);
1590
1591         hdw->std_mask_avail = hdw->std_mask_eeprom;
1592
1593         std2 = (std1|std3) & ~hdw->std_mask_avail;
1594         if (std2) {
1595                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1596                 pvr2_trace(PVR2_TRACE_STD,
1597                            "Expanding supported video standards"
1598                            " to include: %.*s",
1599                            bcnt,buf);
1600                 hdw->std_mask_avail |= std2;
1601         }
1602
1603         pvr2_hdw_internal_set_std_avail(hdw);
1604
1605         if (std1) {
1606                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1607                 pvr2_trace(PVR2_TRACE_STD,
1608                            "Initial video standard forced to %.*s",
1609                            bcnt,buf);
1610                 hdw->std_mask_cur = std1;
1611                 hdw->std_dirty = !0;
1612                 pvr2_hdw_internal_find_stdenum(hdw);
1613                 return;
1614         }
1615         if (std3) {
1616                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1617                 pvr2_trace(PVR2_TRACE_STD,
1618                            "Initial video standard"
1619                            " (determined by device type): %.*s",bcnt,buf);
1620                 hdw->std_mask_cur = std3;
1621                 hdw->std_dirty = !0;
1622                 pvr2_hdw_internal_find_stdenum(hdw);
1623                 return;
1624         }
1625
1626         {
1627                 unsigned int idx;
1628                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1629                         if (std_eeprom_maps[idx].msk ?
1630                             ((std_eeprom_maps[idx].pat ^
1631                              hdw->std_mask_eeprom) &
1632                              std_eeprom_maps[idx].msk) :
1633                             (std_eeprom_maps[idx].pat !=
1634                              hdw->std_mask_eeprom)) continue;
1635                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1636                                                   std_eeprom_maps[idx].std);
1637                         pvr2_trace(PVR2_TRACE_STD,
1638                                    "Initial video standard guessed as %.*s",
1639                                    bcnt,buf);
1640                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1641                         hdw->std_dirty = !0;
1642                         pvr2_hdw_internal_find_stdenum(hdw);
1643                         return;
1644                 }
1645         }
1646
1647         if (hdw->std_enum_cnt > 1) {
1648                 // Autoselect the first listed standard
1649                 hdw->std_enum_cur = 1;
1650                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1651                 hdw->std_dirty = !0;
1652                 pvr2_trace(PVR2_TRACE_STD,
1653                            "Initial video standard auto-selected to %s",
1654                            hdw->std_defs[hdw->std_enum_cur-1].name);
1655                 return;
1656         }
1657
1658         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1659                    "Unable to select a viable initial video standard");
1660 }
1661
1662
1663 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1664 {
1665         int ret;
1666         unsigned int idx;
1667         struct pvr2_ctrl *cptr;
1668         int reloadFl = 0;
1669         if (hdw->hdw_desc->fx2_firmware.cnt) {
1670                 if (!reloadFl) {
1671                         reloadFl =
1672                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1673                                  == 0);
1674                         if (reloadFl) {
1675                                 pvr2_trace(PVR2_TRACE_INIT,
1676                                            "USB endpoint config looks strange"
1677                                            "; possibly firmware needs to be"
1678                                            " loaded");
1679                         }
1680                 }
1681                 if (!reloadFl) {
1682                         reloadFl = !pvr2_hdw_check_firmware(hdw);
1683                         if (reloadFl) {
1684                                 pvr2_trace(PVR2_TRACE_INIT,
1685                                            "Check for FX2 firmware failed"
1686                                            "; possibly firmware needs to be"
1687                                            " loaded");
1688                         }
1689                 }
1690                 if (reloadFl) {
1691                         if (pvr2_upload_firmware1(hdw) != 0) {
1692                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1693                                            "Failure uploading firmware1");
1694                         }
1695                         return;
1696                 }
1697         }
1698         hdw->fw1_state = FW1_STATE_OK;
1699
1700         if (initusbreset) {
1701                 pvr2_hdw_device_reset(hdw);
1702         }
1703         if (!pvr2_hdw_dev_ok(hdw)) return;
1704
1705         for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1706                 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1707         }
1708
1709         if (!hdw->hdw_desc->flag_no_powerup) {
1710                 pvr2_hdw_cmd_powerup(hdw);
1711                 if (!pvr2_hdw_dev_ok(hdw)) return;
1712         }
1713
1714         // This step MUST happen after the earlier powerup step.
1715         pvr2_i2c_core_init(hdw);
1716         if (!pvr2_hdw_dev_ok(hdw)) return;
1717
1718         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1719                 cptr = hdw->controls + idx;
1720                 if (cptr->info->skip_init) continue;
1721                 if (!cptr->info->set_value) continue;
1722                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1723         }
1724
1725         /* Set up special default values for the television and radio
1726            frequencies here.  It's not really important what these defaults
1727            are, but I set them to something usable in the Chicago area just
1728            to make driver testing a little easier. */
1729
1730         hdw->freqValTelevision = default_tv_freq;
1731         hdw->freqValRadio = default_radio_freq;
1732
1733         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
1734         // thread-safe against the normal pvr2_send_request() mechanism.
1735         // (We should make it thread safe).
1736
1737         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1738                 ret = pvr2_hdw_get_eeprom_addr(hdw);
1739                 if (!pvr2_hdw_dev_ok(hdw)) return;
1740                 if (ret < 0) {
1741                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1742                                    "Unable to determine location of eeprom,"
1743                                    " skipping");
1744                 } else {
1745                         hdw->eeprom_addr = ret;
1746                         pvr2_eeprom_analyze(hdw);
1747                         if (!pvr2_hdw_dev_ok(hdw)) return;
1748                 }
1749         } else {
1750                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1751                 hdw->tuner_updated = !0;
1752                 hdw->std_mask_eeprom = V4L2_STD_ALL;
1753         }
1754
1755         pvr2_hdw_setup_std(hdw);
1756
1757         if (!get_default_tuner_type(hdw)) {
1758                 pvr2_trace(PVR2_TRACE_INIT,
1759                            "pvr2_hdw_setup: Tuner type overridden to %d",
1760                            hdw->tuner_type);
1761         }
1762
1763         pvr2_i2c_core_check_stale(hdw);
1764         hdw->tuner_updated = 0;
1765
1766         if (!pvr2_hdw_dev_ok(hdw)) return;
1767
1768         if (hdw->hdw_desc->signal_routing_scheme ==
1769             PVR2_ROUTING_SCHEME_GOTVIEW) {
1770                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1771                    hardware. */
1772                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1773         }
1774
1775         pvr2_hdw_commit_setup(hdw);
1776
1777         hdw->vid_stream = pvr2_stream_create();
1778         if (!pvr2_hdw_dev_ok(hdw)) return;
1779         pvr2_trace(PVR2_TRACE_INIT,
1780                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1781         if (hdw->vid_stream) {
1782                 idx = get_default_error_tolerance(hdw);
1783                 if (idx) {
1784                         pvr2_trace(PVR2_TRACE_INIT,
1785                                    "pvr2_hdw_setup: video stream %p"
1786                                    " setting tolerance %u",
1787                                    hdw->vid_stream,idx);
1788                 }
1789                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1790                                   PVR2_VID_ENDPOINT,idx);
1791         }
1792
1793         if (!pvr2_hdw_dev_ok(hdw)) return;
1794
1795         hdw->flag_init_ok = !0;
1796
1797         pvr2_hdw_state_sched(hdw);
1798 }
1799
1800
1801 /* Set up the structure and attempt to put the device into a usable state.
1802    This can be a time-consuming operation, which is why it is not done
1803    internally as part of the create() step. */
1804 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1805 {
1806         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1807         do {
1808                 pvr2_hdw_setup_low(hdw);
1809                 pvr2_trace(PVR2_TRACE_INIT,
1810                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1811                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1812                 if (pvr2_hdw_dev_ok(hdw)) {
1813                         if (hdw->flag_init_ok) {
1814                                 pvr2_trace(
1815                                         PVR2_TRACE_INFO,
1816                                         "Device initialization"
1817                                         " completed successfully.");
1818                                 break;
1819                         }
1820                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
1821                                 pvr2_trace(
1822                                         PVR2_TRACE_INFO,
1823                                         "Device microcontroller firmware"
1824                                         " (re)loaded; it should now reset"
1825                                         " and reconnect.");
1826                                 break;
1827                         }
1828                         pvr2_trace(
1829                                 PVR2_TRACE_ERROR_LEGS,
1830                                 "Device initialization was not successful.");
1831                         if (hdw->fw1_state == FW1_STATE_MISSING) {
1832                                 pvr2_trace(
1833                                         PVR2_TRACE_ERROR_LEGS,
1834                                         "Giving up since device"
1835                                         " microcontroller firmware"
1836                                         " appears to be missing.");
1837                                 break;
1838                         }
1839                 }
1840                 if (procreload) {
1841                         pvr2_trace(
1842                                 PVR2_TRACE_ERROR_LEGS,
1843                                 "Attempting pvrusb2 recovery by reloading"
1844                                 " primary firmware.");
1845                         pvr2_trace(
1846                                 PVR2_TRACE_ERROR_LEGS,
1847                                 "If this works, device should disconnect"
1848                                 " and reconnect in a sane state.");
1849                         hdw->fw1_state = FW1_STATE_UNKNOWN;
1850                         pvr2_upload_firmware1(hdw);
1851                 } else {
1852                         pvr2_trace(
1853                                 PVR2_TRACE_ERROR_LEGS,
1854                                 "***WARNING*** pvrusb2 device hardware"
1855                                 " appears to be jammed"
1856                                 " and I can't clear it.");
1857                         pvr2_trace(
1858                                 PVR2_TRACE_ERROR_LEGS,
1859                                 "You might need to power cycle"
1860                                 " the pvrusb2 device"
1861                                 " in order to recover.");
1862                 }
1863         } while (0);
1864         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1865 }
1866
1867
1868 /* Perform second stage initialization.  Set callback pointer first so that
1869    we can avoid a possible initialization race (if the kernel thread runs
1870    before the callback has been set). */
1871 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
1872                         void (*callback_func)(void *),
1873                         void *callback_data)
1874 {
1875         LOCK_TAKE(hdw->big_lock); do {
1876                 if (hdw->flag_disconnected) {
1877                         /* Handle a race here: If we're already
1878                            disconnected by this point, then give up.  If we
1879                            get past this then we'll remain connected for
1880                            the duration of initialization since the entire
1881                            initialization sequence is now protected by the
1882                            big_lock. */
1883                         break;
1884                 }
1885                 hdw->state_data = callback_data;
1886                 hdw->state_func = callback_func;
1887                 pvr2_hdw_setup(hdw);
1888         } while (0); LOCK_GIVE(hdw->big_lock);
1889         return hdw->flag_init_ok;
1890 }
1891
1892
1893 /* Create, set up, and return a structure for interacting with the
1894    underlying hardware.  */
1895 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1896                                  const struct usb_device_id *devid)
1897 {
1898         unsigned int idx,cnt1,cnt2,m;
1899         struct pvr2_hdw *hdw;
1900         int valid_std_mask;
1901         struct pvr2_ctrl *cptr;
1902         const struct pvr2_device_desc *hdw_desc;
1903         __u8 ifnum;
1904         struct v4l2_queryctrl qctrl;
1905         struct pvr2_ctl_info *ciptr;
1906
1907         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
1908
1909         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1910         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1911                    hdw,hdw_desc->description);
1912         if (!hdw) goto fail;
1913
1914         init_timer(&hdw->quiescent_timer);
1915         hdw->quiescent_timer.data = (unsigned long)hdw;
1916         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1917
1918         init_timer(&hdw->encoder_wait_timer);
1919         hdw->encoder_wait_timer.data = (unsigned long)hdw;
1920         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1921
1922         init_timer(&hdw->encoder_run_timer);
1923         hdw->encoder_run_timer.data = (unsigned long)hdw;
1924         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
1925
1926         hdw->master_state = PVR2_STATE_DEAD;
1927
1928         init_waitqueue_head(&hdw->state_wait_data);
1929
1930         hdw->tuner_signal_stale = !0;
1931         cx2341x_fill_defaults(&hdw->enc_ctl_state);
1932
1933         /* Calculate which inputs are OK */
1934         m = 0;
1935         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
1936         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
1937                 m |= 1 << PVR2_CVAL_INPUT_DTV;
1938         }
1939         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
1940         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
1941         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
1942         hdw->input_avail_mask = m;
1943         hdw->input_allowed_mask = hdw->input_avail_mask;
1944
1945         /* If not a hybrid device, pathway_state never changes.  So
1946            initialize it here to what it should forever be. */
1947         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
1948                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
1949         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
1950                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
1951         }
1952
1953         hdw->control_cnt = CTRLDEF_COUNT;
1954         hdw->control_cnt += MPEGDEF_COUNT;
1955         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1956                                 GFP_KERNEL);
1957         if (!hdw->controls) goto fail;
1958         hdw->hdw_desc = hdw_desc;
1959         for (idx = 0; idx < hdw->control_cnt; idx++) {
1960                 cptr = hdw->controls + idx;
1961                 cptr->hdw = hdw;
1962         }
1963         for (idx = 0; idx < 32; idx++) {
1964                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1965         }
1966         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1967                 cptr = hdw->controls + idx;
1968                 cptr->info = control_defs+idx;
1969         }
1970
1971         /* Ensure that default input choice is a valid one. */
1972         m = hdw->input_avail_mask;
1973         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
1974                 if (!((1 << idx) & m)) continue;
1975                 hdw->input_val = idx;
1976                 break;
1977         }
1978
1979         /* Define and configure additional controls from cx2341x module. */
1980         hdw->mpeg_ctrl_info = kzalloc(
1981                 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1982         if (!hdw->mpeg_ctrl_info) goto fail;
1983         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1984                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1985                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1986                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1987                 ciptr->name = mpeg_ids[idx].strid;
1988                 ciptr->v4l_id = mpeg_ids[idx].id;
1989                 ciptr->skip_init = !0;
1990                 ciptr->get_value = ctrl_cx2341x_get;
1991                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1992                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1993                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1994                 qctrl.id = ciptr->v4l_id;
1995                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1996                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1997                         ciptr->set_value = ctrl_cx2341x_set;
1998                 }
1999                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2000                         PVR2_CTLD_INFO_DESC_SIZE);
2001                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2002                 ciptr->default_value = qctrl.default_value;
2003                 switch (qctrl.type) {
2004                 default:
2005                 case V4L2_CTRL_TYPE_INTEGER:
2006                         ciptr->type = pvr2_ctl_int;
2007                         ciptr->def.type_int.min_value = qctrl.minimum;
2008                         ciptr->def.type_int.max_value = qctrl.maximum;
2009                         break;
2010                 case V4L2_CTRL_TYPE_BOOLEAN:
2011                         ciptr->type = pvr2_ctl_bool;
2012                         break;
2013                 case V4L2_CTRL_TYPE_MENU:
2014                         ciptr->type = pvr2_ctl_enum;
2015                         ciptr->def.type_enum.value_names =
2016                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2017                                                                 ciptr->v4l_id);
2018                         for (cnt1 = 0;
2019                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2020                              cnt1++) { }
2021                         ciptr->def.type_enum.count = cnt1;
2022                         break;
2023                 }
2024                 cptr->info = ciptr;
2025         }
2026
2027         // Initialize video standard enum dynamic control
2028         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2029         if (cptr) {
2030                 memcpy(&hdw->std_info_enum,cptr->info,
2031                        sizeof(hdw->std_info_enum));
2032                 cptr->info = &hdw->std_info_enum;
2033
2034         }
2035         // Initialize control data regarding video standard masks
2036         valid_std_mask = pvr2_std_get_usable();
2037         for (idx = 0; idx < 32; idx++) {
2038                 if (!(valid_std_mask & (1 << idx))) continue;
2039                 cnt1 = pvr2_std_id_to_str(
2040                         hdw->std_mask_names[idx],
2041                         sizeof(hdw->std_mask_names[idx])-1,
2042                         1 << idx);
2043                 hdw->std_mask_names[idx][cnt1] = 0;
2044         }
2045         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2046         if (cptr) {
2047                 memcpy(&hdw->std_info_avail,cptr->info,
2048                        sizeof(hdw->std_info_avail));
2049                 cptr->info = &hdw->std_info_avail;
2050                 hdw->std_info_avail.def.type_bitmask.bit_names =
2051                         hdw->std_mask_ptrs;
2052                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2053                         valid_std_mask;
2054         }
2055         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2056         if (cptr) {
2057                 memcpy(&hdw->std_info_cur,cptr->info,
2058                        sizeof(hdw->std_info_cur));
2059                 cptr->info = &hdw->std_info_cur;
2060                 hdw->std_info_cur.def.type_bitmask.bit_names =
2061                         hdw->std_mask_ptrs;
2062                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2063                         valid_std_mask;
2064         }
2065
2066         hdw->eeprom_addr = -1;
2067         hdw->unit_number = -1;
2068         hdw->v4l_minor_number_video = -1;
2069         hdw->v4l_minor_number_vbi = -1;
2070         hdw->v4l_minor_number_radio = -1;
2071         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2072         if (!hdw->ctl_write_buffer) goto fail;
2073         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2074         if (!hdw->ctl_read_buffer) goto fail;
2075         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2076         if (!hdw->ctl_write_urb) goto fail;
2077         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2078         if (!hdw->ctl_read_urb) goto fail;
2079
2080         mutex_lock(&pvr2_unit_mtx); do {
2081                 for (idx = 0; idx < PVR_NUM; idx++) {
2082                         if (unit_pointers[idx]) continue;
2083                         hdw->unit_number = idx;
2084                         unit_pointers[idx] = hdw;
2085                         break;
2086                 }
2087         } while (0); mutex_unlock(&pvr2_unit_mtx);
2088
2089         cnt1 = 0;
2090         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2091         cnt1 += cnt2;
2092         if (hdw->unit_number >= 0) {
2093                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2094                                  ('a' + hdw->unit_number));
2095                 cnt1 += cnt2;
2096         }
2097         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2098         hdw->name[cnt1] = 0;
2099
2100         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2101         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2102         INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
2103
2104         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2105                    hdw->unit_number,hdw->name);
2106
2107         hdw->tuner_type = -1;
2108         hdw->flag_ok = !0;
2109
2110         hdw->usb_intf = intf;
2111         hdw->usb_dev = interface_to_usbdev(intf);
2112
2113         scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2114                   "usb %s address %d",
2115                   hdw->usb_dev->dev.bus_id,
2116                   hdw->usb_dev->devnum);
2117
2118         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2119         usb_set_interface(hdw->usb_dev,ifnum,0);
2120
2121         mutex_init(&hdw->ctl_lock_mutex);
2122         mutex_init(&hdw->big_lock_mutex);
2123
2124         return hdw;
2125  fail:
2126         if (hdw) {
2127                 del_timer_sync(&hdw->quiescent_timer);
2128                 del_timer_sync(&hdw->encoder_run_timer);
2129                 del_timer_sync(&hdw->encoder_wait_timer);
2130                 if (hdw->workqueue) {
2131                         flush_workqueue(hdw->workqueue);
2132                         destroy_workqueue(hdw->workqueue);
2133                         hdw->workqueue = NULL;
2134                 }
2135                 usb_free_urb(hdw->ctl_read_urb);
2136                 usb_free_urb(hdw->ctl_write_urb);
2137                 kfree(hdw->ctl_read_buffer);
2138                 kfree(hdw->ctl_write_buffer);
2139                 kfree(hdw->controls);
2140                 kfree(hdw->mpeg_ctrl_info);
2141                 kfree(hdw->std_defs);
2142                 kfree(hdw->std_enum_names);
2143                 kfree(hdw);
2144         }
2145         return NULL;
2146 }
2147
2148
2149 /* Remove _all_ associations between this driver and the underlying USB
2150    layer. */
2151 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2152 {
2153         if (hdw->flag_disconnected) return;
2154         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2155         if (hdw->ctl_read_urb) {
2156                 usb_kill_urb(hdw->ctl_read_urb);
2157                 usb_free_urb(hdw->ctl_read_urb);
2158                 hdw->ctl_read_urb = NULL;
2159         }
2160         if (hdw->ctl_write_urb) {
2161                 usb_kill_urb(hdw->ctl_write_urb);
2162                 usb_free_urb(hdw->ctl_write_urb);
2163                 hdw->ctl_write_urb = NULL;
2164         }
2165         if (hdw->ctl_read_buffer) {
2166                 kfree(hdw->ctl_read_buffer);
2167                 hdw->ctl_read_buffer = NULL;
2168         }
2169         if (hdw->ctl_write_buffer) {
2170                 kfree(hdw->ctl_write_buffer);
2171                 hdw->ctl_write_buffer = NULL;
2172         }
2173         hdw->flag_disconnected = !0;
2174         hdw->usb_dev = NULL;
2175         hdw->usb_intf = NULL;
2176         pvr2_hdw_render_useless(hdw);
2177 }
2178
2179
2180 /* Destroy hardware interaction structure */
2181 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2182 {
2183         if (!hdw) return;
2184         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2185         if (hdw->workqueue) {
2186                 flush_workqueue(hdw->workqueue);
2187                 destroy_workqueue(hdw->workqueue);
2188                 hdw->workqueue = NULL;
2189         }
2190         del_timer_sync(&hdw->quiescent_timer);
2191         del_timer_sync(&hdw->encoder_run_timer);
2192         del_timer_sync(&hdw->encoder_wait_timer);
2193         if (hdw->fw_buffer) {
2194                 kfree(hdw->fw_buffer);
2195                 hdw->fw_buffer = NULL;
2196         }
2197         if (hdw->vid_stream) {
2198                 pvr2_stream_destroy(hdw->vid_stream);
2199                 hdw->vid_stream = NULL;
2200         }
2201         if (hdw->decoder_ctrl) {
2202                 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2203         }
2204         pvr2_i2c_core_done(hdw);
2205         pvr2_hdw_remove_usb_stuff(hdw);
2206         mutex_lock(&pvr2_unit_mtx); do {
2207                 if ((hdw->unit_number >= 0) &&
2208                     (hdw->unit_number < PVR_NUM) &&
2209                     (unit_pointers[hdw->unit_number] == hdw)) {
2210                         unit_pointers[hdw->unit_number] = NULL;
2211                 }
2212         } while (0); mutex_unlock(&pvr2_unit_mtx);
2213         kfree(hdw->controls);
2214         kfree(hdw->mpeg_ctrl_info);
2215         kfree(hdw->std_defs);
2216         kfree(hdw->std_enum_names);
2217         kfree(hdw);
2218 }
2219
2220
2221 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2222 {
2223         return (hdw && hdw->flag_ok);
2224 }
2225
2226
2227 /* Called when hardware has been unplugged */
2228 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2229 {
2230         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2231         LOCK_TAKE(hdw->big_lock);
2232         LOCK_TAKE(hdw->ctl_lock);
2233         pvr2_hdw_remove_usb_stuff(hdw);
2234         LOCK_GIVE(hdw->ctl_lock);
2235         LOCK_GIVE(hdw->big_lock);
2236 }
2237
2238
2239 // Attempt to autoselect an appropriate value for std_enum_cur given
2240 // whatever is currently in std_mask_cur
2241 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2242 {
2243         unsigned int idx;
2244         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2245                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2246                         hdw->std_enum_cur = idx;
2247                         return;
2248                 }
2249         }
2250         hdw->std_enum_cur = 0;
2251 }
2252
2253
2254 // Calculate correct set of enumerated standards based on currently known
2255 // set of available standards bits.
2256 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2257 {
2258         struct v4l2_standard *newstd;
2259         unsigned int std_cnt;
2260         unsigned int idx;
2261
2262         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2263
2264         if (hdw->std_defs) {
2265                 kfree(hdw->std_defs);
2266                 hdw->std_defs = NULL;
2267         }
2268         hdw->std_enum_cnt = 0;
2269         if (hdw->std_enum_names) {
2270                 kfree(hdw->std_enum_names);
2271                 hdw->std_enum_names = NULL;
2272         }
2273
2274         if (!std_cnt) {
2275                 pvr2_trace(
2276                         PVR2_TRACE_ERROR_LEGS,
2277                         "WARNING: Failed to identify any viable standards");
2278         }
2279         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2280         hdw->std_enum_names[0] = "none";
2281         for (idx = 0; idx < std_cnt; idx++) {
2282                 hdw->std_enum_names[idx+1] =
2283                         newstd[idx].name;
2284         }
2285         // Set up the dynamic control for this standard
2286         hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2287         hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2288         hdw->std_defs = newstd;
2289         hdw->std_enum_cnt = std_cnt+1;
2290         hdw->std_enum_cur = 0;
2291         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2292 }
2293
2294
2295 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2296                                struct v4l2_standard *std,
2297                                unsigned int idx)
2298 {
2299         int ret = -EINVAL;
2300         if (!idx) return ret;
2301         LOCK_TAKE(hdw->big_lock); do {
2302                 if (idx >= hdw->std_enum_cnt) break;
2303                 idx--;
2304                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2305                 ret = 0;
2306         } while (0); LOCK_GIVE(hdw->big_lock);
2307         return ret;
2308 }
2309
2310
2311 /* Get the number of defined controls */
2312 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2313 {
2314         return hdw->control_cnt;
2315 }
2316
2317
2318 /* Retrieve a control handle given its index (0..count-1) */
2319 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2320                                              unsigned int idx)
2321 {
2322         if (idx >= hdw->control_cnt) return NULL;
2323         return hdw->controls + idx;
2324 }
2325
2326
2327 /* Retrieve a control handle given its index (0..count-1) */
2328 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2329                                           unsigned int ctl_id)
2330 {
2331         struct pvr2_ctrl *cptr;
2332         unsigned int idx;
2333         int i;
2334
2335         /* This could be made a lot more efficient, but for now... */
2336         for (idx = 0; idx < hdw->control_cnt; idx++) {
2337                 cptr = hdw->controls + idx;
2338                 i = cptr->info->internal_id;
2339                 if (i && (i == ctl_id)) return cptr;
2340         }
2341         return NULL;
2342 }
2343
2344
2345 /* Given a V4L ID, retrieve the control structure associated with it. */
2346 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2347 {
2348         struct pvr2_ctrl *cptr;
2349         unsigned int idx;
2350         int i;
2351
2352         /* This could be made a lot more efficient, but for now... */
2353         for (idx = 0; idx < hdw->control_cnt; idx++) {
2354                 cptr = hdw->controls + idx;
2355                 i = cptr->info->v4l_id;
2356                 if (i && (i == ctl_id)) return cptr;
2357         }
2358         return NULL;
2359 }
2360
2361
2362 /* Given a V4L ID for its immediate predecessor, retrieve the control
2363    structure associated with it. */
2364 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2365                                             unsigned int ctl_id)
2366 {
2367         struct pvr2_ctrl *cptr,*cp2;
2368         unsigned int idx;
2369         int i;
2370
2371         /* This could be made a lot more efficient, but for now... */
2372         cp2 = NULL;
2373         for (idx = 0; idx < hdw->control_cnt; idx++) {
2374                 cptr = hdw->controls + idx;
2375                 i = cptr->info->v4l_id;
2376                 if (!i) continue;
2377                 if (i <= ctl_id) continue;
2378                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2379                 cp2 = cptr;
2380         }
2381         return cp2;
2382         return NULL;
2383 }
2384
2385
2386 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2387 {
2388         switch (tp) {
2389         case pvr2_ctl_int: return "integer";
2390         case pvr2_ctl_enum: return "enum";
2391         case pvr2_ctl_bool: return "boolean";
2392         case pvr2_ctl_bitmask: return "bitmask";
2393         }
2394         return "";
2395 }
2396
2397
2398 /* Figure out if we need to commit control changes.  If so, mark internal
2399    state flags to indicate this fact and return true.  Otherwise do nothing
2400    else and return false. */
2401 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2402 {
2403         unsigned int idx;
2404         struct pvr2_ctrl *cptr;
2405         int value;
2406         int commit_flag = 0;
2407         char buf[100];
2408         unsigned int bcnt,ccnt;
2409
2410         for (idx = 0; idx < hdw->control_cnt; idx++) {
2411                 cptr = hdw->controls + idx;
2412                 if (!cptr->info->is_dirty) continue;
2413                 if (!cptr->info->is_dirty(cptr)) continue;
2414                 commit_flag = !0;
2415
2416                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2417                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2418                                  cptr->info->name);
2419                 value = 0;
2420                 cptr->info->get_value(cptr,&value);
2421                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2422                                                 buf+bcnt,
2423                                                 sizeof(buf)-bcnt,&ccnt);
2424                 bcnt += ccnt;
2425                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2426                                   get_ctrl_typename(cptr->info->type));
2427                 pvr2_trace(PVR2_TRACE_CTL,
2428                            "/*--TRACE_COMMIT--*/ %.*s",
2429                            bcnt,buf);
2430         }
2431
2432         if (!commit_flag) {
2433                 /* Nothing has changed */
2434                 return 0;
2435         }
2436
2437         hdw->state_pipeline_config = 0;
2438         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2439         pvr2_hdw_state_sched(hdw);
2440
2441         return !0;
2442 }
2443
2444
2445 /* Perform all operations needed to commit all control changes.  This must
2446    be performed in synchronization with the pipeline state and is thus
2447    expected to be called as part of the driver's worker thread.  Return
2448    true if commit successful, otherwise return false to indicate that
2449    commit isn't possible at this time. */
2450 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2451 {
2452         unsigned int idx;
2453         struct pvr2_ctrl *cptr;
2454         int disruptive_change;
2455
2456         /* Handle some required side effects when the video standard is
2457            changed.... */
2458         if (hdw->std_dirty) {
2459                 int nvres;
2460                 int gop_size;
2461                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2462                         nvres = 480;
2463                         gop_size = 15;
2464                 } else {
2465                         nvres = 576;
2466                         gop_size = 12;
2467                 }
2468                 /* Rewrite the vertical resolution to be appropriate to the
2469                    video standard that has been selected. */
2470                 if (nvres != hdw->res_ver_val) {
2471                         hdw->res_ver_val = nvres;
2472                         hdw->res_ver_dirty = !0;
2473                 }
2474                 /* Rewrite the GOP size to be appropriate to the video
2475                    standard that has been selected. */
2476                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
2477                         struct v4l2_ext_controls cs;
2478                         struct v4l2_ext_control c1;
2479                         memset(&cs, 0, sizeof(cs));
2480                         memset(&c1, 0, sizeof(c1));
2481                         cs.controls = &c1;
2482                         cs.count = 1;
2483                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
2484                         c1.value = gop_size;
2485                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
2486                                           VIDIOC_S_EXT_CTRLS);
2487                 }
2488         }
2489
2490         if (hdw->input_dirty && hdw->state_pathway_ok &&
2491             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
2492               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
2493              hdw->pathway_state)) {
2494                 /* Change of mode being asked for... */
2495                 hdw->state_pathway_ok = 0;
2496                 trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
2497         }
2498         if (!hdw->state_pathway_ok) {
2499                 /* Can't commit anything until pathway is ok. */
2500                 return 0;
2501         }
2502         /* If any of the below has changed, then we can't do the update
2503            while the pipeline is running.  Pipeline must be paused first
2504            and decoder -> encoder connection be made quiescent before we
2505            can proceed. */
2506         disruptive_change =
2507                 (hdw->std_dirty ||
2508                  hdw->enc_unsafe_stale ||
2509                  hdw->srate_dirty ||
2510                  hdw->res_ver_dirty ||
2511                  hdw->res_hor_dirty ||
2512                  hdw->input_dirty ||
2513                  (hdw->active_stream_type != hdw->desired_stream_type));
2514         if (disruptive_change && !hdw->state_pipeline_idle) {
2515                 /* Pipeline is not idle; we can't proceed.  Arrange to
2516                    cause pipeline to stop so that we can try this again
2517                    later.... */
2518                 hdw->state_pipeline_pause = !0;
2519                 return 0;
2520         }
2521
2522         if (hdw->srate_dirty) {
2523                 /* Write new sample rate into control structure since
2524                  * the master copy is stale.  We must track srate
2525                  * separate from the mpeg control structure because
2526                  * other logic also uses this value. */
2527                 struct v4l2_ext_controls cs;
2528                 struct v4l2_ext_control c1;
2529                 memset(&cs,0,sizeof(cs));
2530                 memset(&c1,0,sizeof(c1));
2531                 cs.controls = &c1;
2532                 cs.count = 1;
2533                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2534                 c1.value = hdw->srate_val;
2535                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2536         }
2537
2538         /* Scan i2c core at this point - before we clear all the dirty
2539            bits.  Various parts of the i2c core will notice dirty bits as
2540            appropriate and arrange to broadcast or directly send updates to
2541            the client drivers in order to keep everything in sync */
2542         pvr2_i2c_core_check_stale(hdw);
2543
2544         for (idx = 0; idx < hdw->control_cnt; idx++) {
2545                 cptr = hdw->controls + idx;
2546                 if (!cptr->info->clear_dirty) continue;
2547                 cptr->info->clear_dirty(cptr);
2548         }
2549
2550         if (hdw->active_stream_type != hdw->desired_stream_type) {
2551                 /* Handle any side effects of stream config here */
2552                 hdw->active_stream_type = hdw->desired_stream_type;
2553         }
2554
2555         if (hdw->hdw_desc->signal_routing_scheme ==
2556             PVR2_ROUTING_SCHEME_GOTVIEW) {
2557                 u32 b;
2558                 /* Handle GOTVIEW audio switching */
2559                 pvr2_hdw_gpio_get_out(hdw,&b);
2560                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2561                         /* Set GPIO 11 */
2562                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
2563                 } else {
2564                         /* Clear GPIO 11 */
2565                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
2566                 }
2567         }
2568
2569         /* Now execute i2c core update */
2570         pvr2_i2c_core_sync(hdw);
2571
2572         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
2573             hdw->state_encoder_run) {
2574                 /* If encoder isn't running or it can't be touched, then
2575                    this will get worked out later when we start the
2576                    encoder. */
2577                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2578         }
2579
2580         hdw->state_pipeline_config = !0;
2581         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2582         return !0;
2583 }
2584
2585
2586 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2587 {
2588         int fl;
2589         LOCK_TAKE(hdw->big_lock);
2590         fl = pvr2_hdw_commit_setup(hdw);
2591         LOCK_GIVE(hdw->big_lock);
2592         if (!fl) return 0;
2593         return pvr2_hdw_wait(hdw,0);
2594 }
2595
2596
2597 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2598 {
2599         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2600         LOCK_TAKE(hdw->big_lock); do {
2601                 pvr2_i2c_core_sync(hdw);
2602         } while (0); LOCK_GIVE(hdw->big_lock);
2603 }
2604
2605
2606 static void pvr2_hdw_worker_poll(struct work_struct *work)
2607 {
2608         int fl = 0;
2609         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2610         LOCK_TAKE(hdw->big_lock); do {
2611                 fl = pvr2_hdw_state_eval(hdw);
2612         } while (0); LOCK_GIVE(hdw->big_lock);
2613         if (fl && hdw->state_func) {
2614                 hdw->state_func(hdw->state_data);
2615         }
2616 }
2617
2618
2619 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2620 {
2621         return wait_event_interruptible(
2622                 hdw->state_wait_data,
2623                 (hdw->state_stale == 0) &&
2624                 (!state || (hdw->master_state != state)));
2625 }
2626
2627
2628 /* Return name for this driver instance */
2629 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2630 {
2631         return hdw->name;
2632 }
2633
2634
2635 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2636 {
2637         return hdw->hdw_desc->description;
2638 }
2639
2640
2641 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2642 {
2643         return hdw->hdw_desc->shortname;
2644 }
2645
2646
2647 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2648 {
2649         int result;
2650         LOCK_TAKE(hdw->ctl_lock); do {
2651                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2652                 result = pvr2_send_request(hdw,
2653                                            hdw->cmd_buffer,1,
2654                                            hdw->cmd_buffer,1);
2655                 if (result < 0) break;
2656                 result = (hdw->cmd_buffer[0] != 0);
2657         } while(0); LOCK_GIVE(hdw->ctl_lock);
2658         return result;
2659 }
2660
2661
2662 /* Execute poll of tuner status */
2663 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2664 {
2665         LOCK_TAKE(hdw->big_lock); do {
2666                 pvr2_i2c_core_status_poll(hdw);
2667         } while (0); LOCK_GIVE(hdw->big_lock);
2668 }
2669
2670
2671 /* Return information about the tuner */
2672 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2673 {
2674         LOCK_TAKE(hdw->big_lock); do {
2675                 if (hdw->tuner_signal_stale) {
2676                         pvr2_i2c_core_status_poll(hdw);
2677                 }
2678                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2679         } while (0); LOCK_GIVE(hdw->big_lock);
2680         return 0;
2681 }
2682
2683
2684 /* Get handle to video output stream */
2685 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2686 {
2687         return hp->vid_stream;
2688 }
2689
2690
2691 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2692 {
2693         int nr = pvr2_hdw_get_unit_number(hdw);
2694         LOCK_TAKE(hdw->big_lock); do {
2695                 hdw->log_requested = !0;
2696                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
2697                 pvr2_i2c_core_check_stale(hdw);
2698                 hdw->log_requested = 0;
2699                 pvr2_i2c_core_sync(hdw);
2700                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2701                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2702                 pvr2_hdw_state_log_state(hdw);
2703                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
2704         } while (0); LOCK_GIVE(hdw->big_lock);
2705 }
2706
2707
2708 /* Grab EEPROM contents, needed for direct method. */
2709 #define EEPROM_SIZE 8192
2710 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2711 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2712 {
2713         struct i2c_msg msg[2];
2714         u8 *eeprom;
2715         u8 iadd[2];
2716         u8 addr;
2717         u16 eepromSize;
2718         unsigned int offs;
2719         int ret;
2720         int mode16 = 0;
2721         unsigned pcnt,tcnt;
2722         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2723         if (!eeprom) {
2724                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2725                            "Failed to allocate memory"
2726                            " required to read eeprom");
2727                 return NULL;
2728         }
2729
2730         trace_eeprom("Value for eeprom addr from controller was 0x%x",
2731                      hdw->eeprom_addr);
2732         addr = hdw->eeprom_addr;
2733         /* Seems that if the high bit is set, then the *real* eeprom
2734            address is shifted right now bit position (noticed this in
2735            newer PVR USB2 hardware) */
2736         if (addr & 0x80) addr >>= 1;
2737
2738         /* FX2 documentation states that a 16bit-addressed eeprom is
2739            expected if the I2C address is an odd number (yeah, this is
2740            strange but it's what they do) */
2741         mode16 = (addr & 1);
2742         eepromSize = (mode16 ? EEPROM_SIZE : 256);
2743         trace_eeprom("Examining %d byte eeprom at location 0x%x"
2744                      " using %d bit addressing",eepromSize,addr,
2745                      mode16 ? 16 : 8);
2746
2747         msg[0].addr = addr;
2748         msg[0].flags = 0;
2749         msg[0].len = mode16 ? 2 : 1;
2750         msg[0].buf = iadd;
2751         msg[1].addr = addr;
2752         msg[1].flags = I2C_M_RD;
2753
2754         /* We have to do the actual eeprom data fetch ourselves, because
2755            (1) we're only fetching part of the eeprom, and (2) if we were
2756            getting the whole thing our I2C driver can't grab it in one
2757            pass - which is what tveeprom is otherwise going to attempt */
2758         memset(eeprom,0,EEPROM_SIZE);
2759         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2760                 pcnt = 16;
2761                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2762                 offs = tcnt + (eepromSize - EEPROM_SIZE);
2763                 if (mode16) {
2764                         iadd[0] = offs >> 8;
2765                         iadd[1] = offs;
2766                 } else {
2767                         iadd[0] = offs;
2768                 }
2769                 msg[1].len = pcnt;
2770                 msg[1].buf = eeprom+tcnt;
2771                 if ((ret = i2c_transfer(&hdw->i2c_adap,
2772                                         msg,ARRAY_SIZE(msg))) != 2) {
2773                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2774                                    "eeprom fetch set offs err=%d",ret);
2775                         kfree(eeprom);
2776                         return NULL;
2777                 }
2778         }
2779         return eeprom;
2780 }
2781
2782
2783 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2784                                 int prom_flag,
2785                                 int enable_flag)
2786 {
2787         int ret;
2788         u16 address;
2789         unsigned int pipe;
2790         LOCK_TAKE(hdw->big_lock); do {
2791                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
2792
2793                 if (!enable_flag) {
2794                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2795                                    "Cleaning up after CPU firmware fetch");
2796                         kfree(hdw->fw_buffer);
2797                         hdw->fw_buffer = NULL;
2798                         hdw->fw_size = 0;
2799                         if (hdw->fw_cpu_flag) {
2800                                 /* Now release the CPU.  It will disconnect
2801                                    and reconnect later. */
2802                                 pvr2_hdw_cpureset_assert(hdw,0);
2803                         }
2804                         break;
2805                 }
2806
2807                 hdw->fw_cpu_flag = (prom_flag == 0);
2808                 if (hdw->fw_cpu_flag) {
2809                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2810                                    "Preparing to suck out CPU firmware");
2811                         hdw->fw_size = 0x2000;
2812                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2813                         if (!hdw->fw_buffer) {
2814                                 hdw->fw_size = 0;
2815                                 break;
2816                         }
2817
2818                         /* We have to hold the CPU during firmware upload. */
2819                         pvr2_hdw_cpureset_assert(hdw,1);
2820
2821                         /* download the firmware from address 0000-1fff in 2048
2822                            (=0x800) bytes chunk. */
2823
2824                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2825                                    "Grabbing CPU firmware");
2826                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2827                         for(address = 0; address < hdw->fw_size;
2828                             address += 0x800) {
2829                                 ret = usb_control_msg(hdw->usb_dev,pipe,
2830                                                       0xa0,0xc0,
2831                                                       address,0,
2832                                                       hdw->fw_buffer+address,
2833                                                       0x800,HZ);
2834                                 if (ret < 0) break;
2835                         }
2836
2837                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2838                                    "Done grabbing CPU firmware");
2839                 } else {
2840                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2841                                    "Sucking down EEPROM contents");
2842                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2843                         if (!hdw->fw_buffer) {
2844                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2845                                            "EEPROM content suck failed.");
2846                                 break;
2847                         }
2848                         hdw->fw_size = EEPROM_SIZE;
2849                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2850                                    "Done sucking down EEPROM contents");
2851                 }
2852
2853         } while (0); LOCK_GIVE(hdw->big_lock);
2854 }
2855
2856
2857 /* Return true if we're in a mode for retrieval CPU firmware */
2858 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2859 {
2860         return hdw->fw_buffer != NULL;
2861 }
2862
2863
2864 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2865                        char *buf,unsigned int cnt)
2866 {
2867         int ret = -EINVAL;
2868         LOCK_TAKE(hdw->big_lock); do {
2869                 if (!buf) break;
2870                 if (!cnt) break;
2871
2872                 if (!hdw->fw_buffer) {
2873                         ret = -EIO;
2874                         break;
2875                 }
2876
2877                 if (offs >= hdw->fw_size) {
2878                         pvr2_trace(PVR2_TRACE_FIRMWARE,
2879                                    "Read firmware data offs=%d EOF",
2880                                    offs);
2881                         ret = 0;
2882                         break;
2883                 }
2884
2885                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2886
2887                 memcpy(buf,hdw->fw_buffer+offs,cnt);
2888
2889                 pvr2_trace(PVR2_TRACE_FIRMWARE,
2890                            "Read firmware data offs=%d cnt=%d",
2891                            offs,cnt);
2892                 ret = cnt;
2893         } while (0); LOCK_GIVE(hdw->big_lock);
2894
2895         return ret;
2896 }
2897
2898
2899 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2900                                   enum pvr2_v4l_type index)
2901 {
2902         switch (index) {
2903         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2904         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2905         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2906         default: return -1;
2907         }
2908 }
2909
2910
2911 /* Store a v4l minor device number */
2912 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2913                                      enum pvr2_v4l_type index,int v)
2914 {
2915         switch (index) {
2916         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2917         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2918         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2919         default: break;
2920         }
2921 }
2922
2923
2924 static void pvr2_ctl_write_complete(struct urb *urb)
2925 {
2926         struct pvr2_hdw *hdw = urb->context;
2927         hdw->ctl_write_pend_flag = 0;
2928         if (hdw->ctl_read_pend_flag) return;
2929         complete(&hdw->ctl_done);
2930 }
2931
2932
2933 static void pvr2_ctl_read_complete(struct urb *urb)
2934 {
2935         struct pvr2_hdw *hdw = urb->context;
2936         hdw->ctl_read_pend_flag = 0;
2937         if (hdw->ctl_write_pend_flag) return;
2938         complete(&hdw->ctl_done);
2939 }
2940
2941
2942 static void pvr2_ctl_timeout(unsigned long data)
2943 {
2944         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2945         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2946                 hdw->ctl_timeout_flag = !0;
2947                 if (hdw->ctl_write_pend_flag)
2948                         usb_unlink_urb(hdw->ctl_write_urb);
2949                 if (hdw->ctl_read_pend_flag)
2950                         usb_unlink_urb(hdw->ctl_read_urb);
2951         }
2952 }
2953
2954
2955 /* Issue a command and get a response from the device.  This extended
2956    version includes a probe flag (which if set means that device errors
2957    should not be logged or treated as fatal) and a timeout in jiffies.
2958    This can be used to non-lethally probe the health of endpoint 1. */
2959 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2960                                 unsigned int timeout,int probe_fl,
2961                                 void *write_data,unsigned int write_len,
2962                                 void *read_data,unsigned int read_len)
2963 {
2964         unsigned int idx;
2965         int status = 0;
2966         struct timer_list timer;
2967         if (!hdw->ctl_lock_held) {
2968                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2969                            "Attempted to execute control transfer"
2970                            " without lock!!");
2971                 return -EDEADLK;
2972         }
2973         if (!hdw->flag_ok && !probe_fl) {
2974                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2975                            "Attempted to execute control transfer"
2976                            " when device not ok");
2977                 return -EIO;
2978         }
2979         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2980                 if (!probe_fl) {
2981                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2982                                    "Attempted to execute control transfer"
2983                                    " when USB is disconnected");
2984                 }
2985                 return -ENOTTY;
2986         }
2987
2988         /* Ensure that we have sane parameters */
2989         if (!write_data) write_len = 0;
2990         if (!read_data) read_len = 0;
2991         if (write_len > PVR2_CTL_BUFFSIZE) {
2992                 pvr2_trace(
2993                         PVR2_TRACE_ERROR_LEGS,
2994                         "Attempted to execute %d byte"
2995                         " control-write transfer (limit=%d)",
2996                         write_len,PVR2_CTL_BUFFSIZE);
2997                 return -EINVAL;
2998         }
2999         if (read_len > PVR2_CTL_BUFFSIZE) {
3000                 pvr2_trace(
3001                         PVR2_TRACE_ERROR_LEGS,
3002                         "Attempted to execute %d byte"
3003                         " control-read transfer (limit=%d)",
3004                         write_len,PVR2_CTL_BUFFSIZE);
3005                 return -EINVAL;
3006         }
3007         if ((!write_len) && (!read_len)) {
3008                 pvr2_trace(
3009                         PVR2_TRACE_ERROR_LEGS,
3010                         "Attempted to execute null control transfer?");
3011                 return -EINVAL;
3012         }
3013
3014
3015         hdw->cmd_debug_state = 1;
3016         if (write_len) {
3017                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3018         } else {
3019                 hdw->cmd_debug_code = 0;
3020         }
3021         hdw->cmd_debug_write_len = write_len;
3022         hdw->cmd_debug_read_len = read_len;
3023
3024         /* Initialize common stuff */
3025         init_completion(&hdw->ctl_done);
3026         hdw->ctl_timeout_flag = 0;
3027         hdw->ctl_write_pend_flag = 0;
3028         hdw->ctl_read_pend_flag = 0;
3029         init_timer(&timer);
3030         timer.expires = jiffies + timeout;
3031         timer.data = (unsigned long)hdw;
3032         timer.function = pvr2_ctl_timeout;
3033
3034         if (write_len) {
3035                 hdw->cmd_debug_state = 2;
3036                 /* Transfer write data to internal buffer */
3037                 for (idx = 0; idx < write_len; idx++) {
3038                         hdw->ctl_write_buffer[idx] =
3039                                 ((unsigned char *)write_data)[idx];
3040                 }
3041                 /* Initiate a write request */
3042                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3043                                   hdw->usb_dev,
3044                                   usb_sndbulkpipe(hdw->usb_dev,
3045                                                   PVR2_CTL_WRITE_ENDPOINT),
3046                                   hdw->ctl_write_buffer,
3047                                   write_len,
3048                                   pvr2_ctl_write_complete,
3049                                   hdw);
3050                 hdw->ctl_write_urb->actual_length = 0;
3051                 hdw->ctl_write_pend_flag = !0;
3052                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3053                 if (status < 0) {
3054                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3055                                    "Failed to submit write-control"
3056                                    " URB status=%d",status);
3057                         hdw->ctl_write_pend_flag = 0;
3058                         goto done;
3059                 }
3060         }
3061
3062         if (read_len) {
3063                 hdw->cmd_debug_state = 3;
3064                 memset(hdw->ctl_read_buffer,0x43,read_len);
3065                 /* Initiate a read request */
3066                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3067                                   hdw->usb_dev,
3068                                   usb_rcvbulkpipe(hdw->usb_dev,
3069                                                   PVR2_CTL_READ_ENDPOINT),
3070                                   hdw->ctl_read_buffer,
3071                                   read_len,
3072                                   pvr2_ctl_read_complete,
3073                                   hdw);
3074                 hdw->ctl_read_urb->actual_length = 0;
3075                 hdw->ctl_read_pend_flag = !0;
3076                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3077                 if (status < 0) {
3078                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3079                                    "Failed to submit read-control"
3080                                    " URB status=%d",status);
3081                         hdw->ctl_read_pend_flag = 0;
3082                         goto done;
3083                 }
3084         }
3085
3086         /* Start timer */
3087         add_timer(&timer);
3088
3089         /* Now wait for all I/O to complete */
3090         hdw->cmd_debug_state = 4;
3091         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3092                 wait_for_completion(&hdw->ctl_done);
3093         }
3094         hdw->cmd_debug_state = 5;
3095
3096         /* Stop timer */
3097         del_timer_sync(&timer);
3098
3099         hdw->cmd_debug_state = 6;
3100         status = 0;
3101
3102         if (hdw->ctl_timeout_flag) {
3103                 status = -ETIMEDOUT;
3104                 if (!probe_fl) {
3105                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3106                                    "Timed out control-write");
3107                 }
3108                 goto done;
3109         }
3110
3111         if (write_len) {
3112                 /* Validate results of write request */
3113                 if ((hdw->ctl_write_urb->status != 0) &&
3114                     (hdw->ctl_write_urb->status != -ENOENT) &&
3115                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3116                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3117                         /* USB subsystem is reporting some kind of failure
3118                            on the write */
3119                         status = hdw->ctl_write_urb->status;
3120                         if (!probe_fl) {
3121                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3122                                            "control-write URB failure,"
3123                                            " status=%d",
3124                                            status);
3125                         }
3126                         goto done;
3127                 }
3128                 if (hdw->ctl_write_urb->actual_length < write_len) {
3129                         /* Failed to write enough data */
3130                         status = -EIO;
3131                         if (!probe_fl) {
3132                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3133                                            "control-write URB short,"
3134                                            " expected=%d got=%d",
3135                                            write_len,
3136                                            hdw->ctl_write_urb->actual_length);
3137                         }
3138                         goto done;
3139                 }
3140         }
3141         if (read_len) {
3142                 /* Validate results of read request */
3143                 if ((hdw->ctl_read_urb->status != 0) &&
3144                     (hdw->ctl_read_urb->status != -ENOENT) &&
3145                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3146                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3147                         /* USB subsystem is reporting some kind of failure
3148                            on the read */
3149                         status = hdw->ctl_read_urb->status;
3150                         if (!probe_fl) {
3151                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3152                                            "control-read URB failure,"
3153                                            " status=%d",
3154                                            status);
3155                         }
3156                         goto done;
3157                 }
3158                 if (hdw->ctl_read_urb->actual_length < read_len) {
3159                         /* Failed to read enough data */
3160                         status = -EIO;
3161                         if (!probe_fl) {
3162                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3163                                            "control-read URB short,"
3164                                            " expected=%d got=%d",
3165                                            read_len,
3166                                            hdw->ctl_read_urb->actual_length);
3167                         }
3168                         goto done;
3169                 }
3170                 /* Transfer retrieved data out from internal buffer */
3171                 for (idx = 0; idx < read_len; idx++) {
3172                         ((unsigned char *)read_data)[idx] =
3173                                 hdw->ctl_read_buffer[idx];
3174                 }
3175         }
3176
3177  done:
3178
3179         hdw->cmd_debug_state = 0;
3180         if ((status < 0) && (!probe_fl)) {
3181                 pvr2_hdw_render_useless(hdw);
3182         }
3183         return status;
3184 }
3185
3186
3187 int pvr2_send_request(struct pvr2_hdw *hdw,
3188                       void *write_data,unsigned int write_len,
3189                       void *read_data,unsigned int read_len)
3190 {
3191         return pvr2_send_request_ex(hdw,HZ*4,0,
3192                                     write_data,write_len,
3193                                     read_data,read_len);
3194 }
3195
3196
3197 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3198 {
3199         int ret;
3200         unsigned int cnt = 1;
3201         unsigned int args = 0;
3202         LOCK_TAKE(hdw->ctl_lock);
3203         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3204         args = (cmdcode >> 8) & 0xffu;
3205         args = (args > 2) ? 2 : args;
3206         if (args) {
3207                 cnt += args;
3208                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3209                 if (args > 1) {
3210                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3211                 }
3212         }
3213         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3214                 unsigned int idx;
3215                 unsigned int ccnt,bcnt;
3216                 char tbuf[50];
3217                 cmdcode &= 0xffu;
3218                 bcnt = 0;
3219                 ccnt = scnprintf(tbuf+bcnt,
3220                                  sizeof(tbuf)-bcnt,
3221                                  "Sending FX2 command 0x%x",cmdcode);
3222                 bcnt += ccnt;
3223                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3224                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3225                                 ccnt = scnprintf(tbuf+bcnt,
3226                                                  sizeof(tbuf)-bcnt,
3227                                                  " \"%s\"",
3228                                                  pvr2_fx2cmd_desc[idx].desc);
3229                                 bcnt += ccnt;
3230                                 break;
3231                         }
3232                 }
3233                 if (args) {
3234                         ccnt = scnprintf(tbuf+bcnt,
3235                                          sizeof(tbuf)-bcnt,
3236                                          " (%u",hdw->cmd_buffer[1]);
3237                         bcnt += ccnt;
3238                         if (args > 1) {
3239                                 ccnt = scnprintf(tbuf+bcnt,
3240                                                  sizeof(tbuf)-bcnt,
3241                                                  ",%u",hdw->cmd_buffer[2]);
3242                                 bcnt += ccnt;
3243                         }
3244                         ccnt = scnprintf(tbuf+bcnt,
3245                                          sizeof(tbuf)-bcnt,
3246                                          ")");
3247                         bcnt += ccnt;
3248                 }
3249                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3250         }
3251         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3252         LOCK_GIVE(hdw->ctl_lock);
3253         return ret;
3254 }
3255
3256
3257 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3258 {
3259         int ret;
3260
3261         LOCK_TAKE(hdw->ctl_lock);
3262
3263         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3264         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3265         hdw->cmd_buffer[5] = 0;
3266         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3267         hdw->cmd_buffer[7] = reg & 0xff;
3268
3269
3270         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3271
3272         LOCK_GIVE(hdw->ctl_lock);
3273
3274         return ret;
3275 }
3276
3277
3278 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3279 {
3280         int ret = 0;
3281
3282         LOCK_TAKE(hdw->ctl_lock);
3283
3284         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3285         hdw->cmd_buffer[1] = 0;
3286         hdw->cmd_buffer[2] = 0;
3287         hdw->cmd_buffer[3] = 0;
3288         hdw->cmd_buffer[4] = 0;
3289         hdw->cmd_buffer[5] = 0;
3290         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3291         hdw->cmd_buffer[7] = reg & 0xff;
3292
3293         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3294         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3295
3296         LOCK_GIVE(hdw->ctl_lock);
3297
3298         return ret;
3299 }
3300
3301
3302 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3303 {
3304         if (!hdw->flag_ok) return;
3305         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3306                    "Device being rendered inoperable");
3307         if (hdw->vid_stream) {
3308                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3309         }
3310         hdw->flag_ok = 0;
3311         trace_stbit("flag_ok",hdw->flag_ok);
3312         pvr2_hdw_state_sched(hdw);
3313 }
3314
3315
3316 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3317 {
3318         int ret;
3319         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3320         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3321         if (ret == 1) {
3322                 ret = usb_reset_device(hdw->usb_dev);
3323                 usb_unlock_device(hdw->usb_dev);
3324         } else {
3325                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3326                            "Failed to lock USB device ret=%d",ret);
3327         }
3328         if (init_pause_msec) {
3329                 pvr2_trace(PVR2_TRACE_INFO,
3330                            "Waiting %u msec for hardware to settle",
3331                            init_pause_msec);
3332                 msleep(init_pause_msec);
3333         }
3334
3335 }
3336
3337
3338 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3339 {
3340         char da[1];
3341         unsigned int pipe;
3342         int ret;
3343
3344         if (!hdw->usb_dev) return;
3345
3346         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3347
3348         da[0] = val ? 0x01 : 0x00;
3349
3350         /* Write the CPUCS register on the 8051.  The lsb of the register
3351            is the reset bit; a 1 asserts reset while a 0 clears it. */
3352         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3353         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3354         if (ret < 0) {
3355                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3356                            "cpureset_assert(%d) error=%d",val,ret);
3357                 pvr2_hdw_render_useless(hdw);
3358         }
3359 }
3360
3361
3362 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3363 {
3364         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3365 }
3366
3367
3368 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3369 {
3370         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3371 }
3372
3373
3374 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
3375 {
3376         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
3377 }
3378
3379
3380 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3381 {
3382         if (!hdw->decoder_ctrl) {
3383                 pvr2_trace(PVR2_TRACE_INIT,
3384                            "Unable to reset decoder: nothing attached");
3385                 return -ENOTTY;
3386         }
3387
3388         if (!hdw->decoder_ctrl->force_reset) {
3389                 pvr2_trace(PVR2_TRACE_INIT,
3390                            "Unable to reset decoder: not implemented");
3391                 return -ENOTTY;
3392         }
3393
3394         pvr2_trace(PVR2_TRACE_INIT,
3395                    "Requesting decoder reset");
3396         hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3397         return 0;
3398 }
3399
3400
3401 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
3402 {
3403         hdw->flag_ok = !0;
3404         return pvr2_issue_simple_cmd(hdw,
3405                                      FX2CMD_HCW_DEMOD_RESETIN |
3406                                      (1 << 8) |
3407                                      ((onoff ? 1 : 0) << 16));
3408 }
3409
3410
3411 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
3412 {
3413         hdw->flag_ok = !0;
3414         return pvr2_issue_simple_cmd(hdw,(onoff ?
3415                                           FX2CMD_ONAIR_DTV_POWER_ON :
3416                                           FX2CMD_ONAIR_DTV_POWER_OFF));
3417 }
3418
3419
3420 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
3421                                                 int onoff)
3422 {
3423         return pvr2_issue_simple_cmd(hdw,(onoff ?
3424                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
3425                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
3426 }
3427
3428
3429 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
3430 {
3431         int cmode;
3432         /* Compare digital/analog desired setting with current setting.  If
3433            they don't match, fix it... */
3434         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
3435         if (cmode == hdw->pathway_state) {
3436                 /* They match; nothing to do */
3437                 return;
3438         }
3439
3440         switch (hdw->hdw_desc->digital_control_scheme) {
3441         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3442                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
3443                 if (cmode == PVR2_PATHWAY_ANALOG) {
3444                         /* If moving to analog mode, also force the decoder
3445                            to reset.  If no decoder is attached, then it's
3446                            ok to ignore this because if/when the decoder
3447                            attaches, it will reset itself at that time. */
3448                         pvr2_hdw_cmd_decoder_reset(hdw);
3449                 }
3450                 break;
3451         case PVR2_DIGITAL_SCHEME_ONAIR:
3452                 /* Supposedly we should always have the power on whether in
3453                    digital or analog mode.  But for now do what appears to
3454                    work... */
3455                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
3456                 break;
3457         default: break;
3458         }
3459
3460         pvr2_hdw_untrip_unlocked(hdw);
3461         hdw->pathway_state = cmode;
3462 }
3463
3464
3465 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
3466 {
3467         /* change some GPIO data
3468          *
3469          * note: bit d7 of dir appears to control the LED,
3470          * so we shut it off here.
3471          *
3472          */
3473         if (onoff) {
3474                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
3475         } else {
3476                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
3477         }
3478         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
3479 }
3480
3481
3482 typedef void (*led_method_func)(struct pvr2_hdw *,int);
3483
3484 static led_method_func led_methods[] = {
3485         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
3486 };
3487
3488
3489 /* Toggle LED */
3490 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
3491 {
3492         unsigned int scheme_id;
3493         led_method_func fp;
3494
3495         if ((!onoff) == (!hdw->led_on)) return;
3496
3497         hdw->led_on = onoff != 0;
3498
3499         scheme_id = hdw->hdw_desc->led_scheme;
3500         if (scheme_id < ARRAY_SIZE(led_methods)) {
3501                 fp = led_methods[scheme_id];
3502         } else {
3503                 fp = NULL;
3504         }
3505
3506         if (fp) (*fp)(hdw,onoff);
3507 }
3508
3509
3510 /* Stop / start video stream transport */
3511 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3512 {
3513         int ret;
3514
3515         /* If we're in analog mode, then just issue the usual analog
3516            command. */
3517         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3518                 return pvr2_issue_simple_cmd(hdw,
3519                                              (runFl ?
3520                                               FX2CMD_STREAMING_ON :
3521                                               FX2CMD_STREAMING_OFF));
3522                 /*Note: Not reached */
3523         }
3524
3525         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
3526                 /* Whoops, we don't know what mode we're in... */
3527                 return -EINVAL;
3528         }
3529
3530         /* To get here we have to be in digital mode.  The mechanism here
3531            is unfortunately different for different vendors.  So we switch
3532            on the device's digital scheme attribute in order to figure out
3533            what to do. */
3534         switch (hdw->hdw_desc->digital_control_scheme) {
3535         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
3536                 return pvr2_issue_simple_cmd(hdw,
3537                                              (runFl ?
3538                                               FX2CMD_HCW_DTV_STREAMING_ON :
3539                                               FX2CMD_HCW_DTV_STREAMING_OFF));
3540         case PVR2_DIGITAL_SCHEME_ONAIR:
3541                 ret = pvr2_issue_simple_cmd(hdw,
3542                                             (runFl ?
3543                                              FX2CMD_STREAMING_ON :
3544                                              FX2CMD_STREAMING_OFF));
3545                 if (ret) return ret;
3546                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
3547         default:
3548                 return -EINVAL;
3549         }
3550 }
3551
3552
3553 /* Evaluate whether or not state_pathway_ok can change */
3554 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
3555 {
3556         if (hdw->state_pathway_ok) {
3557                 /* Nothing to do if pathway is already ok */
3558                 return 0;
3559         }
3560         if (!hdw->state_pipeline_idle) {
3561                 /* Not allowed to change anything if pipeline is not idle */
3562                 return 0;
3563         }
3564         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
3565         hdw->state_pathway_ok = !0;
3566         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
3567         return !0;
3568 }
3569
3570
3571 /* Evaluate whether or not state_encoder_ok can change */
3572 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3573 {
3574         if (hdw->state_encoder_ok) return 0;
3575         if (hdw->flag_tripped) return 0;
3576         if (hdw->state_encoder_run) return 0;
3577         if (hdw->state_encoder_config) return 0;
3578         if (hdw->state_decoder_run) return 0;
3579         if (hdw->state_usbstream_run) return 0;
3580         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
3581                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
3582         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
3583                 return 0;
3584         }
3585
3586         if (pvr2_upload_firmware2(hdw) < 0) {
3587                 hdw->flag_tripped = !0;
3588                 trace_stbit("flag_tripped",hdw->flag_tripped);
3589                 return !0;
3590         }
3591         hdw->state_encoder_ok = !0;
3592         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3593         return !0;
3594 }
3595
3596
3597 /* Evaluate whether or not state_encoder_config can change */
3598 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3599 {
3600         if (hdw->state_encoder_config) {
3601                 if (hdw->state_encoder_ok) {
3602                         if (hdw->state_pipeline_req &&
3603                             !hdw->state_pipeline_pause) return 0;
3604                 }
3605                 hdw->state_encoder_config = 0;
3606                 hdw->state_encoder_waitok = 0;
3607                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3608                 /* paranoia - solve race if timer just completed */
3609                 del_timer_sync(&hdw->encoder_wait_timer);
3610         } else {
3611                 if (!hdw->state_pathway_ok ||
3612                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3613                     !hdw->state_encoder_ok ||
3614                     !hdw->state_pipeline_idle ||
3615                     hdw->state_pipeline_pause ||
3616                     !hdw->state_pipeline_req ||
3617                     !hdw->state_pipeline_config) {
3618                         /* We must reset the enforced wait interval if
3619                            anything has happened that might have disturbed
3620                            the encoder.  This should be a rare case. */
3621                         if (timer_pending(&hdw->encoder_wait_timer)) {
3622                                 del_timer_sync(&hdw->encoder_wait_timer);
3623                         }
3624                         if (hdw->state_encoder_waitok) {
3625                                 /* Must clear the state - therefore we did
3626                                    something to a state bit and must also
3627                                    return true. */
3628                                 hdw->state_encoder_waitok = 0;
3629                                 trace_stbit("state_encoder_waitok",
3630                                             hdw->state_encoder_waitok);
3631                                 return !0;
3632                         }
3633                         return 0;
3634                 }
3635                 if (!hdw->state_encoder_waitok) {
3636                         if (!timer_pending(&hdw->encoder_wait_timer)) {
3637                                 /* waitok flag wasn't set and timer isn't
3638                                    running.  Check flag once more to avoid
3639                                    a race then start the timer.  This is
3640                                    the point when we measure out a minimal
3641                                    quiet interval before doing something to
3642                                    the encoder. */
3643                                 if (!hdw->state_encoder_waitok) {
3644                                         hdw->encoder_wait_timer.expires =
3645                                                 jiffies +
3646                                                 (HZ * TIME_MSEC_ENCODER_WAIT
3647                                                  / 1000);
3648                                         add_timer(&hdw->encoder_wait_timer);
3649                                 }
3650                         }
3651                         /* We can't continue until we know we have been
3652                            quiet for the interval measured by this
3653                            timer. */
3654                         return 0;
3655                 }
3656                 pvr2_encoder_configure(hdw);
3657                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3658         }
3659         trace_stbit("state_encoder_config",hdw->state_encoder_config);
3660         return !0;
3661 }
3662
3663
3664 /* Return true if the encoder should not be running. */
3665 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
3666 {
3667         if (!hdw->state_encoder_ok) {
3668                 /* Encoder isn't healthy at the moment, so stop it. */
3669                 return !0;
3670         }
3671         if (!hdw->state_pathway_ok) {
3672                 /* Mode is not understood at the moment (i.e. it wants to
3673                    change), so encoder must be stopped. */
3674                 return !0;
3675         }
3676
3677         switch (hdw->pathway_state) {
3678         case PVR2_PATHWAY_ANALOG:
3679                 if (!hdw->state_decoder_run) {
3680                         /* We're in analog mode and the decoder is not
3681                            running; thus the encoder should be stopped as
3682                            well. */
3683                         return !0;
3684                 }
3685                 break;
3686         case PVR2_PATHWAY_DIGITAL:
3687                 if (hdw->state_encoder_runok) {
3688                         /* This is a funny case.  We're in digital mode so
3689                            really the encoder should be stopped.  However
3690                            if it really is running, only kill it after
3691                            runok has been set.  This gives a chance for the
3692                            onair quirk to function (encoder must run
3693                            briefly first, at least once, before onair
3694                            digital streaming can work). */
3695                         return !0;
3696                 }
3697                 break;
3698         default:
3699                 /* Unknown mode; so encoder should be stopped. */
3700                 return !0;
3701         }
3702
3703         /* If we get here, we haven't found a reason to stop the
3704            encoder. */
3705         return 0;
3706 }
3707
3708
3709 /* Return true if the encoder should be running. */
3710 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
3711 {
3712         if (!hdw->state_encoder_ok) {
3713                 /* Don't run the encoder if it isn't healthy... */
3714                 return 0;
3715         }
3716         if (!hdw->state_pathway_ok) {
3717                 /* Don't run the encoder if we don't (yet) know what mode
3718                    we need to be in... */
3719                 return 0;
3720         }
3721
3722         switch (hdw->pathway_state) {
3723         case PVR2_PATHWAY_ANALOG:
3724                 if (hdw->state_decoder_run) {
3725                         /* In analog mode, if the decoder is running, then
3726                            run the encoder. */
3727                         return !0;
3728                 }
3729                 break;
3730         case PVR2_PATHWAY_DIGITAL:
3731                 if ((hdw->hdw_desc->digital_control_scheme ==
3732                      PVR2_DIGITAL_SCHEME_ONAIR) &&
3733                     !hdw->state_encoder_runok) {
3734                         /* This is a quirk.  OnAir hardware won't stream
3735                            digital until the encoder has been run at least
3736                            once, for a minimal period of time (empiricially
3737                            measured to be 1/4 second).  So if we're on
3738                            OnAir hardware and the encoder has never been
3739                            run at all, then start the encoder.  Normal
3740                            state machine logic in the driver will
3741                            automatically handle the remaining bits. */
3742                         return !0;
3743                 }
3744                 break;
3745         default:
3746                 /* For completeness (unknown mode; encoder won't run ever) */
3747                 break;
3748         }
3749         /* If we get here, then we haven't found any reason to run the
3750            encoder, so don't run it. */
3751         return 0;
3752 }
3753
3754
3755 /* Evaluate whether or not state_encoder_run can change */
3756 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3757 {
3758         if (hdw->state_encoder_run) {
3759                 if (!state_check_disable_encoder_run(hdw)) return 0;
3760                 if (hdw->state_encoder_ok) {
3761                         del_timer_sync(&hdw->encoder_run_timer);
3762                         if (pvr2_encoder_stop(hdw) < 0) return !0;
3763                 }
3764                 hdw->state_encoder_run = 0;
3765         } else {
3766                 if (!state_check_enable_encoder_run(hdw)) return 0;
3767                 if (pvr2_encoder_start(hdw) < 0) return !0;
3768                 hdw->state_encoder_run = !0;
3769                 if (!hdw->state_encoder_runok) {
3770                         hdw->encoder_run_timer.expires =
3771                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
3772                         add_timer(&hdw->encoder_run_timer);
3773                 }
3774         }
3775         trace_stbit("state_encoder_run",hdw->state_encoder_run);
3776         return !0;
3777 }
3778
3779
3780 /* Timeout function for quiescent timer. */
3781 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3782 {
3783         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3784         hdw->state_decoder_quiescent = !0;
3785         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3786         hdw->state_stale = !0;
3787         queue_work(hdw->workqueue,&hdw->workpoll);
3788 }
3789
3790
3791 /* Timeout function for encoder wait timer. */
3792 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3793 {
3794         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3795         hdw->state_encoder_waitok = !0;
3796         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3797         hdw->state_stale = !0;
3798         queue_work(hdw->workqueue,&hdw->workpoll);
3799 }
3800
3801
3802 /* Timeout function for encoder run timer. */
3803 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
3804 {
3805         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3806         if (!hdw->state_encoder_runok) {
3807                 hdw->state_encoder_runok = !0;
3808                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
3809                 hdw->state_stale = !0;
3810                 queue_work(hdw->workqueue,&hdw->workpoll);
3811         }
3812 }
3813
3814
3815 /* Evaluate whether or not state_decoder_run can change */
3816 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3817 {
3818         if (hdw->state_decoder_run) {
3819                 if (hdw->state_encoder_ok) {
3820                         if (hdw->state_pipeline_req &&
3821                             !hdw->state_pipeline_pause &&
3822                             hdw->state_pathway_ok) return 0;
3823                 }
3824                 if (!hdw->flag_decoder_missed) {
3825                         pvr2_decoder_enable(hdw,0);
3826                 }
3827                 hdw->state_decoder_quiescent = 0;
3828                 hdw->state_decoder_run = 0;
3829                 /* paranoia - solve race if timer just completed */
3830                 del_timer_sync(&hdw->quiescent_timer);
3831         } else {
3832                 if (!hdw->state_decoder_quiescent) {
3833                         if (!timer_pending(&hdw->quiescent_timer)) {
3834                                 /* We don't do something about the
3835                                    quiescent timer until right here because
3836                                    we also want to catch cases where the
3837                                    decoder was already not running (like
3838                                    after initialization) as opposed to
3839                                    knowing that we had just stopped it.
3840                                    The second flag check is here to cover a
3841                                    race - the timer could have run and set
3842                                    this flag just after the previous check
3843                                    but before we did the pending check. */
3844                                 if (!hdw->state_decoder_quiescent) {
3845                                         hdw->quiescent_timer.expires =
3846                                                 jiffies +
3847                                                 (HZ * TIME_MSEC_DECODER_WAIT
3848                                                  / 1000);
3849                                         add_timer(&hdw->quiescent_timer);
3850                                 }
3851                         }
3852                         /* Don't allow decoder to start again until it has
3853                            been quiesced first.  This little detail should
3854                            hopefully further stabilize the encoder. */
3855                         return 0;
3856                 }
3857                 if (!hdw->state_pathway_ok ||
3858                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
3859                     !hdw->state_pipeline_req ||
3860                     hdw->state_pipeline_pause ||
3861                     !hdw->state_pipeline_config ||
3862                     !hdw->state_encoder_config ||
3863                     !hdw->state_encoder_ok) return 0;
3864                 del_timer_sync(&hdw->quiescent_timer);
3865                 if (hdw->flag_decoder_missed) return 0;
3866                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3867                 hdw->state_decoder_quiescent = 0;
3868                 hdw->state_decoder_run = !0;
3869         }
3870         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3871         trace_stbit("state_decoder_run",hdw->state_decoder_run);
3872         return !0;
3873 }
3874
3875
3876 /* Evaluate whether or not state_usbstream_run can change */
3877 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3878 {
3879         if (hdw->state_usbstream_run) {
3880                 int fl = !0;
3881                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3882                         fl = (hdw->state_encoder_ok &&
3883                               hdw->state_encoder_run);
3884                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3885                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3886                         fl = hdw->state_encoder_ok;
3887                 }
3888                 if (fl &&
3889                     hdw->state_pipeline_req &&
3890                     !hdw->state_pipeline_pause &&
3891                     hdw->state_pathway_ok) {
3892                         return 0;
3893                 }
3894                 pvr2_hdw_cmd_usbstream(hdw,0);
3895                 hdw->state_usbstream_run = 0;
3896         } else {
3897                 if (!hdw->state_pipeline_req ||
3898                     hdw->state_pipeline_pause ||
3899                     !hdw->state_pathway_ok) return 0;
3900                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
3901                         if (!hdw->state_encoder_ok ||
3902                             !hdw->state_encoder_run) return 0;
3903                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
3904                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
3905                         if (!hdw->state_encoder_ok) return 0;
3906                         if (hdw->state_encoder_run) return 0;
3907                         if (hdw->hdw_desc->digital_control_scheme ==
3908                             PVR2_DIGITAL_SCHEME_ONAIR) {
3909                                 /* OnAir digital receivers won't stream
3910                                    unless the analog encoder has run first.
3911                                    Why?  I have no idea.  But don't even
3912                                    try until we know the analog side is
3913                                    known to have run. */
3914                                 if (!hdw->state_encoder_runok) return 0;
3915                         }
3916                 }
3917                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3918                 hdw->state_usbstream_run = !0;
3919         }
3920         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3921         return !0;
3922 }
3923
3924
3925 /* Attempt to configure pipeline, if needed */
3926 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3927 {
3928         if (hdw->state_pipeline_config ||
3929             hdw->state_pipeline_pause) return 0;
3930         pvr2_hdw_commit_execute(hdw);
3931         return !0;
3932 }
3933
3934
3935 /* Update pipeline idle and pipeline pause tracking states based on other
3936    inputs.  This must be called whenever the other relevant inputs have
3937    changed. */
3938 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3939 {
3940         unsigned int st;
3941         int updatedFl = 0;
3942         /* Update pipeline state */
3943         st = !(hdw->state_encoder_run ||
3944                hdw->state_decoder_run ||
3945                hdw->state_usbstream_run ||
3946                (!hdw->state_decoder_quiescent));
3947         if (!st != !hdw->state_pipeline_idle) {
3948                 hdw->state_pipeline_idle = st;
3949                 updatedFl = !0;
3950         }
3951         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3952                 hdw->state_pipeline_pause = 0;
3953                 updatedFl = !0;
3954         }
3955         return updatedFl;
3956 }
3957
3958
3959 typedef int (*state_eval_func)(struct pvr2_hdw *);
3960
3961 /* Set of functions to be run to evaluate various states in the driver. */
3962 static const state_eval_func eval_funcs[] = {
3963         state_eval_pathway_ok,
3964         state_eval_pipeline_config,
3965         state_eval_encoder_ok,
3966         state_eval_encoder_config,
3967         state_eval_decoder_run,
3968         state_eval_encoder_run,
3969         state_eval_usbstream_run,
3970 };
3971
3972
3973 /* Process various states and return true if we did anything interesting. */
3974 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3975 {
3976         unsigned int i;
3977         int state_updated = 0;
3978         int check_flag;
3979
3980         if (!hdw->state_stale) return 0;
3981         if ((hdw->fw1_state != FW1_STATE_OK) ||
3982             !hdw->flag_ok) {
3983                 hdw->state_stale = 0;
3984                 return !0;
3985         }
3986         /* This loop is the heart of the entire driver.  It keeps trying to
3987            evaluate various bits of driver state until nothing changes for
3988            one full iteration.  Each "bit of state" tracks some global
3989            aspect of the driver, e.g. whether decoder should run, if
3990            pipeline is configured, usb streaming is on, etc.  We separately
3991            evaluate each of those questions based on other driver state to
3992            arrive at the correct running configuration. */
3993         do {
3994                 check_flag = 0;
3995                 state_update_pipeline_state(hdw);
3996                 /* Iterate over each bit of state */
3997                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3998                         if ((*eval_funcs[i])(hdw)) {
3999                                 check_flag = !0;
4000                                 state_updated = !0;
4001                                 state_update_pipeline_state(hdw);
4002                         }
4003                 }
4004         } while (check_flag && hdw->flag_ok);
4005         hdw->state_stale = 0;
4006         trace_stbit("state_stale",hdw->state_stale);
4007         return state_updated;
4008 }
4009
4010
4011 static unsigned int print_input_mask(unsigned int msk,
4012                                      char *buf,unsigned int acnt)
4013 {
4014         unsigned int idx,ccnt;
4015         unsigned int tcnt = 0;
4016         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4017                 if (!((1 << idx) & msk)) continue;
4018                 ccnt = scnprintf(buf+tcnt,
4019                                  acnt-tcnt,
4020                                  "%s%s",
4021                                  (tcnt ? ", " : ""),
4022                                  control_values_input[idx]);
4023                 tcnt += ccnt;
4024         }
4025         return tcnt;
4026 }
4027
4028
4029 static const char *pvr2_pathway_state_name(int id)
4030 {
4031         switch (id) {
4032         case PVR2_PATHWAY_ANALOG: return "analog";
4033         case PVR2_PATHWAY_DIGITAL: return "digital";
4034         default: return "unknown";
4035         }
4036 }
4037
4038
4039 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4040                                              char *buf,unsigned int acnt)
4041 {
4042         switch (which) {
4043         case 0:
4044                 return scnprintf(
4045                         buf,acnt,
4046                         "driver:%s%s%s%s%s <mode=%s>",
4047                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4048                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4049                         (hdw->flag_disconnected ? " <disconnected>" :
4050                          " <connected>"),
4051                         (hdw->flag_tripped ? " <tripped>" : ""),
4052                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4053                         pvr2_pathway_state_name(hdw->pathway_state));
4054
4055         case 1:
4056                 return scnprintf(
4057                         buf,acnt,
4058                         "pipeline:%s%s%s%s",
4059                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4060                         (hdw->state_pipeline_config ?
4061                          " <configok>" : " <stale>"),
4062                         (hdw->state_pipeline_req ? " <req>" : ""),
4063                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4064         case 2:
4065                 return scnprintf(
4066                         buf,acnt,
4067                         "worker:%s%s%s%s%s%s%s",
4068                         (hdw->state_decoder_run ?
4069                          " <decode:run>" :
4070                          (hdw->state_decoder_quiescent ?
4071                           "" : " <decode:stop>")),
4072                         (hdw->state_decoder_quiescent ?
4073                          " <decode:quiescent>" : ""),
4074                         (hdw->state_encoder_ok ?
4075                          "" : " <encode:init>"),
4076                         (hdw->state_encoder_run ?
4077                          (hdw->state_encoder_runok ?
4078                           " <encode:run>" :
4079                           " <encode:firstrun>") :
4080                          (hdw->state_encoder_runok ?
4081                           " <encode:stop>" :
4082                           " <encode:virgin>")),
4083                         (hdw->state_encoder_config ?
4084                          " <encode:configok>" :
4085                          (hdw->state_encoder_waitok ?
4086                           "" : " <encode:waitok>")),
4087                         (hdw->state_usbstream_run ?
4088                          " <usb:run>" : " <usb:stop>"),
4089                         (hdw->state_pathway_ok ?
4090                          " <pathway:ok>" : ""));
4091         case 3:
4092                 return scnprintf(
4093                         buf,acnt,
4094                         "state: %s",
4095                         pvr2_get_state_name(hdw->master_state));
4096         case 4: {
4097                 unsigned int tcnt = 0;
4098                 unsigned int ccnt;
4099
4100                 ccnt = scnprintf(buf,
4101                                  acnt,
4102                                  "Hardware supported inputs: ");
4103                 tcnt += ccnt;
4104                 tcnt += print_input_mask(hdw->input_avail_mask,
4105                                          buf+tcnt,
4106                                          acnt-tcnt);
4107                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4108                         ccnt = scnprintf(buf+tcnt,
4109                                          acnt-tcnt,
4110                                          "; allowed inputs: ");
4111                         tcnt += ccnt;
4112                         tcnt += print_input_mask(hdw->input_allowed_mask,
4113                                                  buf+tcnt,
4114                                                  acnt-tcnt);
4115                 }
4116                 return tcnt;
4117         }
4118         case 5: {
4119                 struct pvr2_stream_stats stats;
4120                 if (!hdw->vid_stream) break;
4121                 pvr2_stream_get_stats(hdw->vid_stream,
4122                                       &stats,
4123                                       0);
4124                 return scnprintf(
4125                         buf,acnt,
4126                         "Bytes streamed=%u"
4127                         " URBs: queued=%u idle=%u ready=%u"
4128                         " processed=%u failed=%u",
4129                         stats.bytes_processed,
4130                         stats.buffers_in_queue,
4131                         stats.buffers_in_idle,
4132                         stats.buffers_in_ready,
4133                         stats.buffers_processed,
4134                         stats.buffers_failed);
4135         }
4136         default: break;
4137         }
4138         return 0;
4139 }
4140
4141
4142 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4143                                    char *buf,unsigned int acnt)
4144 {
4145         unsigned int bcnt,ccnt,idx;
4146         bcnt = 0;
4147         LOCK_TAKE(hdw->big_lock);
4148         for (idx = 0; ; idx++) {
4149                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4150                 if (!ccnt) break;
4151                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4152                 if (!acnt) break;
4153                 buf[0] = '\n'; ccnt = 1;
4154                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4155         }
4156         LOCK_GIVE(hdw->big_lock);
4157         return bcnt;
4158 }
4159
4160
4161 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4162 {
4163         char buf[128];
4164         unsigned int idx,ccnt;
4165
4166         for (idx = 0; ; idx++) {
4167                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4168                 if (!ccnt) break;
4169                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4170         }
4171 }
4172
4173
4174 /* Evaluate and update the driver's current state, taking various actions
4175    as appropriate for the update. */
4176 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4177 {
4178         unsigned int st;
4179         int state_updated = 0;
4180         int callback_flag = 0;
4181         int analog_mode;
4182
4183         pvr2_trace(PVR2_TRACE_STBITS,
4184                    "Drive state check START");
4185         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4186                 pvr2_hdw_state_log_state(hdw);
4187         }
4188
4189         /* Process all state and get back over disposition */
4190         state_updated = pvr2_hdw_state_update(hdw);
4191
4192         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4193
4194         /* Update master state based upon all other states. */
4195         if (!hdw->flag_ok) {
4196                 st = PVR2_STATE_DEAD;
4197         } else if (hdw->fw1_state != FW1_STATE_OK) {
4198                 st = PVR2_STATE_COLD;
4199         } else if ((analog_mode ||
4200                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
4201                    !hdw->state_encoder_ok) {
4202                 st = PVR2_STATE_WARM;
4203         } else if (hdw->flag_tripped ||
4204                    (analog_mode && hdw->flag_decoder_missed)) {
4205                 st = PVR2_STATE_ERROR;
4206         } else if (hdw->state_usbstream_run &&
4207                    (!analog_mode ||
4208                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
4209                 st = PVR2_STATE_RUN;
4210         } else {
4211                 st = PVR2_STATE_READY;
4212         }
4213         if (hdw->master_state != st) {
4214                 pvr2_trace(PVR2_TRACE_STATE,
4215                            "Device state change from %s to %s",
4216                            pvr2_get_state_name(hdw->master_state),
4217                            pvr2_get_state_name(st));
4218                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4219                 hdw->master_state = st;
4220                 state_updated = !0;
4221                 callback_flag = !0;
4222         }
4223         if (state_updated) {
4224                 /* Trigger anyone waiting on any state changes here. */
4225                 wake_up(&hdw->state_wait_data);
4226         }
4227
4228         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4229                 pvr2_hdw_state_log_state(hdw);
4230         }
4231         pvr2_trace(PVR2_TRACE_STBITS,
4232                    "Drive state check DONE callback=%d",callback_flag);
4233
4234         return callback_flag;
4235 }
4236
4237
4238 /* Cause kernel thread to check / update driver state */
4239 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4240 {
4241         if (hdw->state_stale) return;
4242         hdw->state_stale = !0;
4243         trace_stbit("state_stale",hdw->state_stale);
4244         queue_work(hdw->workqueue,&hdw->workpoll);
4245 }
4246
4247
4248 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4249 {
4250         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4251 }
4252
4253
4254 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4255 {
4256         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4257 }
4258
4259
4260 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4261 {
4262         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4263 }
4264
4265
4266 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4267 {
4268         u32 cval,nval;
4269         int ret;
4270         if (~msk) {
4271                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4272                 if (ret) return ret;
4273                 nval = (cval & ~msk) | (val & msk);
4274                 pvr2_trace(PVR2_TRACE_GPIO,
4275                            "GPIO direction changing 0x%x:0x%x"
4276                            " from 0x%x to 0x%x",
4277                            msk,val,cval,nval);
4278         } else {
4279                 nval = val;
4280                 pvr2_trace(PVR2_TRACE_GPIO,
4281                            "GPIO direction changing to 0x%x",nval);
4282         }
4283         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4284 }
4285
4286
4287 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4288 {
4289         u32 cval,nval;
4290         int ret;
4291         if (~msk) {
4292                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4293                 if (ret) return ret;
4294                 nval = (cval & ~msk) | (val & msk);
4295                 pvr2_trace(PVR2_TRACE_GPIO,
4296                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4297                            msk,val,cval,nval);
4298         } else {
4299                 nval = val;
4300                 pvr2_trace(PVR2_TRACE_GPIO,
4301                            "GPIO output changing to 0x%x",nval);
4302         }
4303         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
4304 }
4305
4306
4307 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
4308 {
4309         return hdw->input_avail_mask;
4310 }
4311
4312
4313 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
4314 {
4315         return hdw->input_allowed_mask;
4316 }
4317
4318
4319 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
4320 {
4321         if (hdw->input_val != v) {
4322                 hdw->input_val = v;
4323                 hdw->input_dirty = !0;
4324         }
4325
4326         /* Handle side effects - if we switch to a mode that needs the RF
4327            tuner, then select the right frequency choice as well and mark
4328            it dirty. */
4329         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
4330                 hdw->freqSelector = 0;
4331                 hdw->freqDirty = !0;
4332         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
4333                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
4334                 hdw->freqSelector = 1;
4335                 hdw->freqDirty = !0;
4336         }
4337         return 0;
4338 }
4339
4340
4341 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
4342                                unsigned int change_mask,
4343                                unsigned int change_val)
4344 {
4345         int ret = 0;
4346         unsigned int nv,m,idx;
4347         LOCK_TAKE(hdw->big_lock);
4348         do {
4349                 nv = hdw->input_allowed_mask & ~change_mask;
4350                 nv |= (change_val & change_mask);
4351                 nv &= hdw->input_avail_mask;
4352                 if (!nv) {
4353                         /* No legal modes left; return error instead. */
4354                         ret = -EPERM;
4355                         break;
4356                 }
4357                 hdw->input_allowed_mask = nv;
4358                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
4359                         /* Current mode is still in the allowed mask, so
4360                            we're done. */
4361                         break;
4362                 }
4363                 /* Select and switch to a mode that is still in the allowed
4364                    mask */
4365                 if (!hdw->input_allowed_mask) {
4366                         /* Nothing legal; give up */
4367                         break;
4368                 }
4369                 m = hdw->input_allowed_mask;
4370                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
4371                         if (!((1 << idx) & m)) continue;
4372                         pvr2_hdw_set_input(hdw,idx);
4373                         break;
4374                 }
4375         } while (0);
4376         LOCK_GIVE(hdw->big_lock);
4377         return ret;
4378 }
4379
4380
4381 /* Find I2C address of eeprom */
4382 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
4383 {
4384         int result;
4385         LOCK_TAKE(hdw->ctl_lock); do {
4386                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
4387                 result = pvr2_send_request(hdw,
4388                                            hdw->cmd_buffer,1,
4389                                            hdw->cmd_buffer,1);
4390                 if (result < 0) break;
4391                 result = hdw->cmd_buffer[0];
4392         } while(0); LOCK_GIVE(hdw->ctl_lock);
4393         return result;
4394 }
4395
4396
4397 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
4398                              u32 match_type, u32 match_chip, u64 reg_id,
4399                              int setFl,u64 *val_ptr)
4400 {
4401 #ifdef CONFIG_VIDEO_ADV_DEBUG
4402         struct pvr2_i2c_client *cp;
4403         struct v4l2_register req;
4404         int stat = 0;
4405         int okFl = 0;
4406
4407         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
4408
4409         req.match_type = match_type;
4410         req.match_chip = match_chip;
4411         req.reg = reg_id;
4412         if (setFl) req.val = *val_ptr;
4413         mutex_lock(&hdw->i2c_list_lock); do {
4414                 list_for_each_entry(cp, &hdw->i2c_clients, list) {
4415                         if (!v4l2_chip_match_i2c_client(
4416                                     cp->client,
4417                                     req.match_type, req.match_chip)) {
4418                                 continue;
4419                         }
4420                         stat = pvr2_i2c_client_cmd(
4421                                 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
4422                                     VIDIOC_DBG_G_REGISTER),&req);
4423                         if (!setFl) *val_ptr = req.val;
4424                         okFl = !0;
4425                         break;
4426                 }
4427         } while (0); mutex_unlock(&hdw->i2c_list_lock);
4428         if (okFl) {
4429                 return stat;
4430         }
4431         return -EINVAL;
4432 #else
4433         return -ENOSYS;
4434 #endif
4435 }
4436
4437
4438 /*
4439   Stuff for Emacs to see, in order to encourage consistent editing style:
4440   *** Local Variables: ***
4441   *** mode: c ***
4442   *** fill-column: 75 ***
4443   *** tab-width: 8 ***
4444   *** c-basic-offset: 8 ***
4445   *** End: ***
4446   */