drivers/media/i2c/ad9389b.c

   1 /*
   2  * Analog Devices AD9389B/AD9889B video encoder driver
   3  *
   4  * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   5  *
   6  * This program is free software; you may redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  11  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  12  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  13  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  14  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  15  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  16  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  17  * SOFTWARE.
  18  */
  19
  20 /*
  21  * References (c = chapter, p = page):
  22  * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
  23  * HDMI Transitter, Rev. A, October 2010
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/slab.h>
  29 #include <linux/i2c.h>
  30 #include <linux/delay.h>
  31 #include <linux/videodev2.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/v4l2-dv-timings.h>
  34 #include <media/v4l2-device.h>
  35 #include <media/v4l2-common.h>
  36 #include <media/v4l2-dv-timings.h>
  37 #include <media/v4l2-ctrls.h>
  38 #include <media/ad9389b.h>
  39
  40 static int debug;
  41 module_param(debug, int, 0644);
  42 MODULE_PARM_DESC(debug, "debug level (0-2)");
  43
  44 MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
  45 MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  46 MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  47 MODULE_LICENSE("GPL");
  48
  49 #define MASK_AD9389B_EDID_RDY_INT   0x04
  50 #define MASK_AD9389B_MSEN_INT       0x40
  51 #define MASK_AD9389B_HPD_INT        0x80
  52
  53 #define MASK_AD9389B_HPD_DETECT     0x40
  54 #define MASK_AD9389B_MSEN_DETECT    0x20
  55 #define MASK_AD9389B_EDID_RDY       0x10
  56
  57 #define EDID_MAX_RETRIES (8)
  58 #define EDID_DELAY 250
  59 #define EDID_MAX_SEGM 8
  60
  61 /*
  62 **********************************************************************
  63 *
  64 *  Arrays with configuration parameters for the AD9389B
  65 *
  66 **********************************************************************
  67 */
  68
  69 struct i2c_reg_value {
  70         u8 reg;
  71         u8 value;
  72 };
  73
  74 struct ad9389b_state_edid {
  75         /* total number of blocks */
  76         u32 blocks;
  77         /* Number of segments read */
  78         u32 segments;
  79         u8 data[EDID_MAX_SEGM * 256];
  80         /* Number of EDID read retries left */
  81         unsigned read_retries;
  82 };
  83
  84 struct ad9389b_state {
  85         struct ad9389b_platform_data pdata;
  86         struct v4l2_subdev sd;
  87         struct media_pad pad;
  88         struct v4l2_ctrl_handler hdl;
  89         int chip_revision;
  90         /* Is the ad9389b powered on? */
  91         bool power_on;
  92         /* Did we receive hotplug and rx-sense signals? */
  93         bool have_monitor;
  94         /* timings from s_dv_timings */
  95         struct v4l2_dv_timings dv_timings;
  96         /* controls */
  97         struct v4l2_ctrl *hdmi_mode_ctrl;
  98         struct v4l2_ctrl *hotplug_ctrl;
  99         struct v4l2_ctrl *rx_sense_ctrl;
 100         struct v4l2_ctrl *have_edid0_ctrl;
 101         struct v4l2_ctrl *rgb_quantization_range_ctrl;
 102         struct i2c_client *edid_i2c_client;
 103         struct ad9389b_state_edid edid;
 104         /* Running counter of the number of detected EDIDs (for debugging) */
 105         unsigned edid_detect_counter;
 106         struct workqueue_struct *work_queue;
 107         struct delayed_work edid_handler; /* work entry */
 108 };
 109
 110 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
 111 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
 112 static void ad9389b_setup(struct v4l2_subdev *sd);
 113 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
 114 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
 115
 116 static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
 117 {
 118         return container_of(sd, struct ad9389b_state, sd);
 119 }
 120
 121 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 122 {
 123         return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
 124 }
 125
 126 /* ------------------------ I2C ----------------------------------------------- */
 127
 128 static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
 129 {
 130         struct i2c_client *client = v4l2_get_subdevdata(sd);
 131
 132         return i2c_smbus_read_byte_data(client, reg);
 133 }
 134
 135 static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
 136 {
 137         struct i2c_client *client = v4l2_get_subdevdata(sd);
 138         int ret;
 139         int i;
 140
 141         for (i = 0; i < 3; i++) {
 142                 ret = i2c_smbus_write_byte_data(client, reg, val);
 143                 if (ret == 0)
 144                         return 0;
 145         }
 146         v4l2_err(sd, "I2C Write Problem\n");
 147         return ret;
 148 }
 149
 150 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
 151    and then the value-mask (to be OR-ed). */
 152 static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
 153                                                 u8 clr_mask, u8 val_mask)
 154 {
 155         ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
 156 }
 157
 158 static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
 159 {
 160         struct ad9389b_state *state = get_ad9389b_state(sd);
 161         int i;
 162
 163         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 164
 165         for (i = 0; i < len; i++)
 166                 buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
 167 }
 168
 169 static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
 170 {
 171         return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
 172 }
 173
 174 static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
 175 {
 176         return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
 177 }
 178
 179 static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
 180 {
 181         ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
 182         ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
 183 }
 184
 185 static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
 186                               u16 A1, u16 A2, u16 A3, u16 A4,
 187                               u16 B1, u16 B2, u16 B3, u16 B4,
 188                               u16 C1, u16 C2, u16 C3, u16 C4)
 189 {
 190         /* A */
 191         ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
 192         ad9389b_wr(sd, 0x19, A1);
 193         ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
 194         ad9389b_wr(sd, 0x1B, A2);
 195         ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
 196         ad9389b_wr(sd, 0x1d, A3);
 197         ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
 198         ad9389b_wr(sd, 0x1f, A4);
 199
 200         /* B */
 201         ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
 202         ad9389b_wr(sd, 0x21, B1);
 203         ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
 204         ad9389b_wr(sd, 0x23, B2);
 205         ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
 206         ad9389b_wr(sd, 0x25, B3);
 207         ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
 208         ad9389b_wr(sd, 0x27, B4);
 209
 210         /* C */
 211         ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
 212         ad9389b_wr(sd, 0x29, C1);
 213         ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
 214         ad9389b_wr(sd, 0x2B, C2);
 215         ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
 216         ad9389b_wr(sd, 0x2D, C3);
 217         ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
 218         ad9389b_wr(sd, 0x2F, C4);
 219 }
 220
 221 static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
 222 {
 223         if (enable) {
 224                 u8 csc_mode = 0;
 225
 226                 ad9389b_csc_conversion_mode(sd, csc_mode);
 227                 ad9389b_csc_coeff(sd,
 228                                   4096-564, 0, 0, 256,
 229                                   0, 4096-564, 0, 256,
 230                                   0, 0, 4096-564, 256);
 231                 /* enable CSC */
 232                 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
 233                 /* AVI infoframe: Limited range RGB (16-235) */
 234                 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
 235         } else {
 236                 /* disable CSC */
 237                 ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
 238                 /* AVI infoframe: Full range RGB (0-255) */
 239                 ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
 240         }
 241 }
 242
 243 static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
 244 {
 245         struct ad9389b_state *state = get_ad9389b_state(sd);
 246
 247         if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 248                 /* CEA format, not IT  */
 249                 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
 250         } else {
 251                 /* IT format */
 252                 ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
 253         }
 254 }
 255
 256 static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
 257 {
 258         struct ad9389b_state *state = get_ad9389b_state(sd);
 259
 260         switch (ctrl->val) {
 261         case V4L2_DV_RGB_RANGE_AUTO:
 262                 /* automatic */
 263                 if (state->dv_timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
 264                         /* cea format, RGB limited range (16-235) */
 265                         ad9389b_csc_rgb_full2limit(sd, true);
 266                 } else {
 267                         /* not cea format, RGB full range (0-255) */
 268                         ad9389b_csc_rgb_full2limit(sd, false);
 269                 }
 270                 break;
 271         case V4L2_DV_RGB_RANGE_LIMITED:
 272                 /* RGB limited range (16-235) */
 273                 ad9389b_csc_rgb_full2limit(sd, true);
 274                 break;
 275         case V4L2_DV_RGB_RANGE_FULL:
 276                 /* RGB full range (0-255) */
 277                 ad9389b_csc_rgb_full2limit(sd, false);
 278                 break;
 279         default:
 280                 return -EINVAL;
 281         }
 282         return 0;
 283 }
 284
 285 static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
 286 {
 287         u8 gear;
 288
 289         /* Workaround for TMDS PLL problem
 290          * The TMDS PLL in AD9389b change gear when the chip is heated above a
 291          * certain temperature. The output is disabled when the PLL change gear
 292          * so the monitor has to lock on the signal again. A workaround for
 293          * this is to use the manual PLL gears. This is a solution from Analog
 294          * Devices that is not documented in the datasheets.
 295          * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
 296          *
 297          * The pixel frequency ranges are based on readout of the gear the
 298          * automatic gearing selects for different pixel clocks
 299          * (read from 0x9e [3:1]).
 300          */
 301
 302         if (pixelclock > 140000000)
 303                 gear = 0xc0; /* 4th gear */
 304         else if (pixelclock > 117000000)
 305                 gear = 0xb0; /* 3rd gear */
 306         else if (pixelclock > 87000000)
 307                 gear = 0xa0; /* 2nd gear */
 308         else if (pixelclock > 60000000)
 309                 gear = 0x90; /* 1st gear */
 310         else
 311                 gear = 0x80; /* 0th gear */
 312
 313         ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
 314 }
 315
 316 /* ------------------------------ CTRL OPS ------------------------------ */
 317
 318 static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
 319 {
 320         struct v4l2_subdev *sd = to_sd(ctrl);
 321         struct ad9389b_state *state = get_ad9389b_state(sd);
 322
 323         v4l2_dbg(1, debug, sd,
 324                 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
 325
 326         if (state->hdmi_mode_ctrl == ctrl) {
 327                 /* Set HDMI or DVI-D */
 328                 ad9389b_wr_and_or(sd, 0xaf, 0xfd,
 329                                 ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
 330                 return 0;
 331         }
 332         if (state->rgb_quantization_range_ctrl == ctrl)
 333                 return ad9389b_set_rgb_quantization_mode(sd, ctrl);
 334         return -EINVAL;
 335 }
 336
 337 static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
 338         .s_ctrl = ad9389b_s_ctrl,
 339 };
 340
 341 /* ---------------------------- CORE OPS ------------------------------------------- */
 342
 343 #ifdef CONFIG_VIDEO_ADV_DEBUG
 344 static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
 345 {
 346         reg->val = ad9389b_rd(sd, reg->reg & 0xff);
 347         reg->size = 1;
 348         return 0;
 349 }
 350
 351 static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
 352 {
 353         ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
 354         return 0;
 355 }
 356 #endif
 357
 358 static int ad9389b_log_status(struct v4l2_subdev *sd)
 359 {
 360         struct ad9389b_state *state = get_ad9389b_state(sd);
 361         struct ad9389b_state_edid *edid = &state->edid;
 362
 363         static const char * const states[] = {
 364                 "in reset",
 365                 "reading EDID",
 366                 "idle",
 367                 "initializing HDCP",
 368                 "HDCP enabled",
 369                 "initializing HDCP repeater",
 370                 "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
 371         };
 372         static const char * const errors[] = {
 373                 "no error",
 374                 "bad receiver BKSV",
 375                 "Ri mismatch",
 376                 "Pj mismatch",
 377                 "i2c error",
 378                 "timed out",
 379                 "max repeater cascade exceeded",
 380                 "hash check failed",
 381                 "too many devices",
 382                 "9", "A", "B", "C", "D", "E", "F"
 383         };
 384
 385         u8 manual_gear;
 386
 387         v4l2_info(sd, "chip revision %d\n", state->chip_revision);
 388         v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
 389         v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
 390                         (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
 391                                                         "detected" : "no",
 392                         (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
 393                                                         "detected" : "no",
 394                         edid->segments ? "found" : "no", edid->blocks);
 395         if (state->have_monitor) {
 396                 v4l2_info(sd, "%s output %s\n",
 397                                   (ad9389b_rd(sd, 0xaf) & 0x02) ?
 398                                   "HDMI" : "DVI-D",
 399                                   (ad9389b_rd(sd, 0xa1) & 0x3c) ?
 400                                   "disabled" : "enabled");
 401         }
 402         v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
 403                                         "encrypted" : "no encryption");
 404         v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
 405                         states[ad9389b_rd(sd, 0xc8) & 0xf],
 406                         errors[ad9389b_rd(sd, 0xc8) >> 4],
 407                         state->edid_detect_counter,
 408                         ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
 409         manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
 410         v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
 411                         ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
 412         v4l2_info(sd, "ad9389b: %s gear %d\n",
 413                   manual_gear ? "manual" : "automatic",
 414                   manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
 415                                 ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
 416         if (state->have_monitor) {
 417                 if (ad9389b_rd(sd, 0xaf) & 0x02) {
 418                         /* HDMI only */
 419                         u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
 420                         u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
 421                                  ad9389b_rd(sd, 0x02) << 8 |
 422                                  ad9389b_rd(sd, 0x03);
 423                         u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
 424                         u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
 425                         u32 CTS;
 426
 427                         if (manual_cts)
 428                                 CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
 429                                        ad9389b_rd(sd, 0x08) << 8 |
 430                                        ad9389b_rd(sd, 0x09);
 431                         else
 432                                 CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
 433                                        ad9389b_rd(sd, 0x05) << 8 |
 434                                        ad9389b_rd(sd, 0x06);
 435                         N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
 436                              ad9389b_rd(sd, 0x02) << 8 |
 437                              ad9389b_rd(sd, 0x03);
 438
 439                         v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
 440                                 manual_cts ? "manual" : "automatic", N, CTS);
 441
 442                         v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
 443                                 vic_detect, vic_sent);
 444                 }
 445         }
 446         if (state->dv_timings.type == V4L2_DV_BT_656_1120) {
 447                 struct v4l2_bt_timings *bt = bt = &state->dv_timings.bt;
 448                 u32 frame_width = bt->width + bt->hfrontporch +
 449                         bt->hsync + bt->hbackporch;
 450                 u32 frame_height = bt->height + bt->vfrontporch +
 451                         bt->vsync + bt->vbackporch;
 452                 u32 frame_size = frame_width * frame_height;
 453
 454                 v4l2_info(sd, "timings: %ux%u%s%u (%ux%u). Pix freq. = %u Hz. Polarities = 0x%x\n",
 455                         bt->width, bt->height, bt->interlaced ? "i" : "p",
 456                         frame_size > 0 ?  (unsigned)bt->pixelclock / frame_size : 0,
 457                         frame_width, frame_height,
 458                         (unsigned)bt->pixelclock, bt->polarities);
 459         } else {
 460                 v4l2_info(sd, "no timings set\n");
 461         }
 462         return 0;
 463 }
 464
 465 /* Power up/down ad9389b */
 466 static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
 467 {
 468         struct ad9389b_state *state = get_ad9389b_state(sd);
 469         struct ad9389b_platform_data *pdata = &state->pdata;
 470         const int retries = 20;
 471         int i;
 472
 473         v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
 474
 475         state->power_on = on;
 476
 477         if (!on) {
 478                 /* Power down */
 479                 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
 480                 return true;
 481         }
 482
 483         /* Power up */
 484         /* The ad9389b does not always come up immediately.
 485            Retry multiple times. */
 486         for (i = 0; i < retries; i++) {
 487                 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
 488                 if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
 489                         break;
 490                 ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
 491                 msleep(10);
 492         }
 493         if (i == retries) {
 494                 v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
 495                 ad9389b_s_power(sd, 0);
 496                 return false;
 497         }
 498         if (i > 1)
 499                 v4l2_dbg(1, debug, sd,
 500                         "needed %d retries to powerup the ad9389b\n", i);
 501
 502         /* Select chip: AD9389B */
 503         ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
 504
 505         /* Reserved registers that must be set according to REF_01 p. 11*/
 506         ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
 507         ad9389b_wr(sd, 0x9c, 0x38);
 508         ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
 509
 510         /* Differential output drive strength */
 511         if (pdata->diff_data_drive_strength > 0)
 512                 ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
 513         else
 514                 ad9389b_wr(sd, 0xa2, 0x87);
 515
 516         if (pdata->diff_clk_drive_strength > 0)
 517                 ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
 518         else
 519                 ad9389b_wr(sd, 0xa3, 0x87);
 520
 521         ad9389b_wr(sd, 0x0a, 0x01);
 522         ad9389b_wr(sd, 0xbb, 0xff);
 523
 524         /* Set number of attempts to read the EDID */
 525         ad9389b_wr(sd, 0xc9, 0xf);
 526         return true;
 527 }
 528
 529 /* Enable interrupts */
 530 static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
 531 {
 532         u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
 533         u8 irqs_rd;
 534         int retries = 100;
 535
 536         /* The datasheet says that the EDID ready interrupt should be
 537            disabled if there is no hotplug. */
 538         if (!enable)
 539                 irqs = 0;
 540         else if (ad9389b_have_hotplug(sd))
 541                 irqs |= MASK_AD9389B_EDID_RDY_INT;
 542
 543         /*
 544          * This i2c write can fail (approx. 1 in 1000 writes). But it
 545          * is essential that this register is correct, so retry it
 546          * multiple times.
 547          *
 548          * Note that the i2c write does not report an error, but the readback
 549          * clearly shows the wrong value.
 550          */
 551         do {
 552                 ad9389b_wr(sd, 0x94, irqs);
 553                 irqs_rd = ad9389b_rd(sd, 0x94);
 554         } while (retries-- && irqs_rd != irqs);
 555
 556         if (irqs_rd != irqs)
 557                 v4l2_err(sd, "Could not set interrupts: hw failure?\n");
 558 }
 559
 560 /* Interrupt handler */
 561 static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
 562 {
 563         u8 irq_status;
 564
 565         /* disable interrupts to prevent a race condition */
 566         ad9389b_set_isr(sd, false);
 567         irq_status = ad9389b_rd(sd, 0x96);
 568         /* clear detected interrupts */
 569         ad9389b_wr(sd, 0x96, irq_status);
 570
 571         if (irq_status & (MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT))
 572                 ad9389b_check_monitor_present_status(sd);
 573         if (irq_status & MASK_AD9389B_EDID_RDY_INT)
 574                 ad9389b_check_edid_status(sd);
 575
 576         /* enable interrupts */
 577         ad9389b_set_isr(sd, true);
 578         *handled = true;
 579         return 0;
 580 }
 581
 582 static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
 583         .log_status = ad9389b_log_status,
 584 #ifdef CONFIG_VIDEO_ADV_DEBUG
 585         .g_register = ad9389b_g_register,
 586         .s_register = ad9389b_s_register,
 587 #endif
 588         .s_power = ad9389b_s_power,
 589         .interrupt_service_routine = ad9389b_isr,
 590 };
 591
 592 /* ------------------------------ PAD OPS ------------------------------ */
 593
 594 static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
 595 {
 596         struct ad9389b_state *state = get_ad9389b_state(sd);
 597
 598         if (edid->pad != 0)
 599                 return -EINVAL;
 600         if (edid->blocks == 0 || edid->blocks > 256)
 601                 return -EINVAL;
 602         if (!edid->edid)
 603                 return -EINVAL;
 604         if (!state->edid.segments) {
 605                 v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
 606                 return -ENODATA;
 607         }
 608         if (edid->start_block >= state->edid.segments * 2)
 609                 return -E2BIG;
 610         if (edid->blocks + edid->start_block >= state->edid.segments * 2)
 611                 edid->blocks = state->edid.segments * 2 - edid->start_block;
 612         memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
 613                                 128 * edid->blocks);
 614         return 0;
 615 }
 616
 617 static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
 618         .get_edid = ad9389b_get_edid,
 619 };
 620
 621 /* ------------------------------ VIDEO OPS ------------------------------ */
 622
 623 /* Enable/disable ad9389b output */
 624 static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
 625 {
 626         struct ad9389b_state *state = get_ad9389b_state(sd);
 627
 628         v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
 629
 630         ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
 631         if (enable) {
 632                 ad9389b_check_monitor_present_status(sd);
 633         } else {
 634                 ad9389b_s_power(sd, 0);
 635                 state->have_monitor = false;
 636         }
 637         return 0;
 638 }
 639
 640 static const struct v4l2_dv_timings ad9389b_timings[] = {
 641         V4L2_DV_BT_CEA_720X480P59_94,
 642         V4L2_DV_BT_CEA_720X576P50,
 643         V4L2_DV_BT_CEA_1280X720P24,
 644         V4L2_DV_BT_CEA_1280X720P25,
 645         V4L2_DV_BT_CEA_1280X720P30,
 646         V4L2_DV_BT_CEA_1280X720P50,
 647         V4L2_DV_BT_CEA_1280X720P60,
 648         V4L2_DV_BT_CEA_1920X1080P24,
 649         V4L2_DV_BT_CEA_1920X1080P25,
 650         V4L2_DV_BT_CEA_1920X1080P30,
 651         V4L2_DV_BT_CEA_1920X1080P50,
 652         V4L2_DV_BT_CEA_1920X1080P60,
 653
 654         V4L2_DV_BT_DMT_640X350P85,
 655         V4L2_DV_BT_DMT_640X400P85,
 656         V4L2_DV_BT_DMT_720X400P85,
 657         V4L2_DV_BT_DMT_640X480P60,
 658         V4L2_DV_BT_DMT_640X480P72,
 659         V4L2_DV_BT_DMT_640X480P75,
 660         V4L2_DV_BT_DMT_640X480P85,
 661         V4L2_DV_BT_DMT_800X600P56,
 662         V4L2_DV_BT_DMT_800X600P60,
 663         V4L2_DV_BT_DMT_800X600P72,
 664         V4L2_DV_BT_DMT_800X600P75,
 665         V4L2_DV_BT_DMT_800X600P85,
 666         V4L2_DV_BT_DMT_848X480P60,
 667         V4L2_DV_BT_DMT_1024X768P60,
 668         V4L2_DV_BT_DMT_1024X768P70,
 669         V4L2_DV_BT_DMT_1024X768P75,
 670         V4L2_DV_BT_DMT_1024X768P85,
 671         V4L2_DV_BT_DMT_1152X864P75,
 672         V4L2_DV_BT_DMT_1280X768P60_RB,
 673         V4L2_DV_BT_DMT_1280X768P60,
 674         V4L2_DV_BT_DMT_1280X768P75,
 675         V4L2_DV_BT_DMT_1280X768P85,
 676         V4L2_DV_BT_DMT_1280X800P60_RB,
 677         V4L2_DV_BT_DMT_1280X800P60,
 678         V4L2_DV_BT_DMT_1280X800P75,
 679         V4L2_DV_BT_DMT_1280X800P85,
 680         V4L2_DV_BT_DMT_1280X960P60,
 681         V4L2_DV_BT_DMT_1280X960P85,
 682         V4L2_DV_BT_DMT_1280X1024P60,
 683         V4L2_DV_BT_DMT_1280X1024P75,
 684         V4L2_DV_BT_DMT_1280X1024P85,
 685         V4L2_DV_BT_DMT_1360X768P60,
 686         V4L2_DV_BT_DMT_1400X1050P60_RB,
 687         V4L2_DV_BT_DMT_1400X1050P60,
 688         V4L2_DV_BT_DMT_1400X1050P75,
 689         V4L2_DV_BT_DMT_1400X1050P85,
 690         V4L2_DV_BT_DMT_1440X900P60_RB,
 691         V4L2_DV_BT_DMT_1440X900P60,
 692         V4L2_DV_BT_DMT_1600X1200P60,
 693         V4L2_DV_BT_DMT_1680X1050P60_RB,
 694         V4L2_DV_BT_DMT_1680X1050P60,
 695         V4L2_DV_BT_DMT_1792X1344P60,
 696         V4L2_DV_BT_DMT_1856X1392P60,
 697         V4L2_DV_BT_DMT_1920X1200P60_RB,
 698         V4L2_DV_BT_DMT_1366X768P60,
 699         V4L2_DV_BT_DMT_1920X1080P60,
 700         {},
 701 };
 702
 703 static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
 704                                 struct v4l2_dv_timings *timings)
 705 {
 706         struct ad9389b_state *state = get_ad9389b_state(sd);
 707         int i;
 708
 709         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 710
 711         /* quick sanity check */
 712         if (timings->type != V4L2_DV_BT_656_1120)
 713                 return -EINVAL;
 714
 715         if (timings->bt.interlaced)
 716                 return -EINVAL;
 717         if (timings->bt.pixelclock < 27000000 ||
 718             timings->bt.pixelclock > 170000000)
 719                 return -EINVAL;
 720
 721         /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
 722            if the format is listed in ad9389b_timings[] */
 723         for (i = 0; ad9389b_timings[i].bt.width; i++) {
 724                 if (v4l_match_dv_timings(timings, &ad9389b_timings[i], 0)) {
 725                         *timings = ad9389b_timings[i];
 726                         break;
 727                 }
 728         }
 729
 730         timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
 731
 732         /* save timings */
 733         state->dv_timings = *timings;
 734
 735         /* update quantization range based on new dv_timings */
 736         ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
 737
 738         /* update PLL gear based on new dv_timings */
 739         if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
 740                 ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
 741
 742         /* update AVI infoframe */
 743         ad9389b_set_IT_content_AVI_InfoFrame(sd);
 744
 745         return 0;
 746 }
 747
 748 static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
 749                                 struct v4l2_dv_timings *timings)
 750 {
 751         struct ad9389b_state *state = get_ad9389b_state(sd);
 752
 753         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 754
 755         if (!timings)
 756                 return -EINVAL;
 757
 758         *timings = state->dv_timings;
 759
 760         return 0;
 761 }
 762
 763 static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
 764                         struct v4l2_enum_dv_timings *timings)
 765 {
 766         if (timings->index >= ARRAY_SIZE(ad9389b_timings))
 767                 return -EINVAL;
 768
 769         memset(timings->reserved, 0, sizeof(timings->reserved));
 770         timings->timings = ad9389b_timings[timings->index];
 771         return 0;
 772 }
 773
 774 static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
 775                         struct v4l2_dv_timings_cap *cap)
 776 {
 777         cap->type = V4L2_DV_BT_656_1120;
 778         cap->bt.max_width = 1920;
 779         cap->bt.max_height = 1200;
 780         cap->bt.min_pixelclock = 27000000;
 781         cap->bt.max_pixelclock = 170000000;
 782         cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 783                          V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
 784         cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
 785                 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
 786         return 0;
 787 }
 788
 789 static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
 790         .s_stream = ad9389b_s_stream,
 791         .s_dv_timings = ad9389b_s_dv_timings,
 792         .g_dv_timings = ad9389b_g_dv_timings,
 793         .enum_dv_timings = ad9389b_enum_dv_timings,
 794         .dv_timings_cap = ad9389b_dv_timings_cap,
 795 };
 796
 797 static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
 798 {
 799         v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
 800
 801         if (enable)
 802                 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
 803         else
 804                 ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
 805
 806         return 0;
 807 }
 808
 809 static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 810 {
 811         u32 N;
 812
 813         switch (freq) {
 814         case 32000: N = 4096; break;
 815         case 44100: N = 6272; break;
 816         case 48000: N = 6144; break;
 817         case 88200: N = 12544; break;
 818         case 96000: N = 12288; break;
 819         case 176400: N = 25088; break;
 820         case 192000: N = 24576; break;
 821         default:
 822                 return -EINVAL;
 823         }
 824
 825         /* Set N (used with CTS to regenerate the audio clock) */
 826         ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
 827         ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
 828         ad9389b_wr(sd, 0x03, N & 0xff);
 829
 830         return 0;
 831 }
 832
 833 static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 834 {
 835         u32 i2s_sf;
 836
 837         switch (freq) {
 838         case 32000: i2s_sf = 0x30; break;
 839         case 44100: i2s_sf = 0x00; break;
 840         case 48000: i2s_sf = 0x20; break;
 841         case 88200: i2s_sf = 0x80; break;
 842         case 96000: i2s_sf = 0xa0; break;
 843         case 176400: i2s_sf = 0xc0; break;
 844         case 192000: i2s_sf = 0xe0; break;
 845         default:
 846                 return -EINVAL;
 847         }
 848
 849         /* Set sampling frequency for I2S audio to 48 kHz */
 850         ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
 851
 852         return 0;
 853 }
 854
 855 static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
 856 {
 857         /* TODO based on input/output/config */
 858         /* TODO See datasheet "Programmers guide" p. 39-40 */
 859
 860         /* Only 2 channels in use for application */
 861         ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
 862         /* Speaker mapping */
 863         ad9389b_wr(sd, 0x51, 0x00);
 864
 865         /* TODO Where should this be placed? */
 866         /* 16 bit audio word length */
 867         ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
 868
 869         return 0;
 870 }
 871
 872 static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
 873         .s_stream = ad9389b_s_audio_stream,
 874         .s_clock_freq = ad9389b_s_clock_freq,
 875         .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
 876         .s_routing = ad9389b_s_routing,
 877 };
 878
 879 /* --------------------- SUBDEV OPS --------------------------------------- */
 880
 881 static const struct v4l2_subdev_ops ad9389b_ops = {
 882         .core  = &ad9389b_core_ops,
 883         .video = &ad9389b_video_ops,
 884         .audio = &ad9389b_audio_ops,
 885         .pad = &ad9389b_pad_ops,
 886 };
 887
 888 /* ----------------------------------------------------------------------- */
 889 static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
 890                                                         int segment, u8 *buf)
 891 {
 892         int i, j;
 893
 894         if (debug < lvl)
 895                 return;
 896
 897         v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
 898         for (i = 0; i < 256; i += 16) {
 899                 u8 b[128];
 900                 u8 *bp = b;
 901
 902                 if (i == 128)
 903                         v4l2_dbg(lvl, debug, sd, "\n");
 904                 for (j = i; j < i + 16; j++) {
 905                         sprintf(bp, "0x%02x, ", buf[j]);
 906                         bp += 6;
 907                 }
 908                 bp[0] = '\0';
 909                 v4l2_dbg(lvl, debug, sd, "%s\n", b);
 910         }
 911 }
 912
 913 static void ad9389b_edid_handler(struct work_struct *work)
 914 {
 915         struct delayed_work *dwork = to_delayed_work(work);
 916         struct ad9389b_state *state = container_of(dwork,
 917                         struct ad9389b_state, edid_handler);
 918         struct v4l2_subdev *sd = &state->sd;
 919         struct ad9389b_edid_detect ed;
 920
 921         v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 922
 923         if (ad9389b_check_edid_status(sd)) {
 924                 /* Return if we received the EDID. */
 925                 return;
 926         }
 927
 928         if (ad9389b_have_hotplug(sd)) {
 929                 /* We must retry reading the EDID several times, it is possible
 930                  * that initially the EDID couldn't be read due to i2c errors
 931                  * (DVI connectors are particularly prone to this problem). */
 932                 if (state->edid.read_retries) {
 933                         state->edid.read_retries--;
 934                         /* EDID read failed, trigger a retry */
 935                         ad9389b_wr(sd, 0xc9, 0xf);
 936                         queue_delayed_work(state->work_queue,
 937                                         &state->edid_handler, EDID_DELAY);
 938                         return;
 939                 }
 940         }
 941
 942         /* We failed to read the EDID, so send an event for this. */
 943         ed.present = false;
 944         ed.segment = ad9389b_rd(sd, 0xc4);
 945         v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
 946         v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
 947 }
 948
 949 static void ad9389b_audio_setup(struct v4l2_subdev *sd)
 950 {
 951         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 952
 953         ad9389b_s_i2s_clock_freq(sd, 48000);
 954         ad9389b_s_clock_freq(sd, 48000);
 955         ad9389b_s_routing(sd, 0, 0, 0);
 956 }
 957
 958 /* Initial setup of AD9389b */
 959
 960 /* Configure hdmi transmitter. */
 961 static void ad9389b_setup(struct v4l2_subdev *sd)
 962 {
 963         struct ad9389b_state *state = get_ad9389b_state(sd);
 964
 965         v4l2_dbg(1, debug, sd, "%s\n", __func__);
 966
 967         /* Input format: RGB 4:4:4 */
 968         ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
 969         /* Output format: RGB 4:4:4 */
 970         ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
 971         /* CSC fixed point: +/-2, 1st order interpolation 4:2:2 -> 4:4:4 up
 972            conversion, Aspect ratio: 16:9 */
 973         ad9389b_wr_and_or(sd, 0x17, 0xe1, 0x0e);
 974         /* Disable pixel repetition and CSC */
 975         ad9389b_wr_and_or(sd, 0x3b, 0x9e, 0x0);
 976         /* Output format: RGB 4:4:4, Active Format Information is valid. */
 977         ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
 978         /* Underscanned */
 979         ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
 980         /* Setup video format */
 981         ad9389b_wr(sd, 0x3c, 0x0);
 982         /* Active format aspect ratio: same as picure. */
 983         ad9389b_wr(sd, 0x47, 0x80);
 984         /* No encryption */
 985         ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
 986         /* Positive clk edge capture for input video clock */
 987         ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
 988
 989         ad9389b_audio_setup(sd);
 990
 991         v4l2_ctrl_handler_setup(&state->hdl);
 992
 993         ad9389b_set_IT_content_AVI_InfoFrame(sd);
 994 }
 995
 996 static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
 997 {
 998         struct ad9389b_monitor_detect mdt;
 999         struct ad9389b_state *state = get_ad9389b_state(sd);
1000
1001         mdt.present = state->have_monitor;
1002         v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
1003 }
1004
1005 static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
1006 {
1007         struct ad9389b_state *state = get_ad9389b_state(sd);
1008         /* read hotplug and rx-sense state */
1009         u8 status = ad9389b_rd(sd, 0x42);
1010
1011         v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
1012                          __func__,
1013                          status,
1014                          status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
1015                          status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
1016
1017         if ((status & MASK_AD9389B_HPD_DETECT) &&
1018             ((status & MASK_AD9389B_MSEN_DETECT) || state->edid.segments)) {
1019                 v4l2_dbg(1, debug, sd,
1020                                 "%s: hotplug and (rx-sense or edid)\n", __func__);
1021                 if (!state->have_monitor) {
1022                         v4l2_dbg(1, debug, sd, "%s: monitor detected\n", __func__);
1023                         state->have_monitor = true;
1024                         ad9389b_set_isr(sd, true);
1025                         if (!ad9389b_s_power(sd, true)) {
1026                                 v4l2_dbg(1, debug, sd,
1027                                         "%s: monitor detected, powerup failed\n", __func__);
1028                                 return;
1029                         }
1030                         ad9389b_setup(sd);
1031                         ad9389b_notify_monitor_detect(sd);
1032                         state->edid.read_retries = EDID_MAX_RETRIES;
1033                         queue_delayed_work(state->work_queue,
1034                                         &state->edid_handler, EDID_DELAY);
1035                 }
1036         } else if (status & MASK_AD9389B_HPD_DETECT) {
1037                 v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
1038                 state->edid.read_retries = EDID_MAX_RETRIES;
1039                 queue_delayed_work(state->work_queue,
1040                                 &state->edid_handler, EDID_DELAY);
1041         } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
1042                 v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
1043                 if (state->have_monitor) {
1044                         v4l2_dbg(1, debug, sd, "%s: monitor not detected\n", __func__);
1045                         state->have_monitor = false;
1046                         ad9389b_notify_monitor_detect(sd);
1047                 }
1048                 ad9389b_s_power(sd, false);
1049                 memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
1050         }
1051
1052         /* update read only ctrls */
1053         v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
1054         v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
1055         v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1056 }
1057
1058 static bool edid_block_verify_crc(u8 *edid_block)
1059 {
1060         int i;
1061         u8 sum = 0;
1062
1063         for (i = 0; i < 127; i++)
1064                 sum += *(edid_block + i);
1065         return ((255 - sum + 1) == edid_block[127]);
1066 }
1067
1068 static bool edid_segment_verify_crc(struct v4l2_subdev *sd, u32 segment)
1069 {
1070         struct ad9389b_state *state = get_ad9389b_state(sd);
1071         u32 blocks = state->edid.blocks;
1072         u8 *data = state->edid.data;
1073
1074         if (edid_block_verify_crc(&data[segment * 256])) {
1075                 if ((segment + 1) * 2 <= blocks)
1076                         return edid_block_verify_crc(&data[segment * 256 + 128]);
1077                 return true;
1078         }
1079         return false;
1080 }
1081
1082 static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1083 {
1084         struct ad9389b_state *state = get_ad9389b_state(sd);
1085         struct ad9389b_edid_detect ed;
1086         int segment;
1087         u8 edidRdy = ad9389b_rd(sd, 0xc5);
1088
1089         v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1090                          __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1091
1092         if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1093                 return false;
1094
1095         segment = ad9389b_rd(sd, 0xc4);
1096         if (segment >= EDID_MAX_SEGM) {
1097                 v4l2_err(sd, "edid segment number too big\n");
1098                 return false;
1099         }
1100         v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1101         ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1102         ad9389b_dbg_dump_edid(2, debug, sd, segment,
1103                         &state->edid.data[segment * 256]);
1104         if (segment == 0) {
1105                 state->edid.blocks = state->edid.data[0x7e] + 1;
1106                 v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1107                                 __func__, state->edid.blocks);
1108         }
1109         if (!edid_segment_verify_crc(sd, segment)) {
1110                 /* edid crc error, force reread of edid segment */
1111                 ad9389b_s_power(sd, false);
1112                 ad9389b_s_power(sd, true);
1113                 return false;
1114         }
1115         /* one more segment read ok */
1116         state->edid.segments = segment + 1;
1117         if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1118                 /* Request next EDID segment */
1119                 v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1120                                 __func__, state->edid.segments);
1121                 ad9389b_wr(sd, 0xc9, 0xf);
1122                 ad9389b_wr(sd, 0xc4, state->edid.segments);
1123                 state->edid.read_retries = EDID_MAX_RETRIES;
1124                 queue_delayed_work(state->work_queue,
1125                                 &state->edid_handler, EDID_DELAY);
1126                 return false;
1127         }
1128
1129         /* report when we have all segments but report only for segment 0 */
1130         ed.present = true;
1131         ed.segment = 0;
1132         v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1133         state->edid_detect_counter++;
1134         v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1135         return ed.present;
1136 }
1137
1138 /* ----------------------------------------------------------------------- */
1139
1140 static void ad9389b_init_setup(struct v4l2_subdev *sd)
1141 {
1142         struct ad9389b_state *state = get_ad9389b_state(sd);
1143         struct ad9389b_state_edid *edid = &state->edid;
1144
1145         v4l2_dbg(1, debug, sd, "%s\n", __func__);
1146
1147         /* clear all interrupts */
1148         ad9389b_wr(sd, 0x96, 0xff);
1149
1150         memset(edid, 0, sizeof(struct ad9389b_state_edid));
1151         state->have_monitor = false;
1152         ad9389b_set_isr(sd, false);
1153 }
1154
1155 static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1156 {
1157         const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1158         struct ad9389b_state *state;
1159         struct ad9389b_platform_data *pdata = client->dev.platform_data;
1160         struct v4l2_ctrl_handler *hdl;
1161         struct v4l2_subdev *sd;
1162         int err = -EIO;
1163
1164         /* Check if the adapter supports the needed features */
1165         if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1166                 return -EIO;
1167
1168         v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1169                         client->addr << 1);
1170
1171         state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1172         if (!state)
1173                 return -ENOMEM;
1174
1175         /* Platform data */
1176         if (pdata == NULL) {
1177                 v4l_err(client, "No platform data!\n");
1178                 return -ENODEV;
1179         }
1180         memcpy(&state->pdata, pdata, sizeof(state->pdata));
1181
1182         sd = &state->sd;
1183         v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1184         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1185
1186         hdl = &state->hdl;
1187         v4l2_ctrl_handler_init(hdl, 5);
1188
1189         /* private controls */
1190
1191         state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1192                         V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1193                         0, V4L2_DV_TX_MODE_DVI_D);
1194         state->hdmi_mode_ctrl->is_private = true;
1195         state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1196                         V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1197         state->hotplug_ctrl->is_private = true;
1198         state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1199                         V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1200         state->rx_sense_ctrl->is_private = true;
1201         state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1202                         V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1203         state->have_edid0_ctrl->is_private = true;
1204         state->rgb_quantization_range_ctrl =
1205                 v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1206                         V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1207                         0, V4L2_DV_RGB_RANGE_AUTO);
1208         state->rgb_quantization_range_ctrl->is_private = true;
1209         sd->ctrl_handler = hdl;
1210         if (hdl->error) {
1211                 err = hdl->error;
1212
1213                 goto err_hdl;
1214         }
1215
1216         state->pad.flags = MEDIA_PAD_FL_SINK;
1217         err = media_entity_init(&sd->entity, 1, &state->pad, 0);
1218         if (err)
1219                 goto err_hdl;
1220
1221         state->chip_revision = ad9389b_rd(sd, 0x0);
1222         if (state->chip_revision != 2) {
1223                 v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1224                 err = -EIO;
1225                 goto err_entity;
1226         }
1227         v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1228                         ad9389b_rd(sd, 0x41), state->chip_revision);
1229
1230         state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1231         if (state->edid_i2c_client == NULL) {
1232                 v4l2_err(sd, "failed to register edid i2c client\n");
1233                 err = -ENOMEM;
1234                 goto err_entity;
1235         }
1236
1237         state->work_queue = create_singlethread_workqueue(sd->name);
1238         if (state->work_queue == NULL) {
1239                 v4l2_err(sd, "could not create workqueue\n");
1240                 err = -ENOMEM;
1241                 goto err_unreg;
1242         }
1243
1244         INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1245         state->dv_timings = dv1080p60;
1246
1247         ad9389b_init_setup(sd);
1248         ad9389b_set_isr(sd, true);
1249
1250         v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1251                           client->addr << 1, client->adapter->name);
1252         return 0;
1253
1254 err_unreg:
1255         i2c_unregister_device(state->edid_i2c_client);
1256 err_entity:
1257         media_entity_cleanup(&sd->entity);
1258 err_hdl:
1259         v4l2_ctrl_handler_free(&state->hdl);
1260         return err;
1261 }
1262
1263 /* ----------------------------------------------------------------------- */
1264
1265 static int ad9389b_remove(struct i2c_client *client)
1266 {
1267         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1268         struct ad9389b_state *state = get_ad9389b_state(sd);
1269
1270         state->chip_revision = -1;
1271
1272         v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1273                  client->addr << 1, client->adapter->name);
1274
1275         ad9389b_s_stream(sd, false);
1276         ad9389b_s_audio_stream(sd, false);
1277         ad9389b_init_setup(sd);
1278         cancel_delayed_work(&state->edid_handler);
1279         i2c_unregister_device(state->edid_i2c_client);
1280         destroy_workqueue(state->work_queue);
1281         v4l2_device_unregister_subdev(sd);
1282         media_entity_cleanup(&sd->entity);
1283         v4l2_ctrl_handler_free(sd->ctrl_handler);
1284         return 0;
1285 }
1286
1287 /* ----------------------------------------------------------------------- */
1288
1289 static struct i2c_device_id ad9389b_id[] = {
1290         { "ad9389b", 0 },
1291         { "ad9889b", 0 },
1292         { }
1293 };
1294 MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1295
1296 static struct i2c_driver ad9389b_driver = {
1297         .driver = {
1298                 .owner = THIS_MODULE,
1299                 .name = "ad9389b",
1300         },
1301         .probe = ad9389b_probe,
1302         .remove = ad9389b_remove,
1303         .id_table = ad9389b_id,
1304 };
1305
1306 module_i2c_driver(ad9389b_driver);