2 * ngene.h: nGene PCIe bridge driver
4 * Copyright (C) 2005-2007 Micronas
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
27 /*#define ONE_ADAPTER*/
29 #include <linux/types.h>
30 #include <linux/sched.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c.h>
34 #include <asm/scatterlist.h>
36 #include <linux/dvb/frontend.h>
40 #include "dvb_demux.h"
41 #include "dvb_frontend.h"
42 #include "dvb_ringbuffer.h"
44 #define NGENE_VID 0x18c3
45 #define NGENE_PID 0x0720
48 #define VIDEO_CAP_AVC 128
49 #define VIDEO_CAP_H264 128
50 #define VIDEO_CAP_VC1 256
51 #define VIDEO_CAP_WMV9 256
52 #define VIDEO_CAP_MPEG4 512
56 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */
58 STREAM_AUDIOIN1, /* I2S or SPI Input */
65 SMODE_AUDIO_SPDIF = 0x20,
67 SMODE_TRANSPORT_STREAM = 0x08,
68 SMODE_AUDIO_CAPTURE = 0x04,
69 SMODE_VBI_CAPTURE = 0x02,
70 SMODE_VIDEO_CAPTURE = 0x01
73 enum STREAM_FLAG_BITS {
74 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */
75 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */
76 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */
77 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */
78 SFLAG_COLORBAR = 0x04, /* Select colorbar */
81 #define PROGRAM_ROM 0x0000
82 #define PROGRAM_SRAM 0x1000
83 #define PERIPHERALS0 0x8000
84 #define PERIPHERALS1 0x9000
85 #define SHARED_BUFFER 0xC000
87 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000)
88 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100)
89 #define NGENE_COMMAND (SHARED_BUFFER+0x0200)
90 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)
91 #define NGENE_STATUS (SHARED_BUFFER+0x0208)
92 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)
93 #define NGENE_EVENT (SHARED_BUFFER+0x0210)
94 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)
95 #define VARIABLES (SHARED_BUFFER+0x0210)
97 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)
98 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)
99 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)
101 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)
102 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)
103 #define EEPROM_AREA (SHARED_BUFFER+0x0A00)
105 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80)
106 #define SG_VBI_1 (SHARED_BUFFER+0x0B00)
107 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80)
108 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00)
109 #define SG_VBI_2 (SHARED_BUFFER+0x0C80)
110 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00)
111 #define SG_V_OUT (SHARED_BUFFER+0x0D80)
112 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00)
114 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)
115 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)
116 #define DATA_A_OUT (SHARED_BUFFER+0x0F80)
117 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000)
118 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000)
119 #define DATA_V_OUT (SHARED_BUFFER+0x3000)
121 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)
123 #define TIMESTAMPS 0xA000
124 #define SCRATCHPAD 0xA080
125 #define FORCE_INT 0xA088
126 #define FORCE_NMI 0xA090
127 #define INT_STATUS 0xA0A0
129 #define DEV_VER 0x9004
131 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)
139 } __attribute__ ((__packed__));
141 struct SHARED_MEMORY {
154 u8 pad1[0xc260 - 0xc218];
161 u8 pad2[0xd000 - 0xc268];
163 } __attribute__ ((__packed__));
165 struct BUFFER_STREAM_RESULTS {
166 u32 Clock; /* Stream time in 100ns units */
167 u16 RemainingLines; /* Remaining lines in this field.
168 0 for complete field */
169 u8 FieldCount; /* Video field number */
170 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,
172 u16 BlockCount; /* Audio block count (unused) */
175 } __attribute__ ((__packed__));
177 struct HW_SCATTER_GATHER_ELEMENT {
181 } __attribute__ ((__packed__));
183 struct BUFFER_HEADER {
185 struct BUFFER_STREAM_RESULTS SR;
187 u32 Number_of_entries_1;
189 u64 Address_of_first_entry_1;
191 u32 Number_of_entries_2;
193 u64 Address_of_first_entry_2;
194 } __attribute__ ((__packed__));
196 struct EVENT_BUFFER {
203 } __attribute__ ((__packed__));
205 typedef struct EVENT_BUFFER *PEVENT_BUFFER;
207 /* Firmware commands. */
211 CMD_FWLOAD_PREPARE = 0x01,
212 CMD_FWLOAD_FINISH = 0x02,
214 CMD_I2C_WRITE = 0x04,
216 CMD_I2C_WRITE_NOSTOP = 0x05,
217 CMD_I2C_CONTINUE_WRITE = 0x06,
218 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,
220 CMD_DEBUG_OUTPUT = 0x09,
223 CMD_CONFIGURE_BUFFER = 0x11,
224 CMD_CONFIGURE_FREE_BUFFER = 0x12,
227 CMD_SPI_WRITE = 0x14,
230 CMD_MEM_WRITE = 0x21,
232 CMD_SFR_WRITE = 0x23,
233 CMD_IRAM_READ = 0x24,
234 CMD_IRAM_WRITE = 0x25,
235 CMD_SET_GPIO_PIN = 0x26,
236 CMD_SET_GPIO_INT = 0x27,
237 CMD_CONFIGURE_UART = 0x28,
238 CMD_WRITE_UART = 0x29,
250 } __attribute__ ((__packed__));
252 struct FW_I2C_WRITE {
253 struct FW_HEADER hdr;
256 } __attribute__ ((__packed__));
258 struct FW_I2C_CONTINUE_WRITE {
259 struct FW_HEADER hdr;
261 } __attribute__ ((__packed__));
264 struct FW_HEADER hdr;
266 u8 Data[252]; /* followed by two bytes of read data count */
267 } __attribute__ ((__packed__));
269 struct FW_SPI_WRITE {
270 struct FW_HEADER hdr;
273 } __attribute__ ((__packed__));
276 struct FW_HEADER hdr;
278 u8 Data[252]; /* followed by two bytes of read data count */
279 } __attribute__ ((__packed__));
281 struct FW_FWLOAD_PREPARE {
282 struct FW_HEADER hdr;
283 } __attribute__ ((__packed__));
285 struct FW_FWLOAD_FINISH {
286 struct FW_HEADER hdr;
287 u16 Address; /* address of final block */
289 } __attribute__ ((__packed__));
292 * Meaning of FW_STREAM_CONTROL::Mode bits:
293 * Bit 7: Loopback PEXin to PEXout using TVOut channel
295 * Bit 5: Audio select; 0=I2S, 1=SPDIF
297 * Bit 3: Enable transport stream
298 * Bit 2: Enable audio capture
299 * Bit 1: Enable ITU-Video VBI capture
300 * Bit 0: Enable ITU-Video capture
302 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)
303 * Bit 7: continuous capture
304 * Bit 6: capture one field
305 * Bit 5: capture one frame
307 * Bit 3: starting field; 0=odd, 1=even
308 * Bit 2: sample size; 0=8-bit, 1=10-bit
309 * Bit 1: data format; 0=UYVY, 1=YUY2
310 * Bit 0: resets buffer pointers
314 SMODE_LOOPBACK = 0x80,
316 _SMODE_AUDIO_SPDIF = 0x20,
317 _SMODE_AVSYNC = 0x10,
318 _SMODE_TRANSPORT_STREAM = 0x08,
319 _SMODE_AUDIO_CAPTURE = 0x04,
320 _SMODE_VBI_CAPTURE = 0x02,
321 _SMODE_VIDEO_CAPTURE = 0x01
325 /* Meaning of FW_STREAM_CONTROL::Stream bits:
326 * Bit 3: Audio sample count: 0 = relative, 1 = absolute
327 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder
328 * Bits 1-0: stream select, UVI1, UVI2, TVOUT
331 struct FW_STREAM_CONTROL {
332 struct FW_HEADER hdr;
333 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */
334 u8 Control; /* Value written to UVI1_CTL */
335 u8 Mode; /* Controls clock source */
336 u8 SetupDataLen; /* Length of setup data, MSB=1 write
338 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer
340 u64 Buffer_Address; /* Address of first buffer header */
341 u16 BytesPerVideoLine;
342 u16 MaxLinesPerField;
343 u16 MinLinesPerField;
346 u16 MaxVBILinesPerField;
347 u16 MinVBILinesPerField;
348 u16 SetupDataAddr; /* ngene relative address of setup data */
349 u8 SetupData[32]; /* setup data */
350 } __attribute__((__packed__));
352 #define AUDIO_BLOCK_SIZE 256
353 #define TS_BLOCK_SIZE 256
356 struct FW_HEADER hdr;
358 } __attribute__ ((__packed__));
360 struct FW_MEM_WRITE {
361 struct FW_HEADER hdr;
364 } __attribute__ ((__packed__));
366 struct FW_SFR_IRAM_READ {
367 struct FW_HEADER hdr;
369 } __attribute__ ((__packed__));
371 struct FW_SFR_IRAM_WRITE {
372 struct FW_HEADER hdr;
375 } __attribute__ ((__packed__));
377 struct FW_SET_GPIO_PIN {
378 struct FW_HEADER hdr;
380 } __attribute__ ((__packed__));
382 struct FW_SET_GPIO_INT {
383 struct FW_HEADER hdr;
385 } __attribute__ ((__packed__));
387 struct FW_SET_DEBUGMODE {
388 struct FW_HEADER hdr;
390 } __attribute__ ((__packed__));
392 struct FW_CONFIGURE_BUFFERS {
393 struct FW_HEADER hdr;
395 } __attribute__ ((__packed__));
397 enum _BUFFER_CONFIGS {
398 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */
399 BUFFER_CONFIG_4422 = 0,
400 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */
401 BUFFER_CONFIG_3333 = 1,
402 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */
403 BUFFER_CONFIG_8022 = 2,
404 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */
407 struct FW_CONFIGURE_FREE_BUFFERS {
408 struct FW_HEADER hdr;
409 u8 UVI1_BufferLength;
410 u8 UVI2_BufferLength;
412 u8 AUD1_BufferLength;
413 u8 AUD2_BufferLength;
415 } __attribute__ ((__packed__));
417 struct FW_CONFIGURE_UART {
418 struct FW_HEADER hdr;
420 } __attribute__ ((__packed__));
423 _UART_BAUDRATE_19200 = 0,
424 _UART_BAUDRATE_9600 = 1,
425 _UART_BAUDRATE_4800 = 2,
426 _UART_BAUDRATE_2400 = 3,
427 _UART_RX_ENABLE = 0x40,
428 _UART_TX_ENABLE = 0x80,
431 struct FW_WRITE_UART {
432 struct FW_HEADER hdr;
434 } __attribute__ ((__packed__));
437 struct ngene_command {
443 struct FW_HEADER hdr;
444 struct FW_I2C_WRITE I2CWrite;
445 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;
446 struct FW_I2C_READ I2CRead;
447 struct FW_STREAM_CONTROL StreamControl;
448 struct FW_FWLOAD_PREPARE FWLoadPrepare;
449 struct FW_FWLOAD_FINISH FWLoadFinish;
450 struct FW_MEM_READ MemoryRead;
451 struct FW_MEM_WRITE MemoryWrite;
452 struct FW_SFR_IRAM_READ SfrIramRead;
453 struct FW_SFR_IRAM_WRITE SfrIramWrite;
454 struct FW_SPI_WRITE SPIWrite;
455 struct FW_SPI_READ SPIRead;
456 struct FW_SET_GPIO_PIN SetGpioPin;
457 struct FW_SET_GPIO_INT SetGpioInt;
458 struct FW_SET_DEBUGMODE SetDebugMode;
459 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;
460 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;
461 struct FW_CONFIGURE_UART ConfigureUart;
462 struct FW_WRITE_UART WriteUart;
464 } __attribute__ ((__packed__));
466 #define NGENE_INTERFACE_VERSION 0x103
467 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */
468 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */
469 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */
470 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */
471 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page
472 Max: (1920x1080i60) */
474 #define OVERFLOW_BUFFER_SIZE (8192)
476 #define RING_SIZE_VIDEO 4
477 #define RING_SIZE_AUDIO 8
478 #define RING_SIZE_TS 8
480 #define NUM_SCATTER_GATHER_ENTRIES 8
482 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \
483 RING_SIZE_VIDEO * 2) + \
484 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \
485 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \
486 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \
487 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \
488 (RING_SIZE_TS * PAGE_SIZE * 4) + \
489 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)
491 #define EVENT_QUEUE_SIZE 16
493 typedef struct HW_SCATTER_GATHER_ELEMENT *PHW_SCATTER_GATHER_ELEMENT;
494 typedef struct FWRB *PFWRB;
496 /* Gathers the current state of a single channel. */
498 struct SBufferHeader {
499 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */
500 struct SBufferHeader *Next;
502 PHW_SCATTER_GATHER_ELEMENT scList1;
504 PHW_SCATTER_GATHER_ELEMENT scList2;
507 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */
508 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)
524 struct SRingBufferDescriptor {
525 struct SBufferHeader *Head; /* Points to first buffer in ring buffer
527 u64 PAHead; /* Physical address of first buffer */
528 u32 MemSize; /* Memory size of allocated ring buffers
529 (needed for freeing) */
530 u32 NumBuffers; /* Number of buffers in the ring */
531 u32 Buffer1Length; /* Allocated length of Buffer 1 */
532 u32 Buffer2Length; /* Allocated length of Buffer 2 */
533 void *SCListMem; /* Memory to hold scatter gather lists for this
535 u64 PASCListMem; /* Physical address .. */
536 u32 SCListMemSize; /* Size of this memory */
539 enum STREAMMODEFLAGS {
540 StreamMode_NONE = 0, /* Stream not used */
541 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */
542 StreamMode_TSIN = 2, /* Transport stream input (all) */
543 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60
545 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */
549 enum BufferExchangeFlags {
550 BEF_EVEN_FIELD = 0x00000001,
551 BEF_CONTINUATION = 0x00000002,
552 BEF_MORE_DATA = 0x00000004,
553 BEF_OVERFLOW = 0x00000008,
554 DF_SWAP32 = 0x00010000,
557 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);
560 IBufferExchange *pExchange;
561 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */
567 u16 nBytesPerLineVideo;
569 u16 nBytesPerLineVBI;
570 u32 CaptureLength; /* Used for audio and transport stream */
571 } MICI_STREAMINFO, *PMICI_STREAMINFO;
573 /****************************************************************************/
574 /* STRUCTS ******************************************************************/
575 /****************************************************************************/
577 /* sound hardware definition */
578 #define MIXER_ADDR_TVTUNER 0
579 #define MIXER_ADDR_LAST 0
581 struct ngene_channel;
583 /*struct sound chip*/
586 struct ngene_channel *chan;
587 struct snd_card *card;
589 struct snd_pcm_substream *substream;
593 spinlock_t mixer_lock;
595 int mixer_volume[MIXER_ADDR_LAST + 1][2];
596 int capture_source[MIXER_ADDR_LAST + 1][2];
600 struct ngene_overlay {
603 enum v4l2_field field;
604 struct v4l2_clip *clips;
609 struct ngene_tvnorm {
612 u16 swidth, sheight; /* scaled standard width, height */
618 struct ngene_channel *ch;
619 enum v4l2_priority prio;
623 struct videobuf_queue vbuf_q;
624 struct videobuf_queue vbi;
628 enum v4l2_buf_type type;
629 const struct ngene_format *fmt;
631 const struct ngene_format *ovfmt;
632 struct ngene_overlay ov;
636 struct ngene_channel {
637 struct device device;
638 struct i2c_adapter i2c_adapter;
645 struct dvb_frontend *fe;
646 struct dmxdev dmxdev;
647 struct dvb_demux demux;
648 struct dmx_frontend hw_frontend;
649 struct dmx_frontend mem_frontend;
651 struct video_device *v4l_dev;
653 struct dvb_adapter dvb_adapter;
655 struct tasklet_struct demux_tasklet;
657 struct SBufferHeader *nextBuffer;
659 enum HWSTATE HWState;
663 IBufferExchange *pBufferExchange;
664 IBufferExchange *pBufferExchange2;
666 spinlock_t state_lock;
670 u16 nBytesPerVBILine;
674 struct SRingBufferDescriptor RingBuffer;
675 struct SRingBufferDescriptor TSRingBuffer;
676 struct SRingBufferDescriptor TSIdleBuffer;
683 int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t);
686 /* stuff from analog driver */
689 struct mychip *mychip;
690 struct snd_card *soundcard;
695 int soundbuffisallocated;
702 struct ngene_tvnorm *tvnorms;
708 struct v4l2_prio_state prio;
709 struct ngene_vopen init;
711 struct v4l2_framebuffer fbuf;
712 struct ngene_buffer *screen; /* overlay */
713 struct list_head capture; /* video capture queue */
715 struct semaphore reslock;
723 typedef void (rx_cb_t)(struct ngene *, u32, u8);
724 typedef void (tx_cb_t)(struct ngene *, u32);
728 struct pci_dev *pci_dev;
729 unsigned char *iomem;
732 struct dvb_adapter dvb_adapter;
734 /*struct i2c_adapter i2c_adapter;*/
737 u32 fw_interface_version;
742 void *OverflowBuffer;
743 dma_addr_t PAOverflowBuffer;
744 void *FWInterfaceBuffer;
745 dma_addr_t PAFWInterfaceBuffer;
749 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];
750 int EventQueueOverflowCount;
751 int EventQueueOverflowFlag;
752 struct tasklet_struct event_tasklet;
753 struct EVENT_BUFFER *EventBuffer;
754 int EventQueueWriteIndex;
755 int EventQueueReadIndex;
757 wait_queue_head_t cmd_wq;
759 struct semaphore cmd_mutex;
760 struct semaphore stream_mutex;
761 struct semaphore pll_mutex;
762 struct semaphore i2c_switch_mutex;
763 int i2c_current_channel;
767 struct ngene_channel channel[MAX_STREAM];
769 struct ngene_info *card_info;
771 tx_cb_t *TxEventNotify;
772 rx_cb_t *RxEventNotify;
774 wait_queue_head_t tx_wq;
775 wait_queue_head_t rx_wq;
776 #define UART_RBUF_LEN 4096
777 u8 uart_rbuf[UART_RBUF_LEN];
778 int uart_rp, uart_wp;
781 #define TSOUT_BUF_SIZE (512*188*8)
782 struct dvb_ringbuffer tsout_rbuf;
785 #define AIN_BUF_SIZE (128*1024)
786 struct dvb_ringbuffer ain_rbuf;
790 #define VIN_BUF_SIZE (4*1920*1080)
791 struct dvb_ringbuffer vin_rbuf;
793 unsigned long exp_val;
800 #define NGENE_TERRATEC 1
801 #define NGENE_SIDEWINDER 2
802 #define NGENE_RACER 3
803 #define NGENE_VIPER 4
804 #define NGENE_PYTHON 5
805 #define NGENE_VBOX_V1 6
806 #define NGENE_VBOX_V2 7
811 int io_type[MAX_STREAM];
812 #define NGENE_IO_NONE 0
813 #define NGENE_IO_TV 1
814 #define NGENE_IO_HDTV 2
815 #define NGENE_IO_TSIN 4
816 #define NGENE_IO_TSOUT 8
817 #define NGENE_IO_AIN 16
820 void *tuner_config[4];
822 int (*demod_attach[4])(struct ngene_channel *);
823 int (*tuner_attach[4])(struct ngene_channel *);
834 int (*gate_ctrl)(struct dvb_frontend *, int);
835 int (*switch_ctrl)(struct ngene_channel *, int, int);
841 int fourcc; /* video4linux 2 */
842 int btformat; /* BT848_COLOR_FMT_* */
844 int btswap; /* BT848_COLOR_CTL_* */
845 int depth; /* bit/pixel */
847 int hshift, vshift; /* for planar modes */
851 #define RESOURCE_OVERLAY 1
852 #define RESOURCE_VIDEO 2
853 #define RESOURCE_VBI 4
855 struct ngene_buffer {
856 /* common v4l buffer stuff -- must be first */
857 struct videobuf_buffer vb;
860 const struct ngene_format *fmt;
867 int ngene_command_stream_control(struct ngene *dev,
868 u8 stream, u8 control, u8 mode, u8 flags);
869 int ngene_command_nop(struct ngene *dev);
870 int ngene_command_i2c_read(struct ngene *dev, u8 adr,
871 u8 *out, u8 outlen, u8 *in, u8 inlen, int flag);
872 int ngene_command_i2c_write(struct ngene *dev, u8 adr, u8 *out, u8 outlen);
873 int ngene_command_imem_read(struct ngene *dev, u8 adr, u8 *data, int type);
874 int ngene_command_imem_write(struct ngene *dev, u8 adr, u8 data, int type);
875 int ngene_stream_control(struct ngene *dev, u8 stream, u8 control, u8 mode,
876 u16 lines, u16 bpl, u16 vblines, u16 vbibpl);