drivers/media/dvb/frontends/drxk_hard.c

   1 /*
   2  * drxk_hard: DRX-K DVB-C/T demodulator driver
   3  *
   4  * Copyright (C) 2010-2011 Digital Devices GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <linux/version.h>
  32 #include <asm/div64.h>
  33
  34 #include "dvb_frontend.h"
  35 #include "drxk.h"
  36 #include "drxk_hard.h"
  37
  38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
  39 static int PowerDownQAM(struct drxk_state *state);
  40 static int SetDVBTStandard(struct drxk_state *state,
  41                            enum OperationMode oMode);
  42 static int SetQAMStandard(struct drxk_state *state,
  43                           enum OperationMode oMode);
  44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
  45                   s32 tunerFreqOffset);
  46 static int SetDVBTStandard(struct drxk_state *state,
  47                            enum OperationMode oMode);
  48 static int DVBTStart(struct drxk_state *state);
  49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
  50                    s32 tunerFreqOffset);
  51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
  52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
  53 static int SwitchAntennaToQAM(struct drxk_state *state);
  54 static int SwitchAntennaToDVBT(struct drxk_state *state);
  55
  56 static bool IsDVBT(struct drxk_state *state)
  57 {
  58         return state->m_OperationMode == OM_DVBT;
  59 }
  60
  61 static bool IsQAM(struct drxk_state *state)
  62 {
  63         return state->m_OperationMode == OM_QAM_ITU_A ||
  64             state->m_OperationMode == OM_QAM_ITU_B ||
  65             state->m_OperationMode == OM_QAM_ITU_C;
  66 }
  67
  68 bool IsA1WithPatchCode(struct drxk_state *state)
  69 {
  70         return state->m_DRXK_A1_PATCH_CODE;
  71 }
  72
  73 bool IsA1WithRomCode(struct drxk_state *state)
  74 {
  75         return state->m_DRXK_A1_ROM_CODE;
  76 }
  77
  78 #define NOA1ROM 0
  79
  80 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
  81 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
  82
  83 #define DEFAULT_MER_83  165
  84 #define DEFAULT_MER_93  250
  85
  86 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
  87 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
  88 #endif
  89
  90 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
  91 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
  92 #endif
  93
  94 #ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
  95 #define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
  96 #endif
  97
  98 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
  99 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
 100
 101 #ifndef DRXK_KI_RAGC_ATV
 102 #define DRXK_KI_RAGC_ATV   4
 103 #endif
 104 #ifndef DRXK_KI_IAGC_ATV
 105 #define DRXK_KI_IAGC_ATV   6
 106 #endif
 107 #ifndef DRXK_KI_DAGC_ATV
 108 #define DRXK_KI_DAGC_ATV   7
 109 #endif
 110
 111 #ifndef DRXK_KI_RAGC_QAM
 112 #define DRXK_KI_RAGC_QAM   3
 113 #endif
 114 #ifndef DRXK_KI_IAGC_QAM
 115 #define DRXK_KI_IAGC_QAM   4
 116 #endif
 117 #ifndef DRXK_KI_DAGC_QAM
 118 #define DRXK_KI_DAGC_QAM   7
 119 #endif
 120 #ifndef DRXK_KI_RAGC_DVBT
 121 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
 122 #endif
 123 #ifndef DRXK_KI_IAGC_DVBT
 124 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
 125 #endif
 126 #ifndef DRXK_KI_DAGC_DVBT
 127 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
 128 #endif
 129
 130 #ifndef DRXK_AGC_DAC_OFFSET
 131 #define DRXK_AGC_DAC_OFFSET (0x800)
 132 #endif
 133
 134 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
 135 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
 136 #endif
 137
 138 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
 139 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
 140 #endif
 141
 142 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
 143 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
 144 #endif
 145
 146 #ifndef DRXK_QAM_SYMBOLRATE_MAX
 147 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
 148 #endif
 149
 150 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
 151 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
 152 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
 153 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
 154 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
 155 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
 156 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
 157 #define DRXK_BL_ROM_OFFSET_UCODE        0
 158
 159 #define DRXK_BLC_TIMEOUT                100
 160
 161 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
 162 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
 163
 164 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
 165
 166 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
 167 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
 168 #endif
 169
 170 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
 171 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
 172 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
 173 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
 174 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
 175
 176 static unsigned int debug;
 177 module_param(debug, int, 0644);
 178 MODULE_PARM_DESC(debug, "enable debug messages");
 179
 180 #define dprintk(level, fmt, arg...) do {                        \
 181 if (debug >= level)                                             \
 182         printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg);    \
 183 } while (0)
 184
 185
 186 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 187 {
 188         u64 tmp64;
 189
 190         tmp64 = (u64) a * (u64) b;
 191         do_div(tmp64, c);
 192
 193         return (u32) tmp64;
 194 }
 195
 196 inline u32 Frac28a(u32 a, u32 c)
 197 {
 198         int i = 0;
 199         u32 Q1 = 0;
 200         u32 R0 = 0;
 201
 202         R0 = (a % c) << 4;      /* 32-28 == 4 shifts possible at max */
 203         Q1 = a / c;             /* integer part, only the 4 least significant bits
 204                                    will be visible in the result */
 205
 206         /* division using radix 16, 7 nibbles in the result */
 207         for (i = 0; i < 7; i++) {
 208                 Q1 = (Q1 << 4) | (R0 / c);
 209                 R0 = (R0 % c) << 4;
 210         }
 211         /* rounding */
 212         if ((R0 >> 3) >= c)
 213                 Q1++;
 214
 215         return Q1;
 216 }
 217
 218 static u32 Log10Times100(u32 x)
 219 {
 220         static const u8 scale = 15;
 221         static const u8 indexWidth = 5;
 222         u8 i = 0;
 223         u32 y = 0;
 224         u32 d = 0;
 225         u32 k = 0;
 226         u32 r = 0;
 227         /*
 228            log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
 229            0 <= n < ((1<<INDEXWIDTH)+1)
 230          */
 231
 232         static const u32 log2lut[] = {
 233                 0,              /* 0.000000 */
 234                 290941,         /* 290941.300628 */
 235                 573196,         /* 573196.476418 */
 236                 847269,         /* 847269.179851 */
 237                 1113620,        /* 1113620.489452 */
 238                 1372674,        /* 1372673.576986 */
 239                 1624818,        /* 1624817.752104 */
 240                 1870412,        /* 1870411.981536 */
 241                 2109788,        /* 2109787.962654 */
 242                 2343253,        /* 2343252.817465 */
 243                 2571091,        /* 2571091.461923 */
 244                 2793569,        /* 2793568.696416 */
 245                 3010931,        /* 3010931.055901 */
 246                 3223408,        /* 3223408.452106 */
 247                 3431216,        /* 3431215.635215 */
 248                 3634553,        /* 3634553.498355 */
 249                 3833610,        /* 3833610.244726 */
 250                 4028562,        /* 4028562.434393 */
 251                 4219576,        /* 4219575.925308 */
 252                 4406807,        /* 4406806.721144 */
 253                 4590402,        /* 4590401.736809 */
 254                 4770499,        /* 4770499.491025 */
 255                 4947231,        /* 4947230.734179 */
 256                 5120719,        /* 5120719.018555 */
 257                 5291081,        /* 5291081.217197 */
 258                 5458428,        /* 5458427.996830 */
 259                 5622864,        /* 5622864.249668 */
 260                 5784489,        /* 5784489.488298 */
 261                 5943398,        /* 5943398.207380 */
 262                 6099680,        /* 6099680.215452 */
 263                 6253421,        /* 6253420.939751 */
 264                 6404702,        /* 6404701.706649 */
 265                 6553600,        /* 6553600.000000 */
 266         };
 267
 268
 269         if (x == 0)
 270                 return 0;
 271
 272         /* Scale x (normalize) */
 273         /* computing y in log(x/y) = log(x) - log(y) */
 274         if ((x & ((0xffffffff) << (scale + 1))) == 0) {
 275                 for (k = scale; k > 0; k--) {
 276                         if (x & (((u32) 1) << scale))
 277                                 break;
 278                         x <<= 1;
 279                 }
 280         } else {
 281                 for (k = scale; k < 31; k++) {
 282                         if ((x & (((u32) (-1)) << (scale + 1))) == 0)
 283                                 break;
 284                         x >>= 1;
 285                 }
 286         }
 287         /*
 288            Now x has binary point between bit[scale] and bit[scale-1]
 289            and 1.0 <= x < 2.0 */
 290
 291         /* correction for divison: log(x) = log(x/y)+log(y) */
 292         y = k * ((((u32) 1) << scale) * 200);
 293
 294         /* remove integer part */
 295         x &= ((((u32) 1) << scale) - 1);
 296         /* get index */
 297         i = (u8) (x >> (scale - indexWidth));
 298         /* compute delta (x - a) */
 299         d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
 300         /* compute log, multiplication (d* (..)) must be within range ! */
 301         y += log2lut[i] +
 302             ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
 303         /* Conver to log10() */
 304         y /= 108853;            /* (log2(10) << scale) */
 305         r = (y >> 1);
 306         /* rounding */
 307         if (y & ((u32) 1))
 308                 r++;
 309         return r;
 310 }
 311
 312 /****************************************************************************/
 313 /* I2C **********************************************************************/
 314 /****************************************************************************/
 315
 316 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
 317 {
 318         struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
 319                                     .buf = val, .len = 1}
 320         };
 321         return (i2c_transfer(adapter, msgs, 1) == 1) ? 0 : -1;
 322 }
 323
 324 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
 325 {
 326         struct i2c_msg msg = {
 327             .addr = adr, .flags = 0, .buf = data, .len = len };
 328
 329         dprintk(3, ":");
 330         if (debug > 2) {
 331                 int i;
 332                 for (i = 0; i < len; i++)
 333                         printk(KERN_CONT " %02x", data[i]);
 334                 printk(KERN_CONT "\n");
 335         }
 336         if (i2c_transfer(adap, &msg, 1) != 1) {
 337                 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
 338                 return -1;
 339         }
 340         return 0;
 341 }
 342
 343 static int i2c_read(struct i2c_adapter *adap,
 344                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 345 {
 346         struct i2c_msg msgs[2] = { {.addr = adr, .flags = 0,
 347                                     .buf = msg, .len = len},
 348         {.addr = adr, .flags = I2C_M_RD,
 349          .buf = answ, .len = alen}
 350         };
 351         dprintk(3, ":");
 352         if (debug > 2) {
 353                 int i;
 354                 for (i = 0; i < len; i++)
 355                         printk(KERN_CONT " %02x", msg[i]);
 356                 printk(KERN_CONT "\n");
 357         }
 358         if (i2c_transfer(adap, msgs, 2) != 2) {
 359                 if (debug > 2)
 360                         printk(KERN_CONT ": ERROR!\n");
 361
 362                 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
 363                 return -1;
 364         }
 365         if (debug > 2) {
 366                 int i;
 367                 printk(KERN_CONT ": Read ");
 368                 for (i = 0; i < len; i++)
 369                         printk(KERN_CONT " %02x", msg[i]);
 370                 printk(KERN_CONT "\n");
 371         }
 372         return 0;
 373 }
 374
 375 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
 376 {
 377         u8 adr = state->demod_address, mm1[4], mm2[2], len;
 378 #ifdef I2C_LONG_ADR
 379         flags |= 0xC0;
 380 #endif
 381         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 382                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 383                 mm1[1] = ((reg >> 16) & 0xFF);
 384                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 385                 mm1[3] = ((reg >> 7) & 0xFF);
 386                 len = 4;
 387         } else {
 388                 mm1[0] = ((reg << 1) & 0xFF);
 389                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 390                 len = 2;
 391         }
 392         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 393         if (i2c_read(state->i2c, adr, mm1, len, mm2, 2) < 0)
 394                 return -1;
 395         if (data)
 396                 *data = mm2[0] | (mm2[1] << 8);
 397
 398         return 0;
 399 }
 400
 401 static int read16(struct drxk_state *state, u32 reg, u16 *data)
 402 {
 403         return read16_flags(state, reg, data, 0);
 404 }
 405
 406 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
 407 {
 408         u8 adr = state->demod_address, mm1[4], mm2[4], len;
 409 #ifdef I2C_LONG_ADR
 410         flags |= 0xC0;
 411 #endif
 412         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 413                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
 414                 mm1[1] = ((reg >> 16) & 0xFF);
 415                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
 416                 mm1[3] = ((reg >> 7) & 0xFF);
 417                 len = 4;
 418         } else {
 419                 mm1[0] = ((reg << 1) & 0xFF);
 420                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 421                 len = 2;
 422         }
 423         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
 424         if (i2c_read(state->i2c, adr, mm1, len, mm2, 4) < 0)
 425                 return -1;
 426         if (data)
 427                 *data = mm2[0] | (mm2[1] << 8) |
 428                     (mm2[2] << 16) | (mm2[3] << 24);
 429
 430         return 0;
 431 }
 432
 433 static int read32(struct drxk_state *state, u32 reg, u32 *data)
 434 {
 435         return read32_flags(state, reg, data, 0);
 436 }
 437
 438 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
 439 {
 440         u8 adr = state->demod_address, mm[6], len;
 441 #ifdef I2C_LONG_ADR
 442         flags |= 0xC0;
 443 #endif
 444         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 445                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 446                 mm[1] = ((reg >> 16) & 0xFF);
 447                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 448                 mm[3] = ((reg >> 7) & 0xFF);
 449                 len = 4;
 450         } else {
 451                 mm[0] = ((reg << 1) & 0xFF);
 452                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 453                 len = 2;
 454         }
 455         mm[len] = data & 0xff;
 456         mm[len + 1] = (data >> 8) & 0xff;
 457
 458         dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
 459         if (i2c_write(state->i2c, adr, mm, len + 2) < 0)
 460                 return -1;
 461         return 0;
 462 }
 463
 464 static int write16(struct drxk_state *state, u32 reg, u16 data)
 465 {
 466         return write16_flags(state, reg, data, 0);
 467 }
 468
 469 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
 470 {
 471         u8 adr = state->demod_address, mm[8], len;
 472 #ifdef I2C_LONG_ADR
 473         flags |= 0xC0;
 474 #endif
 475         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
 476                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
 477                 mm[1] = ((reg >> 16) & 0xFF);
 478                 mm[2] = ((reg >> 24) & 0xFF) | flags;
 479                 mm[3] = ((reg >> 7) & 0xFF);
 480                 len = 4;
 481         } else {
 482                 mm[0] = ((reg << 1) & 0xFF);
 483                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
 484                 len = 2;
 485         }
 486         mm[len] = data & 0xff;
 487         mm[len + 1] = (data >> 8) & 0xff;
 488         mm[len + 2] = (data >> 16) & 0xff;
 489         mm[len + 3] = (data >> 24) & 0xff;
 490         dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
 491         if (i2c_write(state->i2c, adr, mm, len + 4) < 0)
 492                 return -1;
 493         return 0;
 494 }
 495
 496 static int write32(struct drxk_state *state, u32 reg, u32 data)
 497 {
 498         return write32_flags(state, reg, data, 0);
 499 }
 500
 501 static int write_block(struct drxk_state *state, u32 Address,
 502                       const int BlockSize, const u8 pBlock[])
 503 {
 504         int status = 0, BlkSize = BlockSize;
 505         u8 Flags = 0;
 506 #ifdef I2C_LONG_ADR
 507         Flags |= 0xC0;
 508 #endif
 509         while (BlkSize > 0) {
 510                 int Chunk = BlkSize > state->m_ChunkSize ?
 511                     state->m_ChunkSize : BlkSize;
 512                 u8 *AdrBuf = &state->Chunk[0];
 513                 u32 AdrLength = 0;
 514
 515                 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
 516                         AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
 517                         AdrBuf[1] = ((Address >> 16) & 0xFF);
 518                         AdrBuf[2] = ((Address >> 24) & 0xFF);
 519                         AdrBuf[3] = ((Address >> 7) & 0xFF);
 520                         AdrBuf[2] |= Flags;
 521                         AdrLength = 4;
 522                         if (Chunk == state->m_ChunkSize)
 523                                 Chunk -= 2;
 524                 } else {
 525                         AdrBuf[0] = ((Address << 1) & 0xFF);
 526                         AdrBuf[1] = (((Address >> 16) & 0x0F) |
 527                                      ((Address >> 18) & 0xF0));
 528                         AdrLength = 2;
 529                 }
 530                 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
 531                 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
 532                 if (debug > 1) {
 533                         int i;
 534                         if (pBlock)
 535                                 for (i = 0; i < Chunk; i++)
 536                                         printk(KERN_CONT " %02x", pBlock[i]);
 537                         printk(KERN_CONT "\n");
 538                 }
 539                 status = i2c_write(state->i2c, state->demod_address,
 540                                    &state->Chunk[0], Chunk + AdrLength);
 541                 if (status < 0) {
 542                         printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
 543                                __func__, Address);
 544                         break;
 545                 }
 546                 pBlock += Chunk;
 547                 Address += (Chunk >> 1);
 548                 BlkSize -= Chunk;
 549         }
 550         return status;
 551 }
 552
 553 #ifndef DRXK_MAX_RETRIES_POWERUP
 554 #define DRXK_MAX_RETRIES_POWERUP 20
 555 #endif
 556
 557 int PowerUpDevice(struct drxk_state *state)
 558 {
 559         int status;
 560         u8 data = 0;
 561         u16 retryCount = 0;
 562
 563         dprintk(1, "\n");
 564
 565         status = i2c_read1(state->i2c, state->demod_address, &data);
 566         if (status < 0)
 567                 do {
 568                         data = 0;
 569                         if (i2c_write(state->i2c,
 570                                       state->demod_address, &data, 1) < 0)
 571                                 printk(KERN_ERR "drxk: powerup failed\n");
 572                         msleep(10);
 573                         retryCount++;
 574                 } while (i2c_read1(state->i2c,
 575                                    state->demod_address, &data) < 0 &&
 576                          (retryCount < DRXK_MAX_RETRIES_POWERUP));
 577         if (retryCount >= DRXK_MAX_RETRIES_POWERUP)
 578                 return -1;
 579         do {
 580                 /* Make sure all clk domains are active */
 581                 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
 582                 if (status < 0)
 583                         break;
 584                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
 585                 if (status < 0)
 586                         break;
 587                 /* Enable pll lock tests */
 588                 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
 589                 if (status < 0)
 590                         break;
 591                 state->m_currentPowerMode = DRX_POWER_UP;
 592         } while (0);
 593         return status;
 594 }
 595
 596
 597 static int init_state(struct drxk_state *state)
 598 {
 599         u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
 600         u32 ulVSBIfAgcOutputLevel = 0;
 601         u32 ulVSBIfAgcMinLevel = 0;
 602         u32 ulVSBIfAgcMaxLevel = 0x7FFF;
 603         u32 ulVSBIfAgcSpeed = 3;
 604
 605         u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
 606         u32 ulVSBRfAgcOutputLevel = 0;
 607         u32 ulVSBRfAgcMinLevel = 0;
 608         u32 ulVSBRfAgcMaxLevel = 0x7FFF;
 609         u32 ulVSBRfAgcSpeed = 3;
 610         u32 ulVSBRfAgcTop = 9500;
 611         u32 ulVSBRfAgcCutOffCurrent = 4000;
 612
 613         u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
 614         u32 ulATVIfAgcOutputLevel = 0;
 615         u32 ulATVIfAgcMinLevel = 0;
 616         u32 ulATVIfAgcMaxLevel = 0;
 617         u32 ulATVIfAgcSpeed = 3;
 618
 619         u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
 620         u32 ulATVRfAgcOutputLevel = 0;
 621         u32 ulATVRfAgcMinLevel = 0;
 622         u32 ulATVRfAgcMaxLevel = 0;
 623         u32 ulATVRfAgcTop = 9500;
 624         u32 ulATVRfAgcCutOffCurrent = 4000;
 625         u32 ulATVRfAgcSpeed = 3;
 626
 627         u32 ulQual83 = DEFAULT_MER_83;
 628         u32 ulQual93 = DEFAULT_MER_93;
 629
 630         u32 ulDVBTStaticTSClock = 1;
 631         u32 ulDVBCStaticTSClock = 1;
 632
 633         u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 634         u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 635
 636         /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
 637         /* io_pad_cfg_mode output mode is drive always */
 638         /* io_pad_cfg_drive is set to power 2 (23 mA) */
 639         u32 ulGPIOCfg = 0x0113;
 640         u32 ulGPIO = 0;
 641         u32 ulSerialMode = 1;
 642         u32 ulInvertTSClock = 0;
 643         u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
 644         u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
 645         u32 ulDVBTBitrate = 50000000;
 646         u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
 647
 648         u32 ulInsertRSByte = 0;
 649
 650         u32 ulRfMirror = 1;
 651         u32 ulPowerDown = 0;
 652
 653         u32 ulAntennaDVBT = 1;
 654         u32 ulAntennaDVBC = 0;
 655         u32 ulAntennaSwitchDVBTDVBC = 0;
 656
 657         dprintk(1, "\n");
 658
 659         state->m_hasLNA = false;
 660         state->m_hasDVBT = false;
 661         state->m_hasDVBC = false;
 662         state->m_hasATV = false;
 663         state->m_hasOOB = false;
 664         state->m_hasAudio = false;
 665
 666         state->m_ChunkSize = 124;
 667
 668         state->m_oscClockFreq = 0;
 669         state->m_smartAntInverted = false;
 670         state->m_bPDownOpenBridge = false;
 671
 672         /* real system clock frequency in kHz */
 673         state->m_sysClockFreq = 151875;
 674         /* Timing div, 250ns/Psys */
 675         /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
 676         state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
 677                                    HI_I2C_DELAY) / 1000;
 678         /* Clipping */
 679         if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
 680                 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
 681         state->m_HICfgWakeUpKey = (state->demod_address << 1);
 682         /* port/bridge/power down ctrl */
 683         state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
 684
 685         state->m_bPowerDown = (ulPowerDown != 0);
 686
 687         state->m_DRXK_A1_PATCH_CODE = false;
 688         state->m_DRXK_A1_ROM_CODE = false;
 689         state->m_DRXK_A2_ROM_CODE = false;
 690         state->m_DRXK_A3_ROM_CODE = false;
 691         state->m_DRXK_A2_PATCH_CODE = false;
 692         state->m_DRXK_A3_PATCH_CODE = false;
 693
 694         /* Init AGC and PGA parameters */
 695         /* VSB IF */
 696         state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
 697         state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
 698         state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
 699         state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
 700         state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
 701         state->m_vsbPgaCfg = 140;
 702
 703         /* VSB RF */
 704         state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
 705         state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
 706         state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
 707         state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
 708         state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
 709         state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
 710         state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
 711         state->m_vsbPreSawCfg.reference = 0x07;
 712         state->m_vsbPreSawCfg.usePreSaw = true;
 713
 714         state->m_Quality83percent = DEFAULT_MER_83;
 715         state->m_Quality93percent = DEFAULT_MER_93;
 716         if (ulQual93 <= 500 && ulQual83 < ulQual93) {
 717                 state->m_Quality83percent = ulQual83;
 718                 state->m_Quality93percent = ulQual93;
 719         }
 720
 721         /* ATV IF */
 722         state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
 723         state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
 724         state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
 725         state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
 726         state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
 727
 728         /* ATV RF */
 729         state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
 730         state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
 731         state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
 732         state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
 733         state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
 734         state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
 735         state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
 736         state->m_atvPreSawCfg.reference = 0x04;
 737         state->m_atvPreSawCfg.usePreSaw = true;
 738
 739
 740         /* DVBT RF */
 741         state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
 742         state->m_dvbtRfAgcCfg.outputLevel = 0;
 743         state->m_dvbtRfAgcCfg.minOutputLevel = 0;
 744         state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
 745         state->m_dvbtRfAgcCfg.top = 0x2100;
 746         state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
 747         state->m_dvbtRfAgcCfg.speed = 1;
 748
 749
 750         /* DVBT IF */
 751         state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
 752         state->m_dvbtIfAgcCfg.outputLevel = 0;
 753         state->m_dvbtIfAgcCfg.minOutputLevel = 0;
 754         state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
 755         state->m_dvbtIfAgcCfg.top = 13424;
 756         state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
 757         state->m_dvbtIfAgcCfg.speed = 3;
 758         state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
 759         state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
 760         /* state->m_dvbtPgaCfg = 140; */
 761
 762         state->m_dvbtPreSawCfg.reference = 4;
 763         state->m_dvbtPreSawCfg.usePreSaw = false;
 764
 765         /* QAM RF */
 766         state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
 767         state->m_qamRfAgcCfg.outputLevel = 0;
 768         state->m_qamRfAgcCfg.minOutputLevel = 6023;
 769         state->m_qamRfAgcCfg.maxOutputLevel = 27000;
 770         state->m_qamRfAgcCfg.top = 0x2380;
 771         state->m_qamRfAgcCfg.cutOffCurrent = 4000;
 772         state->m_qamRfAgcCfg.speed = 3;
 773
 774         /* QAM IF */
 775         state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
 776         state->m_qamIfAgcCfg.outputLevel = 0;
 777         state->m_qamIfAgcCfg.minOutputLevel = 0;
 778         state->m_qamIfAgcCfg.maxOutputLevel = 9000;
 779         state->m_qamIfAgcCfg.top = 0x0511;
 780         state->m_qamIfAgcCfg.cutOffCurrent = 0;
 781         state->m_qamIfAgcCfg.speed = 3;
 782         state->m_qamIfAgcCfg.IngainTgtMax = 5119;
 783         state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
 784
 785         state->m_qamPgaCfg = 140;
 786         state->m_qamPreSawCfg.reference = 4;
 787         state->m_qamPreSawCfg.usePreSaw = false;
 788
 789         state->m_OperationMode = OM_NONE;
 790         state->m_DrxkState = DRXK_UNINITIALIZED;
 791
 792         /* MPEG output configuration */
 793         state->m_enableMPEGOutput = true;       /* If TRUE; enable MPEG ouput */
 794         state->m_insertRSByte = false;  /* If TRUE; insert RS byte */
 795         state->m_enableParallel = true; /* If TRUE;
 796                                            parallel out otherwise serial */
 797         state->m_invertDATA = false;    /* If TRUE; invert DATA signals */
 798         state->m_invertERR = false;     /* If TRUE; invert ERR signal */
 799         state->m_invertSTR = false;     /* If TRUE; invert STR signals */
 800         state->m_invertVAL = false;     /* If TRUE; invert VAL signals */
 801         state->m_invertCLK = (ulInvertTSClock != 0);    /* If TRUE; invert CLK signals */
 802         state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
 803         state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
 804         /* If TRUE; static MPEG clockrate will be used;
 805            otherwise clockrate will adapt to the bitrate of the TS */
 806
 807         state->m_DVBTBitrate = ulDVBTBitrate;
 808         state->m_DVBCBitrate = ulDVBCBitrate;
 809
 810         state->m_TSDataStrength = (ulTSDataStrength & 0x07);
 811         state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
 812
 813         /* Maximum bitrate in b/s in case static clockrate is selected */
 814         state->m_mpegTsStaticBitrate = 19392658;
 815         state->m_disableTEIhandling = false;
 816
 817         if (ulInsertRSByte)
 818                 state->m_insertRSByte = true;
 819
 820         state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
 821         if (ulMpegLockTimeOut < 10000)
 822                 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
 823         state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
 824         if (ulDemodLockTimeOut < 10000)
 825                 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
 826
 827         /* QAM defaults */
 828         state->m_Constellation = DRX_CONSTELLATION_AUTO;
 829         state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
 830         state->m_fecRsPlen = 204 * 8;   /* fecRsPlen  annex A */
 831         state->m_fecRsPrescale = 1;
 832
 833         state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
 834         state->m_agcFastClipCtrlDelay = 0;
 835
 836         state->m_GPIOCfg = (ulGPIOCfg);
 837         state->m_GPIO = (ulGPIO == 0 ? 0 : 1);
 838
 839         state->m_AntennaDVBT = (ulAntennaDVBT == 0 ? 0 : 1);
 840         state->m_AntennaDVBC = (ulAntennaDVBC == 0 ? 0 : 1);
 841         state->m_AntennaSwitchDVBTDVBC =
 842             (ulAntennaSwitchDVBTDVBC == 0 ? 0 : 1);
 843
 844         state->m_bPowerDown = false;
 845         state->m_currentPowerMode = DRX_POWER_DOWN;
 846
 847         state->m_enableParallel = (ulSerialMode == 0);
 848
 849         state->m_rfmirror = (ulRfMirror == 0);
 850         state->m_IfAgcPol = false;
 851         return 0;
 852 }
 853
 854 static int DRXX_Open(struct drxk_state *state)
 855 {
 856         int status = 0;
 857         u32 jtag = 0;
 858         u16 bid = 0;
 859         u16 key = 0;
 860
 861         dprintk(1, "\n");
 862         do {
 863                 /* stop lock indicator process */
 864                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 865                 if (status < 0)
 866                         break;
 867                 /* Check device id */
 868                 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
 869                 if (status < 0)
 870                         break;
 871                 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
 872                 if (status < 0)
 873                         break;
 874                 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
 875                 if (status < 0)
 876                         break;
 877                 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
 878                 if (status < 0)
 879                         break;
 880                 status = write16(state, SIO_TOP_COMM_KEY__A, key);
 881                 if (status < 0)
 882                         break;
 883         } while (0);
 884         return status;
 885 }
 886
 887 static int GetDeviceCapabilities(struct drxk_state *state)
 888 {
 889         u16 sioPdrOhwCfg = 0;
 890         u32 sioTopJtagidLo = 0;
 891         int status;
 892
 893         dprintk(1, "\n");
 894         do {
 895                 /* driver 0.9.0 */
 896                 /* stop lock indicator process */
 897                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
 898                 if (status < 0)
 899                         break;
 900
 901                 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
 902                 if (status < 0)
 903                         break;
 904                 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
 905                 if (status < 0)
 906                         break;
 907                 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
 908                 if (status < 0)
 909                         break;
 910
 911                 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
 912                 case 0:
 913                         /* ignore (bypass ?) */
 914                         break;
 915                 case 1:
 916                         /* 27 MHz */
 917                         state->m_oscClockFreq = 27000;
 918                         break;
 919                 case 2:
 920                         /* 20.25 MHz */
 921                         state->m_oscClockFreq = 20250;
 922                         break;
 923                 case 3:
 924                         /* 4 MHz */
 925                         state->m_oscClockFreq = 20250;
 926                         break;
 927                 default:
 928                         return -1;
 929                 }
 930                 /*
 931                    Determine device capabilities
 932                    Based on pinning v14
 933                  */
 934                 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
 935                 if (status < 0)
 936                         break;
 937                 /* driver 0.9.0 */
 938                 switch ((sioTopJtagidLo >> 29) & 0xF) {
 939                 case 0:
 940                         state->m_deviceSpin = DRXK_SPIN_A1;
 941                         break;
 942                 case 2:
 943                         state->m_deviceSpin = DRXK_SPIN_A2;
 944                         break;
 945                 case 3:
 946                         state->m_deviceSpin = DRXK_SPIN_A3;
 947                         break;
 948                 default:
 949                         state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
 950                         status = -1;
 951                         break;
 952                 }
 953                 switch ((sioTopJtagidLo >> 12) & 0xFF) {
 954                 case 0x13:
 955                         /* typeId = DRX3913K_TYPE_ID */
 956                         state->m_hasLNA = false;
 957                         state->m_hasOOB = false;
 958                         state->m_hasATV = false;
 959                         state->m_hasAudio = false;
 960                         state->m_hasDVBT = true;
 961                         state->m_hasDVBC = true;
 962                         state->m_hasSAWSW = true;
 963                         state->m_hasGPIO2 = false;
 964                         state->m_hasGPIO1 = false;
 965                         state->m_hasIRQN = false;
 966                         break;
 967                 case 0x15:
 968                         /* typeId = DRX3915K_TYPE_ID */
 969                         state->m_hasLNA = false;
 970                         state->m_hasOOB = false;
 971                         state->m_hasATV = true;
 972                         state->m_hasAudio = false;
 973                         state->m_hasDVBT = true;
 974                         state->m_hasDVBC = false;
 975                         state->m_hasSAWSW = true;
 976                         state->m_hasGPIO2 = true;
 977                         state->m_hasGPIO1 = true;
 978                         state->m_hasIRQN = false;
 979                         break;
 980                 case 0x16:
 981                         /* typeId = DRX3916K_TYPE_ID */
 982                         state->m_hasLNA = false;
 983                         state->m_hasOOB = false;
 984                         state->m_hasATV = true;
 985                         state->m_hasAudio = false;
 986                         state->m_hasDVBT = true;
 987                         state->m_hasDVBC = false;
 988                         state->m_hasSAWSW = true;
 989                         state->m_hasGPIO2 = true;
 990                         state->m_hasGPIO1 = true;
 991                         state->m_hasIRQN = false;
 992                         break;
 993                 case 0x18:
 994                         /* typeId = DRX3918K_TYPE_ID */
 995                         state->m_hasLNA = false;
 996                         state->m_hasOOB = false;
 997                         state->m_hasATV = true;
 998                         state->m_hasAudio = true;
 999                         state->m_hasDVBT = true;
1000                         state->m_hasDVBC = false;
1001                         state->m_hasSAWSW = true;
1002                         state->m_hasGPIO2 = true;
1003                         state->m_hasGPIO1 = true;
1004                         state->m_hasIRQN = false;
1005                         break;
1006                 case 0x21:
1007                         /* typeId = DRX3921K_TYPE_ID */
1008                         state->m_hasLNA = false;
1009                         state->m_hasOOB = false;
1010                         state->m_hasATV = true;
1011                         state->m_hasAudio = true;
1012                         state->m_hasDVBT = true;
1013                         state->m_hasDVBC = true;
1014                         state->m_hasSAWSW = true;
1015                         state->m_hasGPIO2 = true;
1016                         state->m_hasGPIO1 = true;
1017                         state->m_hasIRQN = false;
1018                         break;
1019                 case 0x23:
1020                         /* typeId = DRX3923K_TYPE_ID */
1021                         state->m_hasLNA = false;
1022                         state->m_hasOOB = false;
1023                         state->m_hasATV = true;
1024                         state->m_hasAudio = true;
1025                         state->m_hasDVBT = true;
1026                         state->m_hasDVBC = true;
1027                         state->m_hasSAWSW = true;
1028                         state->m_hasGPIO2 = true;
1029                         state->m_hasGPIO1 = true;
1030                         state->m_hasIRQN = false;
1031                         break;
1032                 case 0x25:
1033                         /* typeId = DRX3925K_TYPE_ID */
1034                         state->m_hasLNA = false;
1035                         state->m_hasOOB = false;
1036                         state->m_hasATV = true;
1037                         state->m_hasAudio = true;
1038                         state->m_hasDVBT = true;
1039                         state->m_hasDVBC = true;
1040                         state->m_hasSAWSW = true;
1041                         state->m_hasGPIO2 = true;
1042                         state->m_hasGPIO1 = true;
1043                         state->m_hasIRQN = false;
1044                         break;
1045                 case 0x26:
1046                         /* typeId = DRX3926K_TYPE_ID */
1047                         state->m_hasLNA = false;
1048                         state->m_hasOOB = false;
1049                         state->m_hasATV = true;
1050                         state->m_hasAudio = false;
1051                         state->m_hasDVBT = true;
1052                         state->m_hasDVBC = true;
1053                         state->m_hasSAWSW = true;
1054                         state->m_hasGPIO2 = true;
1055                         state->m_hasGPIO1 = true;
1056                         state->m_hasIRQN = false;
1057                         break;
1058                 default:
1059                         printk(KERN_ERR "drxk: DeviceID not supported = %02x\n",
1060                                ((sioTopJtagidLo >> 12) & 0xFF));
1061                         status = -1;
1062                         break;
1063                 }
1064         } while (0);
1065         return status;
1066 }
1067
1068 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1069 {
1070         int status;
1071         bool powerdown_cmd;
1072
1073         dprintk(1, "\n");
1074
1075         /* Write command */
1076         status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1077         if (status < 0)
1078                 return status;
1079         if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1080                 msleep(1);
1081
1082         powerdown_cmd =
1083             (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1084                     ((state->m_HICfgCtrl) &
1085                      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1086                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1087         if (powerdown_cmd == false) {
1088                 /* Wait until command rdy */
1089                 u32 retryCount = 0;
1090                 u16 waitCmd;
1091
1092                 do {
1093                         msleep(1);
1094                         retryCount += 1;
1095                         status = read16(state, SIO_HI_RA_RAM_CMD__A,
1096                                           &waitCmd);
1097                 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1098                          && (waitCmd != 0));
1099
1100                 if (status == 0)
1101                         status = read16(state, SIO_HI_RA_RAM_RES__A,
1102                                         pResult);
1103         }
1104         return status;
1105 }
1106
1107 static int HI_CfgCommand(struct drxk_state *state)
1108 {
1109         int status;
1110
1111         dprintk(1, "\n");
1112
1113         mutex_lock(&state->mutex);
1114         do {
1115                 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1116                 if (status < 0)
1117                         break;
1118                 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1119                 if (status < 0)
1120                         break;
1121                 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1122                 if (status < 0)
1123                         break;
1124                 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1125                 if (status < 0)
1126                         break;
1127                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1128                 if (status < 0)
1129                         break;
1130                 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1131                 if (status < 0)
1132                         break;
1133                 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1134                 if (status < 0)
1135                         break;
1136
1137                 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1138         } while (0);
1139         mutex_unlock(&state->mutex);
1140         return status;
1141 }
1142
1143 static int InitHI(struct drxk_state *state)
1144 {
1145         dprintk(1, "\n");
1146
1147         state->m_HICfgWakeUpKey = (state->demod_address << 1);
1148         state->m_HICfgTimeout = 0x96FF;
1149         /* port/bridge/power down ctrl */
1150         state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1151         return HI_CfgCommand(state);
1152 }
1153
1154 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1155 {
1156         int status = -1;
1157         u16 sioPdrMclkCfg = 0;
1158         u16 sioPdrMdxCfg = 0;
1159
1160         dprintk(1, "\n");
1161         do {
1162                 /* stop lock indicator process */
1163                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1164                 if (status < 0)
1165                         break;
1166
1167                 /*  MPEG TS pad configuration */
1168                 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1169                 if (status < 0)
1170                         break;
1171
1172                 if (mpegEnable == false) {
1173                         /*  Set MPEG TS pads to inputmode */
1174                         status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1175                         if (status < 0)
1176                                 break;
1177                         status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1178                         if (status < 0)
1179                                 break;
1180                         status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1181                         if (status < 0)
1182                                 break;
1183                         status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1184                         if (status < 0)
1185                                 break;
1186                         status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1187                         if (status < 0)
1188                                 break;
1189                         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1190                         if (status < 0)
1191                                 break;
1192                         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1193                         if (status < 0)
1194                                 break;
1195                         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1196                         if (status < 0)
1197                                 break;
1198                         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1199                         if (status < 0)
1200                                 break;
1201                         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1202                         if (status < 0)
1203                                 break;
1204                         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1205                         if (status < 0)
1206                                 break;
1207                         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1208                         if (status < 0)
1209                                 break;
1210                 } else {
1211                         /* Enable MPEG output */
1212                         sioPdrMdxCfg =
1213                             ((state->m_TSDataStrength <<
1214                               SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1215                         sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1216                                           SIO_PDR_MCLK_CFG_DRIVE__B) |
1217                                          0x0003);
1218
1219                         status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1220                         if (status < 0)
1221                                 break;
1222                         status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);   /* Disable */
1223                         if (status < 0)
1224                                 break;
1225                         status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);   /* Disable */
1226                         if (status < 0)
1227                                 break;
1228                         if (state->m_enableParallel == true) {
1229                                 /* paralel -> enable MD1 to MD7 */
1230                                 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1231                                 if (status < 0)
1232                                         break;
1233                                 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1234                                 if (status < 0)
1235                                         break;
1236                                 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1237                                 if (status < 0)
1238                                         break;
1239                                 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1240                                 if (status < 0)
1241                                         break;
1242                                 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1243                                 if (status < 0)
1244                                         break;
1245                                 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1246                                 if (status < 0)
1247                                         break;
1248                                 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1249                                 if (status < 0)
1250                                         break;
1251                         } else {
1252                                 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1253                                                  SIO_PDR_MD0_CFG_DRIVE__B)
1254                                                 | 0x0003);
1255                                 /* serial -> disable MD1 to MD7 */
1256                                 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1257                                 if (status < 0)
1258                                         break;
1259                                 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1260                                 if (status < 0)
1261                                         break;
1262                                 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1263                                 if (status < 0)
1264                                         break;
1265                                 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1266                                 if (status < 0)
1267                                         break;
1268                                 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1269                                 if (status < 0)
1270                                         break;
1271                                 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1272                                 if (status < 0)
1273                                         break;
1274                                 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1275                                 if (status < 0)
1276                                         break;
1277                         }
1278                         status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1279                         if (status < 0)
1280                                 break;
1281                         status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1282                         if (status < 0)
1283                                 break;
1284                 }
1285                 /*  Enable MB output over MPEG pads and ctl input */
1286                 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1287                 if (status < 0)
1288                         break;
1289                 /*  Write nomagic word to enable pdr reg write */
1290                 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1291                 if (status < 0)
1292                         break;
1293         } while (0);
1294         return status;
1295 }
1296
1297 static int MPEGTSDisable(struct drxk_state *state)
1298 {
1299         dprintk(1, "\n");
1300
1301         return MPEGTSConfigurePins(state, false);
1302 }
1303
1304 static int BLChainCmd(struct drxk_state *state,
1305                       u16 romOffset, u16 nrOfElements, u32 timeOut)
1306 {
1307         u16 blStatus = 0;
1308         int status;
1309         unsigned long end;
1310
1311         dprintk(1, "\n");
1312
1313         mutex_lock(&state->mutex);
1314         do {
1315                 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1316                 if (status < 0)
1317                         break;
1318                 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1319                 if (status < 0)
1320                         break;
1321                 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1322                 if (status < 0)
1323                         break;
1324                 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1325                 if (status < 0)
1326                         break;
1327                 end = jiffies + msecs_to_jiffies(timeOut);
1328
1329                 do {
1330                         msleep(1);
1331                         status = read16(state, SIO_BL_STATUS__A, &blStatus);
1332                         if (status < 0)
1333                                 break;
1334                 } while ((blStatus == 0x1) &&
1335                          ((time_is_after_jiffies(end))));
1336                 if (blStatus == 0x1) {
1337                         printk(KERN_ERR "drxk: SIO not ready\n");
1338                         mutex_unlock(&state->mutex);
1339                         return -1;
1340                 }
1341         } while (0);
1342         mutex_unlock(&state->mutex);
1343         return status;
1344 }
1345
1346
1347 static int DownloadMicrocode(struct drxk_state *state,
1348                              const u8 pMCImage[], u32 Length)
1349 {
1350         const u8 *pSrc = pMCImage;
1351         u16 Flags;
1352         u16 Drain;
1353         u32 Address;
1354         u16 nBlocks;
1355         u16 BlockSize;
1356         u16 BlockCRC;
1357         u32 offset = 0;
1358         u32 i;
1359         int status = 0;
1360
1361         dprintk(1, "\n");
1362
1363         /* down the drain (we don care about MAGIC_WORD) */
1364         Drain = (pSrc[0] << 8) | pSrc[1];
1365         pSrc += sizeof(u16);
1366         offset += sizeof(u16);
1367         nBlocks = (pSrc[0] << 8) | pSrc[1];
1368         pSrc += sizeof(u16);
1369         offset += sizeof(u16);
1370
1371         for (i = 0; i < nBlocks; i += 1) {
1372                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1373                     (pSrc[2] << 8) | pSrc[3];
1374                 pSrc += sizeof(u32);
1375                 offset += sizeof(u32);
1376
1377                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1378                 pSrc += sizeof(u16);
1379                 offset += sizeof(u16);
1380
1381                 Flags = (pSrc[0] << 8) | pSrc[1];
1382                 pSrc += sizeof(u16);
1383                 offset += sizeof(u16);
1384
1385                 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1386                 pSrc += sizeof(u16);
1387                 offset += sizeof(u16);
1388                 status = write_block(state, Address, BlockSize, pSrc);
1389                 if (status < 0)
1390                         break;
1391                 pSrc += BlockSize;
1392                 offset += BlockSize;
1393         }
1394         return status;
1395 }
1396
1397 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1398 {
1399         int status;
1400         u16 data = 0;
1401         u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1402         u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1403         unsigned long end;
1404
1405         dprintk(1, "\n");
1406
1407         if (enable == false) {
1408                 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1409                 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1410         }
1411
1412         status = (read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data));
1413
1414         if (data == desiredStatus) {
1415                 /* tokenring already has correct status */
1416                 return status;
1417         }
1418         /* Disable/enable dvbt tokenring bridge   */
1419         status =
1420             write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1421
1422         end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1423         do {
1424                 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1425                 if (status < 0)
1426                         break;
1427         } while ((data != desiredStatus) && ((time_is_after_jiffies(end))));
1428         if (data != desiredStatus) {
1429                 printk(KERN_ERR "drxk: SIO not ready\n");
1430                 return -1;
1431         }
1432         return status;
1433 }
1434
1435 static int MPEGTSStop(struct drxk_state *state)
1436 {
1437         int status = 0;
1438         u16 fecOcSncMode = 0;
1439         u16 fecOcIprMode = 0;
1440
1441         dprintk(1, "\n");
1442
1443         do {
1444                 /* Gracefull shutdown (byte boundaries) */
1445                 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1446                 if (status < 0)
1447                         break;
1448                 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1449                 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1450                 if (status < 0)
1451                         break;
1452
1453                 /* Suppress MCLK during absence of data */
1454                 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1455                 if (status < 0)
1456                         break;
1457                 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1458                 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1459                 if (status < 0)
1460                         break;
1461         } while (0);
1462         return status;
1463 }
1464
1465 static int scu_command(struct drxk_state *state,
1466                        u16 cmd, u8 parameterLen,
1467                        u16 *parameter, u8 resultLen, u16 *result)
1468 {
1469 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1470 #error DRXK register mapping no longer compatible with this routine!
1471 #endif
1472         u16 curCmd = 0;
1473         int status;
1474         unsigned long end;
1475
1476         dprintk(1, "\n");
1477
1478         if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1479             ((resultLen > 0) && (result == NULL)))
1480                 return -1;
1481
1482         mutex_lock(&state->mutex);
1483         do {
1484                 /* assume that the command register is ready
1485                    since it is checked afterwards */
1486                 u8 buffer[34];
1487                 int cnt = 0, ii;
1488
1489                 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1490                         buffer[cnt++] = (parameter[ii] & 0xFF);
1491                         buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1492                 }
1493                 buffer[cnt++] = (cmd & 0xFF);
1494                 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1495
1496                 write_block(state, SCU_RAM_PARAM_0__A -
1497                            (parameterLen - 1), cnt, buffer);
1498                 /* Wait until SCU has processed command */
1499                 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1500                 do {
1501                         msleep(1);
1502                         status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1503                         if (status < 0)
1504                                 break;
1505                 } while (!(curCmd == DRX_SCU_READY)
1506                          && (time_is_after_jiffies(end)));
1507                 if (curCmd != DRX_SCU_READY) {
1508                         printk(KERN_ERR "drxk: SCU not ready\n");
1509                         mutex_unlock(&state->mutex);
1510                         return -1;
1511                 }
1512                 /* read results */
1513                 if ((resultLen > 0) && (result != NULL)) {
1514                         s16 err;
1515                         int ii;
1516
1517                         for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1518                                 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1519                                 if (status < 0)
1520                                         break;
1521                         }
1522
1523                         /* Check if an error was reported by SCU */
1524                         err = (s16) result[0];
1525
1526                         /* check a few fixed error codes */
1527                         if (err == SCU_RESULT_UNKSTD) {
1528                                 printk(KERN_ERR "drxk: SCU_RESULT_UNKSTD\n");
1529                                 mutex_unlock(&state->mutex);
1530                                 return -1;
1531                         } else if (err == SCU_RESULT_UNKCMD) {
1532                                 printk(KERN_ERR "drxk: SCU_RESULT_UNKCMD\n");
1533                                 mutex_unlock(&state->mutex);
1534                                 return -1;
1535                         }
1536                         /* here it is assumed that negative means error,
1537                            and positive no error */
1538                         else if (err < 0) {
1539                                 printk(KERN_ERR "drxk: %s ERROR\n", __func__);
1540                                 mutex_unlock(&state->mutex);
1541                                 return -1;
1542                         }
1543                 }
1544         } while (0);
1545         mutex_unlock(&state->mutex);
1546         if (status < 0)
1547                 printk(KERN_ERR "drxk: %s: status = %d\n", __func__, status);
1548
1549         return status;
1550 }
1551
1552 static int SetIqmAf(struct drxk_state *state, bool active)
1553 {
1554         u16 data = 0;
1555         int status;
1556
1557         dprintk(1, "\n");
1558
1559         do {
1560                 /* Configure IQM */
1561                 status = read16(state, IQM_AF_STDBY__A, &data);
1562                 if (status < 0)
1563                         break;
1564                 if (!active) {
1565                         data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1566                                  | IQM_AF_STDBY_STDBY_AMP_STANDBY
1567                                  | IQM_AF_STDBY_STDBY_PD_STANDBY
1568                                  | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1569                                  | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1570                 } else {        /* active */
1571
1572                         data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1573                                  & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1574                                  & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1575                                  & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1576                                  & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1577                             );
1578                 }
1579                 status = write16(state, IQM_AF_STDBY__A, data);
1580                 if (status < 0)
1581                         break;
1582         } while (0);
1583         return status;
1584 }
1585
1586 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1587 {
1588         int status = 0;
1589         u16 sioCcPwdMode = 0;
1590
1591         dprintk(1, "\n");
1592
1593         /* Check arguments */
1594         if (mode == NULL)
1595                 return -1;
1596
1597         switch (*mode) {
1598         case DRX_POWER_UP:
1599                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1600                 break;
1601         case DRXK_POWER_DOWN_OFDM:
1602                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1603                 break;
1604         case DRXK_POWER_DOWN_CORE:
1605                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1606                 break;
1607         case DRXK_POWER_DOWN_PLL:
1608                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1609                 break;
1610         case DRX_POWER_DOWN:
1611                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1612                 break;
1613         default:
1614                 /* Unknow sleep mode */
1615                 return -1;
1616                 break;
1617         }
1618
1619         /* If already in requested power mode, do nothing */
1620         if (state->m_currentPowerMode == *mode)
1621                 return 0;
1622
1623         /* For next steps make sure to start from DRX_POWER_UP mode */
1624         if (state->m_currentPowerMode != DRX_POWER_UP) {
1625                 do {
1626                         status = PowerUpDevice(state);
1627                         if (status < 0)
1628                                 break;
1629                         status = DVBTEnableOFDMTokenRing(state, true);
1630                         if (status < 0)
1631                                 break;
1632                 } while (0);
1633         }
1634
1635         if (*mode == DRX_POWER_UP) {
1636                 /* Restore analog & pin configuartion */
1637         } else {
1638                 /* Power down to requested mode */
1639                 /* Backup some register settings */
1640                 /* Set pins with possible pull-ups connected
1641                    to them in input mode */
1642                 /* Analog power down */
1643                 /* ADC power down */
1644                 /* Power down device */
1645                 /* stop all comm_exec */
1646                 /* Stop and power down previous standard */
1647                 do {
1648                         switch (state->m_OperationMode) {
1649                         case OM_DVBT:
1650                                 status = MPEGTSStop(state);
1651                                 if (status < 0)
1652                                         break;
1653                                 status = PowerDownDVBT(state, false);
1654                                 if (status < 0)
1655                                         break;
1656                                 break;
1657                         case OM_QAM_ITU_A:
1658                         case OM_QAM_ITU_C:
1659                                 status = MPEGTSStop(state);
1660                                 if (status < 0)
1661                                         break;
1662                                 status = PowerDownQAM(state);
1663                                 if (status < 0)
1664                                         break;
1665                                 break;
1666                         default:
1667                                 break;
1668                         }
1669                         status = DVBTEnableOFDMTokenRing(state, false);
1670                         if (status < 0)
1671                                 break;
1672                         status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1673                         if (status < 0)
1674                                 break;
1675                         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1676                         if (status < 0)
1677                                 break;
1678
1679                         if (*mode != DRXK_POWER_DOWN_OFDM) {
1680                                 state->m_HICfgCtrl |=
1681                                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1682                                 status = HI_CfgCommand(state);
1683                                 if (status < 0)
1684                                         break;
1685                         }
1686                 } while (0);
1687         }
1688         state->m_currentPowerMode = *mode;
1689         return status;
1690 }
1691
1692 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1693 {
1694         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1695         u16 cmdResult = 0;
1696         u16 data = 0;
1697         int status;
1698
1699         dprintk(1, "\n");
1700
1701         do {
1702                 status = read16(state, SCU_COMM_EXEC__A, &data);
1703                 if (status < 0)
1704                         break;
1705                 if (data == SCU_COMM_EXEC_ACTIVE) {
1706                         /* Send OFDM stop command */
1707                         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1708                         if (status < 0)
1709                                 break;
1710                         /* Send OFDM reset command */
1711                         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1712                         if (status < 0)
1713                                 break;
1714                 }
1715
1716                 /* Reset datapath for OFDM, processors first */
1717                 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1718                 if (status < 0)
1719                         break;
1720                 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1721                 if (status < 0)
1722                         break;
1723                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1724                 if (status < 0)
1725                         break;
1726
1727                 /* powerdown AFE                   */
1728                 status = SetIqmAf(state, false);
1729                 if (status < 0)
1730                         break;
1731
1732                 /* powerdown to OFDM mode          */
1733                 if (setPowerMode) {
1734                         status = CtrlPowerMode(state, &powerMode);
1735                         if (status < 0)
1736                                 break;
1737                 }
1738         } while (0);
1739         return status;
1740 }
1741
1742 static int SetOperationMode(struct drxk_state *state,
1743                             enum OperationMode oMode)
1744 {
1745         int status = 0;
1746
1747         dprintk(1, "\n");
1748         /*
1749            Stop and power down previous standard
1750            TODO investigate total power down instead of partial
1751            power down depending on "previous" standard.
1752          */
1753         do {
1754                 /* disable HW lock indicator */
1755                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1756                 if (status < 0)
1757                         break;
1758
1759                 if (state->m_OperationMode != oMode) {
1760                         switch (state->m_OperationMode) {
1761                                 /* OM_NONE was added for start up */
1762                         case OM_NONE:
1763                                 break;
1764                         case OM_DVBT:
1765                                 status = MPEGTSStop(state);
1766                                 if (status < 0)
1767                                         break;
1768                                 status = PowerDownDVBT(state, true);
1769                                 if (status < 0)
1770                                         break;
1771                                 state->m_OperationMode = OM_NONE;
1772                                 break;
1773                         case OM_QAM_ITU_B:
1774                                 status = -1;
1775                                 break;
1776                         case OM_QAM_ITU_A:      /* fallthrough */
1777                         case OM_QAM_ITU_C:
1778                                 status = MPEGTSStop(state);
1779                                 if (status < 0)
1780                                         break;
1781                                 status = PowerDownQAM(state);
1782                                 if (status < 0)
1783                                         break;
1784                                 state->m_OperationMode = OM_NONE;
1785                                 break;
1786                         default:
1787                                 status = -1;
1788                         }
1789                         status = status;
1790                         if (status < 0)
1791                                 break;
1792
1793                         /*
1794                            Power up new standard
1795                          */
1796                         switch (oMode) {
1797                         case OM_DVBT:
1798                                 state->m_OperationMode = oMode;
1799                                 status = SetDVBTStandard(state, oMode);
1800                                 if (status < 0)
1801                                         break;
1802                                 break;
1803                         case OM_QAM_ITU_B:
1804                                 status = -1;
1805                                 break;
1806                         case OM_QAM_ITU_A:      /* fallthrough */
1807                         case OM_QAM_ITU_C:
1808                                 state->m_OperationMode = oMode;
1809                                 status = SetQAMStandard(state, oMode);
1810                                 if (status < 0)
1811                                         break;
1812                                 break;
1813                         default:
1814                                 status = -1;
1815                         }
1816                 }
1817                 status = status;
1818                 if (status < 0)
1819                         break;
1820         } while (0);
1821         return 0;
1822 }
1823
1824 static int Start(struct drxk_state *state, s32 offsetFreq,
1825                  s32 IntermediateFrequency)
1826 {
1827         int status = 0;
1828
1829         dprintk(1, "\n");
1830         do {
1831                 u16 IFreqkHz;
1832                 s32 OffsetkHz = offsetFreq / 1000;
1833
1834                 if (state->m_DrxkState != DRXK_STOPPED &&
1835                     state->m_DrxkState != DRXK_DTV_STARTED) {
1836                         status = -1;
1837                         break;
1838                 }
1839                 state->m_bMirrorFreqSpect =
1840                     (state->param.inversion == INVERSION_ON);
1841
1842                 if (IntermediateFrequency < 0) {
1843                         state->m_bMirrorFreqSpect =
1844                             !state->m_bMirrorFreqSpect;
1845                         IntermediateFrequency = -IntermediateFrequency;
1846                 }
1847
1848                 switch (state->m_OperationMode) {
1849                 case OM_QAM_ITU_A:
1850                 case OM_QAM_ITU_C:
1851                         IFreqkHz = (IntermediateFrequency / 1000);
1852                         status = SetQAM(state, IFreqkHz, OffsetkHz);
1853                         if (status < 0)
1854                                 break;
1855                         state->m_DrxkState = DRXK_DTV_STARTED;
1856                         break;
1857                 case OM_DVBT:
1858                         IFreqkHz = (IntermediateFrequency / 1000);
1859                         status = MPEGTSStop(state);
1860                         if (status < 0)
1861                                 break;
1862                         status = SetDVBT(state, IFreqkHz, OffsetkHz);
1863                         if (status < 0)
1864                                 break;
1865                         status = DVBTStart(state);
1866                         if (status < 0)
1867                                 break;
1868                         state->m_DrxkState = DRXK_DTV_STARTED;
1869                         break;
1870                 default:
1871                         break;
1872                 }
1873         } while (0);
1874         return status;
1875 }
1876
1877 static int ShutDown(struct drxk_state *state)
1878 {
1879         dprintk(1, "\n");
1880
1881         MPEGTSStop(state);
1882         return 0;
1883 }
1884
1885 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1886                          u32 Time)
1887 {
1888         int status = 0;
1889
1890         dprintk(1, "\n");
1891
1892         if (pLockStatus == NULL)
1893                 return -1;
1894
1895         *pLockStatus = NOT_LOCKED;
1896
1897         /* define the SCU command code */
1898         switch (state->m_OperationMode) {
1899         case OM_QAM_ITU_A:
1900         case OM_QAM_ITU_B:
1901         case OM_QAM_ITU_C:
1902                 status = GetQAMLockStatus(state, pLockStatus);
1903                 break;
1904         case OM_DVBT:
1905                 status = GetDVBTLockStatus(state, pLockStatus);
1906                 break;
1907         default:
1908                 break;
1909         }
1910         return status;
1911 }
1912
1913 static int MPEGTSStart(struct drxk_state *state)
1914 {
1915         int status = 0;
1916
1917         u16 fecOcSncMode = 0;
1918
1919         do {
1920                 /* Allow OC to sync again */
1921                 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1922                 if (status < 0)
1923                         break;
1924                 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1925                 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1926                 if (status < 0)
1927                         break;
1928                 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1929                 if (status < 0)
1930                         break;
1931         } while (0);
1932         return status;
1933 }
1934
1935 static int MPEGTSDtoInit(struct drxk_state *state)
1936 {
1937         int status = -1;
1938
1939         dprintk(1, "\n");
1940
1941         do {
1942                 /* Rate integration settings */
1943                 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1944                 if (status < 0)
1945                         break;
1946                 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1947                 if (status < 0)
1948                         break;
1949                 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1950                 if (status < 0)
1951                         break;
1952                 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1953                 if (status < 0)
1954                         break;
1955                 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1956                 if (status < 0)
1957                         break;
1958                 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1959                 if (status < 0)
1960                         break;
1961                 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1962                 if (status < 0)
1963                         break;
1964                 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1965                 if (status < 0)
1966                         break;
1967
1968                 /* Additional configuration */
1969                 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1970                 if (status < 0)
1971                         break;
1972                 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1973                 if (status < 0)
1974                         break;
1975                 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1976                 if (status < 0)
1977                         break;
1978         } while (0);
1979         return status;
1980 }
1981
1982 static int MPEGTSDtoSetup(struct drxk_state *state,
1983                           enum OperationMode oMode)
1984 {
1985         int status = -1;
1986
1987         u16 fecOcRegMode = 0;   /* FEC_OC_MODE       register value */
1988         u16 fecOcRegIprMode = 0;        /* FEC_OC_IPR_MODE   register value */
1989         u16 fecOcDtoMode = 0;   /* FEC_OC_IPR_INVERT register value */
1990         u16 fecOcFctMode = 0;   /* FEC_OC_IPR_INVERT register value */
1991         u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
1992         u16 fecOcDtoBurstLen = 188;     /* FEC_OC_IPR_INVERT register value */
1993         u32 fecOcRcnCtlRate = 0;        /* FEC_OC_IPR_INVERT register value */
1994         u16 fecOcTmdMode = 0;
1995         u16 fecOcTmdIntUpdRate = 0;
1996         u32 maxBitRate = 0;
1997         bool staticCLK = false;
1998
1999         dprintk(1, "\n");
2000
2001         do {
2002                 /* Check insertion of the Reed-Solomon parity bytes */
2003                 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2004                 if (status < 0)
2005                         break;
2006                 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2007                 if (status < 0)
2008                         break;
2009                 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2010                 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2011                 if (state->m_insertRSByte == true) {
2012                         /* enable parity symbol forward */
2013                         fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2014                         /* MVAL disable during parity bytes */
2015                         fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2016                         /* TS burst length to 204 */
2017                         fecOcDtoBurstLen = 204;
2018                 }
2019
2020                 /* Check serial or parrallel output */
2021                 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2022                 if (state->m_enableParallel == false) {
2023                         /* MPEG data output is serial -> set ipr_mode[0] */
2024                         fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2025                 }
2026
2027                 switch (oMode) {
2028                 case OM_DVBT:
2029                         maxBitRate = state->m_DVBTBitrate;
2030                         fecOcTmdMode = 3;
2031                         fecOcRcnCtlRate = 0xC00000;
2032                         staticCLK = state->m_DVBTStaticCLK;
2033                         break;
2034                 case OM_QAM_ITU_A:      /* fallthrough */
2035                 case OM_QAM_ITU_C:
2036                         fecOcTmdMode = 0x0004;
2037                         fecOcRcnCtlRate = 0xD2B4EE;     /* good for >63 Mb/s */
2038                         maxBitRate = state->m_DVBCBitrate;
2039                         staticCLK = state->m_DVBCStaticCLK;
2040                         break;
2041                 default:
2042                         status = -1;
2043                 }               /* switch (standard) */
2044                 status = status;
2045                 if (status < 0)
2046                         break;
2047
2048                 /* Configure DTO's */
2049                 if (staticCLK) {
2050                         u32 bitRate = 0;
2051
2052                         /* Rational DTO for MCLK source (static MCLK rate),
2053                            Dynamic DTO for optimal grouping
2054                            (avoid intra-packet gaps),
2055                            DTO offset enable to sync TS burst with MSTRT */
2056                         fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2057                                         FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2058                         fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2059                                         FEC_OC_FCT_MODE_VIRT_ENA__M);
2060
2061                         /* Check user defined bitrate */
2062                         bitRate = maxBitRate;
2063                         if (bitRate > 75900000UL) {     /* max is 75.9 Mb/s */
2064                                 bitRate = 75900000UL;
2065                         }
2066                         /* Rational DTO period:
2067                            dto_period = (Fsys / bitrate) - 2
2068
2069                            Result should be floored,
2070                            to make sure >= requested bitrate
2071                          */
2072                         fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2073                                                  * 1000) / bitRate);
2074                         if (fecOcDtoPeriod <= 2)
2075                                 fecOcDtoPeriod = 0;
2076                         else
2077                                 fecOcDtoPeriod -= 2;
2078                         fecOcTmdIntUpdRate = 8;
2079                 } else {
2080                         /* (commonAttr->staticCLK == false) => dynamic mode */
2081                         fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2082                         fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2083                         fecOcTmdIntUpdRate = 5;
2084                 }
2085
2086                 /* Write appropriate registers with requested configuration */
2087                 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2088                 if (status < 0)
2089                         break;
2090                 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2091                 if (status < 0)
2092                         break;
2093                 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2094                 if (status < 0)
2095                         break;
2096                 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2097                 if (status < 0)
2098                         break;
2099                 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2100                 if (status < 0)
2101                         break;
2102                 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2103                 if (status < 0)
2104                         break;
2105
2106                 /* Rate integration settings */
2107                 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2108                 if (status < 0)
2109                         break;
2110                 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2111                 if (status < 0)
2112                         break;
2113                 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2114                 if (status < 0)
2115                         break;
2116         } while (0);
2117         return status;
2118 }
2119
2120 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2121 {
2122         int status;
2123         u16 fecOcRegIprInvert = 0;
2124
2125         dprintk(1, "\n");
2126
2127         /* Data mask for the output data byte */
2128         u16 InvertDataMask =
2129             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2130             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2131             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2132             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2133
2134         /* Control selective inversion of output bits */
2135         fecOcRegIprInvert &= (~(InvertDataMask));
2136         if (state->m_invertDATA == true)
2137                 fecOcRegIprInvert |= InvertDataMask;
2138         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2139         if (state->m_invertERR == true)
2140                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2141         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2142         if (state->m_invertSTR == true)
2143                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2144         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2145         if (state->m_invertVAL == true)
2146                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2147         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2148         if (state->m_invertCLK == true)
2149                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2150         status = write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2151         return status;
2152 }
2153
2154 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2155
2156 static int SetAgcRf(struct drxk_state *state,
2157                     struct SCfgAgc *pAgcCfg, bool isDTV)
2158 {
2159         int status = 0;
2160         struct SCfgAgc *pIfAgcSettings;
2161
2162         dprintk(1, "\n");
2163
2164         if (pAgcCfg == NULL)
2165                 return -1;
2166
2167         do {
2168                 u16 data = 0;
2169
2170                 switch (pAgcCfg->ctrlMode) {
2171                 case DRXK_AGC_CTRL_AUTO:
2172
2173                         /* Enable RF AGC DAC */
2174                         status = read16(state, IQM_AF_STDBY__A, &data);
2175                         if (status < 0)
2176                                 break;
2177                         data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2178                         status = write16(state, IQM_AF_STDBY__A, data);
2179                         if (status < 0)
2180                                 break;
2181
2182                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2183                         if (status < 0)
2184                                 break;
2185
2186                         /* Enable SCU RF AGC loop */
2187                         data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2188
2189                         /* Polarity */
2190                         if (state->m_RfAgcPol)
2191                                 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2192                         else
2193                                 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2194                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2195                         if (status < 0)
2196                                 break;
2197
2198                         /* Set speed (using complementary reduction value) */
2199                         status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2200                         if (status < 0)
2201                                 break;
2202
2203                         data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2204                         data |= (~(pAgcCfg->speed <<
2205                                    SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2206                                  & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2207
2208                         status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2209                         if (status < 0)
2210                                 break;
2211
2212                         if (IsDVBT(state))
2213                                 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2214                         else if (IsQAM(state))
2215                                 pIfAgcSettings = &state->m_qamIfAgcCfg;
2216                         else
2217                                 pIfAgcSettings = &state->m_atvIfAgcCfg;
2218                         if (pIfAgcSettings == NULL)
2219                                 return -1;
2220
2221                         /* Set TOP, only if IF-AGC is in AUTO mode */
2222                         if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2223                                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2224                                 if (status < 0)
2225                                         break;
2226
2227                         /* Cut-Off current */
2228                         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2229                         if (status < 0)
2230                                 break;
2231
2232                         /* Max. output level */
2233                         status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2234                         if (status < 0)
2235                                 break;
2236
2237                         break;
2238
2239                 case DRXK_AGC_CTRL_USER:
2240                         /* Enable RF AGC DAC */
2241                         status = read16(state, IQM_AF_STDBY__A, &data);
2242                         if (status < 0)
2243                                 break;
2244                         data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2245                         status = write16(state, IQM_AF_STDBY__A, data);
2246                         if (status < 0)
2247                                 break;
2248
2249                         /* Disable SCU RF AGC loop */
2250                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2251                         if (status < 0)
2252                                 break;
2253                         data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2254                         if (state->m_RfAgcPol)
2255                                 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2256                         else
2257                                 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2258                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2259                         if (status < 0)
2260                                 break;
2261
2262                         /* SCU c.o.c. to 0, enabling full control range */
2263                         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2264                         if (status < 0)
2265                                 break;
2266
2267                         /* Write value to output pin */
2268                         status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2269                         if (status < 0)
2270                                 break;
2271                         break;
2272
2273                 case DRXK_AGC_CTRL_OFF:
2274                         /* Disable RF AGC DAC */
2275                         status = read16(state, IQM_AF_STDBY__A, &data);
2276                         if (status < 0)
2277                                 break;
2278                         data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2279                         status = write16(state, IQM_AF_STDBY__A, data);
2280                         if (status < 0)
2281                                 break;
2282
2283                         /* Disable SCU RF AGC loop */
2284                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2285                         if (status < 0)
2286                                 break;
2287                         data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2288                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2289                         if (status < 0)
2290                                 break;
2291                         break;
2292
2293                 default:
2294                         return -1;
2295
2296                 }               /* switch (agcsettings->ctrlMode) */
2297         } while (0);
2298         return status;
2299 }
2300
2301 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2302
2303 static int SetAgcIf(struct drxk_state *state,
2304                     struct SCfgAgc *pAgcCfg, bool isDTV)
2305 {
2306         u16 data = 0;
2307         int status = 0;
2308         struct SCfgAgc *pRfAgcSettings;
2309
2310         dprintk(1, "\n");
2311
2312         do {
2313                 switch (pAgcCfg->ctrlMode) {
2314                 case DRXK_AGC_CTRL_AUTO:
2315
2316                         /* Enable IF AGC DAC */
2317                         status = read16(state, IQM_AF_STDBY__A, &data);
2318                         if (status < 0)
2319                                 break;
2320                         data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2321                         status = write16(state, IQM_AF_STDBY__A, data);
2322                         if (status < 0)
2323                                 break;
2324
2325                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2326                         if (status < 0)
2327                                 break;
2328
2329                         /* Enable SCU IF AGC loop */
2330                         data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2331
2332                         /* Polarity */
2333                         if (state->m_IfAgcPol)
2334                                 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2335                         else
2336                                 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2337                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2338                         if (status < 0)
2339                                 break;
2340
2341                         /* Set speed (using complementary reduction value) */
2342                         status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2343                         if (status < 0)
2344                                 break;
2345                         data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2346                         data |= (~(pAgcCfg->speed <<
2347                                    SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2348                                  & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2349
2350                         status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2351                         if (status < 0)
2352                                 break;
2353
2354                         if (IsQAM(state))
2355                                 pRfAgcSettings = &state->m_qamRfAgcCfg;
2356                         else
2357                                 pRfAgcSettings = &state->m_atvRfAgcCfg;
2358                         if (pRfAgcSettings == NULL)
2359                                 return -1;
2360                         /* Restore TOP */
2361                         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2362                         if (status < 0)
2363                                 break;
2364                         break;
2365
2366                 case DRXK_AGC_CTRL_USER:
2367
2368                         /* Enable IF AGC DAC */
2369                         status = read16(state, IQM_AF_STDBY__A, &data);
2370                         if (status < 0)
2371                                 break;
2372                         data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2373                         status = write16(state, IQM_AF_STDBY__A, data);
2374                         if (status < 0)
2375                                 break;
2376
2377                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2378                         if (status < 0)
2379                                 break;
2380
2381                         /* Disable SCU IF AGC loop */
2382                         data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2383
2384                         /* Polarity */
2385                         if (state->m_IfAgcPol)
2386                                 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2387                         else
2388                                 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2389                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2390                         if (status < 0)
2391                                 break;
2392
2393                         /* Write value to output pin */
2394                         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2395                         if (status < 0)
2396                                 break;
2397                         break;
2398
2399                 case DRXK_AGC_CTRL_OFF:
2400
2401                         /* Disable If AGC DAC */
2402                         status = read16(state, IQM_AF_STDBY__A, &data);
2403                         if (status < 0)
2404                                 break;
2405                         data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2406                         status = write16(state, IQM_AF_STDBY__A, data);
2407                         if (status < 0)
2408                                 break;
2409
2410                         /* Disable SCU IF AGC loop */
2411                         status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2412                         if (status < 0)
2413                                 break;
2414                         data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2415                         status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2416                         if (status < 0)
2417                                 break;
2418                         break;
2419                 }               /* switch (agcSettingsIf->ctrlMode) */
2420
2421                 /* always set the top to support
2422                    configurations without if-loop */
2423                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2424                 if (status < 0)
2425                         break;
2426
2427
2428         } while (0);
2429         return status;
2430 }
2431
2432 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2433 {
2434         u16 agcDacLvl;
2435         int status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2436
2437         dprintk(1, "\n");
2438
2439         *pValue = 0;
2440
2441         if (status == 0) {
2442                 u16 Level = 0;
2443                 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2444                         Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2445                 if (Level < 14000)
2446                         *pValue = (14000 - Level) / 4;
2447                 else
2448                         *pValue = 0;
2449         }
2450         return status;
2451 }
2452
2453 static int GetQAMSignalToNoise(struct drxk_state *state,
2454                                s32 *pSignalToNoise)
2455 {
2456         int status = 0;
2457
2458         dprintk(1, "\n");
2459
2460         do {
2461                 /* MER calculation */
2462                 u16 qamSlErrPower = 0;  /* accum. error between
2463                                            raw and sliced symbols */
2464                 u32 qamSlSigPower = 0;  /* used for MER, depends of
2465                                            QAM constellation */
2466                 u32 qamSlMer = 0;       /* QAM MER */
2467
2468                 /* get the register value needed for MER */
2469                 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2470                 if (status < 0)
2471                         break;
2472
2473                 switch (state->param.u.qam.modulation) {
2474                 case QAM_16:
2475                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2476                         break;
2477                 case QAM_32:
2478                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2479                         break;
2480                 case QAM_64:
2481                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2482                         break;
2483                 case QAM_128:
2484                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2485                         break;
2486                 default:
2487                 case QAM_256:
2488                         qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2489                         break;
2490                 }
2491
2492                 if (qamSlErrPower > 0) {
2493                         qamSlMer = Log10Times100(qamSlSigPower) -
2494                             Log10Times100((u32) qamSlErrPower);
2495                 }
2496                 *pSignalToNoise = qamSlMer;
2497         } while (0);
2498         return status;
2499 }
2500
2501 static int GetDVBTSignalToNoise(struct drxk_state *state,
2502                                 s32 *pSignalToNoise)
2503 {
2504         int status = 0;
2505
2506         u16 regData = 0;
2507         u32 EqRegTdSqrErrI = 0;
2508         u32 EqRegTdSqrErrQ = 0;
2509         u16 EqRegTdSqrErrExp = 0;
2510         u16 EqRegTdTpsPwrOfs = 0;
2511         u16 EqRegTdReqSmbCnt = 0;
2512         u32 tpsCnt = 0;
2513         u32 SqrErrIQ = 0;
2514         u32 a = 0;
2515         u32 b = 0;
2516         u32 c = 0;
2517         u32 iMER = 0;
2518         u16 transmissionParams = 0;
2519
2520         dprintk(1, "\n");
2521         do {
2522                 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2523                 if (status < 0)
2524                         break;
2525                 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2526                 if (status < 0)
2527                         break;
2528                 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2529                 if (status < 0)
2530                         break;
2531                 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2532                 if (status < 0)
2533                         break;
2534                 /* Extend SQR_ERR_I operational range */
2535                 EqRegTdSqrErrI = (u32) regData;
2536                 if ((EqRegTdSqrErrExp > 11) &&
2537                     (EqRegTdSqrErrI < 0x00000FFFUL)) {
2538                         EqRegTdSqrErrI += 0x00010000UL;
2539                 }
2540                 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2541                 if (status < 0)
2542                         break;
2543                 /* Extend SQR_ERR_Q operational range */
2544                 EqRegTdSqrErrQ = (u32) regData;
2545                 if ((EqRegTdSqrErrExp > 11) &&
2546                     (EqRegTdSqrErrQ < 0x00000FFFUL))
2547                         EqRegTdSqrErrQ += 0x00010000UL;
2548
2549                 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2550                 if (status < 0)
2551                         break;
2552
2553                 /* Check input data for MER */
2554
2555                 /* MER calculation (in 0.1 dB) without math.h */
2556                 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2557                         iMER = 0;
2558                 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2559                         /* No error at all, this must be the HW reset value
2560                          * Apparently no first measurement yet
2561                          * Set MER to 0.0 */
2562                         iMER = 0;
2563                 } else {
2564                         SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2565                             EqRegTdSqrErrExp;
2566                         if ((transmissionParams &
2567                              OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2568                             == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2569                                 tpsCnt = 17;
2570                         else
2571                                 tpsCnt = 68;
2572
2573                         /* IMER = 100 * log10 (x)
2574                            where x = (EqRegTdTpsPwrOfs^2 *
2575                            EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2576
2577                            => IMER = a + b -c
2578                            where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2579                            b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2580                            c = 100 * log10 (SqrErrIQ)
2581                          */
2582
2583                         /* log(x) x = 9bits * 9bits->18 bits  */
2584                         a = Log10Times100(EqRegTdTpsPwrOfs *
2585                                           EqRegTdTpsPwrOfs);
2586                         /* log(x) x = 16bits * 7bits->23 bits  */
2587                         b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2588                         /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2589                         c = Log10Times100(SqrErrIQ);
2590
2591                         iMER = a + b;
2592                         /* No negative MER, clip to zero */
2593                         if (iMER > c)
2594                                 iMER -= c;
2595                         else
2596                                 iMER = 0;
2597                 }
2598                 *pSignalToNoise = iMER;
2599         } while (0);
2600
2601         return status;
2602 }
2603
2604 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2605 {
2606         dprintk(1, "\n");
2607
2608         *pSignalToNoise = 0;
2609         switch (state->m_OperationMode) {
2610         case OM_DVBT:
2611                 return GetDVBTSignalToNoise(state, pSignalToNoise);
2612         case OM_QAM_ITU_A:
2613         case OM_QAM_ITU_C:
2614                 return GetQAMSignalToNoise(state, pSignalToNoise);
2615         default:
2616                 break;
2617         }
2618         return 0;
2619 }
2620
2621 #if 0
2622 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2623 {
2624         /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2625         int status = 0;
2626
2627         dprintk(1, "\n");
2628
2629         static s32 QE_SN[] = {
2630                 51,             /* QPSK 1/2 */
2631                 69,             /* QPSK 2/3 */
2632                 79,             /* QPSK 3/4 */
2633                 89,             /* QPSK 5/6 */
2634                 97,             /* QPSK 7/8 */
2635                 108,            /* 16-QAM 1/2 */
2636                 131,            /* 16-QAM 2/3 */
2637                 146,            /* 16-QAM 3/4 */
2638                 156,            /* 16-QAM 5/6 */
2639                 160,            /* 16-QAM 7/8 */
2640                 165,            /* 64-QAM 1/2 */
2641                 187,            /* 64-QAM 2/3 */
2642                 202,            /* 64-QAM 3/4 */
2643                 216,            /* 64-QAM 5/6 */
2644                 225,            /* 64-QAM 7/8 */
2645         };
2646
2647         *pQuality = 0;
2648
2649         do {
2650                 s32 SignalToNoise = 0;
2651                 u16 Constellation = 0;
2652                 u16 CodeRate = 0;
2653                 u32 SignalToNoiseRel;
2654                 u32 BERQuality;
2655
2656                 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2657                 if (status < 0)
2658                         break;
2659                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2660                 if (status < 0)
2661                         break;
2662                 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2663
2664                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2665                 if (status < 0)
2666                         break;
2667                 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2668
2669                 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2670                     CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2671                         break;
2672                 SignalToNoiseRel = SignalToNoise -
2673                     QE_SN[Constellation * 5 + CodeRate];
2674                 BERQuality = 100;
2675
2676                 if (SignalToNoiseRel < -70)
2677                         *pQuality = 0;
2678                 else if (SignalToNoiseRel < 30)
2679                         *pQuality = ((SignalToNoiseRel + 70) *
2680                                      BERQuality) / 100;
2681                 else
2682                         *pQuality = BERQuality;
2683         } while (0);
2684         return 0;
2685 };
2686
2687 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2688 {
2689         int status = 0;
2690         *pQuality = 0;
2691
2692         dprintk(1, "\n");
2693
2694         do {
2695                 u32 SignalToNoise = 0;
2696                 u32 BERQuality = 100;
2697                 u32 SignalToNoiseRel = 0;
2698
2699                 status = GetQAMSignalToNoise(state, &SignalToNoise);
2700                 if (status < 0)
2701                         break;
2702
2703                 switch (state->param.u.qam.modulation) {
2704                 case QAM_16:
2705                         SignalToNoiseRel = SignalToNoise - 200;
2706                         break;
2707                 case QAM_32:
2708                         SignalToNoiseRel = SignalToNoise - 230;
2709                         break;  /* Not in NorDig */
2710                 case QAM_64:
2711                         SignalToNoiseRel = SignalToNoise - 260;
2712                         break;
2713                 case QAM_128:
2714                         SignalToNoiseRel = SignalToNoise - 290;
2715                         break;
2716                 default:
2717                 case QAM_256:
2718                         SignalToNoiseRel = SignalToNoise - 320;
2719                         break;
2720                 }
2721
2722                 if (SignalToNoiseRel < -70)
2723                         *pQuality = 0;
2724                 else if (SignalToNoiseRel < 30)
2725                         *pQuality = ((SignalToNoiseRel + 70) *
2726                                      BERQuality) / 100;
2727                 else
2728                         *pQuality = BERQuality;
2729         } while (0);
2730
2731         return status;
2732 }
2733
2734 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2735 {
2736         dprintk(1, "\n");
2737
2738         switch (state->m_OperationMode) {
2739         case OM_DVBT:
2740                 return GetDVBTQuality(state, pQuality);
2741         case OM_QAM_ITU_A:
2742                 return GetDVBCQuality(state, pQuality);
2743         default:
2744                 break;
2745         }
2746
2747         return 0;
2748 }
2749 #endif
2750
2751 /* Free data ram in SIO HI */
2752 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2753 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2754
2755 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2756 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2757 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2758 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2759
2760 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2761 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2762 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2763
2764 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2765 {
2766         int status;
2767
2768         dprintk(1, "\n");
2769
2770         if (state->m_DrxkState == DRXK_UNINITIALIZED)
2771                 return -1;
2772         if (state->m_DrxkState == DRXK_POWERED_DOWN)
2773                 return -1;
2774
2775         do {
2776                 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2777                 if (status < 0)
2778                         break;
2779                 if (bEnableBridge) {
2780                         status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2781                         if (status < 0)
2782                                 break;
2783                 } else {
2784                         status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2785                         if (status < 0)
2786                                 break;
2787                 }
2788
2789                 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2790                 if (status < 0)
2791                         break;
2792         } while (0);
2793         return status;
2794 }
2795
2796 static int SetPreSaw(struct drxk_state *state,
2797                      struct SCfgPreSaw *pPreSawCfg)
2798 {
2799         int status;
2800
2801         dprintk(1, "\n");
2802
2803         if ((pPreSawCfg == NULL)
2804             || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2805                 return -1;
2806
2807         status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2808         return status;
2809 }
2810
2811 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2812                        u16 romOffset, u16 nrOfElements, u32 timeOut)
2813 {
2814         u16 blStatus = 0;
2815         u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2816         u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2817         int status;
2818         unsigned long end;
2819
2820         dprintk(1, "\n");
2821
2822         mutex_lock(&state->mutex);
2823         do {
2824                 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2825                 if (status < 0)
2826                         break;
2827                 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2828                 if (status < 0)
2829                         break;
2830                 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2831                 if (status < 0)
2832                         break;
2833                 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2834                 if (status < 0)
2835                         break;
2836                 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2837                 if (status < 0)
2838                         break;
2839                 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2840                 if (status < 0)
2841                         break;
2842
2843                 end = jiffies + msecs_to_jiffies(timeOut);
2844                 do {
2845                         status = read16(state, SIO_BL_STATUS__A, &blStatus);
2846                         if (status < 0)
2847                                 break;
2848                 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2849                 if (blStatus == 0x1) {
2850                         printk(KERN_ERR "drxk: SIO not ready\n");
2851                         mutex_unlock(&state->mutex);
2852                         return -1;
2853                 }
2854         } while (0);
2855         mutex_unlock(&state->mutex);
2856         return status;
2857
2858 }
2859
2860 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2861 {
2862         u16 data = 0;
2863         int status;
2864
2865         dprintk(1, "\n");
2866
2867         do {
2868                 /* Start measurement */
2869                 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2870                 if (status < 0)
2871                         break;
2872                 status = write16(state, IQM_AF_START_LOCK__A, 1);
2873                 if (status < 0)
2874                         break;
2875
2876                 *count = 0;
2877                 status = read16(state, IQM_AF_PHASE0__A, &data);
2878                 if (status < 0)
2879                         break;
2880                 if (data == 127)
2881                         *count = *count + 1;
2882                 status = read16(state, IQM_AF_PHASE1__A, &data);
2883                 if (status < 0)
2884                         break;
2885                 if (data == 127)
2886                         *count = *count + 1;
2887                 status = read16(state, IQM_AF_PHASE2__A, &data);
2888                 if (status < 0)
2889                         break;
2890                 if (data == 127)
2891                         *count = *count + 1;
2892         } while (0);
2893         return status;
2894 }
2895
2896 static int ADCSynchronization(struct drxk_state *state)
2897 {
2898         u16 count = 0;
2899         int status;
2900
2901         dprintk(1, "\n");
2902
2903         do {
2904                 status = ADCSyncMeasurement(state, &count);
2905                 if (status < 0)
2906                         break;
2907
2908                 if (count == 1) {
2909                         /* Try sampling on a diffrent edge */
2910                         u16 clkNeg = 0;
2911
2912                         status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2913                         if (status < 0)
2914                                 break;
2915                         if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2916                             IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2917                                 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2918                                 clkNeg |=
2919                                     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2920                         } else {
2921                                 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2922                                 clkNeg |=
2923                                     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2924                         }
2925                         status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2926                         if (status < 0)
2927                                 break;
2928                         status = ADCSyncMeasurement(state, &count);
2929                         if (status < 0)
2930                                 break;
2931                 }
2932
2933                 if (count < 2)
2934                         status = -1;
2935         } while (0);
2936         return status;
2937 }
2938
2939 static int SetFrequencyShifter(struct drxk_state *state,
2940                                u16 intermediateFreqkHz,
2941                                s32 tunerFreqOffset, bool isDTV)
2942 {
2943         bool selectPosImage = false;
2944         u32 rfFreqResidual = tunerFreqOffset;
2945         u32 fmFrequencyShift = 0;
2946         bool tunerMirror = !state->m_bMirrorFreqSpect;
2947         u32 adcFreq;
2948         bool adcFlip;
2949         int status;
2950         u32 ifFreqActual;
2951         u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
2952         u32 frequencyShift;
2953         bool imageToSelect;
2954
2955         dprintk(1, "\n");
2956
2957         /*
2958            Program frequency shifter
2959            No need to account for mirroring on RF
2960          */
2961         if (isDTV) {
2962                 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
2963                     (state->m_OperationMode == OM_QAM_ITU_C) ||
2964                     (state->m_OperationMode == OM_DVBT))
2965                         selectPosImage = true;
2966                 else
2967                         selectPosImage = false;
2968         }
2969         if (tunerMirror)
2970                 /* tuner doesn't mirror */
2971                 ifFreqActual = intermediateFreqkHz +
2972                     rfFreqResidual + fmFrequencyShift;
2973         else
2974                 /* tuner mirrors */
2975                 ifFreqActual = intermediateFreqkHz -
2976                     rfFreqResidual - fmFrequencyShift;
2977         if (ifFreqActual > samplingFrequency / 2) {
2978                 /* adc mirrors */
2979                 adcFreq = samplingFrequency - ifFreqActual;
2980                 adcFlip = true;
2981         } else {
2982                 /* adc doesn't mirror */
2983                 adcFreq = ifFreqActual;
2984                 adcFlip = false;
2985         }
2986
2987         frequencyShift = adcFreq;
2988         imageToSelect = state->m_rfmirror ^ tunerMirror ^
2989             adcFlip ^ selectPosImage;
2990         state->m_IqmFsRateOfs =
2991             Frac28a((frequencyShift), samplingFrequency);
2992
2993         if (imageToSelect)
2994                 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
2995
2996         /* Program frequency shifter with tuner offset compensation */
2997         /* frequencyShift += tunerFreqOffset; TODO */
2998         status = write32(state, IQM_FS_RATE_OFS_LO__A,
2999                          state->m_IqmFsRateOfs);
3000         return status;
3001 }
3002
3003 static int InitAGC(struct drxk_state *state, bool isDTV)
3004 {
3005         u16 ingainTgt = 0;
3006         u16 ingainTgtMin = 0;
3007         u16 ingainTgtMax = 0;
3008         u16 clpCyclen = 0;
3009         u16 clpSumMin = 0;
3010         u16 clpDirTo = 0;
3011         u16 snsSumMin = 0;
3012         u16 snsSumMax = 0;
3013         u16 clpSumMax = 0;
3014         u16 snsDirTo = 0;
3015         u16 kiInnergainMin = 0;
3016         u16 ifIaccuHiTgt = 0;
3017         u16 ifIaccuHiTgtMin = 0;
3018         u16 ifIaccuHiTgtMax = 0;
3019         u16 data = 0;
3020         u16 fastClpCtrlDelay = 0;
3021         u16 clpCtrlMode = 0;
3022         int status = 0;
3023
3024         dprintk(1, "\n");
3025
3026         do {
3027                 /* Common settings */
3028                 snsSumMax = 1023;
3029                 ifIaccuHiTgtMin = 2047;
3030                 clpCyclen = 500;
3031                 clpSumMax = 1023;
3032
3033                 if (IsQAM(state)) {
3034                         /* Standard specific settings */
3035                         clpSumMin = 8;
3036                         clpDirTo = (u16) -9;
3037                         clpCtrlMode = 0;
3038                         snsSumMin = 8;
3039                         snsDirTo = (u16) -9;
3040                         kiInnergainMin = (u16) -1030;
3041                 } else
3042                         status = -1;
3043                 status = (status);
3044                 if (status < 0)
3045                         break;
3046                 if (IsQAM(state)) {
3047                         ifIaccuHiTgtMax = 0x2380;
3048                         ifIaccuHiTgt = 0x2380;
3049                         ingainTgtMin = 0x0511;
3050                         ingainTgt = 0x0511;
3051                         ingainTgtMax = 5119;
3052                         fastClpCtrlDelay =
3053                             state->m_qamIfAgcCfg.FastClipCtrlDelay;
3054                 } else {
3055                         ifIaccuHiTgtMax = 0x1200;
3056                         ifIaccuHiTgt = 0x1200;
3057                         ingainTgtMin = 13424;
3058                         ingainTgt = 13424;
3059                         ingainTgtMax = 30000;
3060                         fastClpCtrlDelay =
3061                             state->m_dvbtIfAgcCfg.FastClipCtrlDelay;
3062                 }
3063                 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3064                 if (status < 0)
3065                         break;
3066
3067                 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3068                 if (status < 0)
3069                         break;
3070                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3071                 if (status < 0)
3072                         break;
3073                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3074                 if (status < 0)
3075                         break;
3076                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3077                 if (status < 0)
3078                         break;
3079                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3080                 if (status < 0)
3081                         break;
3082                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3083                 if (status < 0)
3084                         break;
3085                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3086                 if (status < 0)
3087                         break;
3088                 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3089                 if (status < 0)
3090                         break;
3091                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3092                 if (status < 0)
3093                         break;
3094                 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3095                 if (status < 0)
3096                         break;
3097                 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3098                 if (status < 0)
3099                         break;
3100                 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3101                 if (status < 0)
3102                         break;
3103
3104                 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3105                 if (status < 0)
3106                         break;
3107                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3108                 if (status < 0)
3109                         break;
3110                 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3111                 if (status < 0)
3112                         break;
3113
3114                 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3115                 if (status < 0)
3116                         break;
3117                 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3118                 if (status < 0)
3119                         break;
3120                 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3121                 if (status < 0)
3122                         break;
3123
3124                 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3125                 if (status < 0)
3126                         break;
3127                 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3128                 if (status < 0)
3129                         break;
3130                 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3131                 if (status < 0)
3132                         break;
3133                 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3134                 if (status < 0)
3135                         break;
3136                 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3137                 if (status < 0)
3138                         break;
3139                 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3140                 if (status < 0)
3141                         break;
3142                 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3143                 if (status < 0)
3144                         break;
3145                 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3146                 if (status < 0)
3147                         break;
3148                 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3149                 if (status < 0)
3150                         break;
3151                 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3152                 if (status < 0)
3153                         break;
3154                 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3155                 if (status < 0)
3156                         break;
3157                 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3158                 if (status < 0)
3159                         break;
3160                 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3161                 if (status < 0)
3162                         break;
3163                 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3164                 if (status < 0)
3165                         break;
3166                 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3167                 if (status < 0)
3168                         break;
3169                 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3170                 if (status < 0)
3171                         break;
3172                 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3173                 if (status < 0)
3174                         break;
3175                 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3176                 if (status < 0)
3177                         break;
3178                 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3179                 if (status < 0)
3180                         break;
3181
3182                 /* Initialize inner-loop KI gain factors */
3183                 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3184                 if (status < 0)
3185                         break;
3186                 if (IsQAM(state)) {
3187                         data = 0x0657;
3188                         data &= ~SCU_RAM_AGC_KI_RF__M;
3189                         data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3190                         data &= ~SCU_RAM_AGC_KI_IF__M;
3191                         data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3192                 }
3193                 status = write16(state, SCU_RAM_AGC_KI__A, data);
3194                 if (status < 0)
3195                         break;
3196         } while (0);
3197         return status;
3198 }
3199
3200 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3201 {
3202         int status;
3203
3204         dprintk(1, "\n");
3205         do {
3206                 if (packetErr == NULL) {
3207                         status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3208                         if (status < 0)
3209                                 break;
3210                 } else {
3211                         status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3212                         if (status < 0)
3213                                 break;
3214                 }
3215         } while (0);
3216         return status;
3217 }
3218
3219 static int DVBTScCommand(struct drxk_state *state,
3220                          u16 cmd, u16 subcmd,
3221                          u16 param0, u16 param1, u16 param2,
3222                          u16 param3, u16 param4)
3223 {
3224         u16 curCmd = 0;
3225         u16 errCode = 0;
3226         u16 retryCnt = 0;
3227         u16 scExec = 0;
3228         int status;
3229
3230         dprintk(1, "\n");
3231         status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3232         if (scExec != 1) {
3233                 /* SC is not running */
3234                 return -1;
3235         }
3236
3237         /* Wait until sc is ready to receive command */
3238         retryCnt = 0;
3239         do {
3240                 msleep(1);
3241                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3242                 retryCnt++;
3243         } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3244         if (retryCnt >= DRXK_MAX_RETRIES)
3245                 return -1;
3246         /* Write sub-command */
3247         switch (cmd) {
3248                 /* All commands using sub-cmd */
3249         case OFDM_SC_RA_RAM_CMD_PROC_START:
3250         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3251         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3252                 status =
3253                     write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3254                 break;
3255         default:
3256                 /* Do nothing */
3257                 break;
3258         }                       /* switch (cmd->cmd) */
3259
3260         /* Write needed parameters and the command */
3261         switch (cmd) {
3262                 /* All commands using 5 parameters */
3263                 /* All commands using 4 parameters */
3264                 /* All commands using 3 parameters */
3265                 /* All commands using 2 parameters */
3266         case OFDM_SC_RA_RAM_CMD_PROC_START:
3267         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3268         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3269                 status =
3270                     write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3271                 /* All commands using 1 parameters */
3272         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3273         case OFDM_SC_RA_RAM_CMD_USER_IO:
3274                 status =
3275                     write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3276                 /* All commands using 0 parameters */
3277         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3278         case OFDM_SC_RA_RAM_CMD_NULL:
3279                 /* Write command */
3280                 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3281                 break;
3282         default:
3283                 /* Unknown command */
3284                 return -EINVAL;
3285         }                       /* switch (cmd->cmd) */
3286
3287         /* Wait until sc is ready processing command */
3288         retryCnt = 0;
3289         do {
3290                 msleep(1);
3291                 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3292                 retryCnt++;
3293         } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3294         if (retryCnt >= DRXK_MAX_RETRIES)
3295                 return -1;
3296
3297         /* Check for illegal cmd */
3298         status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3299         if (errCode == 0xFFFF) {
3300                 /* illegal command */
3301                 return -EINVAL;
3302         }
3303
3304         /* Retreive results parameters from SC */
3305         switch (cmd) {
3306                 /* All commands yielding 5 results */
3307                 /* All commands yielding 4 results */
3308                 /* All commands yielding 3 results */
3309                 /* All commands yielding 2 results */
3310                 /* All commands yielding 1 result */
3311         case OFDM_SC_RA_RAM_CMD_USER_IO:
3312         case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3313                 status =
3314                     read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3315                 /* All commands yielding 0 results */
3316         case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3317         case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3318         case OFDM_SC_RA_RAM_CMD_PROC_START:
3319         case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3320         case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3321         case OFDM_SC_RA_RAM_CMD_NULL:
3322                 break;
3323         default:
3324                 /* Unknown command */
3325                 return -EINVAL;
3326                 break;
3327         }                       /* switch (cmd->cmd) */
3328         return status;
3329 }
3330
3331 static int PowerUpDVBT(struct drxk_state *state)
3332 {
3333         enum DRXPowerMode powerMode = DRX_POWER_UP;
3334         int status;
3335
3336         dprintk(1, "\n");
3337         do {
3338                 status = CtrlPowerMode(state, &powerMode);
3339                 if (status < 0)
3340                         break;
3341         } while (0);
3342         return status;
3343 }
3344
3345 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3346 {
3347         int status;
3348
3349         dprintk(1, "\n");
3350         if (*enabled == true)
3351                 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3352         else
3353                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3354
3355         return status;
3356 }
3357
3358 #define DEFAULT_FR_THRES_8K     4000
3359 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3360 {
3361
3362         int status;
3363
3364         dprintk(1, "\n");
3365         if (*enabled == true) {
3366                 /* write mask to 1 */
3367                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3368                                    DEFAULT_FR_THRES_8K);
3369         } else {
3370                 /* write mask to 0 */
3371                 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3372         }
3373
3374         return status;
3375 }
3376
3377 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3378                                     struct DRXKCfgDvbtEchoThres_t *echoThres)
3379 {
3380         u16 data = 0;
3381         int status;
3382
3383         dprintk(1, "\n");
3384         do {
3385                 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3386                 if (status < 0)
3387                         break;
3388
3389                 switch (echoThres->fftMode) {
3390                 case DRX_FFTMODE_2K:
3391                         data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3392                         data |=
3393                             ((echoThres->threshold <<
3394                               OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3395                              & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3396                         break;
3397                 case DRX_FFTMODE_8K:
3398                         data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3399                         data |=
3400                             ((echoThres->threshold <<
3401                               OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3402                              & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3403                         break;
3404                 default:
3405                         return -1;
3406                         break;
3407                 }
3408
3409                 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3410                 if (status < 0)
3411                         break;
3412         } while (0);
3413
3414         return status;
3415 }
3416
3417 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3418                                enum DRXKCfgDvbtSqiSpeed *speed)
3419 {
3420         int status;
3421
3422         dprintk(1, "\n");
3423
3424         switch (*speed) {
3425         case DRXK_DVBT_SQI_SPEED_FAST:
3426         case DRXK_DVBT_SQI_SPEED_MEDIUM:
3427         case DRXK_DVBT_SQI_SPEED_SLOW:
3428                 break;
3429         default:
3430                 return -EINVAL;
3431         }
3432         status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3433                            (u16) *speed);
3434         return status;
3435 }
3436
3437 /*============================================================================*/
3438
3439 /**
3440 * \brief Activate DVBT specific presets
3441 * \param demod instance of demodulator.
3442 * \return DRXStatus_t.
3443 *
3444 * Called in DVBTSetStandard
3445 *
3446 */
3447 static int DVBTActivatePresets(struct drxk_state *state)
3448 {
3449         int status;
3450
3451         struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3452         struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3453
3454         dprintk(1, "\n");
3455         do {
3456                 bool setincenable = false;
3457                 bool setfrenable = true;
3458                 status = DVBTCtrlSetIncEnable(state, &setincenable);
3459                 if (status < 0)
3460                         break;
3461                 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3462                 if (status < 0)
3463                         break;
3464                 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3465                 if (status < 0)
3466                         break;
3467                 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3468                 if (status < 0)
3469                         break;
3470                 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3471                 if (status < 0)
3472                         break;
3473         } while (0);
3474
3475         return status;
3476 }
3477
3478 /*============================================================================*/
3479
3480 /**
3481 * \brief Initialize channelswitch-independent settings for DVBT.
3482 * \param demod instance of demodulator.
3483 * \return DRXStatus_t.
3484 *
3485 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3486 * the DVB-T taps from the drxk_filters.h are used.
3487 */
3488 static int SetDVBTStandard(struct drxk_state *state,
3489                            enum OperationMode oMode)
3490 {
3491         u16 cmdResult = 0;
3492         u16 data = 0;
3493         int status;
3494
3495         dprintk(1, "\n");
3496
3497         PowerUpDVBT(state);
3498         do {
3499                 /* added antenna switch */
3500                 SwitchAntennaToDVBT(state);
3501                 /* send OFDM reset command */
3502                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3503                 if (status < 0)
3504                         break;
3505
3506                 /* send OFDM setenv command */
3507                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3508                 if (status < 0)
3509                         break;
3510
3511                 /* reset datapath for OFDM, processors first */
3512                 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3513                 if (status < 0)
3514                         break;
3515                 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3516                 if (status < 0)
3517                         break;
3518                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3519                 if (status < 0)
3520                         break;
3521
3522                 /* IQM setup */
3523                 /* synchronize on ofdstate->m_festart */
3524                 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3525                 if (status < 0)
3526                         break;
3527                 /* window size for clipping ADC detection */
3528                 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3529                 if (status < 0)
3530                         break;
3531                 /* window size for for sense pre-SAW detection */
3532                 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3533                 if (status < 0)
3534                         break;
3535                 /* sense threshold for sense pre-SAW detection */
3536                 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3537                 if (status < 0)
3538                         break;
3539                 status = SetIqmAf(state, true);
3540                 if (status < 0)
3541                         break;
3542
3543                 status = write16(state, IQM_AF_AGC_RF__A, 0);
3544                 if (status < 0)
3545                         break;
3546
3547                 /* Impulse noise cruncher setup */
3548                 status = write16(state, IQM_AF_INC_LCT__A, 0);  /* crunch in IQM_CF */
3549                 if (status < 0)
3550                         break;
3551                 status = write16(state, IQM_CF_DET_LCT__A, 0);  /* detect in IQM_CF */
3552                 if (status < 0)
3553                         break;
3554                 status = write16(state, IQM_CF_WND_LEN__A, 3);  /* peak detector window length */
3555                 if (status < 0)
3556                         break;
3557
3558                 status = write16(state, IQM_RC_STRETCH__A, 16);
3559                 if (status < 0)
3560                         break;
3561                 status = write16(state, IQM_CF_OUT_ENA__A, 0x4);        /* enable output 2 */
3562                 if (status < 0)
3563                         break;
3564                 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3565                 if (status < 0)
3566                         break;
3567                 status = write16(state, IQM_CF_SCALE__A, 1600);
3568                 if (status < 0)
3569                         break;
3570                 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3571                 if (status < 0)
3572                         break;
3573
3574                 /* virtual clipping threshold for clipping ADC detection */
3575                 status = write16(state, IQM_AF_CLP_TH__A, 448);
3576                 if (status < 0)
3577                         break;
3578                 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3579                 if (status < 0)
3580                         break;
3581
3582                 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3583                 if (status < 0)
3584                         break;
3585
3586                 status = write16(state, IQM_CF_PKDTH__A, 2);    /* peak detector threshold */
3587                 if (status < 0)
3588                         break;
3589                 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3590                 if (status < 0)
3591                         break;
3592                 /* enable power measurement interrupt */
3593                 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3594                 if (status < 0)
3595                         break;
3596                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3597                 if (status < 0)
3598                         break;
3599
3600                 /* IQM will not be reset from here, sync ADC and update/init AGC */
3601                 status = ADCSynchronization(state);
3602                 if (status < 0)
3603                         break;
3604                 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3605                 if (status < 0)
3606                         break;
3607
3608                 /* Halt SCU to enable safe non-atomic accesses */
3609                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3610                 if (status < 0)
3611                         break;
3612
3613                 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3614                 if (status < 0)
3615                         break;
3616                 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3617                 if (status < 0)
3618                         break;
3619
3620                 /* Set Noise Estimation notch width and enable DC fix */
3621                 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3622                 if (status < 0)
3623                         break;
3624                 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3625                 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3626                 if (status < 0)
3627                         break;
3628
3629                 /* Activate SCU to enable SCU commands */
3630                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3631                 if (status < 0)
3632                         break;
3633
3634                 if (!state->m_DRXK_A3_ROM_CODE) {
3635                         /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay  */
3636                         status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3637                         if (status < 0)
3638                                 break;
3639                 }
3640
3641                 /* OFDM_SC setup */
3642 #ifdef COMPILE_FOR_NONRT
3643                 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3644                 if (status < 0)
3645                         break;
3646                 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3647                 if (status < 0)
3648                         break;
3649 #endif
3650
3651                 /* FEC setup */
3652                 status = write16(state, FEC_DI_INPUT_CTL__A, 1);        /* OFDM input */
3653                 if (status < 0)
3654                         break;
3655
3656
3657 #ifdef COMPILE_FOR_NONRT
3658                 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3659                 if (status < 0)
3660                         break;
3661 #else
3662                 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3663                 if (status < 0)
3664                         break;
3665 #endif
3666                 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3667                 if (status < 0)
3668                         break;
3669
3670                 /* Setup MPEG bus */
3671                 status = MPEGTSDtoSetup(state, OM_DVBT);
3672                 if (status < 0)
3673                         break;
3674                 /* Set DVBT Presets */
3675                 status = DVBTActivatePresets(state);
3676                 if (status < 0)
3677                         break;
3678
3679         } while (0);
3680
3681         if (status < 0)
3682                 printk(KERN_ERR "drxk: %s status - %08x\n", __func__, status);
3683
3684         return status;
3685 }
3686
3687 /*============================================================================*/
3688 /**
3689 * \brief Start dvbt demodulating for channel.
3690 * \param demod instance of demodulator.
3691 * \return DRXStatus_t.
3692 */
3693 static int DVBTStart(struct drxk_state *state)
3694 {
3695         u16 param1;
3696         int status;
3697         /* DRXKOfdmScCmd_t scCmd; */
3698
3699         dprintk(1, "\n");
3700         /* Start correct processes to get in lock */
3701         /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3702         do {
3703                 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3704                 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3705                 if (status < 0)
3706                         break;
3707                 /* Start FEC OC */
3708                 status = MPEGTSStart(state);
3709                 if (status < 0)
3710                         break;
3711                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3712                 if (status < 0)
3713                         break;
3714         } while (0);
3715         return status;
3716 }
3717
3718
3719 /*============================================================================*/
3720
3721 /**
3722 * \brief Set up dvbt demodulator for channel.
3723 * \param demod instance of demodulator.
3724 * \return DRXStatus_t.
3725 * // original DVBTSetChannel()
3726 */
3727 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3728                    s32 tunerFreqOffset)
3729 {
3730         u16 cmdResult = 0;
3731         u16 transmissionParams = 0;
3732         u16 operationMode = 0;
3733         u32 iqmRcRateOfs = 0;
3734         u32 bandwidth = 0;
3735         u16 param1;
3736         int status;
3737
3738         dprintk(1, "\n");
3739         /* printk(KERN_DEBUG "drxk: %s IF =%d, TFO = %d\n", __func__, IntermediateFreqkHz, tunerFreqOffset); */
3740         do {
3741                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3742                 if (status < 0)
3743                         break;
3744
3745                 /* Halt SCU to enable safe non-atomic accesses */
3746                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3747                 if (status < 0)
3748                         break;
3749
3750                 /* Stop processors */
3751                 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3752                 if (status < 0)
3753                         break;
3754                 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3755                 if (status < 0)
3756                         break;
3757
3758                 /* Mandatory fix, always stop CP, required to set spl offset back to
3759                    hardware default (is set to 0 by ucode during pilot detection */
3760                 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3761                 if (status < 0)
3762                         break;
3763
3764                 /*== Write channel settings to device =====================================*/
3765
3766                 /* mode */
3767                 switch (state->param.u.ofdm.transmission_mode) {
3768                 case TRANSMISSION_MODE_AUTO:
3769                 default:
3770                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3771                         /* fall through , try first guess DRX_FFTMODE_8K */
3772                 case TRANSMISSION_MODE_8K:
3773                         transmissionParams |=
3774                             OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3775                         break;
3776                 case TRANSMISSION_MODE_2K:
3777                         transmissionParams |=
3778                             OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3779                         break;
3780                 }
3781
3782                 /* guard */
3783                 switch (state->param.u.ofdm.guard_interval) {
3784                 default:
3785                 case GUARD_INTERVAL_AUTO:
3786                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3787                         /* fall through , try first guess DRX_GUARD_1DIV4 */
3788                 case GUARD_INTERVAL_1_4:
3789                         transmissionParams |=
3790                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3791                         break;
3792                 case GUARD_INTERVAL_1_32:
3793                         transmissionParams |=
3794                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3795                         break;
3796                 case GUARD_INTERVAL_1_16:
3797                         transmissionParams |=
3798                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3799                         break;
3800                 case GUARD_INTERVAL_1_8:
3801                         transmissionParams |=
3802                             OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3803                         break;
3804                 }
3805
3806                 /* hierarchy */
3807                 switch (state->param.u.ofdm.hierarchy_information) {
3808                 case HIERARCHY_AUTO:
3809                 case HIERARCHY_NONE:
3810                 default:
3811                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3812                         /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3813                         /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3814                         /* break; */
3815                 case HIERARCHY_1:
3816                         transmissionParams |=
3817                             OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3818                         break;
3819                 case HIERARCHY_2:
3820                         transmissionParams |=
3821                             OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3822                         break;
3823                 case HIERARCHY_4:
3824                         transmissionParams |=
3825                             OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3826                         break;
3827                 }
3828
3829
3830                 /* constellation */
3831                 switch (state->param.u.ofdm.constellation) {
3832                 case QAM_AUTO:
3833                 default:
3834                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3835                         /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3836                 case QAM_64:
3837                         transmissionParams |=
3838                             OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3839                         break;
3840                 case QPSK:
3841                         transmissionParams |=
3842                             OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3843                         break;
3844                 case QAM_16:
3845                         transmissionParams |=
3846                             OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3847                         break;
3848                 }
3849 #if 0
3850                 /* No hierachical channels support in BDA */
3851                 /* Priority (only for hierarchical channels) */
3852                 switch (channel->priority) {
3853                 case DRX_PRIORITY_LOW:
3854                         transmissionParams |=
3855                             OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3856                         WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3857                              OFDM_EC_SB_PRIOR_LO);
3858                         break;
3859                 case DRX_PRIORITY_HIGH:
3860                         transmissionParams |=
3861                             OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3862                         WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3863                              OFDM_EC_SB_PRIOR_HI));
3864                         break;
3865                 case DRX_PRIORITY_UNKNOWN:      /* fall through */
3866                 default:
3867                         return DRX_STS_INVALID_ARG;
3868                         break;
3869                 }
3870 #else
3871                 /* Set Priorty high */
3872                 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3873                 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3874                 if (status < 0)
3875                         break;
3876 #endif
3877
3878                 /* coderate */
3879                 switch (state->param.u.ofdm.code_rate_HP) {
3880                 case FEC_AUTO:
3881                 default:
3882                         operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3883                         /* fall through , try first guess DRX_CODERATE_2DIV3 */
3884                 case FEC_2_3:
3885                         transmissionParams |=
3886                             OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3887                         break;
3888                 case FEC_1_2:
3889                         transmissionParams |=
3890                             OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3891                         break;
3892                 case FEC_3_4:
3893                         transmissionParams |=
3894                             OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3895                         break;
3896                 case FEC_5_6:
3897                         transmissionParams |=
3898                             OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3899                         break;
3900                 case FEC_7_8:
3901                         transmissionParams |=
3902                             OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3903                         break;
3904                 }
3905
3906                 /* SAW filter selection: normaly not necesarry, but if wanted
3907                    the application can select a SAW filter via the driver by using UIOs */
3908                 /* First determine real bandwidth (Hz) */
3909                 /* Also set delay for impulse noise cruncher */
3910                 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3911                    by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3912                    functions */
3913                 switch (state->param.u.ofdm.bandwidth) {
3914                 case BANDWIDTH_AUTO:
3915                 case BANDWIDTH_8_MHZ:
3916                         bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3917                         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3918                         if (status < 0)
3919                                 break;
3920                         /* cochannel protection for PAL 8 MHz */
3921                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3922                         if (status < 0)
3923                                 break;
3924                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3925                         if (status < 0)
3926                                 break;
3927                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3928                         if (status < 0)
3929                                 break;
3930                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3931                         if (status < 0)
3932                                 break;
3933                         break;
3934                 case BANDWIDTH_7_MHZ:
3935                         bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3936                         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3937                         if (status < 0)
3938                                 break;
3939                         /* cochannel protection for PAL 7 MHz */
3940                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3941                         if (status < 0)
3942                                 break;
3943                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3944                         if (status < 0)
3945                                 break;
3946                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3947                         if (status < 0)
3948                                 break;
3949                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3950                         if (status < 0)
3951                                 break;
3952                         break;
3953                 case BANDWIDTH_6_MHZ:
3954                         bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3955                         status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3956                         if (status < 0)
3957                                 break;
3958                         /* cochannel protection for NTSC 6 MHz */
3959                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3960                         if (status < 0)
3961                                 break;
3962                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
3963                         if (status < 0)
3964                                 break;
3965                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
3966                         if (status < 0)
3967                                 break;
3968                         status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3969                         if (status < 0)
3970                                 break;
3971                         break;
3972                 default:
3973                         return -EINVAL;
3974                 }
3975
3976                 if (iqmRcRateOfs == 0) {
3977                         /* Now compute IQM_RC_RATE_OFS
3978                            (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
3979                            =>
3980                            ((SysFreq / BandWidth) * (2^21)) - (2^23)
3981                          */
3982                         /* (SysFreq / BandWidth) * (2^28)  */
3983                         /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
3984                            => assert(MAX(sysClk) < 16*MIN(bandwidth))
3985                            => assert(109714272 > 48000000) = true so Frac 28 can be used  */
3986                         iqmRcRateOfs = Frac28a((u32)
3987                                                ((state->m_sysClockFreq *
3988                                                  1000) / 3), bandwidth);
3989                         /* (SysFreq / BandWidth) * (2^21), rounding before truncating  */
3990                         if ((iqmRcRateOfs & 0x7fL) >= 0x40)
3991                                 iqmRcRateOfs += 0x80L;
3992                         iqmRcRateOfs = iqmRcRateOfs >> 7;
3993                         /* ((SysFreq / BandWidth) * (2^21)) - (2^23)  */
3994                         iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
3995                 }
3996
3997                 iqmRcRateOfs &=
3998                     ((((u32) IQM_RC_RATE_OFS_HI__M) <<
3999                       IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4000                 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4001                 if (status < 0)
4002                         break;
4003
4004                 /* Bandwidth setting done */
4005
4006 #if 0
4007                 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4008                 if (status < 0)
4009                         break;
4010 #endif
4011                 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4012                 if (status < 0)
4013                         break;
4014
4015                 /*== Start SC, write channel settings to SC ===============================*/
4016
4017                 /* Activate SCU to enable SCU commands */
4018                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4019                 if (status < 0)
4020                         break;
4021
4022                 /* Enable SC after setting all other parameters */
4023                 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4024                 if (status < 0)
4025                         break;
4026                 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4027                 if (status < 0)
4028                         break;
4029
4030
4031                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4032                 if (status < 0)
4033                         break;
4034
4035                 /* Write SC parameter registers, set all AUTO flags in operation mode */
4036                 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4037                           OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4038                           OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4039                           OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4040                           OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4041                 status =
4042                     DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4043                                   0, transmissionParams, param1, 0, 0, 0);
4044                 if (!state->m_DRXK_A3_ROM_CODE)
4045                         status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4046                         if (status < 0)
4047                                 break;
4048
4049         } while (0);
4050
4051         return status;
4052 }
4053
4054
4055 /*============================================================================*/
4056
4057 /**
4058 * \brief Retreive lock status .
4059 * \param demod    Pointer to demodulator instance.
4060 * \param lockStat Pointer to lock status structure.
4061 * \return DRXStatus_t.
4062 *
4063 */
4064 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4065 {
4066         int status;
4067         const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4068                                     OFDM_SC_RA_RAM_LOCK_FEC__M);
4069         const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4070         const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4071
4072         u16 ScRaRamLock = 0;
4073         u16 ScCommExec = 0;
4074
4075         dprintk(1, "\n");
4076
4077         /* driver 0.9.0 */
4078         /* Check if SC is running */
4079         status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4080         if (ScCommExec == OFDM_SC_COMM_EXEC_STOP) {
4081                 /* SC not active; return DRX_NOT_LOCKED */
4082                 *pLockStatus = NOT_LOCKED;
4083                 return status;
4084         }
4085
4086         status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4087
4088         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4089                 *pLockStatus = MPEG_LOCK;
4090         else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4091                 *pLockStatus = FEC_LOCK;
4092         else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4093                 *pLockStatus = DEMOD_LOCK;
4094         else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4095                 *pLockStatus = NEVER_LOCK;
4096         else
4097                 *pLockStatus = NOT_LOCKED;
4098
4099         return status;
4100 }
4101
4102 static int PowerUpQAM(struct drxk_state *state)
4103 {
4104         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4105         int status = 0;
4106
4107         dprintk(1, "\n");
4108         do {
4109                 status = CtrlPowerMode(state, &powerMode);
4110                 if (status < 0)
4111                         break;
4112
4113         } while (0);
4114
4115         return status;
4116 }
4117
4118
4119 /** Power Down QAM */
4120 static int PowerDownQAM(struct drxk_state *state)
4121 {
4122         u16 data = 0;
4123         u16 cmdResult;
4124         int status = 0;
4125
4126         dprintk(1, "\n");
4127         do {
4128                 status = read16(state, SCU_COMM_EXEC__A, &data);
4129                 if (status < 0)
4130                         break;
4131                 if (data == SCU_COMM_EXEC_ACTIVE) {
4132                         /*
4133                            STOP demodulator
4134                            QAM and HW blocks
4135                          */
4136                         /* stop all comstate->m_exec */
4137                         status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4138                         if (status < 0)
4139                                 break;
4140                         status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4141                         if (status < 0)
4142                                 break;
4143                 }
4144                 /* powerdown AFE                   */
4145                 status = SetIqmAf(state, false);
4146                 if (status < 0)
4147                         break;
4148         } while (0);
4149
4150         return status;
4151 }
4152
4153 /*============================================================================*/
4154
4155 /**
4156 * \brief Setup of the QAM Measurement intervals for signal quality
4157 * \param demod instance of demod.
4158 * \param constellation current constellation.
4159 * \return DRXStatus_t.
4160 *
4161 *  NOTE:
4162 *  Take into account that for certain settings the errorcounters can overflow.
4163 *  The implementation does not check this.
4164 *
4165 */
4166 static int SetQAMMeasurement(struct drxk_state *state,
4167                              enum EDrxkConstellation constellation,
4168                              u32 symbolRate)
4169 {
4170         u32 fecBitsDesired = 0; /* BER accounting period */
4171         u32 fecRsPeriodTotal = 0;       /* Total period */
4172         u16 fecRsPrescale = 0;  /* ReedSolomon Measurement Prescale */
4173         u16 fecRsPeriod = 0;    /* Value for corresponding I2C register */
4174         int status = 0;
4175
4176         dprintk(1, "\n");
4177
4178         fecRsPrescale = 1;
4179         do {
4180
4181                 /* fecBitsDesired = symbolRate [kHz] *
4182                    FrameLenght [ms] *
4183                    (constellation + 1) *
4184                    SyncLoss (== 1) *
4185                    ViterbiLoss (==1)
4186                  */
4187                 switch (constellation) {
4188                 case DRX_CONSTELLATION_QAM16:
4189                         fecBitsDesired = 4 * symbolRate;
4190                         break;
4191                 case DRX_CONSTELLATION_QAM32:
4192                         fecBitsDesired = 5 * symbolRate;
4193                         break;
4194                 case DRX_CONSTELLATION_QAM64:
4195                         fecBitsDesired = 6 * symbolRate;
4196                         break;
4197                 case DRX_CONSTELLATION_QAM128:
4198                         fecBitsDesired = 7 * symbolRate;
4199                         break;
4200                 case DRX_CONSTELLATION_QAM256:
4201                         fecBitsDesired = 8 * symbolRate;
4202                         break;
4203                 default:
4204                         status = -EINVAL;
4205                 }
4206                 status = status;
4207                 if (status < 0)
4208                         break;
4209
4210                 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz]  */
4211                 fecBitsDesired *= 500;  /* meas. period [ms] */
4212
4213                 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4214                 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4215                 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1;       /* roughly ceil */
4216
4217                 /* fecRsPeriodTotal =  fecRsPrescale * fecRsPeriod  */
4218                 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4219                 if (fecRsPrescale == 0) {
4220                         /* Divide by zero (though impossible) */
4221                         status = -1;
4222                 }
4223                 status = status;
4224                 if (status < 0)
4225                         break;
4226                 fecRsPeriod =
4227                     ((u16) fecRsPeriodTotal +
4228                      (fecRsPrescale >> 1)) / fecRsPrescale;
4229
4230                 /* write corresponding registers */
4231                 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4232                 if (status < 0)
4233                         break;
4234                 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4235                 if (status < 0)
4236                         break;
4237                 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4238                 if (status < 0)
4239                         break;
4240
4241         } while (0);
4242
4243         if (status < 0)
4244                 printk(KERN_ERR "drxk: %s: status - %08x\n", __func__, status);
4245
4246         return status;
4247 }
4248
4249 static int SetQAM16(struct drxk_state *state)
4250 {
4251         int status = 0;
4252
4253         dprintk(1, "\n");
4254         do {
4255                 /* QAM Equalizer Setup */
4256                 /* Equalizer */
4257                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4258                 if (status < 0)
4259                         break;
4260                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4261                 if (status < 0)
4262                         break;
4263                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4264                 if (status < 0)
4265                         break;
4266                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4267                 if (status < 0)
4268                         break;
4269                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4270                 if (status < 0)
4271                         break;
4272                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4273                 if (status < 0)
4274                         break;
4275                 /* Decision Feedback Equalizer */
4276                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4277                 if (status < 0)
4278                         break;
4279                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4280                 if (status < 0)
4281                         break;
4282                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4283                 if (status < 0)
4284                         break;
4285                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4286                 if (status < 0)
4287                         break;
4288                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4289                 if (status < 0)
4290                         break;
4291                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4292                 if (status < 0)
4293                         break;
4294
4295                 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4296                 if (status < 0)
4297                         break;
4298                 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4299                 if (status < 0)
4300                         break;
4301                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4302                 if (status < 0)
4303                         break;
4304
4305                 /* QAM Slicer Settings */
4306                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4307                 if (status < 0)
4308                         break;
4309
4310                 /* QAM Loop Controller Coeficients */
4311                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4312                 if (status < 0)
4313                         break;
4314                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4315                 if (status < 0)
4316                         break;
4317                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4318                 if (status < 0)
4319                         break;
4320                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4321                 if (status < 0)
4322                         break;
4323                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4324                 if (status < 0)
4325                         break;
4326                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4327                 if (status < 0)
4328                         break;
4329                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4330                 if (status < 0)
4331                         break;
4332                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4333                 if (status < 0)
4334                         break;
4335
4336                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4337                 if (status < 0)
4338                         break;
4339                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4340                 if (status < 0)
4341                         break;
4342                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4343                 if (status < 0)
4344                         break;
4345                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4346                 if (status < 0)
4347                         break;
4348                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4349                 if (status < 0)
4350                         break;
4351                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4352                 if (status < 0)
4353                         break;
4354                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4355                 if (status < 0)
4356                         break;
4357                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4358                 if (status < 0)
4359                         break;
4360                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4361                 if (status < 0)
4362                         break;
4363                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4364                 if (status < 0)
4365                         break;
4366                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4367                 if (status < 0)
4368                         break;
4369                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4370                 if (status < 0)
4371                         break;
4372
4373
4374                 /* QAM State Machine (FSM) Thresholds */
4375
4376                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4377                 if (status < 0)
4378                         break;
4379                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4380                 if (status < 0)
4381                         break;
4382                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4383                 if (status < 0)
4384                         break;
4385                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4386                 if (status < 0)
4387                         break;
4388                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4389                 if (status < 0)
4390                         break;
4391                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4392                 if (status < 0)
4393                         break;
4394
4395                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4396                 if (status < 0)
4397                         break;
4398                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4399                 if (status < 0)
4400                         break;
4401                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4402                 if (status < 0)
4403                         break;
4404
4405
4406                 /* QAM FSM Tracking Parameters */
4407
4408                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4409                 if (status < 0)
4410                         break;
4411                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4412                 if (status < 0)
4413                         break;
4414                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4415                 if (status < 0)
4416                         break;
4417                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4418                 if (status < 0)
4419                         break;
4420                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4421                 if (status < 0)
4422                         break;
4423                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4424                 if (status < 0)
4425                         break;
4426                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4427                 if (status < 0)
4428                         break;
4429         } while (0);
4430
4431         return status;
4432 }
4433
4434 /*============================================================================*/
4435
4436 /**
4437 * \brief QAM32 specific setup
4438 * \param demod instance of demod.
4439 * \return DRXStatus_t.
4440 */
4441 static int SetQAM32(struct drxk_state *state)
4442 {
4443         int status = 0;
4444
4445         dprintk(1, "\n");
4446         do {
4447                 /* QAM Equalizer Setup */
4448                 /* Equalizer */
4449                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4450                 if (status < 0)
4451                         break;
4452                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4453                 if (status < 0)
4454                         break;
4455                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4456                 if (status < 0)
4457                         break;
4458                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4459                 if (status < 0)
4460                         break;
4461                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4462                 if (status < 0)
4463                         break;
4464                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4465                 if (status < 0)
4466                         break;
4467
4468                 /* Decision Feedback Equalizer */
4469                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4470                 if (status < 0)
4471                         break;
4472                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4473                 if (status < 0)
4474                         break;
4475                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4476                 if (status < 0)
4477                         break;
4478                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4479                 if (status < 0)
4480                         break;
4481                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4482                 if (status < 0)
4483                         break;
4484                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4485                 if (status < 0)
4486                         break;
4487
4488                 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4489                 if (status < 0)
4490                         break;
4491                 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4492                 if (status < 0)
4493                         break;
4494                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4495                 if (status < 0)
4496                         break;
4497
4498                 /* QAM Slicer Settings */
4499
4500                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4501                 if (status < 0)
4502                         break;
4503
4504
4505                 /* QAM Loop Controller Coeficients */
4506
4507                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4508                 if (status < 0)
4509                         break;
4510                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4511                 if (status < 0)
4512                         break;
4513                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4514                 if (status < 0)
4515                         break;
4516                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4517                 if (status < 0)
4518                         break;
4519                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4520                 if (status < 0)
4521                         break;
4522                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4523                 if (status < 0)
4524                         break;
4525                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4526                 if (status < 0)
4527                         break;
4528                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4529                 if (status < 0)
4530                         break;
4531
4532                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4533                 if (status < 0)
4534                         break;
4535                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4536                 if (status < 0)
4537                         break;
4538                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4539                 if (status < 0)
4540                         break;
4541                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4542                 if (status < 0)
4543                         break;
4544                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4545                 if (status < 0)
4546                         break;
4547                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4548                 if (status < 0)
4549                         break;
4550                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4551                 if (status < 0)
4552                         break;
4553                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4554                 if (status < 0)
4555                         break;
4556                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4557                 if (status < 0)
4558                         break;
4559                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4560                 if (status < 0)
4561                         break;
4562                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4563                 if (status < 0)
4564                         break;
4565                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4566                 if (status < 0)
4567                         break;
4568
4569
4570                 /* QAM State Machine (FSM) Thresholds */
4571
4572                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4573                 if (status < 0)
4574                         break;
4575                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4576                 if (status < 0)
4577                         break;
4578                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4579                 if (status < 0)
4580                         break;
4581                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4582                 if (status < 0)
4583                         break;
4584                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4585                 if (status < 0)
4586                         break;
4587                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4588                 if (status < 0)
4589                         break;
4590
4591                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4592                 if (status < 0)
4593                         break;
4594                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4595                 if (status < 0)
4596                         break;
4597                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4598                 if (status < 0)
4599                         break;
4600
4601
4602                 /* QAM FSM Tracking Parameters */
4603
4604                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4605                 if (status < 0)
4606                         break;
4607                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4608                 if (status < 0)
4609                         break;
4610                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4611                 if (status < 0)
4612                         break;
4613                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4614                 if (status < 0)
4615                         break;
4616                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4617                 if (status < 0)
4618                         break;
4619                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4620                 if (status < 0)
4621                         break;
4622                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4623                 if (status < 0)
4624                         break;
4625         } while (0);
4626
4627         return status;
4628 }
4629
4630 /*============================================================================*/
4631
4632 /**
4633 * \brief QAM64 specific setup
4634 * \param demod instance of demod.
4635 * \return DRXStatus_t.
4636 */
4637 static int SetQAM64(struct drxk_state *state)
4638 {
4639         int status = 0;
4640
4641         dprintk(1, "\n");
4642         do {
4643                 /* QAM Equalizer Setup */
4644                 /* Equalizer */
4645                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4646                 if (status < 0)
4647                         break;
4648                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4649                 if (status < 0)
4650                         break;
4651                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4652                 if (status < 0)
4653                         break;
4654                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4655                 if (status < 0)
4656                         break;
4657                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4658                 if (status < 0)
4659                         break;
4660                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4661                 if (status < 0)
4662                         break;
4663
4664                 /* Decision Feedback Equalizer */
4665                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4666                 if (status < 0)
4667                         break;
4668                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4669                 if (status < 0)
4670                         break;
4671                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4672                 if (status < 0)
4673                         break;
4674                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4675                 if (status < 0)
4676                         break;
4677                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4678                 if (status < 0)
4679                         break;
4680                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4681                 if (status < 0)
4682                         break;
4683
4684                 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4685                 if (status < 0)
4686                         break;
4687                 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4688                 if (status < 0)
4689                         break;
4690                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4691                 if (status < 0)
4692                         break;
4693
4694                 /* QAM Slicer Settings */
4695                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4696                 if (status < 0)
4697                         break;
4698
4699
4700                 /* QAM Loop Controller Coeficients */
4701
4702                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4703                 if (status < 0)
4704                         break;
4705                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4706                 if (status < 0)
4707                         break;
4708                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4709                 if (status < 0)
4710                         break;
4711                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4712                 if (status < 0)
4713                         break;
4714                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4715                 if (status < 0)
4716                         break;
4717                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4718                 if (status < 0)
4719                         break;
4720                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4721                 if (status < 0)
4722                         break;
4723                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4724                 if (status < 0)
4725                         break;
4726
4727                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4728                 if (status < 0)
4729                         break;
4730                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4731                 if (status < 0)
4732                         break;
4733                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4734                 if (status < 0)
4735                         break;
4736                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4737                 if (status < 0)
4738                         break;
4739                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4740                 if (status < 0)
4741                         break;
4742                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4743                 if (status < 0)
4744                         break;
4745                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4746                 if (status < 0)
4747                         break;
4748                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4749                 if (status < 0)
4750                         break;
4751                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4752                 if (status < 0)
4753                         break;
4754                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4755                 if (status < 0)
4756                         break;
4757                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4758                 if (status < 0)
4759                         break;
4760                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4761                 if (status < 0)
4762                         break;
4763
4764
4765                 /* QAM State Machine (FSM) Thresholds */
4766
4767                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4768                 if (status < 0)
4769                         break;
4770                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4771                 if (status < 0)
4772                         break;
4773                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4774                 if (status < 0)
4775                         break;
4776                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4777                 if (status < 0)
4778                         break;
4779                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4780                 if (status < 0)
4781                         break;
4782                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4783                 if (status < 0)
4784                         break;
4785
4786                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4787                 if (status < 0)
4788                         break;
4789                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4790                 if (status < 0)
4791                         break;
4792                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4793                 if (status < 0)
4794                         break;
4795
4796
4797                 /* QAM FSM Tracking Parameters */
4798
4799                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4800                 if (status < 0)
4801                         break;
4802                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4803                 if (status < 0)
4804                         break;
4805                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4806                 if (status < 0)
4807                         break;
4808                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4809                 if (status < 0)
4810                         break;
4811                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4812                 if (status < 0)
4813                         break;
4814                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4815                 if (status < 0)
4816                         break;
4817                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4818                 if (status < 0)
4819                         break;
4820         } while (0);
4821
4822         return status;
4823 }
4824
4825 /*============================================================================*/
4826
4827 /**
4828 * \brief QAM128 specific setup
4829 * \param demod: instance of demod.
4830 * \return DRXStatus_t.
4831 */
4832 static int SetQAM128(struct drxk_state *state)
4833 {
4834         int status = 0;
4835
4836         dprintk(1, "\n");
4837         do {
4838                 /* QAM Equalizer Setup */
4839                 /* Equalizer */
4840                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4841                 if (status < 0)
4842                         break;
4843                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4844                 if (status < 0)
4845                         break;
4846                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4847                 if (status < 0)
4848                         break;
4849                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4850                 if (status < 0)
4851                         break;
4852                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4853                 if (status < 0)
4854                         break;
4855                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4856                 if (status < 0)
4857                         break;
4858
4859                 /* Decision Feedback Equalizer */
4860                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4861                 if (status < 0)
4862                         break;
4863                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4864                 if (status < 0)
4865                         break;
4866                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4867                 if (status < 0)
4868                         break;
4869                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4870                 if (status < 0)
4871                         break;
4872                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4873                 if (status < 0)
4874                         break;
4875                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4876                 if (status < 0)
4877                         break;
4878
4879                 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4880                 if (status < 0)
4881                         break;
4882                 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4883                 if (status < 0)
4884                         break;
4885                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4886                 if (status < 0)
4887                         break;
4888
4889
4890                 /* QAM Slicer Settings */
4891
4892                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4893                 if (status < 0)
4894                         break;
4895
4896
4897                 /* QAM Loop Controller Coeficients */
4898
4899                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4900                 if (status < 0)
4901                         break;
4902                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4903                 if (status < 0)
4904                         break;
4905                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4906                 if (status < 0)
4907                         break;
4908                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4909                 if (status < 0)
4910                         break;
4911                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4912                 if (status < 0)
4913                         break;
4914                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4915                 if (status < 0)
4916                         break;
4917                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4918                 if (status < 0)
4919                         break;
4920                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4921                 if (status < 0)
4922                         break;
4923
4924                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4925                 if (status < 0)
4926                         break;
4927                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4928                 if (status < 0)
4929                         break;
4930                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4931                 if (status < 0)
4932                         break;
4933                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4934                 if (status < 0)
4935                         break;
4936                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4937                 if (status < 0)
4938                         break;
4939                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4940                 if (status < 0)
4941                         break;
4942                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4943                 if (status < 0)
4944                         break;
4945                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4946                 if (status < 0)
4947                         break;
4948                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4949                 if (status < 0)
4950                         break;
4951                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4952                 if (status < 0)
4953                         break;
4954                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4955                 if (status < 0)
4956                         break;
4957                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4958                 if (status < 0)
4959                         break;
4960
4961
4962                 /* QAM State Machine (FSM) Thresholds */
4963
4964                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4965                 if (status < 0)
4966                         break;
4967                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4968                 if (status < 0)
4969                         break;
4970                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4971                 if (status < 0)
4972                         break;
4973                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4974                 if (status < 0)
4975                         break;
4976                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4977                 if (status < 0)
4978                         break;
4979                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4980                 if (status < 0)
4981                         break;
4982
4983                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4984                 if (status < 0)
4985                         break;
4986                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4987                 if (status < 0)
4988                         break;
4989
4990                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4991                 if (status < 0)
4992                         break;
4993
4994                 /* QAM FSM Tracking Parameters */
4995
4996                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4997                 if (status < 0)
4998                         break;
4999                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5000                 if (status < 0)
5001                         break;
5002                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5003                 if (status < 0)
5004                         break;
5005                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5006                 if (status < 0)
5007                         break;
5008                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5009                 if (status < 0)
5010                         break;
5011                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5012                 if (status < 0)
5013                         break;
5014                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5015                 if (status < 0)
5016                         break;
5017         } while (0);
5018
5019         return status;
5020 }
5021
5022 /*============================================================================*/
5023
5024 /**
5025 * \brief QAM256 specific setup
5026 * \param demod: instance of demod.
5027 * \return DRXStatus_t.
5028 */
5029 static int SetQAM256(struct drxk_state *state)
5030 {
5031         int status = 0;
5032
5033         dprintk(1, "\n");
5034         do {
5035                 /* QAM Equalizer Setup */
5036                 /* Equalizer */
5037                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5038                 if (status < 0)
5039                         break;
5040                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5041                 if (status < 0)
5042                         break;
5043                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5044                 if (status < 0)
5045                         break;
5046                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5047                 if (status < 0)
5048                         break;
5049                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5050                 if (status < 0)
5051                         break;
5052                 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5053                 if (status < 0)
5054                         break;
5055
5056                 /* Decision Feedback Equalizer */
5057                 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5058                 if (status < 0)
5059                         break;
5060                 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5061                 if (status < 0)
5062                         break;
5063                 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5064                 if (status < 0)
5065                         break;
5066                 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5067                 if (status < 0)
5068                         break;
5069                 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5070                 if (status < 0)
5071                         break;
5072                 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5073                 if (status < 0)
5074                         break;
5075
5076                 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5077                 if (status < 0)
5078                         break;
5079                 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5080                 if (status < 0)
5081                         break;
5082                 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5083                 if (status < 0)
5084                         break;
5085
5086                 /* QAM Slicer Settings */
5087
5088                 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5089                 if (status < 0)
5090                         break;
5091
5092
5093                 /* QAM Loop Controller Coeficients */
5094
5095                 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5096                 if (status < 0)
5097                         break;
5098                 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5099                 if (status < 0)
5100                         break;
5101                 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5102                 if (status < 0)
5103                         break;
5104                 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5105                 if (status < 0)
5106                         break;
5107                 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5108                 if (status < 0)
5109                         break;
5110                 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5111                 if (status < 0)
5112                         break;
5113                 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5114                 if (status < 0)
5115                         break;
5116                 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5117                 if (status < 0)
5118                         break;
5119
5120                 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5121                 if (status < 0)
5122                         break;
5123                 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5124                 if (status < 0)
5125                         break;
5126                 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5127                 if (status < 0)
5128                         break;
5129                 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5130                 if (status < 0)
5131                         break;
5132                 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5133                 if (status < 0)
5134                         break;
5135                 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5136                 if (status < 0)
5137                         break;
5138                 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5139                 if (status < 0)
5140                         break;
5141                 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5142                 if (status < 0)
5143                         break;
5144                 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5145                 if (status < 0)
5146                         break;
5147                 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5148                 if (status < 0)
5149                         break;
5150                 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5151                 if (status < 0)
5152                         break;
5153                 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5154                 if (status < 0)
5155                         break;
5156
5157
5158                 /* QAM State Machine (FSM) Thresholds */
5159
5160                 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5161                 if (status < 0)
5162                         break;
5163                 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5164                 if (status < 0)
5165                         break;
5166                 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5167                 if (status < 0)
5168                         break;
5169                 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5170                 if (status < 0)
5171                         break;
5172                 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5173                 if (status < 0)
5174                         break;
5175                 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5176                 if (status < 0)
5177                         break;
5178
5179                 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5180                 if (status < 0)
5181                         break;
5182                 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5183                 if (status < 0)
5184                         break;
5185                 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5186                 if (status < 0)
5187                         break;
5188
5189
5190                 /* QAM FSM Tracking Parameters */
5191
5192                 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5193                 if (status < 0)
5194                         break;
5195                 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5196                 if (status < 0)
5197                         break;
5198                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5199                 if (status < 0)
5200                         break;
5201                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5202                 if (status < 0)
5203                         break;
5204                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5205                 if (status < 0)
5206                         break;
5207                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5208                 if (status < 0)
5209                         break;
5210                 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5211                 if (status < 0)
5212                         break;
5213         } while (0);
5214
5215         return status;
5216 }
5217
5218
5219 /*============================================================================*/
5220 /**
5221 * \brief Reset QAM block.
5222 * \param demod:   instance of demod.
5223 * \param channel: pointer to channel data.
5224 * \return DRXStatus_t.
5225 */
5226 static int QAMResetQAM(struct drxk_state *state)
5227 {
5228         int status;
5229         u16 cmdResult;
5230
5231         dprintk(1, "\n");
5232         do {
5233                 /* Stop QAM comstate->m_exec */
5234                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5235                 if (status < 0)
5236                         break;
5237
5238                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5239                 if (status < 0)
5240                         break;
5241         } while (0);
5242
5243         /* All done, all OK */
5244         return status;
5245 }
5246
5247 /*============================================================================*/
5248
5249 /**
5250 * \brief Set QAM symbolrate.
5251 * \param demod:   instance of demod.
5252 * \param channel: pointer to channel data.
5253 * \return DRXStatus_t.
5254 */
5255 static int QAMSetSymbolrate(struct drxk_state *state)
5256 {
5257         u32 adcFrequency = 0;
5258         u32 symbFreq = 0;
5259         u32 iqmRcRate = 0;
5260         u16 ratesel = 0;
5261         u32 lcSymbRate = 0;
5262         int status;
5263
5264         dprintk(1, "\n");
5265         do {
5266                 /* Select & calculate correct IQM rate */
5267                 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5268                 ratesel = 0;
5269                 /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */
5270                 if (state->param.u.qam.symbol_rate <= 1188750)
5271                         ratesel = 3;
5272                 else if (state->param.u.qam.symbol_rate <= 2377500)
5273                         ratesel = 2;
5274                 else if (state->param.u.qam.symbol_rate <= 4755000)
5275                         ratesel = 1;
5276                 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5277                 if (status < 0)
5278                         break;
5279
5280                 /*
5281                    IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5282                  */
5283                 symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel);
5284                 if (symbFreq == 0) {
5285                         /* Divide by zero */
5286                         return -1;
5287                 }
5288                 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5289                     (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5290                     (1 << 23);
5291                 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5292                 if (status < 0)
5293                         break;
5294                 state->m_iqmRcRate = iqmRcRate;
5295                 /*
5296                    LcSymbFreq = round (.125 *  symbolrate / adcFreq * (1<<15))
5297                  */
5298                 symbFreq = state->param.u.qam.symbol_rate;
5299                 if (adcFrequency == 0) {
5300                         /* Divide by zero */
5301                         return -1;
5302                 }
5303                 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5304                     (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5305                      16);
5306                 if (lcSymbRate > 511)
5307                         lcSymbRate = 511;
5308                 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5309                 if (status < 0)
5310                         break;
5311         } while (0);
5312
5313         return status;
5314 }
5315
5316 /*============================================================================*/
5317
5318 /**
5319 * \brief Get QAM lock status.
5320 * \param demod:   instance of demod.
5321 * \param channel: pointer to channel data.
5322 * \return DRXStatus_t.
5323 */
5324
5325 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5326 {
5327         int status;
5328         u16 Result[2] = { 0, 0 };
5329
5330         dprintk(1, "\n");
5331         status =
5332             scu_command(state,
5333                         SCU_RAM_COMMAND_STANDARD_QAM |
5334                         SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5335                         Result);
5336         if (status < 0)
5337                 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5338
5339         if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5340                 /* 0x0000 NOT LOCKED */
5341                 *pLockStatus = NOT_LOCKED;
5342         } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5343                 /* 0x4000 DEMOD LOCKED */
5344                 *pLockStatus = DEMOD_LOCK;
5345         } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5346                 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5347                 *pLockStatus = MPEG_LOCK;
5348         } else {
5349                 /* 0xC000 NEVER LOCKED */
5350                 /* (system will never be able to lock to the signal) */
5351                 /* TODO: check this, intermediate & standard specific lock states are not
5352                    taken into account here */
5353                 *pLockStatus = NEVER_LOCK;
5354         }
5355         return status;
5356 }
5357
5358 #define QAM_MIRROR__M         0x03
5359 #define QAM_MIRROR_NORMAL     0x00
5360 #define QAM_MIRRORED          0x01
5361 #define QAM_MIRROR_AUTO_ON    0x02
5362 #define QAM_LOCKRANGE__M      0x10
5363 #define QAM_LOCKRANGE_NORMAL  0x10
5364
5365 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5366                   s32 tunerFreqOffset)
5367 {
5368         int status = 0;
5369         u8 parameterLen;
5370         u16 setEnvParameters[5];
5371         u16 setParamParameters[4] = { 0, 0, 0, 0 };
5372         u16 cmdResult;
5373
5374         dprintk(1, "\n");
5375         do {
5376                 /*
5377                    STEP 1: reset demodulator
5378                    resets FEC DI and FEC RS
5379                    resets QAM block
5380                    resets SCU variables
5381                  */
5382                 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5383                 if (status < 0)
5384                         break;
5385                 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5386                 if (status < 0)
5387                         break;
5388                 status = QAMResetQAM(state);
5389                 if (status < 0)
5390                         break;
5391
5392                 /*
5393                    STEP 2: configure demodulator
5394                    -set env
5395                    -set params; resets IQM,QAM,FEC HW; initializes some SCU variables
5396                  */
5397                 status = QAMSetSymbolrate(state);
5398                 if (status < 0)
5399                         break;
5400
5401                 /* Env parameters */
5402                 setEnvParameters[2] = QAM_TOP_ANNEX_A;  /* Annex */
5403                 if (state->m_OperationMode == OM_QAM_ITU_C)
5404                         setEnvParameters[2] = QAM_TOP_ANNEX_C;  /* Annex */
5405                 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5406                 /* check for LOCKRANGE Extented */
5407                 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5408                 parameterLen = 4;
5409
5410                 /* Set params */
5411                 switch (state->param.u.qam.modulation) {
5412                 case QAM_256:
5413                         state->m_Constellation = DRX_CONSTELLATION_QAM256;
5414                         break;
5415                 case QAM_AUTO:
5416                 case QAM_64:
5417                         state->m_Constellation = DRX_CONSTELLATION_QAM64;
5418                         break;
5419                 case QAM_16:
5420                         state->m_Constellation = DRX_CONSTELLATION_QAM16;
5421                         break;
5422                 case QAM_32:
5423                         state->m_Constellation = DRX_CONSTELLATION_QAM32;
5424                         break;
5425                 case QAM_128:
5426                         state->m_Constellation = DRX_CONSTELLATION_QAM128;
5427                         break;
5428                 default:
5429                         status = -EINVAL;
5430                         break;
5431                 }
5432                 status = status;
5433                 if (status < 0)
5434                         break;
5435                 setParamParameters[0] = state->m_Constellation; /* constellation     */
5436                 setParamParameters[1] = DRXK_QAM_I12_J17;       /* interleave mode   */
5437
5438                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5439                 if (status < 0)
5440                         break;
5441
5442
5443                 /* STEP 3: enable the system in a mode where the ADC provides valid signal
5444                    setup constellation independent registers */
5445 #if 0
5446                 status = SetFrequency (channel, tunerFreqOffset));
5447                 if (status < 0)
5448                         break;
5449 #endif
5450                 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5451                 if (status < 0)
5452                         break;
5453
5454                 /* Setup BER measurement */
5455                 status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate);
5456                 if (status < 0)
5457                         break;
5458
5459                 /* Reset default values */
5460                 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5461                 if (status < 0)
5462                         break;
5463                 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5464                 if (status < 0)
5465                         break;
5466
5467                 /* Reset default LC values */
5468                 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5469                 if (status < 0)
5470                         break;
5471                 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5472                 if (status < 0)
5473                         break;
5474                 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5475                 if (status < 0)
5476                         break;
5477                 status = write16(state, QAM_LC_MODE__A, 7);
5478                 if (status < 0)
5479                         break;
5480
5481                 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5482                 if (status < 0)
5483                         break;
5484                 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5485                 if (status < 0)
5486                         break;
5487                 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5488                 if (status < 0)
5489                         break;
5490                 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5491                 if (status < 0)
5492                         break;
5493                 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5494                 if (status < 0)
5495                         break;
5496                 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5497                 if (status < 0)
5498                         break;
5499                 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5500                 if (status < 0)
5501                         break;
5502                 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5503                 if (status < 0)
5504                         break;
5505                 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5506                 if (status < 0)
5507                         break;
5508                 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5509                 if (status < 0)
5510                         break;
5511                 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5512                 if (status < 0)
5513                         break;
5514                 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5515                 if (status < 0)
5516                         break;
5517                 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5518                 if (status < 0)
5519                         break;
5520                 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5521                 if (status < 0)
5522                         break;
5523                 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5524                 if (status < 0)
5525                         break;
5526
5527                 /* Mirroring, QAM-block starting point not inverted */
5528                 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5529                 if (status < 0)
5530                         break;
5531
5532                 /* Halt SCU to enable safe non-atomic accesses */
5533                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5534                 if (status < 0)
5535                         break;
5536
5537                 /* STEP 4: constellation specific setup */
5538                 switch (state->param.u.qam.modulation) {
5539                 case QAM_16:
5540                         status = SetQAM16(state);
5541                         if (status < 0)
5542                                 break;
5543                         break;
5544                 case QAM_32:
5545                         status = SetQAM32(state);
5546                         if (status < 0)
5547                                 break;
5548                         break;
5549                 case QAM_AUTO:
5550                 case QAM_64:
5551                         status = SetQAM64(state);
5552                         if (status < 0)
5553                                 break;
5554                         break;
5555                 case QAM_128:
5556                         status = SetQAM128(state);
5557                         if (status < 0)
5558                                 break;
5559                         break;
5560                 case QAM_256:
5561                         status = SetQAM256(state);
5562                         if (status < 0)
5563                                 break;
5564                         break;
5565                 default:
5566                         return -1;
5567                         break;
5568                 }               /* switch */
5569                 /* Activate SCU to enable SCU commands */
5570                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5571                 if (status < 0)
5572                         break;
5573
5574
5575                 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5576                 /* extAttr->currentChannel.constellation = channel->constellation; */
5577                 /* extAttr->currentChannel.symbolrate    = channel->symbolrate; */
5578                 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5579                 if (status < 0)
5580                         break;
5581
5582                 /* Start processes */
5583                 status = MPEGTSStart(state);
5584                 if (status < 0)
5585                         break;
5586                 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5587                 if (status < 0)
5588                         break;
5589                 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5590                 if (status < 0)
5591                         break;
5592                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5593                 if (status < 0)
5594                         break;
5595
5596                 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5597                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5598                 if (status < 0)
5599                         break;
5600
5601                 /* update global DRXK data container */
5602         /*?     extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5603
5604                 /* All done, all OK */
5605         } while (0);
5606
5607         if (status < 0)
5608                 printk(KERN_ERR "drxk: %s %d\n", __func__, status);
5609
5610         return status;
5611 }
5612
5613 static int SetQAMStandard(struct drxk_state *state,
5614                           enum OperationMode oMode)
5615 {
5616 #ifdef DRXK_QAM_TAPS
5617 #define DRXK_QAMA_TAPS_SELECT
5618 #include "drxk_filters.h"
5619 #undef DRXK_QAMA_TAPS_SELECT
5620 #else
5621         int status;
5622 #endif
5623
5624         dprintk(1, "\n");
5625         do {
5626                 /* added antenna switch */
5627                 SwitchAntennaToQAM(state);
5628
5629                 /* Ensure correct power-up mode */
5630                 status = PowerUpQAM(state);
5631                 if (status < 0)
5632                         break;
5633                 /* Reset QAM block */
5634                 status = QAMResetQAM(state);
5635                 if (status < 0)
5636                         break;
5637
5638                 /* Setup IQM */
5639
5640                 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5641                 if (status < 0)
5642                         break;
5643                 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5644                 if (status < 0)
5645                         break;
5646
5647                 /* Upload IQM Channel Filter settings by
5648                    boot loader from ROM table */
5649                 switch (oMode) {
5650                 case OM_QAM_ITU_A:
5651                         status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5652                         if (status < 0)
5653                                 break;
5654                         break;
5655                 case OM_QAM_ITU_C:
5656                         status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5657                         if (status < 0)
5658                                 break;
5659                         status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5660                         if (status < 0)
5661                                 break;
5662                         break;
5663                 default:
5664                         status = -EINVAL;
5665                 }
5666                 status = status;
5667                 if (status < 0)
5668                         break;
5669
5670                 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5671                 if (status < 0)
5672                         break;
5673                 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5674                 if (status < 0)
5675                         break;
5676                 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5677                 if (status < 0)
5678                         break;
5679
5680                 status = write16(state, IQM_RC_STRETCH__A, 21);
5681                 if (status < 0)
5682                         break;
5683                 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5684                 if (status < 0)
5685                         break;
5686                 status = write16(state, IQM_AF_CLP_TH__A, 448);
5687                 if (status < 0)
5688                         break;
5689                 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5690                 if (status < 0)
5691                         break;
5692                 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5693                 if (status < 0)
5694                         break;
5695
5696                 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5697                 if (status < 0)
5698                         break;
5699                 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5700                 if (status < 0)
5701                         break;
5702                 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5703                 if (status < 0)
5704                         break;
5705                 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5706                 if (status < 0)
5707                         break;
5708
5709                 /* IQM Impulse Noise Processing Unit */
5710                 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5711                 if (status < 0)
5712                         break;
5713                 status = write16(state, IQM_CF_DATATH__A, 1000);
5714                 if (status < 0)
5715                         break;
5716                 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5717                 if (status < 0)
5718                         break;
5719                 status = write16(state, IQM_CF_DET_LCT__A, 0);
5720                 if (status < 0)
5721                         break;
5722                 status = write16(state, IQM_CF_WND_LEN__A, 1);
5723                 if (status < 0)
5724                         break;
5725                 status = write16(state, IQM_CF_PKDTH__A, 1);
5726                 if (status < 0)
5727                         break;
5728                 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5729                 if (status < 0)
5730                         break;
5731
5732                 /* turn on IQMAF. Must be done before setAgc**() */
5733                 status = SetIqmAf(state, true);
5734                 if (status < 0)
5735                         break;
5736                 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5737                 if (status < 0)
5738                         break;
5739
5740                 /* IQM will not be reset from here, sync ADC and update/init AGC */
5741                 status = ADCSynchronization(state);
5742                 if (status < 0)
5743                         break;
5744
5745                 /* Set the FSM step period */
5746                 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5747                 if (status < 0)
5748                         break;
5749
5750                 /* Halt SCU to enable safe non-atomic accesses */
5751                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5752                 if (status < 0)
5753                         break;
5754
5755                 /* No more resets of the IQM, current standard correctly set =>
5756                    now AGCs can be configured. */
5757
5758                 status = InitAGC(state, true);
5759                 if (status < 0)
5760                         break;
5761                 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5762                 if (status < 0)
5763                         break;
5764
5765                 /* Configure AGC's */
5766                 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5767                 if (status < 0)
5768                         break;
5769                 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5770                 if (status < 0)
5771                         break;
5772
5773                 /* Activate SCU to enable SCU commands */
5774                 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5775                 if (status < 0)
5776                         break;
5777         } while (0);
5778         return status;
5779 }
5780
5781 static int WriteGPIO(struct drxk_state *state)
5782 {
5783         int status;
5784         u16 value = 0;
5785
5786         dprintk(1, "\n");
5787         do {
5788                 /* stop lock indicator process */
5789                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5790                 if (status < 0)
5791                         break;
5792
5793                 /*  Write magic word to enable pdr reg write               */
5794                 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5795                 if (status < 0)
5796                         break;
5797
5798                 if (state->m_hasSAWSW) {
5799                         /* write to io pad configuration register - output mode */
5800                         status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5801                         if (status < 0)
5802                                 break;
5803
5804                         /* use corresponding bit in io data output registar */
5805                         status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5806                         if (status < 0)
5807                                 break;
5808                         if (state->m_GPIO == 0)
5809                                 value &= 0x7FFF;        /* write zero to 15th bit - 1st UIO */
5810                         else
5811                                 value |= 0x8000;        /* write one to 15th bit - 1st UIO */
5812                         /* write back to io data output register */
5813                         status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5814                         if (status < 0)
5815                                 break;
5816
5817                 }
5818                 /*  Write magic word to disable pdr reg write               */
5819                 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5820                 if (status < 0)
5821                         break;
5822         } while (0);
5823         return status;
5824 }
5825
5826 static int SwitchAntennaToQAM(struct drxk_state *state)
5827 {
5828         int status = -1;
5829
5830         dprintk(1, "\n");
5831         if (state->m_AntennaSwitchDVBTDVBC != 0) {
5832                 if (state->m_GPIO != state->m_AntennaDVBC) {
5833                         state->m_GPIO = state->m_AntennaDVBC;
5834                         status = WriteGPIO(state);
5835                 }
5836         }
5837         return status;
5838 }
5839
5840 static int SwitchAntennaToDVBT(struct drxk_state *state)
5841 {
5842         int status = -1;
5843
5844         dprintk(1, "\n");
5845         if (state->m_AntennaSwitchDVBTDVBC != 0) {
5846                 if (state->m_GPIO != state->m_AntennaDVBT) {
5847                         state->m_GPIO = state->m_AntennaDVBT;
5848                         status = WriteGPIO(state);
5849                 }
5850         }
5851         return status;
5852 }
5853
5854
5855 static int PowerDownDevice(struct drxk_state *state)
5856 {
5857         /* Power down to requested mode */
5858         /* Backup some register settings */
5859         /* Set pins with possible pull-ups connected to them in input mode */
5860         /* Analog power down */
5861         /* ADC power down */
5862         /* Power down device */
5863         int status;
5864
5865         dprintk(1, "\n");
5866         do {
5867                 if (state->m_bPDownOpenBridge) {
5868                         /* Open I2C bridge before power down of DRXK */
5869                         status = ConfigureI2CBridge(state, true);
5870                         if (status < 0)
5871                                 break;
5872                 }
5873                 /* driver 0.9.0 */
5874                 status = DVBTEnableOFDMTokenRing(state, false);
5875                 if (status < 0)
5876                         break;
5877
5878                 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5879                 if (status < 0)
5880                         break;
5881                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5882                 if (status < 0)
5883                         break;
5884                 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5885                 status = HI_CfgCommand(state);
5886                 if (status < 0)
5887                         break;
5888         } while (0);
5889
5890         if (status < 0)
5891                 return -1;
5892
5893         return 0;
5894 }
5895
5896 static int load_microcode(struct drxk_state *state, char *mc_name)
5897 {
5898         const struct firmware *fw = NULL;
5899         int err = 0;
5900
5901         dprintk(1, "\n");
5902
5903         err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5904         if (err < 0) {
5905                 printk(KERN_ERR
5906                        "drxk: Could not load firmware file %s.\n", mc_name);
5907                 printk(KERN_INFO
5908                        "drxk: Copy %s to your hotplug directory!\n", mc_name);
5909                 return err;
5910         }
5911         err = DownloadMicrocode(state, fw->data, fw->size);
5912         release_firmware(fw);
5913         return err;
5914 }
5915
5916 static int init_drxk(struct drxk_state *state)
5917 {
5918         int status;
5919         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5920         u16 driverVersion;
5921
5922         dprintk(1, "\n");
5923         if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5924                 do {
5925                         status = PowerUpDevice(state);
5926                         if (status < 0)
5927                                 break;
5928                         status = DRXX_Open(state);
5929                         if (status < 0)
5930                                 break;
5931                         /* Soft reset of OFDM-, sys- and osc-clockdomain */
5932                         status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
5933                         if (status < 0)
5934                                 break;
5935                         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5936                         if (status < 0)
5937                                 break;
5938                         /* TODO is this needed, if yes how much delay in worst case scenario */
5939                         msleep(1);
5940                         state->m_DRXK_A3_PATCH_CODE = true;
5941                         status = GetDeviceCapabilities(state);
5942                         if (status < 0)
5943                                 break;
5944
5945                         /* Bridge delay, uses oscilator clock */
5946                         /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
5947                         /* SDA brdige delay */
5948                         state->m_HICfgBridgeDelay =
5949                             (u16) ((state->m_oscClockFreq / 1000) *
5950                                    HI_I2C_BRIDGE_DELAY) / 1000;
5951                         /* Clipping */
5952                         if (state->m_HICfgBridgeDelay >
5953                             SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
5954                                 state->m_HICfgBridgeDelay =
5955                                     SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
5956                         }
5957                         /* SCL bridge delay, same as SDA for now */
5958                         state->m_HICfgBridgeDelay +=
5959                             state->m_HICfgBridgeDelay <<
5960                             SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
5961
5962                         status = InitHI(state);
5963                         if (status < 0)
5964                                 break;
5965                         /* disable various processes */
5966 #if NOA1ROM
5967                         if (!(state->m_DRXK_A1_ROM_CODE)
5968                             && !(state->m_DRXK_A2_ROM_CODE))
5969 #endif
5970                         {
5971                                 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5972                                 if (status < 0)
5973                                         break;
5974                         }
5975
5976                         /* disable MPEG port */
5977                         status = MPEGTSDisable(state);
5978                         if (status < 0)
5979                                 break;
5980
5981                         /* Stop AUD and SCU */
5982                         status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
5983                         if (status < 0)
5984                                 break;
5985                         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
5986                         if (status < 0)
5987                                 break;
5988
5989                         /* enable token-ring bus through OFDM block for possible ucode upload */
5990                         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
5991                         if (status < 0)
5992                                 break;
5993
5994                         /* include boot loader section */
5995                         status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
5996                         if (status < 0)
5997                                 break;
5998                         status = BLChainCmd(state, 0, 6, 100);
5999                         if (status < 0)
6000                                 break;
6001
6002 #if 0
6003                         if (state->m_DRXK_A3_PATCH_CODE)
6004                                 status = DownloadMicrocode(state, DRXK_A3_microcode, DRXK_A3_microcode_length);
6005                                 if (status < 0)
6006                                         break;
6007 #else
6008                         load_microcode(state, "drxk_a3.mc");
6009 #endif
6010 #if NOA1ROM
6011                         if (state->m_DRXK_A2_PATCH_CODE)
6012                                 status = DownloadMicrocode(state, DRXK_A2_microcode, DRXK_A2_microcode_length);
6013                                 if (status < 0)
6014                                         break;
6015 #endif
6016                         /* disable token-ring bus through OFDM block for possible ucode upload */
6017                         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6018                         if (status < 0)
6019                                 break;
6020
6021                         /* Run SCU for a little while to initialize microcode version numbers */
6022                         status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6023                         if (status < 0)
6024                                 break;
6025                         status = DRXX_Open(state);
6026                         if (status < 0)
6027                                 break;
6028                         /* added for test */
6029                         msleep(30);
6030
6031                         powerMode = DRXK_POWER_DOWN_OFDM;
6032                         status = CtrlPowerMode(state, &powerMode);
6033                         if (status < 0)
6034                                 break;
6035
6036                         /* Stamp driver version number in SCU data RAM in BCD code
6037                            Done to enable field application engineers to retreive drxdriver version
6038                            via I2C from SCU RAM.
6039                            Not using SCU command interface for SCU register access since no
6040                            microcode may be present.
6041                          */
6042                         driverVersion =
6043                             (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6044                             (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6045                             ((DRXK_VERSION_MAJOR % 10) << 4) +
6046                             (DRXK_VERSION_MINOR % 10);
6047                         status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6048                         if (status < 0)
6049                                 break;
6050                         driverVersion =
6051                             (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6052                             (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6053                             (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6054                             (DRXK_VERSION_PATCH % 10);
6055                         status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6056                         if (status < 0)
6057                                 break;
6058
6059                         printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6060                                DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6061                                DRXK_VERSION_PATCH);
6062
6063                         /* Dirty fix of default values for ROM/PATCH microcode
6064                            Dirty because this fix makes it impossible to setup suitable values
6065                            before calling DRX_Open. This solution requires changes to RF AGC speed
6066                            to be done via the CTRL function after calling DRX_Open */
6067
6068                         /* m_dvbtRfAgcCfg.speed = 3; */
6069
6070                         /* Reset driver debug flags to 0 */
6071                         status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6072                         if (status < 0)
6073                                 break;
6074                         /* driver 0.9.0 */
6075                         /* Setup FEC OC:
6076                            NOTE: No more full FEC resets allowed afterwards!! */
6077                         status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6078                         if (status < 0)
6079                                 break;
6080                         /* MPEGTS functions are still the same */
6081                         status = MPEGTSDtoInit(state);
6082                         if (status < 0)
6083                                 break;
6084                         status = MPEGTSStop(state);
6085                         if (status < 0)
6086                                 break;
6087                         status = MPEGTSConfigurePolarity(state);
6088                         if (status < 0)
6089                                 break;
6090                         status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6091                         if (status < 0)
6092                                 break;
6093                         /* added: configure GPIO */
6094                         status = WriteGPIO(state);
6095                         if (status < 0)
6096                                 break;
6097
6098                         state->m_DrxkState = DRXK_STOPPED;
6099
6100                         if (state->m_bPowerDown) {
6101                                 status = PowerDownDevice(state);
6102                                 if (status < 0)
6103                                         break;
6104                                 state->m_DrxkState = DRXK_POWERED_DOWN;
6105                         } else
6106                                 state->m_DrxkState = DRXK_STOPPED;
6107                 } while (0);
6108         }
6109
6110         return 0;
6111 }
6112
6113 static void drxk_c_release(struct dvb_frontend *fe)
6114 {
6115         struct drxk_state *state = fe->demodulator_priv;
6116
6117         dprintk(1, "\n");
6118         kfree(state);
6119 }
6120
6121 static int drxk_c_init(struct dvb_frontend *fe)
6122 {
6123         struct drxk_state *state = fe->demodulator_priv;
6124
6125         dprintk(1, "\n");
6126         if (mutex_trylock(&state->ctlock) == 0)
6127                 return -EBUSY;
6128         SetOperationMode(state, OM_QAM_ITU_A);
6129         return 0;
6130 }
6131
6132 static int drxk_c_sleep(struct dvb_frontend *fe)
6133 {
6134         struct drxk_state *state = fe->demodulator_priv;
6135
6136         dprintk(1, "\n");
6137         ShutDown(state);
6138         mutex_unlock(&state->ctlock);
6139         return 0;
6140 }
6141
6142 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6143 {
6144         struct drxk_state *state = fe->demodulator_priv;
6145
6146         dprintk(1, "%s\n", enable ? "enable" : "disable");
6147         return ConfigureI2CBridge(state, enable ? true : false);
6148 }
6149
6150 static int drxk_set_parameters(struct dvb_frontend *fe,
6151                                struct dvb_frontend_parameters *p)
6152 {
6153         struct drxk_state *state = fe->demodulator_priv;
6154         u32 IF;
6155
6156         dprintk(1, "\n");
6157         if (fe->ops.i2c_gate_ctrl)
6158                 fe->ops.i2c_gate_ctrl(fe, 1);
6159         if (fe->ops.tuner_ops.set_params)
6160                 fe->ops.tuner_ops.set_params(fe, p);
6161         if (fe->ops.i2c_gate_ctrl)
6162                 fe->ops.i2c_gate_ctrl(fe, 0);
6163         state->param = *p;
6164         fe->ops.tuner_ops.get_frequency(fe, &IF);
6165         Start(state, 0, IF);
6166
6167         /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6168
6169         return 0;
6170 }
6171
6172 static int drxk_c_get_frontend(struct dvb_frontend *fe,
6173                                struct dvb_frontend_parameters *p)
6174 {
6175         dprintk(1, "\n");
6176         return 0;
6177 }
6178
6179 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6180 {
6181         struct drxk_state *state = fe->demodulator_priv;
6182         u32 stat;
6183
6184         dprintk(1, "\n");
6185         *status = 0;
6186         GetLockStatus(state, &stat, 0);
6187         if (stat == MPEG_LOCK)
6188                 *status |= 0x1f;
6189         if (stat == FEC_LOCK)
6190                 *status |= 0x0f;
6191         if (stat == DEMOD_LOCK)
6192                 *status |= 0x07;
6193         return 0;
6194 }
6195
6196 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6197 {
6198         dprintk(1, "\n");
6199
6200         *ber = 0;
6201         return 0;
6202 }
6203
6204 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6205                                      u16 *strength)
6206 {
6207         struct drxk_state *state = fe->demodulator_priv;
6208         u32 val;
6209
6210         dprintk(1, "\n");
6211         ReadIFAgc(state, &val);
6212         *strength = val & 0xffff;
6213         return 0;
6214 }
6215
6216 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6217 {
6218         struct drxk_state *state = fe->demodulator_priv;
6219         s32 snr2;
6220
6221         dprintk(1, "\n");
6222         GetSignalToNoise(state, &snr2);
6223         *snr = snr2 & 0xffff;
6224         return 0;
6225 }
6226
6227 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6228 {
6229         struct drxk_state *state = fe->demodulator_priv;
6230         u16 err;
6231
6232         dprintk(1, "\n");
6233         DVBTQAMGetAccPktErr(state, &err);
6234         *ucblocks = (u32) err;
6235         return 0;
6236 }
6237
6238 static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6239                                     *sets)
6240 {
6241         dprintk(1, "\n");
6242         sets->min_delay_ms = 3000;
6243         sets->max_drift = 0;
6244         sets->step_size = 0;
6245         return 0;
6246 }
6247
6248 static void drxk_t_release(struct dvb_frontend *fe)
6249 {
6250 #if 0
6251         struct drxk_state *state = fe->demodulator_priv;
6252
6253         dprintk(1, "\n");
6254         kfree(state);
6255 #endif
6256 }
6257
6258 static int drxk_t_init(struct dvb_frontend *fe)
6259 {
6260         struct drxk_state *state = fe->demodulator_priv;
6261
6262         dprintk(1, "\n");
6263         if (mutex_trylock(&state->ctlock) == 0)
6264                 return -EBUSY;
6265         SetOperationMode(state, OM_DVBT);
6266         return 0;
6267 }
6268
6269 static int drxk_t_sleep(struct dvb_frontend *fe)
6270 {
6271         struct drxk_state *state = fe->demodulator_priv;
6272
6273         dprintk(1, "\n");
6274         mutex_unlock(&state->ctlock);
6275         return 0;
6276 }
6277
6278 static int drxk_t_get_frontend(struct dvb_frontend *fe,
6279                                struct dvb_frontend_parameters *p)
6280 {
6281         dprintk(1, "\n");
6282
6283         return 0;
6284 }
6285
6286 static struct dvb_frontend_ops drxk_c_ops = {
6287         .info = {
6288                  .name = "DRXK DVB-C",
6289                  .type = FE_QAM,
6290                  .frequency_stepsize = 62500,
6291                  .frequency_min = 47000000,
6292                  .frequency_max = 862000000,
6293                  .symbol_rate_min = 870000,
6294                  .symbol_rate_max = 11700000,
6295                  .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6296                  FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO},
6297         .release = drxk_c_release,
6298         .init = drxk_c_init,
6299         .sleep = drxk_c_sleep,
6300         .i2c_gate_ctrl = drxk_gate_ctrl,
6301
6302         .set_frontend = drxk_set_parameters,
6303         .get_frontend = drxk_c_get_frontend,
6304         .get_tune_settings = drxk_c_get_tune_settings,
6305
6306         .read_status = drxk_read_status,
6307         .read_ber = drxk_read_ber,
6308         .read_signal_strength = drxk_read_signal_strength,
6309         .read_snr = drxk_read_snr,
6310         .read_ucblocks = drxk_read_ucblocks,
6311 };
6312
6313 static struct dvb_frontend_ops drxk_t_ops = {
6314         .info = {
6315                  .name = "DRXK DVB-T",
6316                  .type = FE_OFDM,
6317                  .frequency_min = 47125000,
6318                  .frequency_max = 865000000,
6319                  .frequency_stepsize = 166667,
6320                  .frequency_tolerance = 0,
6321                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
6322                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
6323                  FE_CAN_FEC_AUTO |
6324                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
6325                  FE_CAN_QAM_AUTO |
6326                  FE_CAN_TRANSMISSION_MODE_AUTO |
6327                  FE_CAN_GUARD_INTERVAL_AUTO |
6328                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
6329         .release = drxk_t_release,
6330         .init = drxk_t_init,
6331         .sleep = drxk_t_sleep,
6332         .i2c_gate_ctrl = drxk_gate_ctrl,
6333
6334         .set_frontend = drxk_set_parameters,
6335         .get_frontend = drxk_t_get_frontend,
6336
6337         .read_status = drxk_read_status,
6338         .read_ber = drxk_read_ber,
6339         .read_signal_strength = drxk_read_signal_strength,
6340         .read_snr = drxk_read_snr,
6341         .read_ucblocks = drxk_read_ucblocks,
6342 };
6343
6344 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6345                                  struct i2c_adapter *i2c,
6346                                  struct dvb_frontend **fe_t)
6347 {
6348         struct drxk_state *state = NULL;
6349         u8 adr = config->adr;
6350
6351         dprintk(1, "\n");
6352         state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6353         if (!state)
6354                 return NULL;
6355
6356         state->i2c = i2c;
6357         state->demod_address = adr;
6358
6359         mutex_init(&state->mutex);
6360         mutex_init(&state->ctlock);
6361
6362         memcpy(&state->c_frontend.ops, &drxk_c_ops,
6363                sizeof(struct dvb_frontend_ops));
6364         memcpy(&state->t_frontend.ops, &drxk_t_ops,
6365                sizeof(struct dvb_frontend_ops));
6366         state->c_frontend.demodulator_priv = state;
6367         state->t_frontend.demodulator_priv = state;
6368
6369         init_state(state);
6370         if (init_drxk(state) < 0)
6371                 goto error;
6372         *fe_t = &state->t_frontend;
6373         return &state->c_frontend;
6374
6375 error:
6376         printk(KERN_ERR "drxk: not found\n");
6377         kfree(state);
6378         return NULL;
6379 }
6380 EXPORT_SYMBOL(drxk_attach);
6381
6382 MODULE_DESCRIPTION("DRX-K driver");
6383 MODULE_AUTHOR("Ralph Metzler");
6384 MODULE_LICENSE("GPL");